#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I62935 # Thu Mar 25 18:21:43 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Hex_to_ascii.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\acmtable.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\instructnvm_bb.v" (library work) @I:"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\instructnvm_bb.v":"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\support.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\iram512x9_rtl.v" (library work) @N:CG334 : iram512x9_rtl.v(57) | Read directive translate_off. @N:CG333 : iram512x9_rtl.v(65) | Read directive translate_on. @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\instructram.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\debugblk.v" (library work) @N:CG334 : debugblk.v(68) | Read directive translate_off. @N:CG333 : debugblk.v(745) | Read directive translate_on. @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\instructions.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x8_rtl.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ramblocks.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v" (library work) @N:CG334 : coreabc.v(992) | Read directive translate_off. @N:CG333 : coreabc.v(994) | Read directive translate_on. @N:CG334 : coreabc.v(1389) | Read directive translate_off. @N:CG333 : coreabc.v(1433) | Read directive translate_on. @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Clock_gen.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\fifo_256x8.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUART.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUARTapb.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\UART_top.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Count28.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\CCC_0\my_hpms_CCC_0_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_HPMS\my_hpms_HPMS_syn.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_HPMS\my_hpms_HPMS.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\my_hpms.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_top\my_hpms_top.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v" (library CORESYSSERVICES_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v" (library CORESYSSERVICES_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v" (library CORESYSSERVICES_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v" (library CORESYSSERVICES_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v" (library CORESYSSERVICES_LIB) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\syssvc_blk.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module top @N:CG364 : Count28.v(3) | Synthesizing module counter28 in library work. Running optimization stage 1 on counter28 ....... @N:CG775 : coreahblite.v(23) | Component CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB @N:CG364 : igloo2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : igloo2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @N:CG364 : igloo2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... @N:CG364 : my_hpms_CCC_0_FCCC.v(5) | Synthesizing module my_hpms_CCC_0_FCCC in library work. Running optimization stage 1 on my_hpms_CCC_0_FCCC ....... @W:CG1283 : coreahblite.v(541) | Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(541) | Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(541) | Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(541) | Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_matrix4x16.v(2639) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z1 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z1 ....... @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 Running optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @W:CG1283 : coreahblite_matrix4x16.v(2703) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_matrix4x16.v(2767) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z2 ....... @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @W:CG1283 : coreahblite_matrix4x16.v(2831) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z3 Running optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z3 ....... @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 Running optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b10000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_65536_0_0_0s Running optimization stage 1 on COREAHBLITE_MATRIX4X16_1_1_85_65536_65536_0_0_0s ....... @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite in library COREAHBLITE_LIB. FAMILY=6'b011000 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b1 SC_1=1'b0 SC_2=1'b1 SC_3=1'b0 SC_4=1'b1 SC_5=1'b0 SC_6=1'b1 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b1 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b1 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b10000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000001010101 Generated name = CoreAHBLite_Z4 Running optimization stage 1 on CoreAHBLite_Z4 ....... @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z5 Running optimization stage 1 on CoreResetP_Z5 ....... @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... @N:CG364 : my_hpms_FABOSC_0_OSC.v(5) | Synthesizing module my_hpms_FABOSC_0_OSC in library work. Running optimization stage 1 on my_hpms_FABOSC_0_OSC ....... @W:CL318 : my_hpms_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : my_hpms_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : my_hpms_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : my_hpms_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : my_hpms_HPMS_syn.v(5) | Synthesizing module MSS_010 in library work. Running optimization stage 1 on MSS_010 ....... @N:CG364 : my_hpms_HPMS.v(9) | Synthesizing module my_hpms_HPMS in library work. Running optimization stage 1 on my_hpms_HPMS ....... @N:CG364 : igloo2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... @N:CG364 : my_hpms.v(9) | Synthesizing module my_hpms in library work. Running optimization stage 1 on my_hpms ....... @N:CG364 : my_hpms_top.v(9) | Synthesizing module my_hpms_top in library work. Running optimization stage 1 on my_hpms_top ....... @N:CG775 : CoreSysServices.v(30) | Component syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES not found in library "work" or "__hyper__lib__", but found in library CORESYSSERVICES_LIB @N:CG364 : CoreSysServices_UserIF.v(30) | Synthesizing module CoreSysServices_UserIF in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000001 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000001 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000001000000000000 NRBGPERSTRINGPTR=32'b00100000000000000010000000000000 NRBGGENPTR=32'b00100000000000000011000000000000 NRBGREQDATAPTR=32'b00100000000000000100000000000000 NRBGRESEEDPTR=32'b00100000000000000101000000000000 NRBGADDINPPTR=32'b00100000000000000110000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000001 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = CoreSysServices_UserIF_Z6 Running optimization stage 1 on CoreSysServices_UserIF_Z6 ....... @W:CL169 : CoreSysServices_UserIF.v(789) | Pruning unused register cuhprior_flushdone_d3. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(738) | Pruning unused register pord_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(738) | Pruning unused register pord_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(592) | Pruning unused register custatus_out_en_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(522) | Pruning unused register pord_comb_d1. Make sure that there are no unused intermediate registers. @W:CL207 : CoreSysServices_UserIF.v(719) | All reachable assignments to pord assign 0, register removed by optimization. @W:CL190 : CoreSysServices_UserIF.v(505) | Optimizing register bit hprior_kp_busy_high to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 5 to 2 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_UserIF.v(653) | Pruning register bit 0 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 7 to 5 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_UserIF.v(653) | Pruning register bit 3 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 1 to 0 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL169 : CoreSysServices_UserIF.v(505) | Pruning unused register hprior_kp_busy_high. Make sure that there are no unused intermediate registers. @N:CG364 : igloo2.v(837) | Synthesizing module FLASH_FREEZE in library work. Running optimization stage 1 on FLASH_FREEZE ....... @N:CG364 : CoreSysServices_CmdDec.v(30) | Synthesizing module CoreSysServices_CmdDec in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000001 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000001 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000001000000000000 NRBGPERSTRINGPTR=32'b00100000000000000010000000000000 NRBGGENPTR=32'b00100000000000000011000000000000 NRBGREQDATAPTR=32'b00100000000000000100000000000000 NRBGRESEEDPTR=32'b00100000000000000101000000000000 NRBGADDINPPTR=32'b00100000000000000110000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000001 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 C_IDLE=2'b00 C_REQ_PHASE=2'b01 C_RESP_PHASE=2'b10 REQ_IDLE=6'b000000 REQ_WAIT_MEMWR1=6'b000001 REQ_MEMWR_DESC=6'b000010 REQ_WAIT_MEMWR2=6'b000011 REQ_MEMWR_DATA=6'b000100 REQ_PHASE=6'b000101 REQ_FIIC_INT=6'b000111 REQ_POLL_CINT1=6'b001000 REQ_RDCOMM_STATUS1=6'b001001 REQ_WRCOMM_CTRL=6'b001010 REQ_WRCOMM_INT=6'b001011 REQ_WRCOMM_FRM=6'b001100 REQ_WRCOMM_DATA=6'b001101 REQ_POLL_CINT2=6'b001110 REQ_RDCOMM_STATUS2=6'b001111 REQ_WAIT_REG1=6'b010000 REQ_WAIT_REG2=6'b010001 REQ_WAIT_REG3=6'b010010 REQ_WAIT_REG4=6'b010011 REQ_WAIT_REG5=6'b010100 REQ_WAIT_REG6=6'b010101 REQ_WAIT_REG7=6'b010110 REQ_WAIT_REG8=6'b010111 REQ_WAIT_REG9=6'b011000 REQ_RD_INT=6'b011011 REQ_RDCOMM_INT=6'b011100 REQ_WAIT_REG10=6'b100001 REQ_WAIT_REG11=6'b100010 REQ_WAIT_REG12=6'b100011 REQ_WAIT_REG13=6'b100100 REQ_WRCOMM_CTRL2=6'b100101 REQ_WRCOMM_CTRL3=6'b100110 REQ_WRCOMM_CTRL4=6'b100111 REQ_WRCOMM_INT2=6'b101000 REQ_WAIT_MEMWR22=6'b101001 REQ_MEMWR_DATA1=6'b101010 REQ_WAIT_ASYNCRD1=6'b101011 REQ_RDCOMM_ASYNCFRM1=6'b101100 REQ_WAIT_ASYNCRD2=6'b101101 REQ_RDCOMM_ASYNCFRM2=6'b101110 REQ_ASYNC_OUT1=6'b110000 REQ_ASYNC_OUT2=6'b110001 REQ_WAIT_REG14=6'b110010 REQ_WRCOMM_DESC2=6'b110011 REQ_WAIT_REG15=6'b110100 RESP_IDLE=6'b000000 RESP_PHASE=6'b000001 RESP_RDCOMM_STATUS=6'b000011 RESP_RDCOMM_FRM=6'b000100 RESP_RDCOMM_DESC=6'b000101 RESP_RDCOMM_DATA=6'b000110 RESP_WAIT_MEMRD=6'b000111 RESP_MEMRD=6'b001000 RESP_POLL_CINT1=6'b001001 RESP_POLL_CINT4=6'b001100 RESP_REG1=6'b001101 RESP_REG4=6'b010000 RESP_REG5=6'b010001 RESP_REG6=6'b010010 RESP_REG7=6'b010011 RESP_REG8=6'b010100 RESP_REG9=6'b010101 RESP_WRCOMM_CTRL1=6'b010110 RESP_WAIT_REG11=6'b010111 RESP_WRCOMM_CTRL2=6'b011000 RESP_WAIT_REG12=6'b011001 RESP_RDCOMM_STATUS3=6'b011011 RESP_WRCOMM_INT3=6'b100100 RESP_WAIT_REG13=6'b100101 RESP_FIIC_INT=6'b100110 RESP_WAIT_REG14=6'b100111 RESP_WAIT_ASYNCRD1=6'b101000 RESP_RDCOMM_ASYNCFRM1=6'b101001 RESP_ASYNC_OUT1=6'b101100 RESP_WAIT_ASYNCRD3=6'b101110 RESP_RDCOMM_ASYNCFRM3=6'b101111 RESP_ASYNC_OUT3=6'b110000 ASYNCEVENT_POLL_IDLE=4'b0000 ASYNCEVENT_POLL_WAIT=4'b0001 ASYNCEVENT_POLL_CINT=4'b0010 ASYNCEVENT_REG1=4'b0011 ASYNCEVENT_RDCOMM_STATUS=4'b0100 ASYNCEVENT_WAIT_RD1=4'b0101 ASYNCEVENT_RDCOMM_FRM1=4'b0110 ASYNCEVENT_RDCOMM_OUT1=4'b0111 ASYNCEVENT_WAIT=4'b1000 ASYNCEVENT_PHASE=4'b1001 ASYNCEVENT_WAIT_REG11=4'b1010 ASYNCEVENT_WRCOMM_CTRL1=4'b1011 ASYNCEVENT_WAIT_REG13=4'b1100 ASYNCEVENT_FIIC_INT=4'b1101 ASYNCEVENT_WAIT_REG14=4'b1110 ASYNCEVENT_WRCOMM_INT3=4'b1111 COMM_CTRL_REG=32'b01000000000000010110000000000000 COMM_STATUS_REG=32'b01000000000000010110000000000100 COMM_INTEN_REG=32'b01000000000000010110000000001000 COMM_DATA8_REG=32'b01000000000000010110000000010000 COMM_DATA32_REG=32'b01000000000000010110000000010100 COMM_FRM8_REG=32'b01000000000000010110000000011000 COMM_FRM32_REG=32'b01000000000000010110000000011100 Generated name = CoreSysServices_CmdDec_Z7 @N:CG179 : CoreSysServices_CmdDec.v(1912) | Removing redundant assignment. @W:CG133 : CoreSysServices_CmdDec.v(418) | Object cfwr_req_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(436) | Object cfsrc_addr_int is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(437) | Object cfdst_addr_int is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(447) | Object memwr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(470) | Object req_srcreg_addr is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(472) | Object req_srcreg_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(512) | Object cuhprior_flushdone_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : CoreSysServices_CmdDec.v(555) | Removing wire cfwr_req_int, as there is no assignment to it. @W:CG360 : CoreSysServices_CmdDec.v(557) | Removing wire cfwr_req_c, as there is no assignment to it. @W:CG360 : CoreSysServices_CmdDec.v(563) | Removing wire cfdata_w_o, as there is no assignment to it. Running optimization stage 1 on CoreSysServices_CmdDec_Z7 ....... @W:CL318 : CoreSysServices_CmdDec.v(372) | *Output cutrans_done_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL168 : CoreSysServices_CmdDec.v(2927) | Removing instance FLASH_FREEZE_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL169 : CoreSysServices_CmdDec.v(2980) | Pruning unused register FF_exit. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2962) | Pruning unused register FF_exit_led. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2949) | Pruning unused register FF_entry_led. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2939) | Pruning unused register FF_entry. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2889) | Pruning unused register cunvm_bfr_iapverify_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2770) | Pruning unused register latchen_hrdata_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register fiicreg_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register commctrlreg_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register commpoll_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1924) | Pruning unused register set_puf_getkcnum_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1906) | Pruning unused register wait_count[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1731) | Pruning unused register fctrans_done_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1611) | Pruning unused register pord_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1611) | Pruning unused register pord_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1582) | Pruning unused register req_phase_active_pulse. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1532) | Pruning unused register resp_data_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1532) | Pruning unused register req_phase_active_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1033) | Pruning unused register resp_desc_done. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1033) | Pruning unused register resp_frm_done. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1015) | Pruning unused register req_desc_done. Make sure that there are no unused intermediate registers. @W:CL271 : CoreSysServices_CmdDec.v(1924) | Pruning unused bits 31 to 8 of fcdataout_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL113 : CoreSysServices_CmdDec.v(2811) | Feedback mux created for signal cutamper_msg[7:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL207 : CoreSysServices_CmdDec.v(2786) | All reachable assignments to cutamper_msg_valid assign 0, register removed by optimization. @W:CL177 : CoreSysServices_CmdDec.v(2461) | Sharing sequential element fcpop_d1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element tamper_fail_valid_r. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element tamper_detect_valid_r. Add a syn_preserve attribute to the element to prevent sharing. @W:CL207 : CoreSysServices_CmdDec.v(1594) | All reachable assignments to pord assign 0, register removed by optimization. @W:CL250 : CoreSysServices_CmdDec.v(2811) | All reachable assignments to cutamper_msg[7:0] assign 0, register removed by optimization @W:CL190 : CoreSysServices_CmdDec.v(1944) | Optimizing register bit cutamper_detect_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1944) | Optimizing register bit cutamper_fail_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 31 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 29 to 17 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 15 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 12 to 5 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 1 to 0 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 31 to 30 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 28 to 8 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 6 to 5 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 2 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 0 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL169 : CoreSysServices_CmdDec.v(1944) | Pruning unused register cutamper_detect_valid. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1944) | Pruning unused register cutamper_fail_valid. Make sure that there are no unused intermediate registers. @N:CG364 : CoreSysServices_FSMCtrl.v(30) | Synthesizing module CoreSysServices_FSMCtrl in library CORESYSSERVICES_LIB. @W:CG133 : CoreSysServices_FSMCtrl.v(236) | Object rvalid_out_en_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_FSMCtrl.v(237) | Object rvalid_out_en_d2 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : CoreSysServices_FSMCtrl.v(245) | Removing wire fmhaddr_lat, as there is no assignment to it. Running optimization stage 1 on CoreSysServices_FSMCtrl ....... @W:CL169 : CoreSysServices_FSMCtrl.v(952) | Pruning unused register busreq_prev. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(934) | Pruning unused register pop_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(868) | Pruning unused register fmhtrans_int2[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(732) | Pruning unused register haddr_prev[29:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(709) | Pruning unused register latch_addr_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(709) | Pruning unused register latch_addr_d3. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(639) | Pruning unused register latch_addr_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(627) | Pruning unused register state_prev_clk[3:0]. Make sure that there are no unused intermediate registers. @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_FSMCtrl.v(853) | Optimizing register bit fmhtrans_int[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CoreSysServices_FSMCtrl.v(853) | Pruning register bit 0 of fmhtrans_int[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_FSMCtrl.v(293) | Pruning register bits 2 to 1 of fmhburst_d1[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : CoreSysServices_AHBLMasterIF.v(30) | Synthesizing module CoreSysServices_AHBLMasterIF in library CORESYSSERVICES_LIB. Running optimization stage 1 on CoreSysServices_AHBLMasterIF ....... @N:CG364 : CoreSysServices.v(30) | Synthesizing module syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000001 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000001 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000001000000000000 NRBGPERSTRINGPTR=32'b00100000000000000010000000000000 NRBGGENPTR=32'b00100000000000000011000000000000 NRBGREQDATAPTR=32'b00100000000000000100000000000000 NRBGRESEEDPTR=32'b00100000000000000101000000000000 NRBGADDINPPTR=32'b00100000000000000110000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000001 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z8 @W:CG360 : CoreSysServices.v(259) | Removing wire cfburst_len_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(265) | Removing wire ustatus_resp_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(266) | Removing wire ubusy_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(267) | Removing wire udata_en_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(268) | Removing wire udata_valid_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(269) | Removing wire udata_r_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(275) | Removing wire uclatchpord_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(281) | Removing wire uccrypto_opmode_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(304) | Removing wire cudata_wen_o, as there is no assignment to it. Running optimization stage 1 on syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z8 ....... @N:CG364 : Sysservice_state.v(5) | Synthesizing module my_sysservice_state in library work. Running optimization stage 1 on my_sysservice_state ....... @W:CL113 : Sysservice_state.v(60) | Feedback mux created for signal DSN_VALUE[95:95]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL250 : Sysservice_state.v(60) | All reachable assignments to DSN_VALUE[95] assign 0, register removed by optimization @W:CL190 : Sysservice_state.v(60) | Optimizing register bit SERV_OPTIONS_MODE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : Sysservice_state.v(60) | Optimizing register bit SERV_OPTIONS_MODE[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : Sysservice_state.v(60) | Pruning register bit 2 of SERV_OPTIONS_MODE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : Sysservice_state.v(60) | Pruning register bit 0 of SERV_OPTIONS_MODE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : syssvc_blk.v(9) | Synthesizing module syssvc_blk in library work. Running optimization stage 1 on syssvc_blk ....... @N:CG775 : coreapb3.v(13) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : Hex_to_ascii.v(20) | Synthesizing module Nibble2Ascii in library work. Running optimization stage 1 on Nibble2Ascii ....... @N:CG364 : Hex_to_ascii.v(2) | Synthesizing module Binary2Ascii in library work. Running optimization stage 1 on Binary2Ascii ....... @N:CG364 : APB_register_blk.v(2) | Synthesizing module APB_register_blk in library work. Running optimization stage 1 on APB_register_blk ....... @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : APB_register_blk.v(76) | Optimizing register bit PRDATA[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : APB_register_blk.v(76) | Pruning register bits 31 to 16 of PRDATA[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : coreabc.v(46) | Synthesizing module UART_top_COREABC_0_COREABC in library work. FAMILY=32'b00000000000000000000000000011000 APB_AWIDTH=32'b00000000000000000000000000010000 APB_DWIDTH=32'b00000000000000000000000000100000 APB_SDEPTH=32'b00000000000000000000000000010000 ICWIDTH=32'b00000000000000000000000000001011 ZRWIDTH=32'b00000000000000000000000000000000 IFWIDTH=32'b00000000000000000000000000000100 IIWIDTH=32'b00000000000000000000000000000100 IOWIDTH=32'b00000000000000000000000000000001 STWIDTH=32'b00000000000000000000000000001000 EN_RAM=32'b00000000000000000000000000000001 EN_RAM_ECC=32'b00000000000000000000000000000000 EN_AND=32'b00000000000000000000000000000001 EN_XOR=32'b00000000000000000000000000000001 EN_OR=32'b00000000000000000000000000000001 EN_ADD=32'b00000000000000000000000000000001 EN_INC=32'b00000000000000000000000000000001 EN_SHL=32'b00000000000000000000000000000001 EN_SHR=32'b00000000000000000000000000000001 EN_CALL=32'b00000000000000000000000000000001 EN_PUSH=32'b00000000000000000000000000000001 EN_MULT=32'b00000000000000000000000000000000 EN_ACM=32'b00000000000000000000000000000000 EN_DATAM=32'b00000000000000000000000000000010 EN_INT=32'b00000000000000000000000000000000 EN_IOREAD=32'b00000000000000000000000000000001 EN_IOWRT=32'b00000000000000000000000000000001 EN_ALURAM=32'b00000000000000000000000000000000 EN_INDIRECT=32'b00000000000000000000000000000000 ISRADDR=32'b00000000000000000000000000000001 DEBUG=32'b00000000000000000000000000000001 INSMODE=32'b00000000000000000000000000000000 INITWIDTH=32'b00000000000000000000000000001011 TESTMODE=32'b00000000000000000000000000000000 ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001 IMEM_APB_ACCESS=32'b00000000000000000000000000000000 UNIQ_STRING_LENGTH=32'b00000000000000000000000000010010 MAX_NVMDWIDTH=32'b00000000000000000000000000100000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 IRWIDTH=32'b00000000000000000000000000100000 ICDEPTH=32'b00000000000000000000100000000000 APB_SWIDTH=32'b00000000000000000000000000000100 RAMWIDTH=32'b00000000000000000000000000111010 SYNC_RESET=32'b00000000000000000000000000000000 ZRWIDTH_ZR=32'b00000000000000000000000000000001 CYCLE0=2'b00 CYCLE1=2'b01 CYCLE2=2'b10 CYCLE3=2'b11 Generated name = UART_top_COREABC_0_COREABC_Z9 @N:CG364 : ramblocks.v(25) | Synthesizing module UART_top_COREABC_0_RAMBLOCKS in library work. EN_RAM_ECC=32'b00000000000000000000000000000000 DWIDTH=32'b00000000000000000000000000100000 FAMILY=32'b00000000000000000000000000011000 Generated name = UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s @N:CG364 : ram256x16_rtl.v(20) | Synthesizing module UART_top_COREABC_0_RAM256X16 in library work. Running optimization stage 1 on UART_top_COREABC_0_RAM256X16 ....... @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[0][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[1][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[2][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[3][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[4][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[5][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[6][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[7][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[8][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[9][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[10][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[11][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[12][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[13][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[14][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[15][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[16][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[17][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[18][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[19][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[20][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[21][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[22][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[23][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[24][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[25][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[26][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[27][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[28][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[29][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[30][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[31][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[32][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[33][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[34][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[35][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[36][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[37][15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ram256x16_rtl.v(32) | Pruning unused register RAM[38][15:0]. Make sure that there are no unused intermediate registers. Only the first 100 messages of id 'CL169' are reported. To see all messages use 'report_messages -log C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\synlog\top_compiler.srr -id CL169' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL169} -count unlimited' in the Tcl shell. @N:CL134 : ram256x16_rtl.v(32) | Found RAM RAM, depth=256, width=16 @W:CG360 : ramblocks.v(43) | Removing wire RDW, as there is no assignment to it. @W:CG360 : ramblocks.v(49) | Removing wire RDYY, as there is no assignment to it. Running optimization stage 1 on UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s ....... @W:CL318 : ramblocks.v(40) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : ramblocks.v(41) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : instructions.v(26) | Synthesizing module UART_top_COREABC_0_INSTRUCTIONS in library work. AWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 SWIDTH=32'b00000000000000000000000000000100 ICWIDTH=32'b00000000000000000000000000001011 IIWIDTH=32'b00000000000000000000000000000100 IFWIDTH=32'b00000000000000000000000000000100 IWWIDTH=32'b00000000000000000000000000111010 EN_MULT=32'b00000000000000000000000000000000 EN_INC=32'b00000000000000000000000000000001 TESTMODE=32'b00000000000000000000000000000000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 AW=32'b00000000000000000000000000010000 DW=32'b00000000000000000000000000100000 SW=32'b00000000000000000000000000000100 IW=32'b00000000000000000000000000001011 FW=32'b00000000000000000000000000001000 iJUMP=32'b00000000000000000010001000000100 iCALL=32'b00000000000000000010001100000100 iRETURN=32'b00000000000000000010010000000100 iRETISR=32'b00000000000000000010010100000100 iWAIT=32'b00000000000000000010011000000100 iHALT=32'b00000000000000000010011000000100 iINC=32'b00000000000000000000001100000000 iACM_CTRLSTAT=8'b00000000 iACM_ADDR_ADDR=8'b00000100 iACM_DATA_ADDR=8'b00001000 iADC_CTRL2_HI_ADDR=8'b00010000 iADC_STAT_HI_ADDR=8'b00100000 Label_WelcomeMessage=32'b00000000000000000000000000000000 Label_UARTINPUT=32'b00000000000000000000000010100000 Label_Pattern1=32'b00000000000000000000000010101010 Label_Pattern2=32'b00000000000000000000000110100111 Label_Pattern3=32'b00000000000000000000000111110011 Generated name = UART_top_COREABC_0_INSTRUCTIONS_Z10 Running optimization stage 1 on UART_top_COREABC_0_INSTRUCTIONS_Z10 ....... @W:CG133 : coreabc.v(696) | Object MULT is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(697) | Object A is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(698) | Object B is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(1358) | Object b is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : coreabc.v(234) | Removing wire DEBUG1, as there is no assignment to it. @W:CG360 : coreabc.v(235) | Removing wire DEBUG2, as there is no assignment to it. @W:CG360 : coreabc.v(236) | Removing wire DEBUGBLK_RESETN, as there is no assignment to it. @W:CG133 : coreabc.v(262) | Object iii is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(263) | Object RAMDOUTXX is declared but not assigned. Either assign a value or remove the declaration. @W:CG134 : coreabc.v(267) | No assignment to bit 11 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 12 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 13 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 14 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 15 of ins_addr Running optimization stage 1 on UART_top_COREABC_0_COREABC_Z9 ....... @W:CL207 : coreabc.v(1041) | All reachable assignments to ISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(1041) | All reachable assignments to DOISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(818) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization. @W:CL207 : coreabc.v(818) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization. @N:CL189 : coreabc.v(494) | Register bit UROM.INSTR_SLOT[4] is always 0. @W:CL260 : coreabc.v(494) | Pruning register bit 4 of UROM.INSTR_SLOT[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3II in library COREAPB3_LIB. Running optimization stage 1 on CAPB3II ....... @N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000010001 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b1 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010100 UPR_NIBBLE_POSN=4'b1000 FAMILY=32'b00000000000000000000000000011000 SYNC_RESET=32'b00000000000000000000000000000000 CAPB3OOl=32'b00000000000000000000000000000000 CAPB3IOl=32'b00000000000000000000000000000001 CAPB3lOl=32'b00000000000000000000000000000010 CAPB3OIl=32'b00000000000000000000000000000011 CAPB3IIl=32'b00000000000000000000000000000100 CAPB3lIl=32'b00000000000000000000000000000101 CAPB3Oll=32'b00000000000000000000000000000110 CAPB3Ill=32'b00000000000000000000000000000111 CAPB3lll=32'b00000000000000000000000000001000 CAPB3O0l=32'b00000000000000000000000000001001 CAPB3I0l=32'b00000000000000000000000000001010 CAPB3l0l=32'b00000000000000000000000000001011 CAPB3O1l=32'b00000000000000000000000000001100 CAPB3I1l=32'b00000000000000000000000000001101 CAPB3l1l=32'b00000000000000000000000000001110 CAPB3OO0=32'b00000000000000000000000000001111 CAPB3IO0=32'b00000000000000000000000000010000 CAPB3lO0=32'b00000000000000000000000000010001 CAPB3OI0=16'b0000000000000001 CAPB3II0=16'b0000000000000010 CAPB3lI0=16'b0000000000000000 CAPB3Ol0=16'b0000000000000000 CAPB3Il0=16'b0000000000000000 CAPB3ll0=16'b0000000000000000 CAPB3O00=16'b0000000000000000 CAPB3I00=16'b0000000000000000 CAPB3l00=16'b0000000000000000 CAPB3O10=16'b0000000000000000 CAPB3I10=16'b0000000000000000 CAPB3l10=16'b0000000000000000 CAPB3OO1=16'b0000000000000000 CAPB3IO1=16'b0000000000000000 CAPB3lO1=16'b0000000000000000 CAPB3OI1=16'b1000000000000000 CAPB3II1=16'b0000000000000000 CAPB3lI1=16'b0000000000000000 Generated name = CoreAPB3_Z11 @N:CG364 : coreapb3_iaddr_reg.v(10) | Synthesizing module CAPB3O in library COREAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 APB_DWIDTH=6'b100000 MADDR_BITS=6'b010100 Generated name = CAPB3O_0s_32_20 Running optimization stage 1 on CAPB3O_0s_32_20 ....... Running optimization stage 1 on CoreAPB3_Z11 ....... @N:CG364 : Clock_gen.v(30) | Synthesizing module UART_top_CoreUARTapb_0_Clock_gen in library work. BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = UART_top_CoreUARTapb_0_Clock_gen_0s_0s Running optimization stage 1 on UART_top_CoreUARTapb_0_Clock_gen_0s_0s ....... @N:CG364 : Tx_async.v(14) | Synthesizing module UART_top_CoreUARTapb_0_Tx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 TX_FIFO=32'b00000000000000000000000000000001 CUARTI1ll=32'b00000000000000000000000000000000 CUARTl1ll=32'b00000000000000000000000000000001 CUARTOO0l=32'b00000000000000000000000000000010 CUARTIO0l=32'b00000000000000000000000000000011 CUARTlO0l=32'b00000000000000000000000000000100 CUARTOI0l=32'b00000000000000000000000000000101 CUARTII0l=32'b00000000000000000000000000000110 Generated name = UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s @W:CG1340 : Tx_async.v(605) | Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible. @W:CG1340 : Tx_async.v(605) | Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible. @N:CG179 : Tx_async.v(870) | Removing redundant assignment. Running optimization stage 1 on UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s ....... @N:CG364 : Rx_async.v(14) | Synthesizing module UART_top_CoreUARTapb_0_Rx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000001 CUARTOIIl=32'b00000000000000000000000000000000 CUARTIIIl=32'b00000000000000000000000000000001 CUARTlIIl=32'b00000000000000000000000000000010 CUARTOlIl=32'b00000000000000000000000000000011 Generated name = UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s @N:CG179 : Rx_async.v(750) | Removing redundant assignment. @N:CG179 : Rx_async.v(857) | Removing redundant assignment. Running optimization stage 1 on UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s ....... @W:CL177 : Rx_async.v(1613) | Sharing sequential element CUARTI1l. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : Rx_async.v(1613) | Optimizing register bit CUARTO1Il to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:CG364 : CoreUART.v(14) | Synthesizing module UART_top_CoreUARTapb_0_COREUART in library work. TX_FIFO=32'b00000000000000000000000000000001 RX_FIFO=32'b00000000000000000000000000000001 RX_LEGACY_MODE=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011000 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s @N:CG179 : CoreUART.v(1338) | Removing redundant assignment. @N:CG364 : fifo_256x8.v(701) | Synthesizing module UART_top_CoreUARTapb_0_ram16x8 in library work. Running optimization stage 1 on UART_top_CoreUARTapb_0_ram16x8 ....... @N:CL134 : fifo_256x8.v(835) | Found RAM CUARTI00I, depth=16, width=8 @N:CG364 : fifo_256x8.v(163) | Synthesizing module UART_top_CoreUARTapb_0_fifo_ctrl_256 in library work. SYNC_RESET=32'b00000000000000000000000000000000 CUARTl0lI=32'b00000000000000000000000000010000 CUARTO1lI=32'b00000000000000000000000000000100 CUARTI1lI=32'b00000000000000000000000000001000 Generated name = UART_top_CoreUARTapb_0_fifo_ctrl_256_0s_16s_4s_8s @N:CG179 : fifo_256x8.v(655) | Removing redundant assignment. Running optimization stage 1 on UART_top_CoreUARTapb_0_fifo_ctrl_256_0s_16s_4s_8s ....... @A:CL282 : fifo_256x8.v(601) | Feedback mux created for signal CUARTOIII[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @N:CG364 : fifo_256x8.v(14) | Synthesizing module UART_top_CoreUARTapb_0_fifo_256x8 in library work. SYNC_RESET=32'b00000000000000000000000000000000 CUARTOIlI=8'b01000000 Generated name = UART_top_CoreUARTapb_0_fifo_256x8_0s_64s Running optimization stage 1 on UART_top_CoreUARTapb_0_fifo_256x8_0s_64s ....... @W:CG133 : CoreUART.v(333) | Object CUARTlI0 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s ....... @N:CG364 : CoreUARTapb.v(14) | Synthesizing module UART_top_CoreUARTapb_0_CoreUARTapb in library work. FAMILY=32'b00000000000000000000000000011000 TX_FIFO=32'b00000000000000000000000000000001 RX_FIFO=32'b00000000000000000000000000000001 BAUD_VALUE=32'b00000000000000000000000001101011 FIXEDMODE=32'b00000000000000000000000000000001 PRG_BIT8=32'b00000000000000000000000000000001 PRG_PARITY=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = UART_top_CoreUARTapb_0_CoreUARTapb_Z12 @N:CG179 : CoreUARTapb.v(785) | Removing redundant assignment. @N:CG179 : CoreUARTapb.v(868) | Removing redundant assignment. @W:CG133 : CoreUARTapb.v(283) | Object CUARTI1OI is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on UART_top_CoreUARTapb_0_CoreUARTapb_Z12 ....... @N:CG364 : UART_top.v(9) | Synthesizing module UART_top in library work. Running optimization stage 1 on UART_top ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on UART_top ....... Running optimization stage 2 on UART_top_CoreUARTapb_0_CoreUARTapb_Z12 ....... @W:CL246 : CoreUARTapb.v(126) | Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size. @A:CL153 : CoreUARTapb.v(283) | *Unassigned bits of CUARTI1OI[2:0] are referenced and tied to 0 -- simulation mismatch possible. Running optimization stage 2 on UART_top_CoreUARTapb_0_fifo_256x8_0s_64s ....... @N:CL159 : fifo_256x8.v(44) | Input CUARTIOOI is unused. Running optimization stage 2 on UART_top_CoreUARTapb_0_fifo_ctrl_256_0s_16s_4s_8s ....... Running optimization stage 2 on UART_top_CoreUARTapb_0_ram16x8 ....... Running optimization stage 2 on UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s ....... @N:CL201 : CoreUART.v(984) | Trying to extract state machine for register CUARTll0. Extracted state machine for register CUARTll0 State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s ....... @W:CL190 : Rx_async.v(871) | Optimizing register bit CUARTl1Il to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : Rx_async.v(575) | Optimizing register bit CUARTO11 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:CL201 : Rx_async.v(871) | Trying to extract state machine for register CUARTll0. Extracted state machine for register CUARTll0 State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL159 : Rx_async.v(106) | Input CUARTOOl is unused. Running optimization stage 2 on UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s ....... @N:CL201 : Tx_async.v(301) | Trying to extract state machine for register CUARTlI0l. Extracted state machine for register CUARTlI0l State machine has 7 reachable states with original encodings of: 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 00000000000000000000000000000100 00000000000000000000000000000101 00000000000000000000000000000110 @N:CL159 : Tx_async.v(65) | Input CUARTl0I is unused. @N:CL159 : Tx_async.v(73) | Input CUARTO1I is unused. Running optimization stage 2 on UART_top_CoreUARTapb_0_Clock_gen_0s_0s ....... @N:CL159 : Clock_gen.v(75) | Input BAUD_VAL_FRACTION is unused. Running optimization stage 2 on CAPB3O_0s_32_20 ....... @W:CL246 : coreapb3_iaddr_reg.v(74) | Input port bits 31 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CoreAPB3_Z11 ....... @N:CL159 : coreapb3.v(396) | Input IADDR is unused. @N:CL159 : coreapb3.v(528) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(535) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(542) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(549) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(556) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(563) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(570) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(577) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(584) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(591) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(598) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(605) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(612) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(619) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(632) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(634) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(636) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(638) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(640) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(642) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(644) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(646) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(648) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(650) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(652) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(654) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(656) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(658) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(666) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(668) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(670) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(672) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(674) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(676) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(678) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(680) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(682) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(684) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(686) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(688) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(690) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(692) | Input PSLVERRS15 is unused. Running optimization stage 2 on CAPB3II ....... Running optimization stage 2 on UART_top_COREABC_0_INSTRUCTIONS_Z10 ....... Running optimization stage 2 on UART_top_COREABC_0_RAM256X16 ....... @N:CL159 : ram256x16_rtl.v(23) | Input RESET is unused. Running optimization stage 2 on UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s ....... Running optimization stage 2 on UART_top_COREABC_0_COREABC_Z9 ....... @N:CL201 : coreabc.v(1041) | Trying to extract state machine for register ICYCLE. Extracted state machine for register ICYCLE State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL159 : coreabc.v(135) | Input PSLVERR_M is unused. @N:CL159 : coreabc.v(139) | Input INTREQ is unused. @N:CL159 : coreabc.v(142) | Input INITDATVAL is unused. @N:CL159 : coreabc.v(143) | Input INITDONE is unused. @N:CL159 : coreabc.v(144) | Input INITADDR is unused. @N:CL159 : coreabc.v(145) | Input INITDATA is unused. @N:CL159 : coreabc.v(153) | Input PSEL_S is unused. @N:CL159 : coreabc.v(154) | Input PENABLE_S is unused. @N:CL159 : coreabc.v(155) | Input PWRITE_S is unused. @N:CL159 : coreabc.v(156) | Input PADDR_S is unused. @N:CL159 : coreabc.v(157) | Input PWDATA_S is unused. Running optimization stage 2 on APB_register_blk ....... @N:CL201 : APB_register_blk.v(76) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : APB_register_blk.v(29) | Input port bits 31 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : APB_register_blk.v(30) | Input port bits 31 to 4 of PWDATA[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on Binary2Ascii ....... Running optimization stage 2 on Nibble2Ascii ....... Running optimization stage 2 on syssvc_blk ....... Running optimization stage 2 on my_sysservice_state ....... @N:CL201 : Sysservice_state.v(60) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 13 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1111 Running optimization stage 2 on syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z8 ....... Running optimization stage 2 on CoreSysServices_AHBLMasterIF ....... @N:CL159 : CoreSysServices_AHBLMasterIF.v(72) | Input HCLK is unused. @N:CL159 : CoreSysServices_AHBLMasterIF.v(73) | Input HRESETN is unused. Running optimization stage 2 on CoreSysServices_FSMCtrl ....... @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:CL201 : CoreSysServices_FSMCtrl.v(326) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 7 reachable states with original encodings of: 0000 0001 0010 0101 1000 1001 1011 @N:CL159 : CoreSysServices_FSMCtrl.v(162) | Input cfwr_req_d is unused. @N:CL159 : CoreSysServices_FSMCtrl.v(163) | Input cfrd_req_d is unused. Running optimization stage 2 on CoreSysServices_CmdDec_Z7 ....... @W:CL190 : CoreSysServices_CmdDec.v(997) | Optimizing register bit burstlen_memwr_data_r[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. Only the first 100 messages of id 'CL190' are reported. To see all messages use 'report_messages -log C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\synlog\top_compiler.srr -id CL190' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL190} -count unlimited' in the Tcl shell. @W:CL279 : CoreSysServices_CmdDec.v(1096) | Pruning register bits 31 to 16 of cfburst_len_rd_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(997) | Pruning register bit 31 of burstlen_memwr_data_r[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element fcdataout_d1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL260 : CoreSysServices_CmdDec.v(1096) | Pruning register bit 31 of cfburst_len_wr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : CoreSysServices_CmdDec.v(3426) | Trying to extract state machine for register asynchevent_curr_state. Extracted state machine for register asynchevent_curr_state State machine has 2 reachable states with original encodings of: 0000 1001 @N:CL201 : CoreSysServices_CmdDec.v(3004) | Trying to extract state machine for register resp_curr_state. Extracted state machine for register resp_curr_state State machine has 31 reachable states with original encodings of: 000000 000001 000011 000101 000110 000111 001000 001001 001100 001101 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011011 100100 100101 100110 100111 101000 101001 101100 101110 101111 110000 @N:CL201 : CoreSysServices_CmdDec.v(1970) | Trying to extract state machine for register req_curr_state. Extracted state machine for register req_curr_state State machine has 37 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 100001 100010 100101 100110 101000 101001 101010 101011 101100 101101 101110 110000 110001 110010 110011 110100 @N:CL201 : CoreSysServices_CmdDec.v(1640) | Trying to extract state machine for register main_curr_state. @N:CL159 : CoreSysServices_CmdDec.v(345) | Input ucdata_wvalid_i is unused. @N:CL159 : CoreSysServices_CmdDec.v(356) | Input fcpush_i is unused. @N:CL159 : CoreSysServices_CmdDec.v(360) | Input clr_req is unused. Running optimization stage 2 on FLASH_FREEZE ....... Running optimization stage 2 on CoreSysServices_UserIF_Z6 ....... @N:CL135 : CoreSysServices_UserIF.v(772) | Found sequential shift zer_new_serv_d1 with address depth of 3 words and data bit width of 1. @N:CL159 : CoreSysServices_UserIF.v(257) | Input cutrans_done_i is unused. @N:CL159 : CoreSysServices_UserIF.v(262) | Input cutamper_detect_valid is unused. @N:CL159 : CoreSysServices_UserIF.v(263) | Input cutamper_fail_valid is unused. Running optimization stage 2 on my_hpms_top ....... Running optimization stage 2 on my_hpms ....... Running optimization stage 2 on SYSRESET ....... Running optimization stage 2 on my_hpms_HPMS ....... @W:CL247 : my_hpms_HPMS.v(51) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused Running optimization stage 2 on MSS_010 ....... Running optimization stage 2 on my_hpms_FABOSC_0_OSC ....... @N:CL159 : my_hpms_FABOSC_0_OSC.v(14) | Input XTL is unused. Running optimization stage 2 on RCOSC_25_50MHZ ....... Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Running optimization stage 2 on CoreResetP_Z5 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused. @N:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused. @N:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused. @N:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused. @N:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused. @N:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused. @N:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused. @N:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused. @N:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused. @N:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused. @N:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Running optimization stage 2 on CoreAHBLite_Z4 ....... @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused Running optimization stage 2 on COREAHBLITE_MATRIX4X16_1_1_85_65536_65536_0_0_0s ....... Running optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... Running optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z3 ....... @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState. Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 ....... Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z2 ....... Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 ....... @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z1 ....... Running optimization stage 2 on my_hpms_CCC_0_FCCC ....... Running optimization stage 2 on CCC ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on counter28 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 153MB peak: 171MB) Process took 0h:00m:12s realtime, 0h:00m:12s cputime Process completed successfully. # Thu Mar 25 18:21:56 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode File C:\igloo2_task_feb_2021\test\AC425_M2GL_Sysservices_DF\Libero_Project\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 108MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Mar 25 18:21:57 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 23MB peak: 32MB) Process took 0h:00m:13s realtime, 0h:00m:13s cputime Process completed successfully. # Thu Mar 25 18:21:57 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode File C:\igloo2_task_feb_2021\test\AC425_M2GL_Sysservices_DF\Libero_Project\synthesis\synwork\top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Mar 25 18:21:58 2021 ###########################################################] Premap Report # Thu Mar 25 18:21:59 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Reading constraint file: C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(8) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 156MB peak: 156MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 156MB peak: 157MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 157MB peak: 157MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 157MB peak: 159MB) @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_15 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_14 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_13 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_12 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_11 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_9 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_8 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_7 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_6 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3120) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_5 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3074) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_4 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3028) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_3 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(2982) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_2 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3350) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(2936) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_1 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(653) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_hold[4] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_hold[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(653) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchoptions_hold[1] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_hold[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : my_hpms_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : coresysservices_cmddec.v(372) | Tristate driver cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) on net cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) has its enable tied to GND. @N:MO111 : ramblocks.v(41) | Tristate driver DB_DETECT (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) on net DB_DETECT (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) has its enable tied to GND. @N:MO111 : ramblocks.v(40) | Tristate driver SB_CORRECT (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) on net SB_CORRECT (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_0(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z1_1(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_0(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_1(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_65536_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_65536_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because it does not drive other instances. @N:BN115 : coresysservices.v(700) | Removing instance U_AHBLMasterIF (in view: CORESYSSERVICES_LIB.syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z8(verilog)) of type view:CORESYSSERVICES_LIB.CoreSysServices_AHBLMasterIF(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coresysservices_fsmctrl.v(305) | Removing sequential instance clr_req (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_async.v(871) | Removing sequential instance CUARTI00 (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_65536_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because it does not drive other instances. @N:BN362 : coresysservices_fsmctrl.v(838) | Removing sequential instance fmhsel_o (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(416) | Removing sequential instance ucmd_error (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(439) | Removing sequential instance udata_wrdy_d2 (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2461) | Removing sequential instance cudata_wrdy_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=21 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 198MB) @W:MT688 : synthesis.fdc(8) | No path from master pin (-source) to source of clock my_hpms_top_0/my_hpms_0/CCC_0/GL0 due to black box my_hpms_top_0.my_hpms_0.CCC_0.CCC_INST Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 15 1 . my_hpms_top_0/my_hpms_0/CCC_0/GL0 25.0 MHz 40.000 generated (from my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 1330 =========================================================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 15 my_hpms_top_0.my_hpms_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif0_core.C - my_hpms_top_0.my_hpms_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) my_hpms_top_0/my_hpms_0/CCC_0/GL0 1330 my_hpms_top_0.my_hpms_0.CCC_0.CCC_INST.GL0(CCC) UART_top_0.CoreUARTapb_0.CUARTl0OI[7:0].C - my_hpms_top_0.my_hpms_0.CCC_0.GL0_INST.I(BUFG) =============================================================================================================================================================================================================================================================================================================== @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 199MB) Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z5(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine resp_curr_state[30:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) original code -> new code 000000 -> 0000000000000000000000000000001 000001 -> 0000000000000000000000000000010 000011 -> 0000000000000000000000000000100 000101 -> 0000000000000000000000000001000 000110 -> 0000000000000000000000000010000 000111 -> 0000000000000000000000000100000 001000 -> 0000000000000000000000001000000 001001 -> 0000000000000000000000010000000 001100 -> 0000000000000000000000100000000 001101 -> 0000000000000000000001000000000 010000 -> 0000000000000000000010000000000 010001 -> 0000000000000000000100000000000 010010 -> 0000000000000000001000000000000 010011 -> 0000000000000000010000000000000 010100 -> 0000000000000000100000000000000 010101 -> 0000000000000001000000000000000 010110 -> 0000000000000010000000000000000 010111 -> 0000000000000100000000000000000 011000 -> 0000000000001000000000000000000 011001 -> 0000000000010000000000000000000 011011 -> 0000000000100000000000000000000 100100 -> 0000000001000000000000000000000 100101 -> 0000000010000000000000000000000 100110 -> 0000000100000000000000000000000 100111 -> 0000001000000000000000000000000 101000 -> 0000010000000000000000000000000 101001 -> 0000100000000000000000000000000 101100 -> 0001000000000000000000000000000 101110 -> 0010000000000000000000000000000 101111 -> 0100000000000000000000000000000 110000 -> 1000000000000000000000000000000 Encoding state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) original code -> new code 0000 -> 0 1001 -> 1 @N:MO225 : coresysservices_cmddec.v(3426) | There are no possible illegal states for state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)); safe FSM implementation is not required. Encoding state machine req_curr_state[36:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) original code -> new code 000000 -> 0000000000000000000000000000000000001 000001 -> 0000000000000000000000000000000000010 000010 -> 0000000000000000000000000000000000100 000011 -> 0000000000000000000000000000000001000 000100 -> 0000000000000000000000000000000010000 000101 -> 0000000000000000000000000000000100000 000111 -> 0000000000000000000000000000001000000 001000 -> 0000000000000000000000000000010000000 001001 -> 0000000000000000000000000000100000000 001010 -> 0000000000000000000000000001000000000 001011 -> 0000000000000000000000000010000000000 001100 -> 0000000000000000000000000100000000000 001101 -> 0000000000000000000000001000000000000 001110 -> 0000000000000000000000010000000000000 001111 -> 0000000000000000000000100000000000000 010000 -> 0000000000000000000001000000000000000 010001 -> 0000000000000000000010000000000000000 010010 -> 0000000000000000000100000000000000000 010011 -> 0000000000000000001000000000000000000 010100 -> 0000000000000000010000000000000000000 010101 -> 0000000000000000100000000000000000000 100001 -> 0000000000000001000000000000000000000 100010 -> 0000000000000010000000000000000000000 100101 -> 0000000000000100000000000000000000000 100110 -> 0000000000001000000000000000000000000 101000 -> 0000000000010000000000000000000000000 101001 -> 0000000000100000000000000000000000000 101010 -> 0000000001000000000000000000000000000 101011 -> 0000000010000000000000000000000000000 101100 -> 0000000100000000000000000000000000000 101101 -> 0000001000000000000000000000000000000 101110 -> 0000010000000000000000000000000000000 110000 -> 0000100000000000000000000000000000000 110001 -> 0001000000000000000000000000000000000 110010 -> 0010000000000000000000000000000000000 110011 -> 0100000000000000000000000000000000000 110100 -> 1000000000000000000000000000000000000 Encoding state machine curr_state[6:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0101 -> 0001000 1000 -> 0010000 1001 -> 0100000 1011 -> 1000000 @N:BN362 : coresysservices_fsmctrl.v(612) | Removing sequential instance burstwrflag_last_n (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. Encoding state machine fsm_1[12:0] (in view: work.my_sysservice_state(verilog)) original code -> new code 0000 -> 0000000000001 0001 -> 0000000000010 0010 -> 0000000000100 0011 -> 0000000001000 0100 -> 0000000010000 0101 -> 0000000100000 0110 -> 0000001000000 0111 -> 0000010000000 1000 -> 0000100000000 1001 -> 0001000000000 1010 -> 0010000000000 1011 -> 0100000000000 1111 -> 1000000000000 Encoding state machine fsm[2:0] (in view: work.APB_register_blk(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine ICYCLE[3:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1041) | There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)); safe FSM implementation is not required. Encoding state machine CUARTlI0l[6:0] (in view: work.UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 0000001 00000000000000000000000000000001 -> 0000010 00000000000000000000000000000010 -> 0000100 00000000000000000000000000000011 -> 0001000 00000000000000000000000000000100 -> 0010000 00000000000000000000000000000101 -> 0100000 00000000000000000000000000000110 -> 1000000 Encoding state machine CUARTll0[3:0] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(871) | There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. Encoding state machine CUARTll0[3:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreuart.v(984) | There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 207MB peak: 207MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 210MB peak: 210MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 106MB peak: 211MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Thu Mar 25 18:22:02 2021 ###########################################################] Map & Optimize Report # Thu Mar 25 18:22:03 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB) @N:MO111 : my_hpms_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : coresysservices_cmddec.v(372) | Tristate driver cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) on net cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) has its enable tied to GND. @N:MO111 : ramblocks.v(41) | Tristate driver DB_DETECT (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) on net DB_DETECT (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) has its enable tied to GND. @N:MO111 : ramblocks.v(40) | Tristate driver SB_CORRECT (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) on net SB_CORRECT (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(929) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreuart.v(936) | Removing sequential instance UART_top_0.CoreUARTapb_0.CUARTlOlI.CUARTlO0 because it is equivalent to instance UART_top_0.CoreUARTapb_0.CUARTlOlI.CUARTl1l. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreuart.v(888) | Removing sequential instance UART_top_0.CoreUARTapb_0.CUARTlOlI.CUARTOO0 because it is equivalent to instance UART_top_0.CoreUARTapb_0.CUARTlOlI.CUARTOI0. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found @W:BN132 : coresysservices_cmddec.v(3030) | Removing user instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data[7] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(2889) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data_d1[7] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) @N:MO231 : count28.v(16) | Found counter in view:work.top(verilog) instance counter28_0.cnt[27:0] @W:MO160 : coreahblite_masterstage.v(229) | Register bit my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:BN132 : coreahblite_masterstage.v(163) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[1] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[2] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[1] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z5(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[5] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[4] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[3] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[2] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_d1[0] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[5] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[4] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[3] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[2] (in view view:work.syssvc_blk(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine resp_curr_state[30:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) original code -> new code 000000 -> 0000000000000000000000000000001 000001 -> 0000000000000000000000000000010 000011 -> 0000000000000000000000000000100 000101 -> 0000000000000000000000000001000 000110 -> 0000000000000000000000000010000 000111 -> 0000000000000000000000000100000 001000 -> 0000000000000000000000001000000 001001 -> 0000000000000000000000010000000 001100 -> 0000000000000000000000100000000 001101 -> 0000000000000000000001000000000 010000 -> 0000000000000000000010000000000 010001 -> 0000000000000000000100000000000 010010 -> 0000000000000000001000000000000 010011 -> 0000000000000000010000000000000 010100 -> 0000000000000000100000000000000 010101 -> 0000000000000001000000000000000 010110 -> 0000000000000010000000000000000 010111 -> 0000000000000100000000000000000 011000 -> 0000000000001000000000000000000 011001 -> 0000000000010000000000000000000 011011 -> 0000000000100000000000000000000 100100 -> 0000000001000000000000000000000 100101 -> 0000000010000000000000000000000 100110 -> 0000000100000000000000000000000 100111 -> 0000001000000000000000000000000 101000 -> 0000010000000000000000000000000 101001 -> 0000100000000000000000000000000 101100 -> 0001000000000000000000000000000 101110 -> 0010000000000000000000000000000 101111 -> 0100000000000000000000000000000 110000 -> 1000000000000000000000000000000 Encoding state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) original code -> new code 0000 -> 0 1001 -> 1 @N:MO225 : coresysservices_cmddec.v(3426) | There are no possible illegal states for state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)); safe FSM implementation is not required. Encoding state machine req_curr_state[36:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) original code -> new code 000000 -> 0000000000000000000000000000000000001 000001 -> 0000000000000000000000000000000000010 000010 -> 0000000000000000000000000000000000100 000011 -> 0000000000000000000000000000000001000 000100 -> 0000000000000000000000000000000010000 000101 -> 0000000000000000000000000000000100000 000111 -> 0000000000000000000000000000001000000 001000 -> 0000000000000000000000000000010000000 001001 -> 0000000000000000000000000000100000000 001010 -> 0000000000000000000000000001000000000 001011 -> 0000000000000000000000000010000000000 001100 -> 0000000000000000000000000100000000000 001101 -> 0000000000000000000000001000000000000 001110 -> 0000000000000000000000010000000000000 001111 -> 0000000000000000000000100000000000000 010000 -> 0000000000000000000001000000000000000 010001 -> 0000000000000000000010000000000000000 010010 -> 0000000000000000000100000000000000000 010011 -> 0000000000000000001000000000000000000 010100 -> 0000000000000000010000000000000000000 010101 -> 0000000000000000100000000000000000000 100001 -> 0000000000000001000000000000000000000 100010 -> 0000000000000010000000000000000000000 100101 -> 0000000000000100000000000000000000000 100110 -> 0000000000001000000000000000000000000 101000 -> 0000000000010000000000000000000000000 101001 -> 0000000000100000000000000000000000000 101010 -> 0000000001000000000000000000000000000 101011 -> 0000000010000000000000000000000000000 101100 -> 0000000100000000000000000000000000000 101101 -> 0000001000000000000000000000000000000 101110 -> 0000010000000000000000000000000000000 110000 -> 0000100000000000000000000000000000000 110001 -> 0001000000000000000000000000000000000 110010 -> 0010000000000000000000000000000000000 110011 -> 0100000000000000000000000000000000000 110100 -> 1000000000000000000000000000000000000 @N:MO231 : coresysservices_cmddec.v(2481) | Found counter in view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog) instance desc_datasel_cntr[31:0] @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[14] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[13] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[12] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[30] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[29] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[17] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[16] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[14] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[13] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[12] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[7] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[6] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[5] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[31] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[30] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[17] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[16] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[31] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[17] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[7] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[6] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[5] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[0] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[31] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[30] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Only the first 100 messages of id 'MO160' are reported. To see all messages use 'report_messages -log C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\synlog\top_fpga_mapper.srr -id MO160' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {MO160} -count unlimited' in the Tcl shell. @W:BN132 : coresysservices_cmddec.v(2889) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_addr_d1[14] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.resp_srcreg_addr_d1[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine curr_state[6:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0101 -> 0001000 1000 -> 0010000 1001 -> 0100000 1011 -> 1000000 @N:BN362 : coresysservices_fsmctrl.v(612) | Removing sequential instance burstwrflag_last_n (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. @N:MO231 : coresysservices_fsmctrl.v(760) | Found counter in view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog) instance word_count[31:0] Encoding state machine fsm_1[12:0] (in view: work.my_sysservice_state(verilog)) original code -> new code 0000 -> 0000000000001 0001 -> 0000000000010 0010 -> 0000000000100 0011 -> 0000000001000 0100 -> 0000000010000 0101 -> 0000000100000 0110 -> 0000001000000 0111 -> 0000010000000 1000 -> 0000100000000 1001 -> 0001000000000 1010 -> 0010000000000 1011 -> 0100000000000 1111 -> 1000000000000 @W:MO161 : sysservice_state.v(60) | Register bit SERV_CMDBYTE_REQ[0] (in view view:work.my_sysservice_state(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:BN132 : sysservice_state.v(60) | Removing instance syssvc_blk_0.my_sysservice_state_0.SERV_CMDBYTE_REQ[4] because it is equivalent to instance syssvc_blk_0.my_sysservice_state_0.SERV_CMDBYTE_REQ[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine fsm[2:0] (in view: work.APB_register_blk(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:BN132 : apb_register_blk.v(76) | Removing instance UART_top_0.APB_register_blk_0.PRDATA_1[5] because it is equivalent to instance UART_top_0.APB_register_blk_0.PRDATA_1[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine ICYCLE[3:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1041) | There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)); safe FSM implementation is not required. @W:BN132 : coreabc.v(494) | Removing instance UART_top_0.COREABC_0.UROM.INSTR_SLOT[0] because it is equivalent to instance UART_top_0.COREABC_0.UROM.INSTR_MUXC. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:FX106 : ram256x16_rtl.v(32) | Using block RAM for single-port RAM @W:FX107 : ram256x16_rtl.v(32) | RAM UG3\.UR32\.UR0.RAM[31:0] (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:BN362 : ram256x16_rtl.v(32) | Removing sequential instance UG3\.UR32\.UR0.RD[31:0] (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : ram256x16_rtl.v(32) | Removing sequential instance UG3\.UR32\.UR0.RD_ret_31[31:0] (in view: work.UART_top_COREABC_0_RAMBLOCKS_0s_32s_24s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. Encoding state machine CUARTll0[3:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreuart.v(984) | There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)); safe FSM implementation is not required. @N:FX403 : fifo_256x8.v(835) | Property "block_ram" or "no_rw_check" found for RAM genblk3\.CUARTIIOI.CUARTIIlI.CUARTII0I.CUARTI00I[7:0] with specified coding style. Inferring block RAM. @W:FX107 : fifo_256x8.v(835) | RAM genblk3\.CUARTIIOI.CUARTIIlI.CUARTII0I.CUARTI00I[7:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX403 : fifo_256x8.v(835) | Property "block_ram" or "no_rw_check" found for RAM genblk2\.CUARTl11.CUARTIIlI.CUARTII0I.CUARTI00I[7:0] with specified coding style. Inferring block RAM. @W:FX107 : fifo_256x8.v(835) | RAM genblk2\.CUARTl11.CUARTIIlI.CUARTII0I.CUARTI00I[7:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:MO231 : clock_gen.v(1011) | Found counter in view:work.UART_top_CoreUARTapb_0_Clock_gen_0s_0s(verilog) instance genblk1\.CUARTO0[12:0] Encoding state machine CUARTlI0l[6:0] (in view: work.UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 0000001 00000000000000000000000000000001 -> 0000010 00000000000000000000000000000010 -> 0000100 00000000000000000000000000000011 -> 0001000 00000000000000000000000000000100 -> 0010000 00000000000000000000000000000101 -> 0100000 00000000000000000000000000000110 -> 1000000 @N:BN362 : tx_async.v(808) | Removing sequential instance CUARTO00l (in view: work.UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s(verilog)) because it does not drive other instances. Encoding state machine CUARTll0[3:0] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(871) | There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. @W:MO161 : rx_async.v(754) | Register bit CUARTIOll[3] (in view view:work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 212MB) @W:BN132 : coresysservices_userif.v(696) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[7] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(696) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[6] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(696) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[5] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_fsmctrl.v(780) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_fsm_ctrl.fmhaddr_o[1] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_fsm_ctrl.fmhaddr_o[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(653) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[7] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(653) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[6] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(653) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[5] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coresysservices_fsmctrl.v(780) | Removing sequential instance CORESYSSERVICES_0.U_fsm_ctrl.fmhaddr_o[0] (in view: work.syssvc_blk(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(696) | Removing sequential instance CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[3] (in view: work.syssvc_blk(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.INIT_DONE_int (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[6] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : rx_async.v(1430) | Removing sequential instance UART_top_0.CoreUARTapb_0.CUARTlOlI.CUARTO01.CUARTI11 (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 219MB peak: 219MB) @W:BN132 : coreahblite_masterstage.v(163) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[1] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(696) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[4] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[15] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[14] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[13] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[12] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[11] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[10] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[9] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[8] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[6] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[5] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[21] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[20] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[19] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[18] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[17] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[16] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[15] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[14] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[13] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[12] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[11] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[10] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[9] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[8] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[7] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[30] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[29] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[28] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[27] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[26] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[25] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[24] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[23] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[22] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[3] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1924) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_data_addr_r[13] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1924) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_data_addr_r[14] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(653) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(580) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.set_puf_getkcnum (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2829) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cunvm_bfr_iapverify_done (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(653) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchoptions_o[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(653) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_hold[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(653) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.ucnvm_bfr_iapverify (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(641) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.cunvm_bfr_iapverify_done_d1 (in view: work.top(verilog)) because it does not drive other instances. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 207MB peak: 223MB) @N:BN362 : rx_async.v(1154) | Removing sequential instance UART_top_0.CoreUARTapb_0.CUARTlOlI.CUARTO01.CUARTO0Il[8] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : rx_async.v(1339) | Removing sequential instance UART_top_0.CoreUARTapb_0.CUARTlOlI.CUARTO01.CUARTI0Il (in view: work.top(verilog)) because it does not drive other instances. @W:BN132 : coresysservices_cmddec.v(2668) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[6] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[9] because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(653) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[4] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2668) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[5] (in view: work.top(verilog)) because it does not drive other instances. Starting Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 207MB peak: 223MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 207MB peak: 223MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 207MB peak: 223MB) @W:FA239 : coresysservices_cmddec.v(1466) | ROM syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[8:0] (in view: work.top(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : coresysservices_cmddec.v(1466) | ROM syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[8:0] (in view: work.top(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : coresysservices_cmddec.v(1466) | Found ROM syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[8:0] (in view: work.top(verilog)) with 8 words by 9 bits. @N:MO106 : instructions.v(82) | Found ROM UROM\.UROM.doins_0[57:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)) with 563 words by 58 bits. @W:BN132 : coresysservices_cmddec.v(2668) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[14] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(2668) | Removing instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[13] because it is equivalent to instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[18] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[25] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[22]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[20] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[9] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[8] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[7] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[35] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[34] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[24] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[23] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[21] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[50] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[49] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[48] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[47] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[46] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[45] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[44] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[43] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[42] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[41] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[40] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[39] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[38] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[37] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[36] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[57] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[56] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[55] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[54] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[53] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : instructions.v(82) | Removing instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[52] because it is equivalent to instance UART_top_0.COREABC_0.UROM.UROM.doins_0_dreg[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. Only the first 100 messages of id 'BN132' are reported. To see all messages use 'report_messages -log C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\synlog\top_fpga_mapper.srr -id BN132' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN132} -count unlimited' in the Tcl shell. @N:BN362 : coreresetp.v(1549) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif2_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1517) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif1_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1485) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif0_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif3_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif2_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif1_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif0_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(963) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_spll_lock_q2 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(929) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG1_DONE_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(856) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(856) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(755) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(755) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif3_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif2_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif1_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif0_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1613) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1581) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif3_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(912) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(912) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(898) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(898) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif2_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(884) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(884) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif1_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(870) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(870) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2668) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[12] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1255) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdst_addr_d1[12] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : instructions.v(82) | Removing sequential instance UROM\.UROM.doins_0_dreg[19] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 217MB peak: 223MB) Finished technology mapping (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 250MB peak: 281MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:09s 24.16ns 3059 / 948 @N:BN362 : coresysservices_cmddec.v(1924) | Removing sequential instance syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.memwr_data_addr_r[29] (in view: work.top(verilog)) because it does not drive other instances. @N:FP130 : | Promoting Net MSS_HPMS_READY_int_arst on CLKINT I_562 @N:FP130 : | Promoting Net genblk2\.RSTSYNC2_data on CLKINT I_548 @N:FP130 : | Promoting Net genblk2\.RSTSYNC2_arst on CLKINT I_549 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 251MB peak: 281MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 251MB peak: 281MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 955 clock pin(s) of sequential element(s) 0 instances converted, 955 sequential instances remain driven by gated/generated clocks ============================================================================================== Gated/Generated Clocks ============================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 my_hpms_top_0.my_hpms_0.CCC_0.CCC_INST CCC 955 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_010 ==================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 207MB peak: 281MB) Writing Analyst data base C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 243MB peak: 281MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 244MB peak: 281MB) Start final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 238MB peak: 281MB) @W:MT246 : my_hpms_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock my_hpms_top_0/my_hpms_0/CCC_0/GL0 with period 40.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Thu Mar 25 18:22:15 2021 # Top view: top Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 27.560 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ my_hpms_top_0/my_hpms_0/CCC_0/GL0 25.0 MHz 80.4 MHz 40.000 12.440 27.560 generated (from my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz NA 20.000 NA NA declared default_clkgroup ============================================================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0/my_hpms_0/CCC_0/GL0 my_hpms_top_0/my_hpms_0/CCC_0/GL0 | 40.000 27.560 | No paths - | No paths - | No paths - ============================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: my_hpms_top_0/my_hpms_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_top_0/my_hpms_0/CCC_0/GL0 MSS_010 F_FM0_READYOUT CoreAHBLite_0_AHBmslave16_HREADY 3.086 27.560 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_top_0/my_hpms_0/CCC_0/GL0 MSS_010 F_FM0_RESP CoreAHBLite_0_AHBmslave16_HRESP 3.189 28.310 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[8] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE Q SDATASELInt[8] 0.094 29.087 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[1] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE Q SDATASELInt[1] 0.094 29.155 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[9] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE Q SDATASELInt[9] 0.094 29.155 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[10] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE Q SDATASELInt[10] 0.094 29.195 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[12] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE Q SDATASELInt[12] 0.094 29.195 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE Q SDATASELInt[3] 0.094 29.223 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[11] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE Q SDATASELInt[11] 0.094 29.262 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[5] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE Q SDATASELInt[5] 0.094 29.263 =============================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_top_0/my_hpms_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[29] CoreAHBLite_0_AHBmslave16_HWDATA[29] 39.902 27.560 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_top_0/my_hpms_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[1] CoreAHBLite_0_AHBmslave16_HWDATA[1] 39.926 27.943 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_top_0/my_hpms_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[0] CoreAHBLite_0_AHBmslave16_HWDATA[0] 39.888 28.012 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_top_0/my_hpms_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[7] CoreAHBLite_0_AHBmslave16_HWDATA[7] 39.893 28.017 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_top_0/my_hpms_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[4] CoreAHBLite_0_AHBmslave16_HWDATA[4] 39.953 28.038 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_top_0/my_hpms_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[2] CoreAHBLite_0_AHBmslave16_HWDATA[2] 39.949 28.073 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[29] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE D syssvc_blk_0_AHBL_MASTER_HWDATA[29] 39.778 28.502 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[1] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE D syssvc_blk_0_AHBL_MASTER_HWDATA[1] 39.778 28.861 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[4] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE D syssvc_blk_0_AHBL_MASTER_HWDATA[4] 39.778 28.921 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[0] my_hpms_top_0/my_hpms_0/CCC_0/GL0 SLE D syssvc_blk_0_AHBL_MASTER_HWDATA[0] 39.778 28.954 ============================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 40.000 - Setup time: 0.098 + Clock delay at ending point: 0.000 (ideal) = Required time: 39.902 - Propagation time: 12.342 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 27.560 Number of logic level(s): 10 Starting point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_WDATA[29] The start point is clocked by my_hpms_top_0/my_hpms_0/CCC_0/GL0 [rising] (rise=0.000 fall=20.000 period=40.000) on pin CLK_BASE The end point is clocked by my_hpms_top_0/my_hpms_0/CCC_0/GL0 [rising] (rise=0.000 fall=20.000 period=40.000) on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_010 F_FM0_READYOUT Out 3.086 3.086 f - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.971 - 7 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre_20_iv CFG4 B In - 4.057 f - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre_20_iv CFG4 Y Out 0.143 4.200 f - mchready_i Net - - 1.033 - 25 syssvc_blk_0.CORESYSSERVICES_0.U_fsm_ctrl.pop CFG3 A In - 5.233 f - syssvc_blk_0.CORESYSSERVICES_0.U_fsm_ctrl.pop CFG3 Y Out 0.076 5.309 f - fcpop_o Net - - 0.885 - 9 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int CFG4 C In - 6.193 f - syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int CFG4 Y Out 0.182 6.375 f - un2_cudata_wrdy_int Net - - 0.648 - 3 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_4 CFG4 C In - 7.024 f - syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_4 CFG4 Y Out 0.182 7.206 f - un2_cudata_wrdy_int_4 Net - - 0.648 - 3 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o29 CFG4 C In - 7.854 f - syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o29 CFG4 Y Out 0.194 8.048 r - cfdatain_o29 Net - - 0.216 - 1 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un1_cfdatain_o26 CFG4 D In - 8.264 r - syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.un1_cfdatain_o26 CFG4 Y Out 0.236 8.500 r - N_3773 Net - - 0.779 - 6 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_a2_3_0[29] CFG4 C In - 9.279 r - syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_a2_3_0[29] CFG4 Y Out 0.196 9.475 f - N_3606_3 Net - - 0.779 - 6 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_a2[29] CFG4 B In - 10.254 f - syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_a2[29] CFG4 Y Out 0.143 10.396 f - N_3606 Net - - 0.216 - 1 syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0[29] CFG4 D In - 10.613 f - syssvc_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0[29] CFG4 Y Out 0.250 10.863 f - syssvc_blk_0_AHBL_MASTER_HWDATA[29] Net - - 0.432 - 2 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA[29] CFG2 A In - 11.295 f - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA[29] CFG2 Y Out 0.076 11.371 f - CoreAHBLite_0_AHBmslave16_HWDATA[29] Net - - 0.971 - 1 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_010 F_FM0_WDATA[29] In - 12.342 f - =============================================================================================================================================================== Total path delay (propagation time + setup) of 12.440 is 4.862(39.1%) logic and 7.578(60.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(9) | Timing constraint (through [get_nets { my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled my_hpms_top_0.my_hpms_0.CORERESETP_0.count_ddr_enable my_hpms_top_0.my_hpms_0.CORERESETP_0.release_sdif*_core my_hpms_top_0.my_hpms_0.CORERESETP_0.count_sdif*_enable }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(10) | Timing constraint (from [get_cells { my_hpms_top_0.my_hpms_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(11) | Timing constraint (from [get_cells { my_hpms_top_0.my_hpms_0.CORERESETP_0.MSS_HPMS_READY_int my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(12) | Timing constraint (through [get_nets { my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG1_DONE my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG2_DONE my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF*_PERST_N my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF*_PSEL my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF*_PWRITE my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF*_PRDATA[*] my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_EXT_RESET_OUT my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_RESET_F2M my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_M3_RESET my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_FDDR_CORE_RESET my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET my_hpms_top_0.my_hpms_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(13) | Timing constraint (through [get_pins { my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(14) | Timing constraint (through [get_pins { UART_top_0.COREABC_0.NSYSRESET* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(15) | Timing constraint (through [get_pins { my_hpms_top_0.my_hpms_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 238MB peak: 281MB) Finished timing report (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 238MB peak: 281MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2gl010tsvf400-1 Cell usage: CCC 1 use CLKINT 3 uses MSS_010 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG1 10 uses CFG2 391 uses CFG3 754 uses CFG4 1056 uses Carry cells: ARI1 197 uses - used for arithmetic functions ARI1 87 uses - used for Wide-Mux implementation Total ARI1 284 uses Sequential Cells: SLE 948 uses DSP Blocks: 0 of 22 (0%) I/O ports: 11 I/O primitives: 10 INBUF 1 use OUTBUF 9 uses Global Clock Buffers: 3 RAM/ROM usage summary Total Block RAMs (RAM1K18) : 2 of 21 (9%) Total Block RAMs (RAM64x18) : 2 of 22 (9%) Total LUTs: 2495 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 72; LUTs = 72; RAM1K18 Interface Logic : SLEs = 72; LUTs = 72; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 948 + 72 + 72 + 0 = 1092; Total number of LUTs after P&R: 2495 + 72 + 72 + 0 = 2639; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 79MB peak: 281MB) Process took 0h:00m:12s realtime, 0h:00m:12s cputime # Thu Mar 25 18:22:16 2021 ###########################################################]