@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":541:2:541:11|Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":541:2:541:11|Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":541:2:541:11|Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":541:2:541:11|Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2639:2:2639:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":209:2:209:15|Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2703:2:2703:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2767:2:2767:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":209:2:209:15|Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG1283 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2831:2:2831:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL318 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":789:3:789:8|Pruning unused register cuhprior_flushdone_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":738:3:738:8|Pruning unused register pord_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":738:3:738:8|Pruning unused register pord_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":592:3:592:8|Pruning unused register custatus_out_en_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":522:3:522:8|Pruning unused register pord_comb_d1. Make sure that there are no unused intermediate registers.
@W: CL207 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":719:3:719:8|All reachable assignments to pord assign 0, register removed by optimization.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":505:3:505:8|Optimizing register bit hprior_kp_busy_high to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 5 to 2 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bit 0 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 7 to 5 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bit 3 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 1 to 0 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":505:3:505:8|Pruning unused register hprior_kp_busy_high. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":418:30:418:40|Object cfwr_req_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":436:30:436:43|Object cfsrc_addr_int is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":437:30:437:43|Object cfdst_addr_int is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":447:30:447:39|Object memwr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":470:30:470:44|Object req_srcreg_addr is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":472:30:472:44|Object req_srcreg_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":512:30:512:50|Object cuhprior_flushdone_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":555:30:555:41|Removing wire cfwr_req_int, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":557:30:557:39|Removing wire cfwr_req_c, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":563:30:563:39|Removing wire cfdata_w_o, as there is no assignment to it.
@W: CL318 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":372:29:372:42|*Output cutrans_done_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL168 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2927:16:2927:29|Removing instance FLASH_FREEZE_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2980:3:2980:8|Pruning unused register FF_exit. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2962:3:2962:8|Pruning unused register FF_exit_led. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2949:3:2949:8|Pruning unused register FF_entry_led. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2939:3:2939:8|Pruning unused register FF_entry. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning unused register cunvm_bfr_iapverify_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2770:3:2770:8|Pruning unused register latchen_hrdata_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register fiicreg_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register commctrlreg_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register commpoll_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Pruning unused register set_puf_getkcnum_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1906:3:1906:8|Pruning unused register wait_count[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1731:3:1731:8|Pruning unused register fctrans_done_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1611:3:1611:8|Pruning unused register pord_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1611:3:1611:8|Pruning unused register pord_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1582:3:1582:8|Pruning unused register req_phase_active_pulse. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1532:3:1532:8|Pruning unused register resp_data_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1532:3:1532:8|Pruning unused register req_phase_active_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1033:3:1033:8|Pruning unused register resp_desc_done. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1033:3:1033:8|Pruning unused register resp_frm_done. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1015:3:1015:8|Pruning unused register req_desc_done. Make sure that there are no unused intermediate registers.
@W: CL271 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Pruning unused bits 31 to 8 of fcdataout_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL113 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2811:3:2811:8|Feedback mux created for signal cutamper_msg[7:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL207 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2786:3:2786:8|All reachable assignments to cutamper_msg_valid assign 0, register removed by optimization.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Sharing sequential element fcpop_d1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element tamper_fail_valid_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element tamper_detect_valid_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL207 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1594:3:1594:8|All reachable assignments to pord assign 0, register removed by optimization.
@W: CL250 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2811:3:2811:8|All reachable assignments to cutamper_msg[7:0] assign 0, register removed by optimization
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Optimizing register bit cutamper_detect_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Optimizing register bit cutamper_fail_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 31 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 29 to 17 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 15 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 12 to 5 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 1 to 0 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 31 to 30 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 28 to 8 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 6 to 5 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 2 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 0 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Pruning unused register cutamper_detect_valid. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Pruning unused register cutamper_fail_valid. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":236:21:236:36|Object rvalid_out_en_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":237:21:237:36|Object rvalid_out_en_d2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":245:21:245:31|Removing wire fmhaddr_lat, as there is no assignment to it.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":952:3:952:8|Pruning unused register busreq_prev. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":934:6:934:11|Pruning unused register pop_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":868:5:868:10|Pruning unused register fmhtrans_int2[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":732:3:732:8|Pruning unused register haddr_prev[29:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":709:2:709:7|Pruning unused register latch_addr_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":709:2:709:7|Pruning unused register latch_addr_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":639:2:639:7|Pruning unused register latch_addr_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":627:2:627:7|Pruning unused register state_prev_clk[3:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":853:5:853:10|Optimizing register bit fmhtrans_int[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":853:5:853:10|Pruning register bit 0 of fmhtrans_int[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Pruning register bits 2 to 1 of fmhburst_d1[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":259:29:259:41|Removing wire cfburst_len_o, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":265:29:265:42|Removing wire ustatus_resp_o, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":266:29:266:35|Removing wire ubusy_o, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":267:29:267:38|Removing wire udata_en_o, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":268:29:268:41|Removing wire udata_valid_o, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":269:29:269:37|Removing wire udata_r_o, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":275:29:275:41|Removing wire uclatchpord_o, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":281:29:281:45|Removing wire uccrypto_opmode_o, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":304:29:304:40|Removing wire cudata_wen_o, as there is no assignment to it.
@W: CL113 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v":60:0:60:5|Feedback mux created for signal DSN_VALUE[95:95]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v":60:0:60:5|All reachable assignments to DSN_VALUE[95] assign 0, register removed by optimization
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v":60:0:60:5|Optimizing register bit SERV_OPTIONS_MODE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v":60:0:60:5|Optimizing register bit SERV_OPTIONS_MODE[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v":60:0:60:5|Pruning register bit 2 of SERV_OPTIONS_MODE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v":60:0:60:5|Pruning register bit 0 of SERV_OPTIONS_MODE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Optimizing register bit PRDATA[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Pruning register bits 31 to 16 of PRDATA[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[0][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[1][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[2][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[3][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[4][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[5][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[6][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[7][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[8][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[9][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[10][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[11][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[12][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[13][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[14][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[15][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[16][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[17][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[18][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[19][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[20][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[21][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[22][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[23][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[24][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[25][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[26][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[27][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[28][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[29][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[30][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[31][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[32][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[33][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[34][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[35][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[36][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[37][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Pruning unused register RAM[38][15:0]. Make sure that there are no unused intermediate registers.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ramblocks.v":43:23:43:25|Removing wire RDW, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ramblocks.v":49:15:49:18|Removing wire RDYY, as there is no assignment to it.
@W: CL318 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ramblocks.v":40:11:40:20|*Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ramblocks.v":41:11:41:19|*Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":696:34:696:37|Object MULT is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":697:34:697:34|Object A is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":698:34:698:34|Object B is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":1358:16:1358:16|Object b is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":234:9:234:14|Removing wire DEBUG1, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":235:9:235:14|Removing wire DEBUG2, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":236:9:236:23|Removing wire DEBUGBLK_RESETN, as there is no assignment to it.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":262:12:262:14|Object iii is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":263:25:263:33|Object RAMDOUTXX is declared but not assigned. Either assign a value or remove the declaration.
@W: CG134 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":267:14:267:21|No assignment to bit 11 of ins_addr
@W: CG134 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":267:14:267:21|No assignment to bit 12 of ins_addr
@W: CG134 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":267:14:267:21|No assignment to bit 13 of ins_addr
@W: CG134 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":267:14:267:21|No assignment to bit 14 of ins_addr
@W: CG134 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":267:14:267:21|No assignment to bit 15 of ins_addr
@W: CL207 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":1041:4:1041:9|All reachable assignments to ISR assign 0, register removed by optimization.
@W: CL207 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":1041:4:1041:9|All reachable assignments to DOISR assign 0, register removed by optimization.
@W: CL207 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":818:4:818:9|All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization.
@W: CL207 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":818:4:818:9|All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":494:12:494:17|Pruning register bit 4 of UROM.INSTR_SLOT[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG1340 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v":605:0:605:5|Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v":605:0:605:5|Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":1613:0:1613:5|Sharing sequential element CUARTI1l. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":1613:0:1613:5|Optimizing register bit CUARTO1Il to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUART.v":333:0:333:7|Object CUARTlI0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":283:0:283:8|Object CUARTI1OI is declared but not assigned. Either assign a value or remove the declaration.
@W: CL246 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":126:0:126:4|Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":871:0:871:5|Optimizing register bit CUARTl1Il to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":575:0:575:5|Optimizing register bit CUARTO11 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL246 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v":74:0:74:4|Input port bits 31 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":29:14:29:18|Input port bits 31 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":30:14:30:19|Input port bits 31 to 4 of PWDATA[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":997:3:997:8|Optimizing register bit burstlen_memwr_data_r[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Pruning register bits 31 to 16 of cfburst_len_rd_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":997:3:997:8|Pruning register bit 31 of burstlen_memwr_data_r[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element fcdataout_d1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL260 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Pruning register bit 31 of cfburst_len_wr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_HPMS\my_hpms_HPMS.v":51:14:51:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL246 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 15 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 15 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.

