@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG334 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\iram512x9_rtl.v":57:21:57:33|Read directive translate_off.
@N: CG333 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\iram512x9_rtl.v":65:21:65:32|Read directive translate_on.
@N: CG334 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\debugblk.v":68:17:68:29|Read directive translate_off.
@N: CG333 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\debugblk.v":745:17:745:28|Read directive translate_on.
@N: CG334 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":992:21:992:33|Read directive translate_off.
@N: CG333 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":994:21:994:32|Read directive translate_on.
@N: CG334 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":1389:17:1389:29|Read directive translate_off.
@N: CG333 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":1433:17:1433:28|Read directive translate_on.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Count28.v":3:7:3:15|Synthesizing module counter28 in library work.
@N: CG775 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Component CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":376:7:376:9|Synthesizing module VCC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":372:7:372:9|Synthesizing module GND in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":729:7:729:9|Synthesizing module CCC in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\CCC_0\my_hpms_CCC_0_FCCC.v":5:7:5:24|Synthesizing module my_hpms_CCC_0_FCCC in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":20:7:20:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":20:7:20:30|Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":22:7:22:28|Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":23:7:23:28|Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Synthesizing module CoreAHBLite in library COREAHBLITE_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v":5:7:5:26|Synthesizing module my_hpms_FABOSC_0_OSC in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_HPMS\my_hpms_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010 in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_HPMS\my_hpms_HPMS.v":9:7:9:18|Synthesizing module my_hpms_HPMS in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":720:7:720:14|Synthesizing module SYSRESET in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\my_hpms.v":9:7:9:13|Synthesizing module my_hpms in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_top\my_hpms_top.v":9:7:9:17|Synthesizing module my_hpms_top in library work.
@N: CG775 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":30:7:30:50|Component syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES not found in library "work" or "__hyper__lib__", but found in library CORESYSSERVICES_LIB
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":30:7:30:28|Synthesizing module CoreSysServices_UserIF in library CORESYSSERVICES_LIB.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v":837:7:837:18|Synthesizing module FLASH_FREEZE in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":30:7:30:28|Synthesizing module CoreSysServices_CmdDec in library CORESYSSERVICES_LIB.
@N: CG179 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1912:26:1912:35|Removing redundant assignment.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":30:7:30:29|Synthesizing module CoreSysServices_FSMCtrl in library CORESYSSERVICES_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v":30:7:30:34|Synthesizing module CoreSysServices_AHBLMasterIF in library CORESYSSERVICES_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":30:7:30:50|Synthesizing module syssvc_blk_CORESYSSERVICES_0_CORESYSSERVICES in library CORESYSSERVICES_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v":5:7:5:25|Synthesizing module my_sysservice_state in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\syssvc_blk.v":9:7:9:16|Synthesizing module syssvc_blk in library work.
@N: CG775 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":13:0:13:7|Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Hex_to_ascii.v":20:7:20:18|Synthesizing module Nibble2Ascii in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Hex_to_ascii.v":2:7:2:18|Synthesizing module Binary2Ascii in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":2:7:2:22|Synthesizing module APB_register_blk in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":46:7:46:32|Synthesizing module UART_top_COREABC_0_COREABC in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ramblocks.v":25:7:25:34|Synthesizing module UART_top_COREABC_0_RAMBLOCKS in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":20:7:20:34|Synthesizing module UART_top_COREABC_0_RAM256X16 in library work.
@N: CL134 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":32:4:32:9|Found RAM RAM, depth=256, width=16
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\instructions.v":26:7:26:37|Synthesizing module UART_top_COREABC_0_INSTRUCTIONS in library work.
@N: CL189 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":494:12:494:17|Register bit UROM.INSTR_SLOT[4] is always 0.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v":13:0:13:6|Synthesizing module CAPB3II in library COREAPB3_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":13:0:13:7|Synthesizing module CoreAPB3 in library COREAPB3_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v":10:0:10:5|Synthesizing module CAPB3O in library COREAPB3_LIB.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Clock_gen.v":30:0:30:31|Synthesizing module UART_top_CoreUARTapb_0_Clock_gen in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v":14:0:14:30|Synthesizing module UART_top_CoreUARTapb_0_Tx_async in library work.
@N: CG179 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v":870:0:870:8|Removing redundant assignment.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":14:0:14:30|Synthesizing module UART_top_CoreUARTapb_0_Rx_async in library work.
@N: CG179 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":750:0:750:7|Removing redundant assignment.
@N: CG179 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":857:0:857:8|Removing redundant assignment.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUART.v":14:0:14:30|Synthesizing module UART_top_CoreUARTapb_0_COREUART in library work.
@N: CG179 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUART.v":1338:0:1338:7|Removing redundant assignment.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\fifo_256x8.v":701:0:701:29|Synthesizing module UART_top_CoreUARTapb_0_ram16x8 in library work.
@N: CL134 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\fifo_256x8.v":835:0:835:5|Found RAM CUARTI00I, depth=16, width=8
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\fifo_256x8.v":163:0:163:35|Synthesizing module UART_top_CoreUARTapb_0_fifo_ctrl_256 in library work.
@N: CG179 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\fifo_256x8.v":655:0:655:8|Removing redundant assignment.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\fifo_256x8.v":14:0:14:32|Synthesizing module UART_top_CoreUARTapb_0_fifo_256x8 in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":14:0:14:33|Synthesizing module UART_top_CoreUARTapb_0_CoreUARTapb in library work.
@N: CG179 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":785:0:785:8|Removing redundant assignment.
@N: CG179 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":868:0:868:8|Removing redundant assignment.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\UART_top.v":9:7:9:14|Synthesizing module UART_top in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\top\top.v":9:7:9:9|Synthesizing module top in library work.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\fifo_256x8.v":44:0:44:8|Input CUARTIOOI is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUART.v":984:0:984:5|Trying to extract state machine for register CUARTll0.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":871:0:871:5|Trying to extract state machine for register CUARTll0.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v":106:0:106:7|Input CUARTOOl is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Trying to extract state machine for register CUARTlI0l.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v":65:0:65:7|Input CUARTl0I is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v":73:0:73:7|Input CUARTO1I is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Clock_gen.v":75:0:75:16|Input BAUD_VAL_FRACTION is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":396:0:396:4|Input IADDR is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":528:0:528:7|Input PRDATAS2 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":535:0:535:7|Input PRDATAS3 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":542:0:542:7|Input PRDATAS4 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":549:0:549:7|Input PRDATAS5 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":556:0:556:7|Input PRDATAS6 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":563:0:563:7|Input PRDATAS7 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":570:0:570:7|Input PRDATAS8 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":577:0:577:7|Input PRDATAS9 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":584:0:584:8|Input PRDATAS10 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":591:0:591:8|Input PRDATAS11 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":598:0:598:8|Input PRDATAS12 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":605:0:605:8|Input PRDATAS13 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":612:0:612:8|Input PRDATAS14 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":619:0:619:8|Input PRDATAS15 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":632:0:632:7|Input PREADYS2 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":634:0:634:7|Input PREADYS3 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":636:0:636:7|Input PREADYS4 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":638:0:638:7|Input PREADYS5 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":640:0:640:7|Input PREADYS6 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":642:0:642:7|Input PREADYS7 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":644:0:644:7|Input PREADYS8 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":646:0:646:7|Input PREADYS9 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":648:0:648:8|Input PREADYS10 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":650:0:650:8|Input PREADYS11 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":652:0:652:8|Input PREADYS12 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":654:0:654:8|Input PREADYS13 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":656:0:656:8|Input PREADYS14 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":658:0:658:8|Input PREADYS15 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":666:0:666:8|Input PSLVERRS2 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":668:0:668:8|Input PSLVERRS3 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":670:0:670:8|Input PSLVERRS4 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":672:0:672:8|Input PSLVERRS5 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":674:0:674:8|Input PSLVERRS6 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":676:0:676:8|Input PSLVERRS7 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":678:0:678:8|Input PSLVERRS8 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":680:0:680:8|Input PSLVERRS9 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":682:0:682:9|Input PSLVERRS10 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":684:0:684:9|Input PSLVERRS11 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":686:0:686:9|Input PSLVERRS12 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":688:0:688:9|Input PSLVERRS13 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":690:0:690:9|Input PSLVERRS14 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v":692:0:692:9|Input PSLVERRS15 is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v":23:10:23:14|Input RESET is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":1041:4:1041:9|Trying to extract state machine for register ICYCLE.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":135:10:135:18|Input PSLVERR_M is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":139:10:139:15|Input INTREQ is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":142:10:142:19|Input INITDATVAL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":143:10:143:17|Input INITDONE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":144:27:144:34|Input INITADDR is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":145:15:145:22|Input INITDATA is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":153:11:153:16|Input PSEL_S is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":154:11:154:19|Input PENABLE_S is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":155:11:155:18|Input PWRITE_S is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":156:28:156:34|Input PADDR_S is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v":157:28:157:35|Input PWDATA_S is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v":76:0:76:5|Trying to extract state machine for register fsm.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v":60:0:60:5|Trying to extract state machine for register fsm.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v":72:28:72:31|Input HCLK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v":73:28:73:34|Input HRESETN is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":326:3:326:8|Trying to extract state machine for register curr_state.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":162:21:162:30|Input cfwr_req_d is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":163:21:163:30|Input cfrd_req_d is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":3426:3:3426:8|Trying to extract state machine for register asynchevent_curr_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":3004:3:3004:8|Trying to extract state machine for register resp_curr_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1970:3:1970:8|Trying to extract state machine for register req_curr_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1640:3:1640:8|Trying to extract state machine for register main_curr_state.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":345:17:345:31|Input ucdata_wvalid_i is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":356:17:356:24|Input fcpush_i is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":360:17:360:23|Input clr_req is unused.
@N: CL135 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":772:3:772:8|Found sequential shift zer_new_serv_d1 with address depth of 3 words and data bit width of 1.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":257:28:257:41|Input cutrans_done_i is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":262:28:262:48|Input cutamper_detect_valid is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":263:28:263:46|Input cutamper_fail_valid is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":107:20:107:37|Input SOFT_EXT_RESET_OUT is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":108:20:108:33|Input SOFT_RESET_F2M is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":109:20:109:32|Input SOFT_M3_RESET is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":110:20:110:49|Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":111:20:111:39|Input SOFT_FDDR_CORE_RESET is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":112:20:112:39|Input SOFT_SDIF0_PHY_RESET is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":113:20:113:40|Input SOFT_SDIF0_CORE_RESET is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":114:20:114:39|Input SOFT_SDIF1_PHY_RESET is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":115:20:115:40|Input SOFT_SDIF1_CORE_RESET is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":116:20:116:39|Input SOFT_SDIF2_PHY_RESET is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":117:20:117:40|Input SOFT_SDIF2_CORE_RESET is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Trying to extract state machine for register arbRegSMCurrentState.
@N|Running in 64-bit mode

