Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Thu Mar 25 18:23:47 2021

Design top
Family IGLOO2
Die M2GL010TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
my_hpms_top_0/my_hpms_0/CCC_0/GL0 40.000 25.000 31.451 WORST
my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain my_hpms_top_0/my_hpms_0/CCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_RAM_0_0/INST_RAM1K18_IP:A_CLK UART_top_0/COREABC_0/STD_ACCUM_ZERO:D 8.164 31.451 12.454 43.905 0.254 8.549 WORST
Path 2 UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_RAM_0_1/INST_RAM1K18_IP:A_CLK UART_top_0/COREABC_0/STD_ACCUM_ZERO:D 8.044 31.573 12.332 43.905 0.254 8.427 WORST
Path 3 UART_top_0/COREABC_0/UROM.UROM/doins_0_dreg[1]:CLK UART_top_0/COREABC_0/STD_ACCUM_ZERO:D 8.115 31.638 12.267 43.905 0.254 8.362 WORST
Path 4 UART_top_0/COREABC_0/UROM.INSTR_DATA_ret_1:CLK UART_top_0/COREABC_0/STD_ACCUM_ZERO:D 8.055 31.710 12.195 43.905 0.254 8.290 WORST
Path 5 UART_top_0/COREABC_0/UROM.UROM/doins_0_dreg[4]:CLK UART_top_0/COREABC_0/STD_ACCUM_ZERO:D 7.907 31.851 12.054 43.905 0.254 8.149 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_RAM_0_0/INST_RAM1K18_IP:A_CLK
To: UART_top_0/COREABC_0/STD_ACCUM_ZERO:D
data required time 43.905
data arrival time - 12.454
slack 31.451
Data arrival time calculation
my_hpms_top_0/my_hpms_0/CCC_0/GL0 0.000 0.000
my_hpms_top_0/my_hpms_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.783 2.783
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_net + 0.201 2.984 r
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 3.150 9 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.292 3.442 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YR cell ADLIB:RGB + 0.250 3.692 44 r
UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_RAM_0_0/FF_0:CLK net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbr_net_1 + 0.458 4.150 r
UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_RAM_0_0/FF_0:IPCLKn cell ADLIB:SLE_IP_CLK + 0.059 4.209 1 f
UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_RAM_0_0/INST_RAM1K18_IP:A_CLK net UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_RAM_0_0/A_CLK_net + 0.081 4.290 r
UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_RAM_0_0/INST_RAM1K18_IP:A_DOUT[17] cell ADLIB:RAM1K18_IP + 1.380 5.670 2 r
UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RD_ret_RNI19L7[17]:A net UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RAM_o[1] + 0.883 6.553 r
UART_top_0/COREABC_0/URAM.UR/UG3.UR32.UR0/RD_ret_RNI19L7[17]:Y cell ADLIB:CFG3 + 0.074 6.627 3 r
UART_top_0/COREABC_0/ACCUM_IN[1]:A net UART_top_0/COREABC_0/RAMRDATA[1] + 0.225 6.852 r
UART_top_0/COREABC_0/ACCUM_IN[1]:Y cell ADLIB:CFG3 + 0.074 6.926 2 r
UART_top_0/COREABC_0/ACCUM_IN_RNII75Q[1]:A net UART_top_0/COREABC_0/ACCUM_IN_Z[1] + 0.228 7.154 r
UART_top_0/COREABC_0/ACCUM_IN_RNII75Q[1]:Y cell ADLIB:CFG3 + 0.100 7.254 1 f
UART_top_0/COREABC_0/ACCUM_NEXT_m2_RNIHC1A1[1]:A net UART_top_0/COREABC_0/ACCUM_NEXT_m6_1_1[1] + 0.440 7.694 f
UART_top_0/COREABC_0/ACCUM_NEXT_m2_RNIHC1A1[1]:Y cell ADLIB:CFG4 + 0.221 7.915 1 r
UART_top_0/COREABC_0/un1_PSLVERR_S_2_RNISR343[1]:C net UART_top_0/COREABC_0/ACCUM_NEXT_m2_RNIHC1A1_Z[1] + 0.802 8.717 r
UART_top_0/COREABC_0/un1_PSLVERR_S_2_RNISR343[1]:P cell ADLIB:ARI1_CC + 0.177 8.894 1 f
UART_top_0/COREABC_0/un1_PSLVERR_S_2_RNISR1I1[0]_CC_0:P[1] net NET_CC_CONFIG363 + 0.000 8.894 f
UART_top_0/COREABC_0/un1_PSLVERR_S_2_RNISR1I1[0]_CC_0:CO cell ADLIB:CC_CONFIG + 0.630 9.524 1 f
UART_top_0/COREABC_0/un1_PSLVERR_S_2_RNISR1I1[0]_CC_1:CI net CI_TO_CO358 + 0.000 9.524 f
UART_top_0/COREABC_0/un1_PSLVERR_S_2_RNISR1I1[0]_CC_1:CO cell ADLIB:CC_CONFIG + 0.185 9.709 1 f
UART_top_0/COREABC_0/un1_PSLVERR_S_2_RNISR1I1[0]_CC_2:CI net CI_TO_CO359 + 0.000 9.709 f
UART_top_0/COREABC_0/un1_PSLVERR_S_2_RNISR1I1[0]_CC_2:CC[2] cell ADLIB:CC_CONFIG + 0.252 9.961 1 f
UART_top_0/COREABC_0/ACCUM_IN_RNIHV9C41[26]:CC net NET_CC_CONFIG440 + 0.000 9.961 f
UART_top_0/COREABC_0/ACCUM_IN_RNIHV9C41[26]:S cell ADLIB:ARI1_CC + 0.073 10.034 1 f
UART_top_0/COREABC_0/ACCUM_NEXT[26]:A net UART_top_0/COREABC_0/ACCUM_NEXT_m6[26] + 0.590 10.624 f
UART_top_0/COREABC_0/ACCUM_NEXT[26]:Y cell ADLIB:CFG3 + 0.164 10.788 2 f
UART_top_0/COREABC_0/to_logic_2.tmp_4_22[0]:C net UART_top_0/COREABC_0/ACCUM_NEXT_Z[26] + 0.305 11.093 f
UART_top_0/COREABC_0/to_logic_2.tmp_4_22[0]:Y cell ADLIB:CFG4 + 0.315 11.408 1 r
UART_top_0/COREABC_0/to_logic_2.tmp_4_29[0]:C net UART_top_0/COREABC_0/to_logic_2.tmp_4_22_Z[0] + 0.656 12.064 r
UART_top_0/COREABC_0/to_logic_2.tmp_4_29[0]:Y cell ADLIB:CFG4 + 0.168 12.232 1 r
UART_top_0/COREABC_0/to_logic_2.tmp_4[0]:D net UART_top_0/COREABC_0/to_logic_2.tmp_4_29_Z[0] + 0.085 12.317 r
UART_top_0/COREABC_0/to_logic_2.tmp_4[0]:Y cell ADLIB:CFG4 + 0.072 12.389 1 r
UART_top_0/COREABC_0/STD_ACCUM_ZERO:D net UART_top_0/COREABC_0/to_logic_2.tmp_4_Z[0] + 0.065 12.454 r
data arrival time 12.454
Data required time calculation
my_hpms_top_0/my_hpms_0/CCC_0/GL0 Clock Constraint 40.000 40.000
my_hpms_top_0/my_hpms_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 40.000 r
Clock generation + 2.783 42.783
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_net + 0.201 42.984 r
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 43.149 8 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_YNn + 0.285 43.434 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR cell ADLIB:RGB + 0.250 43.684 44 r
UART_top_0/COREABC_0/STD_ACCUM_ZERO:CLK net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1 + 0.475 44.159 r
UART_top_0/COREABC_0/STD_ACCUM_ZERO:D Library setup time ADLIB:SLE - 0.254 43.905
data required time 43.905
Operating Conditions WORST

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 RX UART_top_0/CoreUARTapb_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D 1.690 1.690 0.138 -0.963 BEST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RX
To: UART_top_0/CoreUARTapb_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D
data required time N/C
data arrival time - 1.690
slack N/C
Data arrival time calculation
RX 0.000 0.000 f
RX_ibuf/U0/U_IOPAD:PAD net RX + 0.000 0.000 f
RX_ibuf/U0/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.919 0.919 1 f
RX_ibuf/U0/U_IOINFF:A net RX_ibuf/U0/YIN1 + 0.091 1.010 f
RX_ibuf/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.103 1.113 1 f
UART_top_0/CoreUARTapb_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D net RX_c + 0.577 1.690 f
data arrival time 1.690
Data required time calculation
my_hpms_top_0/my_hpms_0/CCC_0/GL0 N/C N/C
my_hpms_top_0/my_hpms_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 1.864 N/C
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_net + 0.134 N/C r
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.110 N/C 8 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_YNn + 0.191 N/C f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.168 N/C 21 r
UART_top_0/CoreUARTapb_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:CLK net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 + 0.324 N/C r
UART_top_0/CoreUARTapb_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D Library setup time ADLIB:SLE - 0.138 N/C
Operating Conditions BEST

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 syssvc_blk_0/my_sysservice_state_0/fsm_1_Z[6]:CLK fsm[0] 6.955 11.109 11.109 WORST
Path 2 syssvc_blk_0/my_sysservice_state_0/fsm_1_Z[9]:CLK fsm[1] 6.946 11.108 11.108 WORST
Path 3 syssvc_blk_0/my_sysservice_state_0/fsm_1_Z[8]:CLK fsm[1] 6.890 11.079 11.079 WORST
Path 4 syssvc_blk_0/my_sysservice_state_0/fsm_1_Z[9]:CLK fsm[3] 6.879 11.041 11.041 WORST
Path 5 syssvc_blk_0/my_sysservice_state_0/fsm_1_Z[4]:CLK fsm[1] 6.872 11.031 11.031 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: syssvc_blk_0/my_sysservice_state_0/fsm_1_Z[6]:CLK
To: fsm[0]
data required time N/C
data arrival time - 11.109
slack N/C
Data arrival time calculation
my_hpms_top_0/my_hpms_0/CCC_0/GL0 0.000 0.000
my_hpms_top_0/my_hpms_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.783 2.783
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_net + 0.201 2.984 r
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 3.150 9 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB10:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.292 3.442 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB10:YR cell ADLIB:RGB + 0.250 3.692 68 r
syssvc_blk_0/my_sysservice_state_0/fsm_1_Z[6]:CLK net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB10_rgbr_net_1 + 0.462 4.154 r
syssvc_blk_0/my_sysservice_state_0/fsm_1_Z[6]:Q cell ADLIB:SLE + 0.087 4.241 4 r
syssvc_blk_0/CORESYSSERVICES_0/U_UserIF/m16_e_3:B net syssvc_blk_0/fsm_1[6] + 0.731 4.972 r
syssvc_blk_0/CORESYSSERVICES_0/U_UserIF/m16_e_3:Y cell ADLIB:CFG4 + 0.326 5.298 1 f
syssvc_blk_0/CORESYSSERVICES_0/U_UserIF/m16_e:C net syssvc_blk_0/CORESYSSERVICES_0/U_UserIF/m16_e_3_Z + 0.225 5.523 f
syssvc_blk_0/CORESYSSERVICES_0/U_UserIF/m16_e:Y cell ADLIB:CFG3 + 0.209 5.732 1 f
fsm_obuf[0]/U0/U_IOOUTFF:A net fsm_c[0] + 2.293 8.025 f
fsm_obuf[0]/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.330 8.355 1 f
fsm_obuf[0]/U0/U_IOPAD:D net fsm_obuf[0]/U0/DOUT + 0.088 8.443 f
fsm_obuf[0]/U0/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.666 11.109 0 f
fsm[0] net fsm[0] + 0.000 11.109 f
data arrival time 11.109
Data required time calculation
my_hpms_top_0/my_hpms_0/CCC_0/GL0 N/C N/C
my_hpms_top_0/my_hpms_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 2.783 N/C
fsm[0] N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK syssvc_blk_0/CORESYSSERVICES_0/U_fsm_ctrl/fmhaddr_o[2]:ALn 2.806 36.822 6.987 43.809 0.353 3.178 0.019 WORST
Path 2 my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK syssvc_blk_0/CORESYSSERVICES_0/U_fsm_ctrl/fmhaddr_o[13]:ALn 2.806 36.822 6.987 43.809 0.353 3.178 0.019 WORST
Path 3 my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK syssvc_blk_0/CORESYSSERVICES_0/U_UserIF/ustatus_resp_o[4]:ALn 2.818 36.822 6.999 43.821 0.353 3.178 0.007 WORST
Path 4 my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK syssvc_blk_0/CORESYSSERVICES_0/U_UserIF/ustatus_resp_o[2]:ALn 2.810 36.822 6.991 43.813 0.353 3.178 0.015 WORST
Path 5 my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK my_hpms_top_0/my_hpms_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:ALn 2.806 36.822 6.987 43.809 0.353 3.178 0.019 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK
To: syssvc_blk_0/CORESYSSERVICES_0/U_fsm_ctrl/fmhaddr_o[2]:ALn
data required time 43.809
data arrival time - 6.987
slack 36.822
Data arrival time calculation
my_hpms_top_0/my_hpms_0/CCC_0/GL0 0.000 0.000
my_hpms_top_0/my_hpms_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.783 2.783
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_net + 0.201 2.984 r
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:YNn cell ADLIB:GB + 0.165 3.149 8 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_YNn + 0.287 3.436 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.250 3.686 79 r
my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 + 0.495 4.181 r
my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep:Q cell ADLIB:SLE + 0.087 4.268 1 r
my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNID6U1:An net my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep_Z + 1.441 5.709 f
my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNID6U1:YSn cell ADLIB:GB + 0.221 5.930 9 f
my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNID6U1/U0_RGB1_RGB2:An net my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNID6U1/U0_YNn_GSouth + 0.280 6.210 f
my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNID6U1/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.250 6.460 87 r
syssvc_blk_0/CORESYSSERVICES_0/U_fsm_ctrl/fmhaddr_o[2]:ALn net my_hpms_top_0/my_hpms_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNID6U1/U0_RGB1_RGB2_rgbr_net_1 + 0.527 6.987 r
data arrival time 6.987
Data required time calculation
my_hpms_top_0/my_hpms_0/CCC_0/GL0 Clock Constraint 40.000 40.000
my_hpms_top_0/my_hpms_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 40.000 r
Clock generation + 2.783 42.783
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_net + 0.201 42.984 r
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST:YSn cell ADLIB:GB + 0.166 43.150 9 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB8:An net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_YNn_GSouth + 0.286 43.436 f
my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB8:YR cell ADLIB:RGB + 0.250 43.686 96 r
syssvc_blk_0/CORESYSSERVICES_0/U_fsm_ctrl/fmhaddr_o[2]:CLK net my_hpms_top_0/my_hpms_0/CCC_0/GL0_INST/U0_RGB1_RGB8_rgbr_net_1 + 0.476 44.162 r
syssvc_blk_0/CORESYSSERVICES_0/U_fsm_ctrl/fmhaddr_o[2]:ALn Library recovery time ADLIB:SLE - 0.353 43.809
data required time 43.809
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets