Project Settings
Project Name | top_syn | Device Name | synthesis: Microchip IGLOO2 : M2GL010TS
Implementation Name | synthesis | Top Module | top
Retiming | 0 | Resource Sharing | 1
Fanout Guide | 10000 | Disable I/O Insertion | 0
Disable Sequential Optimizations | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 196 | 340 | 0 | - | 00m:14s | - | 3/25/2021 6:21:57 PM
(premap) | Complete | 64 | 36 | 0 | 0m:03s | 0m:03s | 211MB | 3/25/2021 6:22:02 PM
(fpga_mapper) | Complete | 100 | 275 | 0 | 0m:12s | 0m:12s | 281MB | 3/25/2021 6:22:15 PM
Multi-srs Generator | Complete |  |  |  |  |  |  | 3/25/2021 6:21:58 PM
Area Summary
Carry Cells | 284 | Sequential Cells | 948
DSP Blocks (dsp_used) | 0 | I/O Cells | 10
Global Clock Buffers | 3 | RAM1K18 (v_ram) | 2
RAM64x18 (v_ram) | 2 | LUTs (total_luts) | 2495
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
my_hpms_top_0/my_hpms_0/CCC_0/GL0 | 25.0 MHz | 80.4 MHz | 27.560
my_hpms_top_0/my_hpms_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | NA | NA
Optimizations Summary
Combined Clock Conversion | 0 / 1 |  |