//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Thu Mar 25 18:21:17 2021
// Version: v12.6 12.900.20.24
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// top
module top(
    // Inputs
    DEVRST_N,
    RX,
    // Outputs
    TX,
    cntout,
    fsm
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input          DEVRST_N;
input          RX;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output         TX;
output [27:24] cntout;
output [3:0]   fsm;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [27:24] cntout_net_0;
wire           DEVRST_N;
wire   [3:0]   fsm_net_0;
wire           my_hpms_top_0_COMM_BLK_INT;
wire           my_hpms_top_0_FIC_0_CLK;
wire           my_hpms_top_0_HPMS_READY;
wire           RX;
wire   [31:0]  syssvc_blk_0_AHBL_MASTER_HADDR;
wire   [2:0]   syssvc_blk_0_AHBL_MASTER_HBURST;
wire   [31:0]  syssvc_blk_0_AHBL_MASTER_HRDATA;
wire           syssvc_blk_0_AHBL_MASTER_HREADY;
wire   [2:0]   syssvc_blk_0_AHBL_MASTER_HSIZE;
wire   [1:0]   syssvc_blk_0_AHBL_MASTER_HTRANS;
wire   [31:0]  syssvc_blk_0_AHBL_MASTER_HWDATA;
wire           syssvc_blk_0_AHBL_MASTER_HWRITE;
wire   [15:0]  syssvc_blk_0_DESIGN_VERSION_VALUE;
wire   [127:0] syssvc_blk_0_DSN_VALUE;
wire   [7:0]   syssvc_blk_0_eNVM0_DIGEST_RESP;
wire           syssvc_blk_0_SVC_DONE;
wire           TX_net_0;
wire           UART_top_0_DESIGN_VERSION_SERVICE;
wire           UART_top_0_DEVICE_SERIAL_SERVICE;
wire           UART_top_0_ENVM0_DIGEST_SERVICE;
wire           UART_top_0_START_sysservice;
wire           TX_net_1;
wire   [27:24] cntout_net_1;
wire   [3:0]   fsm_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   [3:0]   HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0_const_net_0;
wire           GND_net;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [1:0]   syssvc_blk_0_AHBL_MASTER_HRESP;
wire   [0:0]   syssvc_blk_0_AHBL_MASTER_HRESP_0_0to0;
wire           syssvc_blk_0_AHBL_MASTER_HRESP_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0_const_net_0 = 4'h0;
assign GND_net                                             = 1'b0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign TX_net_1      = TX_net_0;
assign TX            = TX_net_1;
assign cntout_net_1  = cntout_net_0;
assign cntout[27:24] = cntout_net_1;
assign fsm_net_1     = fsm_net_0;
assign fsm[3:0]      = fsm_net_1;
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign syssvc_blk_0_AHBL_MASTER_HRESP_0_0to0 = syssvc_blk_0_AHBL_MASTER_HRESP[0:0];
assign syssvc_blk_0_AHBL_MASTER_HRESP_0 = { syssvc_blk_0_AHBL_MASTER_HRESP_0_0to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------counter28
counter28 counter28_0(
        // Inputs
        .clk    ( my_hpms_top_0_FIC_0_CLK ),
        .nreset ( my_hpms_top_0_HPMS_READY ),
        // Outputs
        .cntout ( cntout_net_0 ) 
        );

//--------my_hpms_top
my_hpms_top my_hpms_top_0(
        // Inputs
        .DEVRST_N                                    ( DEVRST_N ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HWRITE_M0    ( syssvc_blk_0_AHBL_MASTER_HWRITE ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HMASTLOCK_M0 ( GND_net ), // tied to 1'b0 from definition
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HADDR_M0     ( syssvc_blk_0_AHBL_MASTER_HADDR ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HTRANS_M0    ( syssvc_blk_0_AHBL_MASTER_HTRANS ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HSIZE_M0     ( syssvc_blk_0_AHBL_MASTER_HSIZE ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HBURST_M0    ( syssvc_blk_0_AHBL_MASTER_HBURST ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0     ( HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0_const_net_0 ), // tied to 4'h0 from definition
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HWDATA_M0    ( syssvc_blk_0_AHBL_MASTER_HWDATA ),
        // Outputs
        .COMM_BLK_INT                                ( my_hpms_top_0_COMM_BLK_INT ),
        .FIC_0_CLK                                   ( my_hpms_top_0_FIC_0_CLK ),
        .HPMS_READY                                  ( my_hpms_top_0_HPMS_READY ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_M0    ( syssvc_blk_0_AHBL_MASTER_HREADY ),
        .HPMS_INT_M2F                                (  ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_M0    ( syssvc_blk_0_AHBL_MASTER_HRDATA ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_M0     ( syssvc_blk_0_AHBL_MASTER_HRESP ) 
        );

//--------syssvc_blk
syssvc_blk syssvc_blk_0(
        // Inputs
        .CLK                    ( my_hpms_top_0_FIC_0_CLK ),
        .RESETn                 ( my_hpms_top_0_HPMS_READY ),
        .COMM_BLK_INT           ( my_hpms_top_0_COMM_BLK_INT ),
        .START                  ( UART_top_0_START_sysservice ),
        .DESIGN_VERSION_SERVICE ( UART_top_0_DESIGN_VERSION_SERVICE ),
        .DEVICE_SERIAL_SERVICE  ( UART_top_0_DEVICE_SERIAL_SERVICE ),
        .ENVM0_DIGEST_SERVICE   ( UART_top_0_ENVM0_DIGEST_SERVICE ),
        .HREADY                 ( syssvc_blk_0_AHBL_MASTER_HREADY ),
        .HRESP                  ( syssvc_blk_0_AHBL_MASTER_HRESP_0 ),
        .HRDATA                 ( syssvc_blk_0_AHBL_MASTER_HRDATA ),
        // Outputs
        .SVC_DONE               ( syssvc_blk_0_SVC_DONE ),
        .HWRITE                 ( syssvc_blk_0_AHBL_MASTER_HWRITE ),
        .fsm                    ( fsm_net_0 ),
        .eNVM0_DIGEST_RESP      ( syssvc_blk_0_eNVM0_DIGEST_RESP ),
        .DESIGN_VERSION_VALUE   ( syssvc_blk_0_DESIGN_VERSION_VALUE ),
        .DSN_VALUE              ( syssvc_blk_0_DSN_VALUE ),
        .HADDR                  ( syssvc_blk_0_AHBL_MASTER_HADDR ),
        .HTRANS                 ( syssvc_blk_0_AHBL_MASTER_HTRANS ),
        .HSIZE                  ( syssvc_blk_0_AHBL_MASTER_HSIZE ),
        .HBURST                 ( syssvc_blk_0_AHBL_MASTER_HBURST ),
        .HWDATA                 ( syssvc_blk_0_AHBL_MASTER_HWDATA ) 
        );

//--------UART_top
UART_top UART_top_0(
        // Inputs
        .RX                     ( RX ),
        .NSYSRESET              ( my_hpms_top_0_HPMS_READY ),
        .PCLK                   ( my_hpms_top_0_FIC_0_CLK ),
        .SVC_DONE               ( syssvc_blk_0_SVC_DONE ),
        .eNVM0_DIGEST_RESP      ( syssvc_blk_0_eNVM0_DIGEST_RESP ),
        .DESIGN_VERSION_VALUE   ( syssvc_blk_0_DESIGN_VERSION_VALUE ),
        .DSN_VALUE              ( syssvc_blk_0_DSN_VALUE ),
        // Outputs
        .TX                     ( TX_net_0 ),
        .START_sysservice       ( UART_top_0_START_sysservice ),
        .DESIGN_VERSION_SERVICE ( UART_top_0_DESIGN_VERSION_SERVICE ),
        .ENVM0_DIGEST_SERVICE   ( UART_top_0_ENVM0_DIGEST_SERVICE ),
        .DEVICE_SERIAL_SERVICE  ( UART_top_0_DEVICE_SERIAL_SERVICE ) 
        );


endmodule
