set_device -family {IGLOO2} -die {M2GL010TS} -speed {-1}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Hex_to_ascii.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\APB_register_blk.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\acmtable.v}
 add_include_path  {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\instructnvm_bb.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\iram512x9_rtl.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\instructram.v}
 add_include_path  {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\debugblk.v}
 add_include_path  {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\instructions.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x8_rtl.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\ramblocks.v}
 add_include_path  {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Clock_gen.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\fifo_256x8.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Rx_async.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\Tx_async.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUART.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core_obfuscated\CoreUARTapb.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core_obfuscated\coreapb3.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\UART_top.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Count28.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\CCC_0\my_hpms_CCC_0_FCCC.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_HPMS\my_hpms_HPMS.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\my_hpms.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_top\my_hpms_top.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\hdl\Sysservice_state.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\syssvc_blk\syssvc_blk.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\top\top.v}
set_top_level {top}
read_sdc -component {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\CCC_0\my_hpms_CCC_0_FCCC.sdc}
read_sdc -component {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.sdc}
read_sdc -component {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\my_hpms_HPMS\my_hpms_HPMS.sdc}
read_sdc -component {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\component\work\UART_top\COREABC_0\UART_top_COREABC_0_COREABC.sdc}
derive_constraints
write_sdc {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\constraint\top_derived_constraints.sdc}
write_pdc {C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\constraint\fp\top_derived_constraints.pdc}
