//`timescale 1 ns/100 ps
module APB_register_blk(
  PCLK,
  PENABLE,
  PSEL,
  PRESETN,
  PWRITE,
  PREADY,
  PSLVERR,
  PADDR,
  PWDATA,
  PRDATA,

  START_sysservice,

 	DSN_VALUE,
	DESIGN_VERSION_VALUE,
	eNVM0_DIGEST_RESP,
	

	DEVICE_SERIAL_SERVICE,
	DESIGN_VERSION_SERVICE,
	ENVM0_DIGEST_SERVICE
  
	);


input  PCLK,PENABLE, PSEL, PRESETN, PWRITE;
input  [31:0] PADDR;
input  [31:0] PWDATA;
output reg [31:0] PRDATA;
output reg PREADY;
output PSLVERR;

input [127:0]  DSN_VALUE;
input  [15:0]  DESIGN_VERSION_VALUE;
input  [7:0]   eNVM0_DIGEST_RESP;

output reg 			START_sysservice;


output reg	 DEVICE_SERIAL_SERVICE;
output reg	 DESIGN_VERSION_SERVICE;
output reg	 ENVM0_DIGEST_SERVICE;

reg  [1:0]   fsm; //state machine register

wire [15:0]  reg3_16;
wire [31:0]  reg1_16;
wire [255:0] reg2_16;// Conver 8-bit hex to 16-bit ascii

assign PSLVERR = 1'b0;

Binary2Ascii u0 (.ascii(reg1_16[15:0]), .binary(DESIGN_VERSION_VALUE[7:0]));
Binary2Ascii u1 (.ascii(reg1_16[31:16]), .binary(DESIGN_VERSION_VALUE[15:8]));

Binary2Ascii u2 (.ascii(reg2_16[15:0]), .binary(  DSN_VALUE[7:0]));
Binary2Ascii u3 (.ascii(reg2_16[31:16]), .binary( DSN_VALUE[15:8]));
Binary2Ascii u4 (.ascii(reg2_16[47:32]), .binary( DSN_VALUE[23:16]));
Binary2Ascii u5 (.ascii(reg2_16[63:48]), .binary( DSN_VALUE[31:24]));
Binary2Ascii u6 (.ascii(reg2_16[79:64]), .binary( DSN_VALUE[39:32]));
Binary2Ascii u7 (.ascii(reg2_16[95:80]), .binary( DSN_VALUE[47:40]));
Binary2Ascii u8 (.ascii(reg2_16[111:96]), .binary(  DSN_VALUE[55:48]));
Binary2Ascii u9 (.ascii(reg2_16[127:112]), .binary( DSN_VALUE[63:56]));
Binary2Ascii u10 (.ascii(reg2_16[143:128]), .binary( DSN_VALUE[71:64]));
Binary2Ascii u11 (.ascii(reg2_16[159:144]), .binary( DSN_VALUE[79:72]));
Binary2Ascii u12 (.ascii(reg2_16[175:160]), .binary( DSN_VALUE[87:80]));
Binary2Ascii u13 (.ascii(reg2_16[191:176]), .binary( DSN_VALUE[95:88]));
Binary2Ascii u14 (.ascii(reg2_16[207:192]), .binary( DSN_VALUE[103:96]));
Binary2Ascii u15 (.ascii(reg2_16[223:208]), .binary( DSN_VALUE[111:104]));
Binary2Ascii u16 (.ascii(reg2_16[239:224]), .binary( DSN_VALUE[119:112]));
Binary2Ascii u17 (.ascii(reg2_16[255:240]), .binary( DSN_VALUE[127:120]));

Binary2Ascii u18 (.ascii(reg3_16[15:0]), .binary( eNVM0_DIGEST_RESP));

always@(posedge PCLK or negedge PRESETN)
if(~PRESETN)
  begin
     fsm <= 2'b00;
     PREADY <= 1'b1;
	PRDATA 				<= 16'h00;	
    START_sysservice 		<= 1'b0;
	DEVICE_SERIAL_SERVICE	<= 1'b0;
	DESIGN_VERSION_SERVICE <= 1'b0;
	ENVM0_DIGEST_SERVICE   <= 1'b0;
  end
else
  begin
  
  case (fsm)
     2'b00 :  begin
                  if (~PSEL)
                        begin
                          fsm <= 2'b00;
                        end
                  else        
                        begin
                          fsm <= 2'b01;
						  PREADY <= 1'b0;
						end
			  end
	
     2'b01 :  begin
                          PREADY <= 1'b0; 
                          fsm <= 2'b10; 
                          if ((PENABLE) && (PWRITE))
                          	begin 
								if (PADDR[15:0] == 16'h0000)
								begin
									START_sysservice	<= PWDATA[0];
									DEVICE_SERIAL_SERVICE 	<= PWDATA[1];
									DESIGN_VERSION_SERVICE  <= PWDATA[2];
									ENVM0_DIGEST_SERVICE   	<= PWDATA[3];
							
								end		
							end
                          if ((PENABLE) && (!PWRITE))
                          	begin 
								case (PADDR[15:0])
   									16'h9000 : begin 
               									PRDATA 	<= reg1_16[15:0];
												end
   									16'h9004 : begin 
               									PRDATA 	<= reg1_16[31:16];
            								end	
   									16'h9008 : begin 
               									PRDATA 	<= reg2_16[15:0];
            								end	
   									16'h900C : begin 
               									PRDATA 	<=  reg2_16[31:16];
            								end	
   									16'h9010 : begin 
               									PRDATA 	<= reg2_16[47:32];
            								end	
   									
									16'h9014 : begin 
               									PRDATA 	<= reg2_16[63:48];
            								end	

									16'h9018 : begin 	  

												PRDATA <= reg2_16[79:64];
											end 
									16'h901C : begin 	  

												PRDATA <= reg2_16[95:80];
											end 
									16'h9020 : begin 	  

												PRDATA <= reg2_16[111:96];
											end 
									16'h9024 : begin 	  

												PRDATA <= reg2_16[127:112];
											end

									16'h9028 : begin 
               									PRDATA 	<= reg2_16[143:128];
            								end	
   									16'h902C : begin 
               									PRDATA 	<= reg2_16[159:144];
            								end	
   									16'h9030 : begin 
               									PRDATA 	<=  reg2_16[175:160];
            								end	
   									16'h9034 : begin 
               									PRDATA 	<= reg2_16[191:176];
            								end	
   									
									16'h9038 : begin 
               									PRDATA 	<= reg2_16[207:192];
            								end	

									16'h903C : begin 	  

												PRDATA <= reg2_16[223:208];
											end 
									16'h9040 : begin 	  

												PRDATA <= reg2_16[239:224];
											end 
									16'h9044 : begin 	  

												PRDATA <= reg2_16[255:240];
											end 
									16'h9048 : begin 	  

												PRDATA <= reg3_16;
											end
									
 
									default : begin 
               									PRDATA 	<= 32'h0000_0000;
            								end	
								endcase
							end

               end

     2'b10 :  begin            
                          fsm <= 2'b00;
                          PREADY <= 1'b1; 
                        
              end


    default : fsm <= 2'b00;
  endcase
end




  
endmodule