#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file C:\igloo2_task_feb_2021\Publish_final\igl2\AC_425\Libero_Project\synthesis\run_options.txt
#--  Written on Thu Mar 25 18:21:43 2021


#project files
add_file -include "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/support.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/hdl/Hex_to_ascii.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/hdl/APB_register_blk.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/acmtable.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/instructnvm_bb.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/iram512x9_rtl.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/instructram.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/debugblk.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/instructions.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/ram128x8_smartfusion2.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/ram256x16_rtl.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/ram256x8_rtl.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/ramblocks.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/COREABC_0/rtl/vlog/core/coreabc.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/CoreUARTapb_0/rtl/vlog/core_obfuscated/Clock_gen.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/CoreUARTapb_0/rtl/vlog/core_obfuscated/fifo_256x8.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/CoreUARTapb_0/rtl/vlog/core_obfuscated/Rx_async.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/CoreUARTapb_0/rtl/vlog/core_obfuscated/Tx_async.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/CoreUARTapb_0/rtl/vlog/core_obfuscated/CoreUART.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/CoreUARTapb_0/rtl/vlog/core_obfuscated/CoreUARTapb.v"
add_file -verilog -lib COREAPB3_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core_obfuscated/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core_obfuscated/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core_obfuscated/coreapb3.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/UART_top/UART_top.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/hdl/Count28.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/my_hpms/CCC_0/my_hpms_CCC_0_FCCC.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/my_hpms/FABOSC_0/my_hpms_FABOSC_0_OSC.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/my_hpms_HPMS/my_hpms_HPMS_syn.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/my_hpms_HPMS/my_hpms_HPMS.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/my_hpms/my_hpms.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/my_hpms_top/my_hpms_top.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/hdl/Sysservice_state.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CORESYSSERVICES/3.2.102/rtl/vlog/core/CoreSysServices_AHBLMasterIF.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CORESYSSERVICES/3.2.102/rtl/vlog/core/CoreSysServices_CmdDec.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CORESYSSERVICES/3.2.102/rtl/vlog/core/CoreSysServices_FSMCtrl.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/Actel/DirectCore/CORESYSSERVICES/3.2.102/rtl/vlog/core/CoreSysServices_UserIF.v"
add_file -verilog -lib CORESYSSERVICES_LIB "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/syssvc_blk/CORESYSSERVICES_0/rtl/vlog/core/CoreSysServices.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/syssvc_blk/syssvc_blk.v"
add_file -verilog "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/igloo2_task_feb_2021/Publish_final/igl2/AC_425/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology IGLOO2
set_option -part M2GL010TS
set_option -package VF400
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip IGLOO2
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.vm"
impl -active "synthesis"
