@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1414:0:1414:5|Removing sequential instance CUARTllI of view:PrimLib.dffs(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1414:0:1414:5|Removing sequential instance CUARTl1l_1 of view:PrimLib.dffr(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1031:4:1031:9|Removing sequential instance USER_FAB_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":503:0:503:5|Removing sequential instance CUARTI01 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1235:0:1235:5|Removing sequential instance CUARTl01 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":577:0:577:5|Removing sequential instance CUARTll1 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2708:2:2708:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2771:2:2771:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2834:2:2834:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2892:27:2892:38|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":770:4:770:9|Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":784:4:784:9|Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":798:4:798:9|Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":812:4:812:9|Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":770:4:770:9|Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":784:4:784:9|Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":798:4:798:9|Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":812:4:812:9|Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":723:0:723:5|Removing sequential instance CUARTOIIl of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":723:0:723:5|Removing sequential instance CUARTIIIl of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":90:29:90:41|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN225 |Writing default property annotation file D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap.
