@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1148:0:1148:5|Removing sequential instance CUARTl1Ol of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: FX403 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":347:0:347:5|Property "block_ram" or "no_rw_check" found for RAM Rdata_mem[63:0] with specified coding style. Inferring block RAM.
@N: MF707 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":347:0:347:5|Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for Rdata_mem[63:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog)).
@N: MF179 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":153:45:153:73|Found 10 bit by 10 bit '==' comparator, 'un5_write_idle2'
@N: MF179 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":159:43:159:70|Found 10 bit by 10 bit '==' comparator, 'un3_ahb1'
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":211:0:211:5|Removing sequential instance r_xfer_size_i[0] in hierarchy view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":169:0:169:5|Removing sequential instance w_xfer_size_i[0] in hierarchy view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\tx_async.v":739:0:739:5|Removing sequential instance CUARTIO0l in hierarchy view:work.COM_Interface_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[16] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[17] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[18] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[19] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[20] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[21] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[22] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[23] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[24] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[25] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[26] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[27] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[28] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[29] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[30] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[31] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.paddr[11] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing sequential instance CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.paddr[16] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: MF179 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":509:21:509:46|Found 32 bit by 32 bit '==' comparator, 'd_state128'
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Removing sequential instance HSIZE[2] in hierarchy view:work.CoreConfigMaster_Z2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.paddr[14] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":967:0:967:5|Removing sequential instance COM_Interface_0.COREUART_0.CUARTIl1.CUARTI1Ol[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: FX404 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":147:8:147:11|Found addmux in view:work.MDDR_TA_top(verilog) inst MDDR_TA_0.ConfigMaster_0.d_bytecount_0[15:0] from MDDR_TA_0.ConfigMaster_0.un1_bytecount_16[15:0] 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: FX271 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Instance "MDDR_TA_0.ConfigMaster_0.HADDR[0]" with 5 loads replicated 1 times to improve timing 
@N: FX271 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Instance "MDDR_TA_0.ConfigMaster_0.count[1]" with 32 loads replicated 1 times to improve timing 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[0] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[1] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[2] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[3] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[4] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[5] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[6] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[28] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[29] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[30] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[31] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[32] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[33] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[34] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[35] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[0] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[1] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[2] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[3] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[4] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[5] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[6] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[28] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[29] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[30] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[31] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[32] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[33] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[34] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[35] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_en of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[0] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[1] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[2] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[3] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[4] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[5] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[6] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[7] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[8] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[9] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[10] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[11] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[12] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[13] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[14] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[15] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[16] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[17] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[18] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[19] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[20] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[21] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[22] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[23] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[24] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[25] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[26] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[27] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[28] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[29] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[30] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[31] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[32] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[33] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[34] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[35] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_en of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[0] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[1] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[2] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[3] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[4] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[5] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[6] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[7] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[8] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[9] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[10] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[11] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[12] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[13] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[14] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[15] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[16] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[17] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[18] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[19] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[20] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[21] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[22] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[23] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[24] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[25] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[26] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[27] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[28] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[29] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[30] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[31] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[32] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[33] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[34] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[35] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net MDDR_TA_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_153 
@N: FP130 |Promoting Net MDDR_TA_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_154 
@N: FP130 |Promoting Net MDDR_TA_0.HPMS_READY on CLKINT  I_155 
@N: FP130 |Promoting Net MDDR_TA_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT  I_156 
@N: FP130 |Promoting Net MDDR_TA_0.CORECONFIGP_0_APB_S_PCLK on CLKINT  I_157 
@N: FP130 |Promoting Net MDDR_TA_0_INIT_DONE on CLKINT  I_158 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
