@N|Running in 64-bit mode
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":29:7:29:12|Synthesizing module AXI_IF
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":392:17:392:25|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":400:17:400:25|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":447:17:447:25|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":455:17:455:25|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":542:24:542:29|Removing redundant assignment
@N: CL134 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":347:0:347:5|Found RAM Rdata_mem, depth=512, width=64
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":19:7:19:17|Synthesizing module CMD_Decoder
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\Control_Logic.v":20:7:20:19|Synthesizing module Control_Logic
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":30:0:30:33|Synthesizing module COM_Interface_COREUART_0_Clock_gen
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Tx_async
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":794:0:794:8|Removing redundant assignment
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Rx_async
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":654:0:654:7|Removing redundant assignment
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":1414:0:1414:5|Sharing sequential element CUARTl0l.
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_COREUART
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|Removing redundant assignment
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":377:7:377:13|Synthesizing module RAM1K18
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":367:7:367:9|Synthesizing module GND
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":371:7:371:9|Synthesizing module VCC
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v":5:7:5:35|Synthesizing module COM_Interface_TPSRAM_0_TPSRAM
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COM_Interface.v":9:7:9:19|Synthesizing module COM_Interface
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":722:7:722:9|Synthesizing module CCC
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v":5:7:5:24|Synthesizing module MDDR_TA_CCC_0_FCCC
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":24:7:24:22|Synthesizing module CoreConfigMaster
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v":29:7:29:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":28:7:28:30|Synthesizing module COREAHBLITE_SLAVEARBITER
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":30:7:30:28|Synthesizing module COREAHBLITE_SLAVESTAGE
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":31:7:31:28|Synthesizing module COREAHBLITE_MATRIX4X16
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Synthesizing module CoreAHBLite
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":29:7:29:22|Synthesizing module axi_interconnect
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v":28:7:28:18|Synthesizing module master_stage
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v":421:23:421:30|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v":965:23:965:30|Removing redundant assignment
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:31|Synthesizing module MDDR_TA_COREAXI_0_COREAXI
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v":28:7:28:17|Synthesizing module slave_stage
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1337:4:1337:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":5:7:5:26|Synthesizing module MDDR_TA_FABOSC_0_OSC
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":274:7:274:12|Synthesizing module OUTBUF
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":286:7:286:11|Synthesizing module BIBUF
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v":9:7:9:18|Synthesizing module MDDR_TA_HPMS
@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":713:7:713:14|Synthesizing module SYSRESET
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v":9:7:9:13|Synthesizing module MDDR_TA
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v":9:7:9:17|Synthesizing module MDDR_TA_top
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1031:4:1031:9|Trying to extract state machine for register sm0_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v":433:4:433:9|Trying to extract state machine for register state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Trying to extract state machine for register arbRegSMCurrentState
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Trying to extract state machine for register state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":723:0:723:5|Trying to extract state machine for register CUARTOl0
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":253:0:253:5|Trying to extract state machine for register CUARTO1ll
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\Control_Logic.v":44:0:44:5|Trying to extract state machine for register fsm
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":581:0:581:5|Trying to extract state machine for register axi_fsm_read1_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Trying to extract state machine for register axi_fsm_read_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":470:0:470:5|Trying to extract state machine for register ahb_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":415:0:415:5|Trying to extract state machine for register rt_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":357:0:357:5|Trying to extract state machine for register wt_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Trying to extract state machine for register axi_fsm_current_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":211:0:211:5|Trying to extract state machine for register r_loop_state
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":169:0:169:5|Trying to extract state machine for register w_loop_state

