@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":29:7:29:12|Synthesizing module AXI_IF
@N: CG793 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":347:0:347:7|Ignoring system task $display
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":423:17:423:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":431:17:431:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":478:17:478:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":486:17:486:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":575:24:575:29|Removing redundant assignment
@N: CL134 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":378:0:378:5|Found RAM Rdata_mem, depth=512, width=64
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":19:7:19:17|Synthesizing module CMD_Decoder
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\Control_Logic.v":20:7:20:19|Synthesizing module Control_Logic
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":30:0:30:33|Synthesizing module COM_Interface_COREUART_0_Clock_gen
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Tx_async
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":870:0:870:8|Removing redundant assignment
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Rx_async
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":750:0:750:7|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":857:0:857:8|Removing redundant assignment
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":1613:0:1613:5|Sharing sequential element CUARTI1l.
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_COREUART
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1334:0:1334:7|Removing redundant assignment
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":382:7:382:13|Synthesizing module RAM1K18
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":372:7:372:9|Synthesizing module GND
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":376:7:376:9|Synthesizing module VCC
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v":5:7:5:35|Synthesizing module COM_Interface_TPSRAM_0_TPSRAM
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COM_Interface.v":9:7:9:19|Synthesizing module COM_Interface
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":727:7:727:9|Synthesizing module CCC
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v":5:7:5:24|Synthesizing module MDDR_TA_CCC_0_FCCC
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":24:7:24:22|Synthesizing module CoreConfigMaster
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":20:7:20:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":20:7:20:30|Synthesizing module COREAHBLITE_SLAVEARBITER
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":22:7:22:28|Synthesizing module COREAHBLITE_SLAVESTAGE
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":23:7:23:28|Synthesizing module COREAHBLITE_MATRIX4X16
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Synthesizing module CoreAHBLite
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:31|Synthesizing module MDDR_TA_COREAXI_0_COREAXI
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|Synthesizing module axi_feedthrough
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.105\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.105\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":5:7:5:26|Synthesizing module MDDR_TA_FABOSC_0_OSC
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":274:7:274:12|Synthesizing module OUTBUF
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":286:7:286:11|Synthesizing module BIBUF
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v":9:7:9:18|Synthesizing module MDDR_TA_HPMS
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":718:7:718:14|Synthesizing module SYSRESET
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v":9:7:9:13|Synthesizing module MDDR_TA
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v":9:7:9:17|Synthesizing module MDDR_TA_top
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Trying to extract state machine for register arbRegSMCurrentState
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Trying to extract state machine for register state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":871:0:871:5|Trying to extract state machine for register CUARTll0
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Trying to extract state machine for register CUARTl1ll
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\Control_Logic.v":44:0:44:5|Trying to extract state machine for register fsm
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":614:0:614:5|Trying to extract state machine for register axi_fsm_read1_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Trying to extract state machine for register axi_fsm_read_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":501:0:501:5|Trying to extract state machine for register ahb_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":446:0:446:5|Trying to extract state machine for register rt_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":388:0:388:5|Trying to extract state machine for register wt_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Trying to extract state machine for register axi_fsm_current_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":225:0:225:5|Trying to extract state machine for register r_loop_state
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":183:0:183:5|Trying to extract state machine for register w_loop_state
@N|Running in 64-bit mode

