E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\m_generic.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1  -part M2GL010T  -package FBGA484  -grade -1   -maxfan 10000 -clock_globalthreshold 2 -async_globalthreshold 12 -globalthreshold 5000   -opcond COMWC  -report_path 0  -RWCheckOnRam 0    -summaryfile D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synlog\report\MDDR_TA_top_premap.xml -top_level_module  MDDR_TA_top  -oedif  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.edf  -conchk_prepass  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top_cck_prepass.rpt  -freq 400.000  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_comp.srs  -flow prepass  -gcc_prepass  -osrd  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_prem.srd  -qsap  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap  -devicelib  E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v  -ologparam  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\syntmp\MDDR_TA_top.plg  -osyn  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_prem.srd  -prjdir  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\  -prjname  MDDR_TA_top_syn  -log  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synlog\MDDR_TA_top_premap.srr 
rc:1 success:1
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.edf|o|0|0
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top_cck_prepass.rpt|o|0|0
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_comp.srs|i|1395903011|439041
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_prem.srd|o|1395903016|535783
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap|o|1395903016|64440
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v|i|1389673372|16295
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\syntmp\MDDR_TA_top.plg|o|1395903013|0
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_prem.srd|o|1395903016|535783
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synlog\MDDR_TA_top_premap.srr|o|1395903016|26082
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\m_generic.exe|i|1390193752|31452672
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin\m_generic.exe|i|1390191066|21921280
