<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COM_Interface</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./COM_Interface.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./COM_Interface_DataSheet.xml</name><userFileType>log</userFileType></file><file fileid="2"><name>./COM_Interface_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="3"><name>../../Actel/DirectCore/COREUART/5.5.101/COREUART.cxf</name><userFileType>CXF</userFileType></file><file fileid="4"><name>./COREUART_0/COM_Interface_COREUART_0_COREUART.cxf</name><userFileType>CXF</userFileType></file><file fileid="5"><name>./TPSRAM_0/COM_Interface_TPSRAM_0_TPSRAM.cxf</name><userFileType>CXF</userFileType></file><file fileid="6"><name>../../Actel/SgCore/TPSRAM/1.0.101/TPSRAM.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="7"><name>./COM_Interface.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SmartCoreDesign</category><function>SmartDesign</function><variation>SmartDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SmartCoreDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><previousType/><preDesignInGoodState>false</preDesignInGoodState><componentRef library="" name="" vendor="" version=""/><dependentModules><module id_library="DirectCore" id_name="COREUART" id_vendor="Actel" id_version="5.5.101" module_class="SpiritModule" name="COREUART" state="GOOD" type="3"/><module id_library="SgCore" id_name="TPSRAM" id_vendor="Actel" id_version="1.0.101" module_class="SpiritModule" name="TPSRAM" state="GOOD" type="3"/><module file="hdl\Control_Logic.v" module_class="HdlModule" name="Control_Logic" state="GOOD" type="2"/></dependentModules></vendorExtensions><model><signals><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RESET_N</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RX</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>TX</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>AXI_BUSY</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WEN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>COMMAND</name><direction>out</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WD</name><direction>in</direction><left>15</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WADDR</name><direction>in</direction><left>2</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>