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*                Copyright 2005 Micron Technology, Inc. All rights reserved.
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*
*	Revisions:	 baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK.  Fixed.
*									Added ROW_BITS & BA_BITS for compatibility w/our system.
*									Removed part size parameter.
*
****************************************************************************************/

    //            Parameters current with 1024Mb datasheet rev C (10/02/07)
    // 04.17.08 - Consolidated 1024Mb and T48M designs; Updated to rev E (03/08)


                                          // SYMBOL UNITS DESCRIPTION
                                          // ------ ----- -----------
`ifdef sg5                                //              Timing Parameters for -5 (CL = 3)
    parameter TAC3_MAX         =     5000.0; // tAC    ps    Access window of DQ from CK/CK#
    parameter TAC2_MAX         =     6500.0; // tAC    ps    Access window of DQ from CK/CK#
    parameter TCK              =     5000.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TCK3_MIN         =     5000.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TCK2_MIN         =    12000.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TDQSQ            =      400.0; // TDQSQ  ps    DQS-DQ skew, DQS To last DQ valid, per group, per access
    parameter THZ3_MAX         =     5000.0; // THZ    ps    Data-out high Z window from CK/CK#
    parameter THZ2_MAX         =     6500.0; // THZ    ps    Data-out high Z window from CK/CK#
    parameter TRAS             =    40000.0; // TRAS   ps    Active To Precharge command Time
    parameter TRC              =    55000.0; // TRC    ps    Active To Active/Auto Refresh command Time
    parameter TRCD             =    15000.0; // TRCD   ps    Active To Read/Write command Time
    parameter TRP              =    15000.0; // TRP    ps    Precharge command period
    parameter TRRD             =    10000.0; // TRRD   ps    Active bank a To Active bank b command Time
    parameter TWTR             =          2; // TWTR  TCK    Internal Write-to-Read command delay
    parameter TXP              =    10000.0; // TXP    ps    Exit power-down To first valid cmd *note: In data sheet This is specified as one clk, but min Tck fails before TXP on The actual part
`else `ifdef sg54                         //              Timing Parameters for -6 (CL = 3)
    parameter TAC3_MAX         =     5000.0; // TAC    ps    Access window of DQ from CK/CK#
    parameter TAC2_MAX         =     6500.0; // TAC    ps    Access window of DQ from CK/CK#
    parameter TCK              =     5400.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TCK3_MIN         =     5400.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TCK2_MIN         =    12000.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TDQSQ            =      450.0; // TDQSQ  ps    DQS-DQ skew, DQS To last DQ valid, per group, per access
    parameter THZ3_MAX         =     5000.0; // THZ    ps    Data-out high Z window from CK/CK#
    parameter THZ2_MAX         =     6500.0; // THZ    ps    Data-out high Z window from CK/CK#
    parameter TRAS             =    42000.0; // TRAS   ps    Active To Precharge command Time
    parameter TRC              =    58200.0; // TRC    ps    Active To Active/Auto Refresh command Time
    parameter TRCD             =    16200.0; // TRCD   ps    Active To Read/Write command Time
    parameter TRP              =    16200.0; // TRP    ps    Precharge command period
    parameter TRRD             =    10800.0; // TRRD   ps    Active bank a To Active bank b command Time
    parameter TWTR             =        2.0; // TWTR  TCK    Internal Write-to-Read command delay
    parameter TXP              =    10800.0; // TXP    ps    Exit power-down To first valid cmd *note: In data sheet This is specified as one clk, but min Tck fails before TXP on The actual part
`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 3)
    parameter TAC3_MAX         =     5500.0; // TAC    ps    Access window of DQ from CK/CK#
    parameter TAC2_MAX         =     6500.0; // TAC    ps    Access window of DQ from CK/CK#
    parameter TCK              =     6000.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TCK3_MIN         =     6000.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TCK2_MIN         =    12000.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TDQSQ            =      450.0; // TDQSQ  ps    DQS-DQ skew, DQS To last DQ valid, per group, per access
    parameter THZ3_MAX         =     5500.0; // THZ    ps    Data-out high Z window from CK/CK#
    parameter THZ2_MAX         =     6500.0; // THZ    ps    Data-out high Z window from CK/CK#
    parameter TRAS             =    42000.0; // TRAS   ps    Active To Precharge command Time
    parameter TRC              =    60000.0; // TRC    ps    Active To Active/Auto Refresh command Time
    parameter TRCD             =    18000.0; // TRCD   ps    Active To Read/Write command Time
    parameter TRP              =    18000.0; // TRP    ps    Precharge command period
    parameter TRRD             =    12000.0; // TRRD   ps    Active bank a To Active bank b command Time
    parameter TWTR             =        1.0; // TWTR  TCK    Internal Write-to-Read command delay
    parameter TXP              =    12000.0; // TXP    ps    Exit power-down To first valid cmd *note: In data sheet This is specified as one clk, but min Tck fails before TXP on The actual part
`else
`ifndef sg75 //avoid warnings
 `define sg75                        //              Timing Parameters for -75 (CL = 3)
`endif

    parameter TAC3_MAX         =     6000.0; // TAC    ps    Access window of DQ from CK/CK#
    parameter TAC2_MAX         =     6500.0; // TAC    ps    Access window of DQ from CK/CK#
    parameter TCK              =     7500.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TCK3_MIN         =     7500.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TCK2_MIN         =    12000.0; // TCK    ps    Nominal Clock Cycle Time
    parameter TDQSQ            =      600.0; // TDQSQ  ps    DQS-DQ skew, DQS To last DQ valid, per group, per access
    parameter THZ3_MAX         =     6000.0; // THZ    ps    Data-out high Z window from CK/CK#
    parameter THZ2_MAX         =     6500.0; // THZ    ps    Data-out high Z window from CK/CK#
    parameter TRAS             =    45000.0; // TRAS   ps    Active To Precharge command Time
    parameter TRC              =    75000.0; // TRC    ps    Active To Active/Auto Refresh command Time
    parameter TRCD             =    22500.0; // TRCD   ps    Active To Read/Write command Time
    parameter TRP              =    22500.0; // TRP    ps    Precharge command period
    parameter TRRD             =    15000.0; // TRRD   ps    Active bank a To Active bank b command Time
    parameter TWTR             =        1.0; // TWTR  TCK    Internal Write-to-Read command delay
    parameter TXP              =    15000.0; // TXP    ps    Exit power-down To first valid cmd *note: In data sheet This is specified as one clk, but min Tck fails before TXP on The actual part
`endif `endif `endif

    parameter TAC2_MIN         =   2000.0; // TAC    ps    Access window of DQ from CK/CK#
    parameter TAC3_MIN         =   2000.0; // TAC    ps    Access window of DQ from CK/CK#
    parameter TLZ              =   1000.0; // TLZ    ps    Data-out low Z window from CK/CK#
    parameter TMRD             =      2.0; // TMRD  TCK    Load Mode Register command cycle Time
    parameter TRFC             = 125000.0; // TRFC   ps    Refresh To Refresh Command interval Time
    parameter TSRC             =      1.0; // TSRC  TCK    SRR READ command To first valid command (Not Applicable for 128Mb, 256Mb Parts)
    parameter TSRR             =      2.0; // TSRR  TCK    SRR command To SRR READ command         (Not Applicable for 128Mb, 256Mb Parts)
    parameter TWR              =  15000.0; // TWR    ps    Write recovery Time
    parameter TCH_MAX          =     0.55;                 // Clk high level width
    parameter TCH_MIN          =     0.45;                 // Clk high level width
    parameter TCL_MAX          =     0.55;                 // Clk low level width
    parameter TCL_MIN          =     0.45;                 // Clk low level width
    parameter TCKE             =     1.0 ;                 // Minimum TCKE High/Low Time (in TCK's)
    parameter CL_MAX           =     3   ;                 // Maximum CAS Latency
    parameter BL_MAX           =     16  ;




     // Size Parameters based on Part Width

    parameter ADDR_BITS        =      14; // Set This parameter To control how many Address bits are used
    parameter ROW_BITS         =      14; // Set This parameter To control how many Row bits are used
    parameter DQ_BITS          =      16; // Set This parameter To control how many Data bits are used
    parameter DQS_BITS         =       2; // Set This parameter To control how many DQS bits are used
    parameter DM_BITS          =       2; // Set This parameter To control how many DM bits are used
    parameter COL_BITS         =      10; // Set This parameter To control how many Column bits are used
    parameter BA_BITS          =       2; // Set This parameter To control how many Bank bits are used




    // For use with The Multi Chip Package
`ifdef DUAL_RANK
    parameter CS_BITS          =       2; // Set This parameter To control how many Chip Select bits are used
    parameter RANKS            =       2; // Set This parameter To control how many Ranks on The mcp are used
`else 
    parameter CS_BITS          =       2; // Set This parameter To control how many Chip Select bits are used
    parameter RANKS            =       1; // Set This parameter To control how many Ranks on The mcp are used
`endif

    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set This parameter To control how many unique addresses are used
    `ifdef sg5
    parameter part_mem_bits    = 16;                   // Set This parameter To control how many unique addresses are used
    `else
    parameter part_mem_bits    = 10;                   // Set This parameter To control how many unique addresses are used
    `endif
    parameter part_size        = 1024;                 // Set This parameter To indicate part size(1024Mb, 512Mb, 256Mb, 128Mb)
    

