KEY LIBERO "11.6"
KEY CAPTURE "11.6.0.34"
KEY DEFAULT_IMPORT_LOC "C:\Actelprj\A3P_Verilog_labs\lab2"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "0"
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "IGLOO2"
KEY VendorTechnology_Die "PA4MGL1000"
KEY VendorTechnology_Package "fg484"
KEY VendorTechnology_Speed "-1"
KEY VendorTechnology_DieVoltage "1.2"
KEY VendorTechnology_PART_RANGE "COM"
KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE "100_MS"
KEY VendorTechnology_IO_DEFT_STD "LVCMOS25"
KEY VendorTechnology_OPCONR ""
KEY VendorTechnology_PLL_SUPPLY "PLL_SUPPLY_25"
KEY VendorTechnology_RAD_EXPOSURE ""
KEY VendorTechnology_RESTRICTPROBEPINS "1"
KEY VendorTechnology_RESTRICTSPIPINS "0"
KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE "0"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
KEY VendorTechnology_VCCI_1.2_VOLTR "COM"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_libero11p6_df\Libero_Project\MDDR_TA"
KEY ProjectDescription ""
KEY Pa4PeripheralNewSeq "GOOD"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "MDDR_TA_top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
COREAHBLITE_LIB
ENDLIST
LIST LIBRARY_COREAHBLITE_LIB
ALIAS=..\component\Actel\DirectCore\CoreAHBLite\5.2.100\mti\user_vlog\COREAHBLITE_LIB
COMPILE_OPTION=REFRESH_AND_COMPILE
CUSTOMPATH=false
ENDLIST
LIST FileManager
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ENDFILE
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ENDFILE
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MODULE_UNDER_TEST="testbench"
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BEGIN_USE_CONSTRAINT
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PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CFGM\1.1.100\MSS_CFGM.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="254"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_DDRB\1.0.200\MSS_DDRB.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="254"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_EDAC\1.0.101\MSS_EDAC.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="254"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_ENVM\1.0.101\MSS_ENVM.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="254"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_FIC32\1.0.100\MSS_FIC32.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="255"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_INTR\1.0.100\MSS_INTR.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="254"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_MDDR\1.0.203\MSS_MDDR.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="254"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_RESET\1.0.100\MSS_RESET.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="255"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_SECURITY\1.0.100\MSS_SECURITY.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="258"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_SWITCH\1.0.101\MSS_SWITCH.cxf,actgen_cxf"
STATE="utd"
TIME="1441784444"
SIZE="256"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COM_Interface.cxf,actgen_cxf"
STATE="utd"
TIME="1441703011"
SIZE="3736"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COM_Interface.v,hdl"
STATE="utd"
TIME="1441703009"
SIZE="5129"
PARENT="<project>\component\work\COM_Interface\COM_Interface.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf,actgen_cxf"
STATE="utd"
TIME="1441703000"
SIZE="1947"
PARENT="<project>\component\work\COM_Interface\COM_Interface.cxf"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\coreparameters.v,tb_hdl"
STATE="utd"
TIME="1441703000"
SIZE="466"
PARENT="<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf"
IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\mti\scripts\wave_vlog.do,do"
STATE="utd"
TIME="1441703000"
SIZE="1458"
PARENT="<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v,hdl"
STATE="utd"
TIME="1441703000"
SIZE="6421"
PARENT="<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v,hdl"
STATE="utd"
TIME="1441703000"
SIZE="10056"
PARENT="<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v,hdl"
STATE="utd"
TIME="1441703000"
SIZE="6356"
PARENT="<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v,hdl"
STATE="utd"
TIME="1441703000"
SIZE="10505"
PARENT="<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v,hdl"
STATE="utd"
TIME="1441703000"
SIZE="5580"
PARENT="<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\test\user\testbnch.v,tb_hdl"
STATE="utd"
TIME="1441703000"
SIZE="39124"
PARENT="<project>\component\work\COM_Interface\COREUART_0\COM_Interface_COREUART_0_COREUART.cxf"
MODULE_UNDER_TEST="testbnch"
SIMULATION_TIME="-all"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.cxf,actgen_cxf"
STATE="utd"
TIME="1441703008"
SIZE="961"
PARENT="<project>\component\work\COM_Interface\COM_Interface.cxf"
ENDFILE
VALUE "<project>\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v,hdl"
STATE="utd"
TIME="1441703008"
SIZE="2006"
PARENT="<project>\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf"
STATE="utd"
TIME="1395651508"
SIZE="437"
ENDFILE
VALUE "<project>\component\work\LPDDR_VIP_Simulation\LPDDR_VIP_Simulation.cxf,actgen_cxf"
STATE="utd"
TIME="1443522735"
SIZE="2141"
ENDFILE
VALUE "<project>\component\work\LPDDR_VIP_Simulation\LPDDR_VIP_Simulation.v,tb_hdl"
STATE="utd"
TIME="1443522735"
SIZE="5012"
PARENT="<project>\component\work\LPDDR_VIP_Simulation\LPDDR_VIP_Simulation.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.cxf,actgen_cxf"
STATE="utd"
TIME="1441783241"
SIZE="690"
PARENT="<project>\component\work\MDDR_TA\MDDR_TA.cxf"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v,hdl"
STATE="utd"
TIME="1441783241"
SIZE="1806"
PARENT="<project>\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\coreparameters.v,tb_hdl"
STATE="utd"
TIME="1401287350"
SIZE="921"
PARENT="<project>\component\work\MDDR_TA\COREAXI_0\MDDR_TA_COREAXI_0_COREAXI.cxf"
IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\MDDR_TA_COREAXI_0_COREAXI.cxf,actgen_cxf"
STATE="utd"
TIME="1441783243"
SIZE="2193"
PARENT="<project>\component\work\MDDR_TA\MDDR_TA.cxf"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v,hdl"
STATE="utd"
TIME="1441783243"
SIZE="426271"
PARENT="<project>\component\work\MDDR_TA\COREAXI_0\MDDR_TA_COREAXI_0_COREAXI.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\rtl\vlog\test\user\testbench.v,tb_hdl"
STATE="utd"
TIME="1441783243"
SIZE="372750"
PARENT="<project>\component\work\MDDR_TA\COREAXI_0\MDDR_TA_COREAXI_0_COREAXI.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.cxf,actgen_cxf"
STATE="utd"
TIME="1441783245"
SIZE="463"
PARENT="<project>\component\work\MDDR_TA\MDDR_TA.cxf"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v,hdl"
STATE="utd"
TIME="1441783245"
SIZE="789"
PARENT="<project>\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\MDDR_TA.cxf,actgen_cxf"
STATE="utd"
TIME="1442820369"
SIZE="24473"
ENDFILE
VALUE "<project>\component\work\MDDR_TA\MDDR_TA.v,hdl"
STATE="utd"
TIME="1441783246"
SIZE="113132"
PARENT="<project>\component\work\MDDR_TA\MDDR_TA.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf,actgen_cxf"
STATE="utd"
TIME="1441784455"
SIZE="33841"
ENDFILE
VALUE "<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v,hdl"
STATE="utd"
TIME="1441784453"
SIZE="79467"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_pre.v,hdl"
STATE="utd"
TIME="1441784452"
SIZE="79394"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="PRECISION_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v,hdl"
STATE="utd"
TIME="1441784452"
SIZE="66225"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MDDR_TA_top\MDDR_TA_top.cxf,actgen_cxf"
STATE="utd"
TIME="1443517970"
SIZE="7573"
ENDFILE
VALUE "<project>\component\work\MDDR_TA_top\MDDR_TA_top.v,hdl"
STATE="utd"
TIME="1443517967"
SIZE="15378"
PARENT="<project>\component\work\MDDR_TA_top\MDDR_TA_top.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\constraint\io\MDDR_TA_top.io.pdc,io_pdc"
STATE="utd"
TIME="1441965437"
SIZE="997"
ENDFILE
VALUE "<project>\constraint\MDDR_TA_top_new.sdc,sdc"
STATE="utd"
TIME="1443519247"
SIZE="620"
ENDFILE
VALUE "<project>\designer\impl1\COM_Interface.ide_des,ide_des"
STATE="utd"
TIME="1395651120"
SIZE="205"
ENDFILE
VALUE "<project>\designer\impl1\MDDR_TA_top.ide_des,ide_des"
STATE="utd"
TIME="1443444160"
SIZE="607"
ENDFILE
VALUE "<project>\hdl\AXI_IF.v,hdl"
STATE="utd"
TIME="1443517960"
SIZE="18836"
ENDFILE
VALUE "<project>\hdl\CMD_Decoder.v,hdl"
STATE="utd"
TIME="1396846094"
SIZE="3122"
ENDFILE
VALUE "<project>\hdl\Control_Logic.v,hdl"
STATE="utd"
TIME="1395726784"
SIZE="5101"
ENDFILE
VALUE "<project>\simulation\bfmtovec_compile.log,log"
STATE="utd"
TIME="1443522827"
SIZE="941"
ENDFILE
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
STATE="utd"
TIME="1429074711"
SIZE="1462"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\COM_Interface_TPSRAM_0_TPSRAM_R0C0.mem,sim"
STATE="utd"
TIME="1441703006"
SIZE="160"
PARENT="<project>\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
STATE="utd"
TIME="1395649386"
SIZE="25928"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
STATE="utd"
TIME="1395649386"
SIZE="6200"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
STATE="utd"
TIME="1395649386"
SIZE="6200"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
STATE="utd"
TIME="1395649386"
SIZE="6200"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_include.bfm,sim"
STATE="utd"
TIME="1395649386"
SIZE="12178"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\LPDDR_VIP_Simulation_presynth_simulation.log,log"
STATE="utd"
TIME="1443522711"
SIZE="3262012"
ENDFILE
VALUE "<project>\simulation\peripheral_init.bfm,sim"
STATE="utd"
TIME="1434024947"
SIZE="8450"
PARENT="<project>\component\Actel\SmartFusion2MSS\MSS\1.1.400\MSS.cxf"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
TIME="1443522812"
SIZE="6259"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1443517968"
SIZE="1633"
PARENT="<project>\component\work\MDDR_TA_top\MDDR_TA_top.cxf"
ENDFILE
VALUE "<project>\simulation\test.bfm,sim"
STATE="utd"
TIME="1441784453"
SIZE="537"
PARENT="<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.cxf"
ENDFILE
VALUE "<project>\simulation\testbench_presynth_simulation.log,log"
STATE="utd"
TIME="1443526675"
SIZE="7724385"
ENDFILE
VALUE "<project>\simulation\wave.do,do"
STATE="utd"
TIME="1395749210"
SIZE="9435"
ENDFILE
VALUE "<project>\simulation\wave_vip.do,do"
STATE="utd"
TIME="1396004762"
SIZE="10590"
ENDFILE
VALUE "<project>\stimulus\dram.v,tb_hdl"
STATE="utd"
TIME="1441703100"
SIZE="94525"
ENDFILE
VALUE "<project>\stimulus\testbench.v,tb_hdl"
STATE="utd"
TIME="1443520676"
SIZE="4250"
ENDFILE
VALUE "<project>\synthesis\MDDR_TA_top.edn,syn_edn"
STATE="utd"
TIME="1443518634"
SIZE="2163422"
ENDFILE
VALUE "<project>\synthesis\MDDR_TA_top.so,so"
STATE="utd"
TIME="1443518635"
SIZE="288"
ENDFILE
VALUE "<project>\synthesis\MDDR_TA_top.v,syn_hdl"
STATE="utd"
TIME="1443518644"
SIZE="844242"
ENDFILE
VALUE "<project>\synthesis\MDDR_TA_top_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1443518634"
SIZE="1681"
ENDFILE
VALUE "<project>\synthesis\MDDR_TA_top_syn.prj,prj"
STATE="utd"
TIME="1443518635"
SIZE="13730"
ENDFILE
VALUE "<project>\synthesis\synthesis_1\MDDR_TA_top.edn,syn_edn"
STATE="ood"
TIME="1395903034"
SIZE="2546880"
ENDFILE
VALUE "<project>\synthesis\synthesis_1\MDDR_TA_top.so,so"
STATE="utd"
TIME="1395903034"
SIZE="244"
ENDFILE
VALUE "<project>\synthesis\synthesis_1\MDDR_TA_top_sdc.sdc,syn_sdc"
STATE="ood"
TIME="1395903034"
SIZE="1669"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "COM_Interface_COREUART_0_COREUART::work"
FILE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\COM_Interface\COREUART_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\test\user\testbnch.v,tb_hdl"
VALUE "<project>\component\work\COM_Interface\COREUART_0\mti\scripts\wave_vlog.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\COM_Interface\COREUART_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\test\user\testbnch.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "COM_Interface_TPSRAM_0_TPSRAM::work"
FILE "<project>\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\COM_Interface_TPSRAM_0_TPSRAM_R0C0.mem,sim"
ENDLIST
ENDLIST
LIST "MDDR_TA::work"
FILE "<project>\component\work\MDDR_TA\MDDR_TA.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreahblite_usertb_include.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\mti\scripts\wave_user.do,do"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\coreparameters.v,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\coreparameters.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "MDDR_TA_HPMS::work"
FILE "<project>\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST "MDDR_TA_top::work"
FILE "<project>\component\work\MDDR_TA_top\MDDR_TA_top.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\stimulus\dram.v,tb_hdl"
VALUE "<project>\stimulus\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\MDDR_TA_top.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST PinReports
VALUE "<project>\designer\MDDR_TA_top\MDDR_TA_top_pinrpt_name.rpt,log"
VALUE "<project>\designer\MDDR_TA_top\MDDR_TA_top_pinrpt_number.rpt,log"
VALUE "<project>\designer\MDDR_TA_top\MDDR_TA_top_bankrpt.rpt,log"
VALUE "<project>\designer\MDDR_TA_top\MDDR_TA_top_ioff.xml,log"
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST MDDR_TA_top
VALUE "<project>\stimulus\dram.v,tb_hdl"
VALUE "<project>\stimulus\testbench.v,tb_hdl"
ENDLIST
LIST COM_Interface_COREUART_0_COREUART
VALUE "<project>\component\work\COM_Interface\COREUART_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\test\user\testbnch.v,tb_hdl"
ENDLIST
LIST MDDR_TA
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\coreparameters.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST MDDR_TA_top
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST COM_Interface_COREUART_0_COREUART
VALUE "<project>\component\work\COM_Interface\COREUART_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\COM_Interface\COREUART_0\rtl\vlog\test\user\testbnch.v,tb_hdl"
VALUE "<project>\component\work\COM_Interface\COREUART_0\mti\scripts\wave_vlog.do,do"
ENDLIST
LIST COM_Interface_TPSRAM_0_TPSRAM
VALUE "<project>\simulation\COM_Interface_TPSRAM_0_TPSRAM_R0C0.mem,sim"
ENDLIST
LIST MDDR_TA
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreahblite_usertb_include.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.100\mti\scripts\wave_user.do,do"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\work\MDDR_TA\COREAXI_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_slave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_master.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREAXI\3.0.112\coreparameters.v,tb_hdl"
ENDLIST
LIST MDDR_TA_HPMS
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=true
Type=max
RunTime=8000us
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
TimeUnit=1
TimeUnitBase=ns
Precision=100
PrecisionBase=ps
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=FALSE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="C:\Program Files (x86)\Microsemi\SoftConsole v3.4\Eclipse\eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Synplify Pro ME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\bin\synplify_pro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSim ME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_v11.6\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_v11.6\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Identify Debugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="C:\Microsemi\Libero_v11.6\Synopsys\Identify_ME_J201503M1\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "COM_Interface_COREUART_0_COREUART::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "MDDR_TA::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "MDDR_TA_top::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\MDDR_TA_top.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Run PROGRAM Action:MDDR_TA_top_PROGRAM.log
StartPage;StartPage;0
HDL;constraint\MDDR_TA_top_new.sdc;0
SmartDesign;MDDR_TA_top;0
HDL;constraint\io\MDDR_TA_top.io.pdc;0
ACTIVEVIEW;MDDR_TA_top
ENDLIST
LIST ModuleSubBlockList
LIST "axi_feedthrough::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v","FALSE","FALSE"
ENDLIST
LIST "AXI_IF::work","hdl\AXI_IF.v","FALSE","FALSE"
ENDLIST
LIST "axi_interconnect_ntom::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v","FALSE","FALSE"
SUBBLOCK "axi_matrix_m::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v","FALSE","FALSE"
SUBBLOCK "axi_matrix_s::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v","FALSE","FALSE"
ENDLIST
LIST "axi_master_stage::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v","FALSE","FALSE"
ENDLIST
LIST "axi_matrix_m::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v","FALSE","FALSE"
SUBBLOCK "axi_rd_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v","FALSE","FALSE"
SUBBLOCK "axi_wresp_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v","FALSE","FALSE"
ENDLIST
LIST "axi_matrix_s::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v","FALSE","FALSE"
SUBBLOCK "axi_ra_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v","FALSE","FALSE"
SUBBLOCK "axi_wa_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v","FALSE","FALSE"
SUBBLOCK "axi_wd_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v","FALSE","FALSE"
ENDLIST
LIST "axi_RA_ARBITER::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v","FALSE","FALSE"
ENDLIST
LIST "axi_ra_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v","FALSE","FALSE"
SUBBLOCK "axi_rdmatrix_4Mto1S::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v","FALSE","FALSE"
SUBBLOCK "axi_rdmatrix_4Mto1S_hgs_high::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v","FALSE","FALSE"
SUBBLOCK "axi_rdmatrix_4Mto1S_hgs_low::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v","FALSE","FALSE"
ENDLIST
LIST "axi_rd_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v","FALSE","FALSE"
SUBBLOCK "axi_rdmatrix_16Sto1M::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v","FALSE","FALSE"
ENDLIST
LIST "axi_rdmatrix_16Sto1M::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v","FALSE","FALSE"
ENDLIST
LIST "axi_rdmatrix_4Mto1S::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v","FALSE","FALSE"
SUBBLOCK "axi_RA_ARBITER::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v","FALSE","FALSE"
ENDLIST
LIST "axi_rdmatrix_4Mto1S_hgs_high::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v","FALSE","FALSE"
SUBBLOCK "axi_RA_ARBITER::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v","FALSE","FALSE"
ENDLIST
LIST "axi_rdmatrix_4Mto1S_hgs_low::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v","FALSE","FALSE"
SUBBLOCK "axi_RA_ARBITER::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v","FALSE","FALSE"
ENDLIST
LIST "axi_slave_stage::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v","FALSE","FALSE"
ENDLIST
LIST "axi_WA_ARBITER::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v","FALSE","FALSE"
ENDLIST
LIST "axi_wa_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v","FALSE","FALSE"
SUBBLOCK "axi_wrmatrix_4Mto1S::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v","FALSE","FALSE"
SUBBLOCK "axi_wrmatrix_4Mto1S_hgs_high::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v","FALSE","FALSE"
SUBBLOCK "axi_wrmatrix_4Mto1S_hgs_low::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v","FALSE","FALSE"
ENDLIST
LIST "axi_wd_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v","FALSE","FALSE"
ENDLIST
LIST "axi_wresp_channel::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v","FALSE","FALSE"
ENDLIST
LIST "axi_wrmatrix_4Mto1S::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v","FALSE","FALSE"
SUBBLOCK "axi_WA_ARBITER::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v","FALSE","FALSE"
ENDLIST
LIST "axi_wrmatrix_4Mto1S_hgs_high::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v","FALSE","FALSE"
SUBBLOCK "axi_WA_ARBITER::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v","FALSE","FALSE"
ENDLIST
LIST "axi_wrmatrix_4Mto1S_hgs_low::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v","FALSE","FALSE"
SUBBLOCK "axi_WA_ARBITER::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v","FALSE","FALSE"
ENDLIST
LIST "CMD_Decoder::work","hdl\CMD_Decoder.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface::work","component\work\COM_Interface\COM_Interface.v","TRUE","FALSE"
SUBBLOCK "COM_Interface_COREUART_0_COREUART::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v","FALSE","FALSE"
SUBBLOCK "COM_Interface_TPSRAM_0_TPSRAM::work","component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v","FALSE","FALSE"
SUBBLOCK "Control_Logic::work","hdl\Control_Logic.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface_COREUART_0_Clock_gen::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface_COREUART_0_COREUART::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v","FALSE","FALSE"
SUBBLOCK "COM_Interface_COREUART_0_Clock_gen::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v","FALSE","FALSE"
SUBBLOCK "COM_Interface_COREUART_0_Rx_async::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v","FALSE","FALSE"
SUBBLOCK "COM_Interface_COREUART_0_Tx_async::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v","FALSE","FALSE"
SUBBLOCK "COM_Interface_COREUART_0_fifo_256x8::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface_COREUART_0_fifo_256x8::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v","FALSE","FALSE"
SUBBLOCK "COM_Interface_COREUART_0_fifo_ctrl_128::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface_COREUART_0_fifo_ctrl_128::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v","FALSE","FALSE"
SUBBLOCK "COM_Interface_COREUART_0_ram128x8_pa4::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface_COREUART_0_ram128x8_pa4::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface_COREUART_0_Rx_async::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface_COREUART_0_Tx_async::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v","FALSE","FALSE"
ENDLIST
LIST "COM_Interface_TPSRAM_0_TPSRAM::work","component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v","FALSE","FALSE"
ENDLIST
LIST "Control_Logic::work","hdl\Control_Logic.v","FALSE","FALSE"
ENDLIST
LIST "CoreConfigMaster::work","component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v","FALSE","FALSE"
ENDLIST
LIST "CoreConfigP::work","component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v","FALSE","FALSE"
ENDLIST
LIST "CoreResetP::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v","FALSE","FALSE"
SUBBLOCK "coreresetp_pcie_hotreset::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v","FALSE","FALSE"
ENDLIST
LIST "coreresetp_pcie_hotreset::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v","FALSE","FALSE"
ENDLIST
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
ENDLIST
LIST "MDDR_TA::work","component\work\MDDR_TA\MDDR_TA.v","TRUE","FALSE"
SUBBLOCK "CoreConfigMaster::work","component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v","FALSE","FALSE"
SUBBLOCK "CoreConfigP::work","component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v","FALSE","FALSE"
SUBBLOCK "CoreResetP::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v","FALSE","FALSE"
SUBBLOCK "MDDR_TA_CCC_0_FCCC::work","component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v","FALSE","FALSE"
SUBBLOCK "MDDR_TA_COREAXI_0_COREAXI::work","component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v","FALSE","FALSE"
SUBBLOCK "MDDR_TA_FABOSC_0_OSC::work","component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v","FALSE","FALSE"
SUBBLOCK "MDDR_TA_HPMS::work","component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v","TRUE","FALSE"
SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
ENDLIST
LIST "MDDR_TA_CCC_0_FCCC::work","component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v","FALSE","FALSE"
ENDLIST
LIST "MDDR_TA_COREAXI_0_COREAXI::work","component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v","FALSE","FALSE"
SUBBLOCK "axi_feedthrough::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v","FALSE","FALSE"
SUBBLOCK "axi_interconnect_ntom::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v","FALSE","FALSE"
SUBBLOCK "axi_master_stage::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v","FALSE","FALSE"
SUBBLOCK "axi_slave_stage::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v","FALSE","FALSE"
ENDLIST
LIST "MDDR_TA_FABOSC_0_OSC::work","component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.v","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "MDDR_TA_HPMS::work","component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v","TRUE","FALSE"
SUBBLOCK "MSS_010::work","component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v","FALSE","FALSE"
ENDLIST
LIST "MDDR_TA_top::work","component\work\MDDR_TA_top\MDDR_TA_top.v","TRUE","FALSE"
SUBBLOCK "AXI_IF::work","hdl\AXI_IF.v","FALSE","FALSE"
SUBBLOCK "CMD_Decoder::work","hdl\CMD_Decoder.v","FALSE","FALSE"
SUBBLOCK "COM_Interface::work","component\work\COM_Interface\COM_Interface.v","TRUE","FALSE"
SUBBLOCK "MDDR_TA::work","component\work\MDDR_TA\MDDR_TA.v","TRUE","FALSE"
ENDLIST
LIST "MSS_010::work","component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "XTLOSC::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "XTLOSC_FAB::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "axi_master::work","component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_master.v","FALSE","TRUE"
ENDLIST
LIST "axi_master::work","component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_master.v","FALSE","TRUE"
ENDLIST
LIST "axi_master::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_master.v","FALSE","TRUE"
ENDLIST
LIST "axi_slave::work","component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_slave.v","FALSE","TRUE"
ENDLIST
LIST "axi_slave::work","component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\test\user\axi_slave.v","FALSE","TRUE"
ENDLIST
LIST "axi_slave::work","component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\test\user\axi_slave.v","FALSE","TRUE"
ENDLIST
LIST "dram::work","stimulus\dram.v","FALSE","TRUE"
ENDLIST
LIST "LPDDR_VIP_Simulation::work","component\work\LPDDR_VIP_Simulation\LPDDR_VIP_Simulation.v","TRUE","TRUE"
SUBBLOCK "MDDR_TA_top::work","component\work\MDDR_TA_top\MDDR_TA_top.v","TRUE","FALSE"
SUBBLOCK "RESET_GEN::work","component\Actel\Simulation\RESET_GEN\1.0.1\RESET_GEN.v","FALSE","TRUE"
SUBBLOCK "SimDRAM::work","component\Actel\Simulation\SimDRAM\1.0.101\data\SimDRAM.v","FALSE","TRUE"
ENDLIST
LIST "RESET_GEN::work","component\Actel\Simulation\RESET_GEN\1.0.1\RESET_GEN.v","FALSE","TRUE"
ENDLIST
LIST "SimDRAM::work","component\Actel\Simulation\SimDRAM\1.0.101\data\SimDRAM.v","FALSE","TRUE"
ENDLIST
LIST "testbench::work","component\work\MDDR_TA\COREAXI_0\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
SUBBLOCK "MDDR_TA_COREAXI_0_COREAXI::work","component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v","FALSE","FALSE"
SUBBLOCK "axi_master::work","component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_master.v","FALSE","TRUE"
SUBBLOCK "axi_slave::work","component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\test\user\axi_slave.v","FALSE","TRUE"
ENDLIST
LIST "testbench::work","stimulus\testbench.v","FALSE","TRUE"
SUBBLOCK "MDDR_TA_top::work","component\work\MDDR_TA_top\MDDR_TA_top.v","TRUE","FALSE"
SUBBLOCK "dram::work","stimulus\dram.v","FALSE","TRUE"
ENDLIST
LIST "testbnch::work","component\work\COM_Interface\COREUART_0\rtl\vlog\test\user\testbnch.v","FALSE","TRUE"
SUBBLOCK "COM_Interface_COREUART_0_COREUART::work","component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v","FALSE","FALSE"
ENDLIST
LIST "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v","FALSE","FALSE"
ENDLIST
LIST "BFM_AHBL::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbl.v","FALSE","TRUE"
SUBBLOCK "BFM_MAIN::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "BFM_AHBSLAVE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslave.v","FALSE","TRUE"
SUBBLOCK "BFM_AHBSLAVEEXT::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_AHBSLAVEEXT::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_MAIN::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
SUBBLOCK "BFM_AHBL::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbl.v","FALSE","TRUE"
SUBBLOCK "BFM_AHBSLAVE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\amba_bfm\bfm_ahbslave.v","FALSE","TRUE"
SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
LIST "MDDR_TA_top::work"
ACTIVETESTBENCH "testbench::work","stimulus\testbench.v","FALSE"
ENDLIST
ENDLIST
