quietly set ACTELLIBNAME IGLOO2
quietly set PROJECT_DIR "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_new_without_workaround/Libero_Project/MDDR_TA"
source "${PROJECT_DIR}/simulation/bfmtovec_compile.tcl";

if {[file exists presynth/_info]} {
   echo "INFO: Simulation library presynth already exists"
} else {
   file delete -force presynth 
   vlib presynth
}
vmap presynth presynth
vmap IGLOO2 "C:/Microsemi/Libero_v11.6/Designer/lib/modelsim/precompiled/vlog/smartfusion2"
vmap SmartFusion2 "C:/Microsemi/Libero_v11.6/Designer/lib/modelsim/precompiled/vlog/smartfusion2"
vmap COREAHBLITE_LIB "../component/Actel/DirectCore/CoreAHBLite/5.2.100/mti/user_vlog/COREAHBLITE_LIB"
vcom -work COREAHBLITE_LIB -force_refresh
vlog -work COREAHBLITE_LIB -force_refresh

vlog  -work presynth "${PROJECT_DIR}/hdl/AXI_IF.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/CMD_Decoder.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_g4.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/CoreUART.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/COM_Interface/TPSRAM_0/COM_Interface_TPSRAM_0_TPSRAM.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/Control_Logic.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/COM_Interface/COM_Interface.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vlog/core/coreconfigmaster.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/MDDR_TA/MDDR_TA.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/MDDR_TA_top/MDDR_TA_top.v"
vlog "+incdir+${PROJECT_DIR}/stimulus"  -work presynth "${PROJECT_DIR}/stimulus/dram.v"
vlog "+incdir+${PROJECT_DIR}/stimulus"  -work presynth "${PROJECT_DIR}/stimulus/testbench.v"

vsim -L IGLOO2 -L presynth -L COREAHBLITE_LIB  -t 1ps presynth.testbench
do "wave.do"
run 8000us
