Synopsys Verilog Compiler, version comp201503p1, Build 094R, built May 14 2015
@N|Running in 64-bit mode
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v"
@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\vlog\hypermods.v"
@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\vlog\umr_capim.v"
@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\vlog\scemi_objects.v"
@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\vlog\scemi_pipes.svh"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_smartfusion2.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\Control_Logic.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COM_Interface.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.105\osc_comps.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v"
@I::"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v"
Verilog syntax check successful!
Selecting top level module MDDR_TA_top
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v":29:7:29:12|Synthesizing module AXI_IF

	Idle_0=3'b000
	Idle_1=3'b001
	Write_0=3'b010
	Write_1=3'b011
	Read_0=3'b010
	Read_1=3'b011
	Read_2=3'b100
	Bresp_0=3'b100
	Write_2=3'b101
   Generated name = AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1

@N: CG793 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v":344:0:344:7|Ignoring system task $display
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v":420:17:420:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v":428:17:428:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v":475:17:475:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v":483:17:483:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v":572:24:572:29|Removing redundant assignment
@W: CG133 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v":572:24:572:29|No assignment to ARADDR_int
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":19:7:19:17|Synthesizing module CMD_Decoder

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\hdl\Control_Logic.v":20:7:20:19|Synthesizing module Control_Logic

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":30:0:30:33|Synthesizing module COM_Interface_COREUART_0_Clock_gen

	BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
   Generated name = COM_Interface_COREUART_0_Clock_gen_0s

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Tx_async

	TX_FIFO=32'b00000000000000000000000000000000
	CUARTlIll=32'b00000000000000000000000000000000
	CUARTOlll=32'b00000000000000000000000000000001
	CUARTIlll=32'b00000000000000000000000000000010
	CUARTllll=32'b00000000000000000000000000000011
	CUARTO0ll=32'b00000000000000000000000000000100
	CUARTI0ll=32'b00000000000000000000000000000101
	CUARTl0ll=32'b00000000000000000000000000000110
   Generated name = COM_Interface_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s

@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":794:0:794:8|Removing redundant assignment
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Rx_async

	RX_FIFO=32'b00000000000000000000000000000000
	CUARTllIl=32'b00000000000000000000000000000000
	CUARTO0Il=32'b00000000000000000000000000000001
	CUARTI0Il=32'b00000000000000000000000000000010
   Generated name = COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s

@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":654:0:654:7|Removing redundant assignment
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_COREUART

	TX_FIFO=32'b00000000000000000000000000000000
	RX_FIFO=32'b00000000000000000000000000000000
	RX_LEGACY_MODE=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000010011
	BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
   Generated name = COM_Interface_COREUART_0_COREUART_0s_0s_0s_19s_0s

@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|Removing redundant assignment
@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|No assignment to wire CUARTl0I

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|No assignment to wire CUARTO1I

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|No assignment to wire CUARTlOl

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|No assignment to wire CUARTOIl

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|No assignment to wire CUARTIll

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|No assignment to wire CUARTlll

@W: CG133 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|No assignment to CUARTOI0
@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":382:7:382:13|Synthesizing module RAM1K18

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":372:7:372:9|Synthesizing module GND

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":376:7:376:9|Synthesizing module VCC

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v":5:7:5:35|Synthesizing module COM_Interface_TPSRAM_0_TPSRAM

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COM_Interface.v":9:7:9:19|Synthesizing module COM_Interface

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":727:7:727:9|Synthesizing module CCC

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v":5:7:5:24|Synthesizing module MDDR_TA_CCC_0_FCCC

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":24:7:24:22|Synthesizing module CoreConfigMaster

	DATA_LOCATION=32'b00000000000000111110100000000000
	ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000
	ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
	S7=32'b00000000000000000000000000000111
	S8=32'b00000000000000000000000000001000
	S9=32'b00000000000000000000000000001001
	S10=32'b00000000000000000000000000001010
	S11=32'b00000000000000000000000000001011
	S12=32'b00000000000000000000000000001100
	S13=32'b00000000000000000000000000001101
	S14=32'b00000000000000000000000000001110
	S15=32'b00000000000000000000000000001111
	S16=32'b00000000000000000000000000010000
	S17=32'b00000000000000000000000000010001
	S18=32'b00000000000000000000000000010010
	S19=32'b00000000000000000000000000010011
	S20=32'b00000000000000000000000000010100
	S21=32'b00000000000000000000000000010101
	S22=32'b00000000000000000000000000010110
	P0=32'b00000000000000000000000000100000
	P1=32'b00000000000000000000000000100001
	P2=32'b00000000000000000000000000100010
	P3=32'b00000000000000000000000000100011
	P4=32'b00000000000000000000000000100100
	P5=32'b00000000000000000000000000100101
	P6=32'b00000000000000000000000000100110
	OP_COPY=7'b0000000
	OP_POLL=7'b0000010
	OP_LOAD=7'b0000011
	OP_STORE=7'b0000100
	OP_AND=7'b0000101
	OP_OR=7'b0000110
   Generated name = CoreConfigMaster_Z2

@W: CG775 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":24:7:24:22|Found Component CoreAHBLite in library COREAHBLITE_LIB
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z3

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":20:7:20:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM

	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	HRESPEXTEND=1'b1
   Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z4

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":20:7:20:30|Synthesizing module COREAHBLITE_SLAVEARBITER

	SYNC_RESET=32'b00000000000000000000000000000000
	M0EXTEND=4'b0000
	M0DONE=4'b0001
	M0LOCK=4'b0010
	M0LOCKEXTEND=4'b0011
	M1EXTEND=4'b0100
	M1DONE=4'b0101
	M1LOCK=4'b0110
	M1LOCKEXTEND=4'b0111
	M2EXTEND=4'b1000
	M2DONE=4'b1001
	M2LOCK=4'b1010
	M2LOCKEXTEND=4'b1011
	M3EXTEND=4'b1100
	M3DONE=4'b1101
	M3LOCK=4'b1110
	M3LOCKEXTEND=4'b1111
	MASTER_0=4'b0001
	MASTER_1=4'b0010
	MASTER_2=4'b0100
	MASTER_3=4'b1000
	MASTER_NONE=4'b0000
   Generated name = COREAHBLITE_SLAVEARBITER_Z5

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":22:7:22:28|Synthesizing module COREAHBLITE_SLAVESTAGE

	SYNC_RESET=32'b00000000000000000000000000000000
	TRN_IDLE=1'b0
	MASTER_NONE=4'b0000
   Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":23:7:23:28|Synthesizing module COREAHBLITE_MATRIX4X16

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Synthesizing module CoreAHBLite

	FAMILY=6'b011000
	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC_0=1'b1
	SC_1=1'b0
	SC_2=1'b1
	SC_3=1'b0
	SC_4=1'b1
	SC_5=1'b0
	SC_6=1'b1
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	M0_AHBSLOT0ENABLE=1'b0
	M0_AHBSLOT1ENABLE=1'b0
	M0_AHBSLOT2ENABLE=1'b0
	M0_AHBSLOT3ENABLE=1'b0
	M0_AHBSLOT4ENABLE=1'b0
	M0_AHBSLOT5ENABLE=1'b0
	M0_AHBSLOT6ENABLE=1'b0
	M0_AHBSLOT7ENABLE=1'b0
	M0_AHBSLOT8ENABLE=1'b0
	M0_AHBSLOT9ENABLE=1'b0
	M0_AHBSLOT10ENABLE=1'b0
	M0_AHBSLOT11ENABLE=1'b0
	M0_AHBSLOT12ENABLE=1'b0
	M0_AHBSLOT13ENABLE=1'b0
	M0_AHBSLOT14ENABLE=1'b0
	M0_AHBSLOT15ENABLE=1'b0
	M0_AHBSLOT16ENABLE=1'b1
	M1_AHBSLOT0ENABLE=1'b0
	M1_AHBSLOT1ENABLE=1'b0
	M1_AHBSLOT2ENABLE=1'b0
	M1_AHBSLOT3ENABLE=1'b0
	M1_AHBSLOT4ENABLE=1'b0
	M1_AHBSLOT5ENABLE=1'b0
	M1_AHBSLOT6ENABLE=1'b0
	M1_AHBSLOT7ENABLE=1'b0
	M1_AHBSLOT8ENABLE=1'b0
	M1_AHBSLOT9ENABLE=1'b0
	M1_AHBSLOT10ENABLE=1'b0
	M1_AHBSLOT11ENABLE=1'b0
	M1_AHBSLOT12ENABLE=1'b0
	M1_AHBSLOT13ENABLE=1'b0
	M1_AHBSLOT14ENABLE=1'b0
	M1_AHBSLOT15ENABLE=1'b0
	M1_AHBSLOT16ENABLE=1'b0
	M2_AHBSLOT0ENABLE=1'b0
	M2_AHBSLOT1ENABLE=1'b0
	M2_AHBSLOT2ENABLE=1'b0
	M2_AHBSLOT3ENABLE=1'b0
	M2_AHBSLOT4ENABLE=1'b0
	M2_AHBSLOT5ENABLE=1'b0
	M2_AHBSLOT6ENABLE=1'b0
	M2_AHBSLOT7ENABLE=1'b0
	M2_AHBSLOT8ENABLE=1'b0
	M2_AHBSLOT9ENABLE=1'b0
	M2_AHBSLOT10ENABLE=1'b0
	M2_AHBSLOT11ENABLE=1'b0
	M2_AHBSLOT12ENABLE=1'b0
	M2_AHBSLOT13ENABLE=1'b0
	M2_AHBSLOT14ENABLE=1'b0
	M2_AHBSLOT15ENABLE=1'b0
	M2_AHBSLOT16ENABLE=1'b0
	M3_AHBSLOT0ENABLE=1'b0
	M3_AHBSLOT1ENABLE=1'b0
	M3_AHBSLOT2ENABLE=1'b0
	M3_AHBSLOT3ENABLE=1'b0
	M3_AHBSLOT4ENABLE=1'b0
	M3_AHBSLOT5ENABLE=1'b0
	M3_AHBSLOT6ENABLE=1'b0
	M3_AHBSLOT7ENABLE=1'b0
	M3_AHBSLOT8ENABLE=1'b0
	M3_AHBSLOT9ENABLE=1'b0
	M3_AHBSLOT10ENABLE=1'b0
	M3_AHBSLOT11ENABLE=1'b0
	M3_AHBSLOT12ENABLE=1'b0
	M3_AHBSLOT13ENABLE=1'b0
	M3_AHBSLOT14ENABLE=1'b0
	M3_AHBSLOT15ENABLE=1'b0
	M3_AHBSLOT16ENABLE=1'b0
	SYNC_RESET=32'b00000000000000000000000000000000
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SC=16'b0000000001010101
   Generated name = CoreAHBLite_Z6

@W: CG1283 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Ignoring localparam NUM_SLAVE_SLOT on the instance and using locally defined value
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:31|Synthesizing module MDDR_TA_COREAXI_0_COREAXI

	FAMILY=32'b00000000000000000000000000011000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE16ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	NUM_SLAVE_SLOT=32'b00000000000000000000000000010000
	NUM_MASTER_SLOT=32'b00000000000000000000000000000001
	MEMSPACE=32'b00000000000000000000000000000011
	HGS_CFG=32'b00000000000000000000000000000001
	ADDR_HGS_CFG=32'b00000000000000000000000000000001
	SC_0=32'b00000000000000000000000000000000
	SC_1=32'b00000000000000000000000000000000
	SC_2=32'b00000000000000000000000000000000
	SC_3=32'b00000000000000000000000000000000
	SC_4=32'b00000000000000000000000000000000
	SC_5=32'b00000000000000000000000000000000
	SC_6=32'b00000000000000000000000000000000
	SC_7=32'b00000000000000000000000000000000
	SC_8=32'b00000000000000000000000000000000
	SC_9=32'b00000000000000000000000000000000
	SC_10=32'b00000000000000000000000000000000
	SC_11=32'b00000000000000000000000000000000
	SC_12=32'b00000000000000000000000000000000
	SC_13=32'b00000000000000000000000000000000
	SC_14=32'b00000000000000000000000000000000
	SC_15=32'b00000000000000000000000000000000
	FEED_THROUGH=32'b00000000000000000000000000000001
	INP_REG_BUF=32'b00000000000000000000000000000001
	OUT_REG_BUF=32'b00000000000000000000000000000001
	RD_ACCEPTANCE=32'b00000000000000000000000000000100
	WR_ACCEPTANCE=32'b00000000000000000000000000000100
	AWIDTH1=32'b00000000000000000000000000011000
	AWIDTH2=32'b00000000000000000000000000100000
	AXI_AWIDTH=32'b00000000000000000000000000011000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
	BASE_ID_WIDTH=32'b00000000000000000000000000000010
	SINGLE_MASTER=32'b00000000000000000000000000000001
	SINGLE_SLAVE=32'b00000000000000000000000000000000
	SINGLE_MASTER_SINGLE_SLAVE=32'b00000000000000000000000000000000
	COMB_REG=512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	SLAVE_0=17'b00000000000000001
	SLAVE_1=17'b00000000000000010
	SLAVE_2=17'b00000000000000100
	SLAVE_3=17'b00000000000001000
	SLAVE_4=17'b00000000000010000
	SLAVE_5=17'b00000000000100000
	SLAVE_6=17'b00000000001000000
	SLAVE_7=17'b00000000010000000
	SLAVE_8=17'b00000000100000000
	SLAVE_9=17'b00000001000000000
	SLAVE_A=17'b00000010000000000
	SLAVE_B=17'b00000100000000000
	SLAVE_C=17'b00001000000000000
	SLAVE_D=17'b00010000000000000
	SLAVE_E=17'b00100000000000000
	SLAVE_F=17'b01000000000000000
	SLAVE_N=17'b10000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = MDDR_TA_COREAXI_0_COREAXI_Z7

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|Synthesizing module axi_feedthrough

	AXI_AWIDTH=32'b00000000000000000000000000011000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE16ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	NUM_SLAVE_SLOT=32'b00000000000000000000000000010000
	NUM_MASTER_SLOT=32'b00000000000000000000000000000001
	MEMSPACE=32'b00000000000000000000000000000011
	HGS_CFG=32'b00000000000000000000000000000001
	ADDR_HGS_CFG=32'b00000000000000000000000000000001
	SC_0=32'b00000000000000000000000000000000
	SC_1=32'b00000000000000000000000000000000
	SC_2=32'b00000000000000000000000000000000
	SC_3=32'b00000000000000000000000000000000
	SC_4=32'b00000000000000000000000000000000
	SC_5=32'b00000000000000000000000000000000
	SC_6=32'b00000000000000000000000000000000
	SC_7=32'b00000000000000000000000000000000
	SC_8=32'b00000000000000000000000000000000
	SC_9=32'b00000000000000000000000000000000
	SC_10=32'b00000000000000000000000000000000
	SC_11=32'b00000000000000000000000000000000
	SC_12=32'b00000000000000000000000000000000
	SC_13=32'b00000000000000000000000000000000
	SC_14=32'b00000000000000000000000000000000
	SC_15=32'b00000000000000000000000000000000
	FEED_THROUGH=32'b00000000000000000000000000000001
	INP_REG_BUF=32'b00000000000000000000000000000001
	OUT_REG_BUF=32'b00000000000000000000000000000001
	WR_ACCEPTANCE=32'b00000000000000000000000000000100
	RD_ACCEPTANCE=32'b00000000000000000000000000000100
	BASE_ID_WIDTH=32'b00000000000000000000000000000010
	SYNC_RESET=32'b00000000000000000000000000000000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
   Generated name = axi_feedthrough_Z8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BREADY_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RREADY_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWADDR_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLEN_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWSIZE_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWBURST_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWLOCK_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWCACHE_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWPROT_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWVALID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WDATA_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WSTRB_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WLAST_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WVALID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARADDR_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLEN_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARSIZE_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARBURST_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARLOCK_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARCACHE_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARPROT_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARVALID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire AWREADY_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire WREADY_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire ARREADY_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BID_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BRESP_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire BVALID_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RID_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RDATA_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RRESP_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RLAST_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire RVALID_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire m0_rd_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire m1_rd_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire m2_rd_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire m3_rd_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire m0_wr_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire m1_wr_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire m2_wr_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|No assignment to wire m3_wr_end

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP

	FAMILY=32'b00000000000000000000000000010011
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	VERSION_MAJOR=32'b00000000000000000000000000000111
	VERSION_MINOR=32'b00000000000000000000000000000000
	VERSION_MAJOR_VECTOR=16'b0000000000000111
	VERSION_MINOR_VECTOR=16'b0000000000000000
	S0=2'b00
	S1=2'b01
	S2=2'b10
   Generated name = CoreConfigP_Z9

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z10

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.105\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.105\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":5:7:5:26|Synthesizing module MDDR_TA_FABOSC_0_OSC

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":274:7:274:12|Synthesizing module OUTBUF

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":286:7:286:11|Synthesizing module BIBUF

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":268:7:268:11|Synthesizing module INBUF

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v":9:7:9:18|Synthesizing module MDDR_TA_HPMS

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":718:7:718:14|Synthesizing module SYSRESET

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v":9:7:9:13|Synthesizing module MDDR_TA

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v":9:7:9:17|Synthesizing module MDDR_TA_top

@END

At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 112MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Thu Aug 06 12:43:00 2015

###########################################################]
