Selecting top level module MDDR_TA_top
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":29:7:29:12|Synthesizing module AXI_IF

	Idle_0=3'b000
	Idle_1=3'b001
	Write_0=3'b010
	Write_1=3'b011
	Read_0=3'b010
	Read_1=3'b011
	Read_2=3'b100
	Bresp_0=3'b100
	Write_2=3'b101
   Generated name = AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1

@N: CG793 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":347:0:347:7|Ignoring system task $display
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":423:17:423:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":431:17:431:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":478:17:478:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":486:17:486:25|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":575:24:575:29|Removing redundant assignment
@W: CG133 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":103:13:103:22|No assignment to ARADDR_int
@N: CL134 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":378:0:378:5|Found RAM Rdata_mem, depth=512, width=64
@A: CL282 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Feedback mux created for signal burst_cnt[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Feedback mux created for signal AWADDR[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWBURST[1] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWSIZE[2] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":501:0:501:5|Optimizing register bit WD[14] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":501:0:501:5|Optimizing register bit WD[15] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Optimizing register bit ARBURST[1] to a constant 0
@W: CL279 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":501:0:501:5|Pruning register bits 15 to 14 of WD[15:0] 

@W: CL260 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Pruning register bit 1 of AWBURST[1:0] 

@W: CL260 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Pruning register bit 2 of AWSIZE[2:0] 

@W: CL260 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Pruning register bit 1 of ARBURST[1:0] 

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":19:7:19:17|Synthesizing module CMD_Decoder

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\Control_Logic.v":20:7:20:19|Synthesizing module Control_Logic

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":30:0:30:33|Synthesizing module COM_Interface_COREUART_0_Clock_gen

	BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = COM_Interface_COREUART_0_Clock_gen_0s_0s

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Tx_async

	SYNC_RESET=32'b00000000000000000000000000000000
	TX_FIFO=32'b00000000000000000000000000000000
	CUARTIlll=32'b00000000000000000000000000000000
	CUARTllll=32'b00000000000000000000000000000001
	CUARTO0ll=32'b00000000000000000000000000000010
	CUARTI0ll=32'b00000000000000000000000000000011
	CUARTl0ll=32'b00000000000000000000000000000100
	CUARTO1ll=32'b00000000000000000000000000000101
	CUARTI1ll=32'b00000000000000000000000000000110
   Generated name = COM_Interface_COREUART_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s

@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":870:0:870:8|Removing redundant assignment
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Optimizing register bit CUARTII0l to a constant 1
@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Pruning register CUARTII0l 

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Rx_async

	SYNC_RESET=32'b00000000000000000000000000000000
	RX_FIFO=32'b00000000000000000000000000000000
	CUARTO1Ol=32'b00000000000000000000000000000000
	CUARTI1Ol=32'b00000000000000000000000000000001
	CUARTl1Ol=32'b00000000000000000000000000000010
	CUARTOOIl=32'b00000000000000000000000000000011
   Generated name = COM_Interface_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s

@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":750:0:750:7|Removing redundant assignment
@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":857:0:857:8|Removing redundant assignment
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":1613:0:1613:5|Sharing sequential element CUARTI1l.
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_COREUART

	TX_FIFO=32'b00000000000000000000000000000000
	RX_FIFO=32'b00000000000000000000000000000000
	RX_LEGACY_MODE=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000010011
	BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = COM_Interface_COREUART_0_COREUART_0s_0s_0s_19s_0s_0s

@N: CG179 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1334:0:1334:7|Removing redundant assignment
@W: CG133 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":333:0:333:7|No assignment to CUARTlI0
@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1264:0:1264:5|Pruning register CUARTO10 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1155:0:1155:5|Pruning register CUARTOl0 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1155:0:1155:5|Pruning register CUARTIl0 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1102:0:1102:5|Pruning register CUARTIOl[7:0] 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":980:0:980:5|Pruning register CUARTll0[1:0] 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":932:0:932:5|Pruning register CUARTOI0 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":932:0:932:5|Pruning register CUARTlO0 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":884:0:884:5|Pruning register CUARTOO0 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":884:0:884:5|Pruning register CUARTl1l 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":405:0:405:5|Pruning register CUARTIll 

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":382:7:382:13|Synthesizing module RAM1K18

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":372:7:372:9|Synthesizing module GND

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":376:7:376:9|Synthesizing module VCC

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v":5:7:5:35|Synthesizing module COM_Interface_TPSRAM_0_TPSRAM

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COM_Interface.v":9:7:9:19|Synthesizing module COM_Interface

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":727:7:727:9|Synthesizing module CCC

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v":5:7:5:24|Synthesizing module MDDR_TA_CCC_0_FCCC

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":24:7:24:22|Synthesizing module CoreConfigMaster

	DATA_LOCATION=32'b00000000000000111110100000000000
	ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000
	ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
	S7=32'b00000000000000000000000000000111
	S8=32'b00000000000000000000000000001000
	S9=32'b00000000000000000000000000001001
	S10=32'b00000000000000000000000000001010
	S11=32'b00000000000000000000000000001011
	S12=32'b00000000000000000000000000001100
	S13=32'b00000000000000000000000000001101
	S14=32'b00000000000000000000000000001110
	S15=32'b00000000000000000000000000001111
	S16=32'b00000000000000000000000000010000
	S17=32'b00000000000000000000000000010001
	S18=32'b00000000000000000000000000010010
	S19=32'b00000000000000000000000000010011
	S20=32'b00000000000000000000000000010100
	S21=32'b00000000000000000000000000010101
	S22=32'b00000000000000000000000000010110
	P0=32'b00000000000000000000000000100000
	P1=32'b00000000000000000000000000100001
	P2=32'b00000000000000000000000000100010
	P3=32'b00000000000000000000000000100011
	P4=32'b00000000000000000000000000100100
	P5=32'b00000000000000000000000000100101
	P6=32'b00000000000000000000000000100110
	OP_COPY=7'b0000000
	OP_POLL=7'b0000010
	OP_LOAD=7'b0000011
	OP_STORE=7'b0000100
	OP_AND=7'b0000101
	OP_OR=7'b0000110
   Generated name = CoreConfigMaster_Z2

@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Optimizing register bit HTRANS[0] to a constant 0
@W: CL260 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Pruning register bit 0 of HTRANS[1:0] 

@W: CG775 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z3

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":20:7:20:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM

	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	HRESPEXTEND=1'b1
   Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0

@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z4

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0

@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":20:7:20:30|Synthesizing module COREAHBLITE_SLAVEARBITER

	SYNC_RESET=32'b00000000000000000000000000000000
	M0EXTEND=4'b0000
	M0DONE=4'b0001
	M0LOCK=4'b0010
	M0LOCKEXTEND=4'b0011
	M1EXTEND=4'b0100
	M1DONE=4'b0101
	M1LOCK=4'b0110
	M1LOCKEXTEND=4'b0111
	M2EXTEND=4'b1000
	M2DONE=4'b1001
	M2LOCK=4'b1010
	M2LOCKEXTEND=4'b1011
	M3EXTEND=4'b1100
	M3DONE=4'b1101
	M3LOCK=4'b1110
	M3LOCKEXTEND=4'b1111
	MASTER_0=4'b0001
	MASTER_1=4'b0010
	MASTER_2=4'b0100
	MASTER_3=4'b1000
	MASTER_NONE=4'b0000
   Generated name = COREAHBLITE_SLAVEARBITER_Z5

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":22:7:22:28|Synthesizing module COREAHBLITE_SLAVESTAGE

	SYNC_RESET=32'b00000000000000000000000000000000
	TRN_IDLE=1'b0
	MASTER_NONE=4'b0000
   Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":23:7:23:28|Synthesizing module COREAHBLITE_MATRIX4X16

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Synthesizing module CoreAHBLite

	FAMILY=6'b011000
	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC_0=1'b1
	SC_1=1'b0
	SC_2=1'b1
	SC_3=1'b0
	SC_4=1'b1
	SC_5=1'b0
	SC_6=1'b1
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	M0_AHBSLOT0ENABLE=1'b0
	M0_AHBSLOT1ENABLE=1'b0
	M0_AHBSLOT2ENABLE=1'b0
	M0_AHBSLOT3ENABLE=1'b0
	M0_AHBSLOT4ENABLE=1'b0
	M0_AHBSLOT5ENABLE=1'b0
	M0_AHBSLOT6ENABLE=1'b0
	M0_AHBSLOT7ENABLE=1'b0
	M0_AHBSLOT8ENABLE=1'b0
	M0_AHBSLOT9ENABLE=1'b0
	M0_AHBSLOT10ENABLE=1'b0
	M0_AHBSLOT11ENABLE=1'b0
	M0_AHBSLOT12ENABLE=1'b0
	M0_AHBSLOT13ENABLE=1'b0
	M0_AHBSLOT14ENABLE=1'b0
	M0_AHBSLOT15ENABLE=1'b0
	M0_AHBSLOT16ENABLE=1'b1
	M1_AHBSLOT0ENABLE=1'b0
	M1_AHBSLOT1ENABLE=1'b0
	M1_AHBSLOT2ENABLE=1'b0
	M1_AHBSLOT3ENABLE=1'b0
	M1_AHBSLOT4ENABLE=1'b0
	M1_AHBSLOT5ENABLE=1'b0
	M1_AHBSLOT6ENABLE=1'b0
	M1_AHBSLOT7ENABLE=1'b0
	M1_AHBSLOT8ENABLE=1'b0
	M1_AHBSLOT9ENABLE=1'b0
	M1_AHBSLOT10ENABLE=1'b0
	M1_AHBSLOT11ENABLE=1'b0
	M1_AHBSLOT12ENABLE=1'b0
	M1_AHBSLOT13ENABLE=1'b0
	M1_AHBSLOT14ENABLE=1'b0
	M1_AHBSLOT15ENABLE=1'b0
	M1_AHBSLOT16ENABLE=1'b0
	M2_AHBSLOT0ENABLE=1'b0
	M2_AHBSLOT1ENABLE=1'b0
	M2_AHBSLOT2ENABLE=1'b0
	M2_AHBSLOT3ENABLE=1'b0
	M2_AHBSLOT4ENABLE=1'b0
	M2_AHBSLOT5ENABLE=1'b0
	M2_AHBSLOT6ENABLE=1'b0
	M2_AHBSLOT7ENABLE=1'b0
	M2_AHBSLOT8ENABLE=1'b0
	M2_AHBSLOT9ENABLE=1'b0
	M2_AHBSLOT10ENABLE=1'b0
	M2_AHBSLOT11ENABLE=1'b0
	M2_AHBSLOT12ENABLE=1'b0
	M2_AHBSLOT13ENABLE=1'b0
	M2_AHBSLOT14ENABLE=1'b0
	M2_AHBSLOT15ENABLE=1'b0
	M2_AHBSLOT16ENABLE=1'b0
	M3_AHBSLOT0ENABLE=1'b0
	M3_AHBSLOT1ENABLE=1'b0
	M3_AHBSLOT2ENABLE=1'b0
	M3_AHBSLOT3ENABLE=1'b0
	M3_AHBSLOT4ENABLE=1'b0
	M3_AHBSLOT5ENABLE=1'b0
	M3_AHBSLOT6ENABLE=1'b0
	M3_AHBSLOT7ENABLE=1'b0
	M3_AHBSLOT8ENABLE=1'b0
	M3_AHBSLOT9ENABLE=1'b0
	M3_AHBSLOT10ENABLE=1'b0
	M3_AHBSLOT11ENABLE=1'b0
	M3_AHBSLOT12ENABLE=1'b0
	M3_AHBSLOT13ENABLE=1'b0
	M3_AHBSLOT14ENABLE=1'b0
	M3_AHBSLOT15ENABLE=1'b0
	M3_AHBSLOT16ENABLE=1'b0
	SYNC_RESET=32'b00000000000000000000000000000000
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SC=16'b0000000001010101
   Generated name = CoreAHBLite_Z6

@W: CG1283 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v":1393:0:1393:8|Ignoring localparam NUM_SLAVE_SLOT on the instance and using locally defined value
@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:31|Synthesizing module MDDR_TA_COREAXI_0_COREAXI

	FAMILY=32'b00000000000000000000000000011000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE16ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	NUM_SLAVE_SLOT=32'b00000000000000000000000000010000
	NUM_MASTER_SLOT=32'b00000000000000000000000000000001
	MEMSPACE=32'b00000000000000000000000000000011
	HGS_CFG=32'b00000000000000000000000000000001
	ADDR_HGS_CFG=32'b00000000000000000000000000000001
	SC_0=32'b00000000000000000000000000000000
	SC_1=32'b00000000000000000000000000000000
	SC_2=32'b00000000000000000000000000000000
	SC_3=32'b00000000000000000000000000000000
	SC_4=32'b00000000000000000000000000000000
	SC_5=32'b00000000000000000000000000000000
	SC_6=32'b00000000000000000000000000000000
	SC_7=32'b00000000000000000000000000000000
	SC_8=32'b00000000000000000000000000000000
	SC_9=32'b00000000000000000000000000000000
	SC_10=32'b00000000000000000000000000000000
	SC_11=32'b00000000000000000000000000000000
	SC_12=32'b00000000000000000000000000000000
	SC_13=32'b00000000000000000000000000000000
	SC_14=32'b00000000000000000000000000000000
	SC_15=32'b00000000000000000000000000000000
	FEED_THROUGH=32'b00000000000000000000000000000001
	INP_REG_BUF=32'b00000000000000000000000000000001
	OUT_REG_BUF=32'b00000000000000000000000000000001
	RD_ACCEPTANCE=32'b00000000000000000000000000000100
	WR_ACCEPTANCE=32'b00000000000000000000000000000100
	AWIDTH1=32'b00000000000000000000000000011000
	AWIDTH2=32'b00000000000000000000000000100000
	AXI_AWIDTH=32'b00000000000000000000000000011000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
	BASE_ID_WIDTH=32'b00000000000000000000000000000010
	SINGLE_MASTER=32'b00000000000000000000000000000001
	SINGLE_SLAVE=32'b00000000000000000000000000000000
	SINGLE_MASTER_SINGLE_SLAVE=32'b00000000000000000000000000000000
	COMB_REG=512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	SLAVE_0=17'b00000000000000001
	SLAVE_1=17'b00000000000000010
	SLAVE_2=17'b00000000000000100
	SLAVE_3=17'b00000000000001000
	SLAVE_4=17'b00000000000010000
	SLAVE_5=17'b00000000000100000
	SLAVE_6=17'b00000000001000000
	SLAVE_7=17'b00000000010000000
	SLAVE_8=17'b00000000100000000
	SLAVE_9=17'b00000001000000000
	SLAVE_A=17'b00000010000000000
	SLAVE_B=17'b00000100000000000
	SLAVE_C=17'b00001000000000000
	SLAVE_D=17'b00010000000000000
	SLAVE_E=17'b00100000000000000
	SLAVE_F=17'b01000000000000000
	SLAVE_N=17'b10000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = MDDR_TA_COREAXI_0_COREAXI_Z7

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|Synthesizing module axi_feedthrough

	AXI_AWIDTH=32'b00000000000000000000000000011000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE16ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	NUM_SLAVE_SLOT=32'b00000000000000000000000000010000
	NUM_MASTER_SLOT=32'b00000000000000000000000000000001
	MEMSPACE=32'b00000000000000000000000000000011
	HGS_CFG=32'b00000000000000000000000000000001
	ADDR_HGS_CFG=32'b00000000000000000000000000000001
	SC_0=32'b00000000000000000000000000000000
	SC_1=32'b00000000000000000000000000000000
	SC_2=32'b00000000000000000000000000000000
	SC_3=32'b00000000000000000000000000000000
	SC_4=32'b00000000000000000000000000000000
	SC_5=32'b00000000000000000000000000000000
	SC_6=32'b00000000000000000000000000000000
	SC_7=32'b00000000000000000000000000000000
	SC_8=32'b00000000000000000000000000000000
	SC_9=32'b00000000000000000000000000000000
	SC_10=32'b00000000000000000000000000000000
	SC_11=32'b00000000000000000000000000000000
	SC_12=32'b00000000000000000000000000000000
	SC_13=32'b00000000000000000000000000000000
	SC_14=32'b00000000000000000000000000000000
	SC_15=32'b00000000000000000000000000000000
	FEED_THROUGH=32'b00000000000000000000000000000001
	INP_REG_BUF=32'b00000000000000000000000000000001
	OUT_REG_BUF=32'b00000000000000000000000000000001
	WR_ACCEPTANCE=32'b00000000000000000000000000000100
	RD_ACCEPTANCE=32'b00000000000000000000000000000100
	BASE_ID_WIDTH=32'b00000000000000000000000000000010
	SYNC_RESET=32'b00000000000000000000000000000000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
   Generated name = axi_feedthrough_Z8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:58:1307:64|No assignment to wire AWID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:23:1308:31|No assignment to wire AWADDR_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:40|No assignment to wire AWLEN_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1310:33:1310:41|No assignment to wire AWSIZE_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:33:1311:42|No assignment to wire AWBURST_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|No assignment to wire AWLOCK_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:42|No assignment to wire AWCACHE_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|No assignment to wire AWPROT_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|No assignment to wire AWVALID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1318:58:1318:63|No assignment to wire WID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1319:33:1319:40|No assignment to wire WDATA_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:33:1320:40|No assignment to wire WSTRB_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:40|No assignment to wire WLAST_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|No assignment to wire WVALID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:41|No assignment to wire BREADY_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1330:58:1330:64|No assignment to wire ARID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:23:1331:31|No assignment to wire ARADDR_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:40|No assignment to wire ARLEN_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|No assignment to wire ARSIZE_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:42|No assignment to wire ARBURST_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:41|No assignment to wire ARLOCK_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|No assignment to wire ARCACHE_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1337:33:1337:41|No assignment to wire ARPROT_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:33:1338:42|No assignment to wire ARVALID_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:41|No assignment to wire RREADY_S1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:58:1350:64|No assignment to wire AWID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:23:1351:31|No assignment to wire AWADDR_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:40|No assignment to wire AWLEN_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1353:33:1353:41|No assignment to wire AWSIZE_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:33:1354:42|No assignment to wire AWBURST_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|No assignment to wire AWLOCK_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:42|No assignment to wire AWCACHE_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|No assignment to wire AWPROT_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|No assignment to wire AWVALID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1361:58:1361:63|No assignment to wire WID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1362:33:1362:40|No assignment to wire WDATA_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:33:1363:40|No assignment to wire WSTRB_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:40|No assignment to wire WLAST_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|No assignment to wire WVALID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:41|No assignment to wire BREADY_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1373:58:1373:64|No assignment to wire ARID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:23:1374:31|No assignment to wire ARADDR_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:40|No assignment to wire ARLEN_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|No assignment to wire ARSIZE_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:42|No assignment to wire ARBURST_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:41|No assignment to wire ARLOCK_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|No assignment to wire ARCACHE_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1380:33:1380:41|No assignment to wire ARPROT_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:33:1381:42|No assignment to wire ARVALID_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:41|No assignment to wire RREADY_S2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:58:1393:64|No assignment to wire AWID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:23:1394:31|No assignment to wire AWADDR_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:40|No assignment to wire AWLEN_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1396:33:1396:41|No assignment to wire AWSIZE_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:33:1397:42|No assignment to wire AWBURST_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|No assignment to wire AWLOCK_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:42|No assignment to wire AWCACHE_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|No assignment to wire AWPROT_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|No assignment to wire AWVALID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1404:58:1404:63|No assignment to wire WID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1405:33:1405:40|No assignment to wire WDATA_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:33:1406:40|No assignment to wire WSTRB_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:40|No assignment to wire WLAST_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|No assignment to wire WVALID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:41|No assignment to wire BREADY_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1416:58:1416:64|No assignment to wire ARID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:23:1417:31|No assignment to wire ARADDR_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1418:33:1418:40|No assignment to wire ARLEN_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|No assignment to wire ARSIZE_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1420:33:1420:42|No assignment to wire ARBURST_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1421:33:1421:41|No assignment to wire ARLOCK_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1422:33:1422:42|No assignment to wire ARCACHE_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1423:33:1423:41|No assignment to wire ARPROT_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1424:33:1424:42|No assignment to wire ARVALID_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1432:33:1432:41|No assignment to wire RREADY_S3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1436:58:1436:64|No assignment to wire AWID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1437:23:1437:31|No assignment to wire AWADDR_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1438:33:1438:40|No assignment to wire AWLEN_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1439:33:1439:41|No assignment to wire AWSIZE_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1440:33:1440:42|No assignment to wire AWBURST_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1441:33:1441:41|No assignment to wire AWLOCK_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1442:33:1442:42|No assignment to wire AWCACHE_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1443:33:1443:41|No assignment to wire AWPROT_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1444:33:1444:42|No assignment to wire AWVALID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1447:58:1447:63|No assignment to wire WID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1448:33:1448:40|No assignment to wire WDATA_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:33:1449:40|No assignment to wire WSTRB_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1450:33:1450:40|No assignment to wire WLAST_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|No assignment to wire WVALID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1457:33:1457:41|No assignment to wire BREADY_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1459:58:1459:64|No assignment to wire ARID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:23:1460:31|No assignment to wire ARADDR_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1461:33:1461:40|No assignment to wire ARLEN_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|No assignment to wire ARSIZE_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1463:33:1463:42|No assignment to wire ARBURST_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1464:33:1464:41|No assignment to wire ARLOCK_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1465:33:1465:42|No assignment to wire ARCACHE_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1466:33:1466:41|No assignment to wire ARPROT_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1467:33:1467:42|No assignment to wire ARVALID_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1475:33:1475:41|No assignment to wire RREADY_S4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1479:58:1479:64|No assignment to wire AWID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1480:23:1480:31|No assignment to wire AWADDR_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1481:33:1481:40|No assignment to wire AWLEN_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1482:33:1482:41|No assignment to wire AWSIZE_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1483:33:1483:42|No assignment to wire AWBURST_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1484:33:1484:41|No assignment to wire AWLOCK_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1485:33:1485:42|No assignment to wire AWCACHE_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1486:33:1486:41|No assignment to wire AWPROT_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1487:33:1487:42|No assignment to wire AWVALID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1490:58:1490:63|No assignment to wire WID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1491:33:1491:40|No assignment to wire WDATA_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1492:33:1492:40|No assignment to wire WSTRB_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1493:33:1493:40|No assignment to wire WLAST_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|No assignment to wire WVALID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1500:33:1500:41|No assignment to wire BREADY_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1502:58:1502:64|No assignment to wire ARID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1503:23:1503:31|No assignment to wire ARADDR_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1504:33:1504:40|No assignment to wire ARLEN_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|No assignment to wire ARSIZE_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1506:33:1506:42|No assignment to wire ARBURST_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1507:33:1507:41|No assignment to wire ARLOCK_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1508:33:1508:42|No assignment to wire ARCACHE_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1509:33:1509:41|No assignment to wire ARPROT_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1510:33:1510:42|No assignment to wire ARVALID_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1518:33:1518:41|No assignment to wire RREADY_S5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1522:58:1522:64|No assignment to wire AWID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1523:23:1523:31|No assignment to wire AWADDR_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1524:33:1524:40|No assignment to wire AWLEN_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1525:33:1525:41|No assignment to wire AWSIZE_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1526:33:1526:42|No assignment to wire AWBURST_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1527:33:1527:41|No assignment to wire AWLOCK_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1528:33:1528:42|No assignment to wire AWCACHE_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1529:33:1529:41|No assignment to wire AWPROT_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1530:33:1530:42|No assignment to wire AWVALID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1533:58:1533:63|No assignment to wire WID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1534:33:1534:40|No assignment to wire WDATA_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1535:33:1535:40|No assignment to wire WSTRB_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1536:33:1536:40|No assignment to wire WLAST_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1537:33:1537:41|No assignment to wire WVALID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1543:33:1543:41|No assignment to wire BREADY_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1545:58:1545:64|No assignment to wire ARID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1546:23:1546:31|No assignment to wire ARADDR_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1547:33:1547:40|No assignment to wire ARLEN_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1548:33:1548:41|No assignment to wire ARSIZE_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1549:33:1549:42|No assignment to wire ARBURST_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1550:33:1550:41|No assignment to wire ARLOCK_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1551:33:1551:42|No assignment to wire ARCACHE_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1552:33:1552:41|No assignment to wire ARPROT_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1553:33:1553:42|No assignment to wire ARVALID_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1561:33:1561:41|No assignment to wire RREADY_S6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1565:58:1565:64|No assignment to wire AWID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1566:23:1566:31|No assignment to wire AWADDR_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1567:33:1567:40|No assignment to wire AWLEN_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1568:33:1568:41|No assignment to wire AWSIZE_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1569:33:1569:42|No assignment to wire AWBURST_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1570:33:1570:41|No assignment to wire AWLOCK_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1571:33:1571:42|No assignment to wire AWCACHE_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1572:33:1572:41|No assignment to wire AWPROT_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1573:33:1573:42|No assignment to wire AWVALID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1576:58:1576:63|No assignment to wire WID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1577:33:1577:40|No assignment to wire WDATA_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1578:33:1578:40|No assignment to wire WSTRB_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1579:33:1579:40|No assignment to wire WLAST_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1580:33:1580:41|No assignment to wire WVALID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1586:33:1586:41|No assignment to wire BREADY_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1588:58:1588:64|No assignment to wire ARID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1589:23:1589:31|No assignment to wire ARADDR_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1590:33:1590:40|No assignment to wire ARLEN_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1591:33:1591:41|No assignment to wire ARSIZE_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1592:33:1592:42|No assignment to wire ARBURST_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1593:33:1593:41|No assignment to wire ARLOCK_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1594:33:1594:42|No assignment to wire ARCACHE_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1595:33:1595:41|No assignment to wire ARPROT_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1596:33:1596:42|No assignment to wire ARVALID_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1604:33:1604:41|No assignment to wire RREADY_S7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1608:58:1608:64|No assignment to wire AWID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1609:23:1609:31|No assignment to wire AWADDR_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1610:33:1610:40|No assignment to wire AWLEN_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1611:33:1611:41|No assignment to wire AWSIZE_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1612:33:1612:42|No assignment to wire AWBURST_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1613:33:1613:41|No assignment to wire AWLOCK_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1614:33:1614:42|No assignment to wire AWCACHE_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1615:33:1615:41|No assignment to wire AWPROT_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1616:33:1616:42|No assignment to wire AWVALID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1619:58:1619:63|No assignment to wire WID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1620:33:1620:40|No assignment to wire WDATA_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1621:33:1621:40|No assignment to wire WSTRB_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1622:33:1622:40|No assignment to wire WLAST_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1623:33:1623:41|No assignment to wire WVALID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1629:33:1629:41|No assignment to wire BREADY_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1631:58:1631:64|No assignment to wire ARID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1632:23:1632:31|No assignment to wire ARADDR_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1633:33:1633:40|No assignment to wire ARLEN_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1634:33:1634:41|No assignment to wire ARSIZE_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1635:33:1635:42|No assignment to wire ARBURST_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1636:33:1636:41|No assignment to wire ARLOCK_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1637:33:1637:42|No assignment to wire ARCACHE_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1638:33:1638:41|No assignment to wire ARPROT_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1639:33:1639:42|No assignment to wire ARVALID_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1647:33:1647:41|No assignment to wire RREADY_S8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1651:58:1651:64|No assignment to wire AWID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1652:23:1652:31|No assignment to wire AWADDR_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1653:33:1653:40|No assignment to wire AWLEN_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1654:33:1654:41|No assignment to wire AWSIZE_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1655:33:1655:42|No assignment to wire AWBURST_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1656:33:1656:41|No assignment to wire AWLOCK_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1657:33:1657:42|No assignment to wire AWCACHE_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1658:33:1658:41|No assignment to wire AWPROT_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1659:33:1659:42|No assignment to wire AWVALID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1662:58:1662:63|No assignment to wire WID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1663:33:1663:40|No assignment to wire WDATA_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1664:33:1664:40|No assignment to wire WSTRB_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1665:33:1665:40|No assignment to wire WLAST_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1666:33:1666:41|No assignment to wire WVALID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1672:33:1672:41|No assignment to wire BREADY_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1674:58:1674:64|No assignment to wire ARID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1675:23:1675:31|No assignment to wire ARADDR_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1676:33:1676:40|No assignment to wire ARLEN_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1677:33:1677:41|No assignment to wire ARSIZE_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1678:33:1678:42|No assignment to wire ARBURST_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1679:33:1679:41|No assignment to wire ARLOCK_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1680:33:1680:42|No assignment to wire ARCACHE_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1681:33:1681:41|No assignment to wire ARPROT_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1682:33:1682:42|No assignment to wire ARVALID_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1690:33:1690:41|No assignment to wire RREADY_S9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1694:58:1694:65|No assignment to wire AWID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1695:23:1695:32|No assignment to wire AWADDR_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1696:33:1696:41|No assignment to wire AWLEN_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1697:33:1697:42|No assignment to wire AWSIZE_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1698:33:1698:43|No assignment to wire AWBURST_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1699:33:1699:42|No assignment to wire AWLOCK_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1700:33:1700:43|No assignment to wire AWCACHE_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1701:33:1701:42|No assignment to wire AWPROT_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1702:33:1702:43|No assignment to wire AWVALID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1705:58:1705:64|No assignment to wire WID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1706:33:1706:41|No assignment to wire WDATA_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1707:33:1707:41|No assignment to wire WSTRB_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1708:33:1708:41|No assignment to wire WLAST_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1709:33:1709:42|No assignment to wire WVALID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1715:33:1715:42|No assignment to wire BREADY_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1717:58:1717:65|No assignment to wire ARID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1718:23:1718:32|No assignment to wire ARADDR_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1719:33:1719:41|No assignment to wire ARLEN_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1720:33:1720:42|No assignment to wire ARSIZE_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1721:33:1721:43|No assignment to wire ARBURST_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1722:33:1722:42|No assignment to wire ARLOCK_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1723:33:1723:43|No assignment to wire ARCACHE_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1724:33:1724:42|No assignment to wire ARPROT_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1725:33:1725:43|No assignment to wire ARVALID_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1733:33:1733:42|No assignment to wire RREADY_S10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1737:58:1737:65|No assignment to wire AWID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1738:23:1738:32|No assignment to wire AWADDR_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1739:33:1739:41|No assignment to wire AWLEN_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1740:33:1740:42|No assignment to wire AWSIZE_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1741:33:1741:43|No assignment to wire AWBURST_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1742:33:1742:42|No assignment to wire AWLOCK_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1743:33:1743:43|No assignment to wire AWCACHE_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1744:33:1744:42|No assignment to wire AWPROT_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1745:33:1745:43|No assignment to wire AWVALID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1748:58:1748:64|No assignment to wire WID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1749:33:1749:41|No assignment to wire WDATA_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1750:33:1750:41|No assignment to wire WSTRB_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1751:33:1751:41|No assignment to wire WLAST_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1752:33:1752:42|No assignment to wire WVALID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1758:33:1758:42|No assignment to wire BREADY_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1760:58:1760:65|No assignment to wire ARID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1761:23:1761:32|No assignment to wire ARADDR_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1762:33:1762:41|No assignment to wire ARLEN_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1763:33:1763:42|No assignment to wire ARSIZE_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1764:33:1764:43|No assignment to wire ARBURST_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1765:33:1765:42|No assignment to wire ARLOCK_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1766:33:1766:43|No assignment to wire ARCACHE_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1767:33:1767:42|No assignment to wire ARPROT_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1768:33:1768:43|No assignment to wire ARVALID_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1776:33:1776:42|No assignment to wire RREADY_S11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1780:58:1780:65|No assignment to wire AWID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1781:23:1781:32|No assignment to wire AWADDR_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1782:33:1782:41|No assignment to wire AWLEN_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1783:33:1783:42|No assignment to wire AWSIZE_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1784:33:1784:43|No assignment to wire AWBURST_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1785:33:1785:42|No assignment to wire AWLOCK_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1786:33:1786:43|No assignment to wire AWCACHE_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1787:33:1787:42|No assignment to wire AWPROT_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1788:33:1788:43|No assignment to wire AWVALID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1791:58:1791:64|No assignment to wire WID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1792:33:1792:41|No assignment to wire WDATA_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1793:33:1793:41|No assignment to wire WSTRB_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1794:33:1794:41|No assignment to wire WLAST_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1795:33:1795:42|No assignment to wire WVALID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1801:33:1801:42|No assignment to wire BREADY_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1803:58:1803:65|No assignment to wire ARID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1804:23:1804:32|No assignment to wire ARADDR_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1805:33:1805:41|No assignment to wire ARLEN_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1806:33:1806:42|No assignment to wire ARSIZE_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1807:33:1807:43|No assignment to wire ARBURST_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1808:33:1808:42|No assignment to wire ARLOCK_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1809:33:1809:43|No assignment to wire ARCACHE_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1810:33:1810:42|No assignment to wire ARPROT_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1811:33:1811:43|No assignment to wire ARVALID_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1819:33:1819:42|No assignment to wire RREADY_S12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1823:58:1823:65|No assignment to wire AWID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1824:23:1824:32|No assignment to wire AWADDR_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1825:33:1825:41|No assignment to wire AWLEN_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1826:33:1826:42|No assignment to wire AWSIZE_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1827:33:1827:43|No assignment to wire AWBURST_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1828:33:1828:42|No assignment to wire AWLOCK_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1829:33:1829:43|No assignment to wire AWCACHE_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1830:33:1830:42|No assignment to wire AWPROT_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1831:33:1831:43|No assignment to wire AWVALID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1834:58:1834:64|No assignment to wire WID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1835:33:1835:41|No assignment to wire WDATA_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1836:33:1836:41|No assignment to wire WSTRB_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1837:33:1837:41|No assignment to wire WLAST_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1838:33:1838:42|No assignment to wire WVALID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1844:33:1844:42|No assignment to wire BREADY_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1846:58:1846:65|No assignment to wire ARID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1847:23:1847:32|No assignment to wire ARADDR_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1848:33:1848:41|No assignment to wire ARLEN_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1849:33:1849:42|No assignment to wire ARSIZE_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1850:33:1850:43|No assignment to wire ARBURST_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1851:33:1851:42|No assignment to wire ARLOCK_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1852:33:1852:43|No assignment to wire ARCACHE_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1853:33:1853:42|No assignment to wire ARPROT_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1854:33:1854:43|No assignment to wire ARVALID_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1862:33:1862:42|No assignment to wire RREADY_S13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1866:58:1866:65|No assignment to wire AWID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1867:23:1867:32|No assignment to wire AWADDR_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1868:33:1868:41|No assignment to wire AWLEN_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1869:33:1869:42|No assignment to wire AWSIZE_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1870:33:1870:43|No assignment to wire AWBURST_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1871:33:1871:42|No assignment to wire AWLOCK_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1872:33:1872:43|No assignment to wire AWCACHE_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1873:33:1873:42|No assignment to wire AWPROT_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1874:33:1874:43|No assignment to wire AWVALID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1877:58:1877:64|No assignment to wire WID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1878:33:1878:41|No assignment to wire WDATA_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1879:33:1879:41|No assignment to wire WSTRB_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1880:33:1880:41|No assignment to wire WLAST_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1881:33:1881:42|No assignment to wire WVALID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1887:33:1887:42|No assignment to wire BREADY_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1889:58:1889:65|No assignment to wire ARID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1890:23:1890:32|No assignment to wire ARADDR_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1891:33:1891:41|No assignment to wire ARLEN_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1892:33:1892:42|No assignment to wire ARSIZE_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1893:33:1893:43|No assignment to wire ARBURST_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1894:33:1894:42|No assignment to wire ARLOCK_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1895:33:1895:43|No assignment to wire ARCACHE_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1896:33:1896:42|No assignment to wire ARPROT_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1897:33:1897:43|No assignment to wire ARVALID_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1905:33:1905:42|No assignment to wire RREADY_S14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1909:58:1909:65|No assignment to wire AWID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1910:23:1910:32|No assignment to wire AWADDR_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1911:33:1911:41|No assignment to wire AWLEN_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1912:33:1912:42|No assignment to wire AWSIZE_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1913:33:1913:43|No assignment to wire AWBURST_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1914:33:1914:42|No assignment to wire AWLOCK_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1915:33:1915:43|No assignment to wire AWCACHE_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1916:33:1916:42|No assignment to wire AWPROT_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1917:33:1917:43|No assignment to wire AWVALID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1920:58:1920:64|No assignment to wire WID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1921:33:1921:41|No assignment to wire WDATA_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1922:33:1922:41|No assignment to wire WSTRB_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1923:33:1923:41|No assignment to wire WLAST_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1924:33:1924:42|No assignment to wire WVALID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1930:33:1930:42|No assignment to wire BREADY_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1932:58:1932:65|No assignment to wire ARID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1933:23:1933:32|No assignment to wire ARADDR_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1934:33:1934:41|No assignment to wire ARLEN_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1935:33:1935:42|No assignment to wire ARSIZE_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1936:33:1936:43|No assignment to wire ARBURST_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1937:33:1937:42|No assignment to wire ARLOCK_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1938:33:1938:43|No assignment to wire ARCACHE_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1939:33:1939:42|No assignment to wire ARPROT_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1940:33:1940:43|No assignment to wire ARVALID_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1948:33:1948:42|No assignment to wire RREADY_S15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1952:58:1952:65|No assignment to wire AWID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1953:23:1953:32|No assignment to wire AWADDR_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1954:33:1954:41|No assignment to wire AWLEN_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1955:33:1955:42|No assignment to wire AWSIZE_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1956:33:1956:43|No assignment to wire AWBURST_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1957:33:1957:42|No assignment to wire AWLOCK_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1958:33:1958:43|No assignment to wire AWCACHE_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1959:33:1959:42|No assignment to wire AWPROT_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1960:33:1960:43|No assignment to wire AWVALID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1963:58:1963:64|No assignment to wire WID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1964:33:1964:41|No assignment to wire WDATA_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1965:33:1965:41|No assignment to wire WSTRB_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1966:33:1966:41|No assignment to wire WLAST_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1967:33:1967:42|No assignment to wire WVALID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1973:33:1973:42|No assignment to wire BREADY_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1975:58:1975:65|No assignment to wire ARID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1976:23:1976:32|No assignment to wire ARADDR_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1977:33:1977:41|No assignment to wire ARLEN_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1978:33:1978:42|No assignment to wire ARSIZE_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1979:33:1979:43|No assignment to wire ARBURST_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1980:33:1980:42|No assignment to wire ARLOCK_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1981:33:1981:43|No assignment to wire ARCACHE_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1982:33:1982:42|No assignment to wire ARPROT_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1983:33:1983:43|No assignment to wire ARVALID_S16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1996:33:1996:43|No assignment to wire AWREADY_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1997:33:1997:43|No assignment to wire AWREADY_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1998:33:1998:43|No assignment to wire AWREADY_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1999:33:1999:43|No assignment to wire AWREADY_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2000:33:2000:42|No assignment to wire WREADY_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2001:33:2001:42|No assignment to wire WREADY_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2002:33:2002:42|No assignment to wire WREADY_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2003:33:2003:42|No assignment to wire WREADY_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2004:33:2004:43|No assignment to wire ARREADY_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2005:33:2005:43|No assignment to wire ARREADY_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2006:33:2006:43|No assignment to wire ARREADY_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2007:33:2007:43|No assignment to wire ARREADY_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2009:33:2009:42|No assignment to wire BREADY_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2010:33:2010:42|No assignment to wire BREADY_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2011:33:2011:42|No assignment to wire BREADY_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2012:33:2012:42|No assignment to wire BREADY_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2013:33:2013:42|No assignment to wire RREADY_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2014:33:2014:42|No assignment to wire RREADY_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2015:33:2015:42|No assignment to wire RREADY_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2016:33:2016:42|No assignment to wire RREADY_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2019:39:2019:48|No assignment to wire BVALID_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2020:39:2020:48|No assignment to wire BVALID_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2021:39:2021:48|No assignment to wire BVALID_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2022:39:2022:48|No assignment to wire BVALID_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2025:56:2025:63|No assignment to wire AWID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2026:21:2026:30|No assignment to wire AWADDR_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2027:31:2027:39|No assignment to wire AWLEN_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2028:31:2028:40|No assignment to wire AWSIZE_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2029:31:2029:41|No assignment to wire AWBURST_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2030:31:2030:40|No assignment to wire AWLOCK_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2031:31:2031:41|No assignment to wire AWCACHE_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2032:31:2032:40|No assignment to wire AWPROT_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2033:31:2033:41|No assignment to wire AWVALID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2036:56:2036:62|No assignment to wire WID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2037:31:2037:39|No assignment to wire WDATA_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2038:31:2038:39|No assignment to wire WSTRB_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2039:31:2039:39|No assignment to wire WLAST_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2040:31:2040:40|No assignment to wire WVALID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2042:31:2042:40|No assignment to wire BREADY_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2044:56:2044:63|No assignment to wire ARID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2045:21:2045:30|No assignment to wire ARADDR_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2046:31:2046:39|No assignment to wire ARLEN_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2047:31:2047:40|No assignment to wire ARSIZE_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2048:31:2048:41|No assignment to wire ARBURST_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2049:31:2049:40|No assignment to wire ARLOCK_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2050:31:2050:41|No assignment to wire ARCACHE_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2051:31:2051:40|No assignment to wire ARPROT_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2052:31:2052:41|No assignment to wire ARVALID_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2055:32:2055:41|No assignment to wire RREADY_IS0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2057:56:2057:63|No assignment to wire AWID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2058:21:2058:30|No assignment to wire AWADDR_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2059:31:2059:39|No assignment to wire AWLEN_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2060:31:2060:40|No assignment to wire AWSIZE_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2061:31:2061:41|No assignment to wire AWBURST_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2062:31:2062:40|No assignment to wire AWLOCK_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2063:31:2063:41|No assignment to wire AWCACHE_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2064:31:2064:40|No assignment to wire AWPROT_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2065:31:2065:41|No assignment to wire AWVALID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2068:56:2068:62|No assignment to wire WID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2069:31:2069:39|No assignment to wire WDATA_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2070:31:2070:39|No assignment to wire WSTRB_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2071:31:2071:39|No assignment to wire WLAST_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2072:31:2072:40|No assignment to wire WVALID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2074:31:2074:40|No assignment to wire BREADY_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2076:56:2076:63|No assignment to wire ARID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2077:21:2077:30|No assignment to wire ARADDR_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2078:31:2078:39|No assignment to wire ARLEN_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2079:31:2079:40|No assignment to wire ARSIZE_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2080:31:2080:41|No assignment to wire ARBURST_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2081:31:2081:40|No assignment to wire ARLOCK_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2082:31:2082:41|No assignment to wire ARCACHE_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2083:31:2083:40|No assignment to wire ARPROT_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2084:31:2084:41|No assignment to wire ARVALID_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2087:32:2087:41|No assignment to wire RREADY_IS1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2089:56:2089:63|No assignment to wire AWID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2090:21:2090:30|No assignment to wire AWADDR_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2091:31:2091:39|No assignment to wire AWLEN_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2092:31:2092:40|No assignment to wire AWSIZE_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2093:31:2093:41|No assignment to wire AWBURST_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2094:31:2094:40|No assignment to wire AWLOCK_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2095:31:2095:41|No assignment to wire AWCACHE_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2096:31:2096:40|No assignment to wire AWPROT_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2097:31:2097:41|No assignment to wire AWVALID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2100:56:2100:62|No assignment to wire WID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2101:31:2101:39|No assignment to wire WDATA_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2102:31:2102:39|No assignment to wire WSTRB_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2103:31:2103:39|No assignment to wire WLAST_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2104:31:2104:40|No assignment to wire WVALID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2106:31:2106:40|No assignment to wire BREADY_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2108:56:2108:63|No assignment to wire ARID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2109:21:2109:30|No assignment to wire ARADDR_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2110:31:2110:39|No assignment to wire ARLEN_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2111:31:2111:40|No assignment to wire ARSIZE_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2112:31:2112:41|No assignment to wire ARBURST_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2113:31:2113:40|No assignment to wire ARLOCK_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2114:31:2114:41|No assignment to wire ARCACHE_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2115:31:2115:40|No assignment to wire ARPROT_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2116:31:2116:41|No assignment to wire ARVALID_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2119:32:2119:41|No assignment to wire RREADY_IS2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2121:56:2121:63|No assignment to wire AWID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2122:21:2122:30|No assignment to wire AWADDR_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2123:31:2123:39|No assignment to wire AWLEN_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2124:31:2124:40|No assignment to wire AWSIZE_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2125:31:2125:41|No assignment to wire AWBURST_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2126:31:2126:40|No assignment to wire AWLOCK_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2127:31:2127:41|No assignment to wire AWCACHE_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2128:31:2128:40|No assignment to wire AWPROT_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2129:31:2129:41|No assignment to wire AWVALID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2132:56:2132:62|No assignment to wire WID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2133:31:2133:39|No assignment to wire WDATA_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2134:31:2134:39|No assignment to wire WSTRB_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2135:31:2135:39|No assignment to wire WLAST_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2136:31:2136:40|No assignment to wire WVALID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2138:31:2138:40|No assignment to wire BREADY_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2140:56:2140:63|No assignment to wire ARID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2141:21:2141:30|No assignment to wire ARADDR_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2142:31:2142:39|No assignment to wire ARLEN_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2143:31:2143:40|No assignment to wire ARSIZE_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2144:31:2144:41|No assignment to wire ARBURST_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2145:31:2145:40|No assignment to wire ARLOCK_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2146:31:2146:41|No assignment to wire ARCACHE_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2147:31:2147:40|No assignment to wire ARPROT_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2148:31:2148:41|No assignment to wire ARVALID_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2151:32:2151:41|No assignment to wire RREADY_IS3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2153:56:2153:63|No assignment to wire AWID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2154:21:2154:30|No assignment to wire AWADDR_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2155:31:2155:39|No assignment to wire AWLEN_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2156:31:2156:40|No assignment to wire AWSIZE_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2157:31:2157:41|No assignment to wire AWBURST_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2158:31:2158:40|No assignment to wire AWLOCK_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2159:31:2159:41|No assignment to wire AWCACHE_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2160:31:2160:40|No assignment to wire AWPROT_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2161:31:2161:41|No assignment to wire AWVALID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2164:56:2164:62|No assignment to wire WID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2165:31:2165:39|No assignment to wire WDATA_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2166:31:2166:39|No assignment to wire WSTRB_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2167:31:2167:39|No assignment to wire WLAST_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2168:31:2168:40|No assignment to wire WVALID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2170:31:2170:40|No assignment to wire BREADY_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2172:56:2172:63|No assignment to wire ARID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2173:21:2173:30|No assignment to wire ARADDR_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2174:31:2174:39|No assignment to wire ARLEN_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2175:31:2175:40|No assignment to wire ARSIZE_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2176:31:2176:41|No assignment to wire ARBURST_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2177:31:2177:40|No assignment to wire ARLOCK_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2178:31:2178:41|No assignment to wire ARCACHE_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2179:31:2179:40|No assignment to wire ARPROT_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2180:31:2180:41|No assignment to wire ARVALID_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2183:32:2183:41|No assignment to wire RREADY_IS4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2185:56:2185:63|No assignment to wire AWID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2186:21:2186:30|No assignment to wire AWADDR_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2187:31:2187:39|No assignment to wire AWLEN_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2188:31:2188:40|No assignment to wire AWSIZE_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2189:31:2189:41|No assignment to wire AWBURST_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2190:31:2190:40|No assignment to wire AWLOCK_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2191:31:2191:41|No assignment to wire AWCACHE_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2192:31:2192:40|No assignment to wire AWPROT_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2193:31:2193:41|No assignment to wire AWVALID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2196:56:2196:62|No assignment to wire WID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2197:31:2197:39|No assignment to wire WDATA_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2198:31:2198:39|No assignment to wire WSTRB_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2199:31:2199:39|No assignment to wire WLAST_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2200:31:2200:40|No assignment to wire WVALID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2202:31:2202:40|No assignment to wire BREADY_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2204:56:2204:63|No assignment to wire ARID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2205:21:2205:30|No assignment to wire ARADDR_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2206:31:2206:39|No assignment to wire ARLEN_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2207:31:2207:40|No assignment to wire ARSIZE_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2208:31:2208:41|No assignment to wire ARBURST_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2209:31:2209:40|No assignment to wire ARLOCK_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2210:31:2210:41|No assignment to wire ARCACHE_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2211:31:2211:40|No assignment to wire ARPROT_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2212:31:2212:41|No assignment to wire ARVALID_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2215:32:2215:41|No assignment to wire RREADY_IS5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2217:56:2217:63|No assignment to wire AWID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2218:21:2218:30|No assignment to wire AWADDR_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2219:31:2219:39|No assignment to wire AWLEN_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2220:31:2220:40|No assignment to wire AWSIZE_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2221:31:2221:41|No assignment to wire AWBURST_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2222:31:2222:40|No assignment to wire AWLOCK_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2223:31:2223:41|No assignment to wire AWCACHE_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2224:31:2224:40|No assignment to wire AWPROT_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2225:31:2225:41|No assignment to wire AWVALID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2228:56:2228:62|No assignment to wire WID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2229:31:2229:39|No assignment to wire WDATA_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2230:31:2230:39|No assignment to wire WSTRB_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2231:31:2231:39|No assignment to wire WLAST_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2232:31:2232:40|No assignment to wire WVALID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2234:31:2234:40|No assignment to wire BREADY_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2236:56:2236:63|No assignment to wire ARID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2237:21:2237:30|No assignment to wire ARADDR_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2238:31:2238:39|No assignment to wire ARLEN_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2239:31:2239:40|No assignment to wire ARSIZE_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2240:31:2240:41|No assignment to wire ARBURST_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2241:31:2241:40|No assignment to wire ARLOCK_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2242:31:2242:41|No assignment to wire ARCACHE_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2243:31:2243:40|No assignment to wire ARPROT_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2244:31:2244:41|No assignment to wire ARVALID_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2247:32:2247:41|No assignment to wire RREADY_IS6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2249:56:2249:63|No assignment to wire AWID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2250:21:2250:30|No assignment to wire AWADDR_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2251:31:2251:39|No assignment to wire AWLEN_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2252:31:2252:40|No assignment to wire AWSIZE_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2253:31:2253:41|No assignment to wire AWBURST_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2254:31:2254:40|No assignment to wire AWLOCK_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2255:31:2255:41|No assignment to wire AWCACHE_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2256:31:2256:40|No assignment to wire AWPROT_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2257:31:2257:41|No assignment to wire AWVALID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2260:56:2260:62|No assignment to wire WID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2261:31:2261:39|No assignment to wire WDATA_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2262:31:2262:39|No assignment to wire WSTRB_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2263:31:2263:39|No assignment to wire WLAST_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2264:31:2264:40|No assignment to wire WVALID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2266:31:2266:40|No assignment to wire BREADY_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2268:56:2268:63|No assignment to wire ARID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2269:21:2269:30|No assignment to wire ARADDR_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2270:31:2270:39|No assignment to wire ARLEN_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2271:31:2271:40|No assignment to wire ARSIZE_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2272:31:2272:41|No assignment to wire ARBURST_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2273:31:2273:40|No assignment to wire ARLOCK_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2274:31:2274:41|No assignment to wire ARCACHE_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2275:31:2275:40|No assignment to wire ARPROT_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2276:31:2276:41|No assignment to wire ARVALID_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2279:32:2279:41|No assignment to wire RREADY_IS7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2281:56:2281:63|No assignment to wire AWID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2282:21:2282:30|No assignment to wire AWADDR_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2283:31:2283:39|No assignment to wire AWLEN_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2284:31:2284:40|No assignment to wire AWSIZE_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2285:31:2285:41|No assignment to wire AWBURST_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2286:31:2286:40|No assignment to wire AWLOCK_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2287:31:2287:41|No assignment to wire AWCACHE_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2288:31:2288:40|No assignment to wire AWPROT_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2289:31:2289:41|No assignment to wire AWVALID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2292:56:2292:62|No assignment to wire WID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2293:31:2293:39|No assignment to wire WDATA_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2294:31:2294:39|No assignment to wire WSTRB_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2295:31:2295:39|No assignment to wire WLAST_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2296:31:2296:40|No assignment to wire WVALID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2298:31:2298:40|No assignment to wire BREADY_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2300:56:2300:63|No assignment to wire ARID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2301:21:2301:30|No assignment to wire ARADDR_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2302:31:2302:39|No assignment to wire ARLEN_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2303:31:2303:40|No assignment to wire ARSIZE_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2304:31:2304:41|No assignment to wire ARBURST_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2305:31:2305:40|No assignment to wire ARLOCK_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2306:31:2306:41|No assignment to wire ARCACHE_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2307:31:2307:40|No assignment to wire ARPROT_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2308:31:2308:41|No assignment to wire ARVALID_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2311:32:2311:41|No assignment to wire RREADY_IS8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2313:56:2313:63|No assignment to wire AWID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2314:21:2314:30|No assignment to wire AWADDR_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2315:31:2315:39|No assignment to wire AWLEN_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2316:31:2316:40|No assignment to wire AWSIZE_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2317:31:2317:41|No assignment to wire AWBURST_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2318:31:2318:40|No assignment to wire AWLOCK_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2319:31:2319:41|No assignment to wire AWCACHE_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2320:31:2320:40|No assignment to wire AWPROT_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2321:31:2321:41|No assignment to wire AWVALID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2324:56:2324:62|No assignment to wire WID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2325:31:2325:39|No assignment to wire WDATA_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2326:31:2326:39|No assignment to wire WSTRB_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2327:31:2327:39|No assignment to wire WLAST_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2328:31:2328:40|No assignment to wire WVALID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2330:31:2330:40|No assignment to wire BREADY_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2332:56:2332:63|No assignment to wire ARID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2333:21:2333:30|No assignment to wire ARADDR_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2334:31:2334:39|No assignment to wire ARLEN_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2335:31:2335:40|No assignment to wire ARSIZE_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2336:31:2336:41|No assignment to wire ARBURST_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2337:31:2337:40|No assignment to wire ARLOCK_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2338:31:2338:41|No assignment to wire ARCACHE_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2339:31:2339:40|No assignment to wire ARPROT_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2340:31:2340:41|No assignment to wire ARVALID_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2343:32:2343:41|No assignment to wire RREADY_IS9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2345:56:2345:64|No assignment to wire AWID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2346:21:2346:31|No assignment to wire AWADDR_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2347:31:2347:40|No assignment to wire AWLEN_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2348:31:2348:41|No assignment to wire AWSIZE_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2349:31:2349:42|No assignment to wire AWBURST_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2350:31:2350:41|No assignment to wire AWLOCK_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2351:31:2351:42|No assignment to wire AWCACHE_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2352:31:2352:41|No assignment to wire AWPROT_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2353:31:2353:42|No assignment to wire AWVALID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2356:56:2356:63|No assignment to wire WID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2357:31:2357:40|No assignment to wire WDATA_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2358:31:2358:40|No assignment to wire WSTRB_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2359:31:2359:40|No assignment to wire WLAST_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2360:31:2360:41|No assignment to wire WVALID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2362:31:2362:41|No assignment to wire BREADY_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2364:56:2364:64|No assignment to wire ARID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2365:21:2365:31|No assignment to wire ARADDR_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2366:31:2366:40|No assignment to wire ARLEN_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2367:31:2367:41|No assignment to wire ARSIZE_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2368:31:2368:42|No assignment to wire ARBURST_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2369:31:2369:41|No assignment to wire ARLOCK_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2370:31:2370:42|No assignment to wire ARCACHE_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2371:31:2371:41|No assignment to wire ARPROT_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2372:31:2372:42|No assignment to wire ARVALID_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2375:32:2375:42|No assignment to wire RREADY_IS10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2377:56:2377:64|No assignment to wire AWID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2378:21:2378:31|No assignment to wire AWADDR_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2379:31:2379:40|No assignment to wire AWLEN_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2380:31:2380:41|No assignment to wire AWSIZE_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2381:31:2381:42|No assignment to wire AWBURST_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2382:31:2382:41|No assignment to wire AWLOCK_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2383:31:2383:42|No assignment to wire AWCACHE_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2384:31:2384:41|No assignment to wire AWPROT_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2385:31:2385:42|No assignment to wire AWVALID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2388:56:2388:63|No assignment to wire WID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2389:31:2389:40|No assignment to wire WDATA_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2390:31:2390:40|No assignment to wire WSTRB_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2391:31:2391:40|No assignment to wire WLAST_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2392:31:2392:41|No assignment to wire WVALID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2394:31:2394:41|No assignment to wire BREADY_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2396:56:2396:64|No assignment to wire ARID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2397:21:2397:31|No assignment to wire ARADDR_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2398:31:2398:40|No assignment to wire ARLEN_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2399:31:2399:41|No assignment to wire ARSIZE_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2400:31:2400:42|No assignment to wire ARBURST_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2401:31:2401:41|No assignment to wire ARLOCK_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2402:31:2402:42|No assignment to wire ARCACHE_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2403:31:2403:41|No assignment to wire ARPROT_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2404:31:2404:42|No assignment to wire ARVALID_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2407:32:2407:42|No assignment to wire RREADY_IS11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2409:56:2409:64|No assignment to wire AWID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2410:21:2410:31|No assignment to wire AWADDR_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2411:31:2411:40|No assignment to wire AWLEN_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2412:31:2412:41|No assignment to wire AWSIZE_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2413:31:2413:42|No assignment to wire AWBURST_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2414:31:2414:41|No assignment to wire AWLOCK_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2415:31:2415:42|No assignment to wire AWCACHE_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2416:31:2416:41|No assignment to wire AWPROT_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2417:31:2417:42|No assignment to wire AWVALID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2420:56:2420:63|No assignment to wire WID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2421:31:2421:40|No assignment to wire WDATA_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2422:31:2422:40|No assignment to wire WSTRB_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2423:31:2423:40|No assignment to wire WLAST_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2424:31:2424:41|No assignment to wire WVALID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2426:31:2426:41|No assignment to wire BREADY_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2428:56:2428:64|No assignment to wire ARID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2429:21:2429:31|No assignment to wire ARADDR_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2430:31:2430:40|No assignment to wire ARLEN_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2431:31:2431:41|No assignment to wire ARSIZE_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2432:31:2432:42|No assignment to wire ARBURST_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2433:31:2433:41|No assignment to wire ARLOCK_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2434:31:2434:42|No assignment to wire ARCACHE_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2435:31:2435:41|No assignment to wire ARPROT_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2436:31:2436:42|No assignment to wire ARVALID_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2439:32:2439:42|No assignment to wire RREADY_IS12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2441:56:2441:64|No assignment to wire AWID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2442:21:2442:31|No assignment to wire AWADDR_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2443:31:2443:40|No assignment to wire AWLEN_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2444:31:2444:41|No assignment to wire AWSIZE_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2445:31:2445:42|No assignment to wire AWBURST_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2446:31:2446:41|No assignment to wire AWLOCK_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2447:31:2447:42|No assignment to wire AWCACHE_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2448:31:2448:41|No assignment to wire AWPROT_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2449:31:2449:42|No assignment to wire AWVALID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2452:56:2452:63|No assignment to wire WID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2453:31:2453:40|No assignment to wire WDATA_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2454:31:2454:40|No assignment to wire WSTRB_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2455:31:2455:40|No assignment to wire WLAST_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2456:31:2456:41|No assignment to wire WVALID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2458:31:2458:41|No assignment to wire BREADY_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2460:56:2460:64|No assignment to wire ARID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2461:21:2461:31|No assignment to wire ARADDR_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2462:31:2462:40|No assignment to wire ARLEN_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2463:31:2463:41|No assignment to wire ARSIZE_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2464:31:2464:42|No assignment to wire ARBURST_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2465:31:2465:41|No assignment to wire ARLOCK_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2466:31:2466:42|No assignment to wire ARCACHE_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2467:31:2467:41|No assignment to wire ARPROT_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2468:31:2468:42|No assignment to wire ARVALID_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2471:32:2471:42|No assignment to wire RREADY_IS13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2473:56:2473:64|No assignment to wire AWID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2474:21:2474:31|No assignment to wire AWADDR_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2475:31:2475:40|No assignment to wire AWLEN_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2476:31:2476:41|No assignment to wire AWSIZE_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2477:31:2477:42|No assignment to wire AWBURST_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2478:31:2478:41|No assignment to wire AWLOCK_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2479:31:2479:42|No assignment to wire AWCACHE_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2480:31:2480:41|No assignment to wire AWPROT_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2481:31:2481:42|No assignment to wire AWVALID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2484:56:2484:63|No assignment to wire WID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2485:31:2485:40|No assignment to wire WDATA_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2486:31:2486:40|No assignment to wire WSTRB_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2487:31:2487:40|No assignment to wire WLAST_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2488:31:2488:41|No assignment to wire WVALID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2490:31:2490:41|No assignment to wire BREADY_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2492:56:2492:64|No assignment to wire ARID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2493:21:2493:31|No assignment to wire ARADDR_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2494:31:2494:40|No assignment to wire ARLEN_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2495:31:2495:41|No assignment to wire ARSIZE_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2496:31:2496:42|No assignment to wire ARBURST_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2497:31:2497:41|No assignment to wire ARLOCK_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2498:31:2498:42|No assignment to wire ARCACHE_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2499:31:2499:41|No assignment to wire ARPROT_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2500:31:2500:42|No assignment to wire ARVALID_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2503:32:2503:42|No assignment to wire RREADY_IS14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2505:56:2505:64|No assignment to wire AWID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2506:21:2506:31|No assignment to wire AWADDR_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2507:31:2507:40|No assignment to wire AWLEN_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2508:31:2508:41|No assignment to wire AWSIZE_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2509:31:2509:42|No assignment to wire AWBURST_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2510:31:2510:41|No assignment to wire AWLOCK_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2511:31:2511:42|No assignment to wire AWCACHE_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2512:31:2512:41|No assignment to wire AWPROT_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2513:31:2513:42|No assignment to wire AWVALID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2516:56:2516:63|No assignment to wire WID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2517:31:2517:40|No assignment to wire WDATA_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2518:31:2518:40|No assignment to wire WSTRB_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2519:31:2519:40|No assignment to wire WLAST_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2520:31:2520:41|No assignment to wire WVALID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2522:31:2522:41|No assignment to wire BREADY_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2524:56:2524:64|No assignment to wire ARID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2525:21:2525:31|No assignment to wire ARADDR_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2526:31:2526:40|No assignment to wire ARLEN_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2527:31:2527:41|No assignment to wire ARSIZE_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2528:31:2528:42|No assignment to wire ARBURST_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2529:31:2529:41|No assignment to wire ARLOCK_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2530:31:2530:42|No assignment to wire ARCACHE_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2531:31:2531:41|No assignment to wire ARPROT_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2532:31:2532:42|No assignment to wire ARVALID_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2535:32:2535:42|No assignment to wire RREADY_IS15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2537:56:2537:64|No assignment to wire AWID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2538:21:2538:31|No assignment to wire AWADDR_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2539:31:2539:40|No assignment to wire AWLEN_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2540:31:2540:41|No assignment to wire AWSIZE_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2541:31:2541:42|No assignment to wire AWBURST_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2542:31:2542:41|No assignment to wire AWLOCK_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2543:31:2543:42|No assignment to wire AWCACHE_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2544:31:2544:41|No assignment to wire AWPROT_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2545:31:2545:42|No assignment to wire AWVALID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2548:56:2548:63|No assignment to wire WID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2549:31:2549:40|No assignment to wire WDATA_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2550:31:2550:40|No assignment to wire WSTRB_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2551:31:2551:40|No assignment to wire WLAST_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2552:31:2552:41|No assignment to wire WVALID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2554:31:2554:41|No assignment to wire BREADY_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2556:56:2556:64|No assignment to wire ARID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2557:21:2557:31|No assignment to wire ARADDR_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2558:31:2558:40|No assignment to wire ARLEN_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2559:31:2559:41|No assignment to wire ARSIZE_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2560:31:2560:42|No assignment to wire ARBURST_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2561:31:2561:41|No assignment to wire ARLOCK_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2562:31:2562:42|No assignment to wire ARCACHE_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2563:31:2563:41|No assignment to wire ARPROT_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2564:31:2564:42|No assignment to wire ARVALID_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2567:32:2567:42|No assignment to wire RREADY_IS16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2572:39:2572:46|No assignment to wire AWID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2573:22:2573:31|No assignment to wire AWADDR_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2574:32:2574:40|No assignment to wire AWLEN_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2575:32:2575:41|No assignment to wire AWSIZE_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2576:32:2576:42|No assignment to wire AWBURST_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2577:32:2577:41|No assignment to wire AWLOCK_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2578:32:2578:42|No assignment to wire AWCACHE_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2579:32:2579:41|No assignment to wire AWPROT_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2580:32:2580:42|No assignment to wire AWVALID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2582:39:2582:45|No assignment to wire WID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2583:32:2583:40|No assignment to wire WDATA_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2584:32:2584:40|No assignment to wire WSTRB_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2585:32:2585:40|No assignment to wire WLAST_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2586:32:2586:41|No assignment to wire WVALID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2588:39:2588:46|No assignment to wire ARID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2589:21:2589:30|No assignment to wire ARADDR_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2590:31:2590:39|No assignment to wire ARLEN_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2591:31:2591:40|No assignment to wire ARSIZE_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2592:31:2592:41|No assignment to wire ARBURST_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2593:31:2593:40|No assignment to wire ARLOCK_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2594:31:2594:41|No assignment to wire ARCACHE_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2595:31:2595:40|No assignment to wire ARPROT_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2596:31:2596:41|No assignment to wire ARVALID_MI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2598:31:2598:39|No assignment to wire BRESP_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2599:39:2599:45|No assignment to wire BID_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2601:39:2601:45|No assignment to wire RID_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2602:30:2602:38|No assignment to wire RDATA_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2603:30:2603:38|No assignment to wire RRESP_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2604:30:2604:39|No assignment to wire RVALID_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2605:30:2605:38|No assignment to wire RLAST_IM0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2610:39:2610:46|No assignment to wire AWID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2611:22:2611:31|No assignment to wire AWADDR_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2612:32:2612:40|No assignment to wire AWLEN_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2613:32:2613:41|No assignment to wire AWSIZE_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2614:32:2614:42|No assignment to wire AWBURST_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2615:32:2615:41|No assignment to wire AWLOCK_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2616:32:2616:42|No assignment to wire AWCACHE_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2617:32:2617:41|No assignment to wire AWPROT_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2618:32:2618:42|No assignment to wire AWVALID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2620:39:2620:45|No assignment to wire WID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2621:32:2621:40|No assignment to wire WDATA_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2622:32:2622:40|No assignment to wire WSTRB_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2623:32:2623:40|No assignment to wire WLAST_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2624:32:2624:41|No assignment to wire WVALID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2626:39:2626:46|No assignment to wire ARID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2627:21:2627:30|No assignment to wire ARADDR_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2628:31:2628:39|No assignment to wire ARLEN_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2629:31:2629:40|No assignment to wire ARSIZE_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2630:31:2630:41|No assignment to wire ARBURST_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2631:31:2631:40|No assignment to wire ARLOCK_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2632:31:2632:41|No assignment to wire ARCACHE_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2633:31:2633:40|No assignment to wire ARPROT_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2634:31:2634:41|No assignment to wire ARVALID_MI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2636:31:2636:39|No assignment to wire BRESP_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2637:39:2637:45|No assignment to wire BID_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2639:39:2639:45|No assignment to wire RID_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2640:30:2640:38|No assignment to wire RDATA_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2641:30:2641:38|No assignment to wire RRESP_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2642:30:2642:39|No assignment to wire RVALID_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2643:30:2643:38|No assignment to wire RLAST_IM1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2647:39:2647:46|No assignment to wire AWID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2648:22:2648:31|No assignment to wire AWADDR_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2649:32:2649:40|No assignment to wire AWLEN_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2650:32:2650:41|No assignment to wire AWSIZE_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2651:32:2651:42|No assignment to wire AWBURST_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2652:32:2652:41|No assignment to wire AWLOCK_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2653:32:2653:42|No assignment to wire AWCACHE_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2654:32:2654:41|No assignment to wire AWPROT_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2655:32:2655:42|No assignment to wire AWVALID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2657:39:2657:45|No assignment to wire WID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2658:32:2658:40|No assignment to wire WDATA_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2659:32:2659:40|No assignment to wire WSTRB_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2660:32:2660:40|No assignment to wire WLAST_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2661:32:2661:41|No assignment to wire WVALID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2663:39:2663:46|No assignment to wire ARID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2664:21:2664:30|No assignment to wire ARADDR_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2665:31:2665:39|No assignment to wire ARLEN_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2666:31:2666:40|No assignment to wire ARSIZE_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2667:31:2667:41|No assignment to wire ARBURST_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2668:31:2668:40|No assignment to wire ARLOCK_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2669:31:2669:41|No assignment to wire ARCACHE_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2670:31:2670:40|No assignment to wire ARPROT_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2671:31:2671:41|No assignment to wire ARVALID_MI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2673:31:2673:39|No assignment to wire BRESP_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2674:39:2674:45|No assignment to wire BID_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2676:39:2676:45|No assignment to wire RID_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2677:30:2677:38|No assignment to wire RDATA_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2678:30:2678:38|No assignment to wire RRESP_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2679:30:2679:39|No assignment to wire RVALID_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2680:30:2680:38|No assignment to wire RLAST_IM2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2684:39:2684:46|No assignment to wire AWID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2685:22:2685:31|No assignment to wire AWADDR_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2686:32:2686:40|No assignment to wire AWLEN_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2687:32:2687:41|No assignment to wire AWSIZE_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2688:32:2688:42|No assignment to wire AWBURST_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2689:32:2689:41|No assignment to wire AWLOCK_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2690:32:2690:42|No assignment to wire AWCACHE_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2691:32:2691:41|No assignment to wire AWPROT_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2692:32:2692:42|No assignment to wire AWVALID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2694:39:2694:45|No assignment to wire WID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2695:32:2695:40|No assignment to wire WDATA_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2696:32:2696:40|No assignment to wire WSTRB_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2697:32:2697:40|No assignment to wire WLAST_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2698:32:2698:41|No assignment to wire WVALID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2700:39:2700:46|No assignment to wire ARID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2701:21:2701:30|No assignment to wire ARADDR_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2702:31:2702:39|No assignment to wire ARLEN_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2703:31:2703:40|No assignment to wire ARSIZE_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2704:31:2704:41|No assignment to wire ARBURST_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2705:31:2705:40|No assignment to wire ARLOCK_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2706:31:2706:41|No assignment to wire ARCACHE_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2707:31:2707:40|No assignment to wire ARPROT_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2708:31:2708:41|No assignment to wire ARVALID_MI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2710:31:2710:39|No assignment to wire BRESP_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2711:39:2711:45|No assignment to wire BID_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2713:39:2713:45|No assignment to wire RID_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2714:30:2714:38|No assignment to wire RDATA_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2715:30:2715:38|No assignment to wire RRESP_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2716:30:2716:39|No assignment to wire RVALID_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2717:30:2717:38|No assignment to wire RLAST_IM3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3263:31:3263:41|No assignment to wire AWREADY_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3264:31:3264:41|No assignment to wire AWREADY_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3265:31:3265:41|No assignment to wire AWREADY_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3266:31:3266:41|No assignment to wire AWREADY_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3267:31:3267:41|No assignment to wire AWREADY_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3268:31:3268:41|No assignment to wire AWREADY_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3269:31:3269:41|No assignment to wire AWREADY_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3270:31:3270:41|No assignment to wire AWREADY_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3271:31:3271:41|No assignment to wire AWREADY_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3272:31:3272:41|No assignment to wire AWREADY_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3273:31:3273:42|No assignment to wire AWREADY_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3274:31:3274:42|No assignment to wire AWREADY_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3275:31:3275:42|No assignment to wire AWREADY_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3276:31:3276:42|No assignment to wire AWREADY_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3277:31:3277:42|No assignment to wire AWREADY_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3278:31:3278:42|No assignment to wire AWREADY_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3279:31:3279:42|No assignment to wire AWREADY_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3281:31:3281:40|No assignment to wire WREADY_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3282:31:3282:40|No assignment to wire WREADY_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3283:31:3283:40|No assignment to wire WREADY_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3284:31:3284:40|No assignment to wire WREADY_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3285:31:3285:40|No assignment to wire WREADY_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3286:31:3286:40|No assignment to wire WREADY_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3287:31:3287:40|No assignment to wire WREADY_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3288:31:3288:40|No assignment to wire WREADY_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3289:31:3289:40|No assignment to wire WREADY_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3290:31:3290:40|No assignment to wire WREADY_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3291:31:3291:41|No assignment to wire WREADY_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3292:31:3292:41|No assignment to wire WREADY_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3293:31:3293:41|No assignment to wire WREADY_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3294:31:3294:41|No assignment to wire WREADY_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3295:31:3295:41|No assignment to wire WREADY_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3296:31:3296:41|No assignment to wire WREADY_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3297:31:3297:41|No assignment to wire WREADY_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3299:31:3299:41|No assignment to wire ARREADY_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3300:31:3300:41|No assignment to wire ARREADY_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3301:31:3301:41|No assignment to wire ARREADY_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3302:31:3302:41|No assignment to wire ARREADY_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3303:31:3303:41|No assignment to wire ARREADY_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3304:31:3304:41|No assignment to wire ARREADY_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3305:31:3305:41|No assignment to wire ARREADY_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3306:31:3306:41|No assignment to wire ARREADY_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3307:31:3307:41|No assignment to wire ARREADY_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3308:31:3308:41|No assignment to wire ARREADY_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3309:31:3309:42|No assignment to wire ARREADY_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3310:31:3310:42|No assignment to wire ARREADY_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3311:31:3311:42|No assignment to wire ARREADY_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3312:31:3312:42|No assignment to wire ARREADY_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3313:31:3313:42|No assignment to wire ARREADY_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3314:31:3314:42|No assignment to wire ARREADY_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3315:31:3315:42|No assignment to wire ARREADY_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3388:55:3388:61|No assignment to wire BID_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3389:30:3389:38|No assignment to wire BRESP_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3390:30:3390:39|No assignment to wire BVALID_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3391:55:3391:61|No assignment to wire RID_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3392:30:3392:38|No assignment to wire RDATA_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3393:30:3393:38|No assignment to wire RRESP_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3394:30:3394:38|No assignment to wire RLAST_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3395:30:3395:39|No assignment to wire RVALID_SI0

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3397:55:3397:61|No assignment to wire BID_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3398:30:3398:38|No assignment to wire BRESP_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3399:30:3399:39|No assignment to wire BVALID_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3400:55:3400:61|No assignment to wire RID_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3401:30:3401:38|No assignment to wire RDATA_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3402:30:3402:38|No assignment to wire RRESP_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3403:30:3403:38|No assignment to wire RLAST_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3404:30:3404:39|No assignment to wire RVALID_SI1

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3406:55:3406:61|No assignment to wire BID_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3407:30:3407:38|No assignment to wire BRESP_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3408:30:3408:39|No assignment to wire BVALID_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3409:55:3409:61|No assignment to wire RID_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3410:30:3410:38|No assignment to wire RDATA_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3411:30:3411:38|No assignment to wire RRESP_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3412:30:3412:38|No assignment to wire RLAST_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3413:30:3413:39|No assignment to wire RVALID_SI2

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3415:55:3415:61|No assignment to wire BID_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3416:30:3416:38|No assignment to wire BRESP_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3417:30:3417:39|No assignment to wire BVALID_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3418:55:3418:61|No assignment to wire RID_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3419:30:3419:38|No assignment to wire RDATA_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3420:30:3420:38|No assignment to wire RRESP_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3421:30:3421:38|No assignment to wire RLAST_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3422:30:3422:39|No assignment to wire RVALID_SI3

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3424:55:3424:61|No assignment to wire BID_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3425:30:3425:38|No assignment to wire BRESP_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3426:30:3426:39|No assignment to wire BVALID_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3427:55:3427:61|No assignment to wire RID_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3428:30:3428:38|No assignment to wire RDATA_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3429:30:3429:38|No assignment to wire RRESP_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3430:30:3430:38|No assignment to wire RLAST_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3431:30:3431:39|No assignment to wire RVALID_SI4

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3433:55:3433:61|No assignment to wire BID_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3434:30:3434:38|No assignment to wire BRESP_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3435:30:3435:39|No assignment to wire BVALID_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3436:55:3436:61|No assignment to wire RID_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3437:30:3437:38|No assignment to wire RDATA_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3438:30:3438:38|No assignment to wire RRESP_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3439:30:3439:38|No assignment to wire RLAST_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3440:30:3440:39|No assignment to wire RVALID_SI5

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3442:55:3442:61|No assignment to wire BID_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3443:30:3443:38|No assignment to wire BRESP_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3444:30:3444:39|No assignment to wire BVALID_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3445:55:3445:61|No assignment to wire RID_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3446:30:3446:38|No assignment to wire RDATA_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3447:30:3447:38|No assignment to wire RRESP_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3448:30:3448:38|No assignment to wire RLAST_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3449:30:3449:39|No assignment to wire RVALID_SI6

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3451:55:3451:61|No assignment to wire BID_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3452:30:3452:38|No assignment to wire BRESP_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3453:30:3453:39|No assignment to wire BVALID_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3454:55:3454:61|No assignment to wire RID_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3455:30:3455:38|No assignment to wire RDATA_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3456:30:3456:38|No assignment to wire RRESP_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3457:30:3457:38|No assignment to wire RLAST_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3458:30:3458:39|No assignment to wire RVALID_SI7

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3460:55:3460:61|No assignment to wire BID_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3461:30:3461:38|No assignment to wire BRESP_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3462:30:3462:39|No assignment to wire BVALID_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3463:55:3463:61|No assignment to wire RID_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3464:30:3464:38|No assignment to wire RDATA_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3465:30:3465:38|No assignment to wire RRESP_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3466:30:3466:38|No assignment to wire RLAST_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3467:30:3467:39|No assignment to wire RVALID_SI8

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3469:55:3469:61|No assignment to wire BID_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3470:30:3470:38|No assignment to wire BRESP_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3471:30:3471:39|No assignment to wire BVALID_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3472:55:3472:61|No assignment to wire RID_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3473:30:3473:38|No assignment to wire RDATA_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3474:30:3474:38|No assignment to wire RRESP_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3475:30:3475:38|No assignment to wire RLAST_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3476:30:3476:39|No assignment to wire RVALID_SI9

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3478:55:3478:62|No assignment to wire BID_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3479:30:3479:39|No assignment to wire BRESP_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3480:30:3480:40|No assignment to wire BVALID_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3481:55:3481:62|No assignment to wire RID_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3482:30:3482:39|No assignment to wire RDATA_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3483:30:3483:39|No assignment to wire RRESP_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3484:30:3484:39|No assignment to wire RLAST_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3485:30:3485:40|No assignment to wire RVALID_SI10

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3487:55:3487:62|No assignment to wire BID_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3488:30:3488:39|No assignment to wire BRESP_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3489:30:3489:40|No assignment to wire BVALID_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3490:55:3490:62|No assignment to wire RID_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3491:30:3491:39|No assignment to wire RDATA_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3492:30:3492:39|No assignment to wire RRESP_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3493:30:3493:39|No assignment to wire RLAST_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3494:30:3494:40|No assignment to wire RVALID_SI11

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3496:55:3496:62|No assignment to wire BID_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3497:30:3497:39|No assignment to wire BRESP_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3498:30:3498:40|No assignment to wire BVALID_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3499:55:3499:62|No assignment to wire RID_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3500:30:3500:39|No assignment to wire RDATA_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3501:30:3501:39|No assignment to wire RRESP_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3502:30:3502:39|No assignment to wire RLAST_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3503:30:3503:40|No assignment to wire RVALID_SI12

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3505:55:3505:62|No assignment to wire BID_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3506:30:3506:39|No assignment to wire BRESP_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3507:30:3507:40|No assignment to wire BVALID_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3508:55:3508:62|No assignment to wire RID_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3509:30:3509:39|No assignment to wire RDATA_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3510:30:3510:39|No assignment to wire RRESP_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3511:30:3511:39|No assignment to wire RLAST_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3512:30:3512:40|No assignment to wire RVALID_SI13

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3514:55:3514:62|No assignment to wire BID_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3515:30:3515:39|No assignment to wire BRESP_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3516:30:3516:40|No assignment to wire BVALID_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3517:55:3517:62|No assignment to wire RID_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3518:30:3518:39|No assignment to wire RDATA_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3519:30:3519:39|No assignment to wire RRESP_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3520:30:3520:39|No assignment to wire RLAST_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3521:30:3521:40|No assignment to wire RVALID_SI14

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3523:55:3523:62|No assignment to wire BID_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3524:30:3524:39|No assignment to wire BRESP_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3525:30:3525:40|No assignment to wire BVALID_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3526:55:3526:62|No assignment to wire RID_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3527:30:3527:39|No assignment to wire RDATA_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3528:30:3528:39|No assignment to wire RRESP_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3529:30:3529:39|No assignment to wire RLAST_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3530:30:3530:40|No assignment to wire RVALID_SI15

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3532:55:3532:62|No assignment to wire BID_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3533:30:3533:39|No assignment to wire BRESP_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3534:30:3534:40|No assignment to wire BVALID_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3535:55:3535:62|No assignment to wire RID_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3536:30:3536:39|No assignment to wire RDATA_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3537:30:3537:39|No assignment to wire RRESP_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3538:30:3538:39|No assignment to wire RLAST_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3539:30:3539:40|No assignment to wire RVALID_SI16

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3542:55:3542:60|No assignment to wire BID_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3543:30:3543:37|No assignment to wire BRESP_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3544:30:3544:38|No assignment to wire BVALID_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3545:55:3545:60|No assignment to wire RID_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3546:30:3546:37|No assignment to wire RDATA_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3547:30:3547:37|No assignment to wire RRESP_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3548:30:3548:37|No assignment to wire RLAST_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3549:30:3549:38|No assignment to wire RVALID_IM

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3551:30:3551:38|No assignment to wire m0_rd_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3552:30:3552:38|No assignment to wire m1_rd_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3553:30:3553:38|No assignment to wire m2_rd_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3554:30:3554:38|No assignment to wire m3_rd_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3555:30:3555:38|No assignment to wire m0_wr_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3556:30:3556:38|No assignment to wire m1_wr_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3557:30:3557:38|No assignment to wire m2_wr_end

@W: CG360 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3558:30:3558:38|No assignment to wire m3_wr_end

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP

	FAMILY=32'b00000000000000000000000000010011
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	VERSION_MAJOR=32'b00000000000000000000000000000111
	VERSION_MINOR=32'b00000000000000000000000000000000
	VERSION_MAJOR_VECTOR=16'b0000000000000111
	VERSION_MINOR_VECTOR=16'b0000000000000000
	S0=2'b00
	S1=2'b01
	S2=2'b10
   Generated name = CoreConfigP_Z9

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z10

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning register count_sdif3[12:0] 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning register count_sdif2[12:0] 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning register count_sdif1[12:0] 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning register count_sdif0[12:0] 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_q1 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_q1 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_q1 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_q1 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_rcosc 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_rcosc 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_rcosc 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_rcosc 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning register count_sdif3_enable 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning register count_sdif2_enable 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning register count_sdif1_enable 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning register count_sdif0_enable 

@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register release_ext_reset 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register EXT_RESET_OUT_int 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register sm2_state[2:0] 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_q1 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_clk_base 

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.105\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.105\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":5:7:5:26|Synthesizing module MDDR_TA_FABOSC_0_OSC

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":274:7:274:12|Synthesizing module OUTBUF

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":286:7:286:11|Synthesizing module BIBUF

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":268:7:268:11|Synthesizing module INBUF

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v":9:7:9:18|Synthesizing module MDDR_TA_HPMS

@N: CG364 :"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v":718:7:718:14|Synthesizing module SYSRESET

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v":9:7:9:13|Synthesizing module MDDR_TA

@N: CG364 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v":9:7:9:17|Synthesizing module MDDR_TA_top

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v":112:14:112:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused

@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W: CL246 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":310:57:310:62|Input port bits 5 to 4 of BID_S0[5:0] are unused

@W: CL246 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":326:57:326:62|Input port bits 5 to 4 of RID_S0[5:0] are unused

@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":243:32:243:35|Input ACLK is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":244:32:244:38|Input ARESETN is unused
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1144:33:1144:42|*Output AWREADY_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1151:33:1151:41|*Output WREADY_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1153:33:1153:38|*Output BID_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1154:33:1154:40|*Output BRESP_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1155:33:1155:41|*Output BVALID_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1167:33:1167:42|*Output ARREADY_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1169:33:1169:38|*Output RID_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1170:33:1170:40|*Output RDATA_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1171:33:1171:40|*Output RRESP_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1172:33:1172:40|*Output RLAST_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1173:33:1173:41|*Output RVALID_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1187:33:1187:42|*Output AWREADY_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1194:33:1194:41|*Output WREADY_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1196:33:1196:38|*Output BID_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1197:33:1197:40|*Output BRESP_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1198:33:1198:41|*Output BVALID_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1210:33:1210:42|*Output ARREADY_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1212:33:1212:38|*Output RID_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1213:33:1213:40|*Output RDATA_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1214:33:1214:40|*Output RRESP_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1215:33:1215:40|*Output RLAST_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1216:33:1216:41|*Output RVALID_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1230:33:1230:42|*Output AWREADY_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1237:33:1237:41|*Output WREADY_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1239:33:1239:38|*Output BID_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1240:33:1240:40|*Output BRESP_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1241:33:1241:41|*Output BVALID_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1253:33:1253:42|*Output ARREADY_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1255:33:1255:38|*Output RID_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1256:33:1256:40|*Output RDATA_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1257:33:1257:40|*Output RRESP_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1258:33:1258:40|*Output RLAST_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1259:33:1259:41|*Output RVALID_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:58:1307:64|*Output AWID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:23:1308:31|*Output AWADDR_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:40|*Output AWLEN_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1310:33:1310:41|*Output AWSIZE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:33:1311:42|*Output AWBURST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|*Output AWLOCK_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:42|*Output AWCACHE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|*Output AWPROT_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|*Output AWVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1318:58:1318:63|*Output WID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1319:33:1319:40|*Output WDATA_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:33:1320:40|*Output WSTRB_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:40|*Output WLAST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|*Output WVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:41|*Output BREADY_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1330:58:1330:64|*Output ARID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:23:1331:31|*Output ARADDR_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:40|*Output ARLEN_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|*Output ARSIZE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:42|*Output ARBURST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:41|*Output ARLOCK_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|*Output ARCACHE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1337:33:1337:41|*Output ARPROT_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:33:1338:42|*Output ARVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:41|*Output RREADY_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:58:1350:64|*Output AWID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:23:1351:31|*Output AWADDR_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:40|*Output AWLEN_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1353:33:1353:41|*Output AWSIZE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:33:1354:42|*Output AWBURST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|*Output AWLOCK_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:42|*Output AWCACHE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|*Output AWPROT_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|*Output AWVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1361:58:1361:63|*Output WID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1362:33:1362:40|*Output WDATA_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:33:1363:40|*Output WSTRB_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:40|*Output WLAST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|*Output WVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:41|*Output BREADY_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1373:58:1373:64|*Output ARID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:23:1374:31|*Output ARADDR_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:40|*Output ARLEN_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|*Output ARSIZE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:42|*Output ARBURST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:41|*Output ARLOCK_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|*Output ARCACHE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1380:33:1380:41|*Output ARPROT_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:33:1381:42|*Output ARVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:41|*Output RREADY_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:58:1393:64|*Output AWID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:23:1394:31|*Output AWADDR_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:40|*Output AWLEN_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1396:33:1396:41|*Output AWSIZE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:33:1397:42|*Output AWBURST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|*Output AWLOCK_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:42|*Output AWCACHE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|*Output AWPROT_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|*Output AWVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1404:58:1404:63|*Output WID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1405:33:1405:40|*Output WDATA_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:33:1406:40|*Output WSTRB_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:40|*Output WLAST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|*Output WVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:41|*Output BREADY_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1416:58:1416:64|*Output ARID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:23:1417:31|*Output ARADDR_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1418:33:1418:40|*Output ARLEN_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|*Output ARSIZE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1420:33:1420:42|*Output ARBURST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1421:33:1421:41|*Output ARLOCK_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1422:33:1422:42|*Output ARCACHE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1423:33:1423:41|*Output ARPROT_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1424:33:1424:42|*Output ARVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1432:33:1432:41|*Output RREADY_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1436:58:1436:64|*Output AWID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1437:23:1437:31|*Output AWADDR_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1438:33:1438:40|*Output AWLEN_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1439:33:1439:41|*Output AWSIZE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1440:33:1440:42|*Output AWBURST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1441:33:1441:41|*Output AWLOCK_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1442:33:1442:42|*Output AWCACHE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1443:33:1443:41|*Output AWPROT_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1444:33:1444:42|*Output AWVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1447:58:1447:63|*Output WID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1448:33:1448:40|*Output WDATA_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:33:1449:40|*Output WSTRB_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1450:33:1450:40|*Output WLAST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|*Output WVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1457:33:1457:41|*Output BREADY_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1459:58:1459:64|*Output ARID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:23:1460:31|*Output ARADDR_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1461:33:1461:40|*Output ARLEN_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|*Output ARSIZE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1463:33:1463:42|*Output ARBURST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1464:33:1464:41|*Output ARLOCK_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1465:33:1465:42|*Output ARCACHE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1466:33:1466:41|*Output ARPROT_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1467:33:1467:42|*Output ARVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1475:33:1475:41|*Output RREADY_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1479:58:1479:64|*Output AWID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1480:23:1480:31|*Output AWADDR_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1481:33:1481:40|*Output AWLEN_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1482:33:1482:41|*Output AWSIZE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1483:33:1483:42|*Output AWBURST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1484:33:1484:41|*Output AWLOCK_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1485:33:1485:42|*Output AWCACHE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1486:33:1486:41|*Output AWPROT_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1487:33:1487:42|*Output AWVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1490:58:1490:63|*Output WID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1491:33:1491:40|*Output WDATA_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1492:33:1492:40|*Output WSTRB_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1493:33:1493:40|*Output WLAST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|*Output WVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1500:33:1500:41|*Output BREADY_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1502:58:1502:64|*Output ARID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1503:23:1503:31|*Output ARADDR_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1504:33:1504:40|*Output ARLEN_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|*Output ARSIZE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1506:33:1506:42|*Output ARBURST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1507:33:1507:41|*Output ARLOCK_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1508:33:1508:42|*Output ARCACHE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1509:33:1509:41|*Output ARPROT_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1510:33:1510:42|*Output ARVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1518:33:1518:41|*Output RREADY_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1522:58:1522:64|*Output AWID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1523:23:1523:31|*Output AWADDR_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1524:33:1524:40|*Output AWLEN_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1525:33:1525:41|*Output AWSIZE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1526:33:1526:42|*Output AWBURST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1527:33:1527:41|*Output AWLOCK_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1528:33:1528:42|*Output AWCACHE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1529:33:1529:41|*Output AWPROT_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1530:33:1530:42|*Output AWVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1533:58:1533:63|*Output WID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1534:33:1534:40|*Output WDATA_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1535:33:1535:40|*Output WSTRB_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1536:33:1536:40|*Output WLAST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1537:33:1537:41|*Output WVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1543:33:1543:41|*Output BREADY_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1545:58:1545:64|*Output ARID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1546:23:1546:31|*Output ARADDR_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1547:33:1547:40|*Output ARLEN_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1548:33:1548:41|*Output ARSIZE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1549:33:1549:42|*Output ARBURST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1550:33:1550:41|*Output ARLOCK_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1551:33:1551:42|*Output ARCACHE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1552:33:1552:41|*Output ARPROT_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1553:33:1553:42|*Output ARVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1561:33:1561:41|*Output RREADY_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1565:58:1565:64|*Output AWID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1566:23:1566:31|*Output AWADDR_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1567:33:1567:40|*Output AWLEN_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1568:33:1568:41|*Output AWSIZE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1569:33:1569:42|*Output AWBURST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1570:33:1570:41|*Output AWLOCK_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1571:33:1571:42|*Output AWCACHE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1572:33:1572:41|*Output AWPROT_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1573:33:1573:42|*Output AWVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1576:58:1576:63|*Output WID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1577:33:1577:40|*Output WDATA_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1578:33:1578:40|*Output WSTRB_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1579:33:1579:40|*Output WLAST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1580:33:1580:41|*Output WVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1586:33:1586:41|*Output BREADY_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1588:58:1588:64|*Output ARID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1589:23:1589:31|*Output ARADDR_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1590:33:1590:40|*Output ARLEN_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1591:33:1591:41|*Output ARSIZE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1592:33:1592:42|*Output ARBURST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1593:33:1593:41|*Output ARLOCK_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1594:33:1594:42|*Output ARCACHE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1595:33:1595:41|*Output ARPROT_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1596:33:1596:42|*Output ARVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1604:33:1604:41|*Output RREADY_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1608:58:1608:64|*Output AWID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1609:23:1609:31|*Output AWADDR_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1610:33:1610:40|*Output AWLEN_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1611:33:1611:41|*Output AWSIZE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1612:33:1612:42|*Output AWBURST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1613:33:1613:41|*Output AWLOCK_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1614:33:1614:42|*Output AWCACHE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1615:33:1615:41|*Output AWPROT_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1616:33:1616:42|*Output AWVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1619:58:1619:63|*Output WID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1620:33:1620:40|*Output WDATA_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1621:33:1621:40|*Output WSTRB_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1622:33:1622:40|*Output WLAST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1623:33:1623:41|*Output WVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1629:33:1629:41|*Output BREADY_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1631:58:1631:64|*Output ARID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1632:23:1632:31|*Output ARADDR_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1633:33:1633:40|*Output ARLEN_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1634:33:1634:41|*Output ARSIZE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1635:33:1635:42|*Output ARBURST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1636:33:1636:41|*Output ARLOCK_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1637:33:1637:42|*Output ARCACHE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1638:33:1638:41|*Output ARPROT_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1639:33:1639:42|*Output ARVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1647:33:1647:41|*Output RREADY_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1651:58:1651:64|*Output AWID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1652:23:1652:31|*Output AWADDR_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1653:33:1653:40|*Output AWLEN_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1654:33:1654:41|*Output AWSIZE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1655:33:1655:42|*Output AWBURST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1656:33:1656:41|*Output AWLOCK_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1657:33:1657:42|*Output AWCACHE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1658:33:1658:41|*Output AWPROT_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1659:33:1659:42|*Output AWVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1662:58:1662:63|*Output WID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1663:33:1663:40|*Output WDATA_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1664:33:1664:40|*Output WSTRB_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1665:33:1665:40|*Output WLAST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1666:33:1666:41|*Output WVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1672:33:1672:41|*Output BREADY_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1674:58:1674:64|*Output ARID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1675:23:1675:31|*Output ARADDR_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1676:33:1676:40|*Output ARLEN_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1677:33:1677:41|*Output ARSIZE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1678:33:1678:42|*Output ARBURST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1679:33:1679:41|*Output ARLOCK_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1680:33:1680:42|*Output ARCACHE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1681:33:1681:41|*Output ARPROT_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1682:33:1682:42|*Output ARVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1690:33:1690:41|*Output RREADY_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1694:58:1694:65|*Output AWID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1695:23:1695:32|*Output AWADDR_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1696:33:1696:41|*Output AWLEN_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1697:33:1697:42|*Output AWSIZE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1698:33:1698:43|*Output AWBURST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1699:33:1699:42|*Output AWLOCK_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1700:33:1700:43|*Output AWCACHE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1701:33:1701:42|*Output AWPROT_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1702:33:1702:43|*Output AWVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1705:58:1705:64|*Output WID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1706:33:1706:41|*Output WDATA_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1707:33:1707:41|*Output WSTRB_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1708:33:1708:41|*Output WLAST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1709:33:1709:42|*Output WVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1715:33:1715:42|*Output BREADY_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1717:58:1717:65|*Output ARID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1718:23:1718:32|*Output ARADDR_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1719:33:1719:41|*Output ARLEN_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1720:33:1720:42|*Output ARSIZE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1721:33:1721:43|*Output ARBURST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1722:33:1722:42|*Output ARLOCK_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1723:33:1723:43|*Output ARCACHE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1724:33:1724:42|*Output ARPROT_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1725:33:1725:43|*Output ARVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1733:33:1733:42|*Output RREADY_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1737:58:1737:65|*Output AWID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1738:23:1738:32|*Output AWADDR_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1739:33:1739:41|*Output AWLEN_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1740:33:1740:42|*Output AWSIZE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1741:33:1741:43|*Output AWBURST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1742:33:1742:42|*Output AWLOCK_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1743:33:1743:43|*Output AWCACHE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1744:33:1744:42|*Output AWPROT_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1745:33:1745:43|*Output AWVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1748:58:1748:64|*Output WID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1749:33:1749:41|*Output WDATA_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1750:33:1750:41|*Output WSTRB_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1751:33:1751:41|*Output WLAST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1752:33:1752:42|*Output WVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1758:33:1758:42|*Output BREADY_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1760:58:1760:65|*Output ARID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1761:23:1761:32|*Output ARADDR_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1762:33:1762:41|*Output ARLEN_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1763:33:1763:42|*Output ARSIZE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1764:33:1764:43|*Output ARBURST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1765:33:1765:42|*Output ARLOCK_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1766:33:1766:43|*Output ARCACHE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1767:33:1767:42|*Output ARPROT_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1768:33:1768:43|*Output ARVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1776:33:1776:42|*Output RREADY_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1780:58:1780:65|*Output AWID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1781:23:1781:32|*Output AWADDR_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1782:33:1782:41|*Output AWLEN_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1783:33:1783:42|*Output AWSIZE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1784:33:1784:43|*Output AWBURST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1785:33:1785:42|*Output AWLOCK_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1786:33:1786:43|*Output AWCACHE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1787:33:1787:42|*Output AWPROT_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1788:33:1788:43|*Output AWVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1791:58:1791:64|*Output WID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1792:33:1792:41|*Output WDATA_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1793:33:1793:41|*Output WSTRB_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1794:33:1794:41|*Output WLAST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1795:33:1795:42|*Output WVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1801:33:1801:42|*Output BREADY_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1803:58:1803:65|*Output ARID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1804:23:1804:32|*Output ARADDR_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1805:33:1805:41|*Output ARLEN_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1806:33:1806:42|*Output ARSIZE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1807:33:1807:43|*Output ARBURST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1808:33:1808:42|*Output ARLOCK_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1809:33:1809:43|*Output ARCACHE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1810:33:1810:42|*Output ARPROT_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1811:33:1811:43|*Output ARVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1819:33:1819:42|*Output RREADY_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1823:58:1823:65|*Output AWID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1824:23:1824:32|*Output AWADDR_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1825:33:1825:41|*Output AWLEN_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1826:33:1826:42|*Output AWSIZE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1827:33:1827:43|*Output AWBURST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1828:33:1828:42|*Output AWLOCK_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1829:33:1829:43|*Output AWCACHE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1830:33:1830:42|*Output AWPROT_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1831:33:1831:43|*Output AWVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1834:58:1834:64|*Output WID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1835:33:1835:41|*Output WDATA_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1836:33:1836:41|*Output WSTRB_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1837:33:1837:41|*Output WLAST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1838:33:1838:42|*Output WVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1844:33:1844:42|*Output BREADY_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1846:58:1846:65|*Output ARID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1847:23:1847:32|*Output ARADDR_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1848:33:1848:41|*Output ARLEN_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1849:33:1849:42|*Output ARSIZE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1850:33:1850:43|*Output ARBURST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1851:33:1851:42|*Output ARLOCK_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1852:33:1852:43|*Output ARCACHE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1853:33:1853:42|*Output ARPROT_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1854:33:1854:43|*Output ARVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1862:33:1862:42|*Output RREADY_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1866:58:1866:65|*Output AWID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1867:23:1867:32|*Output AWADDR_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1868:33:1868:41|*Output AWLEN_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1869:33:1869:42|*Output AWSIZE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1870:33:1870:43|*Output AWBURST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1871:33:1871:42|*Output AWLOCK_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1872:33:1872:43|*Output AWCACHE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1873:33:1873:42|*Output AWPROT_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1874:33:1874:43|*Output AWVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1877:58:1877:64|*Output WID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1878:33:1878:41|*Output WDATA_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1879:33:1879:41|*Output WSTRB_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1880:33:1880:41|*Output WLAST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1881:33:1881:42|*Output WVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1887:33:1887:42|*Output BREADY_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1889:58:1889:65|*Output ARID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1890:23:1890:32|*Output ARADDR_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1891:33:1891:41|*Output ARLEN_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1892:33:1892:42|*Output ARSIZE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1893:33:1893:43|*Output ARBURST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1894:33:1894:42|*Output ARLOCK_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1895:33:1895:43|*Output ARCACHE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1896:33:1896:42|*Output ARPROT_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1897:33:1897:43|*Output ARVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1905:33:1905:42|*Output RREADY_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1909:58:1909:65|*Output AWID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1910:23:1910:32|*Output AWADDR_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1911:33:1911:41|*Output AWLEN_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1912:33:1912:42|*Output AWSIZE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1913:33:1913:43|*Output AWBURST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1914:33:1914:42|*Output AWLOCK_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1915:33:1915:43|*Output AWCACHE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1916:33:1916:42|*Output AWPROT_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1917:33:1917:43|*Output AWVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1920:58:1920:64|*Output WID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1921:33:1921:41|*Output WDATA_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1922:33:1922:41|*Output WSTRB_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1923:33:1923:41|*Output WLAST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1924:33:1924:42|*Output WVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1930:33:1930:42|*Output BREADY_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1932:58:1932:65|*Output ARID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1933:23:1933:32|*Output ARADDR_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1934:33:1934:41|*Output ARLEN_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1935:33:1935:42|*Output ARSIZE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1936:33:1936:43|*Output ARBURST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1937:33:1937:42|*Output ARLOCK_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1938:33:1938:43|*Output ARCACHE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1939:33:1939:42|*Output ARPROT_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1940:33:1940:43|*Output ARVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1948:33:1948:42|*Output RREADY_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1952:58:1952:65|*Output AWID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1953:23:1953:32|*Output AWADDR_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1954:33:1954:41|*Output AWLEN_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1955:33:1955:42|*Output AWSIZE_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1956:33:1956:43|*Output AWBURST_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1957:33:1957:42|*Output AWLOCK_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1958:33:1958:43|*Output AWCACHE_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1959:33:1959:42|*Output AWPROT_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1960:33:1960:43|*Output AWVALID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1963:58:1963:64|*Output WID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1964:33:1964:41|*Output WDATA_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1965:33:1965:41|*Output WSTRB_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1966:33:1966:41|*Output WLAST_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1967:33:1967:42|*Output WVALID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1973:33:1973:42|*Output BREADY_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1975:58:1975:65|*Output ARID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1976:23:1976:32|*Output ARADDR_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1977:33:1977:41|*Output ARLEN_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1978:33:1978:42|*Output ARSIZE_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1979:33:1979:43|*Output ARBURST_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1980:33:1980:42|*Output ARLOCK_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1981:33:1981:43|*Output ARCACHE_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1982:33:1982:42|*Output ARPROT_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1983:33:1983:43|*Output ARVALID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1991:33:1991:42|*Output RREADY_S16 has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1135:33:1135:39|Input AWID_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1136:23:1136:31|Input AWADDR_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1137:33:1137:40|Input AWLEN_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1138:33:1138:41|Input AWSIZE_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1139:33:1139:42|Input AWBURST_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1140:33:1140:41|Input AWLOCK_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1141:33:1141:42|Input AWCACHE_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1142:33:1142:41|Input AWPROT_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1143:33:1143:42|Input AWVALID_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1146:33:1146:38|Input WID_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1147:33:1147:40|Input WDATA_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1148:33:1148:40|Input WSTRB_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1149:33:1149:40|Input WLAST_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1150:33:1150:41|Input WVALID_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1156:33:1156:41|Input BREADY_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1158:33:1158:39|Input ARID_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1159:23:1159:31|Input ARADDR_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Input ARLEN_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1161:33:1161:41|Input ARSIZE_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1162:33:1162:42|Input ARBURST_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1163:33:1163:41|Input ARLOCK_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1164:33:1164:42|Input ARCACHE_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1165:33:1165:41|Input ARPROT_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1166:33:1166:42|Input ARVALID_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1174:33:1174:41|Input RREADY_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1178:33:1178:39|Input AWID_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1179:23:1179:31|Input AWADDR_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1180:33:1180:40|Input AWLEN_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1181:33:1181:41|Input AWSIZE_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1182:33:1182:42|Input AWBURST_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1183:33:1183:41|Input AWLOCK_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1184:33:1184:42|Input AWCACHE_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1185:33:1185:41|Input AWPROT_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1186:33:1186:42|Input AWVALID_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1189:33:1189:38|Input WID_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1190:33:1190:40|Input WDATA_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1191:33:1191:40|Input WSTRB_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1192:33:1192:40|Input WLAST_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1193:33:1193:41|Input WVALID_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1199:33:1199:41|Input BREADY_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1201:33:1201:39|Input ARID_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1202:23:1202:31|Input ARADDR_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Input ARLEN_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1204:33:1204:41|Input ARSIZE_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1205:33:1205:42|Input ARBURST_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1206:33:1206:41|Input ARLOCK_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1207:33:1207:42|Input ARCACHE_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1208:33:1208:41|Input ARPROT_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1209:33:1209:42|Input ARVALID_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1217:33:1217:41|Input RREADY_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1221:33:1221:39|Input AWID_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1222:23:1222:31|Input AWADDR_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1223:33:1223:40|Input AWLEN_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1224:33:1224:41|Input AWSIZE_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1225:33:1225:42|Input AWBURST_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1226:33:1226:41|Input AWLOCK_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1227:33:1227:42|Input AWCACHE_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1228:33:1228:41|Input AWPROT_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1229:33:1229:42|Input AWVALID_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1232:33:1232:38|Input WID_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1233:33:1233:40|Input WDATA_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1234:33:1234:40|Input WSTRB_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1235:33:1235:40|Input WLAST_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1236:33:1236:41|Input WVALID_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1242:33:1242:41|Input BREADY_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1244:33:1244:39|Input ARID_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1245:23:1245:31|Input ARADDR_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Input ARLEN_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1247:33:1247:41|Input ARSIZE_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1248:33:1248:42|Input ARBURST_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1249:33:1249:41|Input ARLOCK_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1250:33:1250:42|Input ARCACHE_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1251:33:1251:41|Input ARPROT_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1252:33:1252:42|Input ARVALID_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1260:33:1260:41|Input RREADY_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1316:33:1316:42|Input AWREADY_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1323:33:1323:41|Input WREADY_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1325:58:1325:63|Input BID_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1326:33:1326:40|Input BRESP_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1327:33:1327:41|Input BVALID_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1339:33:1339:42|Input ARREADY_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1341:58:1341:63|Input RID_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1342:33:1342:40|Input RDATA_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1343:33:1343:40|Input RRESP_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1344:33:1344:40|Input RLAST_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1345:33:1345:41|Input RVALID_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1359:33:1359:42|Input AWREADY_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1366:33:1366:41|Input WREADY_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1368:58:1368:63|Input BID_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1369:33:1369:40|Input BRESP_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1370:33:1370:41|Input BVALID_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1382:33:1382:42|Input ARREADY_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1384:58:1384:63|Input RID_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1385:33:1385:40|Input RDATA_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1386:33:1386:40|Input RRESP_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1387:33:1387:40|Input RLAST_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1388:33:1388:41|Input RVALID_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1402:33:1402:42|Input AWREADY_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1409:33:1409:41|Input WREADY_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1411:58:1411:63|Input BID_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1412:33:1412:40|Input BRESP_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1413:33:1413:41|Input BVALID_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1425:33:1425:42|Input ARREADY_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1427:58:1427:63|Input RID_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1428:33:1428:40|Input RDATA_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1429:33:1429:40|Input RRESP_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1430:33:1430:40|Input RLAST_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1431:33:1431:41|Input RVALID_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1445:33:1445:42|Input AWREADY_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1452:33:1452:41|Input WREADY_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1454:58:1454:63|Input BID_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1455:33:1455:40|Input BRESP_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1456:33:1456:41|Input BVALID_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1468:33:1468:42|Input ARREADY_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1470:58:1470:63|Input RID_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1471:33:1471:40|Input RDATA_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1472:33:1472:40|Input RRESP_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1473:33:1473:40|Input RLAST_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1474:33:1474:41|Input RVALID_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1488:33:1488:42|Input AWREADY_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1495:33:1495:41|Input WREADY_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1497:58:1497:63|Input BID_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1498:33:1498:40|Input BRESP_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1499:33:1499:41|Input BVALID_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1511:33:1511:42|Input ARREADY_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1513:58:1513:63|Input RID_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1514:33:1514:40|Input RDATA_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1515:33:1515:40|Input RRESP_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1516:33:1516:40|Input RLAST_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1517:33:1517:41|Input RVALID_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1531:33:1531:42|Input AWREADY_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1538:33:1538:41|Input WREADY_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1540:58:1540:63|Input BID_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1541:33:1541:40|Input BRESP_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1542:33:1542:41|Input BVALID_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1554:33:1554:42|Input ARREADY_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1556:58:1556:63|Input RID_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1557:33:1557:40|Input RDATA_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1558:33:1558:40|Input RRESP_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1559:33:1559:40|Input RLAST_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1560:33:1560:41|Input RVALID_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1574:33:1574:42|Input AWREADY_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1581:33:1581:41|Input WREADY_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1583:58:1583:63|Input BID_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1584:33:1584:40|Input BRESP_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1585:33:1585:41|Input BVALID_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1597:33:1597:42|Input ARREADY_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1599:58:1599:63|Input RID_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1600:33:1600:40|Input RDATA_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1601:33:1601:40|Input RRESP_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1602:33:1602:40|Input RLAST_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1603:33:1603:41|Input RVALID_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1617:33:1617:42|Input AWREADY_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1624:33:1624:41|Input WREADY_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1626:58:1626:63|Input BID_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1627:33:1627:40|Input BRESP_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1628:33:1628:41|Input BVALID_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1640:33:1640:42|Input ARREADY_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1642:58:1642:63|Input RID_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1643:33:1643:40|Input RDATA_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1644:33:1644:40|Input RRESP_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1645:33:1645:40|Input RLAST_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1646:33:1646:41|Input RVALID_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1660:33:1660:42|Input AWREADY_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1667:33:1667:41|Input WREADY_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1669:58:1669:63|Input BID_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1670:33:1670:40|Input BRESP_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1671:33:1671:41|Input BVALID_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1683:33:1683:42|Input ARREADY_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1685:58:1685:63|Input RID_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1686:33:1686:40|Input RDATA_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1687:33:1687:40|Input RRESP_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1688:33:1688:40|Input RLAST_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1689:33:1689:41|Input RVALID_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1703:33:1703:43|Input AWREADY_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1710:33:1710:42|Input WREADY_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1712:58:1712:64|Input BID_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1713:33:1713:41|Input BRESP_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1714:33:1714:42|Input BVALID_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1726:33:1726:43|Input ARREADY_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1728:58:1728:64|Input RID_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1729:33:1729:41|Input RDATA_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1730:33:1730:41|Input RRESP_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1731:33:1731:41|Input RLAST_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1732:33:1732:42|Input RVALID_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1746:33:1746:43|Input AWREADY_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1753:33:1753:42|Input WREADY_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1755:58:1755:64|Input BID_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1756:33:1756:41|Input BRESP_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1757:33:1757:42|Input BVALID_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1769:33:1769:43|Input ARREADY_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1771:58:1771:64|Input RID_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1772:33:1772:41|Input RDATA_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1773:33:1773:41|Input RRESP_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1774:33:1774:41|Input RLAST_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1775:33:1775:42|Input RVALID_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1789:33:1789:43|Input AWREADY_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1796:33:1796:42|Input WREADY_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1798:58:1798:64|Input BID_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1799:33:1799:41|Input BRESP_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1800:33:1800:42|Input BVALID_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1812:33:1812:43|Input ARREADY_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1814:58:1814:64|Input RID_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1815:33:1815:41|Input RDATA_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1816:33:1816:41|Input RRESP_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1817:33:1817:41|Input RLAST_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1818:33:1818:42|Input RVALID_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1832:33:1832:43|Input AWREADY_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1839:33:1839:42|Input WREADY_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1841:58:1841:64|Input BID_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1842:33:1842:41|Input BRESP_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1843:33:1843:42|Input BVALID_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1855:33:1855:43|Input ARREADY_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1857:58:1857:64|Input RID_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1858:33:1858:41|Input RDATA_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1859:33:1859:41|Input RRESP_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1860:33:1860:41|Input RLAST_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1861:33:1861:42|Input RVALID_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1875:33:1875:43|Input AWREADY_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1882:33:1882:42|Input WREADY_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1884:58:1884:64|Input BID_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1885:33:1885:41|Input BRESP_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1886:33:1886:42|Input BVALID_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1898:33:1898:43|Input ARREADY_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1900:58:1900:64|Input RID_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1901:33:1901:41|Input RDATA_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1902:33:1902:41|Input RRESP_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1903:33:1903:41|Input RLAST_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1904:33:1904:42|Input RVALID_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1918:33:1918:43|Input AWREADY_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1925:33:1925:42|Input WREADY_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1927:58:1927:64|Input BID_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1928:33:1928:41|Input BRESP_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1929:33:1929:42|Input BVALID_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1941:33:1941:43|Input ARREADY_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1943:58:1943:64|Input RID_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1944:33:1944:41|Input RDATA_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1945:33:1945:41|Input RRESP_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1946:33:1946:41|Input RLAST_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1947:33:1947:42|Input RVALID_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1961:33:1961:43|Input AWREADY_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1968:33:1968:42|Input WREADY_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1970:58:1970:64|Input BID_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1971:33:1971:41|Input BRESP_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1972:33:1972:42|Input BVALID_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1984:33:1984:43|Input ARREADY_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1986:58:1986:64|Input RID_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1987:33:1987:41|Input RDATA_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1988:33:1988:41|Input RRESP_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1989:33:1989:41|Input RLAST_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1990:33:1990:42|Input RVALID_S16 is unused
@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused

@W: CL247 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused

@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":123:15:123:23|Input HBURST_M0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":124:15:124:22|Input HPROT_M0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":134:15:134:23|Input HBURST_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":135:15:135:22|Input HPROT_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":145:15:145:23|Input HBURST_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":146:15:146:22|Input HPROT_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":156:15:156:23|Input HBURST_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":157:15:157:22|Input HPROT_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":51:18:51:26|Input HWDATA_M1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":60:18:60:26|Input HWDATA_M2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":69:18:69:26|Input HWDATA_M3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":73:18:73:26|Input HRDATA_S0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":74:13:74:24|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":75:13:75:20|Input HRESP_S0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":84:18:84:26|Input HRDATA_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":85:13:85:24|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":86:13:86:20|Input HRESP_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":95:18:95:26|Input HRDATA_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":96:13:96:24|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":97:13:97:20|Input HRESP_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":106:18:106:26|Input HRDATA_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":107:13:107:24|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":108:13:108:20|Input HRESP_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":117:18:117:26|Input HRDATA_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":118:13:118:24|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":119:13:119:20|Input HRESP_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":128:18:128:26|Input HRDATA_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":129:13:129:24|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":130:13:130:20|Input HRESP_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":139:18:139:26|Input HRDATA_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":140:13:140:24|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":141:13:141:20|Input HRESP_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":150:18:150:26|Input HRDATA_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":151:13:151:24|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":152:13:152:20|Input HRESP_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":161:18:161:26|Input HRDATA_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":162:13:162:24|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":163:13:163:20|Input HRESP_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":172:18:172:26|Input HRDATA_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":173:13:173:24|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":174:13:174:20|Input HRESP_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":183:18:183:27|Input HRDATA_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":184:13:184:25|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":185:13:185:21|Input HRESP_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":194:18:194:27|Input HRDATA_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":195:13:195:25|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":196:13:196:21|Input HRESP_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":205:18:205:27|Input HRDATA_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":206:13:206:25|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":207:13:207:21|Input HRESP_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":216:18:216:27|Input HRDATA_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":217:13:217:25|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":218:13:218:21|Input HRESP_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":227:18:227:27|Input HRDATA_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":228:13:228:25|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":229:13:229:21|Input HRESP_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":238:18:238:27|Input HRDATA_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":239:13:239:25|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":240:13:240:21|Input HRESP_S15 is unused
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Trying to extract state machine for register arbRegSMCurrentState
Extracted state machine for register arbRegSMCurrentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input SDATAREADY is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input SHRESP is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":52:16:52:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":53:11:53:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":54:16:54:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":55:11:55:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":56:16:56:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":57:11:57:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":58:16:58:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":59:11:59:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S16 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S16 is unused
@W: CL246 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 15 to 0 of SDATAREADY[16:0] are unused

@W: CL246 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 15 to 0 of SHRESP[16:0] are unused

@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":52:16:52:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":53:11:53:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":54:16:54:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":55:11:55:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":56:16:56:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":57:11:57:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":58:16:58:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":59:11:59:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S15 is unused
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 29 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000101
   000110
   000111
   001001
   001010
   001011
   001100
   001101
   001110
   001111
   010000
   010001
   010010
   010011
   010100
   010101
   010110
   100000
   100001
   100010
   100011
   100100
   100101
   100110
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":871:0:871:5|Trying to extract state machine for register CUARTll0
Extracted state machine for register CUARTll0
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Trying to extract state machine for register CUARTl1ll
Extracted state machine for register CUARTl1ll
State machine has 6 reachable states with original encodings of:
   00000000000000000000000000000000
   00000000000000000000000000000001
   00000000000000000000000000000010
   00000000000000000000000000000011
   00000000000000000000000000000100
   00000000000000000000000000000101
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":81:0:81:7|Input CUARTI1I is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":84:0:84:7|Input CUARTlO1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":87:0:87:7|Input CUARTOI1 is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":75:0:75:16|Input BAUD_VAL_FRACTION is unused
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\Control_Logic.v":44:0:44:5|Trying to extract state machine for register fsm
Extracted state machine for register fsm
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
@W: CL260 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":108:0:108:5|Pruning register bit 9 of r_xfer_size[9:0] 

@W: CL279 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":108:0:108:5|Pruning register bits 3 to 1 of r_xfer_size[9:0] 

@W: CL260 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":70:0:70:5|Pruning register bit 9 of w_xfer_size[9:0] 

@W: CL279 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":70:0:70:5|Pruning register bits 3 to 1 of w_xfer_size[9:0] 

@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":70:0:70:5|Register bit w_xfer_size[0] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":108:0:108:5|Register bit r_xfer_size[0] is always 0, optimizing ...
@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":70:0:70:5|Pruning register w_xfer_size[0] 

@W: CL169 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v":108:0:108:5|Pruning register r_xfer_size[0] 

@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWADDR_int[0] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWADDR_int[1] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWADDR_int[2] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWADDR_int[3] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWADDR_int[4] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWADDR_int[5] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Optimizing register bit AWADDR_int[6] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Optimizing register bit ARADDR[0] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Optimizing register bit ARADDR[1] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Optimizing register bit ARADDR[2] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Optimizing register bit ARADDR[3] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Optimizing register bit ARADDR[4] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Optimizing register bit ARADDR[5] to a constant 0
@W: CL190 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Optimizing register bit ARADDR[6] to a constant 0
@W: CL279 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Pruning register bits 6 to 0 of ARADDR[31:0] 

@W: CL279 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Pruning register bits 6 to 0 of AWADDR_int[31:0] 

@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Register bit AWADDR[0] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Register bit AWADDR[1] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Register bit AWADDR[2] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Register bit AWADDR[3] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Register bit AWADDR[4] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Register bit AWADDR[5] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Register bit AWADDR[6] is always 0, optimizing ...
@W: CL279 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Pruning register bits 6 to 0 of AWADDR[31:0] 

@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":614:0:614:5|Trying to extract state machine for register axi_fsm_read1_state
Extracted state machine for register axi_fsm_read1_state
State machine has 3 reachable states with original encodings of:
   001
   011
   100
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Trying to extract state machine for register axi_fsm_read_state
Extracted state machine for register axi_fsm_read_state
State machine has 2 reachable states with original encodings of:
   001
   010
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":501:0:501:5|Trying to extract state machine for register ahb_state
Extracted state machine for register ahb_state
State machine has 2 reachable states with original encodings of:
   00
   01
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":446:0:446:5|Trying to extract state machine for register rt_state
Extracted state machine for register rt_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":388:0:388:5|Trying to extract state machine for register wt_state
Extracted state machine for register wt_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Trying to extract state machine for register axi_fsm_current_state
Extracted state machine for register axi_fsm_current_state
State machine has 4 reachable states with original encodings of:
   001
   010
   011
   100
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":225:0:225:5|Trying to extract state machine for register r_loop_state
Extracted state machine for register r_loop_state
State machine has 2 reachable states with original encodings of:
   00
   01
@N: CL201 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":183:0:183:5|Trying to extract state machine for register w_loop_state
Extracted state machine for register w_loop_state
State machine has 2 reachable states with original encodings of:
   00
   01
@W: CL260 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Pruning register bit 1 of AWSIZE[1:0] 

@W: CL260 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":556:0:556:5|Pruning register bit 1 of ARSIZE[1:0] 

@W: CL279 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":268:0:268:5|Pruning register bits 7 to 1 of WSTRB[7:0] 

@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":64:22:64:24|Input BID is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":65:21:65:25|Input BRESP is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":66:21:66:26|Input BVALID is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":81:23:81:25|Input RID is unused
@W: CL159 :"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v":83:23:83:27|Input RRESP is unused
