//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Sep 29 14:42:47 2015
// Version: v11.6 11.6.0.34
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// MDDR_TA_top
module MDDR_TA_top(
    // Inputs
    DEVRST_N,
    MDDR_DQS_TMATCH_0_IN,
    RX,
    // Outputs
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    TX,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DQ,
    MDDR_DQS
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         DEVRST_N;
input         MDDR_DQS_TMATCH_0_IN;
input         RX;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        TX;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [1:0]  MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0]  MDDR_DQS;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          AXI_IF_0_AXI_BUSY;
wire   [31:0] AXI_IF_0_BIF_1_ARADDR;
wire   [1:0]  AXI_IF_0_BIF_1_ARBURST;
wire   [3:0]  AXI_IF_0_BIF_1_ARID;
wire   [3:0]  AXI_IF_0_BIF_1_ARLEN;
wire   [1:0]  AXI_IF_0_BIF_1_ARLOCK;
wire          AXI_IF_0_BIF_1_ARREADY;
wire          AXI_IF_0_BIF_1_ARVALID;
wire   [31:0] AXI_IF_0_BIF_1_AWADDR;
wire   [1:0]  AXI_IF_0_BIF_1_AWBURST;
wire   [3:0]  AXI_IF_0_BIF_1_AWID;
wire   [3:0]  AXI_IF_0_BIF_1_AWLEN;
wire   [1:0]  AXI_IF_0_BIF_1_AWLOCK;
wire          AXI_IF_0_BIF_1_AWREADY;
wire   [2:0]  AXI_IF_0_BIF_1_AWSIZE;
wire          AXI_IF_0_BIF_1_AWVALID;
wire   [3:0]  AXI_IF_0_BIF_1_BID;
wire          AXI_IF_0_BIF_1_BREADY;
wire   [1:0]  AXI_IF_0_BIF_1_BRESP;
wire          AXI_IF_0_BIF_1_BVALID;
wire   [63:0] AXI_IF_0_BIF_1_RDATA;
wire   [3:0]  AXI_IF_0_BIF_1_RID;
wire          AXI_IF_0_BIF_1_RLAST;
wire          AXI_IF_0_BIF_1_RREADY;
wire   [1:0]  AXI_IF_0_BIF_1_RRESP;
wire          AXI_IF_0_BIF_1_RVALID;
wire   [63:0] AXI_IF_0_BIF_1_WDATA;
wire   [3:0]  AXI_IF_0_BIF_1_WID;
wire          AXI_IF_0_BIF_1_WLAST;
wire          AXI_IF_0_BIF_1_WREADY;
wire   [7:0]  AXI_IF_0_BIF_1_WSTRB;
wire          AXI_IF_0_BIF_1_WVALID;
wire   [2:0]  AXI_IF_0_WADDR;
wire   [15:0] AXI_IF_0_WD;
wire          AXI_IF_0_WEN;
wire   [9:0]  CMD_Decoder_0_r_xfer_size;
wire          CMD_Decoder_0_read_start;
wire   [9:0]  CMD_Decoder_0_w_xfer_size;
wire          CMD_Decoder_0_write_start;
wire   [7:0]  COM_Interface_0_COMMAND;
wire          DEVRST_N;
wire   [15:0] MDDR_ADDR_net_0;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_TA_0_HPMS_DDR_FIC_SUBSYSTEM_CLK;
wire          MDDR_TA_0_INIT_DONE;
wire          MDDR_WE_N_net_0;
wire          RX;
wire          TX_net_0;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire          TX_net_1;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
wire          GND_net;
wire   [3:0]  AMBA_MASTER_0_AWCACHE_M0_const_net_0;
wire   [2:0]  AMBA_MASTER_0_AWPROT_M0_const_net_0;
wire   [3:0]  AMBA_MASTER_0_ARCACHE_M0_const_net_0;
wire   [2:0]  AMBA_MASTER_0_ARPROT_M0_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [2:2]  AXI_IF_0_BIF_1_ARSIZE_0_2to2;
wire   [1:0]  AXI_IF_0_BIF_1_ARSIZE_0_1to0;
wire   [2:0]  AXI_IF_0_BIF_1_ARSIZE_0;
wire   [1:0]  AXI_IF_0_BIF_1_ARSIZE;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net                              = 1'b1;
assign GND_net                              = 1'b0;
assign AMBA_MASTER_0_AWCACHE_M0_const_net_0 = 4'h0;
assign AMBA_MASTER_0_AWPROT_M0_const_net_0  = 3'h0;
assign AMBA_MASTER_0_ARCACHE_M0_const_net_0 = 4'h0;
assign AMBA_MASTER_0_ARPROT_M0_const_net_0  = 3'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MDDR_DQS_TMATCH_0_OUT_net_1 = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT       = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1            = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                  = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1              = MDDR_CLK_net_0;
assign MDDR_CLK                    = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1            = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                  = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1              = MDDR_CKE_net_0;
assign MDDR_CKE                    = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1             = MDDR_CS_N_net_0;
assign MDDR_CS_N                   = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1              = MDDR_ODT_net_0;
assign MDDR_ODT                    = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1            = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                  = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1          = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1             = MDDR_WE_N_net_0;
assign MDDR_WE_N                   = MDDR_WE_N_net_1;
assign TX_net_1                    = TX_net_0;
assign TX                          = TX_net_1;
assign MDDR_ADDR_net_1             = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]             = MDDR_ADDR_net_1;
assign MDDR_BA_net_1               = MDDR_BA_net_0;
assign MDDR_BA[2:0]                = MDDR_BA_net_1;
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign AXI_IF_0_BIF_1_ARSIZE_0_2to2 = 1'b0;
assign AXI_IF_0_BIF_1_ARSIZE_0_1to0 = AXI_IF_0_BIF_1_ARSIZE[1:0];
assign AXI_IF_0_BIF_1_ARSIZE_0 = { AXI_IF_0_BIF_1_ARSIZE_0_2to2, AXI_IF_0_BIF_1_ARSIZE_0_1to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------AXI_IF
AXI_IF #( 
        .Bresp_0 ( 4 ),
        .Idle_0  ( 0 ),
        .Idle_1  ( 1 ),
        .Read_0  ( 2 ),
        .Read_1  ( 3 ),
        .Read_2  ( 4 ),
        .Write_0 ( 2 ),
        .Write_1 ( 3 ),
        .Write_2 ( 5 ) )
AXI_IF_0(
        // Inputs
        .CLK         ( MDDR_TA_0_HPMS_DDR_FIC_SUBSYSTEM_CLK ),
        .RESETn      ( MDDR_TA_0_INIT_DONE ),
        .write_start ( CMD_Decoder_0_write_start ),
        .read_start  ( CMD_Decoder_0_read_start ),
        .w_xfer_size ( CMD_Decoder_0_w_xfer_size ),
        .r_xfer_size ( CMD_Decoder_0_r_xfer_size ),
        .AWREADY     ( AXI_IF_0_BIF_1_AWREADY ),
        .WREADY      ( AXI_IF_0_BIF_1_WREADY ),
        .BID         ( AXI_IF_0_BIF_1_BID ),
        .BRESP       ( AXI_IF_0_BIF_1_BRESP ),
        .BVALID      ( AXI_IF_0_BIF_1_BVALID ),
        .ARREADY     ( AXI_IF_0_BIF_1_ARREADY ),
        .RID         ( AXI_IF_0_BIF_1_RID ),
        .RDATA       ( AXI_IF_0_BIF_1_RDATA ),
        .RRESP       ( AXI_IF_0_BIF_1_RRESP ),
        .RLAST       ( AXI_IF_0_BIF_1_RLAST ),
        .RVALID      ( AXI_IF_0_BIF_1_RVALID ),
        // Outputs
        .AXI_BUSY    ( AXI_IF_0_AXI_BUSY ),
        .WEN         ( AXI_IF_0_WEN ),
        .WADDR       ( AXI_IF_0_WADDR ),
        .WD          ( AXI_IF_0_WD ),
        .AWID        ( AXI_IF_0_BIF_1_AWID ),
        .AWADDR      ( AXI_IF_0_BIF_1_AWADDR ),
        .AWLEN       ( AXI_IF_0_BIF_1_AWLEN ),
        .AWSIZE      ( AXI_IF_0_BIF_1_AWSIZE ),
        .AWLOCK      ( AXI_IF_0_BIF_1_AWLOCK ),
        .AWBURST     ( AXI_IF_0_BIF_1_AWBURST ),
        .AWVALID     ( AXI_IF_0_BIF_1_AWVALID ),
        .WID         ( AXI_IF_0_BIF_1_WID ),
        .WSTRB       ( AXI_IF_0_BIF_1_WSTRB ),
        .WLAST       ( AXI_IF_0_BIF_1_WLAST ),
        .WVALID      ( AXI_IF_0_BIF_1_WVALID ),
        .WDATA       ( AXI_IF_0_BIF_1_WDATA ),
        .BREADY      ( AXI_IF_0_BIF_1_BREADY ),
        .ARID        ( AXI_IF_0_BIF_1_ARID ),
        .ARADDR      ( AXI_IF_0_BIF_1_ARADDR ),
        .ARLEN       ( AXI_IF_0_BIF_1_ARLEN ),
        .ARSIZE      ( AXI_IF_0_BIF_1_ARSIZE ),
        .ARLOCK      ( AXI_IF_0_BIF_1_ARLOCK ),
        .ARBURST     ( AXI_IF_0_BIF_1_ARBURST ),
        .ARVALID     ( AXI_IF_0_BIF_1_ARVALID ),
        .RREADY      ( AXI_IF_0_BIF_1_RREADY ) 
        );

//--------CMD_Decoder
CMD_Decoder CMD_Decoder_0(
        // Inputs
        .CLK         ( MDDR_TA_0_HPMS_DDR_FIC_SUBSYSTEM_CLK ),
        .RESETn      ( MDDR_TA_0_INIT_DONE ),
        .command     ( COM_Interface_0_COMMAND ),
        // Outputs
        .write_start ( CMD_Decoder_0_write_start ),
        .read_start  ( CMD_Decoder_0_read_start ),
        .w_xfer_size ( CMD_Decoder_0_w_xfer_size ),
        .r_xfer_size ( CMD_Decoder_0_r_xfer_size ) 
        );

//--------COM_Interface
COM_Interface COM_Interface_0(
        // Inputs
        .CLK      ( MDDR_TA_0_HPMS_DDR_FIC_SUBSYSTEM_CLK ),
        .RESET_N  ( MDDR_TA_0_INIT_DONE ),
        .RX       ( RX ),
        .AXI_BUSY ( AXI_IF_0_AXI_BUSY ),
        .WEN      ( AXI_IF_0_WEN ),
        .WD       ( AXI_IF_0_WD ),
        .WADDR    ( AXI_IF_0_WADDR ),
        // Outputs
        .TX       ( TX_net_0 ),
        .COMMAND  ( COM_Interface_0_COMMAND ) 
        );

//--------MDDR_TA
MDDR_TA MDDR_TA_0(
        // Inputs
        .MDDR_DQS_TMATCH_0_IN        ( MDDR_DQS_TMATCH_0_IN ),
        .FAB_RESET_N                 ( VCC_net ),
        .AMBA_MASTER_0_AWVALID_M0    ( AXI_IF_0_BIF_1_AWVALID ),
        .AMBA_MASTER_0_WLAST_M0      ( AXI_IF_0_BIF_1_WLAST ),
        .AMBA_MASTER_0_WVALID_M0     ( AXI_IF_0_BIF_1_WVALID ),
        .AMBA_MASTER_0_BREADY_M0     ( AXI_IF_0_BIF_1_BREADY ),
        .AMBA_MASTER_0_ARVALID_M0    ( AXI_IF_0_BIF_1_ARVALID ),
        .AMBA_MASTER_0_RREADY_M0     ( AXI_IF_0_BIF_1_RREADY ),
        .DEVRST_N                    ( DEVRST_N ),
        .MDDR_AXI_S_RMW              ( GND_net ),
        .AMBA_MASTER_0_AWID_M0       ( AXI_IF_0_BIF_1_AWID ),
        .AMBA_MASTER_0_AWADDR_M0     ( AXI_IF_0_BIF_1_AWADDR ),
        .AMBA_MASTER_0_AWLEN_M0      ( AXI_IF_0_BIF_1_AWLEN ),
        .AMBA_MASTER_0_AWSIZE_M0     ( AXI_IF_0_BIF_1_AWSIZE ),
        .AMBA_MASTER_0_AWBURST_M0    ( AXI_IF_0_BIF_1_AWBURST ),
        .AMBA_MASTER_0_AWLOCK_M0     ( AXI_IF_0_BIF_1_AWLOCK ),
        .AMBA_MASTER_0_AWCACHE_M0    ( AMBA_MASTER_0_AWCACHE_M0_const_net_0 ), // tied to 4'h0 from definition
        .AMBA_MASTER_0_AWPROT_M0     ( AMBA_MASTER_0_AWPROT_M0_const_net_0 ), // tied to 3'h0 from definition
        .AMBA_MASTER_0_WDATA_M0      ( AXI_IF_0_BIF_1_WDATA ),
        .AMBA_MASTER_0_WID_M0        ( AXI_IF_0_BIF_1_WID ),
        .AMBA_MASTER_0_WSTRB_M0      ( AXI_IF_0_BIF_1_WSTRB ),
        .AMBA_MASTER_0_ARID_M0       ( AXI_IF_0_BIF_1_ARID ),
        .AMBA_MASTER_0_ARADDR_M0     ( AXI_IF_0_BIF_1_ARADDR ),
        .AMBA_MASTER_0_ARLEN_M0      ( AXI_IF_0_BIF_1_ARLEN ),
        .AMBA_MASTER_0_ARSIZE_M0     ( AXI_IF_0_BIF_1_ARSIZE_0 ),
        .AMBA_MASTER_0_ARBURST_M0    ( AXI_IF_0_BIF_1_ARBURST ),
        .AMBA_MASTER_0_ARLOCK_M0     ( AXI_IF_0_BIF_1_ARLOCK ),
        .AMBA_MASTER_0_ARCACHE_M0    ( AMBA_MASTER_0_ARCACHE_M0_const_net_0 ), // tied to 4'h0 from definition
        .AMBA_MASTER_0_ARPROT_M0     ( AMBA_MASTER_0_ARPROT_M0_const_net_0 ), // tied to 3'h0 from definition
        // Outputs
        .MDDR_DQS_TMATCH_0_OUT       ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N                  ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK                    ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N                  ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE                    ( MDDR_CKE_net_0 ),
        .MDDR_CS_N                   ( MDDR_CS_N_net_0 ),
        .MDDR_ODT                    ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N                  ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N                ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N                   ( MDDR_WE_N_net_0 ),
        .POWER_ON_RESET_N            (  ),
        .INIT_DONE                   ( MDDR_TA_0_INIT_DONE ),
        .AMBA_MASTER_0_AWREADY_M0    ( AXI_IF_0_BIF_1_AWREADY ),
        .AMBA_MASTER_0_WREADY_M0     ( AXI_IF_0_BIF_1_WREADY ),
        .AMBA_MASTER_0_BVALID_M0     ( AXI_IF_0_BIF_1_BVALID ),
        .AMBA_MASTER_0_ARREADY_M0    ( AXI_IF_0_BIF_1_ARREADY ),
        .AMBA_MASTER_0_RLAST_M0      ( AXI_IF_0_BIF_1_RLAST ),
        .AMBA_MASTER_0_RVALID_M0     ( AXI_IF_0_BIF_1_RVALID ),
        .HPMS_DDR_FIC_SUBSYSTEM_CLK  ( MDDR_TA_0_HPMS_DDR_FIC_SUBSYSTEM_CLK ),
        .HPMS_DDR_FIC_SUBSYSTEM_LOCK (  ),
        .DDR_READY                   (  ),
        .FAB_CCC_GL0                 (  ),
        .FAB_CCC_LOCK                (  ),
        .HPMS_READY                  (  ),
        .COMM_BLK_INT                (  ),
        .MDDR_ADDR                   ( MDDR_ADDR_net_0 ),
        .MDDR_BA                     ( MDDR_BA_net_0 ),
        .AMBA_MASTER_0_BID_M0        ( AXI_IF_0_BIF_1_BID ),
        .AMBA_MASTER_0_BRESP_M0      ( AXI_IF_0_BIF_1_BRESP ),
        .AMBA_MASTER_0_RID_M0        ( AXI_IF_0_BIF_1_RID ),
        .AMBA_MASTER_0_RDATA_M0      ( AXI_IF_0_BIF_1_RDATA ),
        .AMBA_MASTER_0_RRESP_M0      ( AXI_IF_0_BIF_1_RRESP ),
        .HPMS_INT_M2F                (  ),
        // Inouts
        .MDDR_DM_RDQS                ( MDDR_DM_RDQS ),
        .MDDR_DQ                     ( MDDR_DQ ),
        .MDDR_DQS                    ( MDDR_DQS ) 
        );


endmodule
