#--  Synopsys, Inc.
#--  Version I-2013.09M-SP1 
#--  Project file D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\scratchproject.prs

#project files
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/hdl/AXI_IF.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/hdl/CMD_Decoder.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/hdl/Control_Logic.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_smartfusion2.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/CoreUART.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/COM_Interface/TPSRAM_0/COM_Interface_TPSRAM_0_TPSRAM.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/COM_Interface/COM_Interface.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/axi_interconnect.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/master_stage.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/slave_stage.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreConfigP/5.0.101/rtl/vlog/core/coreconfigp.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreResetP/5.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreResetP/5.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/SgCore/OSC/1.0.100/osc_comps.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS_syn.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/MDDR_TA/MDDR_TA.v"
add_file -verilog "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/component/work/MDDR_TA_top/MDDR_TA_top.v"



#implementation: "synthesis_1"
impl -add D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1 -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology IGLOO2
set_option -part M2GL010T
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "MDDR_TA_top"

# mapper_options
set_option -frequency 400.000000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -RWCheckOnRam 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -opcond COMWC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/synthesis/synthesis_1/MDDR_TA_top.edf"
impl -active "synthesis_1"
