onerror {resume}
radix define DDR_COMMAND {
    "3'b000" "LMR" -color "white",
    "3'b001" "AUTOREFRESH" -color "maroon",
    "3'b010" "PRECHARGE" -color "yellow",
    "3'b011" "ACTIVE" -color "pink",
    "3'b100" "WRITE" -color "cyan",
    "3'b101" "READ" -color "magenta",
    "3'b110" "BURST_T" -color "orange",
    "3'b111" "NOP" -color "gold",
    -default binary
    -defaultcolor white
}
radix define M3_COMMAND {
    "8'b00000000" "-" -color "maroon",
    "8'b00100100" "-" -color "maroon",
    "8'b00100101" "WRITE" -color "white",
    "8'b00100110" "READ" -color "yellow",
    -default binary
    -defaultcolor white
}
radix define COMMAND {
    "8'b00000000" "-" -color "maroon",
    "8'b00100100" "-" -color "maroon",
    "8'b00100101" "WRITE" -color "white",
    "8'b00100110" "READ" -color "yellow",
    -default binary
    -defaultcolor white
}
radix define COM_RX {
    "8'b01100011" "HANDSHAKE" -color "pink",
    "8'b00100101" "WRITE" -color "cyan",
    "8'b00100110" "READ" -color "magenta",
    -default binary
    -defaultcolor white
}
radix define COM_TX {
    "8'b01100001" "ACKNOWLEDGEMENT" -color "yellow",
    -default hexadecimal
    -defaultcolor white
}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {COM Interface Signals}
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/RX_RDY
add wave -noupdate -radix COM_RX /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/DATA_IN
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/OEN
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/TX_RDY
add wave -noupdate -radix COM_TX /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/DATA_OUT
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/WEN
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AXI_BUSY
add wave -noupdate /LPDDR_VIP_Simulation/BRCLK
add wave -noupdate /LPDDR_VIP_Simulation/TX
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/RAM_REN
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/RAM_RADDR
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/COM_Interface_0/Control_Logic_0/RAM_RD
add wave -noupdate -divider {MDDR Signals}
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_RESET_N
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_CLK
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_CKE
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_CS_N
add wave -noupdate -radix DDR_COMMAND /LPDDR_VIP_Simulation/COMMAND
add wave -noupdate -radix decimal /LPDDR_VIP_Simulation/MDDR_ADDR
add wave -noupdate -radix unsigned /LPDDR_VIP_Simulation/MDDR_BA
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_DM_RDQS
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_DQS
add wave -noupdate -radix decimal /LPDDR_VIP_Simulation/MDDR_DQ
add wave -noupdate -divider {AXI Master Signal}
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/CLK
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/RESETn
add wave -noupdate -radix COMMAND /LPDDR_VIP_Simulation/MDDR_TA_top_0/CMD_Decoder_0/command
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/write_start
add wave -noupdate -radix decimal -childformat {{{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[31]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[30]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[29]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[28]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[27]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[26]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[25]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[24]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[23]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[22]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[21]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[20]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[19]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[18]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[17]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[16]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[15]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[14]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[13]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[12]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[11]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[10]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[9]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[8]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[7]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[6]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[5]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[4]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[3]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[2]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[1]} -radix decimal} {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[0]} -radix decimal}} -subitemconfig {{/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[31]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[30]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[29]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[28]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[27]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[26]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[25]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[24]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[23]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[22]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[21]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[20]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[19]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[18]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[17]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[16]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[15]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[14]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[13]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[12]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[11]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[10]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[9]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[8]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[7]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[6]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[5]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[4]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[3]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[2]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[1]} {-height 15 -radix decimal} {/LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR[0]} {-height 15 -radix decimal}} /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWADDR
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWVALID
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/AWREADY
add wave -noupdate -radix decimal /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/WDATA
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/WVALID
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/WREADY
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/WLAST
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/BVALID
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/BREADY
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/read_start
add wave -noupdate -radix decimal /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/ARADDR
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/ARVALID
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/ARREADY
add wave -noupdate -radix decimal /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/RDATA
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/RVALID
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/RLAST
add wave -noupdate /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/RREADY
add wave -noupdate -radix decimal /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/WEN
add wave -noupdate -radix hexadecimal /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/WADDR
add wave -noupdate -radix decimal /LPDDR_VIP_Simulation/MDDR_TA_top_0/AXI_IF_0/WD
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2252699923 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 426
configure wave -valuecolwidth 54
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits fs
update
WaveRestoreZoom {2685932816 ps} {2824809430 ps}
