Synopsys Generic Technology Pre-mapping, Version map201503actrcp1, Build 002R, Built Jul  1 2015 06:58:23
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03M-3

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@L: D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top_scck.rpt 
Printing clock  summary report in "D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 139MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 139MB)


Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 139MB)


Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 139MB)

@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\hdl\axi_if.v":556:0:556:5|Removing sequential instance AXI_IF_0.ARBURST_1[0],  because it is equivalent to instance AXI_IF_0.ARSIZE_1[0]
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\hdl\axi_if.v":268:0:268:5|Removing sequential instance AXI_IF_0.AWBURST_1[0],  because it is equivalent to instance AXI_IF_0.AWSIZE_1[0]
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3580:2:3580:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3534:2:3534:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3488:2:3488:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3442:2:3442:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3396:2:3396:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3304:2:3304:13|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3258:2:3258:13|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3212:2:3212:13|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1613:0:1613:5|Removing sequential instance CUARTI0I of view:PrimLib.dffs(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1613:0:1613:5|Removing sequential instance CUARTIO0_1 of view:PrimLib.dffr(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":575:0:575:5|Removing sequential instance CUARTO11 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1430:0:1430:5|Removing sequential instance CUARTI11 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":653:0:653:5|Removing sequential instance CUARTI01 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2703:2:2703:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2767:2:2767:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2831:2:2831:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2890:1:2890:12|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":839:4:839:9|Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":871:0:871:5|Removing sequential instance CUARTllIl of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":871:0:871:5|Removing sequential instance CUARTO0Il of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":839:4:839:9|Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":87:56:87:68|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_0(verilog) because there are no references to its outputs 
syn_allowed_resources : blockrams=21  set on top level netlist MDDR_TA_top

Finished netlist restructuring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 166MB peak: 167MB)



@S |Clock Summary
*****************

Start                                                      Requested     Requested     Clock        Clock              
Clock                                                      Frequency     Period        Type         Group              
-----------------------------------------------------------------------------------------------------------------------
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_1
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_3
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock               100.0 MHz     10.000        inferred     Inferred_clkgroup_0
=======================================================================================================================

@W: MT530 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Found inferred clock MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreconfigmaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Found inferred clock MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock which controls 517 sequential elements including MDDR_TA_0.ConfigMaster_0.state[28:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found inferred clock MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including MDDR_TA_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\libero_11.6_migration\libero_designs\m2gl_ac424_new_without_workaround\libero_project\mddr_ta\hdl\axi_if.v":556:0:556:5|Found inferred clock MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock which controls 487 sequential elements including AXI_IF_0.ARADDR_1[31:7]. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 167MB)

Process took 0h:00m:04s realtime, 0h:00m:01s cputime
# Tue Sep 29 14:53:40 2015

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