#OPTIONS:"|-top|MDDR_TA_top|-prodtype|synplify_pro|-primux|-dspmac|-pqdpadd|-fixsmult|-divnmod|-nram|-I|D:\\Learning\\DDR\\Design\\IGL2\\v0.4\\MDDR_TA\\synthesis\\|-I|E:\\Microsemi\\Libero_v11.3\\Synopsys\\synplify_I201309MSP1\\lib|-v2001|-devicelib|E:\\Microsemi\\Libero_v11.3\\Synopsys\\synplify_I201309MSP1\\lib\\generic\\igloo2.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|work|-lib|work"
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#CUR:"D:\\Learning\\DDR\\Design\\IGL2\\v0.4\\MDDR_TA\\component\\Actel\\DirectCore\\CoreResetP\\5.1.100\\rtl\\vlog\\core\\coreresetp_pcie_hotreset.v":1394614624
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#CUR:"D:\\Learning\\DDR\\Design\\IGL2\\v0.4\\MDDR_TA\\component\\Actel\\DirectCore\\CoreAHBLite\\5.0.100\\rtl\\vlog\\core\\coreahblite_defaultslavesm.v":1395649385
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#numinternalfiles:5
#defaultlanguage:verilog
0			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v" verilog
1			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v" verilog
2			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\Control_Logic.v" verilog
3			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v" verilog
4			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v" verilog
5			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v" verilog
6			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_smartfusion2.v" verilog
7			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v" verilog
8			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v" verilog
9			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COM_Interface.v" verilog
10			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v" verilog
11			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v" verilog
12			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v" verilog
13			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v" verilog
14			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v" verilog
15			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v" verilog
16			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v" verilog
17			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" verilog
18			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v" verilog
19			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v" verilog
20			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v" verilog
21			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v" verilog
22			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v" verilog
23			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v" verilog
24			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v" verilog
25			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v" verilog
26			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v" verilog
27			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v" verilog
28			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v" verilog
29			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v" verilog
30			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v" verilog
31			"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v" verilog
#Dependency Lists(Uses List)
0 -1
1 -1
2 -1
3 -1
4 -1
5 -1
6 -1
7 3 4 5 6
8 -1
9 2 7 8
10 -1
11 -1
12 -1
13 -1
14 -1
15 12 13 14
16 -1
17 -1
18 17
19 -1
20 -1
21 -1
22 -1
23 -1
24 -1
25 23 24
26 -1
27 26
28 25 27
29 28
30 10 11 29 15 16 18 20 22
31 0 1 9 30
#Dependency Lists(Users Of)
0 31
1 31
2 9
3 7
4 7
5 7
6 7
7 9
8 9
9 31
10 30
11 30
12 15
13 15
14 15
15 30
16 30
17 18
18 30
19 -1
20 30
21 -1
22 30
23 25
24 25
25 28
26 27
27 28
28 29
29 30
30 31
31 -1
#Design Unit to File Association
module work AXI_IF 0
module work CMD_Decoder 1
module work Control_Logic 2
module work COM_Interface_COREUART_0_Clock_gen 3
module work COM_Interface_COREUART_0_Tx_async 4
module work COM_Interface_COREUART_0_Rx_async 5
module work COM_Interface_COREUART_0_fifo_ctrl_128 6
module work COM_Interface_COREUART_0_fifo_256x8 6
module work COM_Interface_COREUART_0_ram128x8_pa4 6
module work COM_Interface_COREUART_0_COREUART 7
module work COM_Interface_TPSRAM_0_TPSRAM 8
module work COM_Interface 9
module work MDDR_TA_CCC_0_FCCC 10
module work CoreConfigMaster 11
module work axi_interconnect 12
module work master_stage 13
module work slave_stage 14
module work MDDR_TA_COREAXI_0_COREAXI 15
module work CoreConfigP 16
module work coreresetp_pcie_hotreset 17
module work CoreResetP 18
module work RCOSC_1MHZ 19
module work RCOSC_25_50MHZ 19
module work XTLOSC 19
module work RCOSC_1MHZ_FAB 19
module work RCOSC_25_50MHZ_FAB 19
module work XTLOSC_FAB 19
module work MDDR_TA_FABOSC_0_OSC 20
module work MSS_010 21
module work MDDR_TA_HPMS 22
module work MDDR_TA 30
module work MDDR_TA_top 31
module COREAHBLITE_LIB COREAHBLITE_ADDRDEC 23
module COREAHBLITE_LIB COREAHBLITE_DEFAULTSLAVESM 24
module COREAHBLITE_LIB COREAHBLITE_MASTERSTAGE 25
module COREAHBLITE_LIB COREAHBLITE_SLAVEARBITER 26
module COREAHBLITE_LIB COREAHBLITE_SLAVESTAGE 27
module COREAHBLITE_LIB COREAHBLITE_MATRIX4X16 28
module COREAHBLITE_LIB CoreAHBLite 29
