<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREAXI</name><vendor>Actel</vendor><library>DirectCore</library><version>2.1.101</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\vlog\test\user\axi_master.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\test\user\axi_slave.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="2"><name>rtl\vlog\core\axi_interconnect.v</name><fileType>verilogSource</fileType></file><file fileid="3"><name>rtl\vlog\core\master_stage.v</name><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\vlog\core\slave_stage.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>