@P:  Worst Slack : -6.815
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Estimated Frequency : 123.4 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Requested Frequency : 400.0 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Estimated Period : 8.103
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Requested Period : 2.500
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Slack : -5.603
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Estimated Frequency : 107.4 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Requested Frequency : 400.0 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Estimated Period : 9.315
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Requested Period : 2.500
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Slack : -6.815
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Estimated Frequency : 400.2 MHz
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Requested Frequency : 400.0 MHz
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Estimated Period : 2.499
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Requested Period : 2.500
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Slack : 0.001
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Estimated Frequency : 161.8 MHz
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Requested Frequency : 400.0 MHz
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Estimated Period : 6.181
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Requested Period : 2.500
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Slack : -3.682
@P:  System - Estimated Frequency : 293.1 MHz
@P:  System - Requested Frequency : 400.0 MHz
@P:  System - Estimated Period : 3.412
@P:  System - Requested Period : 2.500
@P:  System - Slack : -0.912
@P:  Worst Slack(min analysis) : 0.315
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Estimated Frequency(min analysis) : 123.4 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Requested Frequency(min analysis) : 400.0 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Estimated Period(min analysis) : 8.103
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Requested Period(min analysis) : 2.500
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Slack(min analysis) : -5.603
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Estimated Frequency(min analysis) : 107.4 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Requested Frequency(min analysis) : 400.0 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Estimated Period(min analysis) : 9.315
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Requested Period(min analysis) : 2.500
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Slack(min analysis) : -6.815
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Estimated Frequency(min analysis) : 400.2 MHz
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Requested Frequency(min analysis) : 400.0 MHz
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Estimated Period(min analysis) : 2.499
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Requested Period(min analysis) : 2.500
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Slack(min analysis) : 0.001
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Estimated Frequency(min analysis) : 161.8 MHz
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Requested Frequency(min analysis) : 400.0 MHz
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Estimated Period(min analysis) : 6.181
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Requested Period(min analysis) : 2.500
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Slack(min analysis) : -3.682
@P:  System - Estimated Frequency(min analysis) : 507.2 MHz
@P:  System - Requested Frequency(min analysis) : 400.0 MHz
@P:  System - Estimated Period(min analysis) : 1.972
@P:  System - Requested Period(min analysis) : 2.500
@P:  System - Slack(min analysis) : 0.528
@P: MDDR_TA_top Part : m2gl010tfbga484-1
@P: MDDR_TA_top Register bits  : 956 
@P: MDDR_TA_top DSP Blocks  : 0
@P: MDDR_TA_top I/O primitives : 51
@P: MDDR_TA_top Block Rams (RAM1K18)  : 3
@P:  CPU Time : 0h:00m:14s
