// ****************************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation.  All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: slave_stage - Module defines interface with slave 
//
// Revision Information:
// Date            Description
// ----            -----------------------------------------
// 02Feb11         Inital. Ports and Parameters declaration
//
// SVN Revision Information:
// SVN $Revision: 11146 $
// SVN $Date: 2009-11-21 11:44:53 -0800 (Sat, 21 Nov 2009) $
//
// Resolved SARs
// SAR      Date     Who   Description
//
// Notes:
// 1. 
//
// ****************************************************************************/
`timescale 1ns/1ps
module slave_stage (
    // Global signals
    ACLK,
    ARESETN,

    // Interconnect
    // Write address channel signals
    AWID_IS,
    AWADDR_IS,
    AWLEN_IS,
    AWSIZE_IS,
    AWBURST_IS,
    AWLOCK_IS,
    AWCACHE_IS,
    AWPROT_IS,
    AWVALID_IS,
    AWREADY_SI,
    // Write data channel signals
    WID_IS,
    WDATA_IS,
    WSTRB_IS,
    WLAST_IS,
    WVALID_IS,
    WREADY_SI,
    // Write response channel signals
    BID_SI,
    BRESP_SI,
    BVALID_SI,
    BREADY_IS,
    // Read address channel signals
    ARID_IS,
    ARADDR_IS,
    ARLEN_IS,
    ARSIZE_IS,
    ARBURST_IS,
    ARLOCK_IS,
    ARCACHE_IS,
    ARPROT_IS,
    ARVALID_IS,
    ARREADY_SI,
    // Read response channel signals
    RID_SI,
    RDATA_SI,
    RRESP_SI,
    RLAST_SI,
    RVALID_SI,
    RREADY_IS,

    // SLAVE Side
    // AXI SLAVE write address channel signals
    AWID_S,
    AWADDR_S,
    AWLEN_S,
    AWSIZE_S,
    AWBURST_S,
    AWLOCK_S,
    AWCACHE_S,
    AWPROT_S,
    AWVALID_S,
    AWREADY_S,
    // AXI SLAVE write data channel signals
    WID_S,
    WDATA_S,
    WSTRB_S,
    WLAST_S,
    WVALID_S,
    WREADY_S,
    // AXI SLAVE write response channel signals
    BID_S,
    BRESP_S,
    BVALID_S,
    BREADY_S,
    // AXI SLAVE read address channel signals
    ARID_S,
    ARADDR_S,
    ARLEN_S,
    ARSIZE_S,
    ARBURST_S,
    ARLOCK_S,
    ARCACHE_S,
    ARPROT_S,
    ARVALID_S,
    ARREADY_S,
    // AXI SLAVE read response channel signals
    RID_S,
    RDATA_S,
    RRESP_S,
    RLAST_S,
    RVALID_S,
    RREADY_S

);

   // --------------------------------------------------------------------------
   // PARAMETER Declaration
   // --------------------------------------------------------------------------
   parameter AXI_AWIDTH           = 32;
   parameter AXI_DWIDTH           = 64;
   parameter AXI_STRBWIDTH        = AXI_DWIDTH/8;
   parameter NUM_SLAVE_SLOT       = 1;
   parameter ID_WIDTH             = 4;
   parameter BASE_ID_WIDTH        = 0;

   // --------------------------------------------------------------------------
   // I/O Declaration
   // --------------------------------------------------------------------------

   // Global signals
   input      ACLK;
   input      ARESETN;

   // MASTER 0
   // AXI MASTER 0 write address channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS;
   input [AXI_AWIDTH-1:0]        AWADDR_IS;
   input [3:0]                   AWLEN_IS;
   input [2:0]                   AWSIZE_IS;
   input [1:0]                   AWBURST_IS;
   input [1:0]                   AWLOCK_IS;
   input [3:0]                   AWCACHE_IS;
   input [2:0]                   AWPROT_IS;
   input                         AWVALID_IS;
   output                        AWREADY_SI;
   // AXI MASTER 0 write data channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS;
   input [AXI_DWIDTH-1:0]        WDATA_IS;
   input [AXI_STRBWIDTH-1:0]     WSTRB_IS;
   input                         WLAST_IS;
   input                         WVALID_IS;
   output                        WREADY_SI;
   // AXI MASTER 0 write response channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_SI;
   output [1:0]                  BRESP_SI;
   output                        BVALID_SI;
   input                         BREADY_IS;
   // AXI MASTER 0 read address channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS;
   input [AXI_AWIDTH-1:0]        ARADDR_IS;
   input [3:0]                   ARLEN_IS;
   input [2:0]                   ARSIZE_IS;
   input [1:0]                   ARBURST_IS;
   input [1:0]                   ARLOCK_IS;
   input [3:0]                   ARCACHE_IS;
   input [2:0]                   ARPROT_IS;
   input                         ARVALID_IS;
   output                        ARREADY_SI;
   // AXI MASTER 0 read response channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_SI;
   output [AXI_DWIDTH-1:0]       RDATA_SI;
   output [1:0]                  RRESP_SI;
   output                        RLAST_SI;
   output                        RVALID_SI;
   input                         RREADY_IS;

   // SLAVE Side
   // AXI SLAVE write address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_S;
   output [AXI_AWIDTH-1:0]      AWADDR_S;
   output [3:0]                 AWLEN_S;
   output [2:0]                 AWSIZE_S;
   output [1:0]                 AWBURST_S;
   output [1:0]                 AWLOCK_S;
   output [3:0]                 AWCACHE_S;
   output [2:0]                 AWPROT_S;
   output                       AWVALID_S;
   input                        AWREADY_S;
   // AXI SLAVE write data channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_S;
   output [AXI_DWIDTH-1:0]      WDATA_S;
   output [AXI_STRBWIDTH-1:0]   WSTRB_S;
   output                       WLAST_S;
   output                       WVALID_S;
   input                        WREADY_S;
   // AXI SLAVE write response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_S;
   input  [1:0]                 BRESP_S;
   input                        BVALID_S;
   output                       BREADY_S;
   // AXI SLAVE read address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_S;
   output [AXI_AWIDTH-1:0]      ARADDR_S;
   output [3:0]                 ARLEN_S;
   output [2:0]                 ARSIZE_S;
   output [1:0]                 ARBURST_S;
   output [1:0]                 ARLOCK_S;
   output [3:0]                 ARCACHE_S;
   output [2:0]                 ARPROT_S;
   output                       ARVALID_S;
   input                        ARREADY_S;
   // AXI SLAVE read response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_S;
   input  [AXI_DWIDTH-1:0]      RDATA_S;
   input  [1:0]                 RRESP_S;
   input                        RLAST_S;
   input                        RVALID_S;
   output                       RREADY_S;


   /////////////////////////////////////////////////////////////////////////////
   //                               Start - of - Code                         //
   /////////////////////////////////////////////////////////////////////////////

   // Write Address signals
   assign                       AWID_S     = AWID_IS;
   assign                       AWADDR_S   = AWADDR_IS;
   assign                       AWVALID_S  = AWVALID_IS;
   assign                       AWLEN_S    = AWLEN_IS;
   assign                       AWBURST_S  = AWBURST_IS;
   assign                       AWSIZE_S   = AWSIZE_IS;
   assign                       AWLOCK_S   = AWLOCK_IS;
   assign                       AWCACHE_S  = AWCACHE_IS;
   assign                       AWPROT_S   = AWPROT_IS;
   assign                       AWREADY_SI = AWREADY_S;
   
   // Write Data signals
   assign                       WID_S     = WID_IS;
   assign                       WDATA_S   = WDATA_IS;
   assign                       WVALID_S  = WVALID_IS;
   assign                       WLAST_S   = WLAST_IS;
   assign                       WSTRB_S   = WSTRB_IS;
   assign                       WREADY_SI = WREADY_S;

   // Read Address signals
   assign                       ARID_S     = ARID_IS;
   assign                       ARADDR_S   = ARADDR_IS;
   assign                       ARVALID_S  = ARVALID_IS;
   assign                       ARLEN_S    = ARLEN_IS;
   assign                       ARBURST_S  = ARBURST_IS;
   assign                       ARSIZE_S   = ARSIZE_IS;
   assign                       ARLOCK_S   = ARLOCK_IS;
   assign                       ARCACHE_S  = ARCACHE_IS;
   assign                       ARPROT_S   = ARPROT_IS;
   assign                       ARREADY_SI = ARREADY_S;

   // Write Response signals
   assign                       BID_SI    = BID_S;
   assign                       BRESP_SI  = BRESP_S;
   assign                       BVALID_SI = BVALID_S;
   assign                       BREADY_S  = BREADY_IS;

   // Read Data signals
   assign                       RID_SI    = RID_S;
   assign                       RDATA_SI  = RDATA_S;
   assign                       RRESP_SI  = RRESP_S;
   assign                       RVALID_SI = RVALID_S;
   assign                       RLAST_SI  = RLAST_S;
   assign                       RREADY_S  = RREADY_IS;


endmodule // slave_stage


   /////////////////////////////////////////////////////////////////////////////
   //                               End - of - Code                         //
   /////////////////////////////////////////////////////////////////////////////
