\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\bin64\m_generic.exe  -mp  1  -prjfile  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\scratchproject.prs  -implementation  synthesis  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis   -part M2GL010T  -package FBGA484  -grade -1    -maxfan 10000 -clock_globalthreshold 2 -async_globalthreshold 12 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMWC -report_path 0 -RWCheckOnRam 0 -summaryfile D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synlog\report\MDDR_TA_top_premap.xml  -top_level_module  MDDR_TA_top  -oedif  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.edn  -conchk_prepass  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top_cck_prepass.rpt   -freq 100.000   D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synwork\MDDR_TA_top_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synwork\MDDR_TA_top_prem.srd  -qsap  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.sap  -devicelib  \\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v  -ologparam  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\syntmp\MDDR_TA_top.plg  -osyn  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synwork\MDDR_TA_top_prem.srd  -prjdir  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\  -prjname  MDDR_TA_top_syn  -log  D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synlog\MDDR_TA_top_premap.srr 
rc:1 success:1
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\scratchproject.prs|o|1443518603|11134
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.edn|o|1442820947|2189718
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top_cck_prepass.rpt|o|0|0
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synwork\MDDR_TA_top_mult.srs|i|1443518615|13367
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synwork\MDDR_TA_top_prem.srd|o|1443518620|476354
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.sap|o|1443518620|62551
\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\generic\igloo2.v|i|1431621606|16387
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\syntmp\MDDR_TA_top.plg|o|1443518616|0
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synwork\MDDR_TA_top_prem.srd|o|1443518620|476354
D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\synlog\MDDR_TA_top_premap.srr|o|1443518620|27525
\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\bin\m_generic.exe|i|1435757632|15522304
\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\bin64\m_generic.exe|i|1435759172|26691584
