Implementation;Generate BitStream;RootName:MDDR_TA_top
Implementation;Generate BitStream||(null)||Please refer to the log file for details||MDDR_TA_top_generateBitstream.log;liberoaction://open_report/file/MDDR_TA_top_generateBitstream.log||(null);(null)
HelpInfo,\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\lib\html,fpgahelp.qhc,errormessages.mp,\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_J201503M-3\bin\mbin\assistant
Implementation;Synthesis;RootName:MDDR_TA_top
Implementation;Synthesis|| CG133 ||@W:No assignment to ARADDR_int||MDDR_TA_top.srr(92);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/92||AXI_IF.v(103);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/103
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit AWBURST[1] to a constant 0||MDDR_TA_top.srr(96);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/96||AXI_IF.v(268);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/268
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit AWSIZE[2] to a constant 0||MDDR_TA_top.srr(97);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/97||AXI_IF.v(268);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/268
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit WD[14] to a constant 0||MDDR_TA_top.srr(98);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/98||AXI_IF.v(501);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/501
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit WD[15] to a constant 0||MDDR_TA_top.srr(99);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/99||AXI_IF.v(501);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/501
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit ARBURST[1] to a constant 0||MDDR_TA_top.srr(100);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/100||AXI_IF.v(556);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/556
Implementation;Synthesis|| CL279 ||@W:Pruning register bits 15 to 14 of WD[15:0] ||MDDR_TA_top.srr(101);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/101||AXI_IF.v(501);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/501
Implementation;Synthesis|| CL260 ||@W:Pruning register bit 1 of AWBURST[1:0] ||MDDR_TA_top.srr(103);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/103||AXI_IF.v(268);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/268
Implementation;Synthesis|| CL260 ||@W:Pruning register bit 2 of AWSIZE[2:0] ||MDDR_TA_top.srr(105);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/105||AXI_IF.v(268);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/268
Implementation;Synthesis|| CL260 ||@W:Pruning register bit 1 of ARBURST[1:0] ||MDDR_TA_top.srr(107);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/107||AXI_IF.v(556);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v'/linenumber/556
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit CUARTII0l to a constant 1||MDDR_TA_top.srr(133);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/133||Tx_async.v(301);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v'/linenumber/301
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTII0l ||MDDR_TA_top.srr(134);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/134||Tx_async.v(301);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v'/linenumber/301
Implementation;Synthesis|| CG133 ||@W:No assignment to CUARTlI0||MDDR_TA_top.srr(160);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/160||CoreUART.v(333);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/333
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTO10 ||MDDR_TA_top.srr(161);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/161||CoreUART.v(1264);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/1264
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTOl0 ||MDDR_TA_top.srr(163);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/163||CoreUART.v(1155);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/1155
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTIl0 ||MDDR_TA_top.srr(165);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/165||CoreUART.v(1155);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/1155
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTIOl[7:0] ||MDDR_TA_top.srr(167);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/167||CoreUART.v(1102);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/1102
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTll0[1:0] ||MDDR_TA_top.srr(169);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/169||CoreUART.v(980);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/980
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTOI0 ||MDDR_TA_top.srr(171);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/171||CoreUART.v(932);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/932
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTlO0 ||MDDR_TA_top.srr(173);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/173||CoreUART.v(932);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/932
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTOO0 ||MDDR_TA_top.srr(175);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/175||CoreUART.v(884);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/884
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTl1l ||MDDR_TA_top.srr(177);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/177||CoreUART.v(884);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/884
Implementation;Synthesis|| CL169 ||@W:Pruning register CUARTIll ||MDDR_TA_top.srr(179);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/179||CoreUART.v(405);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v'/linenumber/405
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit HTRANS[0] to a constant 0||MDDR_TA_top.srr(240);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/240||coreconfigmaster.v(723);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v'/linenumber/723
Implementation;Synthesis|| CL260 ||@W:Pruning register bit 0 of HTRANS[1:0] ||MDDR_TA_top.srr(241);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/241||coreconfigmaster.v(723);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v'/linenumber/723
Implementation;Synthesis|| CG775 ||@W:Found Component CoreAHBLite in library COREAHBLITE_LIB||MDDR_TA_top.srr(243);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/243||coreahblite.v(23);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v'/linenumber/23
Implementation;Synthesis||null||@W:Ignoring localparam NUM_SLAVE_SLOT on the instance and using locally defined value||MDDR_TA_top.srr(471);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/471||MDDR_TA.v(1393);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v'/linenumber/1393
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWID_S1||MDDR_TA_top.srr(704);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/704||coreaxi.v(1307);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1307
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWADDR_S1||MDDR_TA_top.srr(706);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/706||coreaxi.v(1308);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1308
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWLEN_S1||MDDR_TA_top.srr(708);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/708||coreaxi.v(1309);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1309
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWSIZE_S1||MDDR_TA_top.srr(710);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/710||coreaxi.v(1310);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1310
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWBURST_S1||MDDR_TA_top.srr(712);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/712||coreaxi.v(1311);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1311
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWLOCK_S1||MDDR_TA_top.srr(714);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/714||coreaxi.v(1312);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1312
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWCACHE_S1||MDDR_TA_top.srr(716);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/716||coreaxi.v(1313);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1313
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWPROT_S1||MDDR_TA_top.srr(718);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/718||coreaxi.v(1314);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1314
Implementation;Synthesis|| CG360 ||@W:No assignment to wire AWVALID_S1||MDDR_TA_top.srr(720);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/720||coreaxi.v(1315);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1315
Implementation;Synthesis|| CG360 ||@W:No assignment to wire WID_S1||MDDR_TA_top.srr(722);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.srr'/linenumber/722||coreaxi.v(1318);liberoaction://cross_probe/hdl/file/'D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v'/linenumber/1318
Implementation;Synthesis||(null)||Please refer to the log file for details about 5594 Warning(s)||MDDR_TA_top.srr;liberoaction://open_report/file/MDDR_TA_top.srr||(null);(null)
Implementation;Compile;RootName:MDDR_TA_top
Implementation;Compile||(null)||Please refer to the log file for details about 7 Info(s)||MDDR_TA_top_compile_log.log;liberoaction://open_report/file/MDDR_TA_top_compile_log.log||(null);(null)
Implementation;Place and Route;RootName:MDDR_TA_top
Implementation;Place and Route||(null)||Please refer to the log file for details about 3 Info(s)||MDDR_TA_top_layout_log.log;liberoaction://open_report/file/MDDR_TA_top_layout_log.log||(null);(null)
Implementation;Generate Bitstream||(null)||Please refer to the log file for details||MDDR_TA_top_generateBitstream.log;liberoaction://open_report/file/MDDR_TA_top_generateBitstream.log||(null);(null)
Implementation;Generate Bitstream||(null)||Please refer to the log file for details about 2 Warning(s)||MDDR_TA_top_PROGRAM.log;liberoaction://open_report/file/MDDR_TA_top_PROGRAM.log||(null);(null)
Implementation;Generate Bitstream;RootName:MDDR_TA_top
Implementation;Generate Bitstream||(null)||Please refer to the log file for details||MDDR_TA_top_exportBitstream.log;liberoaction://open_report/file/MDDR_TA_top_exportBitstream.log||(null);(null)
