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0			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\AXI_IF.v" verilog
1			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v" verilog
2			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v" verilog
3			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v" verilog
4			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v" verilog
5			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_g4.v" verilog
6			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v" verilog
7			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v" verilog
8			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\hdl\Control_Logic.v" verilog
9			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\COM_Interface\COM_Interface.v" verilog
10			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.1.102\rtl\vlog\core\coreconfigmaster.v" verilog
11			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v" verilog
12			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" verilog
13			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" verilog
14			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v" verilog
15			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v" verilog
16			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v" verilog
17			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v" verilog
18			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v" verilog
19			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v" verilog
20			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v" verilog
21			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v" verilog
22			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v" verilog
23			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v" verilog
24			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v" verilog
25			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v" verilog
26			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v" verilog
27			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v" verilog
28			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v" verilog
29			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v" verilog
30			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v" verilog
31			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v" verilog
32			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v" verilog
33			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v" verilog
34			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v" verilog
35			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v" verilog
36			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.105\osc_comps.v" verilog
37			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v" verilog
38			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v" verilog
39			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v" verilog
40			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" verilog
41			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" verilog
42			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" verilog
43			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" verilog
44			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" verilog
45			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" verilog
46			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" verilog
47			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v" verilog
48			"D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v" verilog
#Dependency Lists(Uses List)
0 -1
1 -1
2 -1
3 -1
4 -1
5 -1
6 5 3 4 2
7 -1
8 -1
9 7 6 8
10 -1
11 -1
12 -1
13 12
14 -1
15 -1
16 -1
17 16
18 -1
19 18 17
20 -1
21 20
22 20
23 20
24 22 23 21
25 -1
26 25
27 25
28 25
29 27 28 26
30 -1
31 24 30 29
32 31 19
33 -1
34 -1
35 34 33 32 15
36 -1
37 36
38 -1
39 38
40 -1
41 -1
42 41 40
43 -1
44 43
45 44 42
46 45
47 39 37 13 11 35 46 10 14
48 47 9 1 0
#Dependency Lists(Users Of)
0 48
1 48
2 6
3 6
4 6
5 6
6 9
7 9
8 9
9 48
10 47
11 47
12 13
13 47
14 47
15 35
16 17
17 19
18 19
19 32
20 23 22 21
21 24
22 24
23 24
24 31
25 28 27 26
26 29
27 29
28 29
29 31
30 31
31 32
32 35
33 35
34 35
35 47
36 37
37 47
38 39
39 47
40 42
41 42
42 45
43 44
44 45
45 46
46 47
47 48
48 -1
#Design Unit to File Association
module COREAHBLITE_LIB CoreAHBLite 46
module COREAHBLITE_LIB COREAHBLITE_MATRIX4X16 45
module COREAHBLITE_LIB COREAHBLITE_SLAVESTAGE 44
module COREAHBLITE_LIB COREAHBLITE_SLAVEARBITER 43
module COREAHBLITE_LIB COREAHBLITE_MASTERSTAGE 42
module COREAHBLITE_LIB COREAHBLITE_DEFAULTSLAVESM 41
module COREAHBLITE_LIB COREAHBLITE_ADDRDEC 40
module work MDDR_TA_top 48
module work MDDR_TA 47
module work MDDR_TA_HPMS 39
module work MSS_010 38
module work MDDR_TA_FABOSC_0_OSC 37
module work XTLOSC_FAB 36
module work RCOSC_25_50MHZ_FAB 36
module work RCOSC_1MHZ_FAB 36
module work XTLOSC 36
module work RCOSC_25_50MHZ 36
module work RCOSC_1MHZ 36
module work MDDR_TA_COREAXI_0_COREAXI 35
module work axi_slave_stage 34
module work axi_master_stage 33
module work axi_interconnect_ntom 32
module work axi_matrix_s 31
module work axi_wd_channel 30
module work axi_wa_channel 29
module work axi_wrmatrix_4Mto1S_hgs_low 28
module work axi_wrmatrix_4Mto1S_hgs_high 27
module work axi_wrmatrix_4Mto1S 26
module work axi_WA_ARBITER 25
module work axi_ra_channel 24
module work axi_rdmatrix_4Mto1S_hgs_low 23
module work axi_rdmatrix_4Mto1S_hgs_high 22
module work axi_rdmatrix_4Mto1S 21
module work axi_RA_ARBITER 20
module work axi_matrix_m 19
module work axi_wresp_channel 18
module work axi_rd_channel 17
module work axi_rdmatrix_16Sto1M 16
module work axi_feedthrough 15
module work MDDR_TA_CCC_0_FCCC 14
module work CoreResetP 13
module work coreresetp_pcie_hotreset 12
module work CoreConfigP 11
module work CoreConfigMaster 10
module work COM_Interface 9
module work Control_Logic 8
module work COM_Interface_TPSRAM_0_TPSRAM 7
module work COM_Interface_COREUART_0_COREUART 6
module work COM_Interface_COREUART_0_ram128x8_pa4 5
module work COM_Interface_COREUART_0_fifo_256x8 5
module work COM_Interface_COREUART_0_fifo_ctrl_128 5
module work COM_Interface_COREUART_0_Tx_async 4
module work COM_Interface_COREUART_0_Rx_async 3
module work COM_Interface_COREUART_0_Clock_gen 2
module work CMD_Decoder 1
module work AXI_IF 0
