E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\c_ver.exe  -osyn  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_comp.srs  -top  MDDR_TA_top  -prodtype  synplify_pro  -primux -dspmac -pqdpadd -fixsmult   -divnmod -nram -I D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\  -I E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib  -v2001  -devicelib  E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v  -encrypt  -pro  -dmgen  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\dm  -ui -fid2 -ram -sharing on  -ll 2000 -autosm -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\Control_Logic.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_smartfusion2.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COM_Interface.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v -lib COREAHBLITE_LIB D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v -lib COREAHBLITE_LIB D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v -lib COREAHBLITE_LIB D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v -lib COREAHBLITE_LIB D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v -lib COREAHBLITE_LIB D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v -lib COREAHBLITE_LIB D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v -lib COREAHBLITE_LIB D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v -lib work D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v -loga  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.srr 
rc:1 success:1
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_comp.srs|o|1395903011|439041
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v|i|1389673372|16295
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v|i|1395683545|15895
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v|i|1395653503|3128
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\Control_Logic.v|i|1395726782|5101
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v|i|1395763892|6129
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v|i|1395763892|5226
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v|i|1395763892|9465
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_smartfusion2.v|i|1395763892|6012
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v|i|1395763892|9057
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v|i|1395763898|2007
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COM_Interface.v|i|1395763899|5128
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v|i|1395846717|1807
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v|i|1395649333|20578
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v|i|1395649385|393476
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v|i|1395649385|33747
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v|i|1395649385|9697
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v|i|1395846720|220372
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v|i|1395223939|24497
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v|i|1394614624|8822
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v|i|1394614624|63299
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v|i|1394614626|924
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v|i|1395846723|645
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v|i|1395846707|66569
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v|i|1395846710|79333
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v|i|1395649385|6867
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v|i|1395649385|2175
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v|i|1395649385|16975
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v|i|1395649385|14771
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v|i|1395649385|8597
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v|i|1395649385|208467
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v|i|1395649385|21688
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v|i|1395846724|94353
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v|i|1395846763|15277
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.srr|o|1395903011|252747
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\c_ver.exe|i|1389638658|5733376
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin\c_ver.exe|i|1389638444|2205696
