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<datasheet>
  <header>COM_Interface</header>
  <project-settings>
    <fam>IGLOO2</fam>
    <die>M2GL010T</die>
    <package>484 FBGA</package>
    <speed-grade>-1</speed-grade>
    <voltage>1.2</voltage>
    <hdl-type>Verilog</hdl-type>
    <project-description>
    </project-description>
    <location>D:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/component/work/COM_Interface</location>
    <state>GENERATED ( Mon Mar 24 14:28:27 2014 )</state>
    <swide-toolchain>SoftConsole workspace has not been generated</swide-toolchain>
  </project-settings>
  <site-map>
  </site-map>
  <fileset>
    <name>HDL File(s)</name>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\COM_Interface\COM_Interface.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_smartfusion2.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_pre.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v</file>
    <file>D:\Learning\DDR\Design\IGL2\v0.1\MDDR_TA\hdl\Control_Logic.v</file>
  </fileset>
  <core type="HdlModule">
    <core-type>HdlModule</core-type>
    <core-exttype>Control_Logic</core-exttype>
    <core-location>hdl\Control_Logic.v</core-location>
    <core-name>Control_Logic_0</core-name>
  </core>
  <core type="SpiritModule">
    <core-exttype>IP</core-exttype>
    <core-type>SpiritModule</core-type>
    <core-vendor>Actel</core-vendor>
    <core-lib>DirectCore</core-lib>
    <core-intname>COREUART</core-intname>
    <core-ver>5.2.2</core-ver>
    <core-desc>CoreUART is a serial communication controller with a flexible serial data interface that is intended primarily for embedded systems. The controller operates in an asynchronous (UART)  The core includes a user testbench to show sample UART operation.</core-desc>
    <core-param>
      <param-name>Enabled Extra Precision:</param-name>
      <param-value>false</param-value>
      <param-hdlname>BAUD_VAL_FRCTN_EN</param-hdlname>
      <param-hdlvalue>0</param-hdlvalue>
      <param-tag>spirit:hwParameter</param-tag>
    </core-param>
    <core-param>
      <param-name>FPGA Family:</param-name>
      <param-value>SmartFusion2</param-value>
      <param-hdlname>FAMILY</param-hdlname>
      <param-hdlvalue>19</param-hdlvalue>
      <param-tag>spirit:hwParameter</param-tag>
    </core-param>
    <core-param>
      <param-name>RX FIFO:</param-name>
      <param-value>Disable RX FIFO</param-value>
      <param-hdlname>RX_FIFO</param-hdlname>
      <param-hdlvalue>0</param-hdlvalue>
      <param-tag>spirit:hwParameter</param-tag>
    </core-param>
    <core-param>
      <param-name>RX Legacy Mode:</param-name>
      <param-value>Disabled</param-value>
      <param-hdlname>RX_LEGACY_MODE</param-hdlname>
      <param-hdlvalue>0</param-hdlvalue>
      <param-tag>spirit:hwParameter</param-tag>
    </core-param>
    <core-param>
      <param-name>TX FIFO:</param-name>
      <param-value>Disable TX FIFO</param-value>
      <param-hdlname>TX_FIFO</param-hdlname>
      <param-hdlvalue>0</param-hdlvalue>
      <param-tag>spirit:hwParameter</param-tag>
    </core-param>
    <core-name>COREUART_0</core-name>
  </core>
  <core type="SpiritModule">
    <core-exttype>IP</core-exttype>
    <core-type>SpiritModule</core-type>
    <core-vendor>Actel</core-vendor>
    <core-lib>SgCore</core-lib>
    <core-intname>TPSRAM</core-intname>
    <core-ver>1.0.101</core-ver>
    <core-desc>SmartFusion2 Two-Port Large SRAM</core-desc>
    <core-name>TPSRAM_0</core-name>
  </core>
  <memorysystem>
    <title>Memory Map for COM_Interface</title>
    <description>The project does not contain any subsystems.</description>
  </memorysystem>
</datasheet>
