#1000 define_clock {n:MDDR_TA_0.MDDR_TA_HPMS_0.FIC_2_APB_M_PCLK} -name {MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock} -ref_rise {0.000000} -ref_fall {1.250000} -uncertainty {0.000000} -period {2.500000} -clockgroup {Inferred_clkgroup_0} -rise {0.000000} -fall {1 . . . 
#1001 define_clock {n:MDDR_TA_0.CCC_0.GL0_net} -name {MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock} -ref_rise {0.000000} -ref_fall {1.250000} -uncertainty {0.000000} -period {2.500000} -clockgroup {Inferred_clkgroup_1} -rise {0.000000} -fall {1.250000}
#1002 define_clock {n:MDDR_TA_0.FABOSC_0.RCOSC_25_50MHZ_CCC} -name {MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock} -ref_rise {0.000000} -ref_fall {1.250000} -uncertainty {0.000000} -period {2.500000} -clockgroup {Inferred_clkgroup_2} -rise {0.000000} -f . . . 
#1003 define_clock {n:MDDR_TA_0.CCC_0.GL2_net} -name {MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock} -ref_rise {0.000000} -ref_fall {1.250000} -uncertainty {0.000000} -period {2.500000} -clockgroup {Inferred_clkgroup_3} -rise {0.000000} -fall {1.250000}
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_0_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_1_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_2_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_3_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_4_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_5_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_6_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_7_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_8_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_9_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_10_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_11_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_12_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_13_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_14_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ADDR_15_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_BA_0_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_BA_1_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_BA_2_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_CAS_N_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_CKE_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_CS_N_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DM_RDQS_0_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DM_RDQS_1_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_0_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_1_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_2_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_3_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_4_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_5_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_6_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_7_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_8_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_9_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_10_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_11_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_12_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_13_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_14_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQ_15_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQS_0_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQS_1_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQS_TMATCH_0_IN_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_DQS_TMATCH_0_OUT_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_ODT_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_RAS_N_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_RESET_N_PAD}  {syn_noprune} 1
define_attribute {i:MDDR_TA_0.MDDR_TA_HPMS_0.MDDR_WE_N_PAD}  {syn_noprune} 1
