BATCH:T
MGNCMPL:F
MGNTIMER:F
GEN_BEHV_MODULE:F
DESDIR:D:\Libero_11.6_migration\Libero_designs\M2GL_AC424_DF\Libero_Project\MDDR_TA\component\work\COM_Interface\TPSRAM_0\
DESIGN:COM_Interface_TPSRAM_0_TPSRAM
OUTFORMAT:Verilog
RESET_POLARITY:2
A_DOUT_EN_PN:RD_EN
A_DOUT_EN_POLARITY:2
A_DOUT_SRST_PN:RD_SRST_N
A_DOUT_SRST_POLARITY:2
CASCADE:0
CLKS:1
WCLK_EDGE:RISE
CLOCK_PN:CLK
DATA_IN_PN:WD
DATA_OUT_PN:RD
FAM:IGLOO2
INIT_RAM:F
LPMTYPE:LPM_RAM
PTYPE:1
RADDRESS_PN:RADDR
RCLK_EDGE:RISE
RCLOCK_PN:RCLK
RDEPTH:16
RESET_PN:ARST_N
RE_PN:REN
RE_POLARITY:1
PMODE2:0
RWIDTH:8
SD_EXPORT_HIDDEN_PORTS:false
WADDRESS_PN:WADDR
WCLOCK_PN:WCLK
WDEPTH:8
WE_PN:WEN
WE_POLARITY:1
WWIDTH:16
DEVICE:1000
