<?xml version="1.0" encoding="ISO-8859-1" ?>
<?xml-stylesheet type="text/xsl" href="datasheet.xsl"?>
<datasheet>
  <header>MDDR_TA_top</header>
  <project-settings>
    <fam>IGLOO2</fam>
    <die>M2GL010T</die>
    <package>484 FBGA</package>
    <speed-grade>-1</speed-grade>
    <voltage>1.2</voltage>
    <hdl-type>Verilog</hdl-type>
    <project-description>
    </project-description>
    <location>D:/Learning/DDR/Design/IGL2/Sim_Board/DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_top</location>
    <state>GENERATED ( Wed May 28 20:02:18 2014 )</state>
    <swide-toolchain>SoftConsole workspace has not been generated</swide-toolchain>
  </project-settings>
  <site-map>
  </site-map>
  <fileset>
    <name>HDL File(s)</name>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COM_Interface.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\fifo_256x8_smartfusion2.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_pre.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\hdl\AXI_IF.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\hdl\CMD_Decoder.v</file>
    <file>D:\Learning\DDR\Design\IGL2\Sim_Board\DF\Libero_Project\MDDR_TA\hdl\Control_Logic.v</file>
  </fileset>
  <core>
    <core-name>AXI_IF_0</core-name>
  </core>
  <core type="HdlModule">
    <core-type>HdlModule</core-type>
    <core-exttype>CMD_Decoder</core-exttype>
    <core-location>hdl\CMD_Decoder.v</core-location>
    <core-name>CMD_Decoder_0</core-name>
  </core>
  <core type="ComponentModule">
    <core-type>ComponentModule</core-type>
    <core-exttype>SmartDesign</core-exttype>
    <core-location>D:/Learning/DDR/Design/IGL2/Sim_Board/DF/Libero_Project/MDDR_TA/component/work/COM_Interface</core-location>
    <core-name>COM_Interface_0</core-name>
  </core>
  <core type="ComponentModule">
    <core-type>ComponentModule</core-type>
    <core-exttype>SysBldDesign</core-exttype>
    <core-location>D:/Learning/DDR/Design/IGL2/Sim_Board/DF/Libero_Project/MDDR_TA/component/work/MDDR_TA</core-location>
    <core-name>MDDR_TA_0</core-name>
  </core>
  <memorysystem>
    <title>Memory Map for MDDR_TA_top</title>
    <description>The project contains the following subsystems:</description>
    <subsystems>
      <subsystem>
        <name>HPMS_MASTERS</name>
        <master>HPMS_MASTERS</master>
        <master>FAB_TO_FIC_2</master>
        <master>FAB_TO_FIC_0_AHB_BRIDGE</master>
        <addressNames>
          <count>1</count>
          <name>
          </name>
        </addressNames>
        <slave>
          <name>FIC_REGION_5</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xF0000000</remapAddress>
          <fullAddressSpace>0xF0000000 - 0xFFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>DDR_0_SPACE_3</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xD0000000</remapAddress>
          <fullAddressSpace>0xD0000000 - 0xDFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>DDR_0_SPACE_2</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xC0000000</remapAddress>
          <fullAddressSpace>0xC0000000 - 0xCFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>DDR_0_SPACE_1</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xB0000000</remapAddress>
          <fullAddressSpace>0xB0000000 - 0xBFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>DDR_0_SPACE_0</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xA0000000</remapAddress>
          <fullAddressSpace>0xA0000000 - 0xAFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>FIC_REGION_4</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x90000000</remapAddress>
          <fullAddressSpace>0x90000000 - 0x9FFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>FIC_REGION_3</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x80000000</remapAddress>
          <fullAddressSpace>0x80000000 - 0x8FFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>AHB_TO_ENVM_1_REGISTERS</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x600C0000</remapAddress>
          <fullAddressSpace>0x600C0000 - 0x600FFFFF</fullAddressSpace>
          <range>0x00040000</range>
        </slave>
        <slave>
          <name>AHB_TO_ENVM_0_REGISTERS</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x60080000</remapAddress>
          <fullAddressSpace>0x60080000 - 0x600BFFFF</fullAddressSpace>
          <range>0x00040000</range>
        </slave>
        <slave>
          <name>ENVM_1</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x60040000</remapAddress>
          <fullAddressSpace>0x60040000 - 0x6007FFFF</fullAddressSpace>
          <range>0x00040000</range>
        </slave>
        <slave>
          <name>ENVM_0</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x60000000</remapAddress>
          <fullAddressSpace>0x60000000 - 0x6003FFFF</fullAddressSpace>
          <range>0x00040000</range>
        </slave>
        <slave>
          <name>FIC_REGION_1</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x50000000</remapAddress>
          <fullAddressSpace>0x50000000 - 0x5FFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>SYSREG</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40038000</remapAddress>
          <fullAddressSpace>0x40038000 - 0x40038FFF</fullAddressSpace>
          <range>0x00001000</range>
        </slave>
        <slave>
          <name>CFGM</name>
          <fullPinName>MDDR_TA_HPMS_0:MDDR_APB_SLAVE</fullPinName>
          <remapAddress>0x40020800</remapAddress>
          <fullAddressSpace>0x40020800 - 0x40020FFF</fullAddressSpace>
          <range>0x800</range>
        </slave>
        <slave>
          <name>COMM_BLK</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40016000</remapAddress>
          <fullAddressSpace>0x40016000 - 0x40016FFF</fullAddressSpace>
          <range>0x1000</range>
        </slave>
        <slave>
          <name>HPDMA</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40014000</remapAddress>
          <fullAddressSpace>0x40014000 - 0x40014FFF</fullAddressSpace>
          <range>0x1000</range>
        </slave>
        <slave>
          <name>H2FINTERRUPT</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40006000</remapAddress>
          <fullAddressSpace>0x40006000 - 0x40006FFF</fullAddressSpace>
          <range>0x1000</range>
        </slave>
        <slave>
          <name>PDMA</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40003000</remapAddress>
          <fullAddressSpace>0x40003000 - 0x40003FFF</fullAddressSpace>
          <range>0x1000</range>
        </slave>
        <slave>
          <name>ESRAM_1</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x20008000</remapAddress>
          <fullAddressSpace>0x20008000 - 0x2000FFFF</fullAddressSpace>
          <range>0x00008000</range>
        </slave>
        <slave>
          <name>ESRAM_0</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x20080000</remapAddress>
          <fullAddressSpace>0x20080000 - 0x20087FFF</fullAddressSpace>
          <range>0x00008000</range>
        </slave>
      </subsystem>
      <subsystem>
        <name>ConfigMaster_0</name>
        <master>ConfigMaster_0</master>
        <addressNames>
          <count>1</count>
          <name>
          </name>
        </addressNames>
        <slave>
          <name>FIC32_0</name>
          <fullPinName>MDDR_TA_HPMS_0:FIC_0_AHB_SLAVE</fullPinName>
          <remapAddress>0x80000000</remapAddress>
          <fullAddressSpace>0x80000000 - 0x7FFFFFFF</fullAddressSpace>
          <range>0x00000000</range>
        </slave>
      </subsystem>
    </subsystems>
  </memorysystem>
</datasheet>
