@P:  Worst Slack : 1.890
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Estimated Frequency : 123.3 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Requested Frequency : 100.0 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Estimated Period : 8.110
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Requested Period : 10.000
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Slack : 1.890
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Estimated Frequency : 161.5 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Requested Frequency : 100.0 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Estimated Period : 6.191
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Requested Period : 10.000
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Slack : 3.809
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Estimated Frequency : 417.3 MHz
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Requested Frequency : 100.0 MHz
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Estimated Period : 2.396
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Requested Period : 10.000
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Slack : 7.604
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Estimated Frequency : 143.4 MHz
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Requested Frequency : 100.0 MHz
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Estimated Period : 6.971
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Requested Period : 10.000
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Slack : 2.274
@P:  Worst Slack(min analysis) : 0.278
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Estimated Frequency(min analysis) : 123.3 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Requested Frequency(min analysis) : 100.0 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Estimated Period(min analysis) : 8.110
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Requested Period(min analysis) : 10.000
@P:  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock - Slack(min analysis) : 1.890
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Estimated Frequency(min analysis) : 161.5 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Requested Frequency(min analysis) : 100.0 MHz
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Estimated Period(min analysis) : 6.191
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Requested Period(min analysis) : 10.000
@P:  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock - Slack(min analysis) : 3.809
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Estimated Frequency(min analysis) : 417.3 MHz
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Requested Frequency(min analysis) : 100.0 MHz
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Estimated Period(min analysis) : 2.396
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Requested Period(min analysis) : 10.000
@P:  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock - Slack(min analysis) : 7.604
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Estimated Frequency(min analysis) : 143.4 MHz
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Requested Frequency(min analysis) : 100.0 MHz
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Estimated Period(min analysis) : 6.971
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Requested Period(min analysis) : 10.000
@P:  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock - Slack(min analysis) : 2.274
@P: MDDR_TA_top Part : m2gl010tfbga484-1
@P: MDDR_TA_top Register bits  : 963 
@P: MDDR_TA_top DSP Blocks  : 0
@P: MDDR_TA_top I/O primitives : 51
@P: MDDR_TA_top Block Rams (RAM1K18) :  3
@P:  CPU Time : 0h:00m:11s
