Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 150MB)

@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1531:33:1531:42|Tristate driver RREADY_S15 on net RREADY_S15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1523:33:1523:43|Tristate driver ARVALID_S15 on net ARVALID_S15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1522:33:1522:42|Tristate driver ARPROT_S15_1 on net ARPROT_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1522:33:1522:42|Tristate driver ARPROT_S15_2 on net ARPROT_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1522:33:1522:42|Tristate driver ARPROT_S15_3 on net ARPROT_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1521:33:1521:43|Tristate driver ARCACHE_S15_1 on net ARCACHE_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1521:33:1521:43|Tristate driver ARCACHE_S15_2 on net ARCACHE_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1521:33:1521:43|Tristate driver ARCACHE_S15_3 on net ARCACHE_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1521:33:1521:43|Tristate driver ARCACHE_S15_4 on net ARCACHE_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1520:33:1520:42|Tristate driver ARLOCK_S15_1 on net ARLOCK_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1520:33:1520:42|Tristate driver ARLOCK_S15_2 on net ARLOCK_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1519:33:1519:43|Tristate driver ARBURST_S15_1 on net ARBURST_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1519:33:1519:43|Tristate driver ARBURST_S15_2 on net ARBURST_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1518:33:1518:42|Tristate driver ARSIZE_S15_1 on net ARSIZE_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1518:33:1518:42|Tristate driver ARSIZE_S15_2 on net ARSIZE_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1518:33:1518:42|Tristate driver ARSIZE_S15_3 on net ARSIZE_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1517:33:1517:41|Tristate driver ARLEN_S15_1 on net ARLEN_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1517:33:1517:41|Tristate driver ARLEN_S15_2 on net ARLEN_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1517:33:1517:41|Tristate driver ARLEN_S15_3 on net ARLEN_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1517:33:1517:41|Tristate driver ARLEN_S15_4 on net ARLEN_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_1 on net ARADDR_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_2 on net ARADDR_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_3 on net ARADDR_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_4 on net ARADDR_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_5 on net ARADDR_S15_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_6 on net ARADDR_S15_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_7 on net ARADDR_S15_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_8 on net ARADDR_S15_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_9 on net ARADDR_S15_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_10 on net ARADDR_S15_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_11 on net ARADDR_S15_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_12 on net ARADDR_S15_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_13 on net ARADDR_S15_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_14 on net ARADDR_S15_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_15 on net ARADDR_S15_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_16 on net ARADDR_S15_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_17 on net ARADDR_S15_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_18 on net ARADDR_S15_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_19 on net ARADDR_S15_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_20 on net ARADDR_S15_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_21 on net ARADDR_S15_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_22 on net ARADDR_S15_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_23 on net ARADDR_S15_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_24 on net ARADDR_S15_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_25 on net ARADDR_S15_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_26 on net ARADDR_S15_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_27 on net ARADDR_S15_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_28 on net ARADDR_S15_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_29 on net ARADDR_S15_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_30 on net ARADDR_S15_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_31 on net ARADDR_S15_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|Tristate driver ARADDR_S15_32 on net ARADDR_S15_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1515:58:1515:65|Tristate driver ARID_S15_1 on net ARID_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1515:58:1515:65|Tristate driver ARID_S15_2 on net ARID_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1515:58:1515:65|Tristate driver ARID_S15_3 on net ARID_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1515:58:1515:65|Tristate driver ARID_S15_4 on net ARID_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1513:33:1513:42|Tristate driver BREADY_S15 on net BREADY_S15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1507:33:1507:42|Tristate driver WVALID_S15 on net WVALID_S15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1506:33:1506:41|Tristate driver WLAST_S15 on net WLAST_S15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Tristate driver WSTRB_S15_1 on net WSTRB_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Tristate driver WSTRB_S15_2 on net WSTRB_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Tristate driver WSTRB_S15_3 on net WSTRB_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Tristate driver WSTRB_S15_4 on net WSTRB_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Tristate driver WSTRB_S15_5 on net WSTRB_S15_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Tristate driver WSTRB_S15_6 on net WSTRB_S15_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Tristate driver WSTRB_S15_7 on net WSTRB_S15_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Tristate driver WSTRB_S15_8 on net WSTRB_S15_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_1 on net WDATA_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_2 on net WDATA_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_3 on net WDATA_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_4 on net WDATA_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_5 on net WDATA_S15_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_6 on net WDATA_S15_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_7 on net WDATA_S15_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_8 on net WDATA_S15_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_9 on net WDATA_S15_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_10 on net WDATA_S15_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_11 on net WDATA_S15_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_12 on net WDATA_S15_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_13 on net WDATA_S15_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_14 on net WDATA_S15_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_15 on net WDATA_S15_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_16 on net WDATA_S15_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_17 on net WDATA_S15_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_18 on net WDATA_S15_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_19 on net WDATA_S15_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_20 on net WDATA_S15_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_21 on net WDATA_S15_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_22 on net WDATA_S15_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_23 on net WDATA_S15_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_24 on net WDATA_S15_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_25 on net WDATA_S15_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_26 on net WDATA_S15_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_27 on net WDATA_S15_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_28 on net WDATA_S15_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_29 on net WDATA_S15_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_30 on net WDATA_S15_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_31 on net WDATA_S15_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_32 on net WDATA_S15_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_33 on net WDATA_S15_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_34 on net WDATA_S15_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_35 on net WDATA_S15_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_36 on net WDATA_S15_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_37 on net WDATA_S15_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_38 on net WDATA_S15_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_39 on net WDATA_S15_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_40 on net WDATA_S15_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_41 on net WDATA_S15_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_42 on net WDATA_S15_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_43 on net WDATA_S15_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_44 on net WDATA_S15_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_45 on net WDATA_S15_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_46 on net WDATA_S15_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_47 on net WDATA_S15_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_48 on net WDATA_S15_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_49 on net WDATA_S15_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_50 on net WDATA_S15_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_51 on net WDATA_S15_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_52 on net WDATA_S15_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_53 on net WDATA_S15_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_54 on net WDATA_S15_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_55 on net WDATA_S15_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_56 on net WDATA_S15_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_57 on net WDATA_S15_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_58 on net WDATA_S15_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_59 on net WDATA_S15_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_60 on net WDATA_S15_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_61 on net WDATA_S15_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_62 on net WDATA_S15_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_63 on net WDATA_S15_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|Tristate driver WDATA_S15_64 on net WDATA_S15_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1503:58:1503:64|Tristate driver WID_S15_1 on net WID_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1503:58:1503:64|Tristate driver WID_S15_2 on net WID_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1503:58:1503:64|Tristate driver WID_S15_3 on net WID_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1503:58:1503:64|Tristate driver WID_S15_4 on net WID_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1500:33:1500:43|Tristate driver AWVALID_S15 on net AWVALID_S15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1499:33:1499:42|Tristate driver AWPROT_S15_1 on net AWPROT_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1499:33:1499:42|Tristate driver AWPROT_S15_2 on net AWPROT_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1499:33:1499:42|Tristate driver AWPROT_S15_3 on net AWPROT_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1498:33:1498:43|Tristate driver AWCACHE_S15_1 on net AWCACHE_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1498:33:1498:43|Tristate driver AWCACHE_S15_2 on net AWCACHE_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1498:33:1498:43|Tristate driver AWCACHE_S15_3 on net AWCACHE_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1498:33:1498:43|Tristate driver AWCACHE_S15_4 on net AWCACHE_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1497:33:1497:42|Tristate driver AWLOCK_S15_1 on net AWLOCK_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1497:33:1497:42|Tristate driver AWLOCK_S15_2 on net AWLOCK_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1496:33:1496:43|Tristate driver AWBURST_S15_1 on net AWBURST_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1496:33:1496:43|Tristate driver AWBURST_S15_2 on net AWBURST_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1495:33:1495:42|Tristate driver AWSIZE_S15_1 on net AWSIZE_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1495:33:1495:42|Tristate driver AWSIZE_S15_2 on net AWSIZE_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1495:33:1495:42|Tristate driver AWSIZE_S15_3 on net AWSIZE_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|Tristate driver AWLEN_S15_1 on net AWLEN_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|Tristate driver AWLEN_S15_2 on net AWLEN_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|Tristate driver AWLEN_S15_3 on net AWLEN_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|Tristate driver AWLEN_S15_4 on net AWLEN_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_1 on net AWADDR_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_2 on net AWADDR_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_3 on net AWADDR_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_4 on net AWADDR_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_5 on net AWADDR_S15_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_6 on net AWADDR_S15_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_7 on net AWADDR_S15_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_8 on net AWADDR_S15_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_9 on net AWADDR_S15_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_10 on net AWADDR_S15_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_11 on net AWADDR_S15_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_12 on net AWADDR_S15_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_13 on net AWADDR_S15_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_14 on net AWADDR_S15_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_15 on net AWADDR_S15_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_16 on net AWADDR_S15_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_17 on net AWADDR_S15_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_18 on net AWADDR_S15_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_19 on net AWADDR_S15_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_20 on net AWADDR_S15_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_21 on net AWADDR_S15_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_22 on net AWADDR_S15_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_23 on net AWADDR_S15_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_24 on net AWADDR_S15_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_25 on net AWADDR_S15_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_26 on net AWADDR_S15_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_27 on net AWADDR_S15_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_28 on net AWADDR_S15_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_29 on net AWADDR_S15_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_30 on net AWADDR_S15_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_31 on net AWADDR_S15_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|Tristate driver AWADDR_S15_32 on net AWADDR_S15_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1492:58:1492:65|Tristate driver AWID_S15_1 on net AWID_S15_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1492:58:1492:65|Tristate driver AWID_S15_2 on net AWID_S15_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1492:58:1492:65|Tristate driver AWID_S15_3 on net AWID_S15_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1492:58:1492:65|Tristate driver AWID_S15_4 on net AWID_S15_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1488:33:1488:42|Tristate driver RREADY_S14 on net RREADY_S14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1480:33:1480:43|Tristate driver ARVALID_S14 on net ARVALID_S14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1479:33:1479:42|Tristate driver ARPROT_S14_1 on net ARPROT_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1479:33:1479:42|Tristate driver ARPROT_S14_2 on net ARPROT_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1479:33:1479:42|Tristate driver ARPROT_S14_3 on net ARPROT_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1478:33:1478:43|Tristate driver ARCACHE_S14_1 on net ARCACHE_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1478:33:1478:43|Tristate driver ARCACHE_S14_2 on net ARCACHE_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1478:33:1478:43|Tristate driver ARCACHE_S14_3 on net ARCACHE_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1478:33:1478:43|Tristate driver ARCACHE_S14_4 on net ARCACHE_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1477:33:1477:42|Tristate driver ARLOCK_S14_1 on net ARLOCK_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1477:33:1477:42|Tristate driver ARLOCK_S14_2 on net ARLOCK_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1476:33:1476:43|Tristate driver ARBURST_S14_1 on net ARBURST_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1476:33:1476:43|Tristate driver ARBURST_S14_2 on net ARBURST_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1475:33:1475:42|Tristate driver ARSIZE_S14_1 on net ARSIZE_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1475:33:1475:42|Tristate driver ARSIZE_S14_2 on net ARSIZE_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1475:33:1475:42|Tristate driver ARSIZE_S14_3 on net ARSIZE_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1474:33:1474:41|Tristate driver ARLEN_S14_1 on net ARLEN_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1474:33:1474:41|Tristate driver ARLEN_S14_2 on net ARLEN_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1474:33:1474:41|Tristate driver ARLEN_S14_3 on net ARLEN_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1474:33:1474:41|Tristate driver ARLEN_S14_4 on net ARLEN_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_1 on net ARADDR_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_2 on net ARADDR_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_3 on net ARADDR_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_4 on net ARADDR_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_5 on net ARADDR_S14_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_6 on net ARADDR_S14_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_7 on net ARADDR_S14_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_8 on net ARADDR_S14_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_9 on net ARADDR_S14_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_10 on net ARADDR_S14_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_11 on net ARADDR_S14_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_12 on net ARADDR_S14_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_13 on net ARADDR_S14_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_14 on net ARADDR_S14_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_15 on net ARADDR_S14_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_16 on net ARADDR_S14_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_17 on net ARADDR_S14_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_18 on net ARADDR_S14_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_19 on net ARADDR_S14_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_20 on net ARADDR_S14_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_21 on net ARADDR_S14_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_22 on net ARADDR_S14_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_23 on net ARADDR_S14_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_24 on net ARADDR_S14_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_25 on net ARADDR_S14_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_26 on net ARADDR_S14_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_27 on net ARADDR_S14_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_28 on net ARADDR_S14_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_29 on net ARADDR_S14_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_30 on net ARADDR_S14_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_31 on net ARADDR_S14_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|Tristate driver ARADDR_S14_32 on net ARADDR_S14_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1472:58:1472:65|Tristate driver ARID_S14_1 on net ARID_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1472:58:1472:65|Tristate driver ARID_S14_2 on net ARID_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1472:58:1472:65|Tristate driver ARID_S14_3 on net ARID_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1472:58:1472:65|Tristate driver ARID_S14_4 on net ARID_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1470:33:1470:42|Tristate driver BREADY_S14 on net BREADY_S14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1464:33:1464:42|Tristate driver WVALID_S14 on net WVALID_S14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1463:33:1463:41|Tristate driver WLAST_S14 on net WLAST_S14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Tristate driver WSTRB_S14_1 on net WSTRB_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Tristate driver WSTRB_S14_2 on net WSTRB_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Tristate driver WSTRB_S14_3 on net WSTRB_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Tristate driver WSTRB_S14_4 on net WSTRB_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Tristate driver WSTRB_S14_5 on net WSTRB_S14_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Tristate driver WSTRB_S14_6 on net WSTRB_S14_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Tristate driver WSTRB_S14_7 on net WSTRB_S14_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Tristate driver WSTRB_S14_8 on net WSTRB_S14_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_1 on net WDATA_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_2 on net WDATA_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_3 on net WDATA_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_4 on net WDATA_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_5 on net WDATA_S14_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_6 on net WDATA_S14_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_7 on net WDATA_S14_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_8 on net WDATA_S14_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_9 on net WDATA_S14_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_10 on net WDATA_S14_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_11 on net WDATA_S14_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_12 on net WDATA_S14_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_13 on net WDATA_S14_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_14 on net WDATA_S14_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_15 on net WDATA_S14_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_16 on net WDATA_S14_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_17 on net WDATA_S14_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_18 on net WDATA_S14_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_19 on net WDATA_S14_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_20 on net WDATA_S14_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_21 on net WDATA_S14_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_22 on net WDATA_S14_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_23 on net WDATA_S14_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_24 on net WDATA_S14_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_25 on net WDATA_S14_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_26 on net WDATA_S14_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_27 on net WDATA_S14_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_28 on net WDATA_S14_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_29 on net WDATA_S14_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_30 on net WDATA_S14_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_31 on net WDATA_S14_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_32 on net WDATA_S14_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_33 on net WDATA_S14_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_34 on net WDATA_S14_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_35 on net WDATA_S14_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_36 on net WDATA_S14_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_37 on net WDATA_S14_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_38 on net WDATA_S14_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_39 on net WDATA_S14_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_40 on net WDATA_S14_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_41 on net WDATA_S14_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_42 on net WDATA_S14_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_43 on net WDATA_S14_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_44 on net WDATA_S14_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_45 on net WDATA_S14_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_46 on net WDATA_S14_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_47 on net WDATA_S14_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_48 on net WDATA_S14_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_49 on net WDATA_S14_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_50 on net WDATA_S14_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_51 on net WDATA_S14_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_52 on net WDATA_S14_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_53 on net WDATA_S14_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_54 on net WDATA_S14_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_55 on net WDATA_S14_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_56 on net WDATA_S14_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_57 on net WDATA_S14_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_58 on net WDATA_S14_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_59 on net WDATA_S14_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_60 on net WDATA_S14_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_61 on net WDATA_S14_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_62 on net WDATA_S14_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_63 on net WDATA_S14_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|Tristate driver WDATA_S14_64 on net WDATA_S14_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1460:58:1460:64|Tristate driver WID_S14_1 on net WID_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1460:58:1460:64|Tristate driver WID_S14_2 on net WID_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1460:58:1460:64|Tristate driver WID_S14_3 on net WID_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1460:58:1460:64|Tristate driver WID_S14_4 on net WID_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1457:33:1457:43|Tristate driver AWVALID_S14 on net AWVALID_S14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1456:33:1456:42|Tristate driver AWPROT_S14_1 on net AWPROT_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1456:33:1456:42|Tristate driver AWPROT_S14_2 on net AWPROT_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1456:33:1456:42|Tristate driver AWPROT_S14_3 on net AWPROT_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1455:33:1455:43|Tristate driver AWCACHE_S14_1 on net AWCACHE_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1455:33:1455:43|Tristate driver AWCACHE_S14_2 on net AWCACHE_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1455:33:1455:43|Tristate driver AWCACHE_S14_3 on net AWCACHE_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1455:33:1455:43|Tristate driver AWCACHE_S14_4 on net AWCACHE_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1454:33:1454:42|Tristate driver AWLOCK_S14_1 on net AWLOCK_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1454:33:1454:42|Tristate driver AWLOCK_S14_2 on net AWLOCK_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1453:33:1453:43|Tristate driver AWBURST_S14_1 on net AWBURST_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1453:33:1453:43|Tristate driver AWBURST_S14_2 on net AWBURST_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1452:33:1452:42|Tristate driver AWSIZE_S14_1 on net AWSIZE_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1452:33:1452:42|Tristate driver AWSIZE_S14_2 on net AWSIZE_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1452:33:1452:42|Tristate driver AWSIZE_S14_3 on net AWSIZE_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|Tristate driver AWLEN_S14_1 on net AWLEN_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|Tristate driver AWLEN_S14_2 on net AWLEN_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|Tristate driver AWLEN_S14_3 on net AWLEN_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|Tristate driver AWLEN_S14_4 on net AWLEN_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_1 on net AWADDR_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_2 on net AWADDR_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_3 on net AWADDR_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_4 on net AWADDR_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_5 on net AWADDR_S14_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_6 on net AWADDR_S14_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_7 on net AWADDR_S14_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_8 on net AWADDR_S14_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_9 on net AWADDR_S14_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_10 on net AWADDR_S14_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_11 on net AWADDR_S14_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_12 on net AWADDR_S14_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_13 on net AWADDR_S14_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_14 on net AWADDR_S14_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_15 on net AWADDR_S14_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_16 on net AWADDR_S14_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_17 on net AWADDR_S14_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_18 on net AWADDR_S14_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_19 on net AWADDR_S14_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_20 on net AWADDR_S14_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_21 on net AWADDR_S14_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_22 on net AWADDR_S14_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_23 on net AWADDR_S14_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_24 on net AWADDR_S14_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_25 on net AWADDR_S14_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_26 on net AWADDR_S14_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_27 on net AWADDR_S14_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_28 on net AWADDR_S14_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_29 on net AWADDR_S14_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_30 on net AWADDR_S14_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_31 on net AWADDR_S14_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|Tristate driver AWADDR_S14_32 on net AWADDR_S14_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1449:58:1449:65|Tristate driver AWID_S14_1 on net AWID_S14_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1449:58:1449:65|Tristate driver AWID_S14_2 on net AWID_S14_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1449:58:1449:65|Tristate driver AWID_S14_3 on net AWID_S14_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1449:58:1449:65|Tristate driver AWID_S14_4 on net AWID_S14_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1445:33:1445:42|Tristate driver RREADY_S13 on net RREADY_S13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1437:33:1437:43|Tristate driver ARVALID_S13 on net ARVALID_S13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1436:33:1436:42|Tristate driver ARPROT_S13_1 on net ARPROT_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1436:33:1436:42|Tristate driver ARPROT_S13_2 on net ARPROT_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1436:33:1436:42|Tristate driver ARPROT_S13_3 on net ARPROT_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1435:33:1435:43|Tristate driver ARCACHE_S13_1 on net ARCACHE_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1435:33:1435:43|Tristate driver ARCACHE_S13_2 on net ARCACHE_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1435:33:1435:43|Tristate driver ARCACHE_S13_3 on net ARCACHE_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1435:33:1435:43|Tristate driver ARCACHE_S13_4 on net ARCACHE_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1434:33:1434:42|Tristate driver ARLOCK_S13_1 on net ARLOCK_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1434:33:1434:42|Tristate driver ARLOCK_S13_2 on net ARLOCK_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1433:33:1433:43|Tristate driver ARBURST_S13_1 on net ARBURST_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1433:33:1433:43|Tristate driver ARBURST_S13_2 on net ARBURST_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1432:33:1432:42|Tristate driver ARSIZE_S13_1 on net ARSIZE_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1432:33:1432:42|Tristate driver ARSIZE_S13_2 on net ARSIZE_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1432:33:1432:42|Tristate driver ARSIZE_S13_3 on net ARSIZE_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1431:33:1431:41|Tristate driver ARLEN_S13_1 on net ARLEN_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1431:33:1431:41|Tristate driver ARLEN_S13_2 on net ARLEN_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1431:33:1431:41|Tristate driver ARLEN_S13_3 on net ARLEN_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1431:33:1431:41|Tristate driver ARLEN_S13_4 on net ARLEN_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_1 on net ARADDR_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_2 on net ARADDR_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_3 on net ARADDR_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_4 on net ARADDR_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_5 on net ARADDR_S13_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_6 on net ARADDR_S13_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_7 on net ARADDR_S13_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_8 on net ARADDR_S13_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_9 on net ARADDR_S13_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_10 on net ARADDR_S13_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_11 on net ARADDR_S13_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_12 on net ARADDR_S13_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_13 on net ARADDR_S13_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_14 on net ARADDR_S13_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_15 on net ARADDR_S13_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_16 on net ARADDR_S13_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_17 on net ARADDR_S13_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_18 on net ARADDR_S13_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_19 on net ARADDR_S13_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_20 on net ARADDR_S13_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_21 on net ARADDR_S13_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_22 on net ARADDR_S13_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_23 on net ARADDR_S13_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_24 on net ARADDR_S13_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_25 on net ARADDR_S13_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_26 on net ARADDR_S13_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_27 on net ARADDR_S13_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_28 on net ARADDR_S13_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_29 on net ARADDR_S13_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_30 on net ARADDR_S13_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_31 on net ARADDR_S13_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|Tristate driver ARADDR_S13_32 on net ARADDR_S13_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1429:58:1429:65|Tristate driver ARID_S13_1 on net ARID_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1429:58:1429:65|Tristate driver ARID_S13_2 on net ARID_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1429:58:1429:65|Tristate driver ARID_S13_3 on net ARID_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1429:58:1429:65|Tristate driver ARID_S13_4 on net ARID_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1427:33:1427:42|Tristate driver BREADY_S13 on net BREADY_S13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1421:33:1421:42|Tristate driver WVALID_S13 on net WVALID_S13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1420:33:1420:41|Tristate driver WLAST_S13 on net WLAST_S13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Tristate driver WSTRB_S13_1 on net WSTRB_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Tristate driver WSTRB_S13_2 on net WSTRB_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Tristate driver WSTRB_S13_3 on net WSTRB_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Tristate driver WSTRB_S13_4 on net WSTRB_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Tristate driver WSTRB_S13_5 on net WSTRB_S13_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Tristate driver WSTRB_S13_6 on net WSTRB_S13_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Tristate driver WSTRB_S13_7 on net WSTRB_S13_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Tristate driver WSTRB_S13_8 on net WSTRB_S13_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_1 on net WDATA_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_2 on net WDATA_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_3 on net WDATA_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_4 on net WDATA_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_5 on net WDATA_S13_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_6 on net WDATA_S13_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_7 on net WDATA_S13_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_8 on net WDATA_S13_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_9 on net WDATA_S13_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_10 on net WDATA_S13_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_11 on net WDATA_S13_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_12 on net WDATA_S13_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_13 on net WDATA_S13_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_14 on net WDATA_S13_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_15 on net WDATA_S13_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_16 on net WDATA_S13_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_17 on net WDATA_S13_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_18 on net WDATA_S13_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_19 on net WDATA_S13_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_20 on net WDATA_S13_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_21 on net WDATA_S13_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_22 on net WDATA_S13_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_23 on net WDATA_S13_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_24 on net WDATA_S13_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_25 on net WDATA_S13_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_26 on net WDATA_S13_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_27 on net WDATA_S13_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_28 on net WDATA_S13_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_29 on net WDATA_S13_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_30 on net WDATA_S13_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_31 on net WDATA_S13_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_32 on net WDATA_S13_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_33 on net WDATA_S13_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_34 on net WDATA_S13_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_35 on net WDATA_S13_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_36 on net WDATA_S13_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_37 on net WDATA_S13_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_38 on net WDATA_S13_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_39 on net WDATA_S13_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_40 on net WDATA_S13_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_41 on net WDATA_S13_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_42 on net WDATA_S13_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_43 on net WDATA_S13_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_44 on net WDATA_S13_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_45 on net WDATA_S13_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_46 on net WDATA_S13_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_47 on net WDATA_S13_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_48 on net WDATA_S13_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_49 on net WDATA_S13_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_50 on net WDATA_S13_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_51 on net WDATA_S13_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_52 on net WDATA_S13_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_53 on net WDATA_S13_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_54 on net WDATA_S13_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_55 on net WDATA_S13_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_56 on net WDATA_S13_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_57 on net WDATA_S13_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_58 on net WDATA_S13_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_59 on net WDATA_S13_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_60 on net WDATA_S13_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_61 on net WDATA_S13_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_62 on net WDATA_S13_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_63 on net WDATA_S13_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|Tristate driver WDATA_S13_64 on net WDATA_S13_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1417:58:1417:64|Tristate driver WID_S13_1 on net WID_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1417:58:1417:64|Tristate driver WID_S13_2 on net WID_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1417:58:1417:64|Tristate driver WID_S13_3 on net WID_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1417:58:1417:64|Tristate driver WID_S13_4 on net WID_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1414:33:1414:43|Tristate driver AWVALID_S13 on net AWVALID_S13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1413:33:1413:42|Tristate driver AWPROT_S13_1 on net AWPROT_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1413:33:1413:42|Tristate driver AWPROT_S13_2 on net AWPROT_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1413:33:1413:42|Tristate driver AWPROT_S13_3 on net AWPROT_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1412:33:1412:43|Tristate driver AWCACHE_S13_1 on net AWCACHE_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1412:33:1412:43|Tristate driver AWCACHE_S13_2 on net AWCACHE_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1412:33:1412:43|Tristate driver AWCACHE_S13_3 on net AWCACHE_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1412:33:1412:43|Tristate driver AWCACHE_S13_4 on net AWCACHE_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1411:33:1411:42|Tristate driver AWLOCK_S13_1 on net AWLOCK_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1411:33:1411:42|Tristate driver AWLOCK_S13_2 on net AWLOCK_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1410:33:1410:43|Tristate driver AWBURST_S13_1 on net AWBURST_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1410:33:1410:43|Tristate driver AWBURST_S13_2 on net AWBURST_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1409:33:1409:42|Tristate driver AWSIZE_S13_1 on net AWSIZE_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1409:33:1409:42|Tristate driver AWSIZE_S13_2 on net AWSIZE_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1409:33:1409:42|Tristate driver AWSIZE_S13_3 on net AWSIZE_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|Tristate driver AWLEN_S13_1 on net AWLEN_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|Tristate driver AWLEN_S13_2 on net AWLEN_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|Tristate driver AWLEN_S13_3 on net AWLEN_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|Tristate driver AWLEN_S13_4 on net AWLEN_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_1 on net AWADDR_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_2 on net AWADDR_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_3 on net AWADDR_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_4 on net AWADDR_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_5 on net AWADDR_S13_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_6 on net AWADDR_S13_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_7 on net AWADDR_S13_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_8 on net AWADDR_S13_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_9 on net AWADDR_S13_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_10 on net AWADDR_S13_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_11 on net AWADDR_S13_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_12 on net AWADDR_S13_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_13 on net AWADDR_S13_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_14 on net AWADDR_S13_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_15 on net AWADDR_S13_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_16 on net AWADDR_S13_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_17 on net AWADDR_S13_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_18 on net AWADDR_S13_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_19 on net AWADDR_S13_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_20 on net AWADDR_S13_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_21 on net AWADDR_S13_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_22 on net AWADDR_S13_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_23 on net AWADDR_S13_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_24 on net AWADDR_S13_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_25 on net AWADDR_S13_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_26 on net AWADDR_S13_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_27 on net AWADDR_S13_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_28 on net AWADDR_S13_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_29 on net AWADDR_S13_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_30 on net AWADDR_S13_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_31 on net AWADDR_S13_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|Tristate driver AWADDR_S13_32 on net AWADDR_S13_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1406:58:1406:65|Tristate driver AWID_S13_1 on net AWID_S13_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1406:58:1406:65|Tristate driver AWID_S13_2 on net AWID_S13_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1406:58:1406:65|Tristate driver AWID_S13_3 on net AWID_S13_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1406:58:1406:65|Tristate driver AWID_S13_4 on net AWID_S13_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1402:33:1402:42|Tristate driver RREADY_S12 on net RREADY_S12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1394:33:1394:43|Tristate driver ARVALID_S12 on net ARVALID_S12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1393:33:1393:42|Tristate driver ARPROT_S12_1 on net ARPROT_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1393:33:1393:42|Tristate driver ARPROT_S12_2 on net ARPROT_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1393:33:1393:42|Tristate driver ARPROT_S12_3 on net ARPROT_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1392:33:1392:43|Tristate driver ARCACHE_S12_1 on net ARCACHE_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1392:33:1392:43|Tristate driver ARCACHE_S12_2 on net ARCACHE_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1392:33:1392:43|Tristate driver ARCACHE_S12_3 on net ARCACHE_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1392:33:1392:43|Tristate driver ARCACHE_S12_4 on net ARCACHE_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1391:33:1391:42|Tristate driver ARLOCK_S12_1 on net ARLOCK_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1391:33:1391:42|Tristate driver ARLOCK_S12_2 on net ARLOCK_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1390:33:1390:43|Tristate driver ARBURST_S12_1 on net ARBURST_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1390:33:1390:43|Tristate driver ARBURST_S12_2 on net ARBURST_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1389:33:1389:42|Tristate driver ARSIZE_S12_1 on net ARSIZE_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1389:33:1389:42|Tristate driver ARSIZE_S12_2 on net ARSIZE_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1389:33:1389:42|Tristate driver ARSIZE_S12_3 on net ARSIZE_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1388:33:1388:41|Tristate driver ARLEN_S12_1 on net ARLEN_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1388:33:1388:41|Tristate driver ARLEN_S12_2 on net ARLEN_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1388:33:1388:41|Tristate driver ARLEN_S12_3 on net ARLEN_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1388:33:1388:41|Tristate driver ARLEN_S12_4 on net ARLEN_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_1 on net ARADDR_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_2 on net ARADDR_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_3 on net ARADDR_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_4 on net ARADDR_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_5 on net ARADDR_S12_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_6 on net ARADDR_S12_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_7 on net ARADDR_S12_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_8 on net ARADDR_S12_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_9 on net ARADDR_S12_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_10 on net ARADDR_S12_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_11 on net ARADDR_S12_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_12 on net ARADDR_S12_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_13 on net ARADDR_S12_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_14 on net ARADDR_S12_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_15 on net ARADDR_S12_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_16 on net ARADDR_S12_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_17 on net ARADDR_S12_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_18 on net ARADDR_S12_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_19 on net ARADDR_S12_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_20 on net ARADDR_S12_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_21 on net ARADDR_S12_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_22 on net ARADDR_S12_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_23 on net ARADDR_S12_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_24 on net ARADDR_S12_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_25 on net ARADDR_S12_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_26 on net ARADDR_S12_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_27 on net ARADDR_S12_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_28 on net ARADDR_S12_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_29 on net ARADDR_S12_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_30 on net ARADDR_S12_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_31 on net ARADDR_S12_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|Tristate driver ARADDR_S12_32 on net ARADDR_S12_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1386:58:1386:65|Tristate driver ARID_S12_1 on net ARID_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1386:58:1386:65|Tristate driver ARID_S12_2 on net ARID_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1386:58:1386:65|Tristate driver ARID_S12_3 on net ARID_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1386:58:1386:65|Tristate driver ARID_S12_4 on net ARID_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1384:33:1384:42|Tristate driver BREADY_S12 on net BREADY_S12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1378:33:1378:42|Tristate driver WVALID_S12 on net WVALID_S12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1377:33:1377:41|Tristate driver WLAST_S12 on net WLAST_S12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Tristate driver WSTRB_S12_1 on net WSTRB_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Tristate driver WSTRB_S12_2 on net WSTRB_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Tristate driver WSTRB_S12_3 on net WSTRB_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Tristate driver WSTRB_S12_4 on net WSTRB_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Tristate driver WSTRB_S12_5 on net WSTRB_S12_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Tristate driver WSTRB_S12_6 on net WSTRB_S12_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Tristate driver WSTRB_S12_7 on net WSTRB_S12_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Tristate driver WSTRB_S12_8 on net WSTRB_S12_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_1 on net WDATA_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_2 on net WDATA_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_3 on net WDATA_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_4 on net WDATA_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_5 on net WDATA_S12_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_6 on net WDATA_S12_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_7 on net WDATA_S12_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_8 on net WDATA_S12_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_9 on net WDATA_S12_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_10 on net WDATA_S12_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_11 on net WDATA_S12_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_12 on net WDATA_S12_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_13 on net WDATA_S12_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_14 on net WDATA_S12_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_15 on net WDATA_S12_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_16 on net WDATA_S12_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_17 on net WDATA_S12_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_18 on net WDATA_S12_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_19 on net WDATA_S12_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_20 on net WDATA_S12_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_21 on net WDATA_S12_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_22 on net WDATA_S12_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_23 on net WDATA_S12_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_24 on net WDATA_S12_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_25 on net WDATA_S12_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_26 on net WDATA_S12_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_27 on net WDATA_S12_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_28 on net WDATA_S12_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_29 on net WDATA_S12_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_30 on net WDATA_S12_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_31 on net WDATA_S12_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_32 on net WDATA_S12_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_33 on net WDATA_S12_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_34 on net WDATA_S12_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_35 on net WDATA_S12_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_36 on net WDATA_S12_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_37 on net WDATA_S12_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_38 on net WDATA_S12_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_39 on net WDATA_S12_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_40 on net WDATA_S12_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_41 on net WDATA_S12_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_42 on net WDATA_S12_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_43 on net WDATA_S12_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_44 on net WDATA_S12_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_45 on net WDATA_S12_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_46 on net WDATA_S12_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_47 on net WDATA_S12_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_48 on net WDATA_S12_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_49 on net WDATA_S12_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_50 on net WDATA_S12_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_51 on net WDATA_S12_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_52 on net WDATA_S12_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_53 on net WDATA_S12_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_54 on net WDATA_S12_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_55 on net WDATA_S12_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_56 on net WDATA_S12_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_57 on net WDATA_S12_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_58 on net WDATA_S12_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_59 on net WDATA_S12_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_60 on net WDATA_S12_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_61 on net WDATA_S12_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_62 on net WDATA_S12_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_63 on net WDATA_S12_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|Tristate driver WDATA_S12_64 on net WDATA_S12_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1374:58:1374:64|Tristate driver WID_S12_1 on net WID_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1374:58:1374:64|Tristate driver WID_S12_2 on net WID_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1374:58:1374:64|Tristate driver WID_S12_3 on net WID_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1374:58:1374:64|Tristate driver WID_S12_4 on net WID_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1371:33:1371:43|Tristate driver AWVALID_S12 on net AWVALID_S12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1370:33:1370:42|Tristate driver AWPROT_S12_1 on net AWPROT_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1370:33:1370:42|Tristate driver AWPROT_S12_2 on net AWPROT_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1370:33:1370:42|Tristate driver AWPROT_S12_3 on net AWPROT_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1369:33:1369:43|Tristate driver AWCACHE_S12_1 on net AWCACHE_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1369:33:1369:43|Tristate driver AWCACHE_S12_2 on net AWCACHE_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1369:33:1369:43|Tristate driver AWCACHE_S12_3 on net AWCACHE_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1369:33:1369:43|Tristate driver AWCACHE_S12_4 on net AWCACHE_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1368:33:1368:42|Tristate driver AWLOCK_S12_1 on net AWLOCK_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1368:33:1368:42|Tristate driver AWLOCK_S12_2 on net AWLOCK_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1367:33:1367:43|Tristate driver AWBURST_S12_1 on net AWBURST_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1367:33:1367:43|Tristate driver AWBURST_S12_2 on net AWBURST_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1366:33:1366:42|Tristate driver AWSIZE_S12_1 on net AWSIZE_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1366:33:1366:42|Tristate driver AWSIZE_S12_2 on net AWSIZE_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1366:33:1366:42|Tristate driver AWSIZE_S12_3 on net AWSIZE_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|Tristate driver AWLEN_S12_1 on net AWLEN_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|Tristate driver AWLEN_S12_2 on net AWLEN_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|Tristate driver AWLEN_S12_3 on net AWLEN_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|Tristate driver AWLEN_S12_4 on net AWLEN_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_1 on net AWADDR_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_2 on net AWADDR_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_3 on net AWADDR_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_4 on net AWADDR_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_5 on net AWADDR_S12_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_6 on net AWADDR_S12_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_7 on net AWADDR_S12_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_8 on net AWADDR_S12_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_9 on net AWADDR_S12_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_10 on net AWADDR_S12_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_11 on net AWADDR_S12_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_12 on net AWADDR_S12_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_13 on net AWADDR_S12_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_14 on net AWADDR_S12_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_15 on net AWADDR_S12_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_16 on net AWADDR_S12_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_17 on net AWADDR_S12_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_18 on net AWADDR_S12_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_19 on net AWADDR_S12_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_20 on net AWADDR_S12_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_21 on net AWADDR_S12_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_22 on net AWADDR_S12_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_23 on net AWADDR_S12_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_24 on net AWADDR_S12_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_25 on net AWADDR_S12_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_26 on net AWADDR_S12_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_27 on net AWADDR_S12_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_28 on net AWADDR_S12_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_29 on net AWADDR_S12_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_30 on net AWADDR_S12_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_31 on net AWADDR_S12_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|Tristate driver AWADDR_S12_32 on net AWADDR_S12_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1363:58:1363:65|Tristate driver AWID_S12_1 on net AWID_S12_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1363:58:1363:65|Tristate driver AWID_S12_2 on net AWID_S12_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1363:58:1363:65|Tristate driver AWID_S12_3 on net AWID_S12_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1363:58:1363:65|Tristate driver AWID_S12_4 on net AWID_S12_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1359:33:1359:42|Tristate driver RREADY_S11 on net RREADY_S11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1351:33:1351:43|Tristate driver ARVALID_S11 on net ARVALID_S11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1350:33:1350:42|Tristate driver ARPROT_S11_1 on net ARPROT_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1350:33:1350:42|Tristate driver ARPROT_S11_2 on net ARPROT_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1350:33:1350:42|Tristate driver ARPROT_S11_3 on net ARPROT_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1349:33:1349:43|Tristate driver ARCACHE_S11_1 on net ARCACHE_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1349:33:1349:43|Tristate driver ARCACHE_S11_2 on net ARCACHE_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1349:33:1349:43|Tristate driver ARCACHE_S11_3 on net ARCACHE_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1349:33:1349:43|Tristate driver ARCACHE_S11_4 on net ARCACHE_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1348:33:1348:42|Tristate driver ARLOCK_S11_1 on net ARLOCK_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1348:33:1348:42|Tristate driver ARLOCK_S11_2 on net ARLOCK_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1347:33:1347:43|Tristate driver ARBURST_S11_1 on net ARBURST_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1347:33:1347:43|Tristate driver ARBURST_S11_2 on net ARBURST_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1346:33:1346:42|Tristate driver ARSIZE_S11_1 on net ARSIZE_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1346:33:1346:42|Tristate driver ARSIZE_S11_2 on net ARSIZE_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1346:33:1346:42|Tristate driver ARSIZE_S11_3 on net ARSIZE_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1345:33:1345:41|Tristate driver ARLEN_S11_1 on net ARLEN_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1345:33:1345:41|Tristate driver ARLEN_S11_2 on net ARLEN_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1345:33:1345:41|Tristate driver ARLEN_S11_3 on net ARLEN_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1345:33:1345:41|Tristate driver ARLEN_S11_4 on net ARLEN_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_1 on net ARADDR_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_2 on net ARADDR_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_3 on net ARADDR_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_4 on net ARADDR_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_5 on net ARADDR_S11_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_6 on net ARADDR_S11_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_7 on net ARADDR_S11_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_8 on net ARADDR_S11_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_9 on net ARADDR_S11_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_10 on net ARADDR_S11_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_11 on net ARADDR_S11_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_12 on net ARADDR_S11_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_13 on net ARADDR_S11_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_14 on net ARADDR_S11_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_15 on net ARADDR_S11_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_16 on net ARADDR_S11_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_17 on net ARADDR_S11_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_18 on net ARADDR_S11_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_19 on net ARADDR_S11_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_20 on net ARADDR_S11_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_21 on net ARADDR_S11_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_22 on net ARADDR_S11_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_23 on net ARADDR_S11_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_24 on net ARADDR_S11_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_25 on net ARADDR_S11_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_26 on net ARADDR_S11_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_27 on net ARADDR_S11_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_28 on net ARADDR_S11_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_29 on net ARADDR_S11_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_30 on net ARADDR_S11_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_31 on net ARADDR_S11_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|Tristate driver ARADDR_S11_32 on net ARADDR_S11_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1343:58:1343:65|Tristate driver ARID_S11_1 on net ARID_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1343:58:1343:65|Tristate driver ARID_S11_2 on net ARID_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1343:58:1343:65|Tristate driver ARID_S11_3 on net ARID_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1343:58:1343:65|Tristate driver ARID_S11_4 on net ARID_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1341:33:1341:42|Tristate driver BREADY_S11 on net BREADY_S11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1335:33:1335:42|Tristate driver WVALID_S11 on net WVALID_S11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1334:33:1334:41|Tristate driver WLAST_S11 on net WLAST_S11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Tristate driver WSTRB_S11_1 on net WSTRB_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Tristate driver WSTRB_S11_2 on net WSTRB_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Tristate driver WSTRB_S11_3 on net WSTRB_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Tristate driver WSTRB_S11_4 on net WSTRB_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Tristate driver WSTRB_S11_5 on net WSTRB_S11_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Tristate driver WSTRB_S11_6 on net WSTRB_S11_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Tristate driver WSTRB_S11_7 on net WSTRB_S11_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Tristate driver WSTRB_S11_8 on net WSTRB_S11_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_1 on net WDATA_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_2 on net WDATA_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_3 on net WDATA_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_4 on net WDATA_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_5 on net WDATA_S11_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_6 on net WDATA_S11_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_7 on net WDATA_S11_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_8 on net WDATA_S11_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_9 on net WDATA_S11_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_10 on net WDATA_S11_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_11 on net WDATA_S11_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_12 on net WDATA_S11_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_13 on net WDATA_S11_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_14 on net WDATA_S11_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_15 on net WDATA_S11_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_16 on net WDATA_S11_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_17 on net WDATA_S11_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_18 on net WDATA_S11_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_19 on net WDATA_S11_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_20 on net WDATA_S11_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_21 on net WDATA_S11_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_22 on net WDATA_S11_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_23 on net WDATA_S11_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_24 on net WDATA_S11_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_25 on net WDATA_S11_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_26 on net WDATA_S11_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_27 on net WDATA_S11_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_28 on net WDATA_S11_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_29 on net WDATA_S11_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_30 on net WDATA_S11_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_31 on net WDATA_S11_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_32 on net WDATA_S11_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_33 on net WDATA_S11_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_34 on net WDATA_S11_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_35 on net WDATA_S11_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_36 on net WDATA_S11_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_37 on net WDATA_S11_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_38 on net WDATA_S11_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_39 on net WDATA_S11_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_40 on net WDATA_S11_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_41 on net WDATA_S11_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_42 on net WDATA_S11_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_43 on net WDATA_S11_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_44 on net WDATA_S11_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_45 on net WDATA_S11_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_46 on net WDATA_S11_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_47 on net WDATA_S11_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_48 on net WDATA_S11_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_49 on net WDATA_S11_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_50 on net WDATA_S11_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_51 on net WDATA_S11_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_52 on net WDATA_S11_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_53 on net WDATA_S11_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_54 on net WDATA_S11_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_55 on net WDATA_S11_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_56 on net WDATA_S11_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_57 on net WDATA_S11_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_58 on net WDATA_S11_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_59 on net WDATA_S11_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_60 on net WDATA_S11_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_61 on net WDATA_S11_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_62 on net WDATA_S11_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_63 on net WDATA_S11_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|Tristate driver WDATA_S11_64 on net WDATA_S11_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1331:58:1331:64|Tristate driver WID_S11_1 on net WID_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1331:58:1331:64|Tristate driver WID_S11_2 on net WID_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1331:58:1331:64|Tristate driver WID_S11_3 on net WID_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1331:58:1331:64|Tristate driver WID_S11_4 on net WID_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1328:33:1328:43|Tristate driver AWVALID_S11 on net AWVALID_S11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1327:33:1327:42|Tristate driver AWPROT_S11_1 on net AWPROT_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1327:33:1327:42|Tristate driver AWPROT_S11_2 on net AWPROT_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1327:33:1327:42|Tristate driver AWPROT_S11_3 on net AWPROT_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1326:33:1326:43|Tristate driver AWCACHE_S11_1 on net AWCACHE_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1326:33:1326:43|Tristate driver AWCACHE_S11_2 on net AWCACHE_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1326:33:1326:43|Tristate driver AWCACHE_S11_3 on net AWCACHE_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1326:33:1326:43|Tristate driver AWCACHE_S11_4 on net AWCACHE_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1325:33:1325:42|Tristate driver AWLOCK_S11_1 on net AWLOCK_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1325:33:1325:42|Tristate driver AWLOCK_S11_2 on net AWLOCK_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1324:33:1324:43|Tristate driver AWBURST_S11_1 on net AWBURST_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1324:33:1324:43|Tristate driver AWBURST_S11_2 on net AWBURST_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1323:33:1323:42|Tristate driver AWSIZE_S11_1 on net AWSIZE_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1323:33:1323:42|Tristate driver AWSIZE_S11_2 on net AWSIZE_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1323:33:1323:42|Tristate driver AWSIZE_S11_3 on net AWSIZE_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|Tristate driver AWLEN_S11_1 on net AWLEN_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|Tristate driver AWLEN_S11_2 on net AWLEN_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|Tristate driver AWLEN_S11_3 on net AWLEN_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|Tristate driver AWLEN_S11_4 on net AWLEN_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_1 on net AWADDR_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_2 on net AWADDR_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_3 on net AWADDR_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_4 on net AWADDR_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_5 on net AWADDR_S11_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_6 on net AWADDR_S11_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_7 on net AWADDR_S11_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_8 on net AWADDR_S11_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_9 on net AWADDR_S11_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_10 on net AWADDR_S11_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_11 on net AWADDR_S11_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_12 on net AWADDR_S11_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_13 on net AWADDR_S11_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_14 on net AWADDR_S11_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_15 on net AWADDR_S11_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_16 on net AWADDR_S11_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_17 on net AWADDR_S11_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_18 on net AWADDR_S11_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_19 on net AWADDR_S11_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_20 on net AWADDR_S11_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_21 on net AWADDR_S11_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_22 on net AWADDR_S11_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_23 on net AWADDR_S11_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_24 on net AWADDR_S11_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_25 on net AWADDR_S11_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_26 on net AWADDR_S11_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_27 on net AWADDR_S11_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_28 on net AWADDR_S11_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_29 on net AWADDR_S11_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_30 on net AWADDR_S11_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_31 on net AWADDR_S11_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|Tristate driver AWADDR_S11_32 on net AWADDR_S11_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1320:58:1320:65|Tristate driver AWID_S11_1 on net AWID_S11_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1320:58:1320:65|Tristate driver AWID_S11_2 on net AWID_S11_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1320:58:1320:65|Tristate driver AWID_S11_3 on net AWID_S11_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1320:58:1320:65|Tristate driver AWID_S11_4 on net AWID_S11_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1316:33:1316:42|Tristate driver RREADY_S10 on net RREADY_S10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1308:33:1308:43|Tristate driver ARVALID_S10 on net ARVALID_S10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1307:33:1307:42|Tristate driver ARPROT_S10_1 on net ARPROT_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1307:33:1307:42|Tristate driver ARPROT_S10_2 on net ARPROT_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1307:33:1307:42|Tristate driver ARPROT_S10_3 on net ARPROT_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1306:33:1306:43|Tristate driver ARCACHE_S10_1 on net ARCACHE_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1306:33:1306:43|Tristate driver ARCACHE_S10_2 on net ARCACHE_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1306:33:1306:43|Tristate driver ARCACHE_S10_3 on net ARCACHE_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1306:33:1306:43|Tristate driver ARCACHE_S10_4 on net ARCACHE_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1305:33:1305:42|Tristate driver ARLOCK_S10_1 on net ARLOCK_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1305:33:1305:42|Tristate driver ARLOCK_S10_2 on net ARLOCK_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1304:33:1304:43|Tristate driver ARBURST_S10_1 on net ARBURST_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1304:33:1304:43|Tristate driver ARBURST_S10_2 on net ARBURST_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1303:33:1303:42|Tristate driver ARSIZE_S10_1 on net ARSIZE_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1303:33:1303:42|Tristate driver ARSIZE_S10_2 on net ARSIZE_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1303:33:1303:42|Tristate driver ARSIZE_S10_3 on net ARSIZE_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1302:33:1302:41|Tristate driver ARLEN_S10_1 on net ARLEN_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1302:33:1302:41|Tristate driver ARLEN_S10_2 on net ARLEN_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1302:33:1302:41|Tristate driver ARLEN_S10_3 on net ARLEN_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1302:33:1302:41|Tristate driver ARLEN_S10_4 on net ARLEN_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_1 on net ARADDR_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_2 on net ARADDR_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_3 on net ARADDR_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_4 on net ARADDR_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_5 on net ARADDR_S10_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_6 on net ARADDR_S10_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_7 on net ARADDR_S10_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_8 on net ARADDR_S10_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_9 on net ARADDR_S10_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_10 on net ARADDR_S10_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_11 on net ARADDR_S10_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_12 on net ARADDR_S10_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_13 on net ARADDR_S10_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_14 on net ARADDR_S10_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_15 on net ARADDR_S10_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_16 on net ARADDR_S10_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_17 on net ARADDR_S10_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_18 on net ARADDR_S10_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_19 on net ARADDR_S10_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_20 on net ARADDR_S10_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_21 on net ARADDR_S10_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_22 on net ARADDR_S10_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_23 on net ARADDR_S10_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_24 on net ARADDR_S10_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_25 on net ARADDR_S10_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_26 on net ARADDR_S10_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_27 on net ARADDR_S10_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_28 on net ARADDR_S10_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_29 on net ARADDR_S10_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_30 on net ARADDR_S10_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_31 on net ARADDR_S10_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|Tristate driver ARADDR_S10_32 on net ARADDR_S10_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1300:58:1300:65|Tristate driver ARID_S10_1 on net ARID_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1300:58:1300:65|Tristate driver ARID_S10_2 on net ARID_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1300:58:1300:65|Tristate driver ARID_S10_3 on net ARID_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1300:58:1300:65|Tristate driver ARID_S10_4 on net ARID_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1298:33:1298:42|Tristate driver BREADY_S10 on net BREADY_S10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1292:33:1292:42|Tristate driver WVALID_S10 on net WVALID_S10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1291:33:1291:41|Tristate driver WLAST_S10 on net WLAST_S10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|Tristate driver WSTRB_S10_1 on net WSTRB_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|Tristate driver WSTRB_S10_2 on net WSTRB_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|Tristate driver WSTRB_S10_3 on net WSTRB_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|Tristate driver WSTRB_S10_4 on net WSTRB_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|Tristate driver WSTRB_S10_5 on net WSTRB_S10_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|Tristate driver WSTRB_S10_6 on net WSTRB_S10_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|Tristate driver WSTRB_S10_7 on net WSTRB_S10_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|Tristate driver WSTRB_S10_8 on net WSTRB_S10_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_1 on net WDATA_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_2 on net WDATA_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_3 on net WDATA_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_4 on net WDATA_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_5 on net WDATA_S10_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_6 on net WDATA_S10_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_7 on net WDATA_S10_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_8 on net WDATA_S10_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_9 on net WDATA_S10_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_10 on net WDATA_S10_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_11 on net WDATA_S10_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_12 on net WDATA_S10_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_13 on net WDATA_S10_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_14 on net WDATA_S10_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_15 on net WDATA_S10_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_16 on net WDATA_S10_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_17 on net WDATA_S10_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_18 on net WDATA_S10_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_19 on net WDATA_S10_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_20 on net WDATA_S10_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_21 on net WDATA_S10_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_22 on net WDATA_S10_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_23 on net WDATA_S10_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_24 on net WDATA_S10_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_25 on net WDATA_S10_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_26 on net WDATA_S10_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_27 on net WDATA_S10_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_28 on net WDATA_S10_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_29 on net WDATA_S10_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_30 on net WDATA_S10_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_31 on net WDATA_S10_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_32 on net WDATA_S10_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_33 on net WDATA_S10_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_34 on net WDATA_S10_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_35 on net WDATA_S10_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_36 on net WDATA_S10_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_37 on net WDATA_S10_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_38 on net WDATA_S10_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_39 on net WDATA_S10_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_40 on net WDATA_S10_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_41 on net WDATA_S10_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_42 on net WDATA_S10_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_43 on net WDATA_S10_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_44 on net WDATA_S10_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_45 on net WDATA_S10_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_46 on net WDATA_S10_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_47 on net WDATA_S10_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_48 on net WDATA_S10_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_49 on net WDATA_S10_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_50 on net WDATA_S10_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_51 on net WDATA_S10_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_52 on net WDATA_S10_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_53 on net WDATA_S10_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_54 on net WDATA_S10_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_55 on net WDATA_S10_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_56 on net WDATA_S10_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_57 on net WDATA_S10_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_58 on net WDATA_S10_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_59 on net WDATA_S10_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_60 on net WDATA_S10_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_61 on net WDATA_S10_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_62 on net WDATA_S10_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_63 on net WDATA_S10_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|Tristate driver WDATA_S10_64 on net WDATA_S10_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1288:58:1288:64|Tristate driver WID_S10_1 on net WID_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1288:58:1288:64|Tristate driver WID_S10_2 on net WID_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1288:58:1288:64|Tristate driver WID_S10_3 on net WID_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1288:58:1288:64|Tristate driver WID_S10_4 on net WID_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1285:33:1285:43|Tristate driver AWVALID_S10 on net AWVALID_S10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1284:33:1284:42|Tristate driver AWPROT_S10_1 on net AWPROT_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1284:33:1284:42|Tristate driver AWPROT_S10_2 on net AWPROT_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1284:33:1284:42|Tristate driver AWPROT_S10_3 on net AWPROT_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1283:33:1283:43|Tristate driver AWCACHE_S10_1 on net AWCACHE_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1283:33:1283:43|Tristate driver AWCACHE_S10_2 on net AWCACHE_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1283:33:1283:43|Tristate driver AWCACHE_S10_3 on net AWCACHE_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1283:33:1283:43|Tristate driver AWCACHE_S10_4 on net AWCACHE_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1282:33:1282:42|Tristate driver AWLOCK_S10_1 on net AWLOCK_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1282:33:1282:42|Tristate driver AWLOCK_S10_2 on net AWLOCK_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1281:33:1281:43|Tristate driver AWBURST_S10_1 on net AWBURST_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1281:33:1281:43|Tristate driver AWBURST_S10_2 on net AWBURST_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1280:33:1280:42|Tristate driver AWSIZE_S10_1 on net AWSIZE_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1280:33:1280:42|Tristate driver AWSIZE_S10_2 on net AWSIZE_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1280:33:1280:42|Tristate driver AWSIZE_S10_3 on net AWSIZE_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1279:33:1279:41|Tristate driver AWLEN_S10_1 on net AWLEN_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1279:33:1279:41|Tristate driver AWLEN_S10_2 on net AWLEN_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1279:33:1279:41|Tristate driver AWLEN_S10_3 on net AWLEN_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1279:33:1279:41|Tristate driver AWLEN_S10_4 on net AWLEN_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_1 on net AWADDR_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_2 on net AWADDR_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_3 on net AWADDR_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_4 on net AWADDR_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_5 on net AWADDR_S10_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_6 on net AWADDR_S10_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_7 on net AWADDR_S10_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_8 on net AWADDR_S10_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_9 on net AWADDR_S10_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_10 on net AWADDR_S10_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_11 on net AWADDR_S10_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_12 on net AWADDR_S10_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_13 on net AWADDR_S10_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_14 on net AWADDR_S10_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_15 on net AWADDR_S10_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_16 on net AWADDR_S10_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_17 on net AWADDR_S10_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_18 on net AWADDR_S10_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_19 on net AWADDR_S10_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_20 on net AWADDR_S10_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_21 on net AWADDR_S10_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_22 on net AWADDR_S10_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_23 on net AWADDR_S10_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_24 on net AWADDR_S10_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_25 on net AWADDR_S10_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_26 on net AWADDR_S10_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_27 on net AWADDR_S10_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_28 on net AWADDR_S10_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_29 on net AWADDR_S10_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_30 on net AWADDR_S10_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_31 on net AWADDR_S10_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|Tristate driver AWADDR_S10_32 on net AWADDR_S10_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1277:58:1277:65|Tristate driver AWID_S10_1 on net AWID_S10_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1277:58:1277:65|Tristate driver AWID_S10_2 on net AWID_S10_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1277:58:1277:65|Tristate driver AWID_S10_3 on net AWID_S10_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1277:58:1277:65|Tristate driver AWID_S10_4 on net AWID_S10_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1273:33:1273:41|Tristate driver RREADY_S9 on net RREADY_S9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1265:33:1265:42|Tristate driver ARVALID_S9 on net ARVALID_S9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1264:33:1264:41|Tristate driver ARPROT_S9_1 on net ARPROT_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1264:33:1264:41|Tristate driver ARPROT_S9_2 on net ARPROT_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1264:33:1264:41|Tristate driver ARPROT_S9_3 on net ARPROT_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1263:33:1263:42|Tristate driver ARCACHE_S9_1 on net ARCACHE_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1263:33:1263:42|Tristate driver ARCACHE_S9_2 on net ARCACHE_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1263:33:1263:42|Tristate driver ARCACHE_S9_3 on net ARCACHE_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1263:33:1263:42|Tristate driver ARCACHE_S9_4 on net ARCACHE_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1262:33:1262:41|Tristate driver ARLOCK_S9_1 on net ARLOCK_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1262:33:1262:41|Tristate driver ARLOCK_S9_2 on net ARLOCK_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1261:33:1261:42|Tristate driver ARBURST_S9_1 on net ARBURST_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1261:33:1261:42|Tristate driver ARBURST_S9_2 on net ARBURST_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1260:33:1260:41|Tristate driver ARSIZE_S9_1 on net ARSIZE_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1260:33:1260:41|Tristate driver ARSIZE_S9_2 on net ARSIZE_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1260:33:1260:41|Tristate driver ARSIZE_S9_3 on net ARSIZE_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1259:33:1259:40|Tristate driver ARLEN_S9_1 on net ARLEN_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1259:33:1259:40|Tristate driver ARLEN_S9_2 on net ARLEN_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1259:33:1259:40|Tristate driver ARLEN_S9_3 on net ARLEN_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1259:33:1259:40|Tristate driver ARLEN_S9_4 on net ARLEN_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_1 on net ARADDR_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_2 on net ARADDR_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_3 on net ARADDR_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_4 on net ARADDR_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_5 on net ARADDR_S9_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_6 on net ARADDR_S9_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_7 on net ARADDR_S9_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_8 on net ARADDR_S9_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_9 on net ARADDR_S9_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_10 on net ARADDR_S9_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_11 on net ARADDR_S9_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_12 on net ARADDR_S9_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_13 on net ARADDR_S9_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_14 on net ARADDR_S9_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_15 on net ARADDR_S9_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_16 on net ARADDR_S9_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_17 on net ARADDR_S9_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_18 on net ARADDR_S9_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_19 on net ARADDR_S9_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_20 on net ARADDR_S9_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_21 on net ARADDR_S9_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_22 on net ARADDR_S9_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_23 on net ARADDR_S9_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_24 on net ARADDR_S9_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_25 on net ARADDR_S9_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_26 on net ARADDR_S9_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_27 on net ARADDR_S9_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_28 on net ARADDR_S9_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_29 on net ARADDR_S9_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_30 on net ARADDR_S9_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_31 on net ARADDR_S9_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|Tristate driver ARADDR_S9_32 on net ARADDR_S9_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1257:58:1257:64|Tristate driver ARID_S9_1 on net ARID_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1257:58:1257:64|Tristate driver ARID_S9_2 on net ARID_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1257:58:1257:64|Tristate driver ARID_S9_3 on net ARID_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1257:58:1257:64|Tristate driver ARID_S9_4 on net ARID_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1255:33:1255:41|Tristate driver BREADY_S9 on net BREADY_S9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1249:33:1249:41|Tristate driver WVALID_S9 on net WVALID_S9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1248:33:1248:40|Tristate driver WLAST_S9 on net WLAST_S9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|Tristate driver WSTRB_S9_1 on net WSTRB_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|Tristate driver WSTRB_S9_2 on net WSTRB_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|Tristate driver WSTRB_S9_3 on net WSTRB_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|Tristate driver WSTRB_S9_4 on net WSTRB_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|Tristate driver WSTRB_S9_5 on net WSTRB_S9_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|Tristate driver WSTRB_S9_6 on net WSTRB_S9_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|Tristate driver WSTRB_S9_7 on net WSTRB_S9_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|Tristate driver WSTRB_S9_8 on net WSTRB_S9_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_1 on net WDATA_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_2 on net WDATA_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_3 on net WDATA_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_4 on net WDATA_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_5 on net WDATA_S9_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_6 on net WDATA_S9_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_7 on net WDATA_S9_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_8 on net WDATA_S9_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_9 on net WDATA_S9_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_10 on net WDATA_S9_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_11 on net WDATA_S9_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_12 on net WDATA_S9_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_13 on net WDATA_S9_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_14 on net WDATA_S9_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_15 on net WDATA_S9_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_16 on net WDATA_S9_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_17 on net WDATA_S9_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_18 on net WDATA_S9_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_19 on net WDATA_S9_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_20 on net WDATA_S9_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_21 on net WDATA_S9_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_22 on net WDATA_S9_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_23 on net WDATA_S9_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_24 on net WDATA_S9_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_25 on net WDATA_S9_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_26 on net WDATA_S9_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_27 on net WDATA_S9_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_28 on net WDATA_S9_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_29 on net WDATA_S9_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_30 on net WDATA_S9_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_31 on net WDATA_S9_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_32 on net WDATA_S9_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_33 on net WDATA_S9_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_34 on net WDATA_S9_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_35 on net WDATA_S9_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_36 on net WDATA_S9_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_37 on net WDATA_S9_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_38 on net WDATA_S9_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_39 on net WDATA_S9_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_40 on net WDATA_S9_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_41 on net WDATA_S9_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_42 on net WDATA_S9_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_43 on net WDATA_S9_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_44 on net WDATA_S9_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_45 on net WDATA_S9_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_46 on net WDATA_S9_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_47 on net WDATA_S9_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_48 on net WDATA_S9_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_49 on net WDATA_S9_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_50 on net WDATA_S9_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_51 on net WDATA_S9_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_52 on net WDATA_S9_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_53 on net WDATA_S9_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_54 on net WDATA_S9_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_55 on net WDATA_S9_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_56 on net WDATA_S9_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_57 on net WDATA_S9_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_58 on net WDATA_S9_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_59 on net WDATA_S9_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_60 on net WDATA_S9_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_61 on net WDATA_S9_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_62 on net WDATA_S9_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_63 on net WDATA_S9_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Tristate driver WDATA_S9_64 on net WDATA_S9_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1245:58:1245:63|Tristate driver WID_S9_1 on net WID_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1245:58:1245:63|Tristate driver WID_S9_2 on net WID_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1245:58:1245:63|Tristate driver WID_S9_3 on net WID_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1245:58:1245:63|Tristate driver WID_S9_4 on net WID_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1242:33:1242:42|Tristate driver AWVALID_S9 on net AWVALID_S9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1241:33:1241:41|Tristate driver AWPROT_S9_1 on net AWPROT_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1241:33:1241:41|Tristate driver AWPROT_S9_2 on net AWPROT_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1241:33:1241:41|Tristate driver AWPROT_S9_3 on net AWPROT_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1240:33:1240:42|Tristate driver AWCACHE_S9_1 on net AWCACHE_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1240:33:1240:42|Tristate driver AWCACHE_S9_2 on net AWCACHE_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1240:33:1240:42|Tristate driver AWCACHE_S9_3 on net AWCACHE_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1240:33:1240:42|Tristate driver AWCACHE_S9_4 on net AWCACHE_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1239:33:1239:41|Tristate driver AWLOCK_S9_1 on net AWLOCK_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1239:33:1239:41|Tristate driver AWLOCK_S9_2 on net AWLOCK_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1238:33:1238:42|Tristate driver AWBURST_S9_1 on net AWBURST_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1238:33:1238:42|Tristate driver AWBURST_S9_2 on net AWBURST_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1237:33:1237:41|Tristate driver AWSIZE_S9_1 on net AWSIZE_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1237:33:1237:41|Tristate driver AWSIZE_S9_2 on net AWSIZE_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1237:33:1237:41|Tristate driver AWSIZE_S9_3 on net AWSIZE_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1236:33:1236:40|Tristate driver AWLEN_S9_1 on net AWLEN_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1236:33:1236:40|Tristate driver AWLEN_S9_2 on net AWLEN_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1236:33:1236:40|Tristate driver AWLEN_S9_3 on net AWLEN_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1236:33:1236:40|Tristate driver AWLEN_S9_4 on net AWLEN_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_1 on net AWADDR_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_2 on net AWADDR_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_3 on net AWADDR_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_4 on net AWADDR_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_5 on net AWADDR_S9_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_6 on net AWADDR_S9_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_7 on net AWADDR_S9_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_8 on net AWADDR_S9_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_9 on net AWADDR_S9_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_10 on net AWADDR_S9_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_11 on net AWADDR_S9_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_12 on net AWADDR_S9_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_13 on net AWADDR_S9_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_14 on net AWADDR_S9_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_15 on net AWADDR_S9_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_16 on net AWADDR_S9_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_17 on net AWADDR_S9_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_18 on net AWADDR_S9_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_19 on net AWADDR_S9_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_20 on net AWADDR_S9_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_21 on net AWADDR_S9_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_22 on net AWADDR_S9_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_23 on net AWADDR_S9_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_24 on net AWADDR_S9_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_25 on net AWADDR_S9_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_26 on net AWADDR_S9_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_27 on net AWADDR_S9_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_28 on net AWADDR_S9_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_29 on net AWADDR_S9_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_30 on net AWADDR_S9_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_31 on net AWADDR_S9_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|Tristate driver AWADDR_S9_32 on net AWADDR_S9_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1234:58:1234:64|Tristate driver AWID_S9_1 on net AWID_S9_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1234:58:1234:64|Tristate driver AWID_S9_2 on net AWID_S9_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1234:58:1234:64|Tristate driver AWID_S9_3 on net AWID_S9_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1234:58:1234:64|Tristate driver AWID_S9_4 on net AWID_S9_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1230:33:1230:41|Tristate driver RREADY_S8 on net RREADY_S8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1222:33:1222:42|Tristate driver ARVALID_S8 on net ARVALID_S8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1221:33:1221:41|Tristate driver ARPROT_S8_1 on net ARPROT_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1221:33:1221:41|Tristate driver ARPROT_S8_2 on net ARPROT_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1221:33:1221:41|Tristate driver ARPROT_S8_3 on net ARPROT_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1220:33:1220:42|Tristate driver ARCACHE_S8_1 on net ARCACHE_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1220:33:1220:42|Tristate driver ARCACHE_S8_2 on net ARCACHE_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1220:33:1220:42|Tristate driver ARCACHE_S8_3 on net ARCACHE_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1220:33:1220:42|Tristate driver ARCACHE_S8_4 on net ARCACHE_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1219:33:1219:41|Tristate driver ARLOCK_S8_1 on net ARLOCK_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1219:33:1219:41|Tristate driver ARLOCK_S8_2 on net ARLOCK_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1218:33:1218:42|Tristate driver ARBURST_S8_1 on net ARBURST_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1218:33:1218:42|Tristate driver ARBURST_S8_2 on net ARBURST_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1217:33:1217:41|Tristate driver ARSIZE_S8_1 on net ARSIZE_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1217:33:1217:41|Tristate driver ARSIZE_S8_2 on net ARSIZE_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1217:33:1217:41|Tristate driver ARSIZE_S8_3 on net ARSIZE_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1216:33:1216:40|Tristate driver ARLEN_S8_1 on net ARLEN_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1216:33:1216:40|Tristate driver ARLEN_S8_2 on net ARLEN_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1216:33:1216:40|Tristate driver ARLEN_S8_3 on net ARLEN_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1216:33:1216:40|Tristate driver ARLEN_S8_4 on net ARLEN_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_1 on net ARADDR_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_2 on net ARADDR_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_3 on net ARADDR_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_4 on net ARADDR_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_5 on net ARADDR_S8_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_6 on net ARADDR_S8_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_7 on net ARADDR_S8_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_8 on net ARADDR_S8_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_9 on net ARADDR_S8_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_10 on net ARADDR_S8_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_11 on net ARADDR_S8_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_12 on net ARADDR_S8_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_13 on net ARADDR_S8_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_14 on net ARADDR_S8_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_15 on net ARADDR_S8_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_16 on net ARADDR_S8_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_17 on net ARADDR_S8_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_18 on net ARADDR_S8_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_19 on net ARADDR_S8_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_20 on net ARADDR_S8_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_21 on net ARADDR_S8_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_22 on net ARADDR_S8_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_23 on net ARADDR_S8_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_24 on net ARADDR_S8_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_25 on net ARADDR_S8_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_26 on net ARADDR_S8_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_27 on net ARADDR_S8_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_28 on net ARADDR_S8_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_29 on net ARADDR_S8_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_30 on net ARADDR_S8_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_31 on net ARADDR_S8_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|Tristate driver ARADDR_S8_32 on net ARADDR_S8_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1214:58:1214:64|Tristate driver ARID_S8_1 on net ARID_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1214:58:1214:64|Tristate driver ARID_S8_2 on net ARID_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1214:58:1214:64|Tristate driver ARID_S8_3 on net ARID_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1214:58:1214:64|Tristate driver ARID_S8_4 on net ARID_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1212:33:1212:41|Tristate driver BREADY_S8 on net BREADY_S8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1206:33:1206:41|Tristate driver WVALID_S8 on net WVALID_S8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1205:33:1205:40|Tristate driver WLAST_S8 on net WLAST_S8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|Tristate driver WSTRB_S8_1 on net WSTRB_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|Tristate driver WSTRB_S8_2 on net WSTRB_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|Tristate driver WSTRB_S8_3 on net WSTRB_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|Tristate driver WSTRB_S8_4 on net WSTRB_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|Tristate driver WSTRB_S8_5 on net WSTRB_S8_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|Tristate driver WSTRB_S8_6 on net WSTRB_S8_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|Tristate driver WSTRB_S8_7 on net WSTRB_S8_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|Tristate driver WSTRB_S8_8 on net WSTRB_S8_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_1 on net WDATA_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_2 on net WDATA_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_3 on net WDATA_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_4 on net WDATA_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_5 on net WDATA_S8_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_6 on net WDATA_S8_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_7 on net WDATA_S8_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_8 on net WDATA_S8_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_9 on net WDATA_S8_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_10 on net WDATA_S8_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_11 on net WDATA_S8_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_12 on net WDATA_S8_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_13 on net WDATA_S8_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_14 on net WDATA_S8_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_15 on net WDATA_S8_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_16 on net WDATA_S8_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_17 on net WDATA_S8_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_18 on net WDATA_S8_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_19 on net WDATA_S8_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_20 on net WDATA_S8_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_21 on net WDATA_S8_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_22 on net WDATA_S8_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_23 on net WDATA_S8_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_24 on net WDATA_S8_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_25 on net WDATA_S8_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_26 on net WDATA_S8_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_27 on net WDATA_S8_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_28 on net WDATA_S8_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_29 on net WDATA_S8_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_30 on net WDATA_S8_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_31 on net WDATA_S8_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_32 on net WDATA_S8_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_33 on net WDATA_S8_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_34 on net WDATA_S8_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_35 on net WDATA_S8_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_36 on net WDATA_S8_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_37 on net WDATA_S8_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_38 on net WDATA_S8_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_39 on net WDATA_S8_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_40 on net WDATA_S8_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_41 on net WDATA_S8_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_42 on net WDATA_S8_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_43 on net WDATA_S8_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_44 on net WDATA_S8_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_45 on net WDATA_S8_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_46 on net WDATA_S8_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_47 on net WDATA_S8_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_48 on net WDATA_S8_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_49 on net WDATA_S8_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_50 on net WDATA_S8_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_51 on net WDATA_S8_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_52 on net WDATA_S8_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_53 on net WDATA_S8_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_54 on net WDATA_S8_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_55 on net WDATA_S8_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_56 on net WDATA_S8_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_57 on net WDATA_S8_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_58 on net WDATA_S8_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_59 on net WDATA_S8_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_60 on net WDATA_S8_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_61 on net WDATA_S8_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_62 on net WDATA_S8_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_63 on net WDATA_S8_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Tristate driver WDATA_S8_64 on net WDATA_S8_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1202:58:1202:63|Tristate driver WID_S8_1 on net WID_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1202:58:1202:63|Tristate driver WID_S8_2 on net WID_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1202:58:1202:63|Tristate driver WID_S8_3 on net WID_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1202:58:1202:63|Tristate driver WID_S8_4 on net WID_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1199:33:1199:42|Tristate driver AWVALID_S8 on net AWVALID_S8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1198:33:1198:41|Tristate driver AWPROT_S8_1 on net AWPROT_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1198:33:1198:41|Tristate driver AWPROT_S8_2 on net AWPROT_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1198:33:1198:41|Tristate driver AWPROT_S8_3 on net AWPROT_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1197:33:1197:42|Tristate driver AWCACHE_S8_1 on net AWCACHE_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1197:33:1197:42|Tristate driver AWCACHE_S8_2 on net AWCACHE_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1197:33:1197:42|Tristate driver AWCACHE_S8_3 on net AWCACHE_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1197:33:1197:42|Tristate driver AWCACHE_S8_4 on net AWCACHE_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1196:33:1196:41|Tristate driver AWLOCK_S8_1 on net AWLOCK_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1196:33:1196:41|Tristate driver AWLOCK_S8_2 on net AWLOCK_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1195:33:1195:42|Tristate driver AWBURST_S8_1 on net AWBURST_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1195:33:1195:42|Tristate driver AWBURST_S8_2 on net AWBURST_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1194:33:1194:41|Tristate driver AWSIZE_S8_1 on net AWSIZE_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1194:33:1194:41|Tristate driver AWSIZE_S8_2 on net AWSIZE_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1194:33:1194:41|Tristate driver AWSIZE_S8_3 on net AWSIZE_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1193:33:1193:40|Tristate driver AWLEN_S8_1 on net AWLEN_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1193:33:1193:40|Tristate driver AWLEN_S8_2 on net AWLEN_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1193:33:1193:40|Tristate driver AWLEN_S8_3 on net AWLEN_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1193:33:1193:40|Tristate driver AWLEN_S8_4 on net AWLEN_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_1 on net AWADDR_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_2 on net AWADDR_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_3 on net AWADDR_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_4 on net AWADDR_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_5 on net AWADDR_S8_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_6 on net AWADDR_S8_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_7 on net AWADDR_S8_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_8 on net AWADDR_S8_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_9 on net AWADDR_S8_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_10 on net AWADDR_S8_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_11 on net AWADDR_S8_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_12 on net AWADDR_S8_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_13 on net AWADDR_S8_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_14 on net AWADDR_S8_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_15 on net AWADDR_S8_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_16 on net AWADDR_S8_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_17 on net AWADDR_S8_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_18 on net AWADDR_S8_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_19 on net AWADDR_S8_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_20 on net AWADDR_S8_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_21 on net AWADDR_S8_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_22 on net AWADDR_S8_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_23 on net AWADDR_S8_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_24 on net AWADDR_S8_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_25 on net AWADDR_S8_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_26 on net AWADDR_S8_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_27 on net AWADDR_S8_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_28 on net AWADDR_S8_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_29 on net AWADDR_S8_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_30 on net AWADDR_S8_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_31 on net AWADDR_S8_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|Tristate driver AWADDR_S8_32 on net AWADDR_S8_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1191:58:1191:64|Tristate driver AWID_S8_1 on net AWID_S8_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1191:58:1191:64|Tristate driver AWID_S8_2 on net AWID_S8_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1191:58:1191:64|Tristate driver AWID_S8_3 on net AWID_S8_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1191:58:1191:64|Tristate driver AWID_S8_4 on net AWID_S8_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1187:33:1187:41|Tristate driver RREADY_S7 on net RREADY_S7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1179:33:1179:42|Tristate driver ARVALID_S7 on net ARVALID_S7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1178:33:1178:41|Tristate driver ARPROT_S7_1 on net ARPROT_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1178:33:1178:41|Tristate driver ARPROT_S7_2 on net ARPROT_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1178:33:1178:41|Tristate driver ARPROT_S7_3 on net ARPROT_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1177:33:1177:42|Tristate driver ARCACHE_S7_1 on net ARCACHE_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1177:33:1177:42|Tristate driver ARCACHE_S7_2 on net ARCACHE_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1177:33:1177:42|Tristate driver ARCACHE_S7_3 on net ARCACHE_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1177:33:1177:42|Tristate driver ARCACHE_S7_4 on net ARCACHE_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1176:33:1176:41|Tristate driver ARLOCK_S7_1 on net ARLOCK_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1176:33:1176:41|Tristate driver ARLOCK_S7_2 on net ARLOCK_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1175:33:1175:42|Tristate driver ARBURST_S7_1 on net ARBURST_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1175:33:1175:42|Tristate driver ARBURST_S7_2 on net ARBURST_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1174:33:1174:41|Tristate driver ARSIZE_S7_1 on net ARSIZE_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1174:33:1174:41|Tristate driver ARSIZE_S7_2 on net ARSIZE_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1174:33:1174:41|Tristate driver ARSIZE_S7_3 on net ARSIZE_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1173:33:1173:40|Tristate driver ARLEN_S7_1 on net ARLEN_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1173:33:1173:40|Tristate driver ARLEN_S7_2 on net ARLEN_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1173:33:1173:40|Tristate driver ARLEN_S7_3 on net ARLEN_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1173:33:1173:40|Tristate driver ARLEN_S7_4 on net ARLEN_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_1 on net ARADDR_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_2 on net ARADDR_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_3 on net ARADDR_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_4 on net ARADDR_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_5 on net ARADDR_S7_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_6 on net ARADDR_S7_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_7 on net ARADDR_S7_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_8 on net ARADDR_S7_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_9 on net ARADDR_S7_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_10 on net ARADDR_S7_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_11 on net ARADDR_S7_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_12 on net ARADDR_S7_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_13 on net ARADDR_S7_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_14 on net ARADDR_S7_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_15 on net ARADDR_S7_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_16 on net ARADDR_S7_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_17 on net ARADDR_S7_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_18 on net ARADDR_S7_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_19 on net ARADDR_S7_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_20 on net ARADDR_S7_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_21 on net ARADDR_S7_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_22 on net ARADDR_S7_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_23 on net ARADDR_S7_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_24 on net ARADDR_S7_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_25 on net ARADDR_S7_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_26 on net ARADDR_S7_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_27 on net ARADDR_S7_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_28 on net ARADDR_S7_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_29 on net ARADDR_S7_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_30 on net ARADDR_S7_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_31 on net ARADDR_S7_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|Tristate driver ARADDR_S7_32 on net ARADDR_S7_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1171:58:1171:64|Tristate driver ARID_S7_1 on net ARID_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1171:58:1171:64|Tristate driver ARID_S7_2 on net ARID_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1171:58:1171:64|Tristate driver ARID_S7_3 on net ARID_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1171:58:1171:64|Tristate driver ARID_S7_4 on net ARID_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1169:33:1169:41|Tristate driver BREADY_S7 on net BREADY_S7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1163:33:1163:41|Tristate driver WVALID_S7 on net WVALID_S7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1162:33:1162:40|Tristate driver WLAST_S7 on net WLAST_S7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|Tristate driver WSTRB_S7_1 on net WSTRB_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|Tristate driver WSTRB_S7_2 on net WSTRB_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|Tristate driver WSTRB_S7_3 on net WSTRB_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|Tristate driver WSTRB_S7_4 on net WSTRB_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|Tristate driver WSTRB_S7_5 on net WSTRB_S7_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|Tristate driver WSTRB_S7_6 on net WSTRB_S7_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|Tristate driver WSTRB_S7_7 on net WSTRB_S7_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|Tristate driver WSTRB_S7_8 on net WSTRB_S7_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_1 on net WDATA_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_2 on net WDATA_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_3 on net WDATA_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_4 on net WDATA_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_5 on net WDATA_S7_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_6 on net WDATA_S7_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_7 on net WDATA_S7_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_8 on net WDATA_S7_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_9 on net WDATA_S7_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_10 on net WDATA_S7_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_11 on net WDATA_S7_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_12 on net WDATA_S7_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_13 on net WDATA_S7_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_14 on net WDATA_S7_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_15 on net WDATA_S7_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_16 on net WDATA_S7_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_17 on net WDATA_S7_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_18 on net WDATA_S7_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_19 on net WDATA_S7_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_20 on net WDATA_S7_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_21 on net WDATA_S7_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_22 on net WDATA_S7_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_23 on net WDATA_S7_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_24 on net WDATA_S7_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_25 on net WDATA_S7_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_26 on net WDATA_S7_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_27 on net WDATA_S7_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_28 on net WDATA_S7_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_29 on net WDATA_S7_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_30 on net WDATA_S7_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_31 on net WDATA_S7_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_32 on net WDATA_S7_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_33 on net WDATA_S7_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_34 on net WDATA_S7_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_35 on net WDATA_S7_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_36 on net WDATA_S7_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_37 on net WDATA_S7_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_38 on net WDATA_S7_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_39 on net WDATA_S7_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_40 on net WDATA_S7_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_41 on net WDATA_S7_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_42 on net WDATA_S7_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_43 on net WDATA_S7_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_44 on net WDATA_S7_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_45 on net WDATA_S7_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_46 on net WDATA_S7_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_47 on net WDATA_S7_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_48 on net WDATA_S7_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_49 on net WDATA_S7_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_50 on net WDATA_S7_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_51 on net WDATA_S7_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_52 on net WDATA_S7_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_53 on net WDATA_S7_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_54 on net WDATA_S7_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_55 on net WDATA_S7_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_56 on net WDATA_S7_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_57 on net WDATA_S7_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_58 on net WDATA_S7_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_59 on net WDATA_S7_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_60 on net WDATA_S7_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_61 on net WDATA_S7_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_62 on net WDATA_S7_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_63 on net WDATA_S7_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Tristate driver WDATA_S7_64 on net WDATA_S7_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1159:58:1159:63|Tristate driver WID_S7_1 on net WID_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1159:58:1159:63|Tristate driver WID_S7_2 on net WID_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1159:58:1159:63|Tristate driver WID_S7_3 on net WID_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1159:58:1159:63|Tristate driver WID_S7_4 on net WID_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1156:33:1156:42|Tristate driver AWVALID_S7 on net AWVALID_S7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1155:33:1155:41|Tristate driver AWPROT_S7_1 on net AWPROT_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1155:33:1155:41|Tristate driver AWPROT_S7_2 on net AWPROT_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1155:33:1155:41|Tristate driver AWPROT_S7_3 on net AWPROT_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1154:33:1154:42|Tristate driver AWCACHE_S7_1 on net AWCACHE_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1154:33:1154:42|Tristate driver AWCACHE_S7_2 on net AWCACHE_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1154:33:1154:42|Tristate driver AWCACHE_S7_3 on net AWCACHE_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1154:33:1154:42|Tristate driver AWCACHE_S7_4 on net AWCACHE_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1153:33:1153:41|Tristate driver AWLOCK_S7_1 on net AWLOCK_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1153:33:1153:41|Tristate driver AWLOCK_S7_2 on net AWLOCK_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1152:33:1152:42|Tristate driver AWBURST_S7_1 on net AWBURST_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1152:33:1152:42|Tristate driver AWBURST_S7_2 on net AWBURST_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1151:33:1151:41|Tristate driver AWSIZE_S7_1 on net AWSIZE_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1151:33:1151:41|Tristate driver AWSIZE_S7_2 on net AWSIZE_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1151:33:1151:41|Tristate driver AWSIZE_S7_3 on net AWSIZE_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1150:33:1150:40|Tristate driver AWLEN_S7_1 on net AWLEN_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1150:33:1150:40|Tristate driver AWLEN_S7_2 on net AWLEN_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1150:33:1150:40|Tristate driver AWLEN_S7_3 on net AWLEN_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1150:33:1150:40|Tristate driver AWLEN_S7_4 on net AWLEN_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_1 on net AWADDR_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_2 on net AWADDR_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_3 on net AWADDR_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_4 on net AWADDR_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_5 on net AWADDR_S7_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_6 on net AWADDR_S7_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_7 on net AWADDR_S7_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_8 on net AWADDR_S7_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_9 on net AWADDR_S7_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_10 on net AWADDR_S7_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_11 on net AWADDR_S7_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_12 on net AWADDR_S7_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_13 on net AWADDR_S7_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_14 on net AWADDR_S7_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_15 on net AWADDR_S7_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_16 on net AWADDR_S7_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_17 on net AWADDR_S7_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_18 on net AWADDR_S7_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_19 on net AWADDR_S7_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_20 on net AWADDR_S7_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_21 on net AWADDR_S7_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_22 on net AWADDR_S7_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_23 on net AWADDR_S7_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_24 on net AWADDR_S7_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_25 on net AWADDR_S7_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_26 on net AWADDR_S7_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_27 on net AWADDR_S7_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_28 on net AWADDR_S7_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_29 on net AWADDR_S7_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_30 on net AWADDR_S7_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_31 on net AWADDR_S7_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|Tristate driver AWADDR_S7_32 on net AWADDR_S7_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1148:58:1148:64|Tristate driver AWID_S7_1 on net AWID_S7_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1148:58:1148:64|Tristate driver AWID_S7_2 on net AWID_S7_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1148:58:1148:64|Tristate driver AWID_S7_3 on net AWID_S7_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1148:58:1148:64|Tristate driver AWID_S7_4 on net AWID_S7_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1144:33:1144:41|Tristate driver RREADY_S6 on net RREADY_S6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1136:33:1136:42|Tristate driver ARVALID_S6 on net ARVALID_S6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1135:33:1135:41|Tristate driver ARPROT_S6_1 on net ARPROT_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1135:33:1135:41|Tristate driver ARPROT_S6_2 on net ARPROT_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1135:33:1135:41|Tristate driver ARPROT_S6_3 on net ARPROT_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1134:33:1134:42|Tristate driver ARCACHE_S6_1 on net ARCACHE_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1134:33:1134:42|Tristate driver ARCACHE_S6_2 on net ARCACHE_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1134:33:1134:42|Tristate driver ARCACHE_S6_3 on net ARCACHE_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1134:33:1134:42|Tristate driver ARCACHE_S6_4 on net ARCACHE_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1133:33:1133:41|Tristate driver ARLOCK_S6_1 on net ARLOCK_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1133:33:1133:41|Tristate driver ARLOCK_S6_2 on net ARLOCK_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1132:33:1132:42|Tristate driver ARBURST_S6_1 on net ARBURST_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1132:33:1132:42|Tristate driver ARBURST_S6_2 on net ARBURST_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1131:33:1131:41|Tristate driver ARSIZE_S6_1 on net ARSIZE_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1131:33:1131:41|Tristate driver ARSIZE_S6_2 on net ARSIZE_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1131:33:1131:41|Tristate driver ARSIZE_S6_3 on net ARSIZE_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1130:33:1130:40|Tristate driver ARLEN_S6_1 on net ARLEN_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1130:33:1130:40|Tristate driver ARLEN_S6_2 on net ARLEN_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1130:33:1130:40|Tristate driver ARLEN_S6_3 on net ARLEN_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1130:33:1130:40|Tristate driver ARLEN_S6_4 on net ARLEN_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_1 on net ARADDR_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_2 on net ARADDR_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_3 on net ARADDR_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_4 on net ARADDR_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_5 on net ARADDR_S6_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_6 on net ARADDR_S6_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_7 on net ARADDR_S6_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_8 on net ARADDR_S6_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_9 on net ARADDR_S6_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_10 on net ARADDR_S6_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_11 on net ARADDR_S6_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_12 on net ARADDR_S6_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_13 on net ARADDR_S6_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_14 on net ARADDR_S6_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_15 on net ARADDR_S6_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_16 on net ARADDR_S6_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_17 on net ARADDR_S6_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_18 on net ARADDR_S6_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_19 on net ARADDR_S6_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_20 on net ARADDR_S6_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_21 on net ARADDR_S6_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_22 on net ARADDR_S6_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_23 on net ARADDR_S6_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_24 on net ARADDR_S6_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_25 on net ARADDR_S6_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_26 on net ARADDR_S6_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_27 on net ARADDR_S6_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_28 on net ARADDR_S6_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_29 on net ARADDR_S6_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_30 on net ARADDR_S6_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_31 on net ARADDR_S6_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|Tristate driver ARADDR_S6_32 on net ARADDR_S6_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1128:58:1128:64|Tristate driver ARID_S6_1 on net ARID_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1128:58:1128:64|Tristate driver ARID_S6_2 on net ARID_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1128:58:1128:64|Tristate driver ARID_S6_3 on net ARID_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1128:58:1128:64|Tristate driver ARID_S6_4 on net ARID_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1126:33:1126:41|Tristate driver BREADY_S6 on net BREADY_S6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1120:33:1120:41|Tristate driver WVALID_S6 on net WVALID_S6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1119:33:1119:40|Tristate driver WLAST_S6 on net WLAST_S6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|Tristate driver WSTRB_S6_1 on net WSTRB_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|Tristate driver WSTRB_S6_2 on net WSTRB_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|Tristate driver WSTRB_S6_3 on net WSTRB_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|Tristate driver WSTRB_S6_4 on net WSTRB_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|Tristate driver WSTRB_S6_5 on net WSTRB_S6_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|Tristate driver WSTRB_S6_6 on net WSTRB_S6_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|Tristate driver WSTRB_S6_7 on net WSTRB_S6_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|Tristate driver WSTRB_S6_8 on net WSTRB_S6_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_1 on net WDATA_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_2 on net WDATA_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_3 on net WDATA_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_4 on net WDATA_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_5 on net WDATA_S6_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_6 on net WDATA_S6_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_7 on net WDATA_S6_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_8 on net WDATA_S6_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_9 on net WDATA_S6_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_10 on net WDATA_S6_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_11 on net WDATA_S6_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_12 on net WDATA_S6_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_13 on net WDATA_S6_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_14 on net WDATA_S6_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_15 on net WDATA_S6_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_16 on net WDATA_S6_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_17 on net WDATA_S6_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_18 on net WDATA_S6_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_19 on net WDATA_S6_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_20 on net WDATA_S6_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_21 on net WDATA_S6_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_22 on net WDATA_S6_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_23 on net WDATA_S6_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_24 on net WDATA_S6_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_25 on net WDATA_S6_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_26 on net WDATA_S6_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_27 on net WDATA_S6_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_28 on net WDATA_S6_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_29 on net WDATA_S6_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_30 on net WDATA_S6_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_31 on net WDATA_S6_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_32 on net WDATA_S6_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_33 on net WDATA_S6_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_34 on net WDATA_S6_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_35 on net WDATA_S6_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_36 on net WDATA_S6_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_37 on net WDATA_S6_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_38 on net WDATA_S6_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_39 on net WDATA_S6_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_40 on net WDATA_S6_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_41 on net WDATA_S6_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_42 on net WDATA_S6_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_43 on net WDATA_S6_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_44 on net WDATA_S6_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_45 on net WDATA_S6_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_46 on net WDATA_S6_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_47 on net WDATA_S6_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_48 on net WDATA_S6_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_49 on net WDATA_S6_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_50 on net WDATA_S6_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_51 on net WDATA_S6_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_52 on net WDATA_S6_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_53 on net WDATA_S6_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_54 on net WDATA_S6_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_55 on net WDATA_S6_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_56 on net WDATA_S6_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_57 on net WDATA_S6_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_58 on net WDATA_S6_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_59 on net WDATA_S6_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_60 on net WDATA_S6_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_61 on net WDATA_S6_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_62 on net WDATA_S6_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_63 on net WDATA_S6_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|Tristate driver WDATA_S6_64 on net WDATA_S6_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1116:58:1116:63|Tristate driver WID_S6_1 on net WID_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1116:58:1116:63|Tristate driver WID_S6_2 on net WID_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1116:58:1116:63|Tristate driver WID_S6_3 on net WID_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1116:58:1116:63|Tristate driver WID_S6_4 on net WID_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1113:33:1113:42|Tristate driver AWVALID_S6 on net AWVALID_S6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1112:33:1112:41|Tristate driver AWPROT_S6_1 on net AWPROT_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1112:33:1112:41|Tristate driver AWPROT_S6_2 on net AWPROT_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1112:33:1112:41|Tristate driver AWPROT_S6_3 on net AWPROT_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1111:33:1111:42|Tristate driver AWCACHE_S6_1 on net AWCACHE_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1111:33:1111:42|Tristate driver AWCACHE_S6_2 on net AWCACHE_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1111:33:1111:42|Tristate driver AWCACHE_S6_3 on net AWCACHE_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1111:33:1111:42|Tristate driver AWCACHE_S6_4 on net AWCACHE_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1110:33:1110:41|Tristate driver AWLOCK_S6_1 on net AWLOCK_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1110:33:1110:41|Tristate driver AWLOCK_S6_2 on net AWLOCK_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1109:33:1109:42|Tristate driver AWBURST_S6_1 on net AWBURST_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1109:33:1109:42|Tristate driver AWBURST_S6_2 on net AWBURST_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1108:33:1108:41|Tristate driver AWSIZE_S6_1 on net AWSIZE_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1108:33:1108:41|Tristate driver AWSIZE_S6_2 on net AWSIZE_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1108:33:1108:41|Tristate driver AWSIZE_S6_3 on net AWSIZE_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1107:33:1107:40|Tristate driver AWLEN_S6_1 on net AWLEN_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1107:33:1107:40|Tristate driver AWLEN_S6_2 on net AWLEN_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1107:33:1107:40|Tristate driver AWLEN_S6_3 on net AWLEN_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1107:33:1107:40|Tristate driver AWLEN_S6_4 on net AWLEN_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_1 on net AWADDR_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_2 on net AWADDR_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_3 on net AWADDR_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_4 on net AWADDR_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_5 on net AWADDR_S6_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_6 on net AWADDR_S6_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_7 on net AWADDR_S6_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_8 on net AWADDR_S6_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_9 on net AWADDR_S6_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_10 on net AWADDR_S6_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_11 on net AWADDR_S6_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_12 on net AWADDR_S6_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_13 on net AWADDR_S6_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_14 on net AWADDR_S6_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_15 on net AWADDR_S6_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_16 on net AWADDR_S6_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_17 on net AWADDR_S6_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_18 on net AWADDR_S6_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_19 on net AWADDR_S6_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_20 on net AWADDR_S6_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_21 on net AWADDR_S6_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_22 on net AWADDR_S6_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_23 on net AWADDR_S6_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_24 on net AWADDR_S6_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_25 on net AWADDR_S6_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_26 on net AWADDR_S6_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_27 on net AWADDR_S6_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_28 on net AWADDR_S6_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_29 on net AWADDR_S6_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_30 on net AWADDR_S6_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_31 on net AWADDR_S6_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|Tristate driver AWADDR_S6_32 on net AWADDR_S6_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1105:58:1105:64|Tristate driver AWID_S6_1 on net AWID_S6_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1105:58:1105:64|Tristate driver AWID_S6_2 on net AWID_S6_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1105:58:1105:64|Tristate driver AWID_S6_3 on net AWID_S6_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1105:58:1105:64|Tristate driver AWID_S6_4 on net AWID_S6_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1101:33:1101:41|Tristate driver RREADY_S5 on net RREADY_S5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1093:33:1093:42|Tristate driver ARVALID_S5 on net ARVALID_S5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1092:33:1092:41|Tristate driver ARPROT_S5_1 on net ARPROT_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1092:33:1092:41|Tristate driver ARPROT_S5_2 on net ARPROT_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1092:33:1092:41|Tristate driver ARPROT_S5_3 on net ARPROT_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1091:33:1091:42|Tristate driver ARCACHE_S5_1 on net ARCACHE_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1091:33:1091:42|Tristate driver ARCACHE_S5_2 on net ARCACHE_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1091:33:1091:42|Tristate driver ARCACHE_S5_3 on net ARCACHE_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1091:33:1091:42|Tristate driver ARCACHE_S5_4 on net ARCACHE_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1090:33:1090:41|Tristate driver ARLOCK_S5_1 on net ARLOCK_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1090:33:1090:41|Tristate driver ARLOCK_S5_2 on net ARLOCK_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1089:33:1089:42|Tristate driver ARBURST_S5_1 on net ARBURST_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1089:33:1089:42|Tristate driver ARBURST_S5_2 on net ARBURST_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1088:33:1088:41|Tristate driver ARSIZE_S5_1 on net ARSIZE_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1088:33:1088:41|Tristate driver ARSIZE_S5_2 on net ARSIZE_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1088:33:1088:41|Tristate driver ARSIZE_S5_3 on net ARSIZE_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1087:33:1087:40|Tristate driver ARLEN_S5_1 on net ARLEN_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1087:33:1087:40|Tristate driver ARLEN_S5_2 on net ARLEN_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1087:33:1087:40|Tristate driver ARLEN_S5_3 on net ARLEN_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1087:33:1087:40|Tristate driver ARLEN_S5_4 on net ARLEN_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_1 on net ARADDR_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_2 on net ARADDR_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_3 on net ARADDR_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_4 on net ARADDR_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_5 on net ARADDR_S5_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_6 on net ARADDR_S5_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_7 on net ARADDR_S5_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_8 on net ARADDR_S5_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_9 on net ARADDR_S5_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_10 on net ARADDR_S5_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_11 on net ARADDR_S5_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_12 on net ARADDR_S5_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_13 on net ARADDR_S5_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_14 on net ARADDR_S5_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_15 on net ARADDR_S5_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_16 on net ARADDR_S5_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_17 on net ARADDR_S5_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_18 on net ARADDR_S5_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_19 on net ARADDR_S5_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_20 on net ARADDR_S5_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_21 on net ARADDR_S5_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_22 on net ARADDR_S5_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_23 on net ARADDR_S5_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_24 on net ARADDR_S5_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_25 on net ARADDR_S5_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_26 on net ARADDR_S5_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_27 on net ARADDR_S5_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_28 on net ARADDR_S5_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_29 on net ARADDR_S5_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_30 on net ARADDR_S5_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_31 on net ARADDR_S5_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|Tristate driver ARADDR_S5_32 on net ARADDR_S5_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1085:58:1085:64|Tristate driver ARID_S5_1 on net ARID_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1085:58:1085:64|Tristate driver ARID_S5_2 on net ARID_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1085:58:1085:64|Tristate driver ARID_S5_3 on net ARID_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1085:58:1085:64|Tristate driver ARID_S5_4 on net ARID_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1083:33:1083:41|Tristate driver BREADY_S5 on net BREADY_S5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1077:33:1077:41|Tristate driver WVALID_S5 on net WVALID_S5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1076:33:1076:40|Tristate driver WLAST_S5 on net WLAST_S5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|Tristate driver WSTRB_S5_1 on net WSTRB_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|Tristate driver WSTRB_S5_2 on net WSTRB_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|Tristate driver WSTRB_S5_3 on net WSTRB_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|Tristate driver WSTRB_S5_4 on net WSTRB_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|Tristate driver WSTRB_S5_5 on net WSTRB_S5_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|Tristate driver WSTRB_S5_6 on net WSTRB_S5_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|Tristate driver WSTRB_S5_7 on net WSTRB_S5_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|Tristate driver WSTRB_S5_8 on net WSTRB_S5_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_1 on net WDATA_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_2 on net WDATA_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_3 on net WDATA_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_4 on net WDATA_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_5 on net WDATA_S5_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_6 on net WDATA_S5_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_7 on net WDATA_S5_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_8 on net WDATA_S5_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_9 on net WDATA_S5_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_10 on net WDATA_S5_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_11 on net WDATA_S5_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_12 on net WDATA_S5_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_13 on net WDATA_S5_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_14 on net WDATA_S5_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_15 on net WDATA_S5_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_16 on net WDATA_S5_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_17 on net WDATA_S5_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_18 on net WDATA_S5_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_19 on net WDATA_S5_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_20 on net WDATA_S5_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_21 on net WDATA_S5_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_22 on net WDATA_S5_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_23 on net WDATA_S5_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_24 on net WDATA_S5_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_25 on net WDATA_S5_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_26 on net WDATA_S5_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_27 on net WDATA_S5_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_28 on net WDATA_S5_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_29 on net WDATA_S5_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_30 on net WDATA_S5_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_31 on net WDATA_S5_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_32 on net WDATA_S5_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_33 on net WDATA_S5_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_34 on net WDATA_S5_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_35 on net WDATA_S5_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_36 on net WDATA_S5_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_37 on net WDATA_S5_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_38 on net WDATA_S5_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_39 on net WDATA_S5_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_40 on net WDATA_S5_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_41 on net WDATA_S5_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_42 on net WDATA_S5_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_43 on net WDATA_S5_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_44 on net WDATA_S5_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_45 on net WDATA_S5_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_46 on net WDATA_S5_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_47 on net WDATA_S5_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_48 on net WDATA_S5_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_49 on net WDATA_S5_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_50 on net WDATA_S5_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_51 on net WDATA_S5_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_52 on net WDATA_S5_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_53 on net WDATA_S5_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_54 on net WDATA_S5_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_55 on net WDATA_S5_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_56 on net WDATA_S5_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_57 on net WDATA_S5_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_58 on net WDATA_S5_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_59 on net WDATA_S5_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_60 on net WDATA_S5_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_61 on net WDATA_S5_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_62 on net WDATA_S5_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_63 on net WDATA_S5_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|Tristate driver WDATA_S5_64 on net WDATA_S5_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1073:58:1073:63|Tristate driver WID_S5_1 on net WID_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1073:58:1073:63|Tristate driver WID_S5_2 on net WID_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1073:58:1073:63|Tristate driver WID_S5_3 on net WID_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1073:58:1073:63|Tristate driver WID_S5_4 on net WID_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1070:33:1070:42|Tristate driver AWVALID_S5 on net AWVALID_S5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1069:33:1069:41|Tristate driver AWPROT_S5_1 on net AWPROT_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1069:33:1069:41|Tristate driver AWPROT_S5_2 on net AWPROT_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1069:33:1069:41|Tristate driver AWPROT_S5_3 on net AWPROT_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1068:33:1068:42|Tristate driver AWCACHE_S5_1 on net AWCACHE_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1068:33:1068:42|Tristate driver AWCACHE_S5_2 on net AWCACHE_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1068:33:1068:42|Tristate driver AWCACHE_S5_3 on net AWCACHE_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1068:33:1068:42|Tristate driver AWCACHE_S5_4 on net AWCACHE_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1067:33:1067:41|Tristate driver AWLOCK_S5_1 on net AWLOCK_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1067:33:1067:41|Tristate driver AWLOCK_S5_2 on net AWLOCK_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1066:33:1066:42|Tristate driver AWBURST_S5_1 on net AWBURST_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1066:33:1066:42|Tristate driver AWBURST_S5_2 on net AWBURST_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1065:33:1065:41|Tristate driver AWSIZE_S5_1 on net AWSIZE_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1065:33:1065:41|Tristate driver AWSIZE_S5_2 on net AWSIZE_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1065:33:1065:41|Tristate driver AWSIZE_S5_3 on net AWSIZE_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1064:33:1064:40|Tristate driver AWLEN_S5_1 on net AWLEN_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1064:33:1064:40|Tristate driver AWLEN_S5_2 on net AWLEN_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1064:33:1064:40|Tristate driver AWLEN_S5_3 on net AWLEN_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1064:33:1064:40|Tristate driver AWLEN_S5_4 on net AWLEN_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_1 on net AWADDR_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_2 on net AWADDR_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_3 on net AWADDR_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_4 on net AWADDR_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_5 on net AWADDR_S5_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_6 on net AWADDR_S5_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_7 on net AWADDR_S5_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_8 on net AWADDR_S5_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_9 on net AWADDR_S5_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_10 on net AWADDR_S5_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_11 on net AWADDR_S5_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_12 on net AWADDR_S5_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_13 on net AWADDR_S5_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_14 on net AWADDR_S5_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_15 on net AWADDR_S5_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_16 on net AWADDR_S5_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_17 on net AWADDR_S5_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_18 on net AWADDR_S5_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_19 on net AWADDR_S5_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_20 on net AWADDR_S5_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_21 on net AWADDR_S5_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_22 on net AWADDR_S5_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_23 on net AWADDR_S5_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_24 on net AWADDR_S5_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_25 on net AWADDR_S5_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_26 on net AWADDR_S5_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_27 on net AWADDR_S5_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_28 on net AWADDR_S5_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_29 on net AWADDR_S5_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_30 on net AWADDR_S5_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_31 on net AWADDR_S5_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|Tristate driver AWADDR_S5_32 on net AWADDR_S5_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1062:58:1062:64|Tristate driver AWID_S5_1 on net AWID_S5_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1062:58:1062:64|Tristate driver AWID_S5_2 on net AWID_S5_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1062:58:1062:64|Tristate driver AWID_S5_3 on net AWID_S5_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1062:58:1062:64|Tristate driver AWID_S5_4 on net AWID_S5_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1058:33:1058:41|Tristate driver RREADY_S4 on net RREADY_S4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1050:33:1050:42|Tristate driver ARVALID_S4 on net ARVALID_S4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1049:33:1049:41|Tristate driver ARPROT_S4_1 on net ARPROT_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1049:33:1049:41|Tristate driver ARPROT_S4_2 on net ARPROT_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1049:33:1049:41|Tristate driver ARPROT_S4_3 on net ARPROT_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1048:33:1048:42|Tristate driver ARCACHE_S4_1 on net ARCACHE_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1048:33:1048:42|Tristate driver ARCACHE_S4_2 on net ARCACHE_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1048:33:1048:42|Tristate driver ARCACHE_S4_3 on net ARCACHE_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1048:33:1048:42|Tristate driver ARCACHE_S4_4 on net ARCACHE_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1047:33:1047:41|Tristate driver ARLOCK_S4_1 on net ARLOCK_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1047:33:1047:41|Tristate driver ARLOCK_S4_2 on net ARLOCK_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1046:33:1046:42|Tristate driver ARBURST_S4_1 on net ARBURST_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1046:33:1046:42|Tristate driver ARBURST_S4_2 on net ARBURST_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1045:33:1045:41|Tristate driver ARSIZE_S4_1 on net ARSIZE_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1045:33:1045:41|Tristate driver ARSIZE_S4_2 on net ARSIZE_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1045:33:1045:41|Tristate driver ARSIZE_S4_3 on net ARSIZE_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1044:33:1044:40|Tristate driver ARLEN_S4_1 on net ARLEN_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1044:33:1044:40|Tristate driver ARLEN_S4_2 on net ARLEN_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1044:33:1044:40|Tristate driver ARLEN_S4_3 on net ARLEN_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1044:33:1044:40|Tristate driver ARLEN_S4_4 on net ARLEN_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_1 on net ARADDR_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_2 on net ARADDR_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_3 on net ARADDR_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_4 on net ARADDR_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_5 on net ARADDR_S4_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_6 on net ARADDR_S4_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_7 on net ARADDR_S4_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_8 on net ARADDR_S4_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_9 on net ARADDR_S4_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_10 on net ARADDR_S4_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_11 on net ARADDR_S4_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_12 on net ARADDR_S4_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_13 on net ARADDR_S4_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_14 on net ARADDR_S4_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_15 on net ARADDR_S4_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_16 on net ARADDR_S4_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_17 on net ARADDR_S4_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_18 on net ARADDR_S4_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_19 on net ARADDR_S4_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_20 on net ARADDR_S4_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_21 on net ARADDR_S4_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_22 on net ARADDR_S4_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_23 on net ARADDR_S4_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_24 on net ARADDR_S4_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_25 on net ARADDR_S4_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_26 on net ARADDR_S4_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_27 on net ARADDR_S4_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_28 on net ARADDR_S4_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_29 on net ARADDR_S4_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_30 on net ARADDR_S4_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_31 on net ARADDR_S4_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|Tristate driver ARADDR_S4_32 on net ARADDR_S4_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1042:58:1042:64|Tristate driver ARID_S4_1 on net ARID_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1042:58:1042:64|Tristate driver ARID_S4_2 on net ARID_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1042:58:1042:64|Tristate driver ARID_S4_3 on net ARID_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1042:58:1042:64|Tristate driver ARID_S4_4 on net ARID_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1040:33:1040:41|Tristate driver BREADY_S4 on net BREADY_S4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1034:33:1034:41|Tristate driver WVALID_S4 on net WVALID_S4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1033:33:1033:40|Tristate driver WLAST_S4 on net WLAST_S4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|Tristate driver WSTRB_S4_1 on net WSTRB_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|Tristate driver WSTRB_S4_2 on net WSTRB_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|Tristate driver WSTRB_S4_3 on net WSTRB_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|Tristate driver WSTRB_S4_4 on net WSTRB_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|Tristate driver WSTRB_S4_5 on net WSTRB_S4_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|Tristate driver WSTRB_S4_6 on net WSTRB_S4_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|Tristate driver WSTRB_S4_7 on net WSTRB_S4_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|Tristate driver WSTRB_S4_8 on net WSTRB_S4_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_1 on net WDATA_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_2 on net WDATA_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_3 on net WDATA_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_4 on net WDATA_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_5 on net WDATA_S4_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_6 on net WDATA_S4_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_7 on net WDATA_S4_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_8 on net WDATA_S4_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_9 on net WDATA_S4_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_10 on net WDATA_S4_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_11 on net WDATA_S4_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_12 on net WDATA_S4_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_13 on net WDATA_S4_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_14 on net WDATA_S4_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_15 on net WDATA_S4_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_16 on net WDATA_S4_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_17 on net WDATA_S4_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_18 on net WDATA_S4_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_19 on net WDATA_S4_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_20 on net WDATA_S4_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_21 on net WDATA_S4_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_22 on net WDATA_S4_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_23 on net WDATA_S4_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_24 on net WDATA_S4_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_25 on net WDATA_S4_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_26 on net WDATA_S4_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_27 on net WDATA_S4_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_28 on net WDATA_S4_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_29 on net WDATA_S4_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_30 on net WDATA_S4_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_31 on net WDATA_S4_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_32 on net WDATA_S4_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_33 on net WDATA_S4_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_34 on net WDATA_S4_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_35 on net WDATA_S4_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_36 on net WDATA_S4_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_37 on net WDATA_S4_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_38 on net WDATA_S4_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_39 on net WDATA_S4_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_40 on net WDATA_S4_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_41 on net WDATA_S4_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_42 on net WDATA_S4_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_43 on net WDATA_S4_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_44 on net WDATA_S4_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_45 on net WDATA_S4_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_46 on net WDATA_S4_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_47 on net WDATA_S4_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_48 on net WDATA_S4_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_49 on net WDATA_S4_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_50 on net WDATA_S4_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_51 on net WDATA_S4_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_52 on net WDATA_S4_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_53 on net WDATA_S4_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_54 on net WDATA_S4_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_55 on net WDATA_S4_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_56 on net WDATA_S4_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_57 on net WDATA_S4_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_58 on net WDATA_S4_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_59 on net WDATA_S4_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_60 on net WDATA_S4_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_61 on net WDATA_S4_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_62 on net WDATA_S4_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_63 on net WDATA_S4_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|Tristate driver WDATA_S4_64 on net WDATA_S4_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1030:58:1030:63|Tristate driver WID_S4_1 on net WID_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1030:58:1030:63|Tristate driver WID_S4_2 on net WID_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1030:58:1030:63|Tristate driver WID_S4_3 on net WID_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1030:58:1030:63|Tristate driver WID_S4_4 on net WID_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1027:33:1027:42|Tristate driver AWVALID_S4 on net AWVALID_S4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1026:33:1026:41|Tristate driver AWPROT_S4_1 on net AWPROT_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1026:33:1026:41|Tristate driver AWPROT_S4_2 on net AWPROT_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1026:33:1026:41|Tristate driver AWPROT_S4_3 on net AWPROT_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1025:33:1025:42|Tristate driver AWCACHE_S4_1 on net AWCACHE_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1025:33:1025:42|Tristate driver AWCACHE_S4_2 on net AWCACHE_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1025:33:1025:42|Tristate driver AWCACHE_S4_3 on net AWCACHE_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1025:33:1025:42|Tristate driver AWCACHE_S4_4 on net AWCACHE_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1024:33:1024:41|Tristate driver AWLOCK_S4_1 on net AWLOCK_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1024:33:1024:41|Tristate driver AWLOCK_S4_2 on net AWLOCK_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1023:33:1023:42|Tristate driver AWBURST_S4_1 on net AWBURST_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1023:33:1023:42|Tristate driver AWBURST_S4_2 on net AWBURST_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1022:33:1022:41|Tristate driver AWSIZE_S4_1 on net AWSIZE_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1022:33:1022:41|Tristate driver AWSIZE_S4_2 on net AWSIZE_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1022:33:1022:41|Tristate driver AWSIZE_S4_3 on net AWSIZE_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1021:33:1021:40|Tristate driver AWLEN_S4_1 on net AWLEN_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1021:33:1021:40|Tristate driver AWLEN_S4_2 on net AWLEN_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1021:33:1021:40|Tristate driver AWLEN_S4_3 on net AWLEN_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1021:33:1021:40|Tristate driver AWLEN_S4_4 on net AWLEN_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_1 on net AWADDR_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_2 on net AWADDR_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_3 on net AWADDR_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_4 on net AWADDR_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_5 on net AWADDR_S4_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_6 on net AWADDR_S4_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_7 on net AWADDR_S4_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_8 on net AWADDR_S4_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_9 on net AWADDR_S4_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_10 on net AWADDR_S4_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_11 on net AWADDR_S4_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_12 on net AWADDR_S4_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_13 on net AWADDR_S4_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_14 on net AWADDR_S4_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_15 on net AWADDR_S4_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_16 on net AWADDR_S4_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_17 on net AWADDR_S4_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_18 on net AWADDR_S4_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_19 on net AWADDR_S4_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_20 on net AWADDR_S4_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_21 on net AWADDR_S4_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_22 on net AWADDR_S4_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_23 on net AWADDR_S4_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_24 on net AWADDR_S4_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_25 on net AWADDR_S4_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_26 on net AWADDR_S4_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_27 on net AWADDR_S4_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_28 on net AWADDR_S4_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_29 on net AWADDR_S4_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_30 on net AWADDR_S4_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_31 on net AWADDR_S4_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|Tristate driver AWADDR_S4_32 on net AWADDR_S4_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1019:58:1019:64|Tristate driver AWID_S4_1 on net AWID_S4_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1019:58:1019:64|Tristate driver AWID_S4_2 on net AWID_S4_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1019:58:1019:64|Tristate driver AWID_S4_3 on net AWID_S4_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1019:58:1019:64|Tristate driver AWID_S4_4 on net AWID_S4_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1015:33:1015:41|Tristate driver RREADY_S3 on net RREADY_S3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1007:33:1007:42|Tristate driver ARVALID_S3 on net ARVALID_S3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1006:33:1006:41|Tristate driver ARPROT_S3_1 on net ARPROT_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1006:33:1006:41|Tristate driver ARPROT_S3_2 on net ARPROT_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1006:33:1006:41|Tristate driver ARPROT_S3_3 on net ARPROT_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1005:33:1005:42|Tristate driver ARCACHE_S3_1 on net ARCACHE_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1005:33:1005:42|Tristate driver ARCACHE_S3_2 on net ARCACHE_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1005:33:1005:42|Tristate driver ARCACHE_S3_3 on net ARCACHE_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1005:33:1005:42|Tristate driver ARCACHE_S3_4 on net ARCACHE_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1004:33:1004:41|Tristate driver ARLOCK_S3_1 on net ARLOCK_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1004:33:1004:41|Tristate driver ARLOCK_S3_2 on net ARLOCK_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1003:33:1003:42|Tristate driver ARBURST_S3_1 on net ARBURST_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1003:33:1003:42|Tristate driver ARBURST_S3_2 on net ARBURST_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1002:33:1002:41|Tristate driver ARSIZE_S3_1 on net ARSIZE_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1002:33:1002:41|Tristate driver ARSIZE_S3_2 on net ARSIZE_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1002:33:1002:41|Tristate driver ARSIZE_S3_3 on net ARSIZE_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1001:33:1001:40|Tristate driver ARLEN_S3_1 on net ARLEN_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1001:33:1001:40|Tristate driver ARLEN_S3_2 on net ARLEN_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1001:33:1001:40|Tristate driver ARLEN_S3_3 on net ARLEN_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1001:33:1001:40|Tristate driver ARLEN_S3_4 on net ARLEN_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_1 on net ARADDR_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_2 on net ARADDR_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_3 on net ARADDR_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_4 on net ARADDR_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_5 on net ARADDR_S3_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_6 on net ARADDR_S3_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_7 on net ARADDR_S3_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_8 on net ARADDR_S3_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_9 on net ARADDR_S3_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_10 on net ARADDR_S3_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_11 on net ARADDR_S3_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_12 on net ARADDR_S3_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_13 on net ARADDR_S3_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_14 on net ARADDR_S3_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_15 on net ARADDR_S3_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_16 on net ARADDR_S3_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_17 on net ARADDR_S3_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_18 on net ARADDR_S3_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_19 on net ARADDR_S3_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_20 on net ARADDR_S3_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_21 on net ARADDR_S3_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_22 on net ARADDR_S3_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_23 on net ARADDR_S3_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_24 on net ARADDR_S3_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_25 on net ARADDR_S3_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_26 on net ARADDR_S3_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_27 on net ARADDR_S3_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_28 on net ARADDR_S3_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_29 on net ARADDR_S3_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_30 on net ARADDR_S3_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_31 on net ARADDR_S3_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|Tristate driver ARADDR_S3_32 on net ARADDR_S3_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":999:58:999:64|Tristate driver ARID_S3_1 on net ARID_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":999:58:999:64|Tristate driver ARID_S3_2 on net ARID_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":999:58:999:64|Tristate driver ARID_S3_3 on net ARID_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":999:58:999:64|Tristate driver ARID_S3_4 on net ARID_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":997:33:997:41|Tristate driver BREADY_S3 on net BREADY_S3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":991:33:991:41|Tristate driver WVALID_S3 on net WVALID_S3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":990:33:990:40|Tristate driver WLAST_S3 on net WLAST_S3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":989:33:989:40|Tristate driver WSTRB_S3_1 on net WSTRB_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":989:33:989:40|Tristate driver WSTRB_S3_2 on net WSTRB_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":989:33:989:40|Tristate driver WSTRB_S3_3 on net WSTRB_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":989:33:989:40|Tristate driver WSTRB_S3_4 on net WSTRB_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":989:33:989:40|Tristate driver WSTRB_S3_5 on net WSTRB_S3_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":989:33:989:40|Tristate driver WSTRB_S3_6 on net WSTRB_S3_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":989:33:989:40|Tristate driver WSTRB_S3_7 on net WSTRB_S3_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":989:33:989:40|Tristate driver WSTRB_S3_8 on net WSTRB_S3_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_1 on net WDATA_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_2 on net WDATA_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_3 on net WDATA_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_4 on net WDATA_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_5 on net WDATA_S3_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_6 on net WDATA_S3_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_7 on net WDATA_S3_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_8 on net WDATA_S3_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_9 on net WDATA_S3_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_10 on net WDATA_S3_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_11 on net WDATA_S3_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_12 on net WDATA_S3_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_13 on net WDATA_S3_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_14 on net WDATA_S3_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_15 on net WDATA_S3_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_16 on net WDATA_S3_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_17 on net WDATA_S3_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_18 on net WDATA_S3_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_19 on net WDATA_S3_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_20 on net WDATA_S3_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_21 on net WDATA_S3_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_22 on net WDATA_S3_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_23 on net WDATA_S3_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_24 on net WDATA_S3_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_25 on net WDATA_S3_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_26 on net WDATA_S3_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_27 on net WDATA_S3_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_28 on net WDATA_S3_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_29 on net WDATA_S3_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_30 on net WDATA_S3_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_31 on net WDATA_S3_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_32 on net WDATA_S3_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_33 on net WDATA_S3_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_34 on net WDATA_S3_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_35 on net WDATA_S3_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_36 on net WDATA_S3_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_37 on net WDATA_S3_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_38 on net WDATA_S3_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_39 on net WDATA_S3_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_40 on net WDATA_S3_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_41 on net WDATA_S3_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_42 on net WDATA_S3_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_43 on net WDATA_S3_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_44 on net WDATA_S3_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_45 on net WDATA_S3_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_46 on net WDATA_S3_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_47 on net WDATA_S3_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_48 on net WDATA_S3_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_49 on net WDATA_S3_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_50 on net WDATA_S3_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_51 on net WDATA_S3_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_52 on net WDATA_S3_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_53 on net WDATA_S3_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_54 on net WDATA_S3_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_55 on net WDATA_S3_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_56 on net WDATA_S3_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_57 on net WDATA_S3_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_58 on net WDATA_S3_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_59 on net WDATA_S3_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_60 on net WDATA_S3_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_61 on net WDATA_S3_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_62 on net WDATA_S3_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_63 on net WDATA_S3_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":988:33:988:40|Tristate driver WDATA_S3_64 on net WDATA_S3_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":987:58:987:63|Tristate driver WID_S3_1 on net WID_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":987:58:987:63|Tristate driver WID_S3_2 on net WID_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":987:58:987:63|Tristate driver WID_S3_3 on net WID_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":987:58:987:63|Tristate driver WID_S3_4 on net WID_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":984:33:984:42|Tristate driver AWVALID_S3 on net AWVALID_S3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":983:33:983:41|Tristate driver AWPROT_S3_1 on net AWPROT_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":983:33:983:41|Tristate driver AWPROT_S3_2 on net AWPROT_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":983:33:983:41|Tristate driver AWPROT_S3_3 on net AWPROT_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":982:33:982:42|Tristate driver AWCACHE_S3_1 on net AWCACHE_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":982:33:982:42|Tristate driver AWCACHE_S3_2 on net AWCACHE_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":982:33:982:42|Tristate driver AWCACHE_S3_3 on net AWCACHE_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":982:33:982:42|Tristate driver AWCACHE_S3_4 on net AWCACHE_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":981:33:981:41|Tristate driver AWLOCK_S3_1 on net AWLOCK_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":981:33:981:41|Tristate driver AWLOCK_S3_2 on net AWLOCK_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":980:33:980:42|Tristate driver AWBURST_S3_1 on net AWBURST_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":980:33:980:42|Tristate driver AWBURST_S3_2 on net AWBURST_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":979:33:979:41|Tristate driver AWSIZE_S3_1 on net AWSIZE_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":979:33:979:41|Tristate driver AWSIZE_S3_2 on net AWSIZE_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":979:33:979:41|Tristate driver AWSIZE_S3_3 on net AWSIZE_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":978:33:978:40|Tristate driver AWLEN_S3_1 on net AWLEN_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":978:33:978:40|Tristate driver AWLEN_S3_2 on net AWLEN_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":978:33:978:40|Tristate driver AWLEN_S3_3 on net AWLEN_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":978:33:978:40|Tristate driver AWLEN_S3_4 on net AWLEN_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_1 on net AWADDR_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_2 on net AWADDR_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_3 on net AWADDR_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_4 on net AWADDR_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_5 on net AWADDR_S3_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_6 on net AWADDR_S3_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_7 on net AWADDR_S3_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_8 on net AWADDR_S3_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_9 on net AWADDR_S3_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_10 on net AWADDR_S3_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_11 on net AWADDR_S3_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_12 on net AWADDR_S3_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_13 on net AWADDR_S3_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_14 on net AWADDR_S3_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_15 on net AWADDR_S3_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_16 on net AWADDR_S3_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_17 on net AWADDR_S3_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_18 on net AWADDR_S3_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_19 on net AWADDR_S3_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_20 on net AWADDR_S3_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_21 on net AWADDR_S3_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_22 on net AWADDR_S3_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_23 on net AWADDR_S3_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_24 on net AWADDR_S3_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_25 on net AWADDR_S3_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_26 on net AWADDR_S3_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_27 on net AWADDR_S3_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_28 on net AWADDR_S3_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_29 on net AWADDR_S3_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_30 on net AWADDR_S3_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_31 on net AWADDR_S3_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":977:33:977:41|Tristate driver AWADDR_S3_32 on net AWADDR_S3_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":976:58:976:64|Tristate driver AWID_S3_1 on net AWID_S3_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":976:58:976:64|Tristate driver AWID_S3_2 on net AWID_S3_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":976:58:976:64|Tristate driver AWID_S3_3 on net AWID_S3_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":976:58:976:64|Tristate driver AWID_S3_4 on net AWID_S3_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":972:33:972:41|Tristate driver RREADY_S2 on net RREADY_S2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":964:33:964:42|Tristate driver ARVALID_S2 on net ARVALID_S2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":963:33:963:41|Tristate driver ARPROT_S2_1 on net ARPROT_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":963:33:963:41|Tristate driver ARPROT_S2_2 on net ARPROT_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":963:33:963:41|Tristate driver ARPROT_S2_3 on net ARPROT_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":962:33:962:42|Tristate driver ARCACHE_S2_1 on net ARCACHE_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":962:33:962:42|Tristate driver ARCACHE_S2_2 on net ARCACHE_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":962:33:962:42|Tristate driver ARCACHE_S2_3 on net ARCACHE_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":962:33:962:42|Tristate driver ARCACHE_S2_4 on net ARCACHE_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":961:33:961:41|Tristate driver ARLOCK_S2_1 on net ARLOCK_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":961:33:961:41|Tristate driver ARLOCK_S2_2 on net ARLOCK_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":960:33:960:42|Tristate driver ARBURST_S2_1 on net ARBURST_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":960:33:960:42|Tristate driver ARBURST_S2_2 on net ARBURST_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":959:33:959:41|Tristate driver ARSIZE_S2_1 on net ARSIZE_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":959:33:959:41|Tristate driver ARSIZE_S2_2 on net ARSIZE_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":959:33:959:41|Tristate driver ARSIZE_S2_3 on net ARSIZE_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":958:33:958:40|Tristate driver ARLEN_S2_1 on net ARLEN_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":958:33:958:40|Tristate driver ARLEN_S2_2 on net ARLEN_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":958:33:958:40|Tristate driver ARLEN_S2_3 on net ARLEN_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":958:33:958:40|Tristate driver ARLEN_S2_4 on net ARLEN_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_1 on net ARADDR_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_2 on net ARADDR_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_3 on net ARADDR_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_4 on net ARADDR_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_5 on net ARADDR_S2_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_6 on net ARADDR_S2_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_7 on net ARADDR_S2_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_8 on net ARADDR_S2_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_9 on net ARADDR_S2_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_10 on net ARADDR_S2_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_11 on net ARADDR_S2_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_12 on net ARADDR_S2_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_13 on net ARADDR_S2_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_14 on net ARADDR_S2_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_15 on net ARADDR_S2_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_16 on net ARADDR_S2_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_17 on net ARADDR_S2_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_18 on net ARADDR_S2_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_19 on net ARADDR_S2_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_20 on net ARADDR_S2_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_21 on net ARADDR_S2_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_22 on net ARADDR_S2_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_23 on net ARADDR_S2_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_24 on net ARADDR_S2_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_25 on net ARADDR_S2_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_26 on net ARADDR_S2_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_27 on net ARADDR_S2_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_28 on net ARADDR_S2_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_29 on net ARADDR_S2_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_30 on net ARADDR_S2_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_31 on net ARADDR_S2_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":957:33:957:41|Tristate driver ARADDR_S2_32 on net ARADDR_S2_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":956:58:956:64|Tristate driver ARID_S2_1 on net ARID_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":956:58:956:64|Tristate driver ARID_S2_2 on net ARID_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":956:58:956:64|Tristate driver ARID_S2_3 on net ARID_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":956:58:956:64|Tristate driver ARID_S2_4 on net ARID_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":954:33:954:41|Tristate driver BREADY_S2 on net BREADY_S2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":948:33:948:41|Tristate driver WVALID_S2 on net WVALID_S2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":947:33:947:40|Tristate driver WLAST_S2 on net WLAST_S2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":946:33:946:40|Tristate driver WSTRB_S2_1 on net WSTRB_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":946:33:946:40|Tristate driver WSTRB_S2_2 on net WSTRB_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":946:33:946:40|Tristate driver WSTRB_S2_3 on net WSTRB_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":946:33:946:40|Tristate driver WSTRB_S2_4 on net WSTRB_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":946:33:946:40|Tristate driver WSTRB_S2_5 on net WSTRB_S2_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":946:33:946:40|Tristate driver WSTRB_S2_6 on net WSTRB_S2_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":946:33:946:40|Tristate driver WSTRB_S2_7 on net WSTRB_S2_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":946:33:946:40|Tristate driver WSTRB_S2_8 on net WSTRB_S2_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_1 on net WDATA_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_2 on net WDATA_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_3 on net WDATA_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_4 on net WDATA_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_5 on net WDATA_S2_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_6 on net WDATA_S2_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_7 on net WDATA_S2_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_8 on net WDATA_S2_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_9 on net WDATA_S2_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_10 on net WDATA_S2_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_11 on net WDATA_S2_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_12 on net WDATA_S2_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_13 on net WDATA_S2_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_14 on net WDATA_S2_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_15 on net WDATA_S2_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_16 on net WDATA_S2_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_17 on net WDATA_S2_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_18 on net WDATA_S2_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_19 on net WDATA_S2_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_20 on net WDATA_S2_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_21 on net WDATA_S2_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_22 on net WDATA_S2_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_23 on net WDATA_S2_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_24 on net WDATA_S2_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_25 on net WDATA_S2_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_26 on net WDATA_S2_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_27 on net WDATA_S2_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_28 on net WDATA_S2_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_29 on net WDATA_S2_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_30 on net WDATA_S2_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_31 on net WDATA_S2_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_32 on net WDATA_S2_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_33 on net WDATA_S2_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_34 on net WDATA_S2_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_35 on net WDATA_S2_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_36 on net WDATA_S2_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_37 on net WDATA_S2_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_38 on net WDATA_S2_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_39 on net WDATA_S2_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_40 on net WDATA_S2_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_41 on net WDATA_S2_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_42 on net WDATA_S2_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_43 on net WDATA_S2_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_44 on net WDATA_S2_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_45 on net WDATA_S2_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_46 on net WDATA_S2_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_47 on net WDATA_S2_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_48 on net WDATA_S2_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_49 on net WDATA_S2_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_50 on net WDATA_S2_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_51 on net WDATA_S2_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_52 on net WDATA_S2_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_53 on net WDATA_S2_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_54 on net WDATA_S2_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_55 on net WDATA_S2_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_56 on net WDATA_S2_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_57 on net WDATA_S2_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_58 on net WDATA_S2_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_59 on net WDATA_S2_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_60 on net WDATA_S2_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_61 on net WDATA_S2_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_62 on net WDATA_S2_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_63 on net WDATA_S2_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":945:33:945:40|Tristate driver WDATA_S2_64 on net WDATA_S2_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":944:58:944:63|Tristate driver WID_S2_1 on net WID_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":944:58:944:63|Tristate driver WID_S2_2 on net WID_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":944:58:944:63|Tristate driver WID_S2_3 on net WID_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":944:58:944:63|Tristate driver WID_S2_4 on net WID_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":941:33:941:42|Tristate driver AWVALID_S2 on net AWVALID_S2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":940:33:940:41|Tristate driver AWPROT_S2_1 on net AWPROT_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":940:33:940:41|Tristate driver AWPROT_S2_2 on net AWPROT_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":940:33:940:41|Tristate driver AWPROT_S2_3 on net AWPROT_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":939:33:939:42|Tristate driver AWCACHE_S2_1 on net AWCACHE_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":939:33:939:42|Tristate driver AWCACHE_S2_2 on net AWCACHE_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":939:33:939:42|Tristate driver AWCACHE_S2_3 on net AWCACHE_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":939:33:939:42|Tristate driver AWCACHE_S2_4 on net AWCACHE_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":938:33:938:41|Tristate driver AWLOCK_S2_1 on net AWLOCK_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":938:33:938:41|Tristate driver AWLOCK_S2_2 on net AWLOCK_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":937:33:937:42|Tristate driver AWBURST_S2_1 on net AWBURST_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":937:33:937:42|Tristate driver AWBURST_S2_2 on net AWBURST_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":936:33:936:41|Tristate driver AWSIZE_S2_1 on net AWSIZE_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":936:33:936:41|Tristate driver AWSIZE_S2_2 on net AWSIZE_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":936:33:936:41|Tristate driver AWSIZE_S2_3 on net AWSIZE_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":935:33:935:40|Tristate driver AWLEN_S2_1 on net AWLEN_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":935:33:935:40|Tristate driver AWLEN_S2_2 on net AWLEN_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":935:33:935:40|Tristate driver AWLEN_S2_3 on net AWLEN_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":935:33:935:40|Tristate driver AWLEN_S2_4 on net AWLEN_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_1 on net AWADDR_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_2 on net AWADDR_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_3 on net AWADDR_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_4 on net AWADDR_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_5 on net AWADDR_S2_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_6 on net AWADDR_S2_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_7 on net AWADDR_S2_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_8 on net AWADDR_S2_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_9 on net AWADDR_S2_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_10 on net AWADDR_S2_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_11 on net AWADDR_S2_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_12 on net AWADDR_S2_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_13 on net AWADDR_S2_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_14 on net AWADDR_S2_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_15 on net AWADDR_S2_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_16 on net AWADDR_S2_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_17 on net AWADDR_S2_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_18 on net AWADDR_S2_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_19 on net AWADDR_S2_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_20 on net AWADDR_S2_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_21 on net AWADDR_S2_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_22 on net AWADDR_S2_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_23 on net AWADDR_S2_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_24 on net AWADDR_S2_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_25 on net AWADDR_S2_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_26 on net AWADDR_S2_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_27 on net AWADDR_S2_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_28 on net AWADDR_S2_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_29 on net AWADDR_S2_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_30 on net AWADDR_S2_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_31 on net AWADDR_S2_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":934:33:934:41|Tristate driver AWADDR_S2_32 on net AWADDR_S2_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":933:58:933:64|Tristate driver AWID_S2_1 on net AWID_S2_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":933:58:933:64|Tristate driver AWID_S2_2 on net AWID_S2_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":933:58:933:64|Tristate driver AWID_S2_3 on net AWID_S2_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":933:58:933:64|Tristate driver AWID_S2_4 on net AWID_S2_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":929:33:929:41|Tristate driver RREADY_S1 on net RREADY_S1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":921:33:921:42|Tristate driver ARVALID_S1 on net ARVALID_S1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":920:33:920:41|Tristate driver ARPROT_S1_1 on net ARPROT_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":920:33:920:41|Tristate driver ARPROT_S1_2 on net ARPROT_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":920:33:920:41|Tristate driver ARPROT_S1_3 on net ARPROT_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":919:33:919:42|Tristate driver ARCACHE_S1_1 on net ARCACHE_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":919:33:919:42|Tristate driver ARCACHE_S1_2 on net ARCACHE_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":919:33:919:42|Tristate driver ARCACHE_S1_3 on net ARCACHE_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":919:33:919:42|Tristate driver ARCACHE_S1_4 on net ARCACHE_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":918:33:918:41|Tristate driver ARLOCK_S1_1 on net ARLOCK_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":918:33:918:41|Tristate driver ARLOCK_S1_2 on net ARLOCK_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":917:33:917:42|Tristate driver ARBURST_S1_1 on net ARBURST_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":917:33:917:42|Tristate driver ARBURST_S1_2 on net ARBURST_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":916:33:916:41|Tristate driver ARSIZE_S1_1 on net ARSIZE_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":916:33:916:41|Tristate driver ARSIZE_S1_2 on net ARSIZE_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":916:33:916:41|Tristate driver ARSIZE_S1_3 on net ARSIZE_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":915:33:915:40|Tristate driver ARLEN_S1_1 on net ARLEN_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":915:33:915:40|Tristate driver ARLEN_S1_2 on net ARLEN_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":915:33:915:40|Tristate driver ARLEN_S1_3 on net ARLEN_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":915:33:915:40|Tristate driver ARLEN_S1_4 on net ARLEN_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_1 on net ARADDR_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_2 on net ARADDR_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_3 on net ARADDR_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_4 on net ARADDR_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_5 on net ARADDR_S1_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_6 on net ARADDR_S1_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_7 on net ARADDR_S1_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_8 on net ARADDR_S1_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_9 on net ARADDR_S1_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_10 on net ARADDR_S1_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_11 on net ARADDR_S1_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_12 on net ARADDR_S1_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_13 on net ARADDR_S1_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_14 on net ARADDR_S1_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_15 on net ARADDR_S1_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_16 on net ARADDR_S1_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_17 on net ARADDR_S1_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_18 on net ARADDR_S1_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_19 on net ARADDR_S1_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_20 on net ARADDR_S1_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_21 on net ARADDR_S1_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_22 on net ARADDR_S1_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_23 on net ARADDR_S1_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_24 on net ARADDR_S1_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_25 on net ARADDR_S1_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_26 on net ARADDR_S1_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_27 on net ARADDR_S1_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_28 on net ARADDR_S1_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_29 on net ARADDR_S1_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_30 on net ARADDR_S1_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_31 on net ARADDR_S1_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":914:33:914:41|Tristate driver ARADDR_S1_32 on net ARADDR_S1_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":913:58:913:64|Tristate driver ARID_S1_1 on net ARID_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":913:58:913:64|Tristate driver ARID_S1_2 on net ARID_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":913:58:913:64|Tristate driver ARID_S1_3 on net ARID_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":913:58:913:64|Tristate driver ARID_S1_4 on net ARID_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":911:33:911:41|Tristate driver BREADY_S1 on net BREADY_S1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":905:33:905:41|Tristate driver WVALID_S1 on net WVALID_S1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":904:33:904:40|Tristate driver WLAST_S1 on net WLAST_S1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":903:33:903:40|Tristate driver WSTRB_S1_1 on net WSTRB_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":903:33:903:40|Tristate driver WSTRB_S1_2 on net WSTRB_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":903:33:903:40|Tristate driver WSTRB_S1_3 on net WSTRB_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":903:33:903:40|Tristate driver WSTRB_S1_4 on net WSTRB_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":903:33:903:40|Tristate driver WSTRB_S1_5 on net WSTRB_S1_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":903:33:903:40|Tristate driver WSTRB_S1_6 on net WSTRB_S1_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":903:33:903:40|Tristate driver WSTRB_S1_7 on net WSTRB_S1_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":903:33:903:40|Tristate driver WSTRB_S1_8 on net WSTRB_S1_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_1 on net WDATA_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_2 on net WDATA_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_3 on net WDATA_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_4 on net WDATA_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_5 on net WDATA_S1_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_6 on net WDATA_S1_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_7 on net WDATA_S1_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_8 on net WDATA_S1_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_9 on net WDATA_S1_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_10 on net WDATA_S1_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_11 on net WDATA_S1_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_12 on net WDATA_S1_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_13 on net WDATA_S1_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_14 on net WDATA_S1_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_15 on net WDATA_S1_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_16 on net WDATA_S1_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_17 on net WDATA_S1_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_18 on net WDATA_S1_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_19 on net WDATA_S1_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_20 on net WDATA_S1_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_21 on net WDATA_S1_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_22 on net WDATA_S1_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_23 on net WDATA_S1_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_24 on net WDATA_S1_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_25 on net WDATA_S1_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_26 on net WDATA_S1_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_27 on net WDATA_S1_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_28 on net WDATA_S1_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_29 on net WDATA_S1_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_30 on net WDATA_S1_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_31 on net WDATA_S1_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_32 on net WDATA_S1_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_33 on net WDATA_S1_33 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_34 on net WDATA_S1_34 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_35 on net WDATA_S1_35 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_36 on net WDATA_S1_36 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_37 on net WDATA_S1_37 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_38 on net WDATA_S1_38 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_39 on net WDATA_S1_39 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_40 on net WDATA_S1_40 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_41 on net WDATA_S1_41 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_42 on net WDATA_S1_42 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_43 on net WDATA_S1_43 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_44 on net WDATA_S1_44 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_45 on net WDATA_S1_45 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_46 on net WDATA_S1_46 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_47 on net WDATA_S1_47 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_48 on net WDATA_S1_48 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_49 on net WDATA_S1_49 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_50 on net WDATA_S1_50 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_51 on net WDATA_S1_51 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_52 on net WDATA_S1_52 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_53 on net WDATA_S1_53 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_54 on net WDATA_S1_54 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_55 on net WDATA_S1_55 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_56 on net WDATA_S1_56 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_57 on net WDATA_S1_57 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_58 on net WDATA_S1_58 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_59 on net WDATA_S1_59 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_60 on net WDATA_S1_60 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_61 on net WDATA_S1_61 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_62 on net WDATA_S1_62 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_63 on net WDATA_S1_63 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":902:33:902:40|Tristate driver WDATA_S1_64 on net WDATA_S1_64 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":901:58:901:63|Tristate driver WID_S1_1 on net WID_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":901:58:901:63|Tristate driver WID_S1_2 on net WID_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":901:58:901:63|Tristate driver WID_S1_3 on net WID_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":901:58:901:63|Tristate driver WID_S1_4 on net WID_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":898:33:898:42|Tristate driver AWVALID_S1 on net AWVALID_S1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":897:33:897:41|Tristate driver AWPROT_S1_1 on net AWPROT_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":897:33:897:41|Tristate driver AWPROT_S1_2 on net AWPROT_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":897:33:897:41|Tristate driver AWPROT_S1_3 on net AWPROT_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":896:33:896:42|Tristate driver AWCACHE_S1_1 on net AWCACHE_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":896:33:896:42|Tristate driver AWCACHE_S1_2 on net AWCACHE_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":896:33:896:42|Tristate driver AWCACHE_S1_3 on net AWCACHE_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":896:33:896:42|Tristate driver AWCACHE_S1_4 on net AWCACHE_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":895:33:895:41|Tristate driver AWLOCK_S1_1 on net AWLOCK_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":895:33:895:41|Tristate driver AWLOCK_S1_2 on net AWLOCK_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":894:33:894:42|Tristate driver AWBURST_S1_1 on net AWBURST_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":894:33:894:42|Tristate driver AWBURST_S1_2 on net AWBURST_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":893:33:893:41|Tristate driver AWSIZE_S1_1 on net AWSIZE_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":893:33:893:41|Tristate driver AWSIZE_S1_2 on net AWSIZE_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":893:33:893:41|Tristate driver AWSIZE_S1_3 on net AWSIZE_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":892:33:892:40|Tristate driver AWLEN_S1_1 on net AWLEN_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":892:33:892:40|Tristate driver AWLEN_S1_2 on net AWLEN_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":892:33:892:40|Tristate driver AWLEN_S1_3 on net AWLEN_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":892:33:892:40|Tristate driver AWLEN_S1_4 on net AWLEN_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_1 on net AWADDR_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_2 on net AWADDR_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_3 on net AWADDR_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_4 on net AWADDR_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_5 on net AWADDR_S1_5 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_6 on net AWADDR_S1_6 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_7 on net AWADDR_S1_7 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_8 on net AWADDR_S1_8 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_9 on net AWADDR_S1_9 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_10 on net AWADDR_S1_10 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_11 on net AWADDR_S1_11 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_12 on net AWADDR_S1_12 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_13 on net AWADDR_S1_13 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_14 on net AWADDR_S1_14 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_15 on net AWADDR_S1_15 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_16 on net AWADDR_S1_16 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_17 on net AWADDR_S1_17 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_18 on net AWADDR_S1_18 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_19 on net AWADDR_S1_19 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_20 on net AWADDR_S1_20 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_21 on net AWADDR_S1_21 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_22 on net AWADDR_S1_22 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_23 on net AWADDR_S1_23 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_24 on net AWADDR_S1_24 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_25 on net AWADDR_S1_25 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_26 on net AWADDR_S1_26 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_27 on net AWADDR_S1_27 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_28 on net AWADDR_S1_28 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_29 on net AWADDR_S1_29 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_30 on net AWADDR_S1_30 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_31 on net AWADDR_S1_31 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":891:33:891:41|Tristate driver AWADDR_S1_32 on net AWADDR_S1_32 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":890:58:890:64|Tristate driver AWID_S1_1 on net AWID_S1_1 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":890:58:890:64|Tristate driver AWID_S1_2 on net AWID_S1_2 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":890:58:890:64|Tristate driver AWID_S1_3 on net AWID_S1_3 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\coreaxi_0\rtl\vlog\core\coreaxi.v":890:58:890:64|Tristate driver AWID_S1_4 on net AWID_S1_4 has its enable tied to GND (module MDDR_TA_COREAXI_0_COREAXI_Z7) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\fabosc_0\mddr_ta_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module MDDR_TA_FABOSC_0_OSC) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\fabosc_0\mddr_ta_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module MDDR_TA_FABOSC_0_OSC) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\fabosc_0\mddr_ta_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module MDDR_TA_FABOSC_0_OSC) 
@W: MO111 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\fabosc_0\mddr_ta_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module MDDR_TA_FABOSC_0_OSC) 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":649:4:649:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":668:4:668:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":687:4:687:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":706:4:706:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":649:4:649:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":668:4:668:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":687:4:687:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":706:4:706:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":649:4:649:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":668:4:668:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":687:4:687:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":706:4:706:9|Sequential instance MDDR_TA_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":742:4:742:9|Sequential instance MDDR_TA_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":742:4:742:9|Sequential instance MDDR_TA_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":857:4:857:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":871:4:871:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":885:4:885:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":829:4:829:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.sm0_areset_n_rcosc_q1,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":885:4:885:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.sm0_areset_n_rcosc
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":871:4:871:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.sm0_areset_n_rcosc
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":857:4:857:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.sdif1_areset_n_rcosc,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.sm0_areset_n_rcosc
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":843:4:843:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.sdif0_areset_n_rcosc,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.sm0_areset_n_rcosc
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1530:4:1530:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif3_core,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif2_core
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1498:4:1498:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif2_core,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif1_core
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1466:4:1466:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif1_core,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif0_core
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1595:4:1595:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif3_core_q1,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif2_core_q1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1595:4:1595:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif2_core_q1,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif1_core_q1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1595:4:1595:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif1_core_q1,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif0_core_q1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1595:4:1595:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif3_core_clk_base,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif2_core_clk_base
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1595:4:1595:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif2_core_clk_base,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif1_core_clk_base
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1595:4:1595:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.release_sdif1_core_clk_base,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.release_sdif0_core_clk_base

Available hyper_sources - for debug and ip models
	None Found

@W: MO129 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1337:4:1337:9|Sequential instance MDDR_TA_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1148:0:1148:5|Removing sequential instance CUARTl1Ol of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 152MB)

Encoding state machine axi_fsm_read_state[1:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 0
   010 -> 1
Encoding state machine r_loop_state[1:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   00 -> 0
   01 -> 1
Encoding state machine w_loop_state[1:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   00 -> 0
   01 -> 1
Encoding state machine rt_state[2:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine wt_state[2:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine axi_fsm_current_state[3:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 00
   010 -> 01
   011 -> 10
   100 -> 11
Encoding state machine axi_fsm_read1_state[2:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 00
   011 -> 01
   100 -> 10
Encoding state machine ahb_state[1:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   00 -> 0
   01 -> 1
@N: FX403 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":347:0:347:5|Property "block_ram" or "no_rw_check" found for RAM Rdata_mem[63:0] with specified coding style. Inferring block RAM.
@W: FX107 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":347:0:347:5|No read/write conflict check. Possible simulation mismatch!
@N: MF707 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":347:0:347:5|Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for Rdata_mem[63:0] (view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog)).
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":211:0:211:5|Removing instance AXI_IF_0.r_xfer_size_i[9],  because it is equivalent to instance AXI_IF_0.r_xfer_size_i[3]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":211:0:211:5|Removing instance AXI_IF_0.r_xfer_size_i[3],  because it is equivalent to instance AXI_IF_0.r_xfer_size_i[2]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":211:0:211:5|Removing instance AXI_IF_0.r_xfer_size_i[2],  because it is equivalent to instance AXI_IF_0.r_xfer_size_i[1]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":211:0:211:5|Removing instance AXI_IF_0.r_xfer_size_i[1],  because it is equivalent to instance AXI_IF_0.r_xfer_size_i[0]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":169:0:169:5|Removing instance AXI_IF_0.w_xfer_size_i[9],  because it is equivalent to instance AXI_IF_0.w_xfer_size_i[3]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":169:0:169:5|Removing instance AXI_IF_0.w_xfer_size_i[3],  because it is equivalent to instance AXI_IF_0.w_xfer_size_i[2]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":169:0:169:5|Removing instance AXI_IF_0.w_xfer_size_i[2],  because it is equivalent to instance AXI_IF_0.w_xfer_size_i[1]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":169:0:169:5|Removing instance AXI_IF_0.w_xfer_size_i[1],  because it is equivalent to instance AXI_IF_0.w_xfer_size_i[0]
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":523:0:523:5|Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) inst ARADDR_1[31:7]
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":415:0:415:5|Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) inst r_clk_cnt[13:0]
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":357:0:357:5|Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) inst w_clk_cnt[13:0]
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":254:0:254:5|Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) inst AWADDR_int[31:7]
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":254:0:254:5|Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) inst WDATA_int[8:0]
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":581:0:581:5|Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) inst rburst_cnt[8:0]
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":254:0:254:5|Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) inst wburst_cnt[8:0]
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":581:0:581:5|Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) inst rdata_cnt[8:0]
@N: MF179 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":153:45:153:73|Found 10 bit by 10 bit '==' comparator, 'un5_write_idle2'
@N: MF179 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":159:43:159:70|Found 10 bit by 10 bit '==' comparator, 'un3_ahb1'
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":211:0:211:5|Removing sequential instance r_xfer_size_i[0] in hierarchy view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":169:0:169:5|Removing sequential instance w_xfer_size_i[0] in hierarchy view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) because there are no references to its outputs 
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":211:0:211:5|Removing instance AXI_IF_0.r_start,  because it is equivalent to instance AXI_IF_0.r_loop_state[0]
Encoding state machine fsm[10:0] (view:work.Control_Logic(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1000 -> 00100000000
   1001 -> 01000000000
   1010 -> 10000000000
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\clock_gen.v":962:0:962:5|Found counter in view:work.COM_Interface_COREUART_0_Clock_gen_0s(verilog) inst genblk1\.CUARTO0[12:0]
Encoding state machine CUARTO1ll[5:0] (view:work.COM_Interface_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s(verilog))
original code -> new code
   00000000000000000000000000000000 -> 000001
   00000000000000000000000000000001 -> 000010
   00000000000000000000000000000010 -> 000100
   00000000000000000000000000000011 -> 001000
   00000000000000000000000000000100 -> 010000
   00000000000000000000000000000101 -> 100000
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\tx_async.v":253:0:253:5|Register bit CUARTO1ll[4] is always 0, optimizing ...
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\tx_async.v":739:0:739:5|Removing sequential instance CUARTIO0l in hierarchy view:work.COM_Interface_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s(verilog) because there are no references to its outputs 
Encoding state machine CUARTOl0[2:0] (view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine CORECONFIGP_0.state[2:0] (view:work.MDDR_TA(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[16] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[17] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[18] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[19] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[20] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[21] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[22] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[23] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[24] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[25] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[26] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[27] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[28] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[29] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[30] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.pwdata[31] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.paddr[11] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[31],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[30]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[30],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[29]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[29],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[28]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[28],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[27]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[27],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[26]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[26],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[25]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[25],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[24]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[24],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[23]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[23],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[22]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[22],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[21]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[21],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[20]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[20],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[19]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[19],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17],  because it is equivalent to instance MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16]
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":532:4:532:9|Removing sequential instance CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.paddr[16] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31],  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28]
Encoding state machine state[20:0] (view:work.CoreConfigMaster_Z2(verilog))
original code -> new code
   00000 -> 000000000000000000001
   00001 -> 000000000000000000010
   00010 -> 000000000000000000100
   00011 -> 000000000000000001000
   00100 -> 000000000000000010000
   00101 -> 000000000000000100000
   00110 -> 000000000000001000000
   00111 -> 000000000000010000000
   01001 -> 000000000000100000000
   01010 -> 000000000001000000000
   01011 -> 000000000010000000000
   01100 -> 000000000100000000000
   01101 -> 000000001000000000000
   01110 -> 000000010000000000000
   01111 -> 000000100000000000000
   10000 -> 000001000000000000000
   10001 -> 000010000000000000000
   10010 -> 000100000000000000000
   10011 -> 001000000000000000000
   10100 -> 010000000000000000000
   10101 -> 100000000000000000000
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Found counter in view:work.CoreConfigMaster_Z2(verilog) inst pause_count[4:0]
@N: MF179 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":509:21:509:46|Found 32 bit by 32 bit '==' comparator, 'd_state128'
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Removing sequential instance HSIZE[2] in hierarchy view:work.CoreConfigMaster_Z2(verilog) because there are no references to its outputs 
Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter_0(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf0_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf0_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf0_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf0_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf0_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf0_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf0_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf0_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf0_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf0_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf0_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf0_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf0_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf0_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf2_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf2_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf2_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf2_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf2_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf2_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf2_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf2_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf2_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf2_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf2_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf2_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf2_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf2_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf3_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf3_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf3_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf3_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf3_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf3_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf3_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf1_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf1_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf1_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf1_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf1_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf1_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit awaddr_bf1_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf3_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf3_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf3_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf3_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf3_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf3_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf3_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf1_d1[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf1_d1[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf1_d1[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf1_d1[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf1_d1[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf1_d1[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Register bit araddr_bf1_d1[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit awaddr_buf_r[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit awaddr_buf_r[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit awaddr_buf_r[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit awaddr_buf_r[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit awaddr_buf_r[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit awaddr_buf_r[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit awaddr_buf_r[0] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit araddr_buf_r[6] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit araddr_buf_r[5] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit araddr_buf_r[4] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit araddr_buf_r[3] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit araddr_buf_r[2] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit araddr_buf_r[1] is always 0, optimizing ...
@W: MO160 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Register bit araddr_buf_r[0] is always 0, optimizing ...
Encoding state machine sm0_state[3:0] (view:work.CoreResetP_Z9(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
   011 -> 11
@N:"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1562:4:1562:9|Found counter in view:work.CoreResetP_Z9(verilog) inst count_ddr[13:0]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\axi_interconnect.v":9449:3:9449:8|Removing instance MDDR_TA_0.COREAXI_0.u_axi_interconnect.addr_for_wready[28],  because it is equivalent to instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[28]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\axi_interconnect.v":9449:3:9449:8|Removing instance MDDR_TA_0.COREAXI_0.u_axi_interconnect.addr_for_wready[29],  because it is equivalent to instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[29]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\axi_interconnect.v":9449:3:9449:8|Removing instance MDDR_TA_0.COREAXI_0.u_axi_interconnect.addr_for_wready[30],  because it is equivalent to instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[30]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\axi_interconnect.v":9449:3:9449:8|Removing instance MDDR_TA_0.COREAXI_0.u_axi_interconnect.addr_for_wready[31],  because it is equivalent to instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[31]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\axi_interconnect.v":9787:3:9787:8|Removing instance MDDR_TA_0.COREAXI_0.u_axi_interconnect.addr_for_rready[28],  because it is equivalent to instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[28]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\axi_interconnect.v":9787:3:9787:8|Removing instance MDDR_TA_0.COREAXI_0.u_axi_interconnect.addr_for_rready[29],  because it is equivalent to instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[29]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\axi_interconnect.v":9787:3:9787:8|Removing instance MDDR_TA_0.COREAXI_0.u_axi_interconnect.addr_for_rready[30],  because it is equivalent to instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[30]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\axi_interconnect.v":9787:3:9787:8|Removing instance MDDR_TA_0.COREAXI_0.u_axi_interconnect.addr_for_rready[31],  because it is equivalent to instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[31]
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance CORECONFIGP_0.paddr[14] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.MDDR_TA(verilog) because there are no references to its outputs 

Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 155MB peak: 156MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 152MB peak: 157MB)

@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":935:4:935:9|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf1_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf3_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf1_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf2_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf2_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.araddr_bf0_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreaxi\2.1.101\rtl\vlog\core\master_stage.v":389:3:389:8|Removing sequential instance MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf0_d1[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":967:0:967:5|Removing sequential instance COM_Interface_0.COREUART_0.CUARTIl1.CUARTI1Ol[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 157MB)

@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7],  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[3],  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15],  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6],  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14],  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10],  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2]
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: FX404 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":147:8:147:11|Found addmux in view:work.MDDR_TA_top(verilog) inst MDDR_TA_0.ConfigMaster_0.d_bytecount_0[15:0] from MDDR_TA_0.ConfigMaster_0.un1_bytecount_16[15:0] 

Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 151MB peak: 157MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 154MB peak: 157MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 153MB peak: 157MB)

@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[9],  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5]
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 

Finished preparing to map (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:08s; Memory used current: 154MB peak: 157MB)


Finished technology mapping (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 188MB peak: 190MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:10s		   -32.88ns		1610 /       954
   2		0h:00m:10s		   -32.04ns		1612 /       954
   3		0h:00m:10s		   -32.04ns		1612 /       954
------------------------------------------------------------

@N: FX271 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Instance "MDDR_TA_0.ConfigMaster_0.HADDR[0]" with 5 loads replicated 1 times to improve timing 
Timing driven replication report
Added 1 Registers via timing driven replication
Added 1 LUTs via timing driven replication

@N: FX271 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Instance "MDDR_TA_0.ConfigMaster_0.count[1]" with 32 loads replicated 1 times to improve timing 
Timing driven replication report
Added 1 Registers via timing driven replication
Added 1 LUTs via timing driven replication


Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:11s		   -20.36ns		1630 /       956
------------------------------------------------------------



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:11s		   -20.36ns		1630 /       956
------------------------------------------------------------

@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[0] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[1] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[2] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[3] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[4] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[5] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[6] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[28] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[29] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[30] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[31] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[32] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[33] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[34] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDA[35] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[0] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[1] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[2] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[3] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[4] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[5] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[6] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[7] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[8] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[9] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[10] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[11] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[12] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[13] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[14] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[15] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[16] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[17] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[18] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[19] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[20] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[21] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[22] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[23] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[24] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[25] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[26] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[27] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[28] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[29] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[30] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[31] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[32] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[33] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[34] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDA[35] in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_en of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[0] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[1] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[2] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[3] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[4] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[5] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[6] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[7] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[8] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[9] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[10] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[11] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[12] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[13] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[14] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[15] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[16] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[17] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[18] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[19] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[20] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[21] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[22] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[23] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[24] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[25] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[26] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[27] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[28] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[29] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[30] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[31] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[32] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[33] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[34] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_1_OLDB[35] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_en of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[0] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[1] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[2] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[3] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[4] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[5] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[6] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[7] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[8] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[9] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[10] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[11] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[12] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[13] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[14] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[15] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[16] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[17] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[18] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[19] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[20] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[21] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[22] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[23] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[24] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[25] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[26] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[27] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[28] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[29] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[30] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[31] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[32] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[33] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[34] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: BN362 :|Removing sequential instance AXI_IF_0.Rdata_mem_Rdata_mem_0_0_OLDB[35] of view:ACG4.SLE(PRIM) in hierarchy view:work.MDDR_TA_top(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net MDDR_TA_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_153 
@N: FP130 |Promoting Net MDDR_TA_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_154 
@N: FP130 |Promoting Net MDDR_TA_0.HPMS_READY on CLKINT  I_155 
@N: FP130 |Promoting Net MDDR_TA_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT  I_156 
@N: FP130 |Promoting Net MDDR_TA_0.CORECONFIGP_0_APB_S_PCLK on CLKINT  I_157 
@N: FP130 |Promoting Net MDDR_TA_0_INIT_DONE on CLKINT  I_158 

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:11s; Memory used current: 161MB peak: 190MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:11s; Memory used current: 162MB peak: 190MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
3 non-gated/non-generated clock tree(s) driving 907 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 57 clock pin(s) of sequential element(s)
0 instances converted, 57 sequential instances remain driven by gated/generated clocks

========================================================= Non-Gated/Non-Generated Clocks =========================================================
Clock Tree ID     Driving Element                             Drive Element Type     Fanout     Sample Instance                                   
--------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0002       MDDR_TA_0.CCC_0.GL2_INST                    CLKINT                 464        MDDR_TA_0.COREAXI_0.master_stage0.araddr_buf_r[30]
@K:CKID0003       MDDR_TA_0.CCC_0.GL0_INST                    CLKINT                 423        MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST           
@K:CKID0004       MDDR_TA_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB     RCOSC_25_50MHZ_FAB     20         MDDR_TA_0.CORERESETP_0.count_ddr[13]              
==================================================================================================================================================
============================================================================================== Gated/Generated Clocks ==============================================================================================
Clock Tree ID     Driving Element                             Drive Element Type     Fanout     Sample Instance                             Explanation                                                             
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MSS_010                57         MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     No generated or derived clock directive on output of sequential instance
====================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:13s; Memory used current: 155MB peak: 190MB)

Writing EDIF Netlist and constraint files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
I-2013.09M-SP1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:14s; Memory used current: 156MB peak: 190MB)

@W: MT246 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\mddr_ta.v":2079:9:2079:20|Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\mddr_ta\ccc_0\mddr_ta_ccc_0_fccc.v":23:36:23:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock with period 2.50ns. Please declare a user-defined clock on object "n:MDDR_TA_0.MDDR_TA_HPMS_0.FIC_2_APB_M_PCLK"

@W: MT420 |Found inferred clock MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 2.50ns. Please declare a user-defined clock on object "n:MDDR_TA_0.FABOSC_0.RCOSC_25_50MHZ_CCC"

@W: MT420 |Found inferred clock MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock with period 2.50ns. Please declare a user-defined clock on object "n:MDDR_TA_0.CCC_0.GL2_net"

@W: MT420 |Found inferred clock MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock with period 2.50ns. Please declare a user-defined clock on object "n:MDDR_TA_0.CCC_0.GL0_net"



##### START OF TIMING REPORT #####[
# Timing Report written on Thu Mar 27 12:20:34 2014
#


Top view:               MDDR_TA_top
Requested Frequency:    400.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: -6.815

                                                           Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock                                             Frequency     Frequency     Period        Period        Slack      Type         Group              
--------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock                  400.0 MHz     123.4 MHz     2.500         8.103         -5.603     inferred     Inferred_clkgroup_1
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock                  400.0 MHz     107.4 MHz     2.500         9.315         -6.815     inferred     Inferred_clkgroup_3
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     400.0 MHz     400.2 MHz     2.500         2.499         0.001      inferred     Inferred_clkgroup_2
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock               400.0 MHz     161.8 MHz     2.500         6.181         -3.682     inferred     Inferred_clkgroup_0
System                                                     400.0 MHz     293.1 MHz     2.500         3.412         -0.912     system       system_clkgroup    
==============================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise  
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                Ending                                                  |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  2.500       -0.912  |  No paths    -      |  No paths    -       |  No paths    -     
System                                                  MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               |  2.500       1.026   |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock            |  2.500       -3.682  |  No paths    -      |  1.250       -0.888  |  1.250       -1.621
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               System                                                  |  2.500       -2.484  |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock            |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  2.500       -5.603  |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  |  2.500       0.001   |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               System                                                  |  2.500       -0.754  |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -     
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               |  2.500       -6.815  |  No paths    -      |  No paths    -       |  No paths    -     
=========================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                    Starting                                                                                                          Arrival           
Instance                                                            Reference                                     Type        Pin                Net                                  Time        Slack 
                                                                    Clock                                                                                                                               
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.ConfigMaster_0.bytecount[12]                              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  bytecount[12]                        0.094       -5.603
MDDR_TA_0.ConfigMaster_0.bytecount[9]                               MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  bytecount[9]                         0.094       -5.542
MDDR_TA_0.ConfigMaster_0.bytecount[8]                               MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  bytecount[8]                         0.094       -5.498
MDDR_TA_0.ConfigMaster_0.bytecount[13]                              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  bytecount[13]                        0.094       -5.419
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST                             MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_FM0_READYOUT     CoreAHBLite_0_AHBmslave16_HREADY     2.383       -5.378
MDDR_TA_0.ConfigMaster_0.bytecount[14]                              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  bytecount[14]                        0.094       -5.352
MDDR_TA_0.ConfigMaster_0.bytecount[15]                              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  bytecount[15]                        0.094       -5.309
MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3]     MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[3]                       0.076       -4.884
MDDR_TA_0.ConfigMaster_0.bytecount[4]                               MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  bytecount[4]                         0.094       -4.723
MDDR_TA_0.ConfigMaster_0.bytecount[11]                              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  bytecount[11]                        0.094       -4.687
========================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                           Starting                                                                                Required           
Instance                                   Reference                                     Type     Pin     Net                      Time         Slack 
                                           Clock                                                                                                      
------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.ConfigMaster_0.count[1]          MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_count[1]               2.278        -5.603
MDDR_TA_0.ConfigMaster_0.count_fast[1]     MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_count_fast[1]          2.278        -5.603
MDDR_TA_0.ConfigMaster_0.HADDR[23]         MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_HADDR[23]              2.348        -5.378
MDDR_TA_0.ConfigMaster_0.HADDR[30]         MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_HADDR_0_iv_i_0[30]     2.278        -4.904
MDDR_TA_0.ConfigMaster_0.HADDR[0]          MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_HADDR[0]               2.278        -4.841
MDDR_TA_0.ConfigMaster_0.HADDR_fast[0]     MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_HADDR_fast[0]          2.278        -4.841
MDDR_TA_0.ConfigMaster_0.HADDR[3]          MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_HADDR_0_iv_i_0[3]      2.278        -4.776
MDDR_TA_0.ConfigMaster_0.HADDR[6]          MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_HADDR_0_iv_i_0[6]      2.278        -4.776
MDDR_TA_0.ConfigMaster_0.HADDR[15]         MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_HADDR_0_iv_i_0[15]     2.278        -4.776
MDDR_TA_0.ConfigMaster_0.HADDR[16]         MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       d_HADDR_0_iv_i_0[16]     2.278        -4.776
======================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      7.881
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -5.603

    Number of logic level(s):                9
    Starting point:                          MDDR_TA_0.ConfigMaster_0.bytecount[12] / Q
    Ending point:                            MDDR_TA_0.ConfigMaster_0.count[1] / D
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                              Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
MDDR_TA_0.ConfigMaster_0.bytecount[12]            SLE      Q        Out     0.094     0.094       -         
bytecount[12]                                     Net      -        -       0.587     -           2         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_4         CFG4     D        In      -         0.681       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_4         CFG4     Y        Out     0.384     1.065       -         
d_HWRITE51_2_0_4                                  Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     C        In      -         1.548       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     Y        Out     0.182     1.730       -         
d_HWRITE51_2_0                                    Net      -        -       0.590     -           3         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     D        In      -         2.320       -         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     Y        Out     0.411     2.731       -         
N_208                                             Net      -        -       0.706     -           8         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     C        In      -         3.437       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     Y        Out     0.182     3.619       -         
N_210                                             Net      -        -       1.008     -           57        
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     C        In      -         4.628       -         
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     Y        Out     0.200     4.827       -         
N_353                                             Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     C        In      -         5.311       -         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     Y        Out     0.182     5.493       -         
d_count_0_2[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     D        In      -         5.976       -         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     Y        Out     0.372     6.348       -         
d_count_0_3[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     C        In      -         6.831       -         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     Y        Out     0.182     7.013       -         
d_count_0_5[1]                                    Net      -        -       0.548     -           2         
MDDR_TA_0.ConfigMaster_0.count_RNO[1]             CFG4     C        In      -         7.561       -         
MDDR_TA_0.ConfigMaster_0.count_RNO[1]             CFG4     Y        Out     0.182     7.743       -         
d_count[1]                                        Net      -        -       0.138     -           1         
MDDR_TA_0.ConfigMaster_0.count[1]                 SLE      D        In      -         7.881       -         
============================================================================================================
Total path delay (propagation time + setup) of 8.103 is 2.594(32.0%) logic and 5.509(68.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      7.881
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -5.603

    Number of logic level(s):                9
    Starting point:                          MDDR_TA_0.ConfigMaster_0.bytecount[12] / Q
    Ending point:                            MDDR_TA_0.ConfigMaster_0.count_fast[1] / D
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                              Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
MDDR_TA_0.ConfigMaster_0.bytecount[12]            SLE      Q        Out     0.094     0.094       -         
bytecount[12]                                     Net      -        -       0.587     -           2         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_4         CFG4     D        In      -         0.681       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_4         CFG4     Y        Out     0.384     1.065       -         
d_HWRITE51_2_0_4                                  Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     C        In      -         1.548       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     Y        Out     0.182     1.730       -         
d_HWRITE51_2_0                                    Net      -        -       0.590     -           3         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     D        In      -         2.320       -         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     Y        Out     0.411     2.731       -         
N_208                                             Net      -        -       0.706     -           8         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     C        In      -         3.437       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     Y        Out     0.182     3.619       -         
N_210                                             Net      -        -       1.008     -           57        
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     C        In      -         4.628       -         
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     Y        Out     0.200     4.827       -         
N_353                                             Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     C        In      -         5.311       -         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     Y        Out     0.182     5.493       -         
d_count_0_2[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     D        In      -         5.976       -         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     Y        Out     0.372     6.348       -         
d_count_0_3[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     C        In      -         6.831       -         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     Y        Out     0.182     7.013       -         
d_count_0_5[1]                                    Net      -        -       0.548     -           2         
MDDR_TA_0.ConfigMaster_0.count_fast_RNO[1]        CFG4     C        In      -         7.561       -         
MDDR_TA_0.ConfigMaster_0.count_fast_RNO[1]        CFG4     Y        Out     0.182     7.743       -         
d_count_fast[1]                                   Net      -        -       0.138     -           1         
MDDR_TA_0.ConfigMaster_0.count_fast[1]            SLE      D        In      -         7.881       -         
============================================================================================================
Total path delay (propagation time + setup) of 8.103 is 2.594(32.0%) logic and 5.509(68.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      7.820
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -5.542

    Number of logic level(s):                9
    Starting point:                          MDDR_TA_0.ConfigMaster_0.bytecount[9] / Q
    Ending point:                            MDDR_TA_0.ConfigMaster_0.count[1] / D
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                              Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
MDDR_TA_0.ConfigMaster_0.bytecount[9]             SLE      Q        Out     0.094     0.094       -         
bytecount[9]                                      Net      -        -       0.587     -           2         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_3         CFG2     B        In      -         0.681       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_3         CFG2     Y        Out     0.133     0.814       -         
d_HWRITE51_2_0_3                                  Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     D        In      -         1.297       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     Y        Out     0.372     1.669       -         
d_HWRITE51_2_0                                    Net      -        -       0.590     -           3         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     D        In      -         2.259       -         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     Y        Out     0.411     2.670       -         
N_208                                             Net      -        -       0.706     -           8         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     C        In      -         3.376       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     Y        Out     0.182     3.558       -         
N_210                                             Net      -        -       1.008     -           57        
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     C        In      -         4.566       -         
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     Y        Out     0.200     4.766       -         
N_353                                             Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     C        In      -         5.249       -         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     Y        Out     0.182     5.431       -         
d_count_0_2[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     D        In      -         5.915       -         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     Y        Out     0.372     6.287       -         
d_count_0_3[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     C        In      -         6.770       -         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     Y        Out     0.182     6.952       -         
d_count_0_5[1]                                    Net      -        -       0.548     -           2         
MDDR_TA_0.ConfigMaster_0.count_RNO[1]             CFG4     C        In      -         7.500       -         
MDDR_TA_0.ConfigMaster_0.count_RNO[1]             CFG4     Y        Out     0.182     7.682       -         
d_count[1]                                        Net      -        -       0.138     -           1         
MDDR_TA_0.ConfigMaster_0.count[1]                 SLE      D        In      -         7.820       -         
============================================================================================================
Total path delay (propagation time + setup) of 8.042 is 2.533(31.5%) logic and 5.509(68.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      7.820
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -5.542

    Number of logic level(s):                9
    Starting point:                          MDDR_TA_0.ConfigMaster_0.bytecount[9] / Q
    Ending point:                            MDDR_TA_0.ConfigMaster_0.count_fast[1] / D
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                              Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
MDDR_TA_0.ConfigMaster_0.bytecount[9]             SLE      Q        Out     0.094     0.094       -         
bytecount[9]                                      Net      -        -       0.587     -           2         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_3         CFG2     B        In      -         0.681       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_3         CFG2     Y        Out     0.133     0.814       -         
d_HWRITE51_2_0_3                                  Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     D        In      -         1.297       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     Y        Out     0.372     1.669       -         
d_HWRITE51_2_0                                    Net      -        -       0.590     -           3         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     D        In      -         2.259       -         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     Y        Out     0.411     2.670       -         
N_208                                             Net      -        -       0.706     -           8         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     C        In      -         3.376       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     Y        Out     0.182     3.558       -         
N_210                                             Net      -        -       1.008     -           57        
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     C        In      -         4.566       -         
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     Y        Out     0.200     4.766       -         
N_353                                             Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     C        In      -         5.249       -         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     Y        Out     0.182     5.431       -         
d_count_0_2[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     D        In      -         5.915       -         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     Y        Out     0.372     6.287       -         
d_count_0_3[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     C        In      -         6.770       -         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     Y        Out     0.182     6.952       -         
d_count_0_5[1]                                    Net      -        -       0.548     -           2         
MDDR_TA_0.ConfigMaster_0.count_fast_RNO[1]        CFG4     C        In      -         7.500       -         
MDDR_TA_0.ConfigMaster_0.count_fast_RNO[1]        CFG4     Y        Out     0.182     7.682       -         
d_count_fast[1]                                   Net      -        -       0.138     -           1         
MDDR_TA_0.ConfigMaster_0.count_fast[1]            SLE      D        In      -         7.820       -         
============================================================================================================
Total path delay (propagation time + setup) of 8.042 is 2.533(31.5%) logic and 5.509(68.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      7.777
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -5.498

    Number of logic level(s):                9
    Starting point:                          MDDR_TA_0.ConfigMaster_0.bytecount[8] / Q
    Ending point:                            MDDR_TA_0.ConfigMaster_0.count[1] / D
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                              Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
MDDR_TA_0.ConfigMaster_0.bytecount[8]             SLE      Q        Out     0.094     0.094       -         
bytecount[8]                                      Net      -        -       0.587     -           2         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_3         CFG2     A        In      -         0.681       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0_3         CFG2     Y        Out     0.090     0.770       -         
d_HWRITE51_2_0_3                                  Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     D        In      -         1.254       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_2_0           CFG4     Y        Out     0.372     1.626       -         
d_HWRITE51_2_0                                    Net      -        -       0.590     -           3         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     D        In      -         2.216       -         
MDDR_TA_0.ConfigMaster_0.d_haddr_write11_0_o2     CFG4     Y        Out     0.411     2.626       -         
N_208                                             Net      -        -       0.706     -           8         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     C        In      -         3.332       -         
MDDR_TA_0.ConfigMaster_0.d_HWRITE51_0_o2          CFG3     Y        Out     0.182     3.515       -         
N_210                                             Net      -        -       1.008     -           57        
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     C        In      -         4.523       -         
MDDR_TA_0.ConfigMaster_0.count_RNIE33B1[1]        CFG4     Y        Out     0.200     4.723       -         
N_353                                             Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     C        In      -         5.206       -         
MDDR_TA_0.ConfigMaster_0.state_RNILIMD4[6]        CFG4     Y        Out     0.182     5.388       -         
d_count_0_2[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     D        In      -         5.871       -         
MDDR_TA_0.ConfigMaster_0.state_RNIVOFQ4[6]        CFG4     Y        Out     0.372     6.243       -         
d_count_0_3[1]                                    Net      -        -       0.483     -           1         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     C        In      -         6.726       -         
MDDR_TA_0.ConfigMaster_0.state_RNIAGHF7[6]        CFG4     Y        Out     0.182     6.909       -         
d_count_0_5[1]                                    Net      -        -       0.548     -           2         
MDDR_TA_0.ConfigMaster_0.count_RNO[1]             CFG4     C        In      -         7.457       -         
MDDR_TA_0.ConfigMaster_0.count_RNO[1]             CFG4     Y        Out     0.182     7.639       -         
d_count[1]                                        Net      -        -       0.138     -           1         
MDDR_TA_0.ConfigMaster_0.count[1]                 SLE      D        In      -         7.777       -         
============================================================================================================
Total path delay (propagation time + setup) of 7.998 is 2.489(31.1%) logic and 5.509(68.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                    Starting                                                                         Arrival           
Instance                                            Reference                                     Type     Pin     Net               Time        Slack 
                                                    Clock                                                                                              
-------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0]       MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       wreq_set[0]       0.094       -6.815
MDDR_TA_0.COREAXI_0.master_stage0.wreq_reset[0]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       wreq_reset[0]     0.094       -6.761
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[1]       MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       wreq_set[1]       0.094       -6.609
MDDR_TA_0.COREAXI_0.master_stage0.wreq_reset[1]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       wreq_reset[1]     0.094       -6.556
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[2]       MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       wreq_set[2]       0.094       -6.553
MDDR_TA_0.COREAXI_0.master_stage0.rreq_set[0]       MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       rreq_set[0]       0.094       -6.534
MDDR_TA_0.COREAXI_0.master_stage0.wreq_reset[2]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       wreq_reset[2]     0.094       -6.499
MDDR_TA_0.COREAXI_0.master_stage0.rreq_reset[0]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       rreq_reset[0]     0.094       -6.481
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[3]       MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       wreq_set[3]       0.094       -6.327
MDDR_TA_0.COREAXI_0.master_stage0.rreq_set[1]       MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       rreq_set[1]       0.094       -6.293
=======================================================================================================================================================


Ending Points with Worst Slack
******************************

                           Starting                                                                       Required           
Instance                   Reference                                     Type     Pin     Net             Time         Slack 
                           Clock                                                                                             
-----------------------------------------------------------------------------------------------------------------------------
AXI_IF_0.WDATA_int[0]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.WDATA_int[1]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.WDATA_int[2]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.WDATA_int[3]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.WDATA_int[4]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.WDATA_int[5]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.WDATA_int[6]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.WDATA_int[7]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.WDATA_int[8]      MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      N_342_i_0       2.207        -6.815
AXI_IF_0.wburst_cnt[0]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      wburst_cnte     2.207        -6.815
=============================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      2.500
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.207

    - Propagation time:                      9.021
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -6.815

    Number of logic level(s):                8
    Starting point:                          MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0] / Q
    Ending point:                            AXI_IF_0.wburst_cnt[0] / EN
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK

Instance / Net                                                              Pin      Pin               Arrival     No. of    
Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0]                      SLE      Q        Out     0.094     0.094       -         
wreq_set[0]                                                        Net      -        -       0.745     -           3         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     B        In      -         0.839       -         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     Y        Out     0.143     0.982       -         
pending_wr_req[0]                                                  Net      -        -       0.859     -           9         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     D        In      -         1.841       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     Y        Out     0.408     2.249       -         
awaddr_bf038                                                       Net      -        -       0.761     -           12        
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     B        In      -         3.010       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     Y        Out     0.133     3.143       -         
un1_N_4_mux_0_1                                                    Net      -        -       0.622     -           4         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     D        In      -         3.765       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     Y        Out     0.411     4.176       -         
awaddr_bf3_m[29]                                                   Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     D        In      -         4.659       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     Y        Out     0.411     5.070       -         
awaddr_m1_0_a2_2_2                                                 Net      -        -       0.548     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     D        In      -         5.618       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     Y        Out     0.408     6.026       -         
SLAVE_SELECT_WDCH_M19_1                                            Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     C        In      -         6.510       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     Y        Out     0.182     6.692       -         
SLAVE_SELECT_WDCH_M19                                              Net      -        -       1.063     -           78        
AXI_IF_0.axi_fsm_current_state_RNI13MU2[0]                         CFG4     D        In      -         7.754       -         
AXI_IF_0.axi_fsm_current_state_RNI13MU2[0]                         CFG4     Y        Out     0.408     8.163       -         
wburst_cnte                                                        Net      -        -       0.859     -           9         
AXI_IF_0.wburst_cnt[0]                                             SLE      EN       In      -         9.021       -         
=============================================================================================================================
Total path delay (propagation time + setup) of 9.315 is 2.893(31.1%) logic and 6.422(68.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      2.500
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.207

    - Propagation time:                      9.021
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -6.815

    Number of logic level(s):                8
    Starting point:                          MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0] / Q
    Ending point:                            AXI_IF_0.WDATA_int[0] / EN
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK

Instance / Net                                                              Pin      Pin               Arrival     No. of    
Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0]                      SLE      Q        Out     0.094     0.094       -         
wreq_set[0]                                                        Net      -        -       0.745     -           3         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     B        In      -         0.839       -         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     Y        Out     0.143     0.982       -         
pending_wr_req[0]                                                  Net      -        -       0.859     -           9         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     D        In      -         1.841       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     Y        Out     0.408     2.249       -         
awaddr_bf038                                                       Net      -        -       0.761     -           12        
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     B        In      -         3.010       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     Y        Out     0.133     3.143       -         
un1_N_4_mux_0_1                                                    Net      -        -       0.622     -           4         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     D        In      -         3.765       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     Y        Out     0.411     4.176       -         
awaddr_bf3_m[29]                                                   Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     D        In      -         4.659       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     Y        Out     0.411     5.070       -         
awaddr_m1_0_a2_2_2                                                 Net      -        -       0.548     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     D        In      -         5.618       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     Y        Out     0.408     6.026       -         
SLAVE_SELECT_WDCH_M19_1                                            Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     C        In      -         6.510       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     Y        Out     0.182     6.692       -         
SLAVE_SELECT_WDCH_M19                                              Net      -        -       1.063     -           78        
AXI_IF_0.un1_WSTRB_0_sqmuxa_1_i_0_1_RNIB4RJ1                       CFG4     D        In      -         7.754       -         
AXI_IF_0.un1_WSTRB_0_sqmuxa_1_i_0_1_RNIB4RJ1                       CFG4     Y        Out     0.408     8.163       -         
N_342_i_0                                                          Net      -        -       0.859     -           9         
AXI_IF_0.WDATA_int[0]                                              SLE      EN       In      -         9.021       -         
=============================================================================================================================
Total path delay (propagation time + setup) of 9.315 is 2.893(31.1%) logic and 6.422(68.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      2.500
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.207

    - Propagation time:                      9.021
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -6.815

    Number of logic level(s):                8
    Starting point:                          MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0] / Q
    Ending point:                            AXI_IF_0.wburst_cnt[8] / EN
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK

Instance / Net                                                              Pin      Pin               Arrival     No. of    
Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0]                      SLE      Q        Out     0.094     0.094       -         
wreq_set[0]                                                        Net      -        -       0.745     -           3         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     B        In      -         0.839       -         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     Y        Out     0.143     0.982       -         
pending_wr_req[0]                                                  Net      -        -       0.859     -           9         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     D        In      -         1.841       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     Y        Out     0.408     2.249       -         
awaddr_bf038                                                       Net      -        -       0.761     -           12        
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     B        In      -         3.010       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     Y        Out     0.133     3.143       -         
un1_N_4_mux_0_1                                                    Net      -        -       0.622     -           4         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     D        In      -         3.765       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     Y        Out     0.411     4.176       -         
awaddr_bf3_m[29]                                                   Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     D        In      -         4.659       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     Y        Out     0.411     5.070       -         
awaddr_m1_0_a2_2_2                                                 Net      -        -       0.548     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     D        In      -         5.618       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     Y        Out     0.408     6.026       -         
SLAVE_SELECT_WDCH_M19_1                                            Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     C        In      -         6.510       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     Y        Out     0.182     6.692       -         
SLAVE_SELECT_WDCH_M19                                              Net      -        -       1.063     -           78        
AXI_IF_0.axi_fsm_current_state_RNI13MU2[0]                         CFG4     D        In      -         7.754       -         
AXI_IF_0.axi_fsm_current_state_RNI13MU2[0]                         CFG4     Y        Out     0.408     8.163       -         
wburst_cnte                                                        Net      -        -       0.859     -           9         
AXI_IF_0.wburst_cnt[8]                                             SLE      EN       In      -         9.021       -         
=============================================================================================================================
Total path delay (propagation time + setup) of 9.315 is 2.893(31.1%) logic and 6.422(68.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      2.500
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.207

    - Propagation time:                      9.021
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -6.815

    Number of logic level(s):                8
    Starting point:                          MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0] / Q
    Ending point:                            AXI_IF_0.wburst_cnt[7] / EN
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK

Instance / Net                                                              Pin      Pin               Arrival     No. of    
Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0]                      SLE      Q        Out     0.094     0.094       -         
wreq_set[0]                                                        Net      -        -       0.745     -           3         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     B        In      -         0.839       -         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     Y        Out     0.143     0.982       -         
pending_wr_req[0]                                                  Net      -        -       0.859     -           9         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     D        In      -         1.841       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     Y        Out     0.408     2.249       -         
awaddr_bf038                                                       Net      -        -       0.761     -           12        
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     B        In      -         3.010       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     Y        Out     0.133     3.143       -         
un1_N_4_mux_0_1                                                    Net      -        -       0.622     -           4         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     D        In      -         3.765       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     Y        Out     0.411     4.176       -         
awaddr_bf3_m[29]                                                   Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     D        In      -         4.659       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     Y        Out     0.411     5.070       -         
awaddr_m1_0_a2_2_2                                                 Net      -        -       0.548     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     D        In      -         5.618       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     Y        Out     0.408     6.026       -         
SLAVE_SELECT_WDCH_M19_1                                            Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     C        In      -         6.510       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     Y        Out     0.182     6.692       -         
SLAVE_SELECT_WDCH_M19                                              Net      -        -       1.063     -           78        
AXI_IF_0.axi_fsm_current_state_RNI13MU2[0]                         CFG4     D        In      -         7.754       -         
AXI_IF_0.axi_fsm_current_state_RNI13MU2[0]                         CFG4     Y        Out     0.408     8.163       -         
wburst_cnte                                                        Net      -        -       0.859     -           9         
AXI_IF_0.wburst_cnt[7]                                             SLE      EN       In      -         9.021       -         
=============================================================================================================================
Total path delay (propagation time + setup) of 9.315 is 2.893(31.1%) logic and 6.422(68.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      2.500
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.207

    - Propagation time:                      9.021
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -6.815

    Number of logic level(s):                8
    Starting point:                          MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0] / Q
    Ending point:                            AXI_IF_0.wburst_cnt[6] / EN
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK

Instance / Net                                                              Pin      Pin               Arrival     No. of    
Name                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.COREAXI_0.master_stage0.wreq_set[0]                      SLE      Q        Out     0.094     0.094       -         
wreq_set[0]                                                        Net      -        -       0.745     -           3         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     B        In      -         0.839       -         
MDDR_TA_0.COREAXI_0.master_stage0.pending_wr_req[0]                CFG2     Y        Out     0.143     0.982       -         
pending_wr_req[0]                                                  Net      -        -       0.859     -           9         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     D        In      -         1.841       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf038                     CFG4     Y        Out     0.408     2.249       -         
awaddr_bf038                                                       Net      -        -       0.761     -           12        
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     B        In      -         3.010       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf021_2_RNINE7B1_0        CFG4     Y        Out     0.133     3.143       -         
un1_N_4_mux_0_1                                                    Net      -        -       0.622     -           4         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     D        In      -         3.765       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_bf3_d1_RNI9PFB2[29]       CFG4     Y        Out     0.411     4.176       -         
awaddr_bf3_m[29]                                                   Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     D        In      -         4.659       -         
MDDR_TA_0.COREAXI_0.master_stage0.awaddr_buf_r_RNI54385[29]        CFG4     Y        Out     0.411     5.070       -         
awaddr_m1_0_a2_2_2                                                 Net      -        -       0.548     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     D        In      -         5.618       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_1     CFG4     Y        Out     0.408     6.026       -         
SLAVE_SELECT_WDCH_M19_1                                            Net      -        -       0.483     -           1         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     C        In      -         6.510       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19       CFG3     Y        Out     0.182     6.692       -         
SLAVE_SELECT_WDCH_M19                                              Net      -        -       1.063     -           78        
AXI_IF_0.axi_fsm_current_state_RNI13MU2[0]                         CFG4     D        In      -         7.754       -         
AXI_IF_0.axi_fsm_current_state_RNI13MU2[0]                         CFG4     Y        Out     0.408     8.163       -         
wburst_cnte                                                        Net      -        -       0.859     -           9         
AXI_IF_0.wburst_cnt[6]                                             SLE      EN       In      -         9.021       -         
=============================================================================================================================
Total path delay (propagation time + setup) of 9.315 is 2.893(31.1%) logic and 6.422(68.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                        Starting                                                                                     Arrival          
Instance                                Reference                                                  Type     Pin     Net              Time        Slack
                                        Clock                                                                                                         
------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.count_ddr[3]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[3]     0.094       0.001
MDDR_TA_0.CORERESETP_0.count_ddr[7]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[7]     0.094       0.015
MDDR_TA_0.CORERESETP_0.count_ddr[1]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[1]     0.076       0.053
MDDR_TA_0.CORERESETP_0.count_ddr[0]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[0]     0.094       0.199
MDDR_TA_0.CORERESETP_0.count_ddr[2]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[2]     0.094       0.229
MDDR_TA_0.CORERESETP_0.count_ddr[6]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[6]     0.094       0.243
MDDR_TA_0.CORERESETP_0.count_ddr[5]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[5]     0.094       0.280
MDDR_TA_0.CORERESETP_0.count_ddr[4]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[4]     0.094       0.294
MDDR_TA_0.CORERESETP_0.count_ddr[8]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[8]     0.094       0.307
MDDR_TA_0.CORERESETP_0.count_ddr[9]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[9]     0.094       0.345
======================================================================================================================================================


Ending Points with Worst Slack
******************************

                                         Starting                                                                                        Required          
Instance                                 Reference                                                  Type     Pin     Net                 Time         Slack
                                         Clock                                                                                                             
-----------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.count_ddr[13]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[13]     2.278        0.001
MDDR_TA_0.CORERESETP_0.count_ddr[12]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[12]     2.278        0.015
MDDR_TA_0.CORERESETP_0.count_ddr[11]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[11]     2.278        0.030
MDDR_TA_0.CORERESETP_0.count_ddr[10]     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[10]     2.278        0.044
MDDR_TA_0.CORERESETP_0.ddr_ready         MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      EN      ddr_ready4          2.207        0.053
MDDR_TA_0.CORERESETP_0.count_ddr[9]      MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[9]      2.278        0.058
MDDR_TA_0.CORERESETP_0.count_ddr[8]      MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[8]      2.278        0.199
MDDR_TA_0.CORERESETP_0.count_ddr[7]      MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[7]      2.278        0.213
MDDR_TA_0.CORERESETP_0.count_ddr[6]      MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[6]      2.278        0.227
MDDR_TA_0.CORERESETP_0.count_ddr[5]      MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[5]      2.278        0.241
===========================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      2.277
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.001

    Number of logic level(s):                7
    Starting point:                          MDDR_TA_0.CORERESETP_0.count_ddr[3] / Q
    Ending point:                            MDDR_TA_0.CORERESETP_0.count_ddr[13] / D
    The start point is clocked by            MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK

Instance / Net                                          Pin      Pin               Arrival     No. of    
Name                                           Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.count_ddr[3]            SLE      Q        Out     0.094     0.094       -         
count_ddr[3]                                   Net      -        -       0.637     -           3         
MDDR_TA_0.CORERESETP_0.count_ddr_cry_1[12]     ARI1     D        In      -         0.732       -         
MDDR_TA_0.CORERESETP_0.count_ddr_cry_1[12]     ARI1     FCO      Out     0.439     1.171       -         
count_ddr_cry_1_FCO[12]                        Net      -        -       0.000     -           1         
MDDR_TA_0.CORERESETP_0.count_ddr_cry_3[12]     ARI1     FCI      In      -         1.171       -         
MDDR_TA_0.CORERESETP_0.count_ddr_cry_3[12]     ARI1     FCO      Out     0.014     1.185       -         
count_ddr_cry_3_FCO[12]                        Net      -        -       0.000     -           1         
MDDR_TA_0.CORERESETP_0.count_ddr_cry[9]        ARI1     FCI      In      -         1.185       -         
MDDR_TA_0.CORERESETP_0.count_ddr_cry[9]        ARI1     FCO      Out     0.014     1.199       -         
count_ddr_cry[9]                               Net      -        -       0.000     -           1         
MDDR_TA_0.CORERESETP_0.count_ddr_cry[10]       ARI1     FCI      In      -         1.199       -         
MDDR_TA_0.CORERESETP_0.count_ddr_cry[10]       ARI1     FCO      Out     0.014     1.214       -         
count_ddr_cry[10]                              Net      -        -       0.000     -           1         
MDDR_TA_0.CORERESETP_0.count_ddr_cry[11]       ARI1     FCI      In      -         1.214       -         
MDDR_TA_0.CORERESETP_0.count_ddr_cry[11]       ARI1     FCO      Out     0.014     1.228       -         
count_ddr_cry[11]                              Net      -        -       0.000     -           1         
MDDR_TA_0.CORERESETP_0.count_ddr_cry[12]       ARI1     FCI      In      -         1.228       -         
MDDR_TA_0.CORERESETP_0.count_ddr_cry[12]       ARI1     FCO      Out     0.014     1.242       -         
count_ddr_cry[12]                              Net      -        -       0.000     -           1         
MDDR_TA_0.CORERESETP_0.count_ddr_s[13]         ARI1     FCI      In      -         1.242       -         
MDDR_TA_0.CORERESETP_0.count_ddr_s[13]         ARI1     S        Out     0.063     1.305       -         
count_ddr_s[13]                                Net      -        -       0.971     -           1         
MDDR_TA_0.CORERESETP_0.count_ddr[13]           SLE      D        In      -         2.277       -         
=========================================================================================================
Total path delay (propagation time + setup) of 2.499 is 0.890(35.6%) logic and 1.609(64.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                            Starting                                                                                                                            Arrival           
Instance                                    Reference                                        Type        Pin                        Net                                         Time        Slack 
                                            Clock                                                                                                                                                 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[7]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[7]      4.783       -3.682
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[5]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[5]      4.605       -3.579
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[9]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[9]      4.628       -3.526
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[1]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[1]      4.575       -3.474
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[8]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[8]      4.574       -3.473
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[12]     CORECONFIGP_0_MDDR_APBmslave_PRDATA[12]     4.569       -3.467
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[6]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[6]      4.516       -3.414
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[3]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[3]      4.448       -3.346
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[0]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[0]      4.350       -3.324
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     MSS_010     MDDR_FABRIC_PRDATA[2]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[2]      4.396       -3.295
==================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                   Starting                                                                         Required           
Instance                                           Reference                                        Type     Pin     Net            Time         Slack 
                                                   Clock                                                                                               
-------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[7]      2.278        -3.682
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[5]      2.278        -3.579
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[9]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[9]      2.278        -3.526
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[1]      2.278        -3.474
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[8]      2.278        -3.473
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[12]     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[12]     2.278        -3.467
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[6]      2.278        -3.414
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[3]      2.278        -3.346
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[0]      2.278        -3.324
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[2]      2.278        -3.295
=======================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      5.960
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.682

    Number of logic level(s):                1
    Starting point:                          MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / MDDR_FABRIC_PRDATA[7]
    Ending point:                            MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] / D
    The start point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB
    The end   point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK

Instance / Net                                                    Pin                       Pin               Arrival     No. of    
Name                                                  Type        Name                      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST               MSS_010     MDDR_FABRIC_PRDATA[7]     Out     4.783     4.783       -         
CORECONFIGP_0_MDDR_APBmslave_PRDATA[7]                Net         -                         -       0.971     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[7]     CFG2        A                         In      -         5.754       -         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[7]     CFG2        Y                         Out     0.067     5.822       -         
prdata[7]                                             Net         -                         -       0.138     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7]         SLE         D                         In      -         5.960       -         
====================================================================================================================================
Total path delay (propagation time + setup) of 6.181 is 5.072(82.1%) logic and 1.109(17.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      5.857
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.579

    Number of logic level(s):                1
    Starting point:                          MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / MDDR_FABRIC_PRDATA[5]
    Ending point:                            MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] / D
    The start point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB
    The end   point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK

Instance / Net                                                Pin                       Pin               Arrival     No. of    
Name                                              Type        Name                      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST           MSS_010     MDDR_FABRIC_PRDATA[5]     Out     4.605     4.605       -         
CORECONFIGP_0_MDDR_APBmslave_PRDATA[5]            Net         -                         -       0.971     -           1         
MDDR_TA_0.CORECONFIGP_0.prdata_m_0[5]             CFG4        B                         In      -         5.576       -         
MDDR_TA_0.CORECONFIGP_0.prdata_m_0[5]             CFG4        Y                         Out     0.143     5.720       -         
prdata[5]                                         Net         -                         -       0.138     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5]     SLE         D                         In      -         5.857       -         
================================================================================================================================
Total path delay (propagation time + setup) of 6.079 is 4.970(81.8%) logic and 1.109(18.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      5.804
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.526

    Number of logic level(s):                1
    Starting point:                          MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / MDDR_FABRIC_PRDATA[9]
    Ending point:                            MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[9] / D
    The start point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB
    The end   point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK

Instance / Net                                                    Pin                       Pin               Arrival     No. of    
Name                                                  Type        Name                      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST               MSS_010     MDDR_FABRIC_PRDATA[9]     Out     4.628     4.628       -         
CORECONFIGP_0_MDDR_APBmslave_PRDATA[9]                Net         -                         -       0.971     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[9]     CFG2        A                         In      -         5.599       -         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[9]     CFG2        Y                         Out     0.067     5.667       -         
prdata[9]                                             Net         -                         -       0.138     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[9]         SLE         D                         In      -         5.804       -         
====================================================================================================================================
Total path delay (propagation time + setup) of 6.026 is 4.917(81.6%) logic and 1.109(18.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      5.752
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.474

    Number of logic level(s):                1
    Starting point:                          MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / MDDR_FABRIC_PRDATA[1]
    Ending point:                            MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] / D
    The start point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB
    The end   point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK

Instance / Net                                                    Pin                       Pin               Arrival     No. of    
Name                                                  Type        Name                      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST               MSS_010     MDDR_FABRIC_PRDATA[1]     Out     4.575     4.575       -         
CORECONFIGP_0_MDDR_APBmslave_PRDATA[1]                Net         -                         -       0.971     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[1]     CFG2        A                         In      -         5.546       -         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[1]     CFG2        Y                         Out     0.067     5.614       -         
prdata[1]                                             Net         -                         -       0.138     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1]         SLE         D                         In      -         5.752       -         
====================================================================================================================================
Total path delay (propagation time + setup) of 5.973 is 4.864(81.4%) logic and 1.109(18.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      2.500
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.278

    - Propagation time:                      5.750
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -3.472

    Number of logic level(s):                1
    Starting point:                          MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / MDDR_FABRIC_PRDATA[8]
    Ending point:                            MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] / D
    The start point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB
    The end   point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK

Instance / Net                                                    Pin                       Pin               Arrival     No. of    
Name                                                  Type        Name                      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST               MSS_010     MDDR_FABRIC_PRDATA[8]     Out     4.574     4.574       -         
CORECONFIGP_0_MDDR_APBmslave_PRDATA[8]                Net         -                         -       0.971     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[8]     CFG2        A                         In      -         5.545       -         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA_RNO[8]     CFG2        Y                         Out     0.067     5.613       -         
prdata[8]                                             Net         -                         -       0.138     -           1         
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8]         SLE         D                         In      -         5.750       -         
====================================================================================================================================
Total path delay (propagation time + setup) of 5.973 is 4.863(81.4%) logic and 1.109(18.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                     Starting                                                        Arrival           
Instance                             Reference     Type        Pin            Net                    Time        Slack 
                                     Clock                                                                             
-----------------------------------------------------------------------------------------------------------------------
AXI_IF_0.Rdata_mem_Rdata_mem_0_1     System        RAM1K18     B_DOUT[12]     Rdata_mem_reto[44]     0.000       -0.912
AXI_IF_0.Rdata_mem_Rdata_mem_0_1     System        RAM1K18     B_DOUT[12]     Rdata_mem_reto[44]     0.000       -0.912
AXI_IF_0.Rdata_mem_Rdata_mem_0_1     System        RAM1K18     B_DOUT[8]      Rdata_mem_reto[40]     0.000       -0.805
AXI_IF_0.Rdata_mem_Rdata_mem_0_1     System        RAM1K18     B_DOUT[8]      Rdata_mem_reto[40]     0.000       -0.805
AXI_IF_0.Rdata_mem_Rdata_mem_0_1     System        RAM1K18     A_DOUT[13]     Rdata_mem_reto[63]     0.000       -0.792
AXI_IF_0.Rdata_mem_Rdata_mem_0_1     System        RAM1K18     A_DOUT[13]     Rdata_mem_reto[63]     0.000       -0.792
AXI_IF_0.Rdata_mem_Rdata_mem_0_1     System        RAM1K18     B_DOUT[16]     Rdata_mem_reto[48]     0.000       -0.783
AXI_IF_0.Rdata_mem_Rdata_mem_0_1     System        RAM1K18     B_DOUT[16]     Rdata_mem_reto[48]     0.000       -0.783
AXI_IF_0.Rdata_mem_Rdata_mem_0_0     System        RAM1K18     A_DOUT[9]      Rdata_mem_reto[27]     0.000       -0.780
AXI_IF_0.Rdata_mem_Rdata_mem_0_0     System        RAM1K18     A_DOUT[9]      Rdata_mem_reto[27]     0.000       -0.780
=======================================================================================================================


Ending Points with Worst Slack
******************************

                                            Starting                                                                              Required           
Instance                                    Reference     Type        Pin                      Net                                Time         Slack 
                                            Clock                                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[44]     COREAXI_0_AXImslave0_WDATA[44]     1.444        -0.912
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[40]     COREAXI_0_AXImslave0_WDATA[40]     1.551        -0.805
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[63]     COREAXI_0_AXImslave0_WDATA[63]     1.564        -0.792
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[48]     COREAXI_0_AXImslave0_WDATA[48]     1.573        -0.783
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[27]     COREAXI_0_AXImslave0_WDATA[27]     1.576        -0.780
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[56]     COREAXI_0_AXImslave0_WDATA[56]     1.587        -0.769
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[60]     COREAXI_0_AXImslave0_WDATA[60]     1.593        -0.763
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[3]      COREAXI_0_AXImslave0_WDATA[3]      1.608        -0.748
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[1]      COREAXI_0_AXImslave0_WDATA[1]      1.610        -0.746
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST     System        MSS_010     F_WDATA_HWDATA01[47]     COREAXI_0_AXImslave0_WDATA[47]     1.612        -0.744
=====================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      2.500
    - Setup time:                            1.056
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.444

    - Propagation time:                      2.356
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.912

    Number of logic level(s):                1
    Starting point:                          AXI_IF_0.Rdata_mem_Rdata_mem_0_1 / B_DOUT[12]
    Ending point:                            MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / F_WDATA_HWDATA01[44]
    The start point is clocked by            System [rising]
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                       Pin                      Pin               Arrival     No. of    
Name                                                                     Type        Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
AXI_IF_0.Rdata_mem_Rdata_mem_0_1                                         RAM1K18     B_DOUT[12]               Out     0.000     0.000       -         
Rdata_mem_reto[44]                                                       Net         -                        -       0.977     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNIDA0M     CFG4        D                        In      -         0.977       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNIDA0M     CFG4        Y                        Out     0.408     1.385       -         
COREAXI_0_AXImslave0_WDATA[44]                                           Net         -                        -       0.971     -           1         
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST                                  MSS_010     F_WDATA_HWDATA01[44]     In      -         2.356       -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 3.412 is 1.464(42.9%) logic and 1.948(57.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      2.500
    - Setup time:                            1.056
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.444

    - Propagation time:                      2.356
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.912

    Number of logic level(s):                1
    Starting point:                          AXI_IF_0.Rdata_mem_Rdata_mem_0_1 / B_DOUT[12]
    Ending point:                            MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / F_WDATA_HWDATA01[44]
    The start point is clocked by            System [rising]
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                       Pin                      Pin               Arrival     No. of    
Name                                                                     Type        Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
AXI_IF_0.Rdata_mem_Rdata_mem_0_1                                         RAM1K18     B_DOUT[12]               Out     0.000     0.000       -         
Rdata_mem_reto[44]                                                       Net         -                        -       0.977     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNIDA0M     CFG4        D                        In      -         0.977       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNIDA0M     CFG4        Y                        Out     0.408     1.385       -         
COREAXI_0_AXImslave0_WDATA[44]                                           Net         -                        -       0.971     -           1         
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST                                  MSS_010     F_WDATA_HWDATA01[44]     In      -         2.356       -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 3.412 is 1.464(42.9%) logic and 1.948(57.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      2.500
    - Setup time:                            0.949
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.551

    - Propagation time:                      2.356
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.805

    Number of logic level(s):                1
    Starting point:                          AXI_IF_0.Rdata_mem_Rdata_mem_0_1 / B_DOUT[8]
    Ending point:                            MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / F_WDATA_HWDATA01[40]
    The start point is clocked by            System [rising]
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                       Pin                      Pin               Arrival     No. of    
Name                                                                     Type        Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
AXI_IF_0.Rdata_mem_Rdata_mem_0_1                                         RAM1K18     B_DOUT[8]                Out     0.000     0.000       -         
Rdata_mem_reto[40]                                                       Net         -                        -       0.977     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNI960M     CFG4        D                        In      -         0.977       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNI960M     CFG4        Y                        Out     0.408     1.385       -         
COREAXI_0_AXImslave0_WDATA[40]                                           Net         -                        -       0.971     -           1         
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST                                  MSS_010     F_WDATA_HWDATA01[40]     In      -         2.356       -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 3.305 is 1.357(41.1%) logic and 1.948(58.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      2.500
    - Setup time:                            0.949
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.551

    - Propagation time:                      2.356
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.805

    Number of logic level(s):                1
    Starting point:                          AXI_IF_0.Rdata_mem_Rdata_mem_0_1 / B_DOUT[8]
    Ending point:                            MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / F_WDATA_HWDATA01[40]
    The start point is clocked by            System [rising]
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                       Pin                      Pin               Arrival     No. of    
Name                                                                     Type        Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
AXI_IF_0.Rdata_mem_Rdata_mem_0_1                                         RAM1K18     B_DOUT[8]                Out     0.000     0.000       -         
Rdata_mem_reto[40]                                                       Net         -                        -       0.977     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNI960M     CFG4        D                        In      -         0.977       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNI960M     CFG4        Y                        Out     0.408     1.385       -         
COREAXI_0_AXImslave0_WDATA[40]                                           Net         -                        -       0.971     -           1         
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST                                  MSS_010     F_WDATA_HWDATA01[40]     In      -         2.356       -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 3.305 is 1.357(41.1%) logic and 1.948(58.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      2.500
    - Setup time:                            0.936
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.564

    - Propagation time:                      2.356
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.792

    Number of logic level(s):                1
    Starting point:                          AXI_IF_0.Rdata_mem_Rdata_mem_0_1 / A_DOUT[13]
    Ending point:                            MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST / F_WDATA_HWDATA01[63]
    The start point is clocked by            System [rising]
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                       Pin                      Pin               Arrival     No. of    
Name                                                                     Type        Name                     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
AXI_IF_0.Rdata_mem_Rdata_mem_0_1                                         RAM1K18     A_DOUT[13]               Out     0.000     0.000       -         
Rdata_mem_reto[63]                                                       Net         -                        -       0.977     -           2         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNIED2M     CFG4        D                        In      -         0.977       -         
MDDR_TA_0.COREAXI_0.u_axi_interconnect.SLAVE_SELECT_WDCH_M19_RNIED2M     CFG4        Y                        Out     0.408     1.385       -         
COREAXI_0_AXImslave0_WDATA[63]                                           Net         -                        -       0.971     -           1         
MDDR_TA_0.MDDR_TA_HPMS_0.MSS_ADLIB_INST                                  MSS_010     F_WDATA_HWDATA01[63]     In      -         2.356       -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 3.292 is 1.344(40.8%) logic and 1.948(59.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for MDDR_TA_top 

Mapping to part: m2gl010tfbga484-1
Cell usage:
CCC             1 use
CLKINT          8 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
RCOSC_25_50MHZ_FAB  1 use
SYSRESET        1 use
CFG1           27 uses
CFG2           367 uses
CFG3           271 uses
CFG4           642 uses

Carry primitives used for arithmetic functions:
ARI1           317 uses


Sequential Cells: 
SLE            956 uses

DSP Blocks:    0

I/O ports: 53
I/O primitives: 51
BIBUF          20 uses
INBUF          2 uses
OUTBUF         28 uses
OUTBUF_DIFF    1 use


Global Clock Buffers: 8


RAM/ROM usage summary
Block Rams (RAM1K18) : 3

Total LUTs:    1624

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:14s; Memory used current: 56MB peak: 190MB)

Process took 0h:00m:17s realtime, 0h:00m:14s cputime
# Thu Mar 27 12:20:34 2014

###########################################################]
