-------------------------------------
 External Hold Repair Report 
-------------------------------------
 Iteration 1  
 Total I/O input ports improved: 0       
-------------------------------------



-------------------------
 Min-delay Repair Report 
-------------------------
 Iteration 1  
 Total paths found:    1       
 Total paths improved: 1       
-------------------------

Path 1
------------------------
From: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB
  To: MDDR_TA_0/CORECONFIGP_0/state[0]:D
------------------------
Path min-delay slack:      -117 ps
------------------------
  On sink pin: MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3:A
-------------------------------------
  Pin max-delay slack:    47781 ps
  Min-delay inserted:       471 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3_CFG1C_TEST




-------------------------------------
 External Hold Repair Report 
-------------------------------------
 Iteration 2  
 Total I/O input ports improved: 0       
-------------------------------------



-------------------------
 Min-delay Repair Report 
-------------------------
 Iteration 2  
 Total paths found:    1       
 Total paths improved: 1       
-------------------------

Path 1
------------------------
From: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB
  To: MDDR_TA_0/CORECONFIGP_0/state[0]:D
------------------------
Path min-delay slack:       -72 ps
------------------------
  On sink pin: MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3:B
-------------------------------------
  Pin max-delay slack:    47749 ps
  Min-delay inserted:       472 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3_CFG1C_TEST0



Note:
    [1]: A net cannot be modified for repair if:
         - it is hardwired, preserved, or global;
         - the sink pin is a clock pin;
         - the sink pin has negative max-delay slack allowance;
         - the sink and driving pins are placed in the same cluster.

    [2]: A location is not feasible for inserting a delay buffer if the estimated minimum delay to be inserted might exceed the max-delay slack allowance of the sink pin.



