E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\m_generic.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1  -part M2GL010T  -package FBGA484  -grade -1   -maxfan 10000 -clock_globalthreshold 2 -async_globalthreshold 12 -globalthreshold 5000   -opcond COMWC  -report_path 0  -RWCheckOnRam 0    -summaryfile D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synlog\report\MDDR_TA_top_fpga_mapper.xml -top_level_module  MDDR_TA_top  -flow mapping  -mp 1 -prjfile  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\scratchproject.prs  -implementation synthesis_1 -licensetype  synplifypro  -oedif  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.edf  -freq 400.000  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_prem.srd  -sap  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap  -otap  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.tap  -omap  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.map  -devicelib  E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v  -sap  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap  -ologparam  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\syntmp\MDDR_TA_top.plg  -osyn  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.srm  -prjdir  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\  -prjname  MDDR_TA_top_syn  -log  D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synlog\MDDR_TA_top_fpga_mapper.srr 
rc:1 success:1
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\scratchproject.prs|o|1395903003|5735
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.edf|o|0|0
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synwork\MDDR_TA_top_prem.srd|i|1395903016|535783
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap|o|1395903016|64440
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.tap|o|0|0
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.map|o|1395903034|28
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v|i|1389673372|16295
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap|o|1395903016|64440
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\syntmp\MDDR_TA_top.plg|o|1395903034|4236
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.srm|o|1395903032|364686
D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synlog\MDDR_TA_top_fpga_mapper.srr|o|1395903034|957255
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\m_generic.exe|i|1390193752|31452672
E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin\m_generic.exe|i|1390191066|21921280
