// ****************************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation.  All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: axi_interconnect - Bridge interconnect matrix 
//
// Revision Information:
// Date            Description
// ----            -----------------------------------------
// 02Feb11         Inital. Ports and Parameters declaration
//
// SVN Revision Information:
// SVN $Revision: 11146 $
// SVN $Date: 2009-11-21 11:44:53 -0800 (Sat, 21 Nov 2009) $
//
// Resolved SARs
// SAR      Date     Who   Description
//
// Notes:
// 1. 
//
// ****************************************************************************/
`timescale 1ns/1ps

module axi_interconnect (
    // Global signals
    ACLK,
    ARESETN,

    // MASTER 
    // AXI MASTER write address channel signals
    AWID_MI,
    AWADDR_MI,
    AWLEN_MI,
    AWSIZE_MI,
    AWBURST_MI,
    AWLOCK_MI,
    AWCACHE_MI,
    AWPROT_MI,
    AWVALID_MI,
    AWREADY_IM,
    // AXI MASTER write data channel signals
    WID_MI,
    WDATA_MI,
    WSTRB_MI,
    WLAST_MI,
    WVALID_MI,
    WREADY_IM,
    // AXI MASTER write response channel signals
    BID_IM,
    BRESP_IM,
    BVALID_IM,
    BREADY_MI,
    // AXI MASTER read address channel signals
    ARID_MI,
    ARADDR_MI,
    ARLEN_MI,
    ARSIZE_MI,
    ARBURST_MI,
    ARLOCK_MI,
    ARCACHE_MI,
    ARPROT_MI,
    ARVALID_MI,
    ARREADY_IM,
    // AXI MASTER read response channel signals
    RID_IM,
    RDATA_IM,
    RRESP_IM,
    RLAST_IM,
    RVALID_IM,
    RREADY_MI,

    // SLAVE 0
    // AXI SLAVE 0 write address channel signals
    AWID_IS0,
    AWADDR_IS0,
    AWLEN_IS0,
    AWSIZE_IS0,
    AWBURST_IS0,
    AWLOCK_IS0,
    AWCACHE_IS0,
    AWPROT_IS0,
    AWVALID_IS0,
    AWREADY_S0_I,
    // AXI SLAVE 0 write data channel signals
    WID_IS0,
    WDATA_IS0,
    WSTRB_IS0,
    WLAST_IS0,
    WVALID_IS0,
    WREADY_S0_I,
    // AXI SLAVE 0 write response channel signals
    BID_S0_I,
    BRESP_S0_I,
    BVALID_S0_I,
    BREADY_IS0,
    // AXI SLAVE 0 read address channel signals
    ARID_IS0,
    ARADDR_IS0,
    ARLEN_IS0,
    ARSIZE_IS0,
    ARBURST_IS0,
    ARLOCK_IS0,
    ARCACHE_IS0,
    ARPROT_IS0,
    ARVALID_IS0,
    ARREADY_S0_I,
    // AXI SLAVE 0 read response channel signals
    RID_S0_I,
    RDATA_S0_I,
    RRESP_S0_I,
    RLAST_S0_I,
    RVALID_S0_I,
    RREADY_IS0,

    // SLAVE 1
    // AXI SLAVE 1 write address channel signals
    AWID_IS1,
    AWADDR_IS1,
    AWLEN_IS1,
    AWSIZE_IS1,
    AWBURST_IS1,
    AWLOCK_IS1,
    AWCACHE_IS1,
    AWPROT_IS1,
    AWVALID_IS1,
    AWREADY_S1_I,
    // AXI SLAVE 1 write data channel signals
    WID_IS1,
    WDATA_IS1,
    WSTRB_IS1,
    WLAST_IS1,
    WVALID_IS1,
    WREADY_S1_I,
    // AXI SLAVE 1 write response channel signals
    BID_S1_I,
    BRESP_S1_I,
    BVALID_S1_I,
    BREADY_IS1,
    // AXI SLAVE 1 read address channel signals
    ARID_IS1,
    ARADDR_IS1,
    ARLEN_IS1,
    ARSIZE_IS1,
    ARBURST_IS1,
    ARLOCK_IS1,
    ARCACHE_IS1,
    ARPROT_IS1,
    ARVALID_IS1,
    ARREADY_S1_I,
    // AXI SLAVE 1 read response channel signals
    RID_S1_I,
    RDATA_S1_I,
    RRESP_S1_I,
    RLAST_S1_I,
    RVALID_S1_I,
    RREADY_IS1,

    // SLAVE 2
    // AXI SLAVE 2 write address channel signals
    AWID_IS2,
    AWADDR_IS2,
    AWLEN_IS2,
    AWSIZE_IS2,
    AWBURST_IS2,
    AWLOCK_IS2,
    AWCACHE_IS2,
    AWPROT_IS2,
    AWVALID_IS2,
    AWREADY_S2_I,
    // AXI SLAVE 2 write data channel signals
    WID_IS2,
    WDATA_IS2,
    WSTRB_IS2,
    WLAST_IS2,
    WVALID_IS2,
    WREADY_S2_I,
    // AXI SLAVE 2 write response channel signals
    BID_S2_I,
    BRESP_S2_I,
    BVALID_S2_I,
    BREADY_IS2,
    // AXI SLAVE 2 read address channel signals
    ARID_IS2,
    ARADDR_IS2,
    ARLEN_IS2,
    ARSIZE_IS2,
    ARBURST_IS2,
    ARLOCK_IS2,
    ARCACHE_IS2,
    ARPROT_IS2,
    ARVALID_IS2,
    ARREADY_S2_I,
    // AXI SLAVE 2 read response channel signals
    RID_S2_I,
    RDATA_S2_I,
    RRESP_S2_I,
    RLAST_S2_I,
    RVALID_S2_I,
    RREADY_IS2,

    // SLAVE 3
    // AXI SLAVE 3 write address channel signals
    AWID_IS3,
    AWADDR_IS3,
    AWLEN_IS3,
    AWSIZE_IS3,
    AWBURST_IS3,
    AWLOCK_IS3,
    AWCACHE_IS3,
    AWPROT_IS3,
    AWVALID_IS3,
    AWREADY_S3_I,
    // AXI SLAVE 3 write data channel signals
    WID_IS3,
    WDATA_IS3,
    WSTRB_IS3,
    WLAST_IS3,
    WVALID_IS3,
    WREADY_S3_I,
    // AXI SLAVE 3 write response channel signals
    BID_S3_I,
    BRESP_S3_I,
    BVALID_S3_I,
    BREADY_IS3,
    // AXI SLAVE 3 read address channel signals
    ARID_IS3,
    ARADDR_IS3,
    ARLEN_IS3,
    ARSIZE_IS3,
    ARBURST_IS3,
    ARLOCK_IS3,
    ARCACHE_IS3,
    ARPROT_IS3,
    ARVALID_IS3,
    ARREADY_S3_I,
    // AXI SLAVE 3 read response channel signals
    RID_S3_I,
    RDATA_S3_I,
    RRESP_S3_I,
    RLAST_S3_I,
    RVALID_S3_I,
    RREADY_IS3,

    // SLAVE 4
    // AXI SLAVE 4 write address channel signals
    AWID_IS4,
    AWADDR_IS4,
    AWLEN_IS4,
    AWSIZE_IS4,
    AWBURST_IS4,
    AWLOCK_IS4,
    AWCACHE_IS4,
    AWPROT_IS4,
    AWVALID_IS4,
    AWREADY_S4_I,
    // AXI SLAVE 4 write data channel signals
    WID_IS4,
    WDATA_IS4,
    WSTRB_IS4,
    WLAST_IS4,
    WVALID_IS4,
    WREADY_S4_I,
    // AXI SLAVE 4 write response channel signals
    BID_S4_I,
    BRESP_S4_I,
    BVALID_S4_I,
    BREADY_IS4,
    // AXI SLAVE 4 read address channel signals
    ARID_IS4,
    ARADDR_IS4,
    ARLEN_IS4,
    ARSIZE_IS4,
    ARBURST_IS4,
    ARLOCK_IS4,
    ARCACHE_IS4,
    ARPROT_IS4,
    ARVALID_IS4,
    ARREADY_S4_I,
    // AXI SLAVE 4 read response channel signals
    RID_S4_I,
    RDATA_S4_I,
    RRESP_S4_I,
    RLAST_S4_I,
    RVALID_S4_I,
    RREADY_IS4,

    // SLAVE 5
    // AXI SLAVE 5 write address channel signals
    AWID_IS5,
    AWADDR_IS5,
    AWLEN_IS5,
    AWSIZE_IS5,
    AWBURST_IS5,
    AWLOCK_IS5,
    AWCACHE_IS5,
    AWPROT_IS5,
    AWVALID_IS5,
    AWREADY_S5_I,
    // AXI SLAVE 5 write data channel signals
    WID_IS5,
    WDATA_IS5,
    WSTRB_IS5,
    WLAST_IS5,
    WVALID_IS5,
    WREADY_S5_I,
    // AXI SLAVE 5 write response channel signals
    BID_S5_I,
    BRESP_S5_I,
    BVALID_S5_I,
    BREADY_IS5,
    // AXI SLAVE 5 read address channel signals
    ARID_IS5,
    ARADDR_IS5,
    ARLEN_IS5,
    ARSIZE_IS5,
    ARBURST_IS5,
    ARLOCK_IS5,
    ARCACHE_IS5,
    ARPROT_IS5,
    ARVALID_IS5,
    ARREADY_S5_I,
    // AXI SLAVE 5 read response channel signals
    RID_S5_I,
    RDATA_S5_I,
    RRESP_S5_I,
    RLAST_S5_I,
    RVALID_S5_I,
    RREADY_IS5,

    // SLAVE 6
    // AXI SLAVE 6 write address channel signals
    AWID_IS6,
    AWADDR_IS6,
    AWLEN_IS6,
    AWSIZE_IS6,
    AWBURST_IS6,
    AWLOCK_IS6,
    AWCACHE_IS6,
    AWPROT_IS6,
    AWVALID_IS6,
    AWREADY_S6_I,
    // AXI SLAVE 6 write data channel signals
    WID_IS6,
    WDATA_IS6,
    WSTRB_IS6,
    WLAST_IS6,
    WVALID_IS6,
    WREADY_S6_I,
    // AXI SLAVE 6 write response channel signals
    BID_S6_I,
    BRESP_S6_I,
    BVALID_S6_I,
    BREADY_IS6,
    // AXI SLAVE 6 read address channel signals
    ARID_IS6,
    ARADDR_IS6,
    ARLEN_IS6,
    ARSIZE_IS6,
    ARBURST_IS6,
    ARLOCK_IS6,
    ARCACHE_IS6,
    ARPROT_IS6,
    ARVALID_IS6,
    ARREADY_S6_I,
    // AXI SLAVE 6 read response channel signals
    RID_S6_I,
    RDATA_S6_I,
    RRESP_S6_I,
    RLAST_S6_I,
    RVALID_S6_I,
    RREADY_IS6,

    // SLAVE 7
    // AXI SLAVE 7 write address channel signals
    AWID_IS7,
    AWADDR_IS7,
    AWLEN_IS7,
    AWSIZE_IS7,
    AWBURST_IS7,
    AWLOCK_IS7,
    AWCACHE_IS7,
    AWPROT_IS7,
    AWVALID_IS7,
    AWREADY_S7_I,
    // AXI SLAVE 7 write data channel signals
    WID_IS7,
    WDATA_IS7,
    WSTRB_IS7,
    WLAST_IS7,
    WVALID_IS7,
    WREADY_S7_I,
    // AXI SLAVE 7 write response channel signals
    BID_S7_I,
    BRESP_S7_I,
    BVALID_S7_I,
    BREADY_IS7,
    // AXI SLAVE 7 read address channel signals
    ARID_IS7,
    ARADDR_IS7,
    ARLEN_IS7,
    ARSIZE_IS7,
    ARBURST_IS7,
    ARLOCK_IS7,
    ARCACHE_IS7,
    ARPROT_IS7,
    ARVALID_IS7,
    ARREADY_S7_I,
    // AXI SLAVE 7 read response channel signals
    RID_S7_I,
    RDATA_S7_I,
    RRESP_S7_I,
    RLAST_S7_I,
    RVALID_S7_I,
    RREADY_IS7,

    // SLAVE 8
    // AXI SLAVE 8 write address channel signals
    AWID_IS8,
    AWADDR_IS8,
    AWLEN_IS8,
    AWSIZE_IS8,
    AWBURST_IS8,
    AWLOCK_IS8,
    AWCACHE_IS8,
    AWPROT_IS8,
    AWVALID_IS8,
    AWREADY_S8_I,
    // AXI SLAVE 8 write data channel signals
    WID_IS8,
    WDATA_IS8,
    WSTRB_IS8,
    WLAST_IS8,
    WVALID_IS8,
    WREADY_S8_I,
    // AXI SLAVE 8 write response channel signals
    BID_S8_I,
    BRESP_S8_I,
    BVALID_S8_I,
    BREADY_IS8,
    // AXI SLAVE 8 read address channel signals
    ARID_IS8,
    ARADDR_IS8,
    ARLEN_IS8,
    ARSIZE_IS8,
    ARBURST_IS8,
    ARLOCK_IS8,
    ARCACHE_IS8,
    ARPROT_IS8,
    ARVALID_IS8,
    ARREADY_S8_I,
    // AXI SLAVE 8 read response channel signals
    RID_S8_I,
    RDATA_S8_I,
    RRESP_S8_I,
    RLAST_S8_I,
    RVALID_S8_I,
    RREADY_IS8,

    // SLAVE 9
    // AXI SLAVE 9 write address channel signals
    AWID_IS9,
    AWADDR_IS9,
    AWLEN_IS9,
    AWSIZE_IS9,
    AWBURST_IS9,
    AWLOCK_IS9,
    AWCACHE_IS9,
    AWPROT_IS9,
    AWVALID_IS9,
    AWREADY_S9_I,
    // AXI SLAVE 9 write data channel signals
    WID_IS9,
    WDATA_IS9,
    WSTRB_IS9,
    WLAST_IS9,
    WVALID_IS9,
    WREADY_S9_I,
    // AXI SLAVE 9 write response channel signals
    BID_S9_I,
    BRESP_S9_I,
    BVALID_S9_I,
    BREADY_IS9,
    // AXI SLAVE 9 read address channel signals
    ARID_IS9,
    ARADDR_IS9,
    ARLEN_IS9,
    ARSIZE_IS9,
    ARBURST_IS9,
    ARLOCK_IS9,
    ARCACHE_IS9,
    ARPROT_IS9,
    ARVALID_IS9,
    ARREADY_S9_I,
    // AXI SLAVE 9 read response channel signals
    RID_S9_I,
    RDATA_S9_I,
    RRESP_S9_I,
    RLAST_S9_I,
    RVALID_S9_I,
    RREADY_IS9,

    // SLAVE 10
    // AXI SLAVE 10 write address channel signals
    AWID_IS10,
    AWADDR_IS10,
    AWLEN_IS10,
    AWSIZE_IS10,
    AWBURST_IS10,
    AWLOCK_IS10,
    AWCACHE_IS10,
    AWPROT_IS10,
    AWVALID_IS10,
    AWREADY_S10_I,
    // AXI SLAVE 10 write data channel signals
    WID_IS10,
    WDATA_IS10,
    WSTRB_IS10,
    WLAST_IS10,
    WVALID_IS10,
    WREADY_S10_I,
    // AXI SLAVE 10 write response channel signals
    BID_S10_I,
    BRESP_S10_I,
    BVALID_S10_I,
    BREADY_IS10,
    // AXI SLAVE 10 read address channel signals
    ARID_IS10,
    ARADDR_IS10,
    ARLEN_IS10,
    ARSIZE_IS10,
    ARBURST_IS10,
    ARLOCK_IS10,
    ARCACHE_IS10,
    ARPROT_IS10,
    ARVALID_IS10,
    ARREADY_S10_I,
    // AXI SLAVE 10 read response channel signals
    RID_S10_I,
    RDATA_S10_I,
    RRESP_S10_I,
    RLAST_S10_I,
    RVALID_S10_I,
    RREADY_IS10,

    // SLAVE 11
    // AXI SLAVE 11 write address channel signals
    AWID_IS11,
    AWADDR_IS11,
    AWLEN_IS11,
    AWSIZE_IS11,
    AWBURST_IS11,
    AWLOCK_IS11,
    AWCACHE_IS11,
    AWPROT_IS11,
    AWVALID_IS11,
    AWREADY_S11_I,
    // AXI SLAVE 11 write data channel signals
    WID_IS11,
    WDATA_IS11,
    WSTRB_IS11,
    WLAST_IS11,
    WVALID_IS11,
    WREADY_S11_I,
    // AXI SLAVE 11 write response channel signals
    BID_S11_I,
    BRESP_S11_I,
    BVALID_S11_I,
    BREADY_IS11,
    // AXI SLAVE 11 read address channel signals
    ARID_IS11,
    ARADDR_IS11,
    ARLEN_IS11,
    ARSIZE_IS11,
    ARBURST_IS11,
    ARLOCK_IS11,
    ARCACHE_IS11,
    ARPROT_IS11,
    ARVALID_IS11,
    ARREADY_S11_I,
    // AXI SLAVE 11 read response channel signals
    RID_S11_I,
    RDATA_S11_I,
    RRESP_S11_I,
    RLAST_S11_I,
    RVALID_S11_I,
    RREADY_IS11,

    // SLAVE 12
    // AXI SLAVE 12 write address channel signals
    AWID_IS12,
    AWADDR_IS12,
    AWLEN_IS12,
    AWSIZE_IS12,
    AWBURST_IS12,
    AWLOCK_IS12,
    AWCACHE_IS12,
    AWPROT_IS12,
    AWVALID_IS12,
    AWREADY_S12_I,
    // AXI SLAVE 12 write data channel signals
    WID_IS12,
    WDATA_IS12,
    WSTRB_IS12,
    WLAST_IS12,
    WVALID_IS12,
    WREADY_S12_I,
    // AXI SLAVE 12 write response channel signals
    BID_S12_I,
    BRESP_S12_I,
    BVALID_S12_I,
    BREADY_IS12,
    // AXI SLAVE 12 read address channel signals
    ARID_IS12,
    ARADDR_IS12,
    ARLEN_IS12,
    ARSIZE_IS12,
    ARBURST_IS12,
    ARLOCK_IS12,
    ARCACHE_IS12,
    ARPROT_IS12,
    ARVALID_IS12,
    ARREADY_S12_I,
    // AXI SLAVE 12 read response channel signals
    RID_S12_I,
    RDATA_S12_I,
    RRESP_S12_I,
    RLAST_S12_I,
    RVALID_S12_I,
    RREADY_IS12,

    // SLAVE 13
    // AXI SLAVE 13 write address channel signals
    AWID_IS13,
    AWADDR_IS13,
    AWLEN_IS13,
    AWSIZE_IS13,
    AWBURST_IS13,
    AWLOCK_IS13,
    AWCACHE_IS13,
    AWPROT_IS13,
    AWVALID_IS13,
    AWREADY_S13_I,
    // AXI SLAVE 13 write data channel signals
    WID_IS13,
    WDATA_IS13,
    WSTRB_IS13,
    WLAST_IS13,
    WVALID_IS13,
    WREADY_S13_I,
    // AXI SLAVE 13 write response channel signals
    BID_S13_I,
    BRESP_S13_I,
    BVALID_S13_I,
    BREADY_IS13,
    // AXI SLAVE 13 read address channel signals
    ARID_IS13,
    ARADDR_IS13,
    ARLEN_IS13,
    ARSIZE_IS13,
    ARBURST_IS13,
    ARLOCK_IS13,
    ARCACHE_IS13,
    ARPROT_IS13,
    ARVALID_IS13,
    ARREADY_S13_I,
    // AXI SLAVE 13 read response channel signals
    RID_S13_I,
    RDATA_S13_I,
    RRESP_S13_I,
    RLAST_S13_I,
    RVALID_S13_I,
    RREADY_IS13,

    // SLAVE 14
    // AXI SLAVE 14 write address channel signals
    AWID_IS14,
    AWADDR_IS14,
    AWLEN_IS14,
    AWSIZE_IS14,
    AWBURST_IS14,
    AWLOCK_IS14,
    AWCACHE_IS14,
    AWPROT_IS14,
    AWVALID_IS14,
    AWREADY_S14_I,
    // AXI SLAVE 14 write data channel signals
    WID_IS14,
    WDATA_IS14,
    WSTRB_IS14,
    WLAST_IS14,
    WVALID_IS14,
    WREADY_S14_I,
    // AXI SLAVE 14 write response channel signals
    BID_S14_I,
    BRESP_S14_I,
    BVALID_S14_I,
    BREADY_IS14,
    // AXI SLAVE 14 read address channel signals
    ARID_IS14,
    ARADDR_IS14,
    ARLEN_IS14,
    ARSIZE_IS14,
    ARBURST_IS14,
    ARLOCK_IS14,
    ARCACHE_IS14,
    ARPROT_IS14,
    ARVALID_IS14,
    ARREADY_S14_I,
    // AXI SLAVE 14 read response channel signals
    RID_S14_I,
    RDATA_S14_I,
    RRESP_S14_I,
    RLAST_S14_I,
    RVALID_S14_I,
    RREADY_IS14,

    // SLAVE 15
    // AXI SLAVE 15 write address channel signals
    AWID_IS15,
    AWADDR_IS15,
    AWLEN_IS15,
    AWSIZE_IS15,
    AWBURST_IS15,
    AWLOCK_IS15,
    AWCACHE_IS15,
    AWPROT_IS15,
    AWVALID_IS15,
    AWREADY_S15_I,
    // AXI SLAVE 15 write data channel signals
    WID_IS15,
    WDATA_IS15,
    WSTRB_IS15,
    WLAST_IS15,
    WVALID_IS15,
    WREADY_S15_I,
    // AXI SLAVE 15 write response channel signals
    BID_S15_I,
    BRESP_S15_I,
    BVALID_S15_I,
    BREADY_IS15,
    // AXI SLAVE 15 read address channel signals
    ARID_IS15,
    ARADDR_IS15,
    ARLEN_IS15,
    ARSIZE_IS15,
    ARBURST_IS15,
    ARLOCK_IS15,
    ARCACHE_IS15,
    ARPROT_IS15,
    ARVALID_IS15,
    ARREADY_S15_I,
    // AXI SLAVE 15 read response channel signals
    RID_S15_I,
    RDATA_S15_I,
    RRESP_S15_I,
    RLAST_S15_I,
    RVALID_S15_I,
    RREADY_IS15,
    awaddr_buf,
    araddr_buf
);

   // --------------------------------------------------------------------------
   // PARAMETER Declaration
   // --------------------------------------------------------------------------
    parameter AXI_AWIDTH           = 32;
    parameter AXI_DWIDTH           = 64;
    parameter AXI_STRBWIDTH        = AXI_DWIDTH/8;
    parameter M0_SLAVE0ENABLE      = 1;
    parameter M0_SLAVE1ENABLE      = 0;
    parameter M0_SLAVE2ENABLE      = 0;
    parameter M0_SLAVE3ENABLE      = 0;
    parameter M0_SLAVE4ENABLE      = 0;
    parameter M0_SLAVE5ENABLE      = 0;
    parameter M0_SLAVE6ENABLE      = 0;
    parameter M0_SLAVE7ENABLE      = 0;
    parameter M0_SLAVE8ENABLE      = 0;
    parameter M0_SLAVE9ENABLE      = 0;
    parameter M0_SLAVE10ENABLE     = 0;
    parameter M0_SLAVE11ENABLE     = 0;
    parameter M0_SLAVE12ENABLE     = 0;
    parameter M0_SLAVE13ENABLE     = 0;
    parameter M0_SLAVE14ENABLE     = 0;
    parameter M0_SLAVE15ENABLE     = 0;
    parameter NUM_SLAVE_SLOT       = 1;
    parameter ID_WIDTH             = 4;
    parameter BASE_ID_WIDTH        = 0;

    localparam SLAVE_0  =        16'b0000000000000001;
    localparam SLAVE_1  =        16'b0000000000000010;
    localparam SLAVE_2  =        16'b0000000000000100;
    localparam SLAVE_3  =        16'b0000000000001000;
    localparam SLAVE_4  =        16'b0000000000010000;
    localparam SLAVE_5  =        16'b0000000000100000;
    localparam SLAVE_6  =        16'b0000000001000000;
    localparam SLAVE_7  =        16'b0000000010000000;
    localparam SLAVE_8  =        16'b0000000100000000;
    localparam SLAVE_9  =        16'b0000001000000000;
    localparam SLAVE_A  =        16'b0000010000000000;
    localparam SLAVE_B  =        16'b0000100000000000;
    localparam SLAVE_C  =        16'b0001000000000000;
    localparam SLAVE_D  =        16'b0010000000000000;
    localparam SLAVE_E  =        16'b0100000000000000;
    localparam SLAVE_F  =        16'b1000000000000000;
    localparam SLAVE_N  =        16'b0000000000000000;

   // --------------------------------------------------------------------------
   // I/O Declaration
   // --------------------------------------------------------------------------
   // Global signals
   input       ACLK;
   input       ARESETN;

   // From Master
   // AXI write address channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_MI;
   input [AXI_AWIDTH-1:0]        AWADDR_MI;
   input [3:0]                   AWLEN_MI;
   input [2:0]                   AWSIZE_MI;
   input [1:0]                   AWBURST_MI;
   input [1:0]                   AWLOCK_MI;
   input [3:0]                   AWCACHE_MI;
   input [2:0]                   AWPROT_MI;
   input                         AWVALID_MI;
   output                        AWREADY_IM;
   // AXI write data channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_MI;
   input [AXI_DWIDTH-1:0]        WDATA_MI;
   input [AXI_STRBWIDTH-1:0]     WSTRB_MI;
   input                         WLAST_MI;
   input                         WVALID_MI;
   output                        WREADY_IM;
   // AXI write response channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_IM;
   output [1:0]                 BRESP_IM;
   output                       BVALID_IM;
   input                        BREADY_MI;
   // AXI read address channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_MI;
   input [AXI_AWIDTH-1:0]       ARADDR_MI;
   input [3:0]                  ARLEN_MI;
   input [2:0]                  ARSIZE_MI;
   input [1:0]                  ARBURST_MI;
   input [1:0]                  ARLOCK_MI;
   input [3:0]                  ARCACHE_MI;
   input [2:0]                  ARPROT_MI;
   input                        ARVALID_MI;
   output                       ARREADY_IM;
   // AXI read response channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_IM;
   output [AXI_DWIDTH-1:0]      RDATA_IM;
   output [1:0]                 RRESP_IM;
   output                       RLAST_IM;
   output                       RVALID_IM;
   input                        RREADY_MI;
   
    // SLAVE 0
    // AXI SLAVE 0 write address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS0;
    output [AXI_AWIDTH-1:0]      AWADDR_IS0;
    output [3:0]                 AWLEN_IS0;
    output [2:0]                 AWSIZE_IS0;
    output [1:0]                 AWBURST_IS0;
    output [1:0]                 AWLOCK_IS0;
    output [3:0]                 AWCACHE_IS0;
    output [2:0]                 AWPROT_IS0;
    output                       AWVALID_IS0;
    input                        AWREADY_S0_I;
    // AXI SLAVE 0 write data channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS0;
    output [AXI_DWIDTH-1:0]      WDATA_IS0;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS0;
    output                       WLAST_IS0;
    output                       WVALID_IS0;
    input                        WREADY_S0_I;
    // AXI SLAVE 0 write response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_S0_I;
    input  [1:0]                 BRESP_S0_I;
    input                        BVALID_S0_I;
    output                       BREADY_IS0;
    // AXI SLAVE 0 read address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS0;
    output [AXI_AWIDTH-1:0]      ARADDR_IS0;
    output [3:0]                 ARLEN_IS0;
    output [2:0]                 ARSIZE_IS0;
    output [1:0]                 ARBURST_IS0;
    output [1:0]                 ARLOCK_IS0;
    output [3:0]                 ARCACHE_IS0;
    output [2:0]                 ARPROT_IS0;
    output                       ARVALID_IS0;
    input                        ARREADY_S0_I;
    // AXI SLAVE 0 read response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_S0_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S0_I;
    input  [1:0]                 RRESP_S0_I;
    input                        RLAST_S0_I;
    input                        RVALID_S0_I;
    output                       RREADY_IS0;

    // SLAVE 1
    // AXI SLAVE 1 write address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS1;
    output [AXI_AWIDTH-1:0]      AWADDR_IS1;
    output [3:0]                 AWLEN_IS1;
    output [2:0]                 AWSIZE_IS1;
    output [1:0]                 AWBURST_IS1;
    output [1:0]                 AWLOCK_IS1;
    output [3:0]                 AWCACHE_IS1;
    output [2:0]                 AWPROT_IS1;
    output                       AWVALID_IS1;
    input                        AWREADY_S1_I;
    // AXI SLAVE 0 write data channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS1;
    output [AXI_DWIDTH-1:0]      WDATA_IS1;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS1;
    output                       WLAST_IS1;
    output                       WVALID_IS1;
    input                        WREADY_S1_I;
    // AXI SLAVE 0 write response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_S1_I;
    input  [1:0]                 BRESP_S1_I;
    input                        BVALID_S1_I;
    output                       BREADY_IS1;
    // AXI SLAVE 0 read address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS1;
    output [AXI_AWIDTH-1:0]      ARADDR_IS1;
    output [3:0]                 ARLEN_IS1;
    output [2:0]                 ARSIZE_IS1;
    output [1:0]                 ARBURST_IS1;
    output [1:0]                 ARLOCK_IS1;
    output [3:0]                 ARCACHE_IS1;
    output [2:0]                 ARPROT_IS1;
    output                       ARVALID_IS1;
    input                        ARREADY_S1_I;
    // AXI SLAVE 0 read response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_S1_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S1_I;
    input  [1:0]                 RRESP_S1_I;
    input                        RLAST_S1_I;
    input                        RVALID_S1_I;
    output                       RREADY_IS1;

    // SLAVE 2
    // AXI SLAVE 2 write address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS2;
    output [AXI_AWIDTH-1:0]      AWADDR_IS2;
    output [3:0]                 AWLEN_IS2;
    output [2:0]                 AWSIZE_IS2;
    output [1:0]                 AWBURST_IS2;
    output [1:0]                 AWLOCK_IS2;
    output [3:0]                 AWCACHE_IS2;
    output [2:0]                 AWPROT_IS2;
    output                       AWVALID_IS2;
    input                        AWREADY_S2_I;
    // AXI SLAVE 0 write data channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS2;
    output [AXI_DWIDTH-1:0]      WDATA_IS2;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS2;
    output                       WLAST_IS2;
    output                       WVALID_IS2;
    input                        WREADY_S2_I;
    // AXI SLAVE 0 write response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_S2_I;
    input  [1:0]                 BRESP_S2_I;
    input                        BVALID_S2_I;
    output                       BREADY_IS2;
    // AXI SLAVE 0 read address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS2;
    output [AXI_AWIDTH-1:0]      ARADDR_IS2;
    output [3:0]                 ARLEN_IS2;
    output [2:0]                 ARSIZE_IS2;
    output [1:0]                 ARBURST_IS2;
    output [1:0]                 ARLOCK_IS2;
    output [3:0]                 ARCACHE_IS2;
    output [2:0]                 ARPROT_IS2;
    output                       ARVALID_IS2;
    input                        ARREADY_S2_I;
    // AXI SLAVE 0 read response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_S2_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S2_I;
    input  [1:0]                 RRESP_S2_I;
    input                        RLAST_S2_I;
    input                        RVALID_S2_I;
    output                       RREADY_IS2;

    // SLAVE 3
    // AXI SLAVE 3 write address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS3;
    output [AXI_AWIDTH-1:0]      AWADDR_IS3;
    output [3:0]                 AWLEN_IS3;
    output [2:0]                 AWSIZE_IS3;
    output [1:0]                 AWBURST_IS3;
    output [1:0]                 AWLOCK_IS3;
    output [3:0]                 AWCACHE_IS3;
    output [2:0]                 AWPROT_IS3;
    output                       AWVALID_IS3;
    input                        AWREADY_S3_I;
    // AXI SLAVE 0 write data channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS3;
    output [AXI_DWIDTH-1:0]      WDATA_IS3;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS3;
    output                       WLAST_IS3;
    output                       WVALID_IS3;
    input                        WREADY_S3_I;
    // AXI SLAVE 0 write response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_S3_I;
    input  [1:0]                 BRESP_S3_I;
    input                        BVALID_S3_I;
    output                       BREADY_IS3;
    // AXI SLAVE 0 read address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS3;
    output [AXI_AWIDTH-1:0]      ARADDR_IS3;
    output [3:0]                 ARLEN_IS3;
    output [2:0]                 ARSIZE_IS3;
    output [1:0]                 ARBURST_IS3;
    output [1:0]                 ARLOCK_IS3;
    output [3:0]                 ARCACHE_IS3;
    output [2:0]                 ARPROT_IS3;
    output                       ARVALID_IS3;
    input                        ARREADY_S3_I;
    // AXI SLAVE 0 read response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_S3_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S3_I;
    input  [1:0]                 RRESP_S3_I;
    input                        RLAST_S3_I;
    input                        RVALID_S3_I;
    output                       RREADY_IS3;

    // SLAVE 4
    // AXI SLAVE 4 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS4;
    output [AXI_AWIDTH-1:0]      AWADDR_IS4;
    output [3:0]                 AWLEN_IS4;
    output [2:0]                 AWSIZE_IS4;
    output [1:0]                 AWBURST_IS4;
    output [1:0]                 AWLOCK_IS4;
    output [3:0]                 AWCACHE_IS4;
    output [2:0]                 AWPROT_IS4;
    output                       AWVALID_IS4;
    input                        AWREADY_S4_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS4;
    output [AXI_DWIDTH-1:0]      WDATA_IS4;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS4;
    output                       WLAST_IS4;
    output                       WVALID_IS4;
    input                        WREADY_S4_I;
    // AXI SLAVE 0 write response channel signals
    input [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_S4_I;
    input  [1:0]                 BRESP_S4_I;
    input                        BVALID_S4_I;
    output                       BREADY_IS4;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS4;
    output [AXI_AWIDTH-1:0]      ARADDR_IS4;
    output [3:0]                 ARLEN_IS4;
    output [2:0]                 ARSIZE_IS4;
    output [1:0]                 ARBURST_IS4;
    output [1:0]                 ARLOCK_IS4;
    output [3:0]                 ARCACHE_IS4;
    output [2:0]                 ARPROT_IS4;
    output                       ARVALID_IS4;
    input                        ARREADY_S4_I;
    // AXI SLAVE 0 read response channel signals
    input [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_S4_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S4_I;
    input  [1:0]                 RRESP_S4_I;
    input                        RLAST_S4_I;
    input                        RVALID_S4_I;
    output                       RREADY_IS4;

    // SLAVE 5
    // AXI SLAVE 5 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS5;
    output [AXI_AWIDTH-1:0]      AWADDR_IS5;
    output [3:0]                 AWLEN_IS5;
    output [2:0]                 AWSIZE_IS5;
    output [1:0]                 AWBURST_IS5;
    output [1:0]                 AWLOCK_IS5;
    output [3:0]                 AWCACHE_IS5;
    output [2:0]                 AWPROT_IS5;
    output                       AWVALID_IS5;
    input                        AWREADY_S5_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS5;
    output [AXI_DWIDTH-1:0]      WDATA_IS5;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS5;
    output                       WLAST_IS5;
    output                       WVALID_IS5;
    input                        WREADY_S5_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S5_I;
    input  [1:0]                 BRESP_S5_I;
    input                        BVALID_S5_I;
    output                       BREADY_IS5;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS5;
    output [AXI_AWIDTH-1:0]      ARADDR_IS5;
    output [3:0]                 ARLEN_IS5;
    output [2:0]                 ARSIZE_IS5;
    output [1:0]                 ARBURST_IS5;
    output [1:0]                 ARLOCK_IS5;
    output [3:0]                 ARCACHE_IS5;
    output [2:0]                 ARPROT_IS5;
    output                       ARVALID_IS5;
    input                        ARREADY_S5_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S5_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S5_I;
    input  [1:0]                 RRESP_S5_I;
    input                        RLAST_S5_I;
    input                        RVALID_S5_I;
    output                       RREADY_IS5;

    // SLAVE 6
    // AXI SLAVE 6 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS6;
    output [AXI_AWIDTH-1:0]      AWADDR_IS6;
    output [3:0]                 AWLEN_IS6;
    output [2:0]                 AWSIZE_IS6;
    output [1:0]                 AWBURST_IS6;
    output [1:0]                 AWLOCK_IS6;
    output [3:0]                 AWCACHE_IS6;
    output [2:0]                 AWPROT_IS6;
    output                       AWVALID_IS6;
    input                        AWREADY_S6_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS6;
    output [AXI_DWIDTH-1:0]      WDATA_IS6;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS6;
    output                       WLAST_IS6;
    output                       WVALID_IS6;
    input                        WREADY_S6_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S6_I;
    input  [1:0]                 BRESP_S6_I;
    input                        BVALID_S6_I;
    output                       BREADY_IS6;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS6;
    output [AXI_AWIDTH-1:0]      ARADDR_IS6;
    output [3:0]                 ARLEN_IS6;
    output [2:0]                 ARSIZE_IS6;
    output [1:0]                 ARBURST_IS6;
    output [1:0]                 ARLOCK_IS6;
    output [3:0]                 ARCACHE_IS6;
    output [2:0]                 ARPROT_IS6;
    output                       ARVALID_IS6;
    input                        ARREADY_S6_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S6_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S6_I;
    input  [1:0]                 RRESP_S6_I;
    input                        RLAST_S6_I;
    input                        RVALID_S6_I;
    output                       RREADY_IS6;

    // SLAVE 7
    // AXI SLAVE 7 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS7;
    output [AXI_AWIDTH-1:0]      AWADDR_IS7;
    output [3:0]                 AWLEN_IS7;
    output [2:0]                 AWSIZE_IS7;
    output [1:0]                 AWBURST_IS7;
    output [1:0]                 AWLOCK_IS7;
    output [3:0]                 AWCACHE_IS7;
    output [2:0]                 AWPROT_IS7;
    output                       AWVALID_IS7;
    input                        AWREADY_S7_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS7;
    output [AXI_DWIDTH-1:0]      WDATA_IS7;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS7;
    output                       WLAST_IS7;
    output                       WVALID_IS7;
    input                        WREADY_S7_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S7_I;
    input  [1:0]                 BRESP_S7_I;
    input                        BVALID_S7_I;
    output                       BREADY_IS7;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS7;
    output [AXI_AWIDTH-1:0]      ARADDR_IS7;
    output [3:0]                 ARLEN_IS7;
    output [2:0]                 ARSIZE_IS7;
    output [1:0]                 ARBURST_IS7;
    output [1:0]                 ARLOCK_IS7;
    output [3:0]                 ARCACHE_IS7;
    output [2:0]                 ARPROT_IS7;
    output                       ARVALID_IS7;
    input                        ARREADY_S7_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S7_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S7_I;
    input  [1:0]                 RRESP_S7_I;
    input                        RLAST_S7_I;
    input                        RVALID_S7_I;
    output                       RREADY_IS7;

    // SLAVE 8
    // AXI SLAVE 8 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS8;
    output [AXI_AWIDTH-1:0]      AWADDR_IS8;
    output [3:0]                 AWLEN_IS8;
    output [2:0]                 AWSIZE_IS8;
    output [1:0]                 AWBURST_IS8;
    output [1:0]                 AWLOCK_IS8;
    output [3:0]                 AWCACHE_IS8;
    output [2:0]                 AWPROT_IS8;
    output                       AWVALID_IS8;
    input                        AWREADY_S8_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS8;
    output [AXI_DWIDTH-1:0]      WDATA_IS8;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS8;
    output                       WLAST_IS8;
    output                       WVALID_IS8;
    input                        WREADY_S8_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S8_I;
    input  [1:0]                 BRESP_S8_I;
    input                        BVALID_S8_I;
    output                       BREADY_IS8;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS8;
    output [AXI_AWIDTH-1:0]      ARADDR_IS8;
    output [3:0]                 ARLEN_IS8;
    output [2:0]                 ARSIZE_IS8;
    output [1:0]                 ARBURST_IS8;
    output [1:0]                 ARLOCK_IS8;
    output [3:0]                 ARCACHE_IS8;
    output [2:0]                 ARPROT_IS8;
    output                       ARVALID_IS8;
    input                        ARREADY_S8_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S8_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S8_I;
    input  [1:0]                 RRESP_S8_I;
    input                        RLAST_S8_I;
    input                        RVALID_S8_I;
    output                       RREADY_IS8;

    // SLAVE 9
    // AXI SLAVE 9 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS9;
    output [AXI_AWIDTH-1:0]      AWADDR_IS9;
    output [3:0]                 AWLEN_IS9;
    output [2:0]                 AWSIZE_IS9;
    output [1:0]                 AWBURST_IS9;
    output [1:0]                 AWLOCK_IS9;
    output [3:0]                 AWCACHE_IS9;
    output [2:0]                 AWPROT_IS9;
    output                       AWVALID_IS9;
    input                        AWREADY_S9_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS9;
    output [AXI_DWIDTH-1:0]      WDATA_IS9;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS9;
    output                       WLAST_IS9;
    output                       WVALID_IS9;
    input                        WREADY_S9_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S9_I;
    input  [1:0]                 BRESP_S9_I;
    input                        BVALID_S9_I;
    output                       BREADY_IS9;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS9;
    output [AXI_AWIDTH-1:0]      ARADDR_IS9;
    output [3:0]                 ARLEN_IS9;
    output [2:0]                 ARSIZE_IS9;
    output [1:0]                 ARBURST_IS9;
    output [1:0]                 ARLOCK_IS9;
    output [3:0]                 ARCACHE_IS9;
    output [2:0]                 ARPROT_IS9;
    output                       ARVALID_IS9;
    input                        ARREADY_S9_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S9_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S9_I;
    input  [1:0]                 RRESP_S9_I;
    input                        RLAST_S9_I;
    input                        RVALID_S9_I;
    output                       RREADY_IS9;

    // SLAVE 10
    // AXI SLAVE 10 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS10;
    output [AXI_AWIDTH-1:0]      AWADDR_IS10;
    output [3:0]                 AWLEN_IS10;
    output [2:0]                 AWSIZE_IS10;
    output [1:0]                 AWBURST_IS10;
    output [1:0]                 AWLOCK_IS10;
    output [3:0]                 AWCACHE_IS10;
    output [2:0]                 AWPROT_IS10;
    output                       AWVALID_IS10;
    input                        AWREADY_S10_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS10;
    output [AXI_DWIDTH-1:0]      WDATA_IS10;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS10;
    output                       WLAST_IS10;
    output                       WVALID_IS10;
    input                        WREADY_S10_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S10_I;
    input  [1:0]                 BRESP_S10_I;
    input                        BVALID_S10_I;
    output                       BREADY_IS10;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS10;
    output [AXI_AWIDTH-1:0]      ARADDR_IS10;
    output [3:0]                 ARLEN_IS10;
    output [2:0]                 ARSIZE_IS10;
    output [1:0]                 ARBURST_IS10;
    output [1:0]                 ARLOCK_IS10;
    output [3:0]                 ARCACHE_IS10;
    output [2:0]                 ARPROT_IS10;
    output                       ARVALID_IS10;
    input                        ARREADY_S10_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S10_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S10_I;
    input  [1:0]                 RRESP_S10_I;
    input                        RLAST_S10_I;
    input                        RVALID_S10_I;
    output                       RREADY_IS10;

    // SLAVE 11
    // AXI SLAVE 11 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS11;
    output [AXI_AWIDTH-1:0]      AWADDR_IS11;
    output [3:0]                 AWLEN_IS11;
    output [2:0]                 AWSIZE_IS11;
    output [1:0]                 AWBURST_IS11;
    output [1:0]                 AWLOCK_IS11;
    output [3:0]                 AWCACHE_IS11;
    output [2:0]                 AWPROT_IS11;
    output                       AWVALID_IS11;
    input                        AWREADY_S11_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS11;
    output [AXI_DWIDTH-1:0]      WDATA_IS11;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS11;
    output                       WLAST_IS11;
    output                       WVALID_IS11;
    input                        WREADY_S11_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S11_I;
    input  [1:0]                 BRESP_S11_I;
    input                        BVALID_S11_I;
    output                       BREADY_IS11;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS11;
    output [AXI_AWIDTH-1:0]      ARADDR_IS11;
    output [3:0]                 ARLEN_IS11;
    output [2:0]                 ARSIZE_IS11;
    output [1:0]                 ARBURST_IS11;
    output [1:0]                 ARLOCK_IS11;
    output [3:0]                 ARCACHE_IS11;
    output [2:0]                 ARPROT_IS11;
    output                       ARVALID_IS11;
    input                        ARREADY_S11_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S11_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S11_I;
    input  [1:0]                 RRESP_S11_I;
    input                        RLAST_S11_I;
    input                        RVALID_S11_I;
    output                       RREADY_IS11;

    // SLAVE 12
    // AXI SLAVE 12 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS12;
    output [AXI_AWIDTH-1:0]      AWADDR_IS12;
    output [3:0]                 AWLEN_IS12;
    output [2:0]                 AWSIZE_IS12;
    output [1:0]                 AWBURST_IS12;
    output [1:0]                 AWLOCK_IS12;
    output [3:0]                 AWCACHE_IS12;
    output [2:0]                 AWPROT_IS12;
    output                       AWVALID_IS12;
    input                        AWREADY_S12_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS12;
    output [AXI_DWIDTH-1:0]      WDATA_IS12;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS12;
    output                       WLAST_IS12;
    output                       WVALID_IS12;
    input                        WREADY_S12_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S12_I;
    input  [1:0]                 BRESP_S12_I;
    input                        BVALID_S12_I;
    output                       BREADY_IS12;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS12;
    output [AXI_AWIDTH-1:0]      ARADDR_IS12;
    output [3:0]                 ARLEN_IS12;
    output [2:0]                 ARSIZE_IS12;
    output [1:0]                 ARBURST_IS12;
    output [1:0]                 ARLOCK_IS12;
    output [3:0]                 ARCACHE_IS12;
    output [2:0]                 ARPROT_IS12;
    output                       ARVALID_IS12;
    input                        ARREADY_S12_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S12_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S12_I;
    input  [1:0]                 RRESP_S12_I;
    input                        RLAST_S12_I;
    input                        RVALID_S12_I;
    output                       RREADY_IS12;

    // SLAVE 13
    // AXI SLAVE 13 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS13;
    output [AXI_AWIDTH-1:0]      AWADDR_IS13;
    output [3:0]                 AWLEN_IS13;
    output [2:0]                 AWSIZE_IS13;
    output [1:0]                 AWBURST_IS13;
    output [1:0]                 AWLOCK_IS13;
    output [3:0]                 AWCACHE_IS13;
    output [2:0]                 AWPROT_IS13;
    output                       AWVALID_IS13;
    input                        AWREADY_S13_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS13;
    output [AXI_DWIDTH-1:0]      WDATA_IS13;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS13;
    output                       WLAST_IS13;
    output                       WVALID_IS13;
    input                        WREADY_S13_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S13_I;
    input  [1:0]                 BRESP_S13_I;
    input                        BVALID_S13_I;
    output                       BREADY_IS13;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS13;
    output [AXI_AWIDTH-1:0]      ARADDR_IS13;
    output [3:0]                 ARLEN_IS13;
    output [2:0]                 ARSIZE_IS13;
    output [1:0]                 ARBURST_IS13;
    output [1:0]                 ARLOCK_IS13;
    output [3:0]                 ARCACHE_IS13;
    output [2:0]                 ARPROT_IS13;
    output                       ARVALID_IS13;
    input                        ARREADY_S13_I;
    // AXI SLAVE 0 read response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 RID_S13_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S13_I;
    input  [1:0]                 RRESP_S13_I;
    input                        RLAST_S13_I;
    input                        RVALID_S13_I;
    output                       RREADY_IS13;

    // SLAVE 14
    // AXI SLAVE 14 write address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 AWID_IS14;
    output [AXI_AWIDTH-1:0]      AWADDR_IS14;
    output [3:0]                 AWLEN_IS14;
    output [2:0]                 AWSIZE_IS14;
    output [1:0]                 AWBURST_IS14;
    output [1:0]                 AWLOCK_IS14;
    output [3:0]                 AWCACHE_IS14;
    output [2:0]                 AWPROT_IS14;
    output                       AWVALID_IS14;
    input                        AWREADY_S14_I;
    // AXI SLAVE 0 write data channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 WID_IS14;
    output [AXI_DWIDTH-1:0]      WDATA_IS14;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS14;
    output                       WLAST_IS14;
    output                       WVALID_IS14;
    input                        WREADY_S14_I;
    // AXI SLAVE 0 write response channel signals
    input  [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 BID_S14_I;
    input  [1:0]                 BRESP_S14_I;
    input                        BVALID_S14_I;
    output                       BREADY_IS14;
    // AXI SLAVE 0 read address channel signals
    output [BASE_ID_WIDTH+ID_WIDTH - 1:0]                 ARID_IS14;
    output [AXI_AWIDTH-1:0]      ARADDR_IS14;
    output [3:0]                 ARLEN_IS14;
    output [2:0]                 ARSIZE_IS14;
    output [1:0]                 ARBURST_IS14;
    output [1:0]                 ARLOCK_IS14;
    output [3:0]                 ARCACHE_IS14;
    output [2:0]                 ARPROT_IS14;
    output                       ARVALID_IS14;
    input                        ARREADY_S14_I;
    // AXI SLAVE 0 read response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_S14_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S14_I;
    input  [1:0]                 RRESP_S14_I;
    input                        RLAST_S14_I;
    input                        RVALID_S14_I;
    output                       RREADY_IS14;

    // SLAVE 15
    // AXI SLAVE 15 write address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS15;
    output [AXI_AWIDTH-1:0]      AWADDR_IS15;
    output [3:0]                 AWLEN_IS15;
    output [2:0]                 AWSIZE_IS15;
    output [1:0]                 AWBURST_IS15;
    output [1:0]                 AWLOCK_IS15;
    output [3:0]                 AWCACHE_IS15;
    output [2:0]                 AWPROT_IS15;
    output                       AWVALID_IS15;
    input                        AWREADY_S15_I;
    // AXI SLAVE 0 write data channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS15;
    output [AXI_DWIDTH-1:0]      WDATA_IS15;
    output [AXI_STRBWIDTH-1:0]   WSTRB_IS15;
    output                       WLAST_IS15;
    output                       WVALID_IS15;
    input                        WREADY_S15_I;
    // AXI SLAVE 0 write response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_S15_I;
    input  [1:0]                 BRESP_S15_I;
    input                        BVALID_S15_I;
    output                       BREADY_IS15;
    // AXI SLAVE 0 read address channel signals
   output [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS15;
    output [AXI_AWIDTH-1:0]      ARADDR_IS15;
    output [3:0]                 ARLEN_IS15;
    output [2:0]                 ARSIZE_IS15;
    output [1:0]                 ARBURST_IS15;
    output [1:0]                 ARLOCK_IS15;
    output [3:0]                 ARCACHE_IS15;
    output [2:0]                 ARPROT_IS15;
    output                       ARVALID_IS15;
    input                        ARREADY_S15_I;
    // AXI SLAVE 0 read response channel signals
   input [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_S15_I;
    input  [AXI_DWIDTH-1:0]      RDATA_S15_I;
    input  [1:0]                 RRESP_S15_I;
    input                        RLAST_S15_I;
    input                        RVALID_S15_I;
    output                       RREADY_IS15;
    input [AXI_AWIDTH - 1:0]     awaddr_buf;
    input [AXI_AWIDTH - 1:0]     araddr_buf;

   // --------------------------------------------------------------------------
   // Internal signals
   // --------------------------------------------------------------------------
   reg [15:0]                    SLAVE_SELECT_WADDRCH_M;
   reg [15:0]                    SLAVE_SELECT_RADDRCH_M;
   reg [15:0]                    SLAVE_SELECT_WDCH_M;
   reg [15:0]                    SLAVE_SELECT_WRESPCH_M;
   reg [15:0]                    SLAVE_SELECT_RDCH_M;
   reg                           AWREADY_IM_int;
   reg                           ARREADY_IM_int;
   reg                           AWREADY_IM;
   reg                           ARREADY_IM;
   reg                           WREADY_IM;
   reg                           WREADY_IM_int;
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_IM_int;
   reg                                BVALID_IM_int;
   reg [1:0]                          BRESP_IM_int;
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_IM_int;
   reg [AXI_DWIDTH - 1:0]             RDATA_IM_int;
   reg                                RLAST_IM_int;
   reg                                RVALID_IM_int;
   reg [1:0]                          RRESP_IM_int;

   reg [AXI_AWIDTH - 1:0]             addr_for_wready;
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_MI_r;
   reg                                WVALID_MI_r;
   reg                                WLAST_MI_r;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_MI_r;
   reg [AXI_DWIDTH-1:0]               WDATA_MI_r ;
   reg                                BREADY_MI_r;
   reg                                RREADY_MI_r;
   reg [AXI_AWIDTH - 1:0]             addr_for_rready;   
                                      
   reg [1:0]                          BRESP_IM;
   reg                                BVALID_IM;
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] BID_IM;

   reg                                BREADY_IS0;
   reg                                BREADY_IS1;
   reg                                BREADY_IS2;
   reg                                BREADY_IS3;
   reg                                BREADY_IS4;
   reg                                BREADY_IS5;
   reg                                BREADY_IS6;
   reg                                BREADY_IS7;
   reg                                BREADY_IS8;
   reg                                BREADY_IS9;
   reg                                BREADY_IS10;
   reg                                BREADY_IS11;
   reg                                BREADY_IS12;
   reg                                BREADY_IS13;
   reg                                BREADY_IS14;
   reg                                BREADY_IS15;
   
   reg [1:0]                          RRESP_IM;
   reg                                RVALID_IM;
   reg                                RLAST_IM;
   reg [AXI_DWIDTH - 1:0]             RDATA_IM;
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] RID_IM;

   reg                                RREADY_IS0;
   reg                                RREADY_IS1;
   reg                                RREADY_IS2;
   reg                                RREADY_IS3;
   reg                                RREADY_IS4;
   reg                                RREADY_IS5;
   reg                                RREADY_IS6;
   reg                                RREADY_IS7;
   reg                                RREADY_IS8;
   reg                                RREADY_IS9;
   reg                                RREADY_IS10;
   reg                                RREADY_IS11;
   reg                                RREADY_IS12;
   reg                                RREADY_IS13;
   reg                                RREADY_IS14;
   reg                                RREADY_IS15;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS0;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS0;
   reg [3:0]                          AWLEN_IS0;
   reg [2:0]                          AWSIZE_IS0;
   reg [1:0]                          AWBURST_IS0;
   reg [1:0]                          AWLOCK_IS0;
   reg [3:0]                          AWCACHE_IS0;
   reg [2:0]                          AWPROT_IS0;
   reg                                AWVALID_IS0;

   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS1;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS1;
   reg [3:0]                          AWLEN_IS1;
   reg [2:0]                          AWSIZE_IS1;
   reg [1:0]                          AWBURST_IS1;
   reg [1:0]                          AWLOCK_IS1;
   reg [3:0]                          AWCACHE_IS1;
   reg [2:0]                          AWPROT_IS1;
   reg                                AWVALID_IS1;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS2;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS2;
   reg [3:0]                          AWLEN_IS2;
   reg [2:0]                          AWSIZE_IS2;
   reg [1:0]                          AWBURST_IS2;
   reg [1:0]                          AWLOCK_IS2;
   reg [3:0]                          AWCACHE_IS2;
   reg [2:0]                          AWPROT_IS2;
   reg                                AWVALID_IS2;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS3;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS3;
   reg [3:0]                          AWLEN_IS3;
   reg [2:0]                          AWSIZE_IS3;
   reg [1:0]                          AWBURST_IS3;
   reg [1:0]                          AWLOCK_IS3;
   reg [3:0]                          AWCACHE_IS3;
   reg [2:0]                          AWPROT_IS3;
   reg                                AWVALID_IS3;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS4;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS4;
   reg [3:0]                          AWLEN_IS4;
   reg [2:0]                          AWSIZE_IS4;
   reg [1:0]                          AWBURST_IS4;
   reg [1:0]                          AWLOCK_IS4;
   reg [3:0]                          AWCACHE_IS4;
   reg [2:0]                          AWPROT_IS4;
   reg                                AWVALID_IS4;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS5;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS5;
   reg [3:0]                          AWLEN_IS5;
   reg [2:0]                          AWSIZE_IS5;
   reg [1:0]                          AWBURST_IS5;
   reg [1:0]                          AWLOCK_IS5;
   reg [3:0]                          AWCACHE_IS5;
   reg [2:0]                          AWPROT_IS5;
   reg                                AWVALID_IS5;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS6;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS6;
   reg [3:0]                          AWLEN_IS6;
   reg [2:0]                          AWSIZE_IS6;
   reg [1:0]                          AWBURST_IS6;
   reg [1:0]                          AWLOCK_IS6;
   reg [3:0]                          AWCACHE_IS6;
   reg [2:0]                          AWPROT_IS6;
   reg                                AWVALID_IS6;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS7;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS7;
   reg [3:0]                          AWLEN_IS7;
   reg [2:0]                          AWSIZE_IS7;
   reg [1:0]                          AWBURST_IS7;
   reg [1:0]                          AWLOCK_IS7;
   reg [3:0]                          AWCACHE_IS7;
   reg [2:0]                          AWPROT_IS7;
   reg                                AWVALID_IS7;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS8;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS8;
   reg [3:0]                          AWLEN_IS8;
   reg [2:0]                          AWSIZE_IS8;
   reg [1:0]                          AWBURST_IS8;
   reg [1:0]                          AWLOCK_IS8;
   reg [3:0]                          AWCACHE_IS8;
   reg [2:0]                          AWPROT_IS8;
   reg                                AWVALID_IS8;

   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS9;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS9;
   reg [3:0]                          AWLEN_IS9;
   reg [2:0]                          AWSIZE_IS9;
   reg [1:0]                          AWBURST_IS9;
   reg [1:0]                          AWLOCK_IS9;
   reg [3:0]                          AWCACHE_IS9;
   reg [2:0]                          AWPROT_IS9;
   reg                                AWVALID_IS9;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS10;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS10;
   reg [3:0]                          AWLEN_IS10;
   reg [2:0]                          AWSIZE_IS10;
   reg [1:0]                          AWBURST_IS10;
   reg [1:0]                          AWLOCK_IS10;
   reg [3:0]                          AWCACHE_IS10;
   reg [2:0]                          AWPROT_IS10;
   reg                                AWVALID_IS10;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS11;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS11;
   reg [3:0]                          AWLEN_IS11;
   reg [2:0]                          AWSIZE_IS11;
   reg [1:0]                          AWBURST_IS11;
   reg [1:0]                          AWLOCK_IS11;
   reg [3:0]                          AWCACHE_IS11;
   reg [2:0]                          AWPROT_IS11;
   reg                                AWVALID_IS11;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS12;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS12;
   reg [3:0]                          AWLEN_IS12;
   reg [2:0]                          AWSIZE_IS12;
   reg [1:0]                          AWBURST_IS12;
   reg [1:0]                          AWLOCK_IS12;
   reg [3:0]                          AWCACHE_IS12;
   reg [2:0]                          AWPROT_IS12;
   reg                                AWVALID_IS12;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS13;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS13;
   reg [3:0]                          AWLEN_IS13;
   reg [2:0]                          AWSIZE_IS13;
   reg [1:0]                          AWBURST_IS13;
   reg [1:0]                          AWLOCK_IS13;
   reg [3:0]                          AWCACHE_IS13;
   reg [2:0]                          AWPROT_IS13;
   reg                                AWVALID_IS13;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS14;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS14;
   reg [3:0]                          AWLEN_IS14;
   reg [2:0]                          AWSIZE_IS14;
   reg [1:0]                          AWBURST_IS14;
   reg [1:0]                          AWLOCK_IS14;
   reg [3:0]                          AWCACHE_IS14;
   reg [2:0]                          AWPROT_IS14;
   reg                                AWVALID_IS14;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] AWID_IS15;
   reg [AXI_AWIDTH-1:0]               AWADDR_IS15;
   reg [3:0]                          AWLEN_IS15;
   reg [2:0]                          AWSIZE_IS15;
   reg [1:0]                          AWBURST_IS15;
   reg [1:0]                          AWLOCK_IS15;
   reg [3:0]                          AWCACHE_IS15;
   reg [2:0]                          AWPROT_IS15;
   reg                                AWVALID_IS15;

   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS0;
   reg                                WVALID_IS0;
   reg [AXI_DWIDTH-1:0]               WDATA_IS0;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS0;
   reg                                WLAST_IS0;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS1;
   reg                                WVALID_IS1;
   reg [AXI_DWIDTH-1:0]               WDATA_IS1;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS1;
   reg                                WLAST_IS1;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS2;
   reg                                WVALID_IS2;
   reg [AXI_DWIDTH-1:0]               WDATA_IS2;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS2;
   reg                                WLAST_IS2;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS3;
   reg                                WVALID_IS3;
   reg [AXI_DWIDTH-1:0]               WDATA_IS3;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS3;
   reg                                WLAST_IS3;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS4;
   reg                                WVALID_IS4;
   reg [AXI_DWIDTH-1:0]               WDATA_IS4;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS4;
   reg                                WLAST_IS4;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS5;
   reg                                WVALID_IS5;
   reg [AXI_DWIDTH-1:0]               WDATA_IS5;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS5;
   reg                                WLAST_IS5;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS6;
   reg                                WVALID_IS6;
   reg [AXI_DWIDTH-1:0]               WDATA_IS6;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS6;
   reg                                WLAST_IS6;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS7;
   reg                                WVALID_IS7;
   reg [AXI_DWIDTH-1:0]               WDATA_IS7;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS7;
   reg                                WLAST_IS7;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS8;
   reg                                WVALID_IS8;
   reg [AXI_DWIDTH-1:0]               WDATA_IS8;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS8;
   reg                                WLAST_IS8;

   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS9;
   reg                                WVALID_IS9;
   reg [AXI_DWIDTH-1:0]               WDATA_IS9;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS9;
   reg                                WLAST_IS9;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS10;
   reg                                WVALID_IS10;
   reg [AXI_DWIDTH-1:0]               WDATA_IS10;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS10;
   reg                                WLAST_IS10;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS11;
   reg                                WVALID_IS11;
   reg [AXI_DWIDTH-1:0]               WDATA_IS11;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS11;
   reg                                WLAST_IS11;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS12;
   reg                                WVALID_IS12;
   reg [AXI_DWIDTH-1:0]               WDATA_IS12;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS12;
   reg                                WLAST_IS12;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS13;
   reg                                WVALID_IS13;
   reg [AXI_DWIDTH-1:0]               WDATA_IS13;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS13;
   reg                                WLAST_IS13;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS14;
   reg                                WVALID_IS14;
   reg [AXI_DWIDTH-1:0]               WDATA_IS14;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS14;
   reg                                WLAST_IS14;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] WID_IS15;
   reg                                WVALID_IS15;
   reg [AXI_DWIDTH-1:0]               WDATA_IS15;
   reg [AXI_STRBWIDTH-1:0]            WSTRB_IS15;
   reg                                WLAST_IS15;

   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS0;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS0;
   reg [3:0]                          ARLEN_IS0;
   reg [2:0]                          ARSIZE_IS0;
   reg [1:0]                          ARBURST_IS0;
   reg [1:0]                          ARLOCK_IS0;
   reg [3:0]                          ARCACHE_IS0;
   reg [2:0]                          ARPROT_IS0;
   reg                                ARVALID_IS0;

   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS1;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS1;
   reg [3:0]                          ARLEN_IS1;
   reg [2:0]                          ARSIZE_IS1;
   reg [1:0]                          ARBURST_IS1;
   reg [1:0]                          ARLOCK_IS1;
   reg [3:0]                          ARCACHE_IS1;
   reg [2:0]                          ARPROT_IS1;
   reg                                ARVALID_IS1;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS2;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS2;
   reg [3:0]                          ARLEN_IS2;
   reg [2:0]                          ARSIZE_IS2;
   reg [1:0]                          ARBURST_IS2;
   reg [1:0]                          ARLOCK_IS2;
   reg [3:0]                          ARCACHE_IS2;
   reg [2:0]                          ARPROT_IS2;
   reg                                ARVALID_IS2;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS3;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS3;
   reg [3:0]                          ARLEN_IS3;
   reg [2:0]                          ARSIZE_IS3;
   reg [1:0]                          ARBURST_IS3;
   reg [1:0]                          ARLOCK_IS3;
   reg [3:0]                          ARCACHE_IS3;
   reg [2:0]                          ARPROT_IS3;
   reg                                ARVALID_IS3;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS4;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS4;
   reg [3:0]                          ARLEN_IS4;
   reg [2:0]                          ARSIZE_IS4;
   reg [1:0]                          ARBURST_IS4;
   reg [1:0]                          ARLOCK_IS4;
   reg [3:0]                          ARCACHE_IS4;
   reg [2:0]                          ARPROT_IS4;
   reg                                ARVALID_IS4;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS5;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS5;
   reg [3:0]                          ARLEN_IS5;
   reg [2:0]                          ARSIZE_IS5;
   reg [1:0]                          ARBURST_IS5;
   reg [1:0]                          ARLOCK_IS5;
   reg [3:0]                          ARCACHE_IS5;
   reg [2:0]                          ARPROT_IS5;
   reg                                ARVALID_IS5;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS6;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS6;
   reg [3:0]                          ARLEN_IS6;
   reg [2:0]                          ARSIZE_IS6;
   reg [1:0]                          ARBURST_IS6;
   reg [1:0]                          ARLOCK_IS6;
   reg [3:0]                          ARCACHE_IS6;
   reg [2:0]                          ARPROT_IS6;
   reg                                ARVALID_IS6;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS7;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS7;
   reg [3:0]                          ARLEN_IS7;
   reg [2:0]                          ARSIZE_IS7;
   reg [1:0]                          ARBURST_IS7;
   reg [1:0]                          ARLOCK_IS7;
   reg [3:0]                          ARCACHE_IS7;
   reg [2:0]                          ARPROT_IS7;
   reg                                ARVALID_IS7;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS8;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS8;
   reg [3:0]                          ARLEN_IS8;
   reg [2:0]                          ARSIZE_IS8;
   reg [1:0]                          ARBURST_IS8;
   reg [1:0]                          ARLOCK_IS8;
   reg [3:0]                          ARCACHE_IS8;
   reg [2:0]                          ARPROT_IS8;
   reg                                ARVALID_IS8;

   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS9;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS9;
   reg [3:0]                          ARLEN_IS9;
   reg [2:0]                          ARSIZE_IS9;
   reg [1:0]                          ARBURST_IS9;
   reg [1:0]                          ARLOCK_IS9;
   reg [3:0]                          ARCACHE_IS9;
   reg [2:0]                          ARPROT_IS9;
   reg                                ARVALID_IS9;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS10;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS10;
   reg [3:0]                          ARLEN_IS10;
   reg [2:0]                          ARSIZE_IS10;
   reg [1:0]                          ARBURST_IS10;
   reg [1:0]                          ARLOCK_IS10;
   reg [3:0]                          ARCACHE_IS10;
   reg [2:0]                          ARPROT_IS10;
   reg                                ARVALID_IS10;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS11;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS11;
   reg [3:0]                          ARLEN_IS11;
   reg [2:0]                          ARSIZE_IS11;
   reg [1:0]                          ARBURST_IS11;
   reg [1:0]                          ARLOCK_IS11;
   reg [3:0]                          ARCACHE_IS11;
   reg [2:0]                          ARPROT_IS11;
   reg                                ARVALID_IS11;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS12;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS12;
   reg [3:0]                          ARLEN_IS12;
   reg [2:0]                          ARSIZE_IS12;
   reg [1:0]                          ARBURST_IS12;
   reg [1:0]                          ARLOCK_IS12;
   reg [3:0]                          ARCACHE_IS12;
   reg [2:0]                          ARPROT_IS12;
   reg                                ARVALID_IS12;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS13;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS13;
   reg [3:0]                          ARLEN_IS13;
   reg [2:0]                          ARSIZE_IS13;
   reg [1:0]                          ARBURST_IS13;
   reg [1:0]                          ARLOCK_IS13;
   reg [3:0]                          ARCACHE_IS13;
   reg [2:0]                          ARPROT_IS13;
   reg                                ARVALID_IS13;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS14;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS14;
   reg [3:0]                          ARLEN_IS14;
   reg [2:0]                          ARSIZE_IS14;
   reg [1:0]                          ARBURST_IS14;
   reg [1:0]                          ARLOCK_IS14;
   reg [3:0]                          ARCACHE_IS14;
   reg [2:0]                          ARPROT_IS14;
   reg                                ARVALID_IS14;
   
   reg [BASE_ID_WIDTH+ID_WIDTH - 1:0] ARID_IS15;
   reg [AXI_AWIDTH-1:0]               ARADDR_IS15;
   reg [3:0]                          ARLEN_IS15;
   reg [2:0]                          ARSIZE_IS15;
   reg [1:0]                          ARBURST_IS15;
   reg [1:0]                          ARLOCK_IS15;
   reg [3:0]                          ARCACHE_IS15;
   reg [2:0]                          ARPROT_IS15;
   reg                                ARVALID_IS15;

   reg [15:0]               SLAVE_SELECT_WADDRCH_M_r;
   reg [15:0]               SLAVE_SELECT_WDCH_M_r;
   reg [15:0]               SLAVE_SELECT_RADDRCH_M_r;


   /////////////////////////////////////////////////////////////////////////////
   //                               Start - of - Code                         //
   /////////////////////////////////////////////////////////////////////////////

   //---------------------------------------------------------------------------
   // Generate the Slave select signal for Write address based on the AWVALID and
   // AWADDR coming from the Master stage
   //---------------------------------------------------------------------------
    always @ (*) begin
        case ({1'b1,AWADDR_MI[AXI_AWIDTH - 1:AXI_AWIDTH-4]})
            5'h10 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_0; end
            5'h11 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_1; end
            5'h12 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_2; end
            5'h13 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_3; end
            5'h14 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_4; end
            5'h15 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_5; end
            5'h16 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_6; end
            5'h17 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_7; end
            5'h18 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_8; end
            5'h19 : begin SLAVE_SELECT_WADDRCH_M = SLAVE_9; end
            5'h1A : begin SLAVE_SELECT_WADDRCH_M = SLAVE_A; end
            5'h1B : begin SLAVE_SELECT_WADDRCH_M = SLAVE_B; end
            5'h1C : begin SLAVE_SELECT_WADDRCH_M = SLAVE_C; end
            5'h1D : begin SLAVE_SELECT_WADDRCH_M = SLAVE_D; end
            5'h1E : begin SLAVE_SELECT_WADDRCH_M = SLAVE_E; end
            5'h1F : begin SLAVE_SELECT_WADDRCH_M = SLAVE_F; end
            default : begin SLAVE_SELECT_WADDRCH_M = SLAVE_SELECT_WADDRCH_M_r; end
        endcase
    end

   //---------------------------------------------------------------------------
   // Select the AWREADY from the slave to which the address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_WADDRCH_M)
            SLAVE_0 : begin AWREADY_IM_int = AWREADY_S0_I; end
            SLAVE_1 : begin AWREADY_IM_int = AWREADY_S1_I; end
            SLAVE_2 : begin AWREADY_IM_int = AWREADY_S2_I; end
            SLAVE_3 : begin AWREADY_IM_int = AWREADY_S3_I; end
            SLAVE_4 : begin AWREADY_IM_int = AWREADY_S4_I; end
            SLAVE_5 : begin AWREADY_IM_int = AWREADY_S5_I; end
            SLAVE_6 : begin AWREADY_IM_int = AWREADY_S6_I; end
            SLAVE_7 : begin AWREADY_IM_int = AWREADY_S7_I; end
            SLAVE_8 : begin AWREADY_IM_int = AWREADY_S8_I; end
            SLAVE_9 : begin AWREADY_IM_int = AWREADY_S9_I; end
            SLAVE_A : begin AWREADY_IM_int = AWREADY_S10_I; end
            SLAVE_B : begin AWREADY_IM_int = AWREADY_S11_I; end
            SLAVE_C : begin AWREADY_IM_int = AWREADY_S12_I; end
            SLAVE_D : begin AWREADY_IM_int = AWREADY_S13_I; end
            SLAVE_E : begin AWREADY_IM_int = AWREADY_S14_I; end
            SLAVE_F : begin AWREADY_IM_int = AWREADY_S15_I; end
            default : begin AWREADY_IM_int = 1'b1; end
        endcase
    end
   
   //---------------------------------------------------------------------------
   // Generate the Slave select signal for Read address based on the ARVALID and
   // ARADDR coming from the Master stage
   //---------------------------------------------------------------------------
    always @ (*) begin
        case ({1'b1,araddr_buf[AXI_AWIDTH - 1:AXI_AWIDTH-4]})
            5'h10 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_0; end
            5'h11 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_1; end
            5'h12 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_2; end
            5'h13 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_3; end
            5'h14 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_4; end
            5'h15 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_5; end
            5'h16 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_6; end
            5'h17 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_7; end
            5'h18 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_8; end
            5'h19 : begin SLAVE_SELECT_RADDRCH_M = SLAVE_9; end
            5'h1A : begin SLAVE_SELECT_RADDRCH_M = SLAVE_A; end
            5'h1B : begin SLAVE_SELECT_RADDRCH_M = SLAVE_B; end
            5'h1C : begin SLAVE_SELECT_RADDRCH_M = SLAVE_C; end
            5'h1D : begin SLAVE_SELECT_RADDRCH_M = SLAVE_D; end
            5'h1E : begin SLAVE_SELECT_RADDRCH_M = SLAVE_E; end
            5'h1F : begin SLAVE_SELECT_RADDRCH_M = SLAVE_F; end
            default : begin SLAVE_SELECT_RADDRCH_M = SLAVE_SELECT_RADDRCH_M_r; end
        endcase
    end

   //---------------------------------------------------------------------------
   // Select the ARREADY from the slave to which the address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_RADDRCH_M)
            SLAVE_0 : begin ARREADY_IM_int = ARREADY_S0_I; end
            SLAVE_1 : begin ARREADY_IM_int = ARREADY_S1_I; end
            SLAVE_2 : begin ARREADY_IM_int = ARREADY_S2_I; end
            SLAVE_3 : begin ARREADY_IM_int = ARREADY_S3_I; end
            SLAVE_4 : begin ARREADY_IM_int = ARREADY_S4_I; end
            SLAVE_5 : begin ARREADY_IM_int = ARREADY_S5_I; end
            SLAVE_6 : begin ARREADY_IM_int = ARREADY_S6_I; end
            SLAVE_7 : begin ARREADY_IM_int = ARREADY_S7_I; end
            SLAVE_8 : begin ARREADY_IM_int = ARREADY_S8_I; end
            SLAVE_9 : begin ARREADY_IM_int = ARREADY_S9_I; end
            SLAVE_A : begin ARREADY_IM_int = ARREADY_S10_I; end
            SLAVE_B : begin ARREADY_IM_int = ARREADY_S11_I; end
            SLAVE_C : begin ARREADY_IM_int = ARREADY_S12_I; end
            SLAVE_D : begin ARREADY_IM_int = ARREADY_S13_I; end
            SLAVE_E : begin ARREADY_IM_int = ARREADY_S14_I; end
            SLAVE_F : begin ARREADY_IM_int = ARREADY_S15_I; end
            default : begin ARREADY_IM_int = 1'b1; end
        endcase
    end   

   // Pass the Write data channel signals
   always @(*) begin
         WID_MI_r         = WID_MI;
         WVALID_MI_r      = WVALID_MI;
         WLAST_MI_r       = WLAST_MI;
         WSTRB_MI_r       = WSTRB_MI;
         WDATA_MI_r       = WDATA_MI;
         BREADY_MI_r      = BREADY_MI;
         RREADY_MI_r      = RREADY_MI;
   end

   // Latch Write data channel signals
   always @(posedge ACLK or negedge ARESETN) begin
      if(!ARESETN) begin
	 SLAVE_SELECT_WADDRCH_M_r  <=  16'h0000;
	 SLAVE_SELECT_WDCH_M_r     <=  16'h0000;
	 SLAVE_SELECT_RADDRCH_M_r  <=  16'h0000;
      end
      else begin
	 SLAVE_SELECT_WADDRCH_M_r  <= SLAVE_SELECT_WADDRCH_M;
	 SLAVE_SELECT_WDCH_M_r     <= SLAVE_SELECT_WDCH_M;
	 SLAVE_SELECT_RADDRCH_M_r  <= SLAVE_SELECT_RADDRCH_M;
      end
   end
   
   // Write address channel selection based on the Slave address

  always @(*) begin
     case(SLAVE_SELECT_WADDRCH_M)
            SLAVE_0 : begin 
               AWADDR_IS0  = AWADDR_MI; 
               AWID_IS0    = AWID_MI; 
               AWVALID_IS0 = AWVALID_MI; 
               AWLEN_IS0   = AWLEN_MI; 
               AWBURST_IS0 = AWBURST_MI; 
               AWSIZE_IS0  = AWSIZE_MI; 
               AWPROT_IS0  = AWPROT_MI; 
               AWCACHE_IS0 = AWCACHE_MI; 
               AWLOCK_IS0  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS1    = 1'b0; 
               AWVALID_IS1 = 1'b0; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS2    = 1'b0; 
               AWVALID_IS2 = 1'b0; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS3    = 1'b0; 
               AWVALID_IS3 = 1'b0; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS4    = 1'b0; 
               AWVALID_IS4 = 1'b0; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS5    = 1'b0; 
               AWVALID_IS5 = 1'b0; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS6    = 1'b0; 
               AWVALID_IS6 = 1'b0; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS7    = 1'b0; 
               AWVALID_IS7 = 1'b0; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS8    = 1'b0; 
               AWVALID_IS8 = 1'b0; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS9    = 1'b0; 
               AWVALID_IS9 = 1'b0; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS10    = 1'b0; 
               AWVALID_IS10 = 1'b0; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS11    = 1'b0; 
               AWVALID_IS11 = 1'b0; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS12    = 1'b0; 
               AWVALID_IS12 = 1'b0; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS13    = 1'b0; 
               AWVALID_IS13 = 1'b0; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS14    = 1'b0; 
               AWVALID_IS14 = 1'b0; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWID_IS15    = 1'b0; 
               AWVALID_IS15 = 1'b0; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;
   
            end

            SLAVE_1 : begin 
               AWADDR_IS1  = AWADDR_MI; 
               AWVALID_IS1 = AWVALID_MI; 
               AWID_IS1    = AWID_MI; 
               AWLEN_IS1   = AWLEN_MI; 
               AWBURST_IS1 = AWBURST_MI; 
               AWSIZE_IS1  = AWSIZE_MI; 
               AWPROT_IS1  = AWPROT_MI; 
               AWCACHE_IS1 = AWCACHE_MI; 
               AWLOCK_IS1  = AWLOCK_MI;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end


            SLAVE_2 : begin 
               AWADDR_IS2  = AWADDR_MI; 
               AWVALID_IS2 = AWVALID_MI; 
               AWID_IS2    = AWID_MI; 
               AWLEN_IS2   = AWLEN_MI; 
               AWBURST_IS2 = AWBURST_MI; 
               AWSIZE_IS2  = AWSIZE_MI; 
               AWPROT_IS2  = AWPROT_MI; 
               AWCACHE_IS2 = AWCACHE_MI; 
               AWLOCK_IS2  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;


            end

            SLAVE_3 : begin 
               AWADDR_IS3  = AWADDR_MI; 
               AWVALID_IS3 = AWVALID_MI; 
               AWID_IS3    = AWID_MI; 
               AWLEN_IS3   = AWLEN_MI; 
               AWBURST_IS3 = AWBURST_MI; 
               AWSIZE_IS3  = AWSIZE_MI; 
               AWPROT_IS3  = AWPROT_MI; 
               AWCACHE_IS3 = AWCACHE_MI; 
               AWLOCK_IS3  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;


            end

            SLAVE_4 : begin 
               AWADDR_IS4  = AWADDR_MI; 
               AWVALID_IS4 = AWVALID_MI; 
               AWID_IS4    = AWID_MI; 
               AWLEN_IS4   = AWLEN_MI; 
               AWBURST_IS4 = AWBURST_MI; 
               AWSIZE_IS4  = AWSIZE_MI; 
               AWPROT_IS4  = AWPROT_MI; 
               AWCACHE_IS4 = AWCACHE_MI; 
               AWLOCK_IS4  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_5 : begin 
               AWADDR_IS5  = AWADDR_MI; 
               AWVALID_IS5 = AWVALID_MI; 
               AWID_IS5    = AWID_MI; 
               AWLEN_IS5   = AWLEN_MI; 
               AWBURST_IS5 = AWBURST_MI; 
               AWSIZE_IS5  = AWSIZE_MI; 
               AWPROT_IS5  = AWPROT_MI; 
               AWCACHE_IS5 = AWCACHE_MI; 
               AWLOCK_IS5  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;


            end

            SLAVE_6 : begin 
               AWADDR_IS6  = AWADDR_MI; 
               AWVALID_IS6 = AWVALID_MI; 
               AWID_IS6    = AWID_MI; 
               AWLEN_IS6   = AWLEN_MI; 
               AWBURST_IS6 = AWBURST_MI; 
               AWSIZE_IS6  = AWSIZE_MI; 
               AWPROT_IS6  = AWPROT_MI; 
               AWCACHE_IS6 = AWCACHE_MI; 
               AWLOCK_IS6  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_7 : begin 
               AWADDR_IS7  = AWADDR_MI; 
               AWVALID_IS7 = AWVALID_MI; 
               AWID_IS7    = AWID_MI; 
               AWLEN_IS7   = AWLEN_MI; 
               AWBURST_IS7 = AWBURST_MI; 
               AWSIZE_IS7  = AWSIZE_MI; 
               AWPROT_IS7  = AWPROT_MI; 
               AWCACHE_IS7 = AWCACHE_MI; 
               AWLOCK_IS7  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_8 : begin 
               AWADDR_IS8  = AWADDR_MI; 
               AWVALID_IS8 = AWVALID_MI; 
               AWID_IS8    = AWID_MI; 
               AWLEN_IS8   = AWLEN_MI; 
               AWBURST_IS8 = AWBURST_MI; 
               AWSIZE_IS8  = AWSIZE_MI; 
               AWPROT_IS8  = AWPROT_MI; 
               AWCACHE_IS8 = AWCACHE_MI; 
               AWLOCK_IS8  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_9 : begin 
               AWADDR_IS9  = AWADDR_MI; 
               AWVALID_IS9 = AWVALID_MI; 
               AWID_IS9    = AWID_MI; 
               AWLEN_IS9   = AWLEN_MI; 
               AWBURST_IS9 = AWBURST_MI; 
               AWSIZE_IS9  = AWSIZE_MI; 
               AWPROT_IS9  = AWPROT_MI; 
               AWCACHE_IS9 = AWCACHE_MI; 
               AWLOCK_IS9  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_A : begin 
               AWADDR_IS10  = AWADDR_MI; 
               AWVALID_IS10 = AWVALID_MI; 
               AWID_IS10    = AWID_MI; 
               AWLEN_IS10   = AWLEN_MI; 
               AWBURST_IS10 = AWBURST_MI; 
               AWSIZE_IS10  = AWSIZE_MI; 
               AWPROT_IS10  = AWPROT_MI; 
               AWCACHE_IS10 = AWCACHE_MI; 
               AWLOCK_IS10  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_B : begin 
               AWADDR_IS11  = AWADDR_MI; 
               AWVALID_IS11 = AWVALID_MI; 
               AWID_IS11    = AWID_MI; 
               AWLEN_IS11   = AWLEN_MI; 
               AWBURST_IS11 = AWBURST_MI; 
               AWSIZE_IS11  = AWSIZE_MI; 
               AWPROT_IS11  = AWPROT_MI; 
               AWCACHE_IS11 = AWCACHE_MI; 
               AWLOCK_IS11  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_C : begin 
               AWADDR_IS12  = AWADDR_MI; 
               AWVALID_IS12 = AWVALID_MI; 
               AWID_IS12    = AWID_MI; 
               AWLEN_IS12   = AWLEN_MI; 
               AWBURST_IS12 = AWBURST_MI; 
               AWSIZE_IS12  = AWSIZE_MI; 
               AWPROT_IS12  = AWPROT_MI; 
               AWCACHE_IS12 = AWCACHE_MI; 
               AWLOCK_IS12  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_D : begin 
               AWADDR_IS13  = AWADDR_MI; 
               AWVALID_IS13 = AWVALID_MI; 
               AWID_IS13    = AWID_MI; 
               AWLEN_IS13   = AWLEN_MI; 
               AWBURST_IS13 = AWBURST_MI; 
               AWSIZE_IS13  = AWSIZE_MI; 
               AWPROT_IS13  = AWPROT_MI; 
               AWCACHE_IS13 = AWCACHE_MI; 
               AWLOCK_IS13  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_E : begin 
               AWADDR_IS14  = AWADDR_MI; 
               AWVALID_IS14 = AWVALID_MI; 
               AWID_IS14    = AWID_MI; 
               AWLEN_IS14   = AWLEN_MI; 
               AWBURST_IS14 = AWBURST_MI; 
               AWSIZE_IS14  = AWSIZE_MI; 
               AWPROT_IS14  = AWPROT_MI; 
               AWCACHE_IS14 = AWCACHE_MI; 
               AWLOCK_IS14  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

            end

            SLAVE_F : begin 
               AWADDR_IS15  = AWADDR_MI; 
               AWVALID_IS15 = AWVALID_MI; 
               AWID_IS15    = AWID_MI; 
               AWLEN_IS15   = AWLEN_MI; 
               AWBURST_IS15 = AWBURST_MI; 
               AWSIZE_IS15  = AWSIZE_MI; 
               AWPROT_IS15  = AWPROT_MI; 
               AWCACHE_IS15 = AWCACHE_MI; 
               AWLOCK_IS15  = AWLOCK_MI;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS1 = 1'b0; 
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS1   = 4'b0000; 
               AWBURST_IS1 = 2'b00; 
               AWSIZE_IS1  = 3'b000; 
               AWPROT_IS1  = 3'b000; 
               AWCACHE_IS1 = 4'b0000; 
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS0 = 1'b0; 
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS0   = 4'b0000; 
               AWBURST_IS0 = 2'b00; 
               AWSIZE_IS0  = 3'b000; 
               AWPROT_IS0  = 3'b000; 
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

            end
       default: begin
               AWADDR_IS0  = {AXI_AWIDTH{1'b0}};
               AWVALID_IS0 = 1'b0;
               AWID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               AWLEN_IS0   = 4'b0000;
               AWBURST_IS0 = 2'b00;
               AWSIZE_IS0  = 3'b000;
               AWPROT_IS0  = 3'b000;
               AWCACHE_IS0 = 4'b0000; 
               AWLOCK_IS0  = 2'b00;

               AWADDR_IS1  = {AXI_AWIDTH{1'b0}};
               AWVALID_IS1 = 1'b0;
               AWID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               AWLEN_IS1   = 4'b0000;
               AWBURST_IS1 = 2'b00;
               AWSIZE_IS1  = 3'b000;
               AWPROT_IS1  = 3'b000;
               AWCACHE_IS1 = 4'b0000;
               AWLOCK_IS1  = 2'b00;

               AWADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS2 = 1'b0; 
               AWID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS2   = 4'b0000; 
               AWBURST_IS2 = 2'b00; 
               AWSIZE_IS2  = 3'b000; 
               AWPROT_IS2  = 3'b000; 
               AWCACHE_IS2 = 4'b0000; 
               AWLOCK_IS2  = 2'b00;

               AWADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS3 = 1'b0; 
               AWID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS3   = 4'b0000; 
               AWBURST_IS3 = 2'b00; 
               AWSIZE_IS3  = 3'b000; 
               AWPROT_IS3  = 3'b000; 
               AWCACHE_IS3 = 4'b0000; 
               AWLOCK_IS3  = 2'b00;

               AWADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS4 = 1'b0; 
               AWID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS4   = 4'b0000; 
               AWBURST_IS4 = 2'b00; 
               AWSIZE_IS4  = 3'b000; 
               AWPROT_IS4  = 3'b000; 
               AWCACHE_IS4 = 4'b0000; 
               AWLOCK_IS4  = 2'b00;

               AWADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS5 = 1'b0; 
               AWID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS5   = 4'b0000; 
               AWBURST_IS5 = 2'b00; 
               AWSIZE_IS5  = 3'b000; 
               AWPROT_IS5  = 3'b000; 
               AWCACHE_IS5 = 4'b0000; 
               AWLOCK_IS5  = 2'b00;

               AWADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS6 = 1'b0; 
               AWID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS6   = 4'b0000; 
               AWBURST_IS6 = 2'b00; 
               AWSIZE_IS6  = 3'b000; 
               AWPROT_IS6  = 3'b000; 
               AWCACHE_IS6 = 4'b0000; 
               AWLOCK_IS6  = 2'b00;

               AWADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS7 = 1'b0; 
               AWID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS7   = 4'b0000; 
               AWBURST_IS7 = 2'b00; 
               AWSIZE_IS7  = 3'b000; 
               AWPROT_IS7  = 3'b000; 
               AWCACHE_IS7 = 4'b0000; 
               AWLOCK_IS7  = 2'b00;

               AWADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS8 = 1'b0; 
               AWID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS8   = 4'b0000; 
               AWBURST_IS8 = 2'b00; 
               AWSIZE_IS8  = 3'b000; 
               AWPROT_IS8  = 3'b000; 
               AWCACHE_IS8 = 4'b0000; 
               AWLOCK_IS8  = 2'b00;

               AWADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS9 = 1'b0; 
               AWID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS9   = 4'b0000; 
               AWBURST_IS9 = 2'b00; 
               AWSIZE_IS9  = 3'b000; 
               AWPROT_IS9  = 3'b000; 
               AWCACHE_IS9 = 4'b0000; 
               AWLOCK_IS9  = 2'b00;

               AWADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS10 = 1'b0; 
               AWID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS10   = 4'b0000; 
               AWBURST_IS10 = 2'b00; 
               AWSIZE_IS10  = 3'b000; 
               AWPROT_IS10  = 3'b000; 
               AWCACHE_IS10 = 4'b0000; 
               AWLOCK_IS10  = 2'b00;

               AWADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS11 = 1'b0; 
               AWID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS11   = 4'b0000; 
               AWBURST_IS11 = 2'b00; 
               AWSIZE_IS11  = 3'b000; 
               AWPROT_IS11  = 3'b000; 
               AWCACHE_IS11 = 4'b0000; 
               AWLOCK_IS11  = 2'b00;

               AWADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS12 = 1'b0; 
               AWID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS12   = 4'b0000; 
               AWBURST_IS12 = 2'b00; 
               AWSIZE_IS12  = 3'b000; 
               AWPROT_IS12  = 3'b000; 
               AWCACHE_IS12 = 4'b0000; 
               AWLOCK_IS12  = 2'b00;

               AWADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS13 = 1'b0; 
               AWID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS13   = 4'b0000; 
               AWBURST_IS13 = 2'b00; 
               AWSIZE_IS13  = 3'b000; 
               AWPROT_IS13  = 3'b000; 
               AWCACHE_IS13 = 4'b0000; 
               AWLOCK_IS13  = 2'b00;

               AWADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS14 = 1'b0; 
               AWID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS14   = 4'b0000; 
               AWBURST_IS14 = 2'b00; 
               AWSIZE_IS14  = 3'b000; 
               AWPROT_IS14  = 3'b000; 
               AWCACHE_IS14 = 4'b0000; 
               AWLOCK_IS14  = 2'b00;

               AWADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               AWVALID_IS15 = 1'b0; 
               AWID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               AWLEN_IS15   = 4'b0000; 
               AWBURST_IS15 = 2'b00; 
               AWSIZE_IS15  = 3'b000; 
               AWPROT_IS15  = 3'b000; 
               AWCACHE_IS15 = 4'b0000; 
               AWLOCK_IS15  = 2'b00;

       end
     endcase // case (SLAVE_SELECT_WADDRCH_M)
  end // always @ (*)
   

  always @(*) begin
     case(SLAVE_SELECT_WDCH_M)
     //case(SLAVE_SELECT_WADDRCH_M)
            SLAVE_0 : begin  
               WID_IS0    = WID_MI_r;
               WVALID_IS0 = WVALID_MI_r; 
               WLAST_IS0  = WLAST_MI_r; 
               WSTRB_IS0  = WSTRB_MI_r; 
               WDATA_IS0  = WDATA_MI_r; 

               WID_IS1  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS1 = 1'b0; 
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS1  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_1 : begin 
               WID_IS1    = WID_MI_r;        //SAR#48894
               WVALID_IS1 = WVALID_MI_r; 
               WLAST_IS1  = WLAST_MI_r; 
               WSTRB_IS1  = WSTRB_MI_r; 
               WDATA_IS1  = WDATA_MI_r; 

               WID_IS0  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_2 : begin 
               WID_IS2    = WID_MI_r;     //SAR#48894
               WVALID_IS2 = WVALID_MI_r; 
               WLAST_IS2  = WLAST_MI_r; 
               WSTRB_IS2  = WSTRB_MI_r; 
               WDATA_IS2  = WDATA_MI_r; 

               WID_IS0  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               //WID_IS1    = 1'b0; 
               WID_IS1  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS1 = 1'b0; 
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS1  = {AXI_DWIDTH{1'b0}}; 

               //WID_IS3    = 1'b0;
               WID_IS3  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               //WID_IS4    = 1'b0;
               WID_IS4  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               //WID_IS5    = 1'b0;
               WID_IS5  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               //WID_IS6    = 1'b0;
               WID_IS6  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               //WID_IS7    = 1'b0;
               WID_IS7  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               //WID_IS8    = 1'b0;
               WID_IS8  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               //WID_IS9    = 1'b0;
               WID_IS9  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               //WID_IS10    = 1'b0;
               WID_IS10  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               //WID_IS11    = 1'b0;
               WID_IS11  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               //WID_IS12    = 1'b0;
               WID_IS12  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               //WID_IS13    = 1'b0;
               WID_IS13  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               //WID_IS14    = 1'b0;
               WID_IS14  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               //WID_IS15    = 1'b0;
               WID_IS15  = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_3 : begin                     //SAR#48894
               WID_IS3    = WID_MI_r; 
               WVALID_IS3 = WVALID_MI_r; 
               WLAST_IS3  = WLAST_MI_r; 
               WSTRB_IS3  = WSTRB_MI_r; 
               WDATA_IS3  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_4 : begin 
               WID_IS4    = WID_MI_r;     //SAR#48894
               WVALID_IS4 = WVALID_MI_r; 
               WLAST_IS4  = WLAST_MI_r; 
               WSTRB_IS4  = WSTRB_MI_r; 
               WDATA_IS4  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_5 : begin 
               WID_IS5    = WID_MI_r;     //SAR#48894
               WVALID_IS5 = WVALID_MI_r; 
               WLAST_IS5  = WLAST_MI_r; 
               WSTRB_IS5  = WSTRB_MI_r; 
               WDATA_IS5  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_6 : begin 
               WID_IS6    = WID_MI_r;     //SAR#48894
               WVALID_IS6 = WVALID_MI_r; 
               WLAST_IS6  = WLAST_MI_r; 
               WSTRB_IS6  = WSTRB_MI_r; 
               WDATA_IS6  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_7 : begin 
               WID_IS7    = WID_MI_r;       //SAR#48894
               WVALID_IS7 = WVALID_MI_r; 
               WLAST_IS7  = WLAST_MI_r; 
               WSTRB_IS7  = WSTRB_MI_r; 
               WDATA_IS7  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_8 : begin 
               WID_IS8    = WID_MI_r;      //SAR#48894
               WVALID_IS8 = WVALID_MI_r; 
               WLAST_IS8  = WLAST_MI_r; 
               WSTRB_IS8  = WSTRB_MI_r; 
               WDATA_IS8  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_9 : begin 
               WID_IS9    = WID_MI_r;     //SAR#48894
               WVALID_IS9 = WVALID_MI_r; 
               WLAST_IS9  = WLAST_MI_r; 
               WSTRB_IS9  = WSTRB_MI_r; 
               WDATA_IS9  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_A : begin 
               WID_IS10    = WID_MI_r;     //SAR#48894
               WVALID_IS10 = WVALID_MI_r; 
               WLAST_IS10  = WLAST_MI_r; 
               WSTRB_IS10  = WSTRB_MI_r; 
               WDATA_IS10  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_B : begin 
               WID_IS11    = WID_MI_r;     //SAR#48894
               WVALID_IS11 = WVALID_MI_r; 
               WLAST_IS11  = WLAST_MI_r; 
               WSTRB_IS11  = WSTRB_MI_r; 
               WDATA_IS11  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_C : begin 
               WID_IS12    = WID_MI_r;     //SAR#48894
               WVALID_IS12 = WVALID_MI_r; 
               WLAST_IS12  = WLAST_MI_r; 
               WSTRB_IS12  = WSTRB_MI_r; 
               WDATA_IS12  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_D : begin 
               WID_IS13    = WID_MI_r;     //SAR#48894
               WVALID_IS13 = WVALID_MI_r; 
               WLAST_IS13  = WLAST_MI_r; 
               WSTRB_IS13  = WSTRB_MI_r; 
               WDATA_IS13  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_E : begin 
               WID_IS14    = WID_MI_r;     //SAR#48894
               WVALID_IS14 = WVALID_MI_r; 
               WLAST_IS14  = WLAST_MI_r; 
               WSTRB_IS14  = WSTRB_MI_r; 
               WDATA_IS14  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

            SLAVE_F : begin 
               WID_IS15    = WID_MI_r;     //SAR#48894
               WVALID_IS15 = WVALID_MI_r; 
               WLAST_IS15  = WLAST_MI_r; 
               WSTRB_IS15  = WSTRB_MI_r; 
               WDATA_IS15  = WDATA_MI_r; 

               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS1 = 1'b0;
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS1  = {AXI_DWIDTH{1'b0}};
            end

            default : begin 
               WID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS0 = 1'b0; 
               WLAST_IS0  = 1'b0; 
               WSTRB_IS0  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS0  = {AXI_DWIDTH{1'b0}}; 

               WID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS1 = 1'b0; 
               WLAST_IS1  = 1'b0; 
               WSTRB_IS1  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS1  = {AXI_DWIDTH{1'b0}}; 

               WID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               WVALID_IS2 = 1'b0; 
               WLAST_IS2  = 1'b0; 
               WSTRB_IS2  = {AXI_STRBWIDTH{1'b0}}; 
               WDATA_IS2  = {AXI_DWIDTH{1'b0}}; 

               WID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS3 = 1'b0;
               WLAST_IS3  = 1'b0; 
               WSTRB_IS3  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS3  = {AXI_DWIDTH{1'b0}};
               
               WID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS4 = 1'b0;
               WLAST_IS4  = 1'b0; 
               WSTRB_IS4  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS4  = {AXI_DWIDTH{1'b0}};

               WID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS5 = 1'b0;
               WLAST_IS5  = 1'b0; 
               WSTRB_IS5  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS5  = {AXI_DWIDTH{1'b0}};

               WID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS6 = 1'b0;
               WLAST_IS6  = 1'b0; 
               WSTRB_IS6  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS6  = {AXI_DWIDTH{1'b0}};

               WID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS7 = 1'b0;
               WLAST_IS7  = 1'b0; 
               WSTRB_IS7  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS7  = {AXI_DWIDTH{1'b0}};

               WID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS8 = 1'b0;
               WLAST_IS8  = 1'b0; 
               WSTRB_IS8  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS8  = {AXI_DWIDTH{1'b0}};

               WID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS9 = 1'b0;
               WLAST_IS9  = 1'b0; 
               WSTRB_IS9  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS9  = {AXI_DWIDTH{1'b0}};

               WID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS10 = 1'b0;
               WLAST_IS10  = 1'b0; 
               WSTRB_IS10  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS10  = {AXI_DWIDTH{1'b0}};

               WID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS11 = 1'b0;
               WLAST_IS11  = 1'b0; 
               WSTRB_IS11  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS11  = {AXI_DWIDTH{1'b0}};

               WID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS12 = 1'b0;
               WLAST_IS12  = 1'b0; 
               WSTRB_IS12  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS12  = {AXI_DWIDTH{1'b0}};

               WID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS13 = 1'b0;
               WLAST_IS13  = 1'b0; 
               WSTRB_IS13  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS13  = {AXI_DWIDTH{1'b0}};

               WID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS14 = 1'b0;
               WLAST_IS14  = 1'b0; 
               WSTRB_IS14  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS14  = {AXI_DWIDTH{1'b0}};

               WID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               WVALID_IS15 = 1'b0;
               WLAST_IS15  = 1'b0; 
               WSTRB_IS15  = {AXI_STRBWIDTH{1'b0}};
               WDATA_IS15  = {AXI_DWIDTH{1'b0}};
            end

     endcase // case (SLAVE_SELECT_WDCH_M)
  end // always @ (*)   


   // Read address channel selection based on the Slave address
  always @(*) begin
     case(SLAVE_SELECT_RADDRCH_M)
            SLAVE_0 : begin 
               ARADDR_IS0  = ARADDR_MI; 
               ARID_IS0    = ARID_MI; 
               ARVALID_IS0 = ARVALID_MI; 
               ARLEN_IS0   = ARLEN_MI; 
               ARBURST_IS0 = ARBURST_MI; 
               ARSIZE_IS0  = ARSIZE_MI; 
               ARPROT_IS0  = ARPROT_MI; 
               ARCACHE_IS0 = ARCACHE_MI; 
               ARLOCK_IS0  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;
   
            end

            SLAVE_1 : begin 
               ARADDR_IS1  = ARADDR_MI; 
               ARVALID_IS1 = ARVALID_MI; 
               ARID_IS1    = ARID_MI; 
               ARLEN_IS1   = ARLEN_MI; 
               ARBURST_IS1 = ARBURST_MI; 
               ARSIZE_IS1  = ARSIZE_MI; 
               ARPROT_IS1  = ARPROT_MI; 
               ARCACHE_IS1 = ARCACHE_MI; 
               ARLOCK_IS1  = ARLOCK_MI;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end


            SLAVE_2 : begin 
               ARADDR_IS2  = ARADDR_MI; 
               ARVALID_IS2 = ARVALID_MI; 
               ARID_IS2    = ARID_MI; 
               ARLEN_IS2   = ARLEN_MI; 
               ARBURST_IS2 = ARBURST_MI; 
               ARSIZE_IS2  = ARSIZE_MI; 
               ARPROT_IS2  = ARPROT_MI; 
               ARCACHE_IS2 = ARCACHE_MI; 
               ARLOCK_IS2  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;


            end

            SLAVE_3 : begin 
               ARADDR_IS3  = ARADDR_MI; 
               ARVALID_IS3 = ARVALID_MI; 
               ARID_IS3    = ARID_MI; 
               ARLEN_IS3   = ARLEN_MI; 
               ARBURST_IS3 = ARBURST_MI; 
               ARSIZE_IS3  = ARSIZE_MI; 
               ARPROT_IS3  = ARPROT_MI; 
               ARCACHE_IS3 = ARCACHE_MI; 
               ARLOCK_IS3  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;


            end

            SLAVE_4 : begin 
               ARADDR_IS4  = ARADDR_MI; 
               ARVALID_IS4 = ARVALID_MI; 
               ARID_IS4    = ARID_MI; 
               ARLEN_IS4   = ARLEN_MI; 
               ARBURST_IS4 = ARBURST_MI; 
               ARSIZE_IS4  = ARSIZE_MI; 
               ARPROT_IS4  = ARPROT_MI; 
               ARCACHE_IS4 = ARCACHE_MI; 
               ARLOCK_IS4  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_5 : begin 
               ARADDR_IS5  = ARADDR_MI; 
               ARVALID_IS5 = ARVALID_MI; 
               ARID_IS5    = ARID_MI; 
               ARLEN_IS5   = ARLEN_MI; 
               ARBURST_IS5 = ARBURST_MI; 
               ARSIZE_IS5  = ARSIZE_MI; 
               ARPROT_IS5  = ARPROT_MI; 
               ARCACHE_IS5 = ARCACHE_MI; 
               ARLOCK_IS5  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;


            end

            SLAVE_6 : begin 
               ARADDR_IS6  = ARADDR_MI; 
               ARVALID_IS6 = ARVALID_MI; 
               ARID_IS6    = ARID_MI; 
               ARLEN_IS6   = ARLEN_MI; 
               ARBURST_IS6 = ARBURST_MI; 
               ARSIZE_IS6  = ARSIZE_MI; 
               ARPROT_IS6  = ARPROT_MI; 
               ARCACHE_IS6 = ARCACHE_MI; 
               ARLOCK_IS6  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_7 : begin 
               ARADDR_IS7  = ARADDR_MI; 
               ARVALID_IS7 = ARVALID_MI; 
               ARID_IS7    = ARID_MI; 
               ARLEN_IS7   = ARLEN_MI; 
               ARBURST_IS7 = ARBURST_MI; 
               ARSIZE_IS7  = ARSIZE_MI; 
               ARPROT_IS7  = ARPROT_MI; 
               ARCACHE_IS7 = ARCACHE_MI; 
               ARLOCK_IS7  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_8 : begin 
               ARADDR_IS8  = ARADDR_MI; 
               ARVALID_IS8 = ARVALID_MI; 
               ARID_IS8    = ARID_MI; 
               ARLEN_IS8   = ARLEN_MI; 
               ARBURST_IS8 = ARBURST_MI; 
               ARSIZE_IS8  = ARSIZE_MI; 
               ARPROT_IS8  = ARPROT_MI; 
               ARCACHE_IS8 = ARCACHE_MI; 
               ARLOCK_IS8  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_9 : begin 
               ARADDR_IS9  = ARADDR_MI; 
               ARVALID_IS9 = ARVALID_MI; 
               ARID_IS9    = ARID_MI; 
               ARLEN_IS9   = ARLEN_MI; 
               ARBURST_IS9 = ARBURST_MI; 
               ARSIZE_IS9  = ARSIZE_MI; 
               ARPROT_IS9  = ARPROT_MI; 
               ARCACHE_IS9 = ARCACHE_MI; 
               ARLOCK_IS9  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_A : begin 
               ARADDR_IS10  = ARADDR_MI; 
               ARVALID_IS10 = ARVALID_MI; 
               ARID_IS10    = ARID_MI; 
               ARLEN_IS10   = ARLEN_MI; 
               ARBURST_IS10 = ARBURST_MI; 
               ARSIZE_IS10  = ARSIZE_MI; 
               ARPROT_IS10  = ARPROT_MI; 
               ARCACHE_IS10 = ARCACHE_MI; 
               ARLOCK_IS10  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_B : begin 
               ARADDR_IS11  = ARADDR_MI; 
               ARVALID_IS11 = ARVALID_MI; 
               ARID_IS11    = ARID_MI; 
               ARLEN_IS11   = ARLEN_MI; 
               ARBURST_IS11 = ARBURST_MI; 
               ARSIZE_IS11  = ARSIZE_MI; 
               ARPROT_IS11  = ARPROT_MI; 
               ARCACHE_IS11 = ARCACHE_MI; 
               ARLOCK_IS11  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_C : begin 
               ARADDR_IS12  = ARADDR_MI; 
               ARVALID_IS12 = ARVALID_MI; 
               ARID_IS12    = ARID_MI; 
               ARLEN_IS12   = ARLEN_MI; 
               ARBURST_IS12 = ARBURST_MI; 
               ARSIZE_IS12  = ARSIZE_MI; 
               ARPROT_IS12  = ARPROT_MI; 
               ARCACHE_IS12 = ARCACHE_MI; 
               ARLOCK_IS12  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_D : begin 
               ARADDR_IS13  = ARADDR_MI; 
               ARVALID_IS13 = ARVALID_MI; 
               ARID_IS13    = ARID_MI; 
               ARLEN_IS13   = ARLEN_MI; 
               ARBURST_IS13 = ARBURST_MI; 
               ARSIZE_IS13  = ARSIZE_MI; 
               ARPROT_IS13  = ARPROT_MI; 
               ARCACHE_IS13 = ARCACHE_MI; 
               ARLOCK_IS13  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_E : begin 
               ARADDR_IS14  = ARADDR_MI; 
               ARVALID_IS14 = ARVALID_MI; 
               ARID_IS14    = ARID_MI; 
               ARLEN_IS14   = ARLEN_MI; 
               ARBURST_IS14 = ARBURST_MI; 
               ARSIZE_IS14  = ARSIZE_MI; 
               ARPROT_IS14  = ARPROT_MI; 
               ARCACHE_IS14 = ARCACHE_MI; 
               ARLOCK_IS14  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

            end

            SLAVE_F : begin 
               ARADDR_IS15  = ARADDR_MI; 
               ARVALID_IS15 = ARVALID_MI; 
               ARID_IS15    = ARID_MI; 
               ARLEN_IS15   = ARLEN_MI; 
               ARBURST_IS15 = ARBURST_MI; 
               ARSIZE_IS15  = ARSIZE_MI; 
               ARPROT_IS15  = ARPROT_MI; 
               ARCACHE_IS15 = ARCACHE_MI; 
               ARLOCK_IS15  = ARLOCK_MI;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS1 = 1'b0; 
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS1   = 4'b0000; 
               ARBURST_IS1 = 2'b00; 
               ARSIZE_IS1  = 3'b000; 
               ARPROT_IS1  = 3'b000; 
               ARCACHE_IS1 = 4'b0000; 
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS0  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS0 = 1'b0; 
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS0   = 4'b0000; 
               ARBURST_IS0 = 2'b00; 
               ARSIZE_IS0  = 3'b000; 
               ARPROT_IS0  = 3'b000; 
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

            end
       default: begin
               ARADDR_IS0  = {AXI_AWIDTH{1'b0}};
               ARVALID_IS0 = 1'b0;
               ARID_IS0    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               ARLEN_IS0   = 4'b0000;
               ARBURST_IS0 = 2'b00;
               ARSIZE_IS0  = 3'b000;
               ARPROT_IS0  = 3'b000;
               ARCACHE_IS0 = 4'b0000; 
               ARLOCK_IS0  = 2'b00;

               ARADDR_IS1  = {AXI_AWIDTH{1'b0}};
               ARVALID_IS1 = 1'b0;
               ARID_IS1    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}};
               ARLEN_IS1   = 4'b0000;
               ARBURST_IS1 = 2'b00;
               ARSIZE_IS1  = 3'b000;
               ARPROT_IS1  = 3'b000;
               ARCACHE_IS1 = 4'b0000;
               ARLOCK_IS1  = 2'b00;

               ARADDR_IS2  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS2 = 1'b0; 
               ARID_IS2    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS2   = 4'b0000; 
               ARBURST_IS2 = 2'b00; 
               ARSIZE_IS2  = 3'b000; 
               ARPROT_IS2  = 3'b000; 
               ARCACHE_IS2 = 4'b0000; 
               ARLOCK_IS2  = 2'b00;

               ARADDR_IS3  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS3 = 1'b0; 
               ARID_IS3    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS3   = 4'b0000; 
               ARBURST_IS3 = 2'b00; 
               ARSIZE_IS3  = 3'b000; 
               ARPROT_IS3  = 3'b000; 
               ARCACHE_IS3 = 4'b0000; 
               ARLOCK_IS3  = 2'b00;

               ARADDR_IS4  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS4 = 1'b0; 
               ARID_IS4    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS4   = 4'b0000; 
               ARBURST_IS4 = 2'b00; 
               ARSIZE_IS4  = 3'b000; 
               ARPROT_IS4  = 3'b000; 
               ARCACHE_IS4 = 4'b0000; 
               ARLOCK_IS4  = 2'b00;

               ARADDR_IS5  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS5 = 1'b0; 
               ARID_IS5    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS5   = 4'b0000; 
               ARBURST_IS5 = 2'b00; 
               ARSIZE_IS5  = 3'b000; 
               ARPROT_IS5  = 3'b000; 
               ARCACHE_IS5 = 4'b0000; 
               ARLOCK_IS5  = 2'b00;

               ARADDR_IS6  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS6 = 1'b0; 
               ARID_IS6    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS6   = 4'b0000; 
               ARBURST_IS6 = 2'b00; 
               ARSIZE_IS6  = 3'b000; 
               ARPROT_IS6  = 3'b000; 
               ARCACHE_IS6 = 4'b0000; 
               ARLOCK_IS6  = 2'b00;

               ARADDR_IS7  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS7 = 1'b0; 
               ARID_IS7    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS7   = 4'b0000; 
               ARBURST_IS7 = 2'b00; 
               ARSIZE_IS7  = 3'b000; 
               ARPROT_IS7  = 3'b000; 
               ARCACHE_IS7 = 4'b0000; 
               ARLOCK_IS7  = 2'b00;

               ARADDR_IS8  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS8 = 1'b0; 
               ARID_IS8    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS8   = 4'b0000; 
               ARBURST_IS8 = 2'b00; 
               ARSIZE_IS8  = 3'b000; 
               ARPROT_IS8  = 3'b000; 
               ARCACHE_IS8 = 4'b0000; 
               ARLOCK_IS8  = 2'b00;

               ARADDR_IS9  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS9 = 1'b0; 
               ARID_IS9    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS9   = 4'b0000; 
               ARBURST_IS9 = 2'b00; 
               ARSIZE_IS9  = 3'b000; 
               ARPROT_IS9  = 3'b000; 
               ARCACHE_IS9 = 4'b0000; 
               ARLOCK_IS9  = 2'b00;

               ARADDR_IS10  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS10 = 1'b0; 
               ARID_IS10    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS10   = 4'b0000; 
               ARBURST_IS10 = 2'b00; 
               ARSIZE_IS10  = 3'b000; 
               ARPROT_IS10  = 3'b000; 
               ARCACHE_IS10 = 4'b0000; 
               ARLOCK_IS10  = 2'b00;

               ARADDR_IS11  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS11 = 1'b0; 
               ARID_IS11    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS11   = 4'b0000; 
               ARBURST_IS11 = 2'b00; 
               ARSIZE_IS11  = 3'b000; 
               ARPROT_IS11  = 3'b000; 
               ARCACHE_IS11 = 4'b0000; 
               ARLOCK_IS11  = 2'b00;

               ARADDR_IS12  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS12 = 1'b0; 
               ARID_IS12    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS12   = 4'b0000; 
               ARBURST_IS12 = 2'b00; 
               ARSIZE_IS12  = 3'b000; 
               ARPROT_IS12  = 3'b000; 
               ARCACHE_IS12 = 4'b0000; 
               ARLOCK_IS12  = 2'b00;

               ARADDR_IS13  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS13 = 1'b0; 
               ARID_IS13    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS13   = 4'b0000; 
               ARBURST_IS13 = 2'b00; 
               ARSIZE_IS13  = 3'b000; 
               ARPROT_IS13  = 3'b000; 
               ARCACHE_IS13 = 4'b0000; 
               ARLOCK_IS13  = 2'b00;

               ARADDR_IS14  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS14 = 1'b0; 
               ARID_IS14    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS14   = 4'b0000; 
               ARBURST_IS14 = 2'b00; 
               ARSIZE_IS14  = 3'b000; 
               ARPROT_IS14  = 3'b000; 
               ARCACHE_IS14 = 4'b0000; 
               ARLOCK_IS14  = 2'b00;

               ARADDR_IS15  = {AXI_AWIDTH{1'b0}}; 
               ARVALID_IS15 = 1'b0; 
               ARID_IS15    = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; 
               ARLEN_IS15   = 4'b0000; 
               ARBURST_IS15 = 2'b00; 
               ARSIZE_IS15  = 3'b000; 
               ARPROT_IS15  = 3'b000; 
               ARCACHE_IS15 = 4'b0000; 
               ARLOCK_IS15  = 2'b00;

       end
     endcase // case (SLAVE_SELECT_RADDRCH_M)
  end // always @ (*)

   // Select the BREADY from the Master going to the respective slave based on the select line
   always @(*) begin
               BREADY_IS0 = BREADY_MI_r;
               BREADY_IS1 = BREADY_MI_r;
               BREADY_IS2 = BREADY_MI_r;
               BREADY_IS3 = BREADY_MI_r;
               BREADY_IS4 = BREADY_MI_r;
               BREADY_IS5 = BREADY_MI_r;
               BREADY_IS6 = BREADY_MI_r;
               BREADY_IS7 = BREADY_MI_r;
               BREADY_IS8 = BREADY_MI_r;
               BREADY_IS9 = BREADY_MI_r;
               BREADY_IS10 = BREADY_MI_r;
               BREADY_IS11 = BREADY_MI_r;
               BREADY_IS12 = BREADY_MI_r;
               BREADY_IS13 = BREADY_MI_r;
               BREADY_IS14 = BREADY_MI_r;
               BREADY_IS15 = BREADY_MI_r;
   end
      
   always @(posedge ACLK or negedge ARESETN) begin
      if(!ARESETN) begin
         addr_for_wready      <= {AXI_AWIDTH{1'b0}};
      end
      else begin
         addr_for_wready   <= awaddr_buf;
      end // else: !if(!ARESETN)
   end // always @ (posedge ACLK or negedge ARESETN)

   // Select the RREADY from the Master going to the respective slave based on the select line
   always @(*) begin
      case(SLAVE_SELECT_RDCH_M)
            SLAVE_0 : begin 
               RREADY_IS0 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_1 : begin 
               RREADY_IS1 = RREADY_MI_r;
               RREADY_IS0 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_2 : begin 
               RREADY_IS2 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_3 : begin 
               RREADY_IS3 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_4 : begin 
               RREADY_IS4 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_5 : begin 
               RREADY_IS5 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_6 : begin 
               RREADY_IS6 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_7 : begin 
               RREADY_IS7 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_8 : begin 
               RREADY_IS8 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_9 : begin 
               RREADY_IS9 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_A : begin 
               RREADY_IS10 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS0 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_B : begin 
               RREADY_IS11 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS0  = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_C : begin 
               RREADY_IS12 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS0  = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_D : begin 
               RREADY_IS13 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS0  = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_E : begin 
               RREADY_IS14 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS0  = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
            SLAVE_F : begin 
               RREADY_IS15 = RREADY_MI_r;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS0  = 1'b0;
            end
       
            default : begin 
               RREADY_IS0 = 1'b0;
               RREADY_IS1 = 1'b0;
               RREADY_IS2 = 1'b0;
               RREADY_IS3 = 1'b0;
               RREADY_IS4 = 1'b0;
               RREADY_IS5 = 1'b0;
               RREADY_IS6 = 1'b0;
               RREADY_IS7 = 1'b0;
               RREADY_IS8 = 1'b0;
               RREADY_IS9 = 1'b0;
               RREADY_IS10 = 1'b0;
               RREADY_IS11 = 1'b0;
               RREADY_IS12 = 1'b0;
               RREADY_IS13 = 1'b0;
               RREADY_IS14 = 1'b0;
               RREADY_IS15 = 1'b0;
            end
       
     endcase // case (SLAVE_SELECT_RDRESPCH_M)
  end

   always @(posedge ACLK or negedge ARESETN) begin
      if(!ARESETN) begin
         addr_for_rready   <= {AXI_AWIDTH{1'b0}};
      end
      else begin
         addr_for_rready   <= araddr_buf;
      end // else: !if(!ARESETN)
   end // always @ (posedge ACLK or negedge ARESETN)
                  
   //---------------------------------------------------------------------------
   // Generate the Slave select signal for Write data channel to select
   // corresponding WREADY from the respective slave
   //---------------------------------------------------------------------------
    always @ (*) begin
        //case ({WVALID_MI_r,awaddr_buf[AXI_AWIDTH-1:AXI_AWIDTH-4]}) 
        case (awaddr_buf[AXI_AWIDTH-1:AXI_AWIDTH-4])  //SAR#48894
            4'h0 : begin SLAVE_SELECT_WDCH_M = SLAVE_0; end
            4'h1 : begin SLAVE_SELECT_WDCH_M = SLAVE_1; end
            4'h2 : begin SLAVE_SELECT_WDCH_M = SLAVE_2; end
            4'h3 : begin SLAVE_SELECT_WDCH_M = SLAVE_3; end
            4'h4 : begin SLAVE_SELECT_WDCH_M = SLAVE_4; end
            4'h5 : begin SLAVE_SELECT_WDCH_M = SLAVE_5; end
            4'h6 : begin SLAVE_SELECT_WDCH_M = SLAVE_6; end
            4'h7 : begin SLAVE_SELECT_WDCH_M = SLAVE_7; end
            4'h8 : begin SLAVE_SELECT_WDCH_M = SLAVE_8; end
            4'h9 : begin SLAVE_SELECT_WDCH_M = SLAVE_9; end
            4'hA : begin SLAVE_SELECT_WDCH_M = SLAVE_A; end
            4'hB : begin SLAVE_SELECT_WDCH_M = SLAVE_B; end
            4'hC : begin SLAVE_SELECT_WDCH_M = SLAVE_C; end
            4'hD : begin SLAVE_SELECT_WDCH_M = SLAVE_D; end
            4'hE : begin SLAVE_SELECT_WDCH_M = SLAVE_E; end
            4'hF : begin SLAVE_SELECT_WDCH_M = SLAVE_F; end
            default : begin SLAVE_SELECT_WDCH_M = SLAVE_SELECT_WDCH_M_r; end
        endcase
    end

   //---------------------------------------------------------------------------
   // Select the WREADY from the slave to which write address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_WDCH_M)
            SLAVE_0 : begin WREADY_IM_int = WREADY_S0_I; end
            SLAVE_1 : begin WREADY_IM_int = WREADY_S1_I; end
            SLAVE_2 : begin WREADY_IM_int = WREADY_S2_I; end
            SLAVE_3 : begin WREADY_IM_int = WREADY_S3_I; end
            SLAVE_4 : begin WREADY_IM_int = WREADY_S4_I; end
            SLAVE_5 : begin WREADY_IM_int = WREADY_S5_I; end
            SLAVE_6 : begin WREADY_IM_int = WREADY_S6_I; end
            SLAVE_7 : begin WREADY_IM_int = WREADY_S7_I; end
            SLAVE_8 : begin WREADY_IM_int = WREADY_S8_I; end
            SLAVE_9 : begin WREADY_IM_int = WREADY_S9_I; end
            SLAVE_A : begin WREADY_IM_int = WREADY_S10_I; end
            SLAVE_B : begin WREADY_IM_int = WREADY_S11_I; end
            SLAVE_C : begin WREADY_IM_int = WREADY_S12_I; end
            SLAVE_D : begin WREADY_IM_int = WREADY_S13_I; end
            SLAVE_E : begin WREADY_IM_int = WREADY_S14_I; end
            SLAVE_F : begin WREADY_IM_int = WREADY_S15_I; end
            default : begin WREADY_IM_int = 1'b1; end
        endcase
    end


   //---------------------------------------------------------------------------
   // Generate the Slave select signal for Write response channel to select
   // corresponding BVALID from the respective slave
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (addr_for_wready[AXI_AWIDTH-1:AXI_AWIDTH-4])
            4'h0 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_0; end
            4'h1 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_1; end
            4'h2 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_2; end
            4'h3 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_3; end
            4'h4 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_4; end
            4'h5 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_5; end
            4'h6 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_6; end
            4'h7 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_7; end
            4'h8 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_8; end
            4'h9 : begin SLAVE_SELECT_WRESPCH_M = SLAVE_9; end
            4'hA : begin SLAVE_SELECT_WRESPCH_M = SLAVE_A; end
            4'hB : begin SLAVE_SELECT_WRESPCH_M = SLAVE_B; end
            4'hC : begin SLAVE_SELECT_WRESPCH_M = SLAVE_C; end
            4'hD : begin SLAVE_SELECT_WRESPCH_M = SLAVE_D; end
            4'hE : begin SLAVE_SELECT_WRESPCH_M = SLAVE_E; end
            4'hF : begin SLAVE_SELECT_WRESPCH_M = SLAVE_F; end
            default : begin SLAVE_SELECT_WRESPCH_M = 16'h0000; end
        endcase
    end

   //---------------------------------------------------------------------------
   // Select the BVALID from the slave to which write address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_WRESPCH_M)
            SLAVE_0 : begin BVALID_IM_int = BVALID_S0_I; end
            SLAVE_1 : begin BVALID_IM_int = BVALID_S1_I; end
            SLAVE_2 : begin BVALID_IM_int = BVALID_S2_I; end
            SLAVE_3 : begin BVALID_IM_int = BVALID_S3_I; end
            SLAVE_4 : begin BVALID_IM_int = BVALID_S4_I; end
            SLAVE_5 : begin BVALID_IM_int = BVALID_S5_I; end
            SLAVE_6 : begin BVALID_IM_int = BVALID_S6_I; end
            SLAVE_7 : begin BVALID_IM_int = BVALID_S7_I; end
            SLAVE_8 : begin BVALID_IM_int = BVALID_S8_I; end
            SLAVE_9 : begin BVALID_IM_int = BVALID_S9_I; end
            SLAVE_A : begin BVALID_IM_int = BVALID_S10_I; end
            SLAVE_B : begin BVALID_IM_int = BVALID_S11_I; end
            SLAVE_C : begin BVALID_IM_int = BVALID_S12_I; end
            SLAVE_D : begin BVALID_IM_int = BVALID_S13_I; end
            SLAVE_E : begin BVALID_IM_int = BVALID_S14_I; end
            SLAVE_F : begin BVALID_IM_int = BVALID_S15_I; end
            default : begin BVALID_IM_int = 1'b0; end
        endcase
    end


   //---------------------------------------------------------------------------
   // Select the BRESP from the slave to which write address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_WRESPCH_M)
            SLAVE_0 : begin BRESP_IM_int = BRESP_S0_I; end
            SLAVE_1 : begin BRESP_IM_int = BRESP_S1_I; end
            SLAVE_2 : begin BRESP_IM_int = BRESP_S2_I; end
            SLAVE_3 : begin BRESP_IM_int = BRESP_S3_I; end
            SLAVE_4 : begin BRESP_IM_int = BRESP_S4_I; end
            SLAVE_5 : begin BRESP_IM_int = BRESP_S5_I; end
            SLAVE_6 : begin BRESP_IM_int = BRESP_S6_I; end
            SLAVE_7 : begin BRESP_IM_int = BRESP_S7_I; end
            SLAVE_8 : begin BRESP_IM_int = BRESP_S8_I; end
            SLAVE_9 : begin BRESP_IM_int = BRESP_S9_I; end
            SLAVE_A : begin BRESP_IM_int = BRESP_S10_I; end
            SLAVE_B : begin BRESP_IM_int = BRESP_S11_I; end
            SLAVE_C : begin BRESP_IM_int = BRESP_S12_I; end
            SLAVE_D : begin BRESP_IM_int = BRESP_S13_I; end
            SLAVE_E : begin BRESP_IM_int = BRESP_S14_I; end
            SLAVE_F : begin BRESP_IM_int = BRESP_S15_I; end
            default : begin BRESP_IM_int = 2'b00; end
        endcase
    end

   //---------------------------------------------------------------------------
   // Select the BID from the slave to which write address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_WRESPCH_M)
            SLAVE_0 : begin BID_IM_int = BID_S0_I; end
            SLAVE_1 : begin BID_IM_int = BID_S1_I; end
            SLAVE_2 : begin BID_IM_int = BID_S2_I; end
            SLAVE_3 : begin BID_IM_int = BID_S3_I; end
            SLAVE_4 : begin BID_IM_int = BID_S4_I; end
            SLAVE_5 : begin BID_IM_int = BID_S5_I; end
            SLAVE_6 : begin BID_IM_int = BID_S6_I; end
            SLAVE_7 : begin BID_IM_int = BID_S7_I; end
            SLAVE_8 : begin BID_IM_int = BID_S8_I; end
            SLAVE_9 : begin BID_IM_int = BID_S9_I; end
            SLAVE_A : begin BID_IM_int = BID_S10_I; end
            SLAVE_B : begin BID_IM_int = BID_S11_I; end
            SLAVE_C : begin BID_IM_int = BID_S12_I; end
            SLAVE_D : begin BID_IM_int = BID_S13_I; end
            SLAVE_E : begin BID_IM_int = BID_S14_I; end
            SLAVE_F : begin BID_IM_int = BID_S15_I; end
            default : begin BID_IM_int = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; end
        endcase
    end


   //---------------------------------------------------------------------------
   // Generate the Slave select signal for Read channel to select
   // corresponding RVALID from the respective slave
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (addr_for_rready[AXI_AWIDTH-1:AXI_AWIDTH-4])
            4'h0 : begin SLAVE_SELECT_RDCH_M = SLAVE_0; end
            4'h1 : begin SLAVE_SELECT_RDCH_M = SLAVE_1; end
            4'h2 : begin SLAVE_SELECT_RDCH_M = SLAVE_2; end
            4'h3 : begin SLAVE_SELECT_RDCH_M = SLAVE_3; end
            4'h4 : begin SLAVE_SELECT_RDCH_M = SLAVE_4; end
            4'h5 : begin SLAVE_SELECT_RDCH_M = SLAVE_5; end
            4'h6 : begin SLAVE_SELECT_RDCH_M = SLAVE_6; end
            4'h7 : begin SLAVE_SELECT_RDCH_M = SLAVE_7; end
            4'h8 : begin SLAVE_SELECT_RDCH_M = SLAVE_8; end
            4'h9 : begin SLAVE_SELECT_RDCH_M = SLAVE_9; end
            4'hA : begin SLAVE_SELECT_RDCH_M = SLAVE_A; end
            4'hB : begin SLAVE_SELECT_RDCH_M = SLAVE_B; end
            4'hC : begin SLAVE_SELECT_RDCH_M = SLAVE_C; end
            4'hD : begin SLAVE_SELECT_RDCH_M = SLAVE_D; end
            4'hE : begin SLAVE_SELECT_RDCH_M = SLAVE_E; end
            4'hF : begin SLAVE_SELECT_RDCH_M = SLAVE_F; end
            default : begin SLAVE_SELECT_RDCH_M = 16'h0000; end
        endcase
    end

   //---------------------------------------------------------------------------
   // Select the BVALID from the slave to which write address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_RDCH_M)
            SLAVE_0 : begin RVALID_IM_int = RVALID_S0_I; end
            SLAVE_1 : begin RVALID_IM_int = RVALID_S1_I; end
            SLAVE_2 : begin RVALID_IM_int = RVALID_S2_I; end
            SLAVE_3 : begin RVALID_IM_int = RVALID_S3_I; end
            SLAVE_4 : begin RVALID_IM_int = RVALID_S4_I; end
            SLAVE_5 : begin RVALID_IM_int = RVALID_S5_I; end
            SLAVE_6 : begin RVALID_IM_int = RVALID_S6_I; end
            SLAVE_7 : begin RVALID_IM_int = RVALID_S7_I; end
            SLAVE_8 : begin RVALID_IM_int = RVALID_S8_I; end
            SLAVE_9 : begin RVALID_IM_int = RVALID_S9_I; end
            SLAVE_A : begin RVALID_IM_int = RVALID_S10_I; end
            SLAVE_B : begin RVALID_IM_int = RVALID_S11_I; end
            SLAVE_C : begin RVALID_IM_int = RVALID_S12_I; end
            SLAVE_D : begin RVALID_IM_int = RVALID_S13_I; end
            SLAVE_E : begin RVALID_IM_int = RVALID_S14_I; end
            SLAVE_F : begin RVALID_IM_int = RVALID_S15_I; end
            default : begin RVALID_IM_int = 1'b0; end
        endcase
    end


   //---------------------------------------------------------------------------
   // Select the BRESP from the slave to which write address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_RDCH_M)
            SLAVE_0 : begin RRESP_IM_int = RRESP_S0_I; end
            SLAVE_1 : begin RRESP_IM_int = RRESP_S1_I; end
            SLAVE_2 : begin RRESP_IM_int = RRESP_S2_I; end
            SLAVE_3 : begin RRESP_IM_int = RRESP_S3_I; end
            SLAVE_4 : begin RRESP_IM_int = RRESP_S4_I; end
            SLAVE_5 : begin RRESP_IM_int = RRESP_S5_I; end
            SLAVE_6 : begin RRESP_IM_int = RRESP_S6_I; end
            SLAVE_7 : begin RRESP_IM_int = RRESP_S7_I; end
            SLAVE_8 : begin RRESP_IM_int = RRESP_S8_I; end
            SLAVE_9 : begin RRESP_IM_int = RRESP_S9_I; end
            SLAVE_A : begin RRESP_IM_int = RRESP_S10_I; end
            SLAVE_B : begin RRESP_IM_int = RRESP_S11_I; end
            SLAVE_C : begin RRESP_IM_int = RRESP_S12_I; end
            SLAVE_D : begin RRESP_IM_int = RRESP_S13_I; end
            SLAVE_E : begin RRESP_IM_int = RRESP_S14_I; end
            SLAVE_F : begin RRESP_IM_int = RRESP_S15_I; end
            default : begin RRESP_IM_int = 2'b00; end
        endcase
    end

   //---------------------------------------------------------------------------
   // Select the RID from the slave to which read address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_RDCH_M)
            SLAVE_0 : begin RID_IM_int = RID_S0_I; end
            SLAVE_1 : begin RID_IM_int = RID_S1_I; end
            SLAVE_2 : begin RID_IM_int = RID_S2_I; end
            SLAVE_3 : begin RID_IM_int = RID_S3_I; end
            SLAVE_4 : begin RID_IM_int = RID_S4_I; end
            SLAVE_5 : begin RID_IM_int = RID_S5_I; end
            SLAVE_6 : begin RID_IM_int = RID_S6_I; end
            SLAVE_7 : begin RID_IM_int = RID_S7_I; end
            SLAVE_8 : begin RID_IM_int = RID_S8_I; end
            SLAVE_9 : begin RID_IM_int = RID_S9_I; end
            SLAVE_A : begin RID_IM_int = RID_S10_I; end
            SLAVE_B : begin RID_IM_int = RID_S11_I; end
            SLAVE_C : begin RID_IM_int = RID_S12_I; end
            SLAVE_D : begin RID_IM_int = RID_S13_I; end
            SLAVE_E : begin RID_IM_int = RID_S14_I; end
            SLAVE_F : begin RID_IM_int = RID_S15_I; end
            default : begin RID_IM_int = {(BASE_ID_WIDTH+ID_WIDTH){1'b0}}; end
        endcase
    end

   //---------------------------------------------------------------------------
   // Select the RLAST from the slave to which read address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_RDCH_M)
            SLAVE_0 : begin RLAST_IM_int = RLAST_S0_I; end
            SLAVE_1 : begin RLAST_IM_int = RLAST_S1_I; end
            SLAVE_2 : begin RLAST_IM_int = RLAST_S2_I; end
            SLAVE_3 : begin RLAST_IM_int = RLAST_S3_I; end
            SLAVE_4 : begin RLAST_IM_int = RLAST_S4_I; end
            SLAVE_5 : begin RLAST_IM_int = RLAST_S5_I; end
            SLAVE_6 : begin RLAST_IM_int = RLAST_S6_I; end
            SLAVE_7 : begin RLAST_IM_int = RLAST_S7_I; end
            SLAVE_8 : begin RLAST_IM_int = RLAST_S8_I; end
            SLAVE_9 : begin RLAST_IM_int = RLAST_S9_I; end
            SLAVE_A : begin RLAST_IM_int = RLAST_S10_I; end
            SLAVE_B : begin RLAST_IM_int = RLAST_S11_I; end
            SLAVE_C : begin RLAST_IM_int = RLAST_S12_I; end
            SLAVE_D : begin RLAST_IM_int = RLAST_S13_I; end
            SLAVE_E : begin RLAST_IM_int = RLAST_S14_I; end
            SLAVE_F : begin RLAST_IM_int = RLAST_S15_I; end
            default : begin RLAST_IM_int = 1'b0; end
        endcase
    end
   
   //---------------------------------------------------------------------------
   // Select the RDATA from the slave to which read address is addressed to.
   //---------------------------------------------------------------------------
    always @ (*) begin
        case (SLAVE_SELECT_RDCH_M)
            SLAVE_0 : begin RDATA_IM_int = RDATA_S0_I; end
            SLAVE_1 : begin RDATA_IM_int = RDATA_S1_I; end
            SLAVE_2 : begin RDATA_IM_int = RDATA_S2_I; end
            SLAVE_3 : begin RDATA_IM_int = RDATA_S3_I; end
            SLAVE_4 : begin RDATA_IM_int = RDATA_S4_I; end
            SLAVE_5 : begin RDATA_IM_int = RDATA_S5_I; end
            SLAVE_6 : begin RDATA_IM_int = RDATA_S6_I; end
            SLAVE_7 : begin RDATA_IM_int = RDATA_S7_I; end
            SLAVE_8 : begin RDATA_IM_int = RDATA_S8_I; end
            SLAVE_9 : begin RDATA_IM_int = RDATA_S9_I; end
            SLAVE_A : begin RDATA_IM_int = RDATA_S10_I; end
            SLAVE_B : begin RDATA_IM_int = RDATA_S11_I; end
            SLAVE_C : begin RDATA_IM_int = RDATA_S12_I; end
            SLAVE_D : begin RDATA_IM_int = RDATA_S13_I; end
            SLAVE_E : begin RDATA_IM_int = RDATA_S14_I; end
            SLAVE_F : begin RDATA_IM_int = RDATA_S15_I; end
            default : begin RDATA_IM_int = {AXI_DWIDTH{1'b0}}; end
        endcase // case (SLAVE_SELECT_RDCH_M)       
    end

   always @(*) begin
      WREADY_IM       <= WREADY_IM_int;
      AWREADY_IM      <= AWREADY_IM_int;
      ARREADY_IM      <= ARREADY_IM_int;
   end

   // Latch the READY signal before passing to the Master stage        
   always @(*) begin
         BID_IM          = BID_IM_int;
         BVALID_IM       = BVALID_IM_int;
         BRESP_IM        = BRESP_IM_int;

         RID_IM          = RID_IM_int;
         RVALID_IM       = RVALID_IM_int;
         RLAST_IM        = RLAST_IM_int;
         RDATA_IM        = RDATA_IM_int;
         RRESP_IM        = RRESP_IM_int;

   end // always @ (posedge ACLK or negedge ARESETN)


endmodule // axi_interconnect

   /////////////////////////////////////////////////////////////////////////////
   //                               End - of - Code                           //
   /////////////////////////////////////////////////////////////////////////////

