<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.6.0.34</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)</text>
<text>Date: Tue Sep 29 15:06:38 2015
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>MDDR_TA_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>IGLOO2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2GL010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>8.137</cell>
 <cell>122.895</cell>
 <cell>48.193</cell>
 <cell>20.750</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>5.186</cell>
 <cell>192.827</cell>
 <cell>12.048</cell>
 <cell>83.001</cell>
 <cell>-0.992</cell>
 <cell>1.015</cell>
 <cell>5.757</cell>
 <cell>9.514</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>3.043</cell>
 <cell>328.623</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell>6.121</cell>
 <cell>163.372</cell>
 <cell>48.000</cell>
 <cell>20.833</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>0.293</cell>
 <cell>0.249</cell>
 <cell>3.665</cell>
 <cell>3.416</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base:D</cell>
 <cell>0.289</cell>
 <cell>0.255</cell>
 <cell>3.651</cell>
 <cell>3.396</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif3_spll_lock_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif3_spll_lock_q2:D</cell>
 <cell>0.300</cell>
 <cell>0.257</cell>
 <cell>3.671</cell>
 <cell>3.414</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_state[0]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_state[1]:D</cell>
 <cell>0.293</cell>
 <cell>0.258</cell>
 <cell>3.664</cell>
 <cell>3.406</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled_clk_base:D</cell>
 <cell>0.295</cell>
 <cell>0.259</cell>
 <cell>3.675</cell>
 <cell>3.416</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.665</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.416</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.249</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.477</cell>
 <cell>2.477</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.146</cell>
 <cell>2.623</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.725</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.903</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>3.059</cell>
 <cell>31</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.313</cell>
 <cell>3.372</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.426</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif3_core_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.239</cell>
 <cell>3.665</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.665</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.477</cell>
 <cell>2.477</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.146</cell>
 <cell>2.623</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.725</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.903</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>3.059</cell>
 <cell>31</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.357</cell>
 <cell>3.416</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.416</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.416</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell>0.497</cell>
 <cell>0.479</cell>
 <cell>3.868</cell>
 <cell>3.389</cell>
 <cell>0.000</cell>
 <cell>-0.018</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>0.497</cell>
 <cell>0.479</cell>
 <cell>3.868</cell>
 <cell>3.389</cell>
 <cell>0.000</cell>
 <cell>-0.018</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>0.497</cell>
 <cell>0.479</cell>
 <cell>3.868</cell>
 <cell>3.389</cell>
 <cell>0.000</cell>
 <cell>-0.018</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_q1:ALn</cell>
 <cell>0.632</cell>
 <cell>0.592</cell>
 <cell>3.988</cell>
 <cell>3.396</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base:ALn</cell>
 <cell>0.632</cell>
 <cell>0.592</cell>
 <cell>3.988</cell>
 <cell>3.396</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.868</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.389</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.479</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.477</cell>
 <cell>2.477</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.146</cell>
 <cell>2.623</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.725</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.903</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>3.059</cell>
 <cell>31</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.312</cell>
 <cell>3.371</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.425</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.443</cell>
 <cell>3.868</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.868</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.477</cell>
 <cell>2.477</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.146</cell>
 <cell>2.623</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.725</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.903</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>3.059</cell>
 <cell>31</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/mss_ready_select:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.330</cell>
 <cell>3.389</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.389</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.389</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>AXI_IF_0/AWADDR_1[27]:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[27]</cell>
 <cell>0.713</cell>
 <cell>0.937</cell>
 <cell>3.949</cell>
 <cell>3.012</cell>
 <cell>-0.417</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>AXI_IF_0/AWADDR_1[9]:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[9]</cell>
 <cell>0.723</cell>
 <cell>0.990</cell>
 <cell>3.959</cell>
 <cell>2.969</cell>
 <cell>-0.460</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>AXI_IF_0/AWADDR_1[19]:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[19]</cell>
 <cell>0.726</cell>
 <cell>0.991</cell>
 <cell>3.970</cell>
 <cell>2.979</cell>
 <cell>-0.450</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>AXI_IF_0/AWADDR_1[18]:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[18]</cell>
 <cell>0.742</cell>
 <cell>1.007</cell>
 <cell>3.986</cell>
 <cell>2.979</cell>
 <cell>-0.450</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>AXI_IF_0/AWADDR_1[28]:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[28]</cell>
 <cell>0.726</cell>
 <cell>1.011</cell>
 <cell>3.967</cell>
 <cell>2.956</cell>
 <cell>-0.473</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: AXI_IF_0/AWADDR_1[27]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[27]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.949</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.012</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.937</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.350</cell>
 <cell>2.350</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.139</cell>
 <cell>2.489</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.591</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.192</cell>
 <cell>2.783</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.939</cell>
 <cell>75</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/AWADDR_1[27]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.297</cell>
 <cell>3.236</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/AWADDR_1[27]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>3.303</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_209:A</cell>
 <cell>net</cell>
 <cell>AXI_IF_0_BIF_1_AWADDR[27]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.523</cell>
 <cell>3.826</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_209:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.123</cell>
 <cell>3.949</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[27]</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/F_AWADDR_HADDR0_net[27]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.949</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.949</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.477</cell>
 <cell>2.477</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.146</cell>
 <cell>2.623</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.725</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.179</cell>
 <cell>2.904</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>3.060</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.239</cell>
 <cell>3.299</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>3.429</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.429</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_AWADDR_HADDR0[27]</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>-0.417</cell>
 <cell>3.012</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.012</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FIC2_APB_CLK to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>0.485</cell>
 <cell>22.780</cell>
 <cell>2.195</cell>
 <cell>-20.585</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>0.666</cell>
 <cell>22.968</cell>
 <cell>2.384</cell>
 <cell>-20.584</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.195</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-20.585</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>22.780</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.917</cell>
 <cell>0.917</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>1.053</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.189</cell>
 <cell>1.242</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>1.398</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.312</cell>
 <cell>1.710</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>1.777</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0_CONFIG1_DONE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.418</cell>
 <cell>2.195</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.195</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Min Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-24.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.477</cell>
 <cell>-21.523</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.146</cell>
 <cell>-21.377</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>-21.275</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>-21.097</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>-20.941</cell>
 <cell>31</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>-20.585</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-20.585</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-20.585</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COM_Interface_0/Control_Logic_0/DATA_OUT[7]:CLK</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTO1I[7]:D</cell>
 <cell>0.281</cell>
 <cell>0.253</cell>
 <cell>3.541</cell>
 <cell>3.288</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTOIIl[0]:CLK</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTlOl[0]:D</cell>
 <cell>0.297</cell>
 <cell>0.254</cell>
 <cell>3.544</cell>
 <cell>3.290</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>COM_Interface_0/Control_Logic_0/DATA_OUT[0]:CLK</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTO1I[0]:D</cell>
 <cell>0.297</cell>
 <cell>0.262</cell>
 <cell>3.546</cell>
 <cell>3.284</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>COM_Interface_0/Control_Logic_0/DATA_OUT[3]:CLK</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTO1I[3]:D</cell>
 <cell>0.298</cell>
 <cell>0.263</cell>
 <cell>3.547</cell>
 <cell>3.284</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>AXI_IF_0/rt_state[0]:CLK</cell>
 <cell>AXI_IF_0/rt_state[0]:D</cell>
 <cell>0.302</cell>
 <cell>0.267</cell>
 <cell>3.552</cell>
 <cell>3.285</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COM_Interface_0/Control_Logic_0/DATA_OUT[7]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COM_Interface_0/COREUART_0/CUARTO1I[7]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.541</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.288</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.253</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.350</cell>
 <cell>2.350</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.139</cell>
 <cell>2.489</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.591</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.782</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.938</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/Control_Logic_0/DATA_OUT[7]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.322</cell>
 <cell>3.260</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/Control_Logic_0/DATA_OUT[7]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>3.317</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO1I[7]:D</cell>
 <cell>net</cell>
 <cell>COM_Interface_0/Control_Logic_0_DATA_OUT[7]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>3.541</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.541</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.350</cell>
 <cell>2.350</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.139</cell>
 <cell>2.489</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.591</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.782</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.938</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO1I[7]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.350</cell>
 <cell>3.288</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO1I[7]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.288</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.288</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>RX</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D</cell>
 <cell>2.336</cell>
 <cell></cell>
 <cell>2.336</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>1.015</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: RX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.336</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>RX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>RX</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.463</cell>
 <cell>1.463</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>RX_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.463</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>1.515</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D</cell>
 <cell>net</cell>
 <cell>RX_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.821</cell>
 <cell>2.336</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.336</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.350</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.113</cell>
 <cell>N/C</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.210</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB4:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>N/C</cell>
 <cell>34</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB4_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTIO1/CUARTll1:CLK</cell>
 <cell>TX</cell>
 <cell>2.500</cell>
 <cell></cell>
 <cell>5.757</cell>
 <cell></cell>
 <cell>5.757</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COM_Interface_0/COREUART_0/CUARTIO1/CUARTll1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: TX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.757</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.350</cell>
 <cell>2.350</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.139</cell>
 <cell>2.489</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.591</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.782</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.938</cell>
 <cell>54</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTIO1/CUARTll1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>3.257</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTIO1/CUARTll1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.311</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>TX_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>TX_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.743</cell>
 <cell>4.054</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>TX_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.219</cell>
 <cell>4.273</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>TX_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>TX_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.273</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>TX_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.484</cell>
 <cell>5.757</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>TX</cell>
 <cell>net</cell>
 <cell>TX</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.757</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.757</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.350</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>TX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[16]</cell>
 <cell>1.104</cell>
 <cell>1.161</cell>
 <cell>4.533</cell>
 <cell>3.372</cell>
 <cell>0.057</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[3]</cell>
 <cell>1.091</cell>
 <cell>1.169</cell>
 <cell>4.520</cell>
 <cell>3.351</cell>
 <cell>0.036</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[4]</cell>
 <cell>1.103</cell>
 <cell>1.181</cell>
 <cell>4.532</cell>
 <cell>3.351</cell>
 <cell>0.036</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[11]</cell>
 <cell>1.145</cell>
 <cell>1.194</cell>
 <cell>4.574</cell>
 <cell>3.380</cell>
 <cell>0.065</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[0]</cell>
 <cell>1.140</cell>
 <cell>1.205</cell>
 <cell>4.569</cell>
 <cell>3.364</cell>
 <cell>0.049</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[16]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.533</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.372</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.161</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.477</cell>
 <cell>2.477</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.146</cell>
 <cell>2.623</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.725</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.179</cell>
 <cell>2.904</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>3.060</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.239</cell>
 <cell>3.299</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>3.429</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.429</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RDATA_HRDATA01[16]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>0.522</cell>
 <cell>3.951</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/CFG_31:B</cell>
 <cell>net</cell>
 <cell>AXI_IF_0_BIF_1_RDATA[16]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.430</cell>
 <cell>4.381</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/CFG_31:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2_IP_BC</cell>
 <cell>+</cell>
 <cell>0.124</cell>
 <cell>4.505</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[16]</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/B_DIN_net[16]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.028</cell>
 <cell>4.533</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.533</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.350</cell>
 <cell>2.350</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.139</cell>
 <cell>2.489</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.591</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.782</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.938</cell>
 <cell>14</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/FF_24:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.285</cell>
 <cell>3.223</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/FF_24:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLK</cell>
 <cell>+</cell>
 <cell>0.037</cell>
 <cell>3.260</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_CLK</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/B_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>3.315</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[16]</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:RAM1K18_IP</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>3.372</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.372</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:D</cell>
 <cell>0.300</cell>
 <cell>0.266</cell>
 <cell>3.387</cell>
 <cell>3.121</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>0.380</cell>
 <cell>0.333</cell>
 <cell>3.467</cell>
 <cell>3.134</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[6]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[6]:D</cell>
 <cell>0.404</cell>
 <cell>0.369</cell>
 <cell>3.503</cell>
 <cell>3.134</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[3]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[3]:D</cell>
 <cell>0.407</cell>
 <cell>0.373</cell>
 <cell>3.499</cell>
 <cell>3.126</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[8]:EN</cell>
 <cell>0.423</cell>
 <cell>0.387</cell>
 <cell>3.522</cell>
 <cell>3.135</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.387</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.121</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.266</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.277</cell>
 <cell>1.277</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>1.372</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.931</cell>
 <cell>2.303</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>2.439</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.630</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.786</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.301</cell>
 <cell>3.087</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_rcosc_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.141</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_rcosc_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.246</cell>
 <cell>3.387</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.387</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.277</cell>
 <cell>1.277</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>1.372</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.931</cell>
 <cell>2.303</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>2.439</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.630</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.786</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.335</cell>
 <cell>3.121</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.121</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.121</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[2]:ALn</cell>
 <cell>0.403</cell>
 <cell>0.362</cell>
 <cell>3.490</cell>
 <cell>3.128</cell>
 <cell>0.000</cell>
 <cell>-0.041</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[12]:ALn</cell>
 <cell>0.403</cell>
 <cell>0.363</cell>
 <cell>3.490</cell>
 <cell>3.127</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:ALn</cell>
 <cell>0.403</cell>
 <cell>0.363</cell>
 <cell>3.490</cell>
 <cell>3.127</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[0]:ALn</cell>
 <cell>0.403</cell>
 <cell>0.363</cell>
 <cell>3.490</cell>
 <cell>3.127</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1:ALn</cell>
 <cell>0.403</cell>
 <cell>0.369</cell>
 <cell>3.490</cell>
 <cell>3.121</cell>
 <cell>0.000</cell>
 <cell>-0.034</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/count_ddr[2]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.490</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.362</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.277</cell>
 <cell>1.277</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>1.372</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.931</cell>
 <cell>2.303</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>2.439</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.630</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.786</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.301</cell>
 <cell>3.087</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.141</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[2]:ALn</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.349</cell>
 <cell>3.490</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.490</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.277</cell>
 <cell>1.277</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>1.372</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.931</cell>
 <cell>2.303</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>2.439</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.630</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.786</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[2]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.342</cell>
 <cell>3.128</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[2]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_APB_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/state[0]:D</cell>
 <cell>2.134</cell>
 <cell>0.405</cell>
 <cell>2.134</cell>
 <cell>1.729</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/paddr[6]:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[6]</cell>
 <cell>0.559</cell>
 <cell>23.148</cell>
 <cell>2.265</cell>
 <cell>-20.883</cell>
 <cell>1.350</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/paddr[3]:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PADDR[3]</cell>
 <cell>0.562</cell>
 <cell>23.231</cell>
 <cell>2.261</cell>
 <cell>-20.970</cell>
 <cell>1.263</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/pwdata[14]:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MDDR_FABRIC_PWDATA[14]</cell>
 <cell>0.581</cell>
 <cell>23.231</cell>
 <cell>2.287</cell>
 <cell>-20.944</cell>
 <cell>1.289</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/pwdata[11]:D</cell>
 <cell>1.014</cell>
 <cell>23.262</cell>
 <cell>1.014</cell>
 <cell>-22.248</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORECONFIGP_0/state[0]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.134</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>1.729</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.405</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:PER2_FABRIC_PENABLE</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>0.599</cell>
 <cell>0.599</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3_CFG1C_TEST0:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_TMP_0_FIC_2_APB_MASTER_PENABLE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.575</cell>
 <cell>1.174</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3_CFG1C_TEST0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1C_TEST</cell>
 <cell>+</cell>
 <cell>0.129</cell>
 <cell>1.303</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3:B</cell>
 <cell>net</cell>
 <cell>mdr_MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3_CFG1C_TEST_net0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.372</cell>
 <cell>1.675</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.122</cell>
 <cell>1.797</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_a3_0_a2:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/N_42</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.149</cell>
 <cell>1.946</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_a3_0_a2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.146</cell>
 <cell>2.092</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/state[0]:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/state_ns[0]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.042</cell>
 <cell>2.134</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.134</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell>Min Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.917</cell>
 <cell>0.917</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>1.053</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.186</cell>
 <cell>1.239</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>1.395</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/state[0]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.334</cell>
 <cell>1.729</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/state[0]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.729</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.729</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_APB_CLK</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
