<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\synlog\MDDR_TA_top_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock</data>
<data>400.0 MHz</data>
<data>123.4 MHz</data>
<data>-5.603</data>
</row>
<row>
<data>MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock</data>
<data>400.0 MHz</data>
<data>107.4 MHz</data>
<data>-6.815</data>
</row>
<row>
<data>MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock</data>
<data>400.0 MHz</data>
<data>400.2 MHz</data>
<data>0.001</data>
</row>
<row>
<data>MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock</data>
<data>400.0 MHz</data>
<data>161.8 MHz</data>
<data>-3.682</data>
</row>
<row>
<data>System</data>
<data>400.0 MHz</data>
<data>293.1 MHz</data>
<data>-0.912</data>
</row>
</report_table>
