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<doc>
<title>Global Net Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)</text>
<text>Date: Tue Sep 29 15:05:22 2015
</text>
<section>
<name>Global Nets Information</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> GB Location </cell>
 <cell> Net Name </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>GB[3] </cell>
 <cell>(221, 54)</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell>475</cell>
</row>
<row>
 <cell>2</cell>
 <cell>GB[1] </cell>
 <cell>(219, 54)</cell>
 <cell>MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int_RNIPJE6/U0_YNn</cell>
 <cell>443</cell>
</row>
<row>
 <cell>3</cell>
 <cell>GB[0] </cell>
 <cell>(218, 54)</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell>401</cell>
</row>
<row>
 <cell>4</cell>
 <cell>GB[5] </cell>
 <cell>(223, 54)</cell>
 <cell>MDDR_TA_0/CORERESETP_0/INIT_DONE_int_RNIKK5F/U0_YNn</cell>
 <cell>301</cell>
</row>
<row>
 <cell>5</cell>
 <cell>GB[2] </cell>
 <cell>(220, 54)</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST_RNIISCE/U0_YNn</cell>
 <cell>77</cell>
</row>
<row>
 <cell>6</cell>
 <cell>GB[4] </cell>
 <cell>(222, 54)</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_YNn</cell>
 <cell>75</cell>
</row>
<row>
 <cell>7</cell>
 <cell>GB[6] </cell>
 <cell>(224, 54)</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base_RNI4FO6/U0_YNn</cell>
 <cell>20</cell>
</row>
<row>
 <cell>8</cell>
 <cell>GB[7] </cell>
 <cell>(225, 54)</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell>20</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>I/O to GB Connections</name>
<text>(none)</text>
</section>
<section>
<name>Fabric to GB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> To </cell>
 <cell> Net Name </cell>
 <cell> Net Type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:Q</cell>
 <cell>(364, 85)</cell>
 <cell>GB[1] </cell>
 <cell>MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int</cell>
 <cell>ROUTED</cell>
 <cell>2</cell>
</row>
<row>
 <cell>2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/INIT_DONE_int:Q</cell>
 <cell>(306, 85)</cell>
 <cell>GB[5] </cell>
 <cell>MDDR_TA_0/CORERESETP_0/INIT_DONE_int</cell>
 <cell>ROUTED</cell>
 <cell>4</cell>
</row>
<row>
 <cell>3</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CONFIG_PRESET_N</cell>
 <cell>(300, 104)</cell>
 <cell>GB[2] </cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/CONFIG_PRESET_N</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>4</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>(300, 104)</cell>
 <cell>GB[4] </cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base:Q</cell>
 <cell>(363, 85)</cell>
 <cell>GB[6] </cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base_0</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>6</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>(397, 92)</cell>
 <cell>GB[7] </cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>CCC to GB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell>Pin Swapped for Back Annotation Only</cell>
 <cell> To </cell>
 <cell> Net Name </cell>
 <cell> Net Type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>CCC-NE1 (390, 92)</cell>
 <cell>GL0 =&gt; GL3</cell>
 <cell>GB[3] </cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell>HARDWIRED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>2</cell>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>CCC-NE1 (390, 92)</cell>
 <cell>GL2 =&gt; GL0</cell>
 <cell>GB[0] </cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell>HARDWIRED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>CCC Input Connections</name>
<text>(none)</text>
</section>
<section>
<name>Local Clock Nets to RGB Connections</name>
<text>(none)</text>
</section>
</doc>
