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<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)</text>
<text>Date: Tue Sep 29 15:04:19 2015
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>IGLOO2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2GL010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
<row>
 <cell>Restrict SPI Pins</cell>
 <cell>No</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>MDDR_TA_top</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top.edn</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\constraint\MDDR_TA_top_new.sdc</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_new_without_workaround\Libero_Project\MDDR_TA\constraint\io\MDDR_TA_top.io.pdc</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Enable Single Event Transient mitigation</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Enable Design Separation Methodology</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>4LUT</cell>
 <cell>1632</cell>
 <cell>12084</cell>
 <cell>13.51</cell>
</row>
<row>
 <cell>DFF</cell>
 <cell>1071</cell>
 <cell>12084</cell>
 <cell>8.86</cell>
</row>
<row>
 <cell>I/O Register</cell>
 <cell>0</cell>
 <cell>693</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>User I/O</cell>
 <cell>52</cell>
 <cell>231</cell>
 <cell>22.51</cell>
</row>
<row>
 <cell>-- Single-ended I/O</cell>
 <cell>50</cell>
 <cell>231</cell>
 <cell>21.65</cell>
</row>
<row>
 <cell>-- Differential I/O Pairs</cell>
 <cell>1</cell>
 <cell>115</cell>
 <cell>0.87</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>22</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>3</cell>
 <cell>21</cell>
 <cell>14.29</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>0</cell>
 <cell>22</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>Chip Globals</cell>
 <cell>8</cell>
 <cell>8</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>1</cell>
 <cell>2</cell>
 <cell>50.00</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>SERDESIF Blocks</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>-- SERDESIF Lanes</cell>
 <cell>0</cell>
 <cell>4</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>HPMS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Detailed Logic Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>4LUT</cell>
 <cell>DFF</cell>
</header>
<row>
 <cell>Fabric Logic</cell>
 <cell>1524</cell>
 <cell>963</cell>
</row>
<row>
 <cell>RAM64x18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM1K18 Interface Logic</cell>
 <cell>108</cell>
 <cell>108</cell>
</row>
<row>
 <cell>MACC Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Total Used</cell>
 <cell>1632</cell>
 <cell>1071</cell>
</row>
</table>
<section><name>HPMS Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>eNVM (256KB)*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eSRAM*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>SPI</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MDDR</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>HPDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>PDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
</table>
<text>* These resources are always marked as used when you are using the HPMS</text>
<text></text>
<section><name>Detailed Carry Chains Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>6</cell>
 <cell>2</cell>
</row>
<row>
 <cell>9</cell>
 <cell>2</cell>
</row>
<row>
 <cell>10</cell>
 <cell>2</cell>
</row>
<row>
 <cell>12</cell>
 <cell>2</cell>
</row>
<row>
 <cell>14</cell>
 <cell>2</cell>
</row>
<row>
 <cell>15</cell>
 <cell>2</cell>
</row>
<row>
 <cell>16</cell>
 <cell>1</cell>
</row>
<row>
 <cell>17</cell>
 <cell>1</cell>
</row>
<row>
 <cell>26</cell>
 <cell>3</cell>
</row>
<row>
 <cell>30</cell>
 <cell>1</cell>
</row>
<row>
 <cell>32</cell>
 <cell>1</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>19</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>2</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>28</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>20</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vddi</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 1</cell>
 <cell> 1</cell>
 <cell> 0</cell>
</row>
<row>
 <cell>LPDDRI (Input/Bidirectional)</cell>
 <cell> 1.80v</cell>
 <cell> 1.00v</cell>
 <cell> 1</cell>
 <cell> 0</cell>
 <cell> 20</cell>
</row>
<row>
 <cell>LPDDRI (Output)</cell>
 <cell> 1.80v</cell>
 <cell> N/A</cell>
 <cell> 0</cell>
 <cell> 29</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 52</cell>
 <cell>100.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>475</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/GL0_INST</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>443</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/MSS_HPMS_READY_int_RNIPJE6</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int_RNIPJE6/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>401</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0_HPMS_DDR_FIC_SUBSYSTEM_CLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>301</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0_INIT_DONE</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CORERESETP_0/INIT_DONE_int_RNIKK5F/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>77</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/CORECONFIGP_0_APB_S_PRESET_N</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST_RNIISCE/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>75</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/CORECONFIGP_0_APB_S_PCLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>20</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base_RNI4FO6/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>20</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>128</cell>
 <cell>INT_NET</cell>
 <cell>Net   : AXI_IF_0/RVALID_li_reto</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: AXI_IF_0/WDATA_ret_128</cell>
</row>
<row>
 <cell>56</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/state[6]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/state[6]</cell>
</row>
<row>
 <cell>53</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/ConfigMaster_0/N_937</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/un1_state_42_i_a2_0_d_0</cell>
</row>
<row>
 <cell>43</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>39</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/ConfigMaster_0/state[5]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/state[5]</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/N_152</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNIE8PL[0]</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/ConfigMaster_0/state[18]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/state[18]</cell>
</row>
<row>
 <cell>36</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/HREADY_M_pre37</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37</cell>
</row>
<row>
 <cell>35</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/masterDataInProg[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]</cell>
</row>
<row>
 <cell>35</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/ConfigMaster_0/state[20]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/state[20]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>128</cell>
 <cell>INT_NET</cell>
 <cell>Net   : AXI_IF_0/RVALID_li_reto</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: AXI_IF_0/WDATA_ret_128</cell>
</row>
<row>
 <cell>56</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/state[6]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/state[6]</cell>
</row>
<row>
 <cell>53</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/ConfigMaster_0/N_937</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/un1_state_42_i_a2_0_d_0</cell>
</row>
<row>
 <cell>43</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>39</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/ConfigMaster_0/state[5]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/state[5]</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/N_152</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNIE8PL[0]</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/ConfigMaster_0/state[18]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/state[18]</cell>
</row>
<row>
 <cell>36</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/HREADY_M_pre37</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37</cell>
</row>
<row>
 <cell>35</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/masterDataInProg[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]</cell>
</row>
<row>
 <cell>35</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MDDR_TA_0/ConfigMaster_0/state[20]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MDDR_TA_0/ConfigMaster_0/state[20]</cell>
</row>
</table>
</doc>
