Project Status Summary Page

Project Settings
Project Name | MDDR_TA_top_syn | Implementation Name | synthesis
Top Module | MDDR_TA_top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 86 | 2126 | 0 | - | 0m:09s | - | 9/29/2015 2:53:32 PM
(premap) | Complete | 53 | 14 | 0 | 0m:01s | 0m:04s | 167MB | 9/29/2015 2:53:40 PM
(fpga_mapper) | Complete | 196 | 3454 | 0 | 0m:11s | 0m:14s | 217MB | 9/29/2015 2:53:55 PM
Multi-srs Generator | Complete |  |  |  | 0m:02s |  |  | 9/29/2015 2:53:35 PM

Area Summary
Carry Cells | 299 | Sequential Cells | 963
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 51
Global Clock Buffers | 9 | Block Rams (RAM1K18) (v_ram) | 3
LUTs (total_luts) | 1520 |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 123.3 MHz | 1.890
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock | 100.0 MHz | 161.5 MHz | 3.809
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | 417.3 MHz | 7.604
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock | 100.0 MHz | 143.4 MHz | 2.274

Optimizations Summary
Combined Clock Conversion | 3 / 1 |  |