<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.6.0.34</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)</text>
<text>Date: Tue Sep 29 15:06:38 2015
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>MDDR_TA_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>IGLOO2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2GL010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>8.137</cell>
 <cell>122.895</cell>
 <cell>48.193</cell>
 <cell>20.750</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>5.186</cell>
 <cell>192.827</cell>
 <cell>12.048</cell>
 <cell>83.001</cell>
 <cell>-0.992</cell>
 <cell>1.015</cell>
 <cell>5.757</cell>
 <cell>9.514</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>3.043</cell>
 <cell>328.623</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell>6.121</cell>
 <cell>163.372</cell>
 <cell>48.000</cell>
 <cell>20.833</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:CLK</cell>
 <cell>MDDR_TA_0/ConfigMaster_0/HADDR[25]:EN</cell>
 <cell>7.757</cell>
 <cell>40.056</cell>
 <cell>13.161</cell>
 <cell>53.217</cell>
 <cell>0.335</cell>
 <cell>8.137</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:CLK</cell>
 <cell>MDDR_TA_0/ConfigMaster_0/HADDR[26]:EN</cell>
 <cell>7.757</cell>
 <cell>40.056</cell>
 <cell>13.161</cell>
 <cell>53.217</cell>
 <cell>0.335</cell>
 <cell>8.137</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:CLK</cell>
 <cell>MDDR_TA_0/ConfigMaster_0/HADDR[29]:EN</cell>
 <cell>7.757</cell>
 <cell>40.064</cell>
 <cell>13.161</cell>
 <cell>53.225</cell>
 <cell>0.335</cell>
 <cell>8.129</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:CLK</cell>
 <cell>MDDR_TA_0/ConfigMaster_0/HADDR[27]:EN</cell>
 <cell>7.757</cell>
 <cell>40.064</cell>
 <cell>13.161</cell>
 <cell>53.225</cell>
 <cell>0.335</cell>
 <cell>8.129</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:CLK</cell>
 <cell>MDDR_TA_0/ConfigMaster_0/HADDR[25]:EN</cell>
 <cell>7.528</cell>
 <cell>40.285</cell>
 <cell>12.932</cell>
 <cell>53.217</cell>
 <cell>0.335</cell>
 <cell>7.908</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/ConfigMaster_0/HADDR[25]:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>53.217</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>13.161</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>40.056</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.982</cell>
 <cell>3.982</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>4.216</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>4.382</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.292</cell>
 <cell>4.674</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.924</cell>
 <cell>40</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.480</cell>
 <cell>5.404</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>5.512</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37_8:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.504</cell>
 <cell>6.016</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37_8:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.315</cell>
 <cell>6.331</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37_8</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.428</cell>
 <cell>6.759</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.202</cell>
 <cell>6.961</cell>
 <cell>36</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37_RNI24F61:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/HREADY_M_pre37</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.824</cell>
 <cell>7.785</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37_RNI24F61:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.158</cell>
 <cell>7.943</cell>
 <cell>26</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/un1_state_46_0_o2_0_1_0:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/N_102</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.993</cell>
 <cell>8.936</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/un1_state_46_0_o2_0_1_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.336</cell>
 <cell>9.272</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/un1_state_46_0_o2_0_0:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/ConfigMaster_0/un1_state_46_0_o2_0_1_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.625</cell>
 <cell>9.897</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/un1_state_46_0_o2_0_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.140</cell>
 <cell>10.037</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/un1_state_46:C</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/ConfigMaster_0/N_1123</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.615</cell>
 <cell>10.652</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/un1_state_46:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.134</cell>
 <cell>10.786</cell>
 <cell>32</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/HADDR[25]:EN</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/ConfigMaster_0/un1_state_46</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.375</cell>
 <cell>13.161</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.161</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>48.193</cell>
 <cell>48.193</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>48.193</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.982</cell>
 <cell>52.175</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>52.409</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>52.575</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.292</cell>
 <cell>52.867</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>53.117</cell>
 <cell>40</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/HADDR[25]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.435</cell>
 <cell>53.552</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/ConfigMaster_0/HADDR[25]:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>53.217</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>53.217</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N</cell>
 <cell>1.490</cell>
 <cell>44.472</cell>
 <cell>6.924</cell>
 <cell>51.396</cell>
 <cell>2.311</cell>
 <cell>3.721</cell>
 <cell>-0.080</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:ALn</cell>
 <cell>3.023</cell>
 <cell>44.783</cell>
 <cell>8.431</cell>
 <cell>53.214</cell>
 <cell>0.353</cell>
 <cell>3.410</cell>
 <cell>0.034</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_state[5]:ALn</cell>
 <cell>3.023</cell>
 <cell>44.783</cell>
 <cell>8.431</cell>
 <cell>53.214</cell>
 <cell>0.353</cell>
 <cell>3.410</cell>
 <cell>0.034</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_state[4]:ALn</cell>
 <cell>3.023</cell>
 <cell>44.783</cell>
 <cell>8.431</cell>
 <cell>53.214</cell>
 <cell>0.353</cell>
 <cell>3.410</cell>
 <cell>0.034</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable:ALn</cell>
 <cell>3.023</cell>
 <cell>44.783</cell>
 <cell>8.431</cell>
 <cell>53.214</cell>
 <cell>0.353</cell>
 <cell>3.410</cell>
 <cell>0.034</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>51.396</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.924</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>44.472</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.982</cell>
 <cell>3.982</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>4.216</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>4.381</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.289</cell>
 <cell>4.670</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.920</cell>
 <cell>31</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.514</cell>
 <cell>5.434</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>5.521</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.324</cell>
 <cell>5.845</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.074</cell>
 <cell>5.919</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_271:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.796</cell>
 <cell>6.715</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_271:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>6.924</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/FPGA_MDDR_ARESET_N_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.924</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.924</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>48.193</cell>
 <cell>48.193</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>48.193</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.982</cell>
 <cell>52.175</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>52.409</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>52.574</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>52.864</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>53.114</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.384</cell>
 <cell>53.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>53.707</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>53.707</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:FPGA_MDDR_ARESET_N</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>-</cell>
 <cell>2.311</cell>
 <cell>51.396</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>51.396</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[55]</cell>
 <cell>4.455</cell>
 <cell>0.892</cell>
 <cell>9.773</cell>
 <cell>10.665</cell>
 <cell>6.897</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[52]</cell>
 <cell>4.502</cell>
 <cell>0.895</cell>
 <cell>9.820</cell>
 <cell>10.715</cell>
 <cell>6.847</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[61]</cell>
 <cell>4.417</cell>
 <cell>0.919</cell>
 <cell>9.735</cell>
 <cell>10.654</cell>
 <cell>6.908</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[40]</cell>
 <cell>4.304</cell>
 <cell>0.951</cell>
 <cell>9.622</cell>
 <cell>10.573</cell>
 <cell>6.989</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[41]</cell>
 <cell>4.420</cell>
 <cell>0.953</cell>
 <cell>9.738</cell>
 <cell>10.691</cell>
 <cell>6.871</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[55]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.665</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>9.773</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.892</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.778</cell>
 <cell>3.778</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>4.001</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>4.166</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.310</cell>
 <cell>4.476</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.726</cell>
 <cell>14</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/FF_0:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.456</cell>
 <cell>5.182</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/FF_0:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLK</cell>
 <cell>+</cell>
 <cell>0.059</cell>
 <cell>5.241</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/A_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>5.318</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_DOUT[5]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RAM1K18_IP</cell>
 <cell>+</cell>
 <cell>2.191</cell>
 <cell>7.509</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/WDATA_ret_RNIB8JC[55]:B</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/Rdata_mem_reto[55]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.044</cell>
 <cell>8.553</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/WDATA_ret_RNIB8JC[55]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.158</cell>
 <cell>8.711</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_243:A</cell>
 <cell>net</cell>
 <cell>AXI_IF_0_BIF_1_WDATA[55]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.868</cell>
 <cell>9.579</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_243:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>9.773</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[55]</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/F_WDATA_HWDATA01_net[55]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>9.773</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.773</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.048</cell>
 <cell>12.048</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>12.048</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.982</cell>
 <cell>16.030</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>16.264</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>16.429</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>16.719</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>16.969</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.384</cell>
 <cell>17.353</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>17.562</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>17.562</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_WDATA_HWDATA01[55]</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>-</cell>
 <cell>6.897</cell>
 <cell>10.665</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.665</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FIC2_APB_CLK to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>1.095</cell>
 <cell>1.464</cell>
 <cell>3.860</cell>
 <cell>5.324</cell>
 <cell>0.254</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>0.788</cell>
 <cell>1.781</cell>
 <cell>3.541</cell>
 <cell>5.322</cell>
 <cell>0.254</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.324</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.860</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.464</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.476</cell>
 <cell>1.476</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.220</cell>
 <cell>1.696</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.305</cell>
 <cell>2.001</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>2.251</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.514</cell>
 <cell>2.765</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>2.852</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0_CONFIG2_DONE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.008</cell>
 <cell>3.860</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.860</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.193</cell>
 <cell>0.193</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.193</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.982</cell>
 <cell>4.175</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>4.409</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>4.574</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.289</cell>
 <cell>4.863</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>5.113</cell>
 <cell>31</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.465</cell>
 <cell>5.578</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>5.324</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.324</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>AXI_IF_0/rburst_cnt[4]:CLK</cell>
 <cell>AXI_IF_0/r_clk_cnt[10]:D</cell>
 <cell>4.892</cell>
 <cell>6.862</cell>
 <cell>10.104</cell>
 <cell>16.966</cell>
 <cell>0.254</cell>
 <cell>5.186</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>AXI_IF_0/rburst_cnt[4]:CLK</cell>
 <cell>AXI_IF_0/r_clk_cnt[6]:D</cell>
 <cell>4.859</cell>
 <cell>6.891</cell>
 <cell>10.071</cell>
 <cell>16.962</cell>
 <cell>0.254</cell>
 <cell>5.157</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>AXI_IF_0/rburst_cnt[5]:CLK</cell>
 <cell>AXI_IF_0/r_clk_cnt[10]:D</cell>
 <cell>4.840</cell>
 <cell>6.914</cell>
 <cell>10.052</cell>
 <cell>16.966</cell>
 <cell>0.254</cell>
 <cell>5.134</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>AXI_IF_0/rburst_cnt[4]:CLK</cell>
 <cell>AXI_IF_0/r_clk_cnt[13]:D</cell>
 <cell>4.820</cell>
 <cell>6.932</cell>
 <cell>10.032</cell>
 <cell>16.964</cell>
 <cell>0.254</cell>
 <cell>5.116</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>AXI_IF_0/rburst_cnt[5]:CLK</cell>
 <cell>AXI_IF_0/r_clk_cnt[6]:D</cell>
 <cell>4.807</cell>
 <cell>6.943</cell>
 <cell>10.019</cell>
 <cell>16.962</cell>
 <cell>0.254</cell>
 <cell>5.105</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: AXI_IF_0/rburst_cnt[4]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: AXI_IF_0/r_clk_cnt[10]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.966</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.104</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.862</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.778</cell>
 <cell>3.778</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>4.001</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>4.166</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB6:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.304</cell>
 <cell>4.470</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB6:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>4.721</cell>
 <cell>51</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/rburst_cnt[4]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB6_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.491</cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/rburst_cnt[4]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>5.320</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/un3_rt_0_cry_4:B</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/rburst_cnt[4]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.441</cell>
 <cell>5.761</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/un3_rt_0_cry_4:UB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>5.984</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/un3_rt_0_cry_4_CC_0:UB[6]</cell>
 <cell>net</cell>
 <cell>NET_CC_CONFIG696</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.984</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/un3_rt_0_cry_4_CC_0:CC[11]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CC_CONFIG</cell>
 <cell>+</cell>
 <cell>0.797</cell>
 <cell>6.781</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/un3_rt_0_cry_8_FCINST1:CC</cell>
 <cell>net</cell>
 <cell>NET_CC_CONFIG712</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.781</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/un3_rt_0_cry_8_FCINST1:CO</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:FCEND_BUFF_CC</cell>
 <cell>+</cell>
 <cell>0.073</cell>
 <cell>6.854</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/rt_0:C</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/un3_rt_0_cry_9</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.346</cell>
 <cell>7.200</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/rt_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>7.287</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_cry_cy[0]:B</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/rt_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.738</cell>
 <cell>8.025</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_cry_cy[0]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.164</cell>
 <cell>8.189</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_cry[5]:B</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/r_clk_cnt_cry_cy_Y[0]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.278</cell>
 <cell>8.467</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_cry[5]:P</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.200</cell>
 <cell>8.667</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_cry_cy[0]_CC_0:P[6]</cell>
 <cell>net</cell>
 <cell>NET_CC_CONFIG536</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>8.667</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_cry_cy[0]_CC_0:CC[11]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CC_CONFIG</cell>
 <cell>+</cell>
 <cell>0.698</cell>
 <cell>9.365</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_cry[10]:CC</cell>
 <cell>net</cell>
 <cell>NET_CC_CONFIG553</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>9.365</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_cry[10]:S</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.066</cell>
 <cell>9.431</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_ldmx[10]:B</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/r_clk_cnt_s[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.525</cell>
 <cell>9.956</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt_ldmx[10]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.074</cell>
 <cell>10.030</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt[10]:D</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/r_clk_cnt_ldmx[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.074</cell>
 <cell>10.104</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.104</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.048</cell>
 <cell>12.048</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>12.048</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.778</cell>
 <cell>15.826</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>16.049</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>16.214</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB6:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.304</cell>
 <cell>16.518</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB6:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>16.769</cell>
 <cell>51</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt[10]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB6_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.451</cell>
 <cell>17.220</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/r_clk_cnt[10]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>16.966</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.966</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>External Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>RX</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D</cell>
 <cell>3.840</cell>
 <cell></cell>
 <cell>3.840</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>-0.992</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: RX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.840</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>RX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>RX</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>2.437</cell>
 <cell>2.437</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>RX_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.437</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.083</cell>
 <cell>2.520</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D</cell>
 <cell>net</cell>
 <cell>RX_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.320</cell>
 <cell>3.840</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.840</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.778</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.201</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.149</cell>
 <cell>N/C</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.275</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB4:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.226</cell>
 <cell>N/C</cell>
 <cell>34</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB4_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.457</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTO01/CUARTIlIl[2]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COM_Interface_0/COREUART_0/CUARTIO1/CUARTll1:CLK</cell>
 <cell>TX</cell>
 <cell>4.275</cell>
 <cell></cell>
 <cell>9.514</cell>
 <cell></cell>
 <cell>9.514</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COM_Interface_0/COREUART_0/CUARTIO1/CUARTll1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: TX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>9.514</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.778</cell>
 <cell>3.778</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>4.001</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>4.166</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>4.475</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>4.726</cell>
 <cell>54</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTIO1/CUARTll1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.513</cell>
 <cell>5.239</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COM_Interface_0/COREUART_0/CUARTIO1/CUARTll1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>5.347</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>TX_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>TX_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.158</cell>
 <cell>6.505</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>TX_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.343</cell>
 <cell>6.848</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>TX_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>TX_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.848</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>TX_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.666</cell>
 <cell>9.514</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>TX</cell>
 <cell>net</cell>
 <cell>TX</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>9.514</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.514</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.778</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>TX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/rdata_cnt[6]:EN</cell>
 <cell>4.755</cell>
 <cell>6.608</cell>
 <cell>10.269</cell>
 <cell>16.877</cell>
 <cell>0.335</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/rdata_cnt[4]:EN</cell>
 <cell>4.755</cell>
 <cell>6.608</cell>
 <cell>10.269</cell>
 <cell>16.877</cell>
 <cell>0.335</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/rdata_cnt[2]:EN</cell>
 <cell>4.755</cell>
 <cell>6.608</cell>
 <cell>10.269</cell>
 <cell>16.877</cell>
 <cell>0.335</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/rdata_cnt[8]:EN</cell>
 <cell>4.755</cell>
 <cell>6.608</cell>
 <cell>10.269</cell>
 <cell>16.877</cell>
 <cell>0.335</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/rdata_cnt[0]:EN</cell>
 <cell>4.755</cell>
 <cell>6.616</cell>
 <cell>10.269</cell>
 <cell>16.885</cell>
 <cell>0.335</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: AXI_IF_0/rdata_cnt[6]:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.877</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.269</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.608</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.982</cell>
 <cell>3.982</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>4.216</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>4.381</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>4.671</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.921</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.384</cell>
 <cell>5.305</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>5.514</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.514</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_RVALID</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>0.993</cell>
 <cell>6.507</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/axi_fsm_read1_state_RNIR29S[1]:B</cell>
 <cell>net</cell>
 <cell>AXI_IF_0_BIF_1_RVALID</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.656</cell>
 <cell>9.163</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/axi_fsm_read1_state_RNIR29S[1]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.164</cell>
 <cell>9.327</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/rdata_cnt[6]:EN</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/N_395_i_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.942</cell>
 <cell>10.269</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.269</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.048</cell>
 <cell>12.048</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>12.048</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.778</cell>
 <cell>15.826</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>16.049</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>16.214</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>16.523</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>16.773</cell>
 <cell>10</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/rdata_cnt[6]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.439</cell>
 <cell>17.212</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/rdata_cnt[6]:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>16.877</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.877</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[10]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.649</cell>
 <cell>16.957</cell>
 <cell>7.634</cell>
 <cell>24.591</cell>
 <cell>0.335</cell>
 <cell>3.043</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[9]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.606</cell>
 <cell>17.012</cell>
 <cell>7.579</cell>
 <cell>24.591</cell>
 <cell>0.335</cell>
 <cell>2.988</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[7]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.521</cell>
 <cell>17.097</cell>
 <cell>7.494</cell>
 <cell>24.591</cell>
 <cell>0.335</cell>
 <cell>2.903</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[8]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.481</cell>
 <cell>17.125</cell>
 <cell>7.466</cell>
 <cell>24.591</cell>
 <cell>0.335</cell>
 <cell>2.875</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[13]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.429</cell>
 <cell>17.189</cell>
 <cell>7.402</cell>
 <cell>24.591</cell>
 <cell>0.335</cell>
 <cell>2.811</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/count_ddr[10]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>24.591</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.634</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.957</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.053</cell>
 <cell>2.053</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>2.205</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.497</cell>
 <cell>3.702</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.220</cell>
 <cell>3.922</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>4.231</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.481</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[10]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.504</cell>
 <cell>4.985</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[10]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>5.093</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled4_7:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.517</cell>
 <cell>5.610</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled4_7:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.287</cell>
 <cell>5.897</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled4:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled4_7</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.206</cell>
 <cell>6.103</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.287</cell>
 <cell>6.390</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.244</cell>
 <cell>7.634</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.634</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.053</cell>
 <cell>22.053</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>22.205</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.497</cell>
 <cell>23.702</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.220</cell>
 <cell>23.922</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>24.231</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>24.481</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.445</cell>
 <cell>24.926</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>24.591</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>24.591</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[13]:ALn</cell>
 <cell>1.173</cell>
 <cell>18.433</cell>
 <cell>6.138</cell>
 <cell>24.571</cell>
 <cell>0.353</cell>
 <cell>1.567</cell>
 <cell>0.041</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[5]:ALn</cell>
 <cell>1.173</cell>
 <cell>18.433</cell>
 <cell>6.138</cell>
 <cell>24.571</cell>
 <cell>0.353</cell>
 <cell>1.567</cell>
 <cell>0.041</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[11]:ALn</cell>
 <cell>1.173</cell>
 <cell>18.433</cell>
 <cell>6.138</cell>
 <cell>24.571</cell>
 <cell>0.353</cell>
 <cell>1.567</cell>
 <cell>0.041</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[9]:ALn</cell>
 <cell>1.173</cell>
 <cell>18.433</cell>
 <cell>6.138</cell>
 <cell>24.571</cell>
 <cell>0.353</cell>
 <cell>1.567</cell>
 <cell>0.041</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[7]:ALn</cell>
 <cell>1.173</cell>
 <cell>18.433</cell>
 <cell>6.138</cell>
 <cell>24.571</cell>
 <cell>0.353</cell>
 <cell>1.567</cell>
 <cell>0.041</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/count_ddr[13]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>24.571</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.138</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>18.433</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.053</cell>
 <cell>2.053</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>2.205</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.497</cell>
 <cell>3.702</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.220</cell>
 <cell>3.922</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>4.231</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.481</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.484</cell>
 <cell>4.965</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>5.052</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[13]:ALn</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.086</cell>
 <cell>6.138</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.138</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.053</cell>
 <cell>22.053</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>22.205</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.497</cell>
 <cell>23.702</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.220</cell>
 <cell>23.922</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>24.231</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>24.481</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[13]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.443</cell>
 <cell>24.924</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[13]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>24.571</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>24.571</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_APB_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>1.920</cell>
 <cell>21.660</cell>
 <cell>4.692</cell>
 <cell>26.352</cell>
 <cell>0.339</cell>
 <cell>4.680</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[11]:D</cell>
 <cell>1.922</cell>
 <cell>21.753</cell>
 <cell>4.694</cell>
 <cell>26.447</cell>
 <cell>0.254</cell>
 <cell>4.494</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:D</cell>
 <cell>1.918</cell>
 <cell>21.768</cell>
 <cell>4.690</cell>
 <cell>26.458</cell>
 <cell>0.254</cell>
 <cell>4.464</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:D</cell>
 <cell>1.784</cell>
 <cell>21.903</cell>
 <cell>4.556</cell>
 <cell>26.459</cell>
 <cell>0.254</cell>
 <cell>4.194</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:D</cell>
 <cell>1.783</cell>
 <cell>21.904</cell>
 <cell>4.555</cell>
 <cell>26.459</cell>
 <cell>0.254</cell>
 <cell>4.192</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>26.352</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.692</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.660</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.559</cell>
 <cell>1.559</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>1.782</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.299</cell>
 <cell>2.081</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.182</cell>
 <cell>2.263</cell>
 <cell>7</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.509</cell>
 <cell>2.772</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>2.864</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/state_ns_0_0_a2_1[1]:C</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.438</cell>
 <cell>3.302</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/state_ns_0_0_a2_1[1]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.265</cell>
 <cell>3.567</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/state_ns_0_0_a2_1[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.244</cell>
 <cell>3.811</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.134</cell>
 <cell>3.945</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/N_82_i_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.747</cell>
 <cell>4.692</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.692</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>24.000</cell>
 <cell>24.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>24.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.476</cell>
 <cell>25.476</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.220</cell>
 <cell>25.696</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.302</cell>
 <cell>25.998</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>26.248</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIA209/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.443</cell>
 <cell>26.691</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.339</cell>
 <cell>26.352</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>26.352</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_APB_CLK</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
