#--  Synopsys, Inc.
#--  Version J-2015.03M-3
#--  Project file D:\Libero_11.6_migration\Libero_designs\m2gl_ac424_libero11p6_df\Libero_Project\MDDR_TA\synthesis\MDDR_TA_top_syn.prj

#project files
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/hdl/AXI_IF.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/hdl/CMD_Decoder.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_g4.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/CoreUART.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/COM_Interface/TPSRAM_0/COM_Interface_TPSRAM_0_TPSRAM.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/hdl/Control_Logic.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/COM_Interface/COM_Interface.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vlog/core/coreconfigmaster.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/SgCore/OSC/1.0.105/osc_comps.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS_syn.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/MDDR_TA/MDDR_TA.v"
add_file -verilog "D:/Libero_11.6_migration/Libero_designs/m2gl_ac424_libero11p6_df/Libero_Project/MDDR_TA/component/work/MDDR_TA_top/MDDR_TA_top.v"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology IGLOO2
set_option -part M2GL010T
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "MDDR_TA_top"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMWC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./MDDR_TA_top.edn"


#implementation: "synthesis_1"
impl -add synthesis_1 -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology IGLOO2
set_option -part M2GL010T
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "MDDR_TA_top"

# mapper_options
set_option -frequency 400.000000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMWC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "synthesis_1/MDDR_TA_top.edn"


#implementation: "synthesis_2"
impl -add synthesis_2 -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology IGLOO2
set_option -part M2GL010T
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "MDDR_TA_top"

# mapper_options
set_option -frequency 400.000000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -identify_debug_mode 1
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMWC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "synthesis_2/MDDR_TA_top.edn"
impl -active "synthesis"
