

@S |##### START OF TIMING REPORT #####[
# Timing Report written on Tue Sep 29 14:53:55 2015
#


Top view:               MDDR_TA_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 0.278

                                                           Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                                             Frequency     Frequency     Period        Period        Slack     Type         Group              
-------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     123.3 MHz     10.000        8.110         1.890     inferred     Inferred_clkgroup_1
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock                  100.0 MHz     161.5 MHz     10.000        6.191         3.809     inferred     Inferred_clkgroup_3
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     417.3 MHz     10.000        2.396         7.604     inferred     Inferred_clkgroup_2
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock               100.0 MHz     143.4 MHz     10.000        6.971         2.274     inferred     Inferred_clkgroup_0
=============================================================================================================================================================



Clock Relationships
*******************

Clocks                                                                                                          |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                Ending                                                  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock            |  0.000       0.315  |  No paths    -      |  5.000       5.480  |  5.000       5.461
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock            |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  0.000       0.278  |  No paths    -      |  No paths    -      |  No paths    -    
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  |  0.000       0.315  |  No paths    -      |  No paths    -      |  No paths    -    
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock               |  0.000       0.315  |  No paths    -      |  No paths    -      |  No paths    -    
======================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                   Starting                                                                                   Arrival          
Instance                                           Reference                                     Type     Pin     Net                         Time        Slack
                                                   Clock                                                                                                       
---------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.sm0_state[6]                MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       sm0_state[6]                0.066       0.278
MDDR_TA_0.CORERESETP_0.CONFIG1_DONE_q1             MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       CONFIG1_DONE_q1             0.053       0.315
MDDR_TA_0.CORERESETP_0.CONFIG2_DONE_q1             MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       CONFIG2_DONE_q1             0.053       0.315
MDDR_TA_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_q1     MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       FIC_2_APB_M_PRESET_N_q1     0.053       0.315
MDDR_TA_0.CORERESETP_0.POWER_ON_RESET_N_q1         MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       POWER_ON_RESET_N_q1         0.053       0.315
MDDR_TA_0.CORERESETP_0.RESET_N_M2F_q1              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       RESET_N_M2F_q1              0.053       0.315
MDDR_TA_0.CORERESETP_0.ddr_settled_q1              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       ddr_settled_q1              0.053       0.315
MDDR_TA_0.CORERESETP_0.release_sdif0_core_q1       MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       release_sdif3_core_q1       0.053       0.315
MDDR_TA_0.CORERESETP_0.sdif3_spll_lock_q1          MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       sdif3_spll_lock_q1          0.053       0.315
MDDR_TA_0.CORERESETP_0.sm0_areset_n_q1             MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       sm0_areset_n_q1             0.053       0.315
===============================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                         Starting                                                                                   Required          
Instance                                                 Reference                                     Type     Pin     Net                         Time         Slack
                                                         Clock                                                                                                        
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.INIT_DONE_int                     MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      sm0_state[6]                0.205        0.278
MDDR_TA_0.CORERESETP_0.CONFIG1_DONE_clk_base             MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CONFIG1_DONE_q1             0.155        0.315
MDDR_TA_0.CORERESETP_0.CONFIG2_DONE_clk_base             MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CONFIG2_DONE_q1             0.155        0.315
MDDR_TA_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base     MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       FIC_2_APB_M_PRESET_N_q1     0.155        0.315
MDDR_TA_0.CORERESETP_0.POWER_ON_RESET_N_clk_base         MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       POWER_ON_RESET_N_q1         0.155        0.315
MDDR_TA_0.CORERESETP_0.RESET_N_M2F_clk_base              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       RESET_N_M2F_q1              0.155        0.315
MDDR_TA_0.CORERESETP_0.ddr_settled_clk_base              MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       ddr_settled_q1              0.155        0.315
MDDR_TA_0.CORERESETP_0.release_sdif0_core_clk_base       MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       release_sdif3_core_q1       0.155        0.315
MDDR_TA_0.CORERESETP_0.sdif3_spll_lock_q2                MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       sdif3_spll_lock_q1          0.155        0.315
MDDR_TA_0.CORERESETP_0.sm0_areset_n_clk_base             MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       sm0_areset_n_q1             0.155        0.315
======================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.483
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.205
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     0.277

    Number of logic level(s):                0
    Starting point:                          MDDR_TA_0.CORERESETP_0.sm0_state[6] / Q
    Ending point:                            MDDR_TA_0.CORERESETP_0.INIT_DONE_int / EN
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.sm0_state[6]      SLE      Q        Out     0.066     0.066       -         
sm0_state[6]                             Net      -        -       0.417     -           1         
MDDR_TA_0.CORERESETP_0.INIT_DONE_int     SLE      EN       In      -         0.483       -         
===================================================================================================




====================================
Detailed Report for Clock: MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                     Starting                                                                                       Arrival          
Instance                                             Reference                                     Type     Pin     Net                             Time        Slack
                                                     Clock                                                                                                           
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
COM_Interface_0.COREUART_0.CUARTO1I[0]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTO1I[0]                     0.053       0.315
COM_Interface_0.COREUART_0.CUARTO1I[1]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTO1I[1]                     0.053       0.315
COM_Interface_0.COREUART_0.CUARTO1I[2]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTO1I[2]                     0.053       0.315
COM_Interface_0.COREUART_0.CUARTO1I[3]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTO1I[3]                     0.053       0.315
COM_Interface_0.COREUART_0.CUARTO1I[4]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTO1I[4]                     0.053       0.315
COM_Interface_0.COREUART_0.CUARTO1I[5]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTO1I[5]                     0.053       0.315
COM_Interface_0.COREUART_0.CUARTO1I[6]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTO1I[6]                     0.053       0.315
COM_Interface_0.COREUART_0.CUARTO1I[7]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTO1I[7]                     0.053       0.315
COM_Interface_0.COREUART_0.CUARTO01.CUARTOIIl[0]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       CUARTOIIl[0]                    0.053       0.315
COM_Interface_0.Control_Logic_0.DATA_OUT[0]          MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       Control_Logic_0_DATA_OUT[0]     0.053       0.315
=====================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                     Starting                                                                                       Required          
Instance                                             Reference                                     Type     Pin     Net                             Time         Slack
                                                     Clock                                                                                                            
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[0]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       CUARTO1I[0]                     0.155        0.315
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[1]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       CUARTO1I[1]                     0.155        0.315
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[2]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       CUARTO1I[2]                     0.155        0.315
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[3]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       CUARTO1I[3]                     0.155        0.315
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[4]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       CUARTO1I[4]                     0.155        0.315
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[5]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       CUARTO1I[5]                     0.155        0.315
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[6]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       CUARTO1I[6]                     0.155        0.315
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[7]     MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       CUARTO1I[7]                     0.155        0.315
COM_Interface_0.COREUART_0.CUARTO1I[0]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       Control_Logic_0_DATA_OUT[0]     0.155        0.315
COM_Interface_0.COREUART_0.CUARTO1I[1]               MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       Control_Logic_0_DATA_OUT[1]     0.155        0.315
======================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.470
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.155
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (non-critical) :                 0.315

    Number of logic level(s):                0
    Starting point:                          COM_Interface_0.COREUART_0.CUARTO1I[0] / Q
    Ending point:                            COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[0] / D
    The start point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                 Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
COM_Interface_0.COREUART_0.CUARTO1I[0]               SLE      Q        Out     0.053     0.053       -         
CUARTO1I[0]                                          Net      -        -       0.417     -           1         
COM_Interface_0.COREUART_0.CUARTIO1.CUARTIO0l[0]     SLE      D        In      -         0.470       -         
===============================================================================================================




====================================
Detailed Report for Clock: MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                  Starting                                                                                               Arrival          
Instance                                          Reference                                                  Type     Pin     Net                        Time        Slack
                                                  Clock                                                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.count_ddr_enable_q1        MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr_enable_q1        0.053       0.315
MDDR_TA_0.CORERESETP_0.sm0_areset_n_rcosc_q1      MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       sm0_areset_n_rcosc_q1      0.053       0.315
MDDR_TA_0.CORERESETP_0.count_ddr[0]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[0]               0.066       0.516
MDDR_TA_0.CORERESETP_0.count_ddr_enable_rcosc     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr_enable_rcosc     0.066       0.717
MDDR_TA_0.CORERESETP_0.count_ddr[10]              MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[10]              0.066       0.812
MDDR_TA_0.CORERESETP_0.count_ddr[7]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[7]               0.053       0.854
MDDR_TA_0.CORERESETP_0.count_ddr[9]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[9]               0.066       0.859
MDDR_TA_0.CORERESETP_0.count_ddr[6]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[6]               0.053       0.880
MDDR_TA_0.CORERESETP_0.count_ddr[5]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[5]               0.053       0.882
MDDR_TA_0.CORERESETP_0.count_ddr[8]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[8]               0.066       0.886
==========================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                  Starting                                                                                               Required          
Instance                                          Reference                                                  Type     Pin     Net                        Time         Slack
                                                  Clock                                                                                                                    
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.count_ddr_enable_rcosc     MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_enable_q1        0.155        0.315
MDDR_TA_0.CORERESETP_0.sdif0_areset_n_rcosc       MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       sm0_areset_n_rcosc_q1      0.155        0.315
MDDR_TA_0.CORERESETP_0.count_ddr[0]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[0]             0.155        0.516
MDDR_TA_0.CORERESETP_0.count_ddr[0]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      EN      count_ddr_enable_rcosc     0.205        0.717
MDDR_TA_0.CORERESETP_0.count_ddr[1]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      EN      count_ddr_enable_rcosc     0.205        0.717
MDDR_TA_0.CORERESETP_0.count_ddr[2]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      EN      count_ddr_enable_rcosc     0.205        0.717
MDDR_TA_0.CORERESETP_0.count_ddr[3]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      EN      count_ddr_enable_rcosc     0.205        0.717
MDDR_TA_0.CORERESETP_0.count_ddr[4]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      EN      count_ddr_enable_rcosc     0.205        0.717
MDDR_TA_0.CORERESETP_0.count_ddr[5]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      EN      count_ddr_enable_rcosc     0.205        0.717
MDDR_TA_0.CORERESETP_0.count_ddr[6]               MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      EN      count_ddr_enable_rcosc     0.205        0.717
===========================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.470
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.155
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (non-critical) :                 0.315

    Number of logic level(s):                0
    Starting point:                          MDDR_TA_0.CORERESETP_0.count_ddr_enable_q1 / Q
    Ending point:                            MDDR_TA_0.CORERESETP_0.count_ddr_enable_rcosc / D
    The start point is clocked by            MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK

Instance / Net                                             Pin      Pin               Arrival     No. of    
Name                                              Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORERESETP_0.count_ddr_enable_q1        SLE      Q        Out     0.053     0.053       -         
count_ddr_enable_q1                               Net      -        -       0.417     -           1         
MDDR_TA_0.CORERESETP_0.count_ddr_enable_rcosc     SLE      D        In      -         0.470       -         
============================================================================================================




====================================
Detailed Report for Clock: MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                               Starting                                                                                                         Arrival          
Instance                                       Reference                                        Type     Pin     Net                                            Time        Slack
                                               Clock                                                                                                                             
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORECONFIGP_0.INIT_DONE_q1           MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       INIT_DONE_q1                                   0.053       0.315
MDDR_TA_0.CORECONFIGP_0.state[0]               MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       state[0]                                       0.053       0.515
MDDR_TA_0.CORECONFIGP_0.paddr[15]              MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       paddr[15]                                      0.053       0.609
MDDR_TA_0.CORECONFIGP_0.control_reg_1[0]       MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       CORECONFIGP_0_CONFIG1_DONE                     0.053       0.643
MDDR_TA_0.CORECONFIGP_0.control_reg_1[1]       MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       CORECONFIGP_0_CONFIG2_DONE                     0.053       0.643
MDDR_TA_0.CORECONFIGP_0.state[1]               MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       state[1]                                       0.066       0.797
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PREADY     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       MDDR_TA_HPMS_TMP_0_FIC_2_APB_MASTER_PREADY     0.053       0.805
MDDR_TA_0.CORECONFIGP_0.soft_reset_reg[0]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       soft_reset_reg[0]                              0.053       0.919
MDDR_TA_0.CORECONFIGP_0.soft_reset_reg[2]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       soft_reset_reg[2]                              0.053       0.944
MDDR_TA_0.CORECONFIGP_0.soft_reset_reg[4]      MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      Q       soft_reset_reg[4]                              0.053       0.944
=================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                  Starting                                                                                    Required          
Instance                                          Reference                                        Type     Pin     Net                       Time         Slack
                                                  Clock                                                                                                         
----------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_TA_0.CORECONFIGP_0.INIT_DONE_q2              MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       INIT_DONE_q1              0.155        0.315
MDDR_TA_0.CORECONFIGP_0.state[1]                  MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       state_ns[1]               0.155        0.515
MDDR_TA_0.CORECONFIGP_0.control_reg_1[0]          MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       control_reg_1_ldmx[0]     0.155        0.609
MDDR_TA_0.CORECONFIGP_0.control_reg_1[1]          MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       control_reg_1_ldmx[1]     0.155        0.609
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0]     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      EN      state[1]                  0.205        0.797
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1]     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      EN      state[1]                  0.205        0.797
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2]     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      EN      state[1]                  0.205        0.797
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3]     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      EN      state[1]                  0.205        0.797
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4]     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      EN      state[1]                  0.205        0.797
MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5]     MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock     SLE      EN      state[1]                  0.205        0.797
================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.470
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.155
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (non-critical) :                 0.315

    Number of logic level(s):                0
    Starting point:                          MDDR_TA_0.CORECONFIGP_0.INIT_DONE_q1 / Q
    Ending point:                            MDDR_TA_0.CORECONFIGP_0.INIT_DONE_q2 / D
    The start point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
MDDR_TA_0.CORECONFIGP_0.INIT_DONE_q1     SLE      Q        Out     0.053     0.053       -         
INIT_DONE_q1                             Net      -        -       0.417     -           1         
MDDR_TA_0.CORECONFIGP_0.INIT_DONE_q2     SLE      D        In      -         0.470       -         
===================================================================================================



##### END OF TIMING REPORT #####]

