Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@L: D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top_scck.rpt 
Printing clock  summary report in "D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 123MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 123MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 123MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 125MB)

@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":254:0:254:5|Removing sequential instance AXI_IF_0.AWBURST_1[0],  because it is equivalent to instance AXI_IF_0.AWSIZE_1[0]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":523:0:523:5|Removing sequential instance AXI_IF_0.ARBURST_1[0],  because it is equivalent to instance AXI_IF_0.ARSIZE_1[0]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3567:27:3567:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3522:27:3522:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3477:27:3477:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3432:27:3432:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3387:27:3387:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3297:26:3297:37|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3252:27:3252:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3207:27:3207:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3162:27:3162:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3117:27:3117:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3072:27:3072:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_4,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3027:27:3027:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_3,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2982:27:2982:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_2,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3342:27:3342:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2937:27:2937:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_1,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_0
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1031:4:1031:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1414:0:1414:5|Removing sequential instance CUARTllI of view:PrimLib.dffs(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1414:0:1414:5|Removing sequential instance CUARTl1l_1 of view:PrimLib.dffr(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":447:4:447:9|Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z8(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1031:4:1031:9|Removing sequential instance USER_FAB_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":503:0:503:5|Removing sequential instance CUARTI01 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":1235:0:1235:5|Removing sequential instance CUARTl01 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":577:0:577:5|Removing sequential instance CUARTll1 of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2708:2:2708:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2771:2:2771:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2834:2:2834:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2892:27:2892:38|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":770:4:770:9|Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":784:4:784:9|Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":798:4:798:9|Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":812:4:812:9|Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":770:4:770:9|Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":784:4:784:9|Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":798:4:798:9|Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":812:4:812:9|Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":723:0:723:5|Removing sequential instance CUARTOIIl of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\work\com_interface\coreuart_0\rtl\vlog\core_obfuscated\rx_async.v":723:0:723:5|Removing sequential instance CUARTIIIl of view:PrimLib.dffre(prim) in hierarchy view:work.COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN115 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":90:29:90:41|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN362 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
syn_allowed_resources : blockrams=21  set on top level netlist MDDR_TA_top


Clock Summary
**************

Start                                                      Requested     Requested     Clock        Clock              
Clock                                                      Frequency     Period        Type         Group              
-----------------------------------------------------------------------------------------------------------------------
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock                  400.0 MHz     2.500         inferred     Inferred_clkgroup_1
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock                  400.0 MHz     2.500         inferred     Inferred_clkgroup_3
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     400.0 MHz     2.500         inferred     Inferred_clkgroup_2
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock               400.0 MHz     2.500         inferred     Inferred_clkgroup_0
System                                                     1.0 MHz       1000.000      system       system_clkgroup    
=======================================================================================================================

@W: MT530 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":433:4:433:9|Found inferred clock MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 92 sequential elements including MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Found inferred clock MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock which controls 473 sequential elements including MDDR_TA_0.ConfigMaster_0.state[20:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1562:4:1562:9|Found inferred clock MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including MDDR_TA_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":523:0:523:5|Found inferred clock MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock which controls 834 sequential elements including AXI_IF_0.ARADDR_1[31:7]. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 156MB)

Process took 0h:00m:03s realtime, 0h:00m:01s cputime
# Thu Mar 27 12:20:16 2014

###########################################################]
