# Synospys Constraint Checker(syntax only), version mapact, Build 1154R, built Jan 20 2014
# Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

# Written on Thu Mar 27 12:20:13 2014


##### DESIGN INFO #######################################################

Top View:                "MDDR_TA_top"
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
**************

Start                                                      Requested     Requested     Clock        Clock              
Clock                                                      Frequency     Period        Type         Group              
-----------------------------------------------------------------------------------------------------------------------
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock                  400.0 MHz     2.500         inferred     Inferred_clkgroup_1
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock                  400.0 MHz     2.500         inferred     Inferred_clkgroup_3
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     400.0 MHz     2.500         inferred     Inferred_clkgroup_2
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock               400.0 MHz     2.500         inferred     Inferred_clkgroup_0
System                                                     1.0 MHz       1000.000      system       system_clkgroup    
=======================================================================================================================
