Selecting top level module MDDR_TA_top
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":29:7:29:12|Synthesizing module AXI_IF

	Idle_0=3'b000
	Idle_1=3'b001
	Write_0=3'b010
	Write_1=3'b011
	Read_0=3'b010
	Read_1=3'b011
	Read_2=3'b100
	Bresp_0=3'b100
	Write_2=3'b101
   Generated name = AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1

@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":392:17:392:25|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":400:17:400:25|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":447:17:447:25|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":455:17:455:25|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":542:24:542:29|Removing redundant assignment
@W: CG133 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":95:13:95:22|No assignment to ARADDR_int
@N: CL134 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":347:0:347:5|Found RAM Rdata_mem, depth=512, width=64
@A: CL282 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Feedback mux created for signal burst_cnt[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Feedback mux created for signal AWADDR[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWBURST[1] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWSIZE[2] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":470:0:470:5|Optimizing register bit WD[14] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":470:0:470:5|Optimizing register bit WD[15] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Optimizing register bit ARBURST[1] to a constant 0
@W: CL279 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":470:0:470:5|Pruning register bits 15 to 14 of WD[15:0] 

@W: CL260 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Pruning register bit 1 of AWBURST[1:0] 

@W: CL260 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Pruning register bit 2 of AWSIZE[2:0] 

@W: CL260 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Pruning register bit 1 of ARBURST[1:0] 

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":19:7:19:17|Synthesizing module CMD_Decoder

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\Control_Logic.v":20:7:20:19|Synthesizing module Control_Logic

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":30:0:30:33|Synthesizing module COM_Interface_COREUART_0_Clock_gen

	BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
   Generated name = COM_Interface_COREUART_0_Clock_gen_0s

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Tx_async

	TX_FIFO=32'b00000000000000000000000000000000
	CUARTlIll=32'b00000000000000000000000000000000
	CUARTOlll=32'b00000000000000000000000000000001
	CUARTIlll=32'b00000000000000000000000000000010
	CUARTllll=32'b00000000000000000000000000000011
	CUARTO0ll=32'b00000000000000000000000000000100
	CUARTI0ll=32'b00000000000000000000000000000101
	CUARTl0ll=32'b00000000000000000000000000000110
   Generated name = COM_Interface_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s

@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":794:0:794:8|Removing redundant assignment
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":253:0:253:5|Optimizing register bit CUARTlO0l to a constant 1
@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":253:0:253:5|Pruning register CUARTlO0l 

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_Rx_async

	RX_FIFO=32'b00000000000000000000000000000000
	CUARTllIl=32'b00000000000000000000000000000000
	CUARTO0Il=32'b00000000000000000000000000000001
	CUARTI0Il=32'b00000000000000000000000000000010
   Generated name = COM_Interface_COREUART_0_Rx_async_0s_0s_1s_2s

@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":654:0:654:7|Removing redundant assignment
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":1414:0:1414:5|Sharing sequential element CUARTl0l.
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":14:0:14:32|Synthesizing module COM_Interface_COREUART_0_COREUART

	TX_FIFO=32'b00000000000000000000000000000000
	RX_FIFO=32'b00000000000000000000000000000000
	RX_LEGACY_MODE=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000010011
	BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
   Generated name = COM_Interface_COREUART_0_COREUART_0s_0s_0s_19s_0s

@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1209:0:1209:7|Removing redundant assignment
@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":234:0:234:7|No assignment to wire CUARTl0I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":242:0:242:7|No assignment to wire CUARTO1I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":272:0:272:7|No assignment to wire CUARTlOl

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":275:0:275:7|No assignment to wire CUARTOIl

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":287:0:287:7|No assignment to wire CUARTIll

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":290:0:290:7|No assignment to wire CUARTlll

@W: CG133 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":320:0:320:7|No assignment to CUARTOI0
@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1143:0:1143:5|Pruning register CUARTI00 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1062:0:1062:5|Pruning register CUARTII0 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1062:0:1062:5|Pruning register CUARTlI0 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":1013:0:1013:5|Pruning register CUARTl1I[7:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":895:0:895:5|Pruning register CUARTOl0[1:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":851:0:851:5|Pruning register CUARTIO0 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":851:0:851:5|Pruning register CUARTOO0 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":807:0:807:5|Pruning register CUARTI1l 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":807:0:807:5|Pruning register CUARTO1l 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":356:0:356:5|Pruning register CUARTlIl 

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":377:7:377:13|Synthesizing module RAM1K18

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":367:7:367:9|Synthesizing module GND

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":371:7:371:9|Synthesizing module VCC

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\TPSRAM_0\COM_Interface_TPSRAM_0_TPSRAM.v":5:7:5:35|Synthesizing module COM_Interface_TPSRAM_0_TPSRAM

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COM_Interface.v":9:7:9:19|Synthesizing module COM_Interface

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":722:7:722:9|Synthesizing module CCC

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\CCC_0\MDDR_TA_CCC_0_FCCC.v":5:7:5:24|Synthesizing module MDDR_TA_CCC_0_FCCC

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":24:7:24:22|Synthesizing module CoreConfigMaster

	DATA_LOCATION=32'b00000000000000111110100000000000
	ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000
	ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
	S7=32'b00000000000000000000000000000111
	S8=32'b00000000000000000000000000001000
	S9=32'b00000000000000000000000000001001
	S10=32'b00000000000000000000000000001010
	S11=32'b00000000000000000000000000001011
	S12=32'b00000000000000000000000000001100
	S13=32'b00000000000000000000000000001101
	S14=32'b00000000000000000000000000001110
	P0=32'b00000000000000000000000000001111
	P1=32'b00000000000000000000000000010000
	P2=32'b00000000000000000000000000010001
	P3=32'b00000000000000000000000000010010
	P4=32'b00000000000000000000000000010011
	P5=32'b00000000000000000000000000010100
	P6=32'b00000000000000000000000000010101
	OP_COPY=7'b0000000
   Generated name = CoreConfigMaster_Z2

@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Optimizing register bit HTRANS[0] to a constant 0
@W: CL260 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Pruning register bit 0 of HTRANS[1:0] 

@W: CG775 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z3

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v":29:7:29:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0_1_0

@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z4

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0

@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":28:7:28:30|Synthesizing module COREAHBLITE_SLAVEARBITER

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":30:7:30:28|Synthesizing module COREAHBLITE_SLAVESTAGE

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":31:7:31:28|Synthesizing module COREAHBLITE_MATRIX4X16

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
   Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Synthesizing module CoreAHBLite

	FAMILY=6'b010011
	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC_0=1'b1
	SC_1=1'b0
	SC_2=1'b1
	SC_3=1'b0
	SC_4=1'b1
	SC_5=1'b0
	SC_6=1'b1
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	M0_AHBSLOT0ENABLE=1'b0
	M0_AHBSLOT1ENABLE=1'b0
	M0_AHBSLOT2ENABLE=1'b0
	M0_AHBSLOT3ENABLE=1'b0
	M0_AHBSLOT4ENABLE=1'b0
	M0_AHBSLOT5ENABLE=1'b0
	M0_AHBSLOT6ENABLE=1'b0
	M0_AHBSLOT7ENABLE=1'b0
	M0_AHBSLOT8ENABLE=1'b0
	M0_AHBSLOT9ENABLE=1'b0
	M0_AHBSLOT10ENABLE=1'b0
	M0_AHBSLOT11ENABLE=1'b0
	M0_AHBSLOT12ENABLE=1'b0
	M0_AHBSLOT13ENABLE=1'b0
	M0_AHBSLOT14ENABLE=1'b0
	M0_AHBSLOT15ENABLE=1'b0
	M0_AHBSLOT16ENABLE=1'b1
	M1_AHBSLOT0ENABLE=1'b0
	M1_AHBSLOT1ENABLE=1'b0
	M1_AHBSLOT2ENABLE=1'b0
	M1_AHBSLOT3ENABLE=1'b0
	M1_AHBSLOT4ENABLE=1'b0
	M1_AHBSLOT5ENABLE=1'b0
	M1_AHBSLOT6ENABLE=1'b0
	M1_AHBSLOT7ENABLE=1'b0
	M1_AHBSLOT8ENABLE=1'b0
	M1_AHBSLOT9ENABLE=1'b0
	M1_AHBSLOT10ENABLE=1'b0
	M1_AHBSLOT11ENABLE=1'b0
	M1_AHBSLOT12ENABLE=1'b0
	M1_AHBSLOT13ENABLE=1'b0
	M1_AHBSLOT14ENABLE=1'b0
	M1_AHBSLOT15ENABLE=1'b0
	M1_AHBSLOT16ENABLE=1'b0
	M2_AHBSLOT0ENABLE=1'b0
	M2_AHBSLOT1ENABLE=1'b0
	M2_AHBSLOT2ENABLE=1'b0
	M2_AHBSLOT3ENABLE=1'b0
	M2_AHBSLOT4ENABLE=1'b0
	M2_AHBSLOT5ENABLE=1'b0
	M2_AHBSLOT6ENABLE=1'b0
	M2_AHBSLOT7ENABLE=1'b0
	M2_AHBSLOT8ENABLE=1'b0
	M2_AHBSLOT9ENABLE=1'b0
	M2_AHBSLOT10ENABLE=1'b0
	M2_AHBSLOT11ENABLE=1'b0
	M2_AHBSLOT12ENABLE=1'b0
	M2_AHBSLOT13ENABLE=1'b0
	M2_AHBSLOT14ENABLE=1'b0
	M2_AHBSLOT15ENABLE=1'b0
	M2_AHBSLOT16ENABLE=1'b0
	M3_AHBSLOT0ENABLE=1'b0
	M3_AHBSLOT1ENABLE=1'b0
	M3_AHBSLOT2ENABLE=1'b0
	M3_AHBSLOT3ENABLE=1'b0
	M3_AHBSLOT4ENABLE=1'b0
	M3_AHBSLOT5ENABLE=1'b0
	M3_AHBSLOT6ENABLE=1'b0
	M3_AHBSLOT7ENABLE=1'b0
	M3_AHBSLOT8ENABLE=1'b0
	M3_AHBSLOT9ENABLE=1'b0
	M3_AHBSLOT10ENABLE=1'b0
	M3_AHBSLOT11ENABLE=1'b0
	M3_AHBSLOT12ENABLE=1'b0
	M3_AHBSLOT13ENABLE=1'b0
	M3_AHBSLOT14ENABLE=1'b0
	M3_AHBSLOT15ENABLE=1'b0
	M3_AHBSLOT16ENABLE=1'b0
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SC=16'b0000000001010101
   Generated name = CoreAHBLite_Z5

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":29:7:29:22|Synthesizing module axi_interconnect

	AXI_AWIDTH=32'b00000000000000000000000000100000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	NUM_SLAVE_SLOT=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
	BASE_ID_WIDTH=32'b00000000000000000000000000000000
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_A=16'b0000010000000000
	SLAVE_B=16'b0000100000000000
	SLAVE_C=16'b0001000000000000
	SLAVE_D=16'b0010000000000000
	SLAVE_E=16'b0100000000000000
	SLAVE_F=16'b1000000000000000
	SLAVE_N=16'b0000000000000000
   Generated name = axi_interconnect_Z6

@W: CL271 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":9787:3:9787:8|Pruning bits 27 to 0 of addr_for_rready[31:0] -- not in use ...

@W: CL271 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":9449:3:9449:8|Pruning bits 27 to 0 of addr_for_wready[31:0] -- not in use ...

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":2169:3:2169:8|Pruning register SLAVE_SELECT_RADDRCH_M_r[15:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":2169:3:2169:8|Pruning register SLAVE_SELECT_WADDRCH_M_r[15:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":2169:3:2169:8|Pruning register SLAVE_SELECT_WDCH_M_r[15:0] 

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v":28:7:28:18|Synthesizing module master_stage

	AXI_AWIDTH=32'b00000000000000000000000000100000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
	NUM_SLAVE_SLOT=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
	BASE_ID_WIDTH=32'b00000000000000000000000000000000
	UNIQUE_MASTER_ID=32'b00000000000000000000000000000000
   Generated name = master_stage_32s_64s_8s_1s_4s_0s_0s

@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v":421:23:421:30|Removing redundant assignment
@N: CG179 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v":965:23:965:30|Removing redundant assignment
@W: CG133 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v":278:11:278:11|No assignment to k
@W: CG133 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\master_stage.v":279:11:279:11|No assignment to p
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:31|Synthesizing module MDDR_TA_COREAXI_0_COREAXI

	FAMILY=32'b00000000000000000000000000011000
	AXI_AWIDTH=32'b00000000000000000000000000100000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
	NUM_SLAVE_SLOT=32'b00000000000000000000000000000001
	BASE_ID_WIDTH=32'b00000000000000000000000000000000
   Generated name = MDDR_TA_COREAXI_0_COREAXI_Z7

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v":28:7:28:17|Synthesizing module slave_stage

	AXI_AWIDTH=32'b00000000000000000000000000100000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
	NUM_SLAVE_SLOT=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
	BASE_ID_WIDTH=32'b00000000000000000000000000000000
   Generated name = slave_stage_32s_64s_8s_1s_4s_0s

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":890:58:890:64|No assignment to wire AWID_S1

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":901:58:901:63|No assignment to wire WID_S1

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":933:58:933:64|No assignment to wire AWID_S2

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":944:58:944:63|No assignment to wire WID_S2

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":976:58:976:64|No assignment to wire AWID_S3

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":987:58:987:63|No assignment to wire WID_S3

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1019:58:1019:64|No assignment to wire AWID_S4

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1030:58:1030:63|No assignment to wire WID_S4

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1062:58:1062:64|No assignment to wire AWID_S5

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1073:58:1073:63|No assignment to wire WID_S5

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1105:58:1105:64|No assignment to wire AWID_S6

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1116:58:1116:63|No assignment to wire WID_S6

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1148:58:1148:64|No assignment to wire AWID_S7

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1159:58:1159:63|No assignment to wire WID_S7

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1191:58:1191:64|No assignment to wire AWID_S8

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1202:58:1202:63|No assignment to wire WID_S8

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1234:58:1234:64|No assignment to wire AWID_S9

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1245:58:1245:63|No assignment to wire WID_S9

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1277:58:1277:65|No assignment to wire AWID_S10

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1288:58:1288:64|No assignment to wire WID_S10

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:58:1320:65|No assignment to wire AWID_S11

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:58:1331:64|No assignment to wire WID_S11

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:58:1363:65|No assignment to wire AWID_S12

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:58:1374:64|No assignment to wire WID_S12

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:58:1406:65|No assignment to wire AWID_S13

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:58:1417:64|No assignment to wire WID_S13

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:58:1449:65|No assignment to wire AWID_S14

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:58:1460:64|No assignment to wire WID_S14

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1492:58:1492:65|No assignment to wire AWID_S15

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1503:58:1503:64|No assignment to wire WID_S15

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2150:55:2150:62|No assignment to wire BID_S1_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2151:30:2151:39|No assignment to wire BRESP_S1_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2152:30:2152:40|No assignment to wire BVALID_S1_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2153:55:2153:62|No assignment to wire RID_S1_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2154:30:2154:39|No assignment to wire RDATA_S1_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2155:30:2155:39|No assignment to wire RRESP_S1_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2156:30:2156:39|No assignment to wire RLAST_S1_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2157:30:2157:40|No assignment to wire RVALID_S1_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2159:55:2159:62|No assignment to wire BID_S2_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2160:30:2160:39|No assignment to wire BRESP_S2_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2161:30:2161:40|No assignment to wire BVALID_S2_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2162:55:2162:62|No assignment to wire RID_S2_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2163:30:2163:39|No assignment to wire RDATA_S2_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2164:30:2164:39|No assignment to wire RRESP_S2_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2165:30:2165:39|No assignment to wire RLAST_S2_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2166:30:2166:40|No assignment to wire RVALID_S2_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2168:55:2168:62|No assignment to wire BID_S3_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2169:30:2169:39|No assignment to wire BRESP_S3_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2170:30:2170:40|No assignment to wire BVALID_S3_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2171:55:2171:62|No assignment to wire RID_S3_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2172:30:2172:39|No assignment to wire RDATA_S3_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2173:30:2173:39|No assignment to wire RRESP_S3_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2174:30:2174:39|No assignment to wire RLAST_S3_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2175:30:2175:40|No assignment to wire RVALID_S3_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2177:55:2177:62|No assignment to wire BID_S4_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2178:30:2178:39|No assignment to wire BRESP_S4_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2179:30:2179:40|No assignment to wire BVALID_S4_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2180:55:2180:62|No assignment to wire RID_S4_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2181:30:2181:39|No assignment to wire RDATA_S4_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2182:30:2182:39|No assignment to wire RRESP_S4_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2183:30:2183:39|No assignment to wire RLAST_S4_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2184:30:2184:40|No assignment to wire RVALID_S4_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2186:55:2186:62|No assignment to wire BID_S5_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2187:30:2187:39|No assignment to wire BRESP_S5_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2188:30:2188:40|No assignment to wire BVALID_S5_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2189:55:2189:62|No assignment to wire RID_S5_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2190:30:2190:39|No assignment to wire RDATA_S5_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2191:30:2191:39|No assignment to wire RRESP_S5_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2192:30:2192:39|No assignment to wire RLAST_S5_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2193:30:2193:40|No assignment to wire RVALID_S5_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2195:55:2195:62|No assignment to wire BID_S6_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2196:30:2196:39|No assignment to wire BRESP_S6_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2197:30:2197:40|No assignment to wire BVALID_S6_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2198:55:2198:62|No assignment to wire RID_S6_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2199:30:2199:39|No assignment to wire RDATA_S6_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2200:30:2200:39|No assignment to wire RRESP_S6_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2201:30:2201:39|No assignment to wire RLAST_S6_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2202:30:2202:40|No assignment to wire RVALID_S6_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2204:55:2204:62|No assignment to wire BID_S7_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2205:30:2205:39|No assignment to wire BRESP_S7_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2206:30:2206:40|No assignment to wire BVALID_S7_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2207:55:2207:62|No assignment to wire RID_S7_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2208:30:2208:39|No assignment to wire RDATA_S7_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2209:30:2209:39|No assignment to wire RRESP_S7_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2210:30:2210:39|No assignment to wire RLAST_S7_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2211:30:2211:40|No assignment to wire RVALID_S7_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2213:55:2213:62|No assignment to wire BID_S8_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2214:30:2214:39|No assignment to wire BRESP_S8_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2215:30:2215:40|No assignment to wire BVALID_S8_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2216:55:2216:62|No assignment to wire RID_S8_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2217:30:2217:39|No assignment to wire RDATA_S8_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2218:30:2218:39|No assignment to wire RRESP_S8_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2219:30:2219:39|No assignment to wire RLAST_S8_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2220:30:2220:40|No assignment to wire RVALID_S8_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2222:55:2222:62|No assignment to wire BID_S9_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2223:30:2223:39|No assignment to wire BRESP_S9_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2224:30:2224:40|No assignment to wire BVALID_S9_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2225:55:2225:62|No assignment to wire RID_S9_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2226:30:2226:39|No assignment to wire RDATA_S9_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2227:30:2227:39|No assignment to wire RRESP_S9_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2228:30:2228:39|No assignment to wire RLAST_S9_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2229:30:2229:40|No assignment to wire RVALID_S9_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2231:55:2231:63|No assignment to wire BID_S10_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2232:30:2232:40|No assignment to wire BRESP_S10_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2233:30:2233:41|No assignment to wire BVALID_S10_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2234:55:2234:63|No assignment to wire RID_S10_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2235:30:2235:40|No assignment to wire RDATA_S10_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2236:30:2236:40|No assignment to wire RRESP_S10_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2237:30:2237:40|No assignment to wire RLAST_S10_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2238:30:2238:41|No assignment to wire RVALID_S10_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2240:55:2240:63|No assignment to wire BID_S11_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2241:30:2241:40|No assignment to wire BRESP_S11_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2242:30:2242:41|No assignment to wire BVALID_S11_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2243:55:2243:63|No assignment to wire RID_S11_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2244:30:2244:40|No assignment to wire RDATA_S11_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2245:30:2245:40|No assignment to wire RRESP_S11_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2246:30:2246:40|No assignment to wire RLAST_S11_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2247:30:2247:41|No assignment to wire RVALID_S11_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2249:55:2249:63|No assignment to wire BID_S12_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2250:30:2250:40|No assignment to wire BRESP_S12_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2251:30:2251:41|No assignment to wire BVALID_S12_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2252:55:2252:63|No assignment to wire RID_S12_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2253:30:2253:40|No assignment to wire RDATA_S12_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2254:30:2254:40|No assignment to wire RRESP_S12_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2255:30:2255:40|No assignment to wire RLAST_S12_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2256:30:2256:41|No assignment to wire RVALID_S12_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2258:55:2258:63|No assignment to wire BID_S13_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2259:30:2259:40|No assignment to wire BRESP_S13_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2260:30:2260:41|No assignment to wire BVALID_S13_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2261:55:2261:63|No assignment to wire RID_S13_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2262:30:2262:40|No assignment to wire RDATA_S13_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2263:30:2263:40|No assignment to wire RRESP_S13_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2264:30:2264:40|No assignment to wire RLAST_S13_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2265:30:2265:41|No assignment to wire RVALID_S13_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2267:55:2267:63|No assignment to wire BID_S14_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2268:30:2268:40|No assignment to wire BRESP_S14_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2269:30:2269:41|No assignment to wire BVALID_S14_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2270:55:2270:63|No assignment to wire RID_S14_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2271:30:2271:40|No assignment to wire RDATA_S14_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2272:30:2272:40|No assignment to wire RRESP_S14_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2273:30:2273:40|No assignment to wire RLAST_S14_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2274:30:2274:41|No assignment to wire RVALID_S14_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2276:55:2276:63|No assignment to wire BID_S15_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2277:30:2277:40|No assignment to wire BRESP_S15_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2278:30:2278:41|No assignment to wire BVALID_S15_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2279:55:2279:63|No assignment to wire RID_S15_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2280:30:2280:40|No assignment to wire RDATA_S15_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2281:30:2281:40|No assignment to wire RRESP_S15_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2282:30:2282:40|No assignment to wire RLAST_S15_I

@W: CG360 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2283:30:2283:41|No assignment to wire RVALID_S15_I

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP

	FAMILY=32'b00000000000000000000000000010011
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
	DEVICE_090=32'b00000000000000000000000000000000
	S0=2'b00
	S1=2'b01
	S2=2'b10
   Generated name = CoreConfigP_Z8

@W: CL113 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v":628:4:628:9|Feedback mux created for signal soft_reset_reg[14:0].
@W: CL250 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v":628:4:628:9|All reachable assignments to soft_reset_reg[14:0] assign 0, register removed by optimization
@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z9

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1530:4:1530:9|Pruning register count_sdif3[12:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1498:4:1498:9|Pruning register count_sdif2[12:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1466:4:1466:9|Pruning register count_sdif1[12:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1434:4:1434:9|Pruning register count_sdif0[12:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1404:4:1404:9|Pruning register count_sdif0_enable_q1 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1404:4:1404:9|Pruning register count_sdif1_enable_q1 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1404:4:1404:9|Pruning register count_sdif2_enable_q1 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1404:4:1404:9|Pruning register count_sdif3_enable_q1 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1404:4:1404:9|Pruning register count_sdif0_enable_rcosc 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1404:4:1404:9|Pruning register count_sdif1_enable_rcosc 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1404:4:1404:9|Pruning register count_sdif2_enable_rcosc 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1404:4:1404:9|Pruning register count_sdif3_enable_rcosc 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Pruning register count_sdif3_enable 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Pruning register count_sdif2_enable 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Pruning register count_sdif1_enable 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Pruning register count_sdif0_enable 

@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1337:4:1337:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element fpll_lock_q1.
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1382:4:1382:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1031:4:1031:9|Pruning register release_ext_reset 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1382:4:1382:9|Pruning register EXT_RESET_OUT_int 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1382:4:1382:9|Pruning register sm2_state[2:0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":756:4:756:9|Pruning register sm2_areset_n_q1 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":756:4:756:9|Pruning register sm2_areset_n_clk_base 

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\SgCore\OSC\1.0.100\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":5:7:5:26|Synthesizing module MDDR_TA_FABOSC_0_OSC

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":274:7:274:12|Synthesizing module OUTBUF

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":286:7:286:11|Synthesizing module BIBUF

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":268:7:268:11|Synthesizing module INBUF

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v":9:7:9:18|Synthesizing module MDDR_TA_HPMS

@N: CG364 :"E:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":713:7:713:14|Synthesizing module SYSRESET

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\MDDR_TA.v":9:7:9:13|Synthesizing module MDDR_TA

@N: CG364 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_top\MDDR_TA_top.v":9:7:9:17|Synthesizing module MDDR_TA_top

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA_HPMS\MDDR_TA_HPMS.v":112:14:112:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused

@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\FABOSC_0\MDDR_TA_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1031:4:1031:9|Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":63:20:63:34|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":67:20:67:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":71:20:71:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":85:20:85:29|Input SDIF0_PSEL is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":86:20:86:31|Input SDIF0_PWRITE is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":87:20:87:31|Input SDIF0_PRDATA is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":88:20:88:29|Input SDIF1_PSEL is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":89:20:89:31|Input SDIF1_PWRITE is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":90:20:90:31|Input SDIF1_PRDATA is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":91:20:91:29|Input SDIF2_PSEL is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF2_PWRITE is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":93:20:93:31|Input SDIF2_PRDATA is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":94:20:94:29|Input SDIF3_PSEL is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF3_PWRITE is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":96:20:96:31|Input SDIF3_PRDATA is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":102:20:102:37|Input SOFT_EXT_RESET_OUT is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":103:20:103:33|Input SOFT_RESET_F2M is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":104:20:104:32|Input SOFT_M3_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":105:20:105:49|Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":106:20:106:33|Input SOFT_FAB_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":107:20:107:38|Input SOFT_USER_FAB_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":108:20:108:39|Input SOFT_FDDR_CORE_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":109:20:109:39|Input SOFT_SDIF0_PHY_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":110:20:110:40|Input SOFT_SDIF0_CORE_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":111:20:111:39|Input SOFT_SDIF1_PHY_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":112:20:112:40|Input SOFT_SDIF1_CORE_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":113:20:113:39|Input SOFT_SDIF2_PHY_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":114:20:114:40|Input SOFT_SDIF2_CORE_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":115:20:115:39|Input SOFT_SDIF3_PHY_RESET is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":116:20:116:40|Input SOFT_SDIF3_CORE_RESET is unused
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v":433:4:433:9|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v":136:14:136:17|Input ACLK is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\slave_stage.v":137:14:137:20|Input ARESETN is unused
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2427:35:2427:46|*Input AWREADY_S1_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2434:34:2434:44|*Input WREADY_S1_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2150:55:2150:62|*Input BID_S1_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2151:30:2151:39|*Input BRESP_S1_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2152:30:2152:40|*Input BVALID_S1_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2450:35:2450:46|*Input ARREADY_S1_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2153:55:2153:62|*Input RID_S1_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2154:30:2154:39|*Input RDATA_S1_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2155:30:2155:39|*Input RRESP_S1_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2156:30:2156:39|*Input RLAST_S1_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2157:30:2157:40|*Input RVALID_S1_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2470:35:2470:46|*Input AWREADY_S2_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2477:34:2477:44|*Input WREADY_S2_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2159:55:2159:62|*Input BID_S2_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2160:30:2160:39|*Input BRESP_S2_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2161:30:2161:40|*Input BVALID_S2_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2493:35:2493:46|*Input ARREADY_S2_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2162:55:2162:62|*Input RID_S2_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2163:30:2163:39|*Input RDATA_S2_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2164:30:2164:39|*Input RRESP_S2_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2165:30:2165:39|*Input RLAST_S2_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2166:30:2166:40|*Input RVALID_S2_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2513:35:2513:46|*Input AWREADY_S3_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2520:34:2520:44|*Input WREADY_S3_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2168:55:2168:62|*Input BID_S3_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2169:30:2169:39|*Input BRESP_S3_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2170:30:2170:40|*Input BVALID_S3_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2536:35:2536:46|*Input ARREADY_S3_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2171:55:2171:62|*Input RID_S3_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2172:30:2172:39|*Input RDATA_S3_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2173:30:2173:39|*Input RRESP_S3_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2174:30:2174:39|*Input RLAST_S3_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2175:30:2175:40|*Input RVALID_S3_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2556:35:2556:46|*Input AWREADY_S4_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2563:34:2563:44|*Input WREADY_S4_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2177:55:2177:62|*Input BID_S4_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2178:30:2178:39|*Input BRESP_S4_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2179:30:2179:40|*Input BVALID_S4_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2579:35:2579:46|*Input ARREADY_S4_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2180:55:2180:62|*Input RID_S4_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2181:30:2181:39|*Input RDATA_S4_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2182:30:2182:39|*Input RRESP_S4_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2183:30:2183:39|*Input RLAST_S4_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2184:30:2184:40|*Input RVALID_S4_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2599:35:2599:46|*Input AWREADY_S5_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2606:34:2606:44|*Input WREADY_S5_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2186:55:2186:62|*Input BID_S5_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2187:30:2187:39|*Input BRESP_S5_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2188:30:2188:40|*Input BVALID_S5_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2622:35:2622:46|*Input ARREADY_S5_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2189:55:2189:62|*Input RID_S5_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2190:30:2190:39|*Input RDATA_S5_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2191:30:2191:39|*Input RRESP_S5_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2192:30:2192:39|*Input RLAST_S5_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2193:30:2193:40|*Input RVALID_S5_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2642:35:2642:46|*Input AWREADY_S6_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2649:34:2649:44|*Input WREADY_S6_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2195:55:2195:62|*Input BID_S6_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2196:30:2196:39|*Input BRESP_S6_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2197:30:2197:40|*Input BVALID_S6_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2665:35:2665:46|*Input ARREADY_S6_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2198:55:2198:62|*Input RID_S6_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2199:30:2199:39|*Input RDATA_S6_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2200:30:2200:39|*Input RRESP_S6_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2201:30:2201:39|*Input RLAST_S6_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2202:30:2202:40|*Input RVALID_S6_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2685:35:2685:46|*Input AWREADY_S7_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2692:34:2692:44|*Input WREADY_S7_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2204:55:2204:62|*Input BID_S7_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2205:30:2205:39|*Input BRESP_S7_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2206:30:2206:40|*Input BVALID_S7_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2708:35:2708:46|*Input ARREADY_S7_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2207:55:2207:62|*Input RID_S7_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2208:30:2208:39|*Input RDATA_S7_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2209:30:2209:39|*Input RRESP_S7_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2210:30:2210:39|*Input RLAST_S7_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2211:30:2211:40|*Input RVALID_S7_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2728:35:2728:46|*Input AWREADY_S8_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2735:34:2735:44|*Input WREADY_S8_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2213:55:2213:62|*Input BID_S8_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2214:30:2214:39|*Input BRESP_S8_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2215:30:2215:40|*Input BVALID_S8_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2751:35:2751:46|*Input ARREADY_S8_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2216:55:2216:62|*Input RID_S8_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2217:30:2217:39|*Input RDATA_S8_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2218:30:2218:39|*Input RRESP_S8_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2219:30:2219:39|*Input RLAST_S8_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2220:30:2220:40|*Input RVALID_S8_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2771:35:2771:46|*Input AWREADY_S9_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2778:34:2778:44|*Input WREADY_S9_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2222:55:2222:62|*Input BID_S9_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2223:30:2223:39|*Input BRESP_S9_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2224:30:2224:40|*Input BVALID_S9_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2794:35:2794:46|*Input ARREADY_S9_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2225:55:2225:62|*Input RID_S9_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2226:30:2226:39|*Input RDATA_S9_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2227:30:2227:39|*Input RRESP_S9_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2228:30:2228:39|*Input RLAST_S9_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2229:30:2229:40|*Input RVALID_S9_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2814:36:2814:48|*Input AWREADY_S10_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2821:35:2821:46|*Input WREADY_S10_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2231:55:2231:63|*Input BID_S10_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2232:30:2232:40|*Input BRESP_S10_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2233:30:2233:41|*Input BVALID_S10_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2837:36:2837:48|*Input ARREADY_S10_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2234:55:2234:63|*Input RID_S10_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2235:30:2235:40|*Input RDATA_S10_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2236:30:2236:40|*Input RRESP_S10_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2237:30:2237:40|*Input RLAST_S10_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2238:30:2238:41|*Input RVALID_S10_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2857:36:2857:48|*Input AWREADY_S11_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2864:35:2864:46|*Input WREADY_S11_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2240:55:2240:63|*Input BID_S11_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2241:30:2241:40|*Input BRESP_S11_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2242:30:2242:41|*Input BVALID_S11_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2880:36:2880:48|*Input ARREADY_S11_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2243:55:2243:63|*Input RID_S11_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2244:30:2244:40|*Input RDATA_S11_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2245:30:2245:40|*Input RRESP_S11_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2246:30:2246:40|*Input RLAST_S11_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2247:30:2247:41|*Input RVALID_S11_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2900:36:2900:48|*Input AWREADY_S12_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2907:35:2907:46|*Input WREADY_S12_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2249:55:2249:63|*Input BID_S12_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2250:30:2250:40|*Input BRESP_S12_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2251:30:2251:41|*Input BVALID_S12_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2923:36:2923:48|*Input ARREADY_S12_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2252:55:2252:63|*Input RID_S12_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2253:30:2253:40|*Input RDATA_S12_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2254:30:2254:40|*Input RRESP_S12_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2255:30:2255:40|*Input RLAST_S12_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2256:30:2256:41|*Input RVALID_S12_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2943:36:2943:48|*Input AWREADY_S13_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2950:35:2950:46|*Input WREADY_S13_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2258:55:2258:63|*Input BID_S13_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2259:30:2259:40|*Input BRESP_S13_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2260:30:2260:41|*Input BVALID_S13_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2966:36:2966:48|*Input ARREADY_S13_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2261:55:2261:63|*Input RID_S13_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2262:30:2262:40|*Input RDATA_S13_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2263:30:2263:40|*Input RRESP_S13_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2264:30:2264:40|*Input RLAST_S13_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2265:30:2265:41|*Input RVALID_S13_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2986:36:2986:48|*Input AWREADY_S14_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2993:35:2993:46|*Input WREADY_S14_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2267:55:2267:63|*Input BID_S14_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2268:30:2268:40|*Input BRESP_S14_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2269:30:2269:41|*Input BVALID_S14_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3009:36:3009:48|*Input ARREADY_S14_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2270:55:2270:63|*Input RID_S14_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2271:30:2271:40|*Input RDATA_S14_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2272:30:2272:40|*Input RRESP_S14_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2273:30:2273:40|*Input RLAST_S14_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2274:30:2274:41|*Input RVALID_S14_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3029:36:3029:48|*Input AWREADY_S15_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3036:35:3036:46|*Input WREADY_S15_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2276:55:2276:63|*Input BID_S15_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2277:30:2277:40|*Input BRESP_S15_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2278:30:2278:41|*Input BVALID_S15_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":3052:36:3052:48|*Input ARREADY_S15_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2279:55:2279:63|*Input RID_S15_I[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2280:30:2280:40|*Input RDATA_S15_I[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2281:30:2281:40|*Input RRESP_S15_I[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2282:30:2282:40|*Input RLAST_S15_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":2283:30:2283:41|*Input RVALID_S15_I to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":890:58:890:64|*Output AWID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":891:33:891:41|*Output AWADDR_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":892:33:892:40|*Output AWLEN_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":893:33:893:41|*Output AWSIZE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":894:33:894:42|*Output AWBURST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":895:33:895:41|*Output AWLOCK_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":896:33:896:42|*Output AWCACHE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":897:33:897:41|*Output AWPROT_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":898:33:898:42|*Output AWVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":901:58:901:63|*Output WID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":902:33:902:40|*Output WDATA_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":903:33:903:40|*Output WSTRB_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":904:33:904:40|*Output WLAST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":905:33:905:41|*Output WVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":911:33:911:41|*Output BREADY_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":913:58:913:64|*Output ARID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":914:33:914:41|*Output ARADDR_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":915:33:915:40|*Output ARLEN_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":916:33:916:41|*Output ARSIZE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":917:33:917:42|*Output ARBURST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":918:33:918:41|*Output ARLOCK_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":919:33:919:42|*Output ARCACHE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":920:33:920:41|*Output ARPROT_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":921:33:921:42|*Output ARVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":929:33:929:41|*Output RREADY_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":933:58:933:64|*Output AWID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":934:33:934:41|*Output AWADDR_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":935:33:935:40|*Output AWLEN_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":936:33:936:41|*Output AWSIZE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":937:33:937:42|*Output AWBURST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":938:33:938:41|*Output AWLOCK_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":939:33:939:42|*Output AWCACHE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":940:33:940:41|*Output AWPROT_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":941:33:941:42|*Output AWVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":944:58:944:63|*Output WID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":945:33:945:40|*Output WDATA_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":946:33:946:40|*Output WSTRB_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":947:33:947:40|*Output WLAST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":948:33:948:41|*Output WVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":954:33:954:41|*Output BREADY_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":956:58:956:64|*Output ARID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":957:33:957:41|*Output ARADDR_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":958:33:958:40|*Output ARLEN_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":959:33:959:41|*Output ARSIZE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":960:33:960:42|*Output ARBURST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":961:33:961:41|*Output ARLOCK_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":962:33:962:42|*Output ARCACHE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":963:33:963:41|*Output ARPROT_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":964:33:964:42|*Output ARVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":972:33:972:41|*Output RREADY_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":976:58:976:64|*Output AWID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":977:33:977:41|*Output AWADDR_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":978:33:978:40|*Output AWLEN_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":979:33:979:41|*Output AWSIZE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":980:33:980:42|*Output AWBURST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":981:33:981:41|*Output AWLOCK_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":982:33:982:42|*Output AWCACHE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":983:33:983:41|*Output AWPROT_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":984:33:984:42|*Output AWVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":987:58:987:63|*Output WID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":988:33:988:40|*Output WDATA_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":989:33:989:40|*Output WSTRB_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":990:33:990:40|*Output WLAST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":991:33:991:41|*Output WVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":997:33:997:41|*Output BREADY_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":999:58:999:64|*Output ARID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1000:33:1000:41|*Output ARADDR_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1001:33:1001:40|*Output ARLEN_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1002:33:1002:41|*Output ARSIZE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1003:33:1003:42|*Output ARBURST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1004:33:1004:41|*Output ARLOCK_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1005:33:1005:42|*Output ARCACHE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1006:33:1006:41|*Output ARPROT_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1007:33:1007:42|*Output ARVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1015:33:1015:41|*Output RREADY_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1019:58:1019:64|*Output AWID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1020:33:1020:41|*Output AWADDR_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1021:33:1021:40|*Output AWLEN_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1022:33:1022:41|*Output AWSIZE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1023:33:1023:42|*Output AWBURST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1024:33:1024:41|*Output AWLOCK_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1025:33:1025:42|*Output AWCACHE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1026:33:1026:41|*Output AWPROT_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1027:33:1027:42|*Output AWVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1030:58:1030:63|*Output WID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1031:33:1031:40|*Output WDATA_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1032:33:1032:40|*Output WSTRB_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1033:33:1033:40|*Output WLAST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1034:33:1034:41|*Output WVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1040:33:1040:41|*Output BREADY_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1042:58:1042:64|*Output ARID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1043:33:1043:41|*Output ARADDR_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1044:33:1044:40|*Output ARLEN_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1045:33:1045:41|*Output ARSIZE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1046:33:1046:42|*Output ARBURST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1047:33:1047:41|*Output ARLOCK_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1048:33:1048:42|*Output ARCACHE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1049:33:1049:41|*Output ARPROT_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1050:33:1050:42|*Output ARVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1058:33:1058:41|*Output RREADY_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1062:58:1062:64|*Output AWID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1063:33:1063:41|*Output AWADDR_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1064:33:1064:40|*Output AWLEN_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1065:33:1065:41|*Output AWSIZE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1066:33:1066:42|*Output AWBURST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1067:33:1067:41|*Output AWLOCK_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1068:33:1068:42|*Output AWCACHE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1069:33:1069:41|*Output AWPROT_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1070:33:1070:42|*Output AWVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1073:58:1073:63|*Output WID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1074:33:1074:40|*Output WDATA_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1075:33:1075:40|*Output WSTRB_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1076:33:1076:40|*Output WLAST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1077:33:1077:41|*Output WVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1083:33:1083:41|*Output BREADY_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1085:58:1085:64|*Output ARID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1086:33:1086:41|*Output ARADDR_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1087:33:1087:40|*Output ARLEN_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1088:33:1088:41|*Output ARSIZE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1089:33:1089:42|*Output ARBURST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1090:33:1090:41|*Output ARLOCK_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1091:33:1091:42|*Output ARCACHE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1092:33:1092:41|*Output ARPROT_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1093:33:1093:42|*Output ARVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1101:33:1101:41|*Output RREADY_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1105:58:1105:64|*Output AWID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1106:33:1106:41|*Output AWADDR_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1107:33:1107:40|*Output AWLEN_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1108:33:1108:41|*Output AWSIZE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1109:33:1109:42|*Output AWBURST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1110:33:1110:41|*Output AWLOCK_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1111:33:1111:42|*Output AWCACHE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1112:33:1112:41|*Output AWPROT_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1113:33:1113:42|*Output AWVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1116:58:1116:63|*Output WID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1117:33:1117:40|*Output WDATA_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1118:33:1118:40|*Output WSTRB_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1119:33:1119:40|*Output WLAST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1120:33:1120:41|*Output WVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1126:33:1126:41|*Output BREADY_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1128:58:1128:64|*Output ARID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1129:33:1129:41|*Output ARADDR_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1130:33:1130:40|*Output ARLEN_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1131:33:1131:41|*Output ARSIZE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1132:33:1132:42|*Output ARBURST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1133:33:1133:41|*Output ARLOCK_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1134:33:1134:42|*Output ARCACHE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1135:33:1135:41|*Output ARPROT_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1136:33:1136:42|*Output ARVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1144:33:1144:41|*Output RREADY_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1148:58:1148:64|*Output AWID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1149:33:1149:41|*Output AWADDR_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1150:33:1150:40|*Output AWLEN_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1151:33:1151:41|*Output AWSIZE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1152:33:1152:42|*Output AWBURST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1153:33:1153:41|*Output AWLOCK_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1154:33:1154:42|*Output AWCACHE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1155:33:1155:41|*Output AWPROT_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1156:33:1156:42|*Output AWVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1159:58:1159:63|*Output WID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|*Output WDATA_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1161:33:1161:40|*Output WSTRB_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1162:33:1162:40|*Output WLAST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1163:33:1163:41|*Output WVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1169:33:1169:41|*Output BREADY_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1171:58:1171:64|*Output ARID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1172:33:1172:41|*Output ARADDR_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1173:33:1173:40|*Output ARLEN_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1174:33:1174:41|*Output ARSIZE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1175:33:1175:42|*Output ARBURST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1176:33:1176:41|*Output ARLOCK_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1177:33:1177:42|*Output ARCACHE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1178:33:1178:41|*Output ARPROT_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1179:33:1179:42|*Output ARVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1187:33:1187:41|*Output RREADY_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1191:58:1191:64|*Output AWID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1192:33:1192:41|*Output AWADDR_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1193:33:1193:40|*Output AWLEN_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1194:33:1194:41|*Output AWSIZE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1195:33:1195:42|*Output AWBURST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1196:33:1196:41|*Output AWLOCK_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1197:33:1197:42|*Output AWCACHE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1198:33:1198:41|*Output AWPROT_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1199:33:1199:42|*Output AWVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1202:58:1202:63|*Output WID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|*Output WDATA_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1204:33:1204:40|*Output WSTRB_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1205:33:1205:40|*Output WLAST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1206:33:1206:41|*Output WVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1212:33:1212:41|*Output BREADY_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1214:58:1214:64|*Output ARID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1215:33:1215:41|*Output ARADDR_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1216:33:1216:40|*Output ARLEN_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1217:33:1217:41|*Output ARSIZE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1218:33:1218:42|*Output ARBURST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1219:33:1219:41|*Output ARLOCK_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1220:33:1220:42|*Output ARCACHE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1221:33:1221:41|*Output ARPROT_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1222:33:1222:42|*Output ARVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1230:33:1230:41|*Output RREADY_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1234:58:1234:64|*Output AWID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1235:33:1235:41|*Output AWADDR_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1236:33:1236:40|*Output AWLEN_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1237:33:1237:41|*Output AWSIZE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1238:33:1238:42|*Output AWBURST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1239:33:1239:41|*Output AWLOCK_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1240:33:1240:42|*Output AWCACHE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1241:33:1241:41|*Output AWPROT_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1242:33:1242:42|*Output AWVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1245:58:1245:63|*Output WID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|*Output WDATA_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1247:33:1247:40|*Output WSTRB_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1248:33:1248:40|*Output WLAST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1249:33:1249:41|*Output WVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1255:33:1255:41|*Output BREADY_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1257:58:1257:64|*Output ARID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1258:33:1258:41|*Output ARADDR_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1259:33:1259:40|*Output ARLEN_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1260:33:1260:41|*Output ARSIZE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1261:33:1261:42|*Output ARBURST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1262:33:1262:41|*Output ARLOCK_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1263:33:1263:42|*Output ARCACHE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1264:33:1264:41|*Output ARPROT_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1265:33:1265:42|*Output ARVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1273:33:1273:41|*Output RREADY_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1277:58:1277:65|*Output AWID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1278:33:1278:42|*Output AWADDR_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1279:33:1279:41|*Output AWLEN_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1280:33:1280:42|*Output AWSIZE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1281:33:1281:43|*Output AWBURST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1282:33:1282:42|*Output AWLOCK_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1283:33:1283:43|*Output AWCACHE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1284:33:1284:42|*Output AWPROT_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1285:33:1285:43|*Output AWVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1288:58:1288:64|*Output WID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1289:33:1289:41|*Output WDATA_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1290:33:1290:41|*Output WSTRB_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1291:33:1291:41|*Output WLAST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1292:33:1292:42|*Output WVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1298:33:1298:42|*Output BREADY_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1300:58:1300:65|*Output ARID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1301:33:1301:42|*Output ARADDR_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1302:33:1302:41|*Output ARLEN_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1303:33:1303:42|*Output ARSIZE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1304:33:1304:43|*Output ARBURST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1305:33:1305:42|*Output ARLOCK_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1306:33:1306:43|*Output ARCACHE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:33:1307:42|*Output ARPROT_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:33:1308:43|*Output ARVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1316:33:1316:42|*Output RREADY_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:58:1320:65|*Output AWID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:42|*Output AWADDR_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|*Output AWLEN_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1323:33:1323:42|*Output AWSIZE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1324:33:1324:43|*Output AWBURST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1325:33:1325:42|*Output AWLOCK_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1326:33:1326:43|*Output AWCACHE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1327:33:1327:42|*Output AWPROT_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:43|*Output AWVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:58:1331:64|*Output WID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:41|*Output WDATA_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|*Output WSTRB_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:41|*Output WLAST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:42|*Output WVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1341:33:1341:42|*Output BREADY_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1343:58:1343:65|*Output ARID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1344:33:1344:42|*Output ARADDR_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1345:33:1345:41|*Output ARLEN_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:42|*Output ARSIZE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1347:33:1347:43|*Output ARBURST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1348:33:1348:42|*Output ARLOCK_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1349:33:1349:43|*Output ARCACHE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:33:1350:42|*Output ARPROT_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:33:1351:43|*Output ARVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1359:33:1359:42|*Output RREADY_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:58:1363:65|*Output AWID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:42|*Output AWADDR_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|*Output AWLEN_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1366:33:1366:42|*Output AWSIZE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1367:33:1367:43|*Output AWBURST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1368:33:1368:42|*Output AWLOCK_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1369:33:1369:43|*Output AWCACHE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1370:33:1370:42|*Output AWPROT_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:43|*Output AWVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:58:1374:64|*Output WID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:41|*Output WDATA_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|*Output WSTRB_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:41|*Output WLAST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:42|*Output WVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1384:33:1384:42|*Output BREADY_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1386:58:1386:65|*Output ARID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1387:33:1387:42|*Output ARADDR_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1388:33:1388:41|*Output ARLEN_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:42|*Output ARSIZE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1390:33:1390:43|*Output ARBURST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1391:33:1391:42|*Output ARLOCK_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1392:33:1392:43|*Output ARCACHE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:33:1393:42|*Output ARPROT_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:33:1394:43|*Output ARVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1402:33:1402:42|*Output RREADY_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:58:1406:65|*Output AWID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:42|*Output AWADDR_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|*Output AWLEN_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1409:33:1409:42|*Output AWSIZE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1410:33:1410:43|*Output AWBURST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1411:33:1411:42|*Output AWLOCK_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1412:33:1412:43|*Output AWCACHE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1413:33:1413:42|*Output AWPROT_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:43|*Output AWVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:58:1417:64|*Output WID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1418:33:1418:41|*Output WDATA_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|*Output WSTRB_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1420:33:1420:41|*Output WLAST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1421:33:1421:42|*Output WVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1427:33:1427:42|*Output BREADY_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1429:58:1429:65|*Output ARID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1430:33:1430:42|*Output ARADDR_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1431:33:1431:41|*Output ARLEN_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1432:33:1432:42|*Output ARSIZE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1433:33:1433:43|*Output ARBURST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1434:33:1434:42|*Output ARLOCK_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1435:33:1435:43|*Output ARCACHE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1436:33:1436:42|*Output ARPROT_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1437:33:1437:43|*Output ARVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1445:33:1445:42|*Output RREADY_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:58:1449:65|*Output AWID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1450:33:1450:42|*Output AWADDR_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|*Output AWLEN_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1452:33:1452:42|*Output AWSIZE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1453:33:1453:43|*Output AWBURST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1454:33:1454:42|*Output AWLOCK_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1455:33:1455:43|*Output AWCACHE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1456:33:1456:42|*Output AWPROT_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1457:33:1457:43|*Output AWVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:58:1460:64|*Output WID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1461:33:1461:41|*Output WDATA_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|*Output WSTRB_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1463:33:1463:41|*Output WLAST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1464:33:1464:42|*Output WVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1470:33:1470:42|*Output BREADY_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1472:58:1472:65|*Output ARID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1473:33:1473:42|*Output ARADDR_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1474:33:1474:41|*Output ARLEN_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1475:33:1475:42|*Output ARSIZE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1476:33:1476:43|*Output ARBURST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1477:33:1477:42|*Output ARLOCK_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1478:33:1478:43|*Output ARCACHE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1479:33:1479:42|*Output ARPROT_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1480:33:1480:43|*Output ARVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1488:33:1488:42|*Output RREADY_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1492:58:1492:65|*Output AWID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1493:33:1493:42|*Output AWADDR_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|*Output AWLEN_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1495:33:1495:42|*Output AWSIZE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1496:33:1496:43|*Output AWBURST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1497:33:1497:42|*Output AWLOCK_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1498:33:1498:43|*Output AWCACHE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1499:33:1499:42|*Output AWPROT_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1500:33:1500:43|*Output AWVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1503:58:1503:64|*Output WID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1504:33:1504:41|*Output WDATA_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|*Output WSTRB_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1506:33:1506:41|*Output WLAST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1507:33:1507:42|*Output WVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1513:33:1513:42|*Output BREADY_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1515:58:1515:65|*Output ARID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1516:33:1516:42|*Output ARADDR_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1517:33:1517:41|*Output ARLEN_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1518:33:1518:42|*Output ARSIZE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1519:33:1519:43|*Output ARBURST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1520:33:1520:42|*Output ARLOCK_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1521:33:1521:43|*Output ARCACHE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1522:33:1522:42|*Output ARPROT_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1523:33:1523:43|*Output ARVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1531:33:1531:42|*Output RREADY_S15 has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":899:33:899:42|Input AWREADY_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":906:33:906:41|Input WREADY_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":908:58:908:63|Input BID_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":909:33:909:40|Input BRESP_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":910:33:910:41|Input BVALID_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":922:33:922:42|Input ARREADY_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":924:58:924:63|Input RID_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":925:33:925:40|Input RDATA_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":926:33:926:40|Input RRESP_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":927:33:927:40|Input RLAST_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":928:33:928:41|Input RVALID_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":942:33:942:42|Input AWREADY_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":949:33:949:41|Input WREADY_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":951:58:951:63|Input BID_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":952:33:952:40|Input BRESP_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":953:33:953:41|Input BVALID_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":965:33:965:42|Input ARREADY_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":967:58:967:63|Input RID_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":968:33:968:40|Input RDATA_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":969:33:969:40|Input RRESP_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":970:33:970:40|Input RLAST_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":971:33:971:41|Input RVALID_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":985:33:985:42|Input AWREADY_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":992:33:992:41|Input WREADY_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":994:58:994:63|Input BID_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":995:33:995:40|Input BRESP_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":996:33:996:41|Input BVALID_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1008:33:1008:42|Input ARREADY_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1010:58:1010:63|Input RID_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1011:33:1011:40|Input RDATA_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1012:33:1012:40|Input RRESP_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1013:33:1013:40|Input RLAST_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1014:33:1014:41|Input RVALID_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1028:33:1028:42|Input AWREADY_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1035:33:1035:41|Input WREADY_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1037:58:1037:63|Input BID_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1038:33:1038:40|Input BRESP_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1039:33:1039:41|Input BVALID_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1051:33:1051:42|Input ARREADY_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1053:58:1053:63|Input RID_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1054:33:1054:40|Input RDATA_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1055:33:1055:40|Input RRESP_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1056:33:1056:40|Input RLAST_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1057:33:1057:41|Input RVALID_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1071:33:1071:42|Input AWREADY_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1078:33:1078:41|Input WREADY_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1080:58:1080:63|Input BID_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1081:33:1081:40|Input BRESP_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1082:33:1082:41|Input BVALID_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1094:33:1094:42|Input ARREADY_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1096:58:1096:63|Input RID_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1097:33:1097:40|Input RDATA_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1098:33:1098:40|Input RRESP_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1099:33:1099:40|Input RLAST_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1100:33:1100:41|Input RVALID_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1114:33:1114:42|Input AWREADY_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1121:33:1121:41|Input WREADY_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1123:58:1123:63|Input BID_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1124:33:1124:40|Input BRESP_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1125:33:1125:41|Input BVALID_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1137:33:1137:42|Input ARREADY_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1139:58:1139:63|Input RID_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1140:33:1140:40|Input RDATA_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1141:33:1141:40|Input RRESP_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1142:33:1142:40|Input RLAST_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1143:33:1143:41|Input RVALID_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1157:33:1157:42|Input AWREADY_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1164:33:1164:41|Input WREADY_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1166:58:1166:63|Input BID_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1167:33:1167:40|Input BRESP_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1168:33:1168:41|Input BVALID_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1180:33:1180:42|Input ARREADY_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1182:58:1182:63|Input RID_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1183:33:1183:40|Input RDATA_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1184:33:1184:40|Input RRESP_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1185:33:1185:40|Input RLAST_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1186:33:1186:41|Input RVALID_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1200:33:1200:42|Input AWREADY_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1207:33:1207:41|Input WREADY_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1209:58:1209:63|Input BID_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1210:33:1210:40|Input BRESP_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1211:33:1211:41|Input BVALID_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1223:33:1223:42|Input ARREADY_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1225:58:1225:63|Input RID_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1226:33:1226:40|Input RDATA_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1227:33:1227:40|Input RRESP_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1228:33:1228:40|Input RLAST_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1229:33:1229:41|Input RVALID_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1243:33:1243:42|Input AWREADY_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1250:33:1250:41|Input WREADY_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1252:58:1252:63|Input BID_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1253:33:1253:40|Input BRESP_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1254:33:1254:41|Input BVALID_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1266:33:1266:42|Input ARREADY_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1268:58:1268:63|Input RID_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1269:33:1269:40|Input RDATA_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1270:33:1270:40|Input RRESP_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1271:33:1271:40|Input RLAST_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1272:33:1272:41|Input RVALID_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1286:33:1286:43|Input AWREADY_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1293:33:1293:42|Input WREADY_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1295:58:1295:64|Input BID_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1296:33:1296:41|Input BRESP_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1297:33:1297:42|Input BVALID_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:43|Input ARREADY_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:58:1311:64|Input RID_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|Input RDATA_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:41|Input RRESP_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|Input RLAST_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|Input RVALID_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1329:33:1329:43|Input AWREADY_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|Input WREADY_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:58:1338:64|Input BID_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1339:33:1339:41|Input BRESP_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1340:33:1340:42|Input BVALID_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:43|Input ARREADY_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:58:1354:64|Input RID_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|Input RDATA_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:41|Input RRESP_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|Input RLAST_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|Input RVALID_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1372:33:1372:43|Input AWREADY_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|Input WREADY_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:58:1381:64|Input BID_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1382:33:1382:41|Input BRESP_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1383:33:1383:42|Input BVALID_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:43|Input ARREADY_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:58:1397:64|Input RID_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|Input RDATA_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:41|Input RRESP_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|Input RLAST_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|Input RVALID_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1415:33:1415:43|Input AWREADY_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1422:33:1422:42|Input WREADY_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1424:58:1424:64|Input BID_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1425:33:1425:41|Input BRESP_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1426:33:1426:42|Input BVALID_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1438:33:1438:43|Input ARREADY_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1440:58:1440:64|Input RID_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1441:33:1441:41|Input RDATA_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1442:33:1442:41|Input RRESP_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1443:33:1443:41|Input RLAST_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1444:33:1444:42|Input RVALID_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1458:33:1458:43|Input AWREADY_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1465:33:1465:42|Input WREADY_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1467:58:1467:64|Input BID_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1468:33:1468:41|Input BRESP_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1469:33:1469:42|Input BVALID_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1481:33:1481:43|Input ARREADY_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1483:58:1483:64|Input RID_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1484:33:1484:41|Input RDATA_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1485:33:1485:41|Input RRESP_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1486:33:1486:41|Input RLAST_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1487:33:1487:42|Input RVALID_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1501:33:1501:43|Input AWREADY_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1508:33:1508:42|Input WREADY_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1510:58:1510:64|Input BID_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1511:33:1511:41|Input BRESP_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1512:33:1512:42|Input BVALID_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1524:33:1524:43|Input ARREADY_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1526:58:1526:64|Input RID_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1527:33:1527:41|Input RDATA_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1528:33:1528:41|Input RRESP_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1529:33:1529:41|Input RLAST_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\MDDR_TA\COREAXI_0\rtl\vlog\core\coreaxi.v":1530:33:1530:42|Input RVALID_S15 is unused
@W: CL246 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":1549:33:1549:42|Input port bits 27 to 0 of awaddr_buf[31:0] are unused

@W: CL246 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\COREAXI\2.1.101\rtl\vlog\core\axi_interconnect.v":1550:33:1550:42|Input port bits 27 to 0 of araddr_buf[31:0] are unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":128:15:128:23|Input port bit 0 of HTRANS_M0[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":139:15:139:23|Input port bit 0 of HTRANS_M1[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":150:15:150:23|Input port bit 0 of HTRANS_M2[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":161:15:161:23|Input port bit 0 of HTRANS_M3[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":171:15:171:22|Input port bit 1 of HRESP_S0[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":184:15:184:22|Input port bit 1 of HRESP_S1[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":197:15:197:22|Input port bit 1 of HRESP_S2[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":210:15:210:22|Input port bit 1 of HRESP_S3[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":223:15:223:22|Input port bit 1 of HRESP_S4[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":236:15:236:22|Input port bit 1 of HRESP_S5[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":249:15:249:22|Input port bit 1 of HRESP_S6[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":262:15:262:22|Input port bit 1 of HRESP_S7[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":275:15:275:22|Input port bit 1 of HRESP_S8[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":288:15:288:22|Input port bit 1 of HRESP_S9[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":301:15:301:23|Input port bit 1 of HRESP_S10[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":314:15:314:23|Input port bit 1 of HRESP_S11[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":327:15:327:23|Input port bit 1 of HRESP_S12[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":340:15:340:23|Input port bit 1 of HRESP_S13[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":353:15:353:23|Input port bit 1 of HRESP_S14[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":366:15:366:23|Input port bit 1 of HRESP_S15[1:0] is unused

@W: CL247 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":379:15:379:23|Input port bit 1 of HRESP_S16[1:0] is unused

@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input HBURST_M0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":132:15:132:22|Input HPROT_M0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input HBURST_M1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":143:15:143:22|Input HPROT_M1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input HBURST_M2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":154:15:154:22|Input HPROT_M2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":164:15:164:23|Input HBURST_M3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":165:15:165:22|Input HPROT_M3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":58:18:58:26|Input HWDATA_M1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":67:18:67:26|Input HWDATA_M2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":76:18:76:26|Input HWDATA_M3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":80:18:80:26|Input HRDATA_S0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":81:13:81:24|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":82:13:82:20|Input HRESP_S0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":91:18:91:26|Input HRDATA_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":92:13:92:24|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":93:13:93:20|Input HRESP_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":102:18:102:26|Input HRDATA_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":103:13:103:24|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":104:13:104:20|Input HRESP_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":113:18:113:26|Input HRDATA_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":114:13:114:24|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":115:13:115:20|Input HRESP_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":124:18:124:26|Input HRDATA_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":125:13:125:24|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":126:13:126:20|Input HRESP_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":135:18:135:26|Input HRDATA_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":136:13:136:24|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":137:13:137:20|Input HRESP_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":146:18:146:26|Input HRDATA_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":147:13:147:24|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":148:13:148:20|Input HRESP_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":157:18:157:26|Input HRDATA_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":158:13:158:24|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":159:13:159:20|Input HRESP_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":168:18:168:26|Input HRDATA_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":169:13:169:24|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":170:13:170:20|Input HRESP_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":179:18:179:26|Input HRDATA_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":180:13:180:24|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":181:13:181:20|Input HRESP_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":190:18:190:27|Input HRDATA_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":191:13:191:25|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":192:13:192:21|Input HRESP_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":201:18:201:27|Input HRDATA_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":202:13:202:25|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":203:13:203:21|Input HRESP_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":212:18:212:27|Input HRDATA_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":213:13:213:25|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":214:13:214:21|Input HRESP_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":223:18:223:27|Input HRDATA_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":224:13:224:25|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":225:13:225:21|Input HRESP_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":234:18:234:27|Input HRDATA_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":235:13:235:25|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":236:13:236:21|Input HRESP_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":245:18:245:27|Input HRDATA_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":246:13:246:25|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":247:13:247:21|Input HRESP_S15 is unused
@W: CL246 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":46:15:46:33|Input port bits 3 to 2 of MPREVDATASLAVEREADY[3:0] are unused

@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Trying to extract state machine for register arbRegSMCurrentState
Extracted state machine for register arbRegSMCurrentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input SDATAREADY is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input SHRESP is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":86:16:86:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":87:11:87:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":88:16:88:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":89:11:89:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":90:16:90:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":91:11:91:23|Input HREADYOUT_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":92:16:92:25|Input HRDATA_S16 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":93:11:93:23|Input HREADYOUT_S16 is unused
@W: CL246 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input port bits 15 to 0 of SDATAREADY[16:0] are unused

@W: CL246 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input port bits 15 to 0 of SHRESP[16:0] are unused

@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S0 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S2 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S3 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S4 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S5 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:24|Input HRDATA_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:22|Input HREADYOUT_S6 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:24|Input HRDATA_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:22|Input HREADYOUT_S7 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:24|Input HRDATA_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:22|Input HREADYOUT_S8 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:24|Input HRDATA_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:22|Input HREADYOUT_S9 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S10 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S11 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S12 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":86:16:86:25|Input HRDATA_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":87:11:87:23|Input HREADYOUT_S13 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":88:16:88:25|Input HRDATA_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":89:11:89:23|Input HREADYOUT_S14 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":90:16:90:25|Input HRDATA_S15 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":91:11:91:23|Input HREADYOUT_S15 is unused
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 21 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
   10001
   10010
   10011
   10100
   10101
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":234:0:234:7|*Input CUARTl0I[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":272:0:272:7|*Input CUARTlOl to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\CoreUART.v":287:0:287:7|*Input CUARTIll to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Rx_async.v":723:0:723:5|Trying to extract state machine for register CUARTOl0
Extracted state machine for register CUARTOl0
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":253:0:253:5|Trying to extract state machine for register CUARTO1ll
Extracted state machine for register CUARTO1ll
State machine has 6 reachable states with original encodings of:
   00000000000000000000000000000000
   00000000000000000000000000000001
   00000000000000000000000000000010
   00000000000000000000000000000011
   00000000000000000000000000000100
   00000000000000000000000000000101
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":76:0:76:7|Input CUARTl0I is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":79:0:79:7|Input CUARTOO1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Tx_async.v":82:0:82:7|Input CUARTIO1 is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\component\work\COM_Interface\COREUART_0\rtl\vlog\core_obfuscated\Clock_gen.v":70:0:70:16|Input BAUD_VAL_FRACTION is unused
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\Control_Logic.v":44:0:44:5|Trying to extract state machine for register fsm
Extracted state machine for register fsm
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
@W: CL260 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":108:0:108:5|Pruning register bit 9 of r_xfer_size[9:0] 

@W: CL279 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":108:0:108:5|Pruning register bits 3 to 1 of r_xfer_size[9:0] 

@W: CL260 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":70:0:70:5|Pruning register bit 9 of w_xfer_size[9:0] 

@W: CL279 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":70:0:70:5|Pruning register bits 3 to 1 of w_xfer_size[9:0] 

@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":70:0:70:5|Register bit w_xfer_size[0] is always 0, optimizing ...
@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":108:0:108:5|Register bit r_xfer_size[0] is always 0, optimizing ...
@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":70:0:70:5|Pruning register w_xfer_size[0] 

@W: CL169 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\CMD_Decoder.v":108:0:108:5|Pruning register r_xfer_size[0] 

@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWADDR_int[0] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWADDR_int[1] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWADDR_int[2] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWADDR_int[3] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWADDR_int[4] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWADDR_int[5] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Optimizing register bit AWADDR_int[6] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Optimizing register bit ARADDR[0] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Optimizing register bit ARADDR[1] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Optimizing register bit ARADDR[2] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Optimizing register bit ARADDR[3] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Optimizing register bit ARADDR[4] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Optimizing register bit ARADDR[5] to a constant 0
@W: CL190 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Optimizing register bit ARADDR[6] to a constant 0
@W: CL279 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Pruning register bits 6 to 0 of ARADDR[31:0] 

@W: CL279 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Pruning register bits 6 to 0 of AWADDR_int[31:0] 

@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Register bit AWADDR[0] is always 0, optimizing ...
@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Register bit AWADDR[1] is always 0, optimizing ...
@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Register bit AWADDR[2] is always 0, optimizing ...
@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Register bit AWADDR[3] is always 0, optimizing ...
@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Register bit AWADDR[4] is always 0, optimizing ...
@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Register bit AWADDR[5] is always 0, optimizing ...
@W: CL189 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Register bit AWADDR[6] is always 0, optimizing ...
@W: CL279 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Pruning register bits 6 to 0 of AWADDR[31:0] 

@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":581:0:581:5|Trying to extract state machine for register axi_fsm_read1_state
Extracted state machine for register axi_fsm_read1_state
State machine has 3 reachable states with original encodings of:
   001
   011
   100
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Trying to extract state machine for register axi_fsm_read_state
Extracted state machine for register axi_fsm_read_state
State machine has 2 reachable states with original encodings of:
   001
   010
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":470:0:470:5|Trying to extract state machine for register ahb_state
Extracted state machine for register ahb_state
State machine has 2 reachable states with original encodings of:
   00
   01
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":415:0:415:5|Trying to extract state machine for register rt_state
Extracted state machine for register rt_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":357:0:357:5|Trying to extract state machine for register wt_state
Extracted state machine for register wt_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Trying to extract state machine for register axi_fsm_current_state
Extracted state machine for register axi_fsm_current_state
State machine has 4 reachable states with original encodings of:
   001
   010
   011
   100
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":211:0:211:5|Trying to extract state machine for register r_loop_state
Extracted state machine for register r_loop_state
State machine has 2 reachable states with original encodings of:
   00
   01
@N: CL201 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":169:0:169:5|Trying to extract state machine for register w_loop_state
Extracted state machine for register w_loop_state
State machine has 2 reachable states with original encodings of:
   00
   01
@W: CL260 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Pruning register bit 1 of AWSIZE[1:0] 

@W: CL260 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":523:0:523:5|Pruning register bit 1 of ARSIZE[1:0] 

@W: CL279 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":254:0:254:5|Pruning register bits 7 to 1 of WSTRB[7:0] 

@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":62:22:62:24|Input BID is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":63:21:63:25|Input BRESP is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":64:21:64:26|Input BVALID is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":78:23:78:25|Input RID is unused
@W: CL159 :"D:\Learning\DDR\Design\IGL2\v0.4\MDDR_TA\hdl\AXI_IF.v":80:23:80:27|Input RRESP is unused
