#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: E:\Microsemi\Libero_SOC_v_11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-ALIM #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ns @N: : Top.vhd(17) | Top entity is set to Top. File E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\generic\smartfusion2.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\counter28.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp_pcie_hotreset.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms\CCC_0\my_hpms_CCC_0_FCCC.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms_HPMS\my_hpms_HPMS_syn.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_addrdec.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_defaultslavesm.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_slavearbiter.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_pkg.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_penablescheduler.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_ahbtoapbsm.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core\ahbtoapb3_pkg.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_iaddr_reg.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\components.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\components.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\components.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\SRAM_64x8\SRAM_64x8.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\RAM_with_wrapper\RAM_with_wrapper.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms_HPMS\my_hpms_HPMS.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_slavestage.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms\my_hpms.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms_top\my_hpms_top.vhd changed - recompiling File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\Top\Top.vhd changed - recompiling VHDL syntax check successful! Compiler output is up to date. No re-compile necessary @N:CD231 : std1164.vhd(890) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : Top.vhd(17) | Synthesizing work.top.rtl @N:CD630 : RAM_with_wrapper.vhd(17) | Synthesizing work.ram_with_wrapper.rtl @N:CD630 : SRAM_64x8.vhd(17) | Synthesizing work.sram_64x8.rtl @N:CD630 : SRAM_64x8_SRAM_64x8_0_TPSRAM.vhd(8) | Synthesizing work.sram_64x8_sram_64x8_0_tpsram.def_arch @N:CD630 : smartfusion2.vhd(588) | Synthesizing smartfusion2.ram1k18.syn_black_box Post processing for smartfusion2.ram1k18.syn_black_box @N:CD630 : smartfusion2.vhd(582) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box @N:CD630 : smartfusion2.vhd(576) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box Post processing for work.sram_64x8_sram_64x8_0_tpsram.def_arch Post processing for work.sram_64x8.rtl @N:CD630 : mux_blk.vhd(5) | Synthesizing work.mux_blk.trans Post processing for work.mux_blk.trans @N:CD630 : mem_apb_wrp.vhd(5) | Synthesizing work.mem_apb_wrp.trans @W:CD604 : mem_apb_wrp.vhd(107) | OTHERS clause is not synthesized Post processing for work.mem_apb_wrp.trans @N:CL177 : mem_apb_wrp.vhd(116) | Sharing sequential element INT_OUT. Post processing for work.ram_with_wrapper.rtl @N:CD630 : my_hpms_top.vhd(17) | Synthesizing work.my_hpms_top.rtl @N:CD630 : my_hpms.vhd(26) | Synthesizing work.my_hpms.rtl @N:CD630 : smartfusion2.vhd(786) | Synthesizing smartfusion2.sysreset.syn_black_box Post processing for smartfusion2.sysreset.syn_black_box @N:CD630 : my_hpms_HPMS.vhd(17) | Synthesizing work.my_hpms_hpms.rtl @N:CD630 : my_hpms_HPMS_syn.vhd(10) | Synthesizing work.mss_010.def_arch Post processing for work.mss_010.def_arch Post processing for work.my_hpms_hpms.rtl @N:CD630 : my_hpms_FABOSC_0_OSC.vhd(8) | Synthesizing work.my_hpms_fabosc_0_osc.def_arch @N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box Post processing for smartfusion2.clkint.syn_black_box @N:CD630 : osc_comps.vhd(19) | Synthesizing work.rcosc_25_50mhz.def_arch Post processing for work.rcosc_25_50mhz.def_arch @N:CD630 : osc_comps.vhd(79) | Synthesizing work.rcosc_25_50mhz_fab.def_arch Post processing for work.rcosc_25_50mhz_fab.def_arch Post processing for work.my_hpms_fabosc_0_osc.def_arch @W:CL240 : my_hpms_FABOSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : my_hpms_FABOSC_0_OSC.vhd(15) | XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : my_hpms_FABOSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : my_hpms_FABOSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @N:CD630 : coreresetp.vhd(27) | Synthesizing work.coreresetp.rtl @W:CD434 : coreresetp.vhd(477) | Signal soft_ext_reset_out in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(478) | Signal soft_reset_f2m in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(479) | Signal soft_m3_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(480) | Signal soft_mddr_ddr_axi_s_core_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(481) | Signal soft_fddr_core_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(482) | Signal soft_sdif0_phy_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(483) | Signal soft_sdif0_core_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(484) | Signal soft_sdif1_phy_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(485) | Signal soft_sdif1_core_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(486) | Signal soft_sdif2_phy_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(487) | Signal soft_sdif2_core_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(488) | Signal soft_sdif3_phy_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(489) | Signal soft_sdif3_core_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(490) | Signal soft_sdif0_0_core_reset in the sensitivity list is not used in the process @W:CD434 : coreresetp.vhd(491) | Signal soft_sdif0_1_core_reset in the sensitivity list is not used in the process Post processing for work.coreresetp.rtl @W:CL169 : coreresetp.vhd(1519) | Pruning register count_ddr_2(13 downto 0) @W:CL169 : coreresetp.vhd(1495) | Pruning register count_sdif3_2(12 downto 0) @W:CL169 : coreresetp.vhd(1471) | Pruning register count_sdif2_2(12 downto 0) @W:CL169 : coreresetp.vhd(1447) | Pruning register count_sdif1_2(12 downto 0) @W:CL169 : coreresetp.vhd(1423) | Pruning register count_sdif0_2(12 downto 0) @W:CL169 : coreresetp.vhd(1395) | Pruning register count_ddr_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_ddr_enable_q1_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif3_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif2_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif1_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif0_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif3_enable_q1_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif2_enable_q1_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif1_enable_q1_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif0_enable_q1_2 @W:CL169 : coreresetp.vhd(1311) | Pruning register count_sdif3_enable_3 @W:CL169 : coreresetp.vhd(1252) | Pruning register count_sdif2_enable_3 @W:CL169 : coreresetp.vhd(1193) | Pruning register count_sdif1_enable_3 @W:CL169 : coreresetp.vhd(1134) | Pruning register count_sdif0_enable_3 @W:CL169 : coreresetp.vhd(1059) | Pruning register count_ddr_enable_3 @N:CL177 : coreresetp.vhd(1331) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.vhd(1376) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.vhd(1059) | Pruning register release_ext_reset @W:CL169 : coreresetp.vhd(1376) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.vhd(1376) | Pruning register sm2_state(2 downto 0) @W:CL169 : coreresetp.vhd(792) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.vhd(792) | Pruning register sm2_areset_n_clk_base @N:CD630 : coreapb3.vhd(34) | Synthesizing coreapb3_lib.coreapb3.coreapb3_arch @W:CD604 : coreapb3.vhd(665) | OTHERS clause is not synthesized @W:CD434 : coreapb3.vhd(1453) | Signal infill in the sensitivity list is not used in the process @W:CD638 : coreapb3.vhd(616) | Signal ia_prdata is undriven @N:CD630 : coreapb3_muxptob3.vhd(33) | Synthesizing coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch Post processing for coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch Post processing for coreapb3_lib.coreapb3.coreapb3_arch @N:CD630 : coreahbtoapb3.vhd(10) | Synthesizing coreahbtoapb3_lib.coreahbtoapb3.cahbtoapb3lol @N:CD630 : coreahbtoapb3_apbaddrdata.vhd(9) | Synthesizing coreahbtoapb3_lib.cahbtoapb3lli.cahbtoapb3lol Post processing for coreahbtoapb3_lib.cahbtoapb3lli.cahbtoapb3lol @N:CD630 : coreahbtoapb3_penablescheduler.vhd(9) | Synthesizing coreahbtoapb3_lib.cahbtoapb3iii.cahbtoapb3lol Post processing for coreahbtoapb3_lib.cahbtoapb3iii.cahbtoapb3lol @N:CD630 : coreahbtoapb3_ahbtoapbsm.vhd(9) | Synthesizing coreahbtoapb3_lib.cahbtoapb3o.cahbtoapb3lol @W:CD604 : coreahbtoapb3_ahbtoapbsm.vhd(305) | OTHERS clause is not synthesized Post processing for coreahbtoapb3_lib.cahbtoapb3o.cahbtoapb3lol Post processing for coreahbtoapb3_lib.coreahbtoapb3.cahbtoapb3lol @N:CD630 : coreahblite.vhd(27) | Synthesizing coreahblite_lib.coreahblite.coreahblite_arch @N:CD630 : coreahblite_matrix4x16.vhd(25) | Synthesizing coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch @N:CD630 : coreahblite_slavestage.vhd(24) | Synthesizing coreahblite_lib.coreahblite_slavestage.trans @N:CD630 : coreahblite_slavearbiter.vhd(22) | Synthesizing coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch @W:CD604 : coreahblite_slavearbiter.vhd(391) | OTHERS clause is not synthesized Post processing for coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch Post processing for coreahblite_lib.coreahblite_slavestage.trans @N:CD630 : coreahblite_masterstage.vhd(24) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(339) | Signal sdataready in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(340) | Signal shresp in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hrdata_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hreadyout_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(357) | Signal hrdata_s16 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(357) | Signal hreadyout_s16 in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(637) | OTHERS clause is not synthesized @N:CD630 : coreahblite_defaultslavesm.vhd(22) | Synthesizing coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch @W:CD604 : coreahblite_defaultslavesm.vhd(63) | OTHERS clause is not synthesized Post processing for coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch @N:CD630 : coreahblite_addrdec.vhd(50) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(644) | Sharing sequential element addrRegSMCurrentState. @N:CD630 : coreahblite_masterstage.vhd(24) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hrdata_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hreadyout_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(637) | OTHERS clause is not synthesized @N:CD630 : coreahblite_addrdec.vhd(50) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(644) | Sharing sequential element addrRegSMCurrentState. Post processing for coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch Post processing for coreahblite_lib.coreahblite.coreahblite_arch @N:CD630 : my_hpms_CCC_0_FCCC.vhd(8) | Synthesizing work.my_hpms_ccc_0_fccc.def_arch @N:CD630 : smartfusion2.vhd(794) | Synthesizing smartfusion2.ccc.syn_black_box Post processing for smartfusion2.ccc.syn_black_box Post processing for work.my_hpms_ccc_0_fccc.def_arch Post processing for work.my_hpms.rtl Post processing for work.my_hpms_top.rtl @N:CD630 : counter28.vhd(5) | Synthesizing work.counter28.behavior Post processing for work.counter28.behavior @N:CD630 : AHBMASTER_FIC.vhd(6) | Synthesizing work.ahbmaster_fic.trans @N:CD231 : AHBMASTER_FIC.vhd(34) | Using onehot encoding for type state_type (idle="100000000000000000000000000000") Post processing for work.ahbmaster_fic.trans @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(0) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(1) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(2) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(3) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(4) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(5) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(6) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(7) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(8) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(9) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(10) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(11) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(12) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(13) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(14) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(15) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(16) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(17) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(18) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(19) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(20) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(21) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(22) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(23) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(24) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(25) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(26) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(27) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(28) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(29) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(30) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_STATUS(31) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(0) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(1) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(2) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(3) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(4) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(5) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(6) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(7) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(8) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(9) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(10) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(11) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(12) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(13) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(14) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(15) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(16) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(17) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(18) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(19) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(20) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(21) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(22) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(23) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(24) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(25) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(26) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(27) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(28) assign '0'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(29) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(30) assign '1'; register removed by optimization @W:CL111 : AHBMASTER_FIC.vhd(66) | All reachable assignments to NVM_CTRL(31) assign '0'; register removed by optimization @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HTRANS(0) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(8) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(9) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(10) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(11) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(12) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(13) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(14) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(15) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(16) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(17) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(18) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(19) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(20) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(21) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(22) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(23) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(24) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(25) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(26) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(27) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(28) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(29) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(30) to a constant 0 @W:CL190 : AHBMASTER_FIC.vhd(66) | Optimizing register bit HWDATA(31) to a constant 0 @W:CL260 : AHBMASTER_FIC.vhd(66) | Pruning register bit 0 of HTRANS(1 downto 0) @W:CL279 : AHBMASTER_FIC.vhd(66) | Pruning register bits 31 to 8 of HWDATA(31 downto 0) Post processing for work.top.rtl @N:CL201 : AHBMASTER_FIC.vhd(66) | Trying to extract state machine for register ahb_fsm_current_state Extracted state machine for register ahb_fsm_current_state State machine has 30 reachable states with original encodings of: 000000000000000000000000000001 000000000000000000000000000010 000000000000000000000000000100 000000000000000000000000001000 000000000000000000000000010000 000000000000000000000000100000 000000000000000000000001000000 000000000000000000000010000000 000000000000000000000100000000 000000000000000000001000000000 000000000000000000010000000000 000000000000000000100000000000 000000000000000001000000000000 000000000000000010000000000000 000000000000000100000000000000 000000000000001000000000000000 000000000000010000000000000000 000000000000100000000000000000 000000000001000000000000000000 000000000010000000000000000000 000000000100000000000000000000 000000001000000000000000000000 000000010000000000000000000000 000000100000000000000000000000 000001000000000000000000000000 000010000000000000000000000000 000100000000000000000000000000 001000000000000000000000000000 010000000000000000000000000000 100000000000000000000000000000 @W:CL246 : coreahblite_masterstage.vhd(45) | Input port bits 15 to 2 of sdataready(16 downto 0) are unused @W:CL247 : coreahblite_masterstage.vhd(45) | Input port bit 0 of sdataready(16 downto 0) is unused @W:CL246 : coreahblite_masterstage.vhd(46) | Input port bits 15 to 2 of shresp(16 downto 0) are unused @W:CL247 : coreahblite_masterstage.vhd(46) | Input port bit 0 of shresp(16 downto 0) is unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(59) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(60) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(61) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(62) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(63) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(64) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(65) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(66) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(67) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(45) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.vhd(46) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(57) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(58) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(59) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(60) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(61) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(62) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(63) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(64) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(65) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(66) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(67) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(87) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.vhd(88) | Input HREADYOUT_S16 is unused @N:CL201 : coreahblite_slavearbiter.vhd(398) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_matrix4x16.vhd(54) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(63) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(72) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(76) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.vhd(77) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.vhd(78) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.vhd(98) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(99) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(100) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(109) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(110) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(111) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(120) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(121) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(122) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(131) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(132) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(133) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(142) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(143) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(144) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(153) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(154) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(155) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(164) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(165) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(166) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(175) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(176) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(177) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(186) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(187) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(188) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(197) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(198) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(199) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(208) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(209) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(210) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(219) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(220) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(221) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(230) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(231) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(232) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(241) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.vhd(242) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.vhd(243) | Input HRESP_S15 is unused @W:CL247 : coreahblite.vhd(124) | Input port bit 0 of htrans_m0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(135) | Input port bit 0 of htrans_m1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(146) | Input port bit 0 of htrans_m2(1 downto 0) is unused @W:CL247 : coreahblite.vhd(157) | Input port bit 0 of htrans_m3(1 downto 0) is unused @W:CL247 : coreahblite.vhd(167) | Input port bit 1 of hresp_s0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(180) | Input port bit 1 of hresp_s1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(193) | Input port bit 1 of hresp_s2(1 downto 0) is unused @W:CL247 : coreahblite.vhd(206) | Input port bit 1 of hresp_s3(1 downto 0) is unused @W:CL247 : coreahblite.vhd(219) | Input port bit 1 of hresp_s4(1 downto 0) is unused @W:CL247 : coreahblite.vhd(232) | Input port bit 1 of hresp_s5(1 downto 0) is unused @W:CL247 : coreahblite.vhd(245) | Input port bit 1 of hresp_s6(1 downto 0) is unused @W:CL247 : coreahblite.vhd(258) | Input port bit 1 of hresp_s7(1 downto 0) is unused @W:CL247 : coreahblite.vhd(271) | Input port bit 1 of hresp_s8(1 downto 0) is unused @W:CL247 : coreahblite.vhd(284) | Input port bit 1 of hresp_s9(1 downto 0) is unused @W:CL247 : coreahblite.vhd(297) | Input port bit 1 of hresp_s10(1 downto 0) is unused @W:CL247 : coreahblite.vhd(310) | Input port bit 1 of hresp_s11(1 downto 0) is unused @W:CL247 : coreahblite.vhd(323) | Input port bit 1 of hresp_s12(1 downto 0) is unused @W:CL247 : coreahblite.vhd(336) | Input port bit 1 of hresp_s13(1 downto 0) is unused @W:CL247 : coreahblite.vhd(349) | Input port bit 1 of hresp_s14(1 downto 0) is unused @W:CL247 : coreahblite.vhd(362) | Input port bit 1 of hresp_s15(1 downto 0) is unused @W:CL247 : coreahblite.vhd(375) | Input port bit 1 of hresp_s16(1 downto 0) is unused @W:CL159 : coreahblite.vhd(127) | Input HBURST_M0 is unused @W:CL159 : coreahblite.vhd(128) | Input HPROT_M0 is unused @W:CL159 : coreahblite.vhd(138) | Input HBURST_M1 is unused @W:CL159 : coreahblite.vhd(139) | Input HPROT_M1 is unused @W:CL159 : coreahblite.vhd(149) | Input HBURST_M2 is unused @W:CL159 : coreahblite.vhd(150) | Input HPROT_M2 is unused @W:CL159 : coreahblite.vhd(160) | Input HBURST_M3 is unused @W:CL159 : coreahblite.vhd(161) | Input HPROT_M3 is unused @N:CL201 : coreahbtoapb3_ahbtoapbsm.vhd(223) | Trying to extract state machine for register CAHBTOAPB3Iol Extracted state machine for register CAHBTOAPB3Iol State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @N:CL201 : coreahbtoapb3_penablescheduler.vhd(93) | Trying to extract state machine for register CAHBtoAPB3l0i Extracted state machine for register CAHBtoAPB3l0i State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL247 : coreahbtoapb3.vhd(17) | Input port bit 0 of htrans(1 downto 0) is unused @W:CL159 : coreapb3.vhd(75) | Input IADDR is unused @W:CL159 : coreapb3.vhd(76) | Input PRESETN is unused @W:CL159 : coreapb3.vhd(77) | Input PCLK is unused @W:CL159 : coreapb3.vhd(108) | Input PRDATAS1 is unused @W:CL159 : coreapb3.vhd(109) | Input PRDATAS2 is unused @W:CL159 : coreapb3.vhd(110) | Input PRDATAS3 is unused @W:CL159 : coreapb3.vhd(111) | Input PRDATAS4 is unused @W:CL159 : coreapb3.vhd(112) | Input PRDATAS5 is unused @W:CL159 : coreapb3.vhd(113) | Input PRDATAS6 is unused @W:CL159 : coreapb3.vhd(114) | Input PRDATAS7 is unused @W:CL159 : coreapb3.vhd(115) | Input PRDATAS8 is unused @W:CL159 : coreapb3.vhd(116) | Input PRDATAS9 is unused @W:CL159 : coreapb3.vhd(117) | Input PRDATAS10 is unused @W:CL159 : coreapb3.vhd(118) | Input PRDATAS11 is unused @W:CL159 : coreapb3.vhd(119) | Input PRDATAS12 is unused @W:CL159 : coreapb3.vhd(120) | Input PRDATAS13 is unused @W:CL159 : coreapb3.vhd(121) | Input PRDATAS14 is unused @W:CL159 : coreapb3.vhd(122) | Input PRDATAS15 is unused @W:CL159 : coreapb3.vhd(125) | Input PREADYS1 is unused @W:CL159 : coreapb3.vhd(126) | Input PREADYS2 is unused @W:CL159 : coreapb3.vhd(127) | Input PREADYS3 is unused @W:CL159 : coreapb3.vhd(128) | Input PREADYS4 is unused @W:CL159 : coreapb3.vhd(129) | Input PREADYS5 is unused @W:CL159 : coreapb3.vhd(130) | Input PREADYS6 is unused @W:CL159 : coreapb3.vhd(131) | Input PREADYS7 is unused @W:CL159 : coreapb3.vhd(132) | Input PREADYS8 is unused @W:CL159 : coreapb3.vhd(133) | Input PREADYS9 is unused @W:CL159 : coreapb3.vhd(134) | Input PREADYS10 is unused @W:CL159 : coreapb3.vhd(135) | Input PREADYS11 is unused @W:CL159 : coreapb3.vhd(136) | Input PREADYS12 is unused @W:CL159 : coreapb3.vhd(137) | Input PREADYS13 is unused @W:CL159 : coreapb3.vhd(138) | Input PREADYS14 is unused @W:CL159 : coreapb3.vhd(139) | Input PREADYS15 is unused @W:CL159 : coreapb3.vhd(142) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.vhd(143) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.vhd(144) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.vhd(145) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.vhd(146) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.vhd(147) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.vhd(148) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.vhd(149) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.vhd(150) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.vhd(151) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.vhd(152) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.vhd(153) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.vhd(154) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.vhd(155) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.vhd(156) | Input PSLVERRS15 is unused @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element fpll_lock_q2. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q2. @N:CL201 : coreresetp.vhd(1311) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.vhd(1252) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.vhd(1193) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.vhd(1134) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.vhd(1059) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.vhd(96) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.vhd(123) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.vhd(126) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coreresetp.vhd(135) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.vhd(139) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.vhd(143) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.vhd(157) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.vhd(158) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.vhd(159) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.vhd(160) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.vhd(161) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.vhd(162) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.vhd(163) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.vhd(164) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.vhd(165) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.vhd(166) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.vhd(167) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.vhd(168) | Input SDIF3_PRDATA is unused @W:CL159 : coreresetp.vhd(174) | Input SOFT_EXT_RESET_OUT is unused @W:CL159 : coreresetp.vhd(175) | Input SOFT_RESET_F2M is unused @W:CL159 : coreresetp.vhd(176) | Input SOFT_M3_RESET is unused @W:CL159 : coreresetp.vhd(177) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused @W:CL159 : coreresetp.vhd(178) | Input SOFT_FDDR_CORE_RESET is unused @W:CL159 : coreresetp.vhd(179) | Input SOFT_SDIF0_PHY_RESET is unused @W:CL159 : coreresetp.vhd(180) | Input SOFT_SDIF0_CORE_RESET is unused @W:CL159 : coreresetp.vhd(181) | Input SOFT_SDIF1_PHY_RESET is unused @W:CL159 : coreresetp.vhd(182) | Input SOFT_SDIF1_CORE_RESET is unused @W:CL159 : coreresetp.vhd(183) | Input SOFT_SDIF2_PHY_RESET is unused @W:CL159 : coreresetp.vhd(184) | Input SOFT_SDIF2_CORE_RESET is unused @W:CL159 : coreresetp.vhd(185) | Input SOFT_SDIF3_PHY_RESET is unused @W:CL159 : coreresetp.vhd(186) | Input SOFT_SDIF3_CORE_RESET is unused @W:CL159 : coreresetp.vhd(190) | Input SOFT_SDIF0_0_CORE_RESET is unused @W:CL159 : coreresetp.vhd(191) | Input SOFT_SDIF0_1_CORE_RESET is unused @W:CL159 : my_hpms_FABOSC_0_OSC.vhd(10) | Input XTL is unused @W:CL247 : my_hpms_HPMS.vhd(26) | Input port bit 0 of fic_0_ahb_s_htrans(1 downto 0) is unused @N:CL201 : mem_apb_wrp.vhd(55) | Trying to extract state machine for register fsm Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : mem_apb_wrp.vhd(14) | Input PENABLE is unused At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 85MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Feb 12 12:22:18 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Feb 12 12:22:18 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Feb 12 12:22:19 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\synthesis\synwork\Top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 84MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Feb 12 12:22:20 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: Top_scck.rpt Printing clock summary report in "D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\synthesis\Top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 120MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 120MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 120MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 121MB) @W:BN132 : coreahblite_matrix4x16.vhd(5268) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.vhd(5214) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.vhd(5160) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.vhd(5106) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.vhd(5052) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4944) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_9, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4890) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_8, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4836) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_7, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4782) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_6, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4728) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_5, because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10 @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4238) | Removing instance masterstage_1 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4311) | Removing instance masterstage_2 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4384) | Removing instance masterstage_3 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_1_1_85_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4458) | Removing instance slavestage_0 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_2(trans) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance sdif0_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance sdif1_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance sdif2_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance sdif3_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance sm0_state[0:6] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(922) | Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(936) | Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(908) | Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(922) | Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(936) | Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(908) | Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1495) | Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1471) | Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1447) | Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.vhd(122) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_2(trans) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1423) | Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1519) | Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(770) | Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(894) | Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(883) | Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(872) | Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.vhd(137) | Removing instance slave_arbiter of view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_0(coreahblite_slavearbiter_arch) because there are no references to its outputs @N:BN362 : coreresetp.vhd(861) | Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(770) | Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(850) | Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(894) | Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(883) | Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(872) | Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(861) | Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(850) | Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.vhd(398) | Removing sequential instance arbRegSMCurrentState[0:15] of view:PrimLib.statemachine(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_0(coreahblite_slavearbiter_arch) because there are no references to its outputs @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @W:MT462 : mux_blk.vhd(48) | Net RAM_with_wrapper_0.mux_blk_0.wclk appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : mux_blk.vhd(49) | Net RAM_with_wrapper_0.mux_blk_0.rclk appears to be an unidentified clock source. Assuming default frequency. syn_allowed_resources : blockrams=21 set on top level netlist Top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 149MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ---------------------------------------------------------------------------------------------------------- System 100.0 MHz 10.000 system system_clkgroup my_hpms_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ========================================================================================================== @W:MT530 : ahbmaster_fic.vhd(66) | Found inferred clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock which controls 466 sequential elements including AHBMASTER_FIC_0.HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\synthesis\Top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 149MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Feb 12 12:22:21 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) @W:MO171 : coreresetp.vhd(781) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(781) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(1331) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) @N: : counter28.vhd(16) | Found counter in view:work.Top(rtl) inst counter28_0.counter_value[27:0] Encoding state machine ahb_fsm_current_state[0:29] (view:work.AHBMASTER_FIC(trans)) original code -> new code 000000000000000000000000000001 -> 000000000000000000000000000001 000000000000000000000000000010 -> 000000000000000000000000000010 000000000000000000000000000100 -> 000000000000000000000000000100 000000000000000000000000001000 -> 000000000000000000000000001000 000000000000000000000000010000 -> 000000000000000000000000010000 000000000000000000000000100000 -> 000000000000000000000000100000 000000000000000000000001000000 -> 000000000000000000000001000000 000000000000000000000010000000 -> 000000000000000000000010000000 000000000000000000000100000000 -> 000000000000000000000100000000 000000000000000000001000000000 -> 000000000000000000001000000000 000000000000000000010000000000 -> 000000000000000000010000000000 000000000000000000100000000000 -> 000000000000000000100000000000 000000000000000001000000000000 -> 000000000000000001000000000000 000000000000000010000000000000 -> 000000000000000010000000000000 000000000000000100000000000000 -> 000000000000000100000000000000 000000000000001000000000000000 -> 000000000000001000000000000000 000000000000010000000000000000 -> 000000000000010000000000000000 000000000000100000000000000000 -> 000000000000100000000000000000 000000000001000000000000000000 -> 000000000001000000000000000000 000000000010000000000000000000 -> 000000000010000000000000000000 000000000100000000000000000000 -> 000000000100000000000000000000 000000001000000000000000000000 -> 000000001000000000000000000000 000000010000000000000000000000 -> 000000010000000000000000000000 000000100000000000000000000000 -> 000000100000000000000000000000 000001000000000000000000000000 -> 000001000000000000000000000000 000010000000000000000000000000 -> 000010000000000000000000000000 000100000000000000000000000000 -> 000100000000000000000000000000 001000000000000000000000000000 -> 001000000000000000000000000000 010000000000000000000000000000 -> 010000000000000000000000000000 100000000000000000000000000000 -> 100000000000000000000000000000 @W:MO160 : ahbmaster_fic.vhd(66) | Register bit HSIZE[2] is always 0, optimizing ... @W:MO160 : ahbmaster_fic.vhd(66) | Register bit HSIZE[0] is always 0, optimizing ... @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.my_hpms(rtl) because there are no references to its outputs @W:MO160 : coreahblite_masterstage.vhd(305) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.vhd(305) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.vhd(305) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.vhd(305) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ... Encoding state machine arbRegSMCurrentState[0:15] (view:coreahblite_lib.COREAHBLITE_SLAVEARBITER(coreahblite_slavearbiter_arch)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[3] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[7] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[11] is always 0, optimizing ... @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[8] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[9] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[10] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[11] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[16] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[17] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[18] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[19] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[20] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[21] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[22] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[23] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[24] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[25] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[26] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[27] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[28] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[29] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[30] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(44) | Removing sequential instance CAHBtoAPB3ii0.CAHBToAPB3ili[31] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[8] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[9] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[10] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[11] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[12] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[13] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[14] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[15] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[16] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[17] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[18] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[19] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[20] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[21] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[22] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[23] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[24] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[25] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[26] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[27] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[28] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[29] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[30] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(80) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3lii[31] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[8] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[9] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[10] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[11] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[16] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[17] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[18] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[19] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[20] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[21] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[22] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[23] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[24] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[25] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[26] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[27] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[28] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[29] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[30] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @N:BN362 : coreahbtoapb3_apbaddrdata.vhd(66) | Removing sequential instance CAHBtoAPB3ii0.CAHBtoAPB3oii[31] of view:PrimLib.dffr(prim) in hierarchy view:coreahbtoapb3_lib.COREAHBTOAPB3(cahbtoapb3lol) because there are no references to its outputs @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[31] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[30] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[29] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[28] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[27] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[26] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[25] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[24] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[23] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[22] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[21] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[20] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[19] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[18] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[17] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[16] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[15] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[14] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[13] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[12] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[11] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[10] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[9] is always 0, optimizing ... @W:MO160 : coreahbtoapb3_apbaddrdata.vhd(98) | Register bit CAHBtoAPB3ii0.HRDATA[8] is always 0, optimizing ... Encoding state machine CAHBTOAPB3Iol[0:4] (view:coreahbtoapb3_lib.CAHBtoAPB3o(cahbtoapb3lol)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @W:BN132 : coreahbtoapb3_ahbtoapbsm.vhd(223) | Removing sequential instance my_hpms_top_0.my_hpms_0.COREAHBTOAPB3_0.CAHBTOAPB3OI0.PWRITE, because it is equivalent to instance my_hpms_top_0.my_hpms_0.COREAHBTOAPB3_0.CAHBTOAPB3OI0.CAHBTOAPB3Iol[2] Encoding state machine CAHBtoAPB3l0i[0:2] (view:coreahbtoapb3_lib.CAHBTOAPB3III(cahbtoapb3lol)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine fsm[0:3] (view:work.mem_apb_wrp(trans)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : mem_apb_wrp.vhd(55) | No possible illegal states for state machine fsm[0:3],safe FSM implementation is disabled @W:BN132 : coreahbtoapb3_penablescheduler.vhd(93) | Removing instance my_hpms_top_0.my_hpms_0.COREAHBTOAPB3_0.CAHBTOAPB3LI0.PENABLE, because it is equivalent to instance my_hpms_top_0.my_hpms_0.COREAHBTOAPB3_0.CAHBTOAPB3LI0.CAHBtoAPB3l0i[1] @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] in hierarchy view:work.Top(rtl) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 147MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 147MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 147MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 147MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 147MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 147MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 159MB peak: 161MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s 0.79ns 526 / 351 2 0h:00m:01s 0.79ns 521 / 351 3 0h:00m:01s 1.06ns 521 / 351 4 0h:00m:01s 1.08ns 521 / 351 @N:FP130 : | Promoting Net my_hpms_top_0_HPMS_READY on CLKINT I_155 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 159MB peak: 161MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 161MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 352 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 2 clock pin(s) of sequential element(s) 0 instances converted, 2 sequential instances remain driven by gated/generated clocks ========================================================== Non-Gated/Non-Generated Clocks ========================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0003 my_hpms_top_0.my_hpms_0.CCC_0.GL0_INST CLKINT 352 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST ==================================================================================================================================================== ======================================================================================================= Gated/Generated Clocks ======================================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 RAM_with_wrapper_0.mux_blk_0.wclk CFG3 1 RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0 No gated clock conversion method for cell cell:ACG4.RAM1K18 ClockId0002 RAM_with_wrapper_0.mux_blk_0.rclk CFG3 1 RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0 No gated clock conversion method for cell cell:ACG4.RAM1K18 ====================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 130MB peak: 161MB) Writing Analyst data base D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\synthesis\synwork\Top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 156MB peak: 161MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 158MB peak: 161MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 157MB peak: 161MB) @W:MT246 : my_hpms_ccc_0_fccc.vhd(106) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_hpms_top_0.my_hpms_0.CCC_0.GL0_net" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Fri Feb 12 12:22:25 2016 # Top view: Top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 1.863 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 122.9 MHz 10.000 8.137 1.863 inferred Inferred_clkgroup_0 System 100.0 MHz 1029.4 MHz 10.000 0.971 9.029 system system_clkgroup ================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 9.029 | No paths - | No paths - | No paths - my_hpms_CCC_0_FCCC|GL0_net_inferred_clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 1.863 | No paths - | No paths - | No paths - ============================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: my_hpms_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_READYOUT CoreAHBLite_0_AHBmslave16_HREADY 3.086 1.863 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[10] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[10] 0.094 2.973 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[3] 0.094 3.038 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[11] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[11] 0.094 3.041 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[5] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[5] 0.094 3.106 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[8] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[8] 0.094 3.119 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[7] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[7] 0.094 3.145 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[13] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[13] 0.094 3.180 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[9] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[9] 0.094 3.186 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[12] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[12] 0.094 3.212 ====================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_TRANS1 CoreAHBLite_0_AHBmslave16_HTRANS[1] 8.886 1.863 AHBMASTER_FIC_0.DATAOUT[0] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 AHBMASTER_FIC_0.DATAOUT[1] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 AHBMASTER_FIC_0.DATAOUT[2] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 AHBMASTER_FIC_0.DATAOUT[3] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 AHBMASTER_FIC_0.DATAOUT[4] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 AHBMASTER_FIC_0.DATAOUT[5] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 AHBMASTER_FIC_0.DATAOUT[6] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 AHBMASTER_FIC_0.DATAOUT[7] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 AHBMASTER_FIC_0.DATAOUT[8] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_295_i_0 9.707 2.352 =============================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.114 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.886 - Propagation time: 7.023 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.863 Number of logic level(s): 3 Starting point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_TRANS1 The start point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_010 F_FM0_READYOUT Out 3.086 3.086 - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.993 - 19 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST_RNIG7H92 CFG4 D In - 4.079 - my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST_RNIG7H92 CFG4 Y Out 0.276 4.355 - CoreAHBLite_0_AHBmslave16_HREADY_i_m Net - - 0.648 - 5 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState_RNID2APF CFG3 B In - 5.003 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState_RNID2APF CFG3 Y Out 0.143 5.146 - N_224 Net - - 0.622 - 4 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.hsel2_RNIJTI9I CFG4 D In - 5.768 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.hsel2_RNIJTI9I CFG4 Y Out 0.284 6.051 - CoreAHBLite_0_AHBmslave16_HTRANS[1] Net - - 0.971 - 1 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_010 F_FM0_TRANS1 In - 7.023 - =========================================================================================================================================================================================== Total path delay (propagation time + setup) of 8.137 is 4.903(60.3%) logic and 3.234(39.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.FABOSC_0.I_RCOSC_25_50MHZ System RCOSC_25_50MHZ CLKOUT FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC 0.000 9.029 ========================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.CCC_0.CCC_INST System CCC RCOSC_25_50MHZ FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC 10.000 9.029 ============================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 9.029 Number of logic level(s): 0 Starting point: my_hpms_top_0.my_hpms_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT Ending point: my_hpms_top_0.my_hpms_0.CCC_0.CCC_INST / RCOSC_25_50MHZ The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.FABOSC_0.I_RCOSC_25_50MHZ RCOSC_25_50MHZ CLKOUT Out 0.000 0.000 - FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC Net - - 0.971 - 1 my_hpms_top_0.my_hpms_0.CCC_0.CCC_INST CCC RCOSC_25_50MHZ In - 0.971 - ===================================================================================================================================== Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 157MB peak: 161MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 157MB peak: 161MB) --------------------------------------- Resource Usage Report for Top Mapping to part: m2gl010tfbga484-1 Cell usage: CCC 1 use CLKINT 2 uses MSS_010 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG1 2 uses CFG2 137 uses CFG3 119 uses CFG4 177 uses Carry primitives used for arithmetic functions: ARI1 88 uses Sequential Cells: SLE 351 uses DSP Blocks: 0 I/O ports: 43 I/O primitives: 42 INBUF 24 uses OUTBUF 18 uses Global Clock Buffers: 2 RAM/ROM usage summary Block Rams (RAM1K18) : 1 Total LUTs: 523 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 36; LUTs = 36; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 351 + 0 + 36 + 0 = 387; Total number of LUTs after P&R: 523 + 0 + 36 + 0 = 559; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 53MB peak: 161MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Fri Feb 12 12:22:25 2016 ###########################################################]