@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":5268:4:5268:16|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":5214:4:5214:16|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":5160:4:5160:16|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":5106:4:5106:16|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":5052:4:5052:16|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":4944:4:4944:15|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":4890:4:4890:15|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":4836:4:4836:15|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":4782:4:4782:15|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":4728:4:4728:15|Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: MT462 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\hdl\mux_blk.vhd":48:8:48:9|Net RAM_with_wrapper_0.mux_blk_0.wclk appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\hdl\mux_blk.vhd":49:8:49:9|Net RAM_with_wrapper_0.mux_blk_0.rclk appears to be an unidentified clock source. Assuming default frequency. 
@W: MT530 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\hdl\ahbmaster_fic.vhd":66:6:66:7|Found inferred clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock which controls 466 sequential elements including AHBMASTER_FIC_0.HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 
