@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CD720 :"E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
@N:"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\Top\Top.vhd":17:7:17:9|Top entity is set to Top.
@N: CD231 :"E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\Top\Top.vhd":17:7:17:9|Synthesizing work.top.rtl 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\RAM_with_wrapper\RAM_with_wrapper.vhd":17:7:17:22|Synthesizing work.ram_with_wrapper.rtl 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\SRAM_64x8\SRAM_64x8.vhd":17:7:17:15|Synthesizing work.sram_64x8.rtl 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\SRAM_64x8\SRAM_64x8_0\SRAM_64x8_SRAM_64x8_0_TPSRAM.vhd":8:7:8:34|Synthesizing work.sram_64x8_sram_64x8_0_tpsram.def_arch 
@N: CD630 :"E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\generic\smartfusion2.vhd":588:10:588:16|Synthesizing smartfusion2.ram1k18.syn_black_box 
@N: CD630 :"E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\generic\smartfusion2.vhd":582:10:582:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\generic\smartfusion2.vhd":576:10:576:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\mux_blk.vhd":5:7:5:13|Synthesizing work.mux_blk.trans 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\mem_apb_wrp.vhd":5:7:5:17|Synthesizing work.mem_apb_wrp.trans 
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\mem_apb_wrp.vhd":116:6:116:7|Sharing sequential element INT_OUT.
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms_top\my_hpms_top.vhd":17:7:17:17|Synthesizing work.my_hpms_top.rtl 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms\my_hpms.vhd":26:7:26:13|Synthesizing work.my_hpms.rtl 
@N: CD630 :"E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\generic\smartfusion2.vhd":786:10:786:17|Synthesizing smartfusion2.sysreset.syn_black_box 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms_HPMS\my_hpms_HPMS.vhd":17:7:17:18|Synthesizing work.my_hpms_hpms.rtl 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms_HPMS\my_hpms_HPMS_syn.vhd":10:7:10:13|Synthesizing work.mss_010.def_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.vhd":8:7:8:26|Synthesizing work.my_hpms_fabosc_0_osc.def_arch 
@N: CD630 :"E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\generic\smartfusion2.vhd":562:10:562:15|Synthesizing smartfusion2.clkint.syn_black_box 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd":19:7:19:20|Synthesizing work.rcosc_25_50mhz.def_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd":79:7:79:24|Synthesizing work.rcosc_25_50mhz_fab.def_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":27:7:27:16|Synthesizing work.coreresetp.rtl 
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q1.
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":34:7:34:14|Synthesizing coreapb3_lib.coreapb3.coreapb3_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd":33:7:33:23|Synthesizing coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3.vhd":10:7:10:19|Synthesizing coreahbtoapb3_lib.coreahbtoapb3.cahbtoapb3lol 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":9:7:9:19|Synthesizing coreahbtoapb3_lib.cahbtoapb3lli.cahbtoapb3lol 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_penablescheduler.vhd":9:7:9:19|Synthesizing coreahbtoapb3_lib.cahbtoapb3iii.cahbtoapb3lol 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_ahbtoapbsm.vhd":9:7:9:17|Synthesizing coreahbtoapb3_lib.cahbtoapb3o.cahbtoapb3lol 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite.vhd":27:7:27:17|Synthesizing coreahblite_lib.coreahblite.coreahblite_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd":25:7:25:28|Synthesizing coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_slavestage.vhd":24:7:24:28|Synthesizing coreahblite_lib.coreahblite_slavestage.trans 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_slavearbiter.vhd":22:7:22:30|Synthesizing coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd":24:7:24:29|Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_defaultslavesm.vhd":22:7:22:32|Synthesizing coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_addrdec.vhd":50:7:50:25|Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch 
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd":644:8:644:9|Sharing sequential element addrRegSMCurrentState.
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd":24:7:24:29|Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_addrdec.vhd":50:7:50:25|Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch 
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd":644:8:644:9|Sharing sequential element addrRegSMCurrentState.
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\work\my_hpms\CCC_0\my_hpms_CCC_0_FCCC.vhd":8:7:8:24|Synthesizing work.my_hpms_ccc_0_fccc.def_arch 
@N: CD630 :"E:\Microsemi\Libero_SOC_v_11.7\Synplify\lib\generic\smartfusion2.vhd":794:10:794:12|Synthesizing smartfusion2.ccc.syn_black_box 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\counter28.vhd":5:7:5:15|Synthesizing work.counter28.behavior 
@N: CD630 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\AHBMASTER_FIC.vhd":6:7:6:19|Synthesizing work.ahbmaster_fic.trans 
@N: CD231 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\AHBMASTER_FIC.vhd":34:19:34:20|Using onehot encoding for type state_type (idle="100000000000000000000000000000")
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\AHBMASTER_FIC.vhd":66:6:66:7|Trying to extract state machine for register ahb_fsm_current_state
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_slavearbiter.vhd":398:8:398:9|Trying to extract state machine for register arbRegSMCurrentState
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_ahbtoapbsm.vhd":223:0:223:1|Trying to extract state machine for register CAHBTOAPB3Iol
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_penablescheduler.vhd":93:0:93:1|Trying to extract state machine for register CAHBtoAPB3l0i
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q2.
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Trying to extract state machine for register sm0_state
@N: CL201 :"D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vhdl\hdl\mem_apb_wrp.vhd":55:6:55:7|Trying to extract state machine for register fsm
@N|Running in 64-bit mode

