@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\hdl\ahbmaster_fic.vhd":66:6:66:7|Register bit HSIZE[2] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\hdl\ahbmaster_fic.vhd":66:6:66:7|Register bit HSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd":305:8:305:9|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd":305:8:305:9|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd":305:8:305:9|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd":305:8:305:9|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_slavearbiter.vhd":398:8:398:9|Register bit arbRegSMCurrentState[3] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_slavearbiter.vhd":398:8:398:9|Register bit arbRegSMCurrentState[7] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahblite\5.2.100\rtl\vhdl\core\coreahblite_slavearbiter.vhd":398:8:398:9|Register bit arbRegSMCurrentState[11] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[31] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[30] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[29] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[28] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[27] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[26] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[25] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[24] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[23] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[22] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[21] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[20] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[19] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[18] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[17] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[16] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[15] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[14] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[13] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[12] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[11] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[10] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[9] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_apbaddrdata.vhd":98:0:98:1|Register bit CAHBtoAPB3ii0.HRDATA[8] is always 0, optimizing ...
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_ahbtoapbsm.vhd":223:0:223:1|Removing sequential instance my_hpms_top_0.my_hpms_0.COREAHBTOAPB3_0.CAHBTOAPB3OI0.PWRITE,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.COREAHBTOAPB3_0.CAHBTOAPB3OI0.CAHBTOAPB3Iol[2]
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vhdl\core_obfuscated\coreahbtoapb3_penablescheduler.vhd":93:0:93:1|Removing instance my_hpms_top_0.my_hpms_0.COREAHBTOAPB3_0.CAHBTOAPB3LI0.PENABLE,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.COREAHBTOAPB3_0.CAHBTOAPB3LI0.CAHBtoAPB3l0i[1]
@W: MT246 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vhdl\component\work\my_hpms\ccc_0\my_hpms_ccc_0_fccc.vhd":106:4:106:11|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_hpms_top_0.my_hpms_0.CCC_0.GL0_net"
