@W: MO111 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\work\my_hpms\fabosc_0\my_hpms_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module my_hpms_FABOSC_0_OSC) 
@W: MO111 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\work\my_hpms\fabosc_0\my_hpms_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module my_hpms_FABOSC_0_OSC) 
@W: MO111 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\work\my_hpms\fabosc_0\my_hpms_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module my_hpms_FABOSC_0_OSC) 
@W: MO111 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\work\my_hpms\fabosc_0\my_hpms_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module my_hpms_FABOSC_0_OSC) 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_spll_lock_q1,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG2_DONE_q1
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG2_DONE_q1,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG1_DONE_q1
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG2_DONE_clk_base,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_spll_lock_q2
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG1_DONE_clk_base,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_spll_lock_q2
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc_q1,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc
@W: BN132 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\hdl\ahbmaster_fic.v":94:0:94:5|Register bit HSIZE[2] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\hdl\ahbmaster_fic.v":94:0:94:5|Register bit HSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[31] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[30] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[29] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[28] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[27] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[26] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[25] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[24] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[23] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[22] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[21] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[20] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[19] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[18] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[17] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[16] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[15] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[14] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[13] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[12] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[11] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[10] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[9] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":278:0:278:5|Register bit CAHBtoAPB3I0l.CAHBtoAPB3lOl[8] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[31] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[30] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[29] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[28] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[27] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[26] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[25] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[24] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[23] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[22] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[21] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[20] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[19] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[18] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[17] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[16] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[15] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[14] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[13] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[12] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[11] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[10] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[9] is always 0, optimizing ...
@W: MO160 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\actel\directcore\coreahbtoapb3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v":353:0:353:5|Register bit CAHBtoAPB3I0l.HRDATA[8] is always 0, optimizing ...
@W: MT246 :"d:\appsnotes\2016\11_7_update\sram_init\igl2\m2gl_ac421_df\sram_init_igl2_vlog\component\work\my_hpms\ccc_0\my_hpms_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock my_hpms_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_hpms_top_0.my_hpms_0.FABOSC_0.RCOSC_25_50MHZ_CCC"
@W: MT420 |Found inferred clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_hpms_top_0.my_hpms_0.CCC_0.GL0_net"
