#--  Synopsys, Inc.
#--  Version J-2015.03M-SP1-2
#--  Project file D:\Appsnotes\2016\11_7_update\SRAM_init\IGL2\M2GL_AC421_DF\SRAM_init_IGL2_vlog\synthesis\run_options.txt
#--  Written on Fri Feb 12 11:28:51 2016


#project files
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/hdl/AHBMASTER_FIC.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/SRAM_64x8/SRAM_64x8_0/SRAM_64x8_SRAM_64x8_0_TPSRAM.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/SRAM_64x8/SRAM_64x8.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/hdl/mem_apb_wrp.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/hdl/mux_blk.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/RAM_with_wrapper/RAM_with_wrapper.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/hdl/Count28.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/my_hpms/CCC_0/my_hpms_CCC_0_FCCC.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/my_hpms/FABOSC_0/my_hpms_FABOSC_0_OSC.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/my_hpms_HPMS/my_hpms_HPMS_syn.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/my_hpms_HPMS/my_hpms_HPMS.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_ahbtoapbsm.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_penablescheduler.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_apbaddrdata.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3.v"
add_file -verilog -lib COREAPB3_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/my_hpms/my_hpms.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/my_hpms_top/my_hpms_top.v"
add_file -verilog "D:/Appsnotes/2016/11_7_update/SRAM_init/IGL2/M2GL_AC421_DF/SRAM_init_IGL2_vlog/component/work/Top/Top.v"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology IGLOO2
set_option -part M2GL010T
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "Top"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./Top.edn"
impl -active "synthesis"
