Project Settings
Project Name | Top_syn | Implementation Name | synthesis
Top Module | work.Top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 67 | 443 | 0 | - | 0m:01s | - | 2/12/2016 12:22:19 PM
(premap) | Complete | 94 | 13 | 0 | 0m:00s | 0m:00s | 149MB | 2/12/2016 12:22:21 PM
(fpga_mapper) | Complete | 76 | 40 | 0 | 0m:03s | 0m:03s | 161MB | 2/12/2016 12:22:25 PM
Multi-srs Generator | Complete |  |  |  | 0m:00s |  |  | 2/12/2016 12:22:20 PM
Area Summary
Carry Cells | 88 | Sequential Cells | 351
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 42
Global Clock Buffers | 2 | Block Rams (RAM1K18) (v_ram) | 1
LUTs (total_luts) | 523 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
my_hpms_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 122.9 MHz | 1.863
System | 100.0 MHz | 1029.4 MHz | 9.029
Optimizations Summary
Combined Clock Conversion | 1 / 2 |  |