Project Settings
Project Name | Top_syn | Implementation Name | synthesis
Top Module | Top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 67 | 307 | 0 | - | 0m:02s | - | 2/12/2016 11:28:52 AM
(premap) | Complete | 43 | 14 | 0 | 0m:00s | 0m:00s | 149MB | 2/12/2016 11:28:55 AM
(fpga_mapper) | Complete | 93 | 92 | 0 | 0m:03s | 0m:03s | 156MB | 2/12/2016 11:28:59 AM
Multi-srs Generator | Complete |  |  |  | 0m:00s |  |  | 2/12/2016 11:28:54 AM
Area Summary
Carry Cells | 88 | Sequential Cells | 329
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 42
Global Clock Buffers | 2 | Block Rams (RAM1K18) (v_ram) | 1
LUTs (total_luts) | 499 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
my_hpms_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 127.9 MHz | 2.183
my_hpms_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA
Optimizations Summary
Combined Clock Conversion | 1 / 2 |  |