#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I53165 # Wed Mar 31 12:54:19 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\igloo2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\AHBMASTER_FIC.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\RAM_with_wrapper\SRAM_64x8_0\RAM_with_wrapper_SRAM_64x8_0_TPSRAM.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\mem_apb_wrp.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\mux_blk.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\RAM_with_wrapper\RAM_with_wrapper.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3_ahbtoapbsm.v" (library COREAHBTOAPB3_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3_penablescheduler.v" (library COREAHBTOAPB3_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v" (library COREAHBTOAPB3_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3.v" (library COREAHBTOAPB3_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\AHBMASTER_FIC_RAM\AHBMASTER_FIC_RAM.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\FF_BLKS\FF_BLKS.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CCC_0\SystemBuilder_CCC_0_FCCC.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\FABOSC_0\SystemBuilder_FABOSC_0_OSC.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder_HPMS\SystemBuilder_HPMS_syn.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder_HPMS\SystemBuilder_HPMS.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\SystemBuilder.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\cnt34.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\counter_delay.v" (library work) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v" (library CORESYSSERVICES_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v" (library CORESYSSERVICES_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v" (library CORESYSSERVICES_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v" (library CORESYSSERVICES_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v" (library CORESYSSERVICES_LIB) @I::"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! File C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\AHBMASTER_FIC_RAM\AHBMASTER_FIC_RAM.v changed - recompiling File C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v changed - recompiling File C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CCC_0\SystemBuilder_CCC_0_FCCC.v changed - recompiling File C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\FABOSC_0\SystemBuilder_FABOSC_0_OSC.v changed - recompiling File C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v changed - recompiling File C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\SystemBuilder.v changed - recompiling Selecting top level module top @N:CG775 : CoreSysServices.v(30) | Component top_CORESYSSERVICES_0_CORESYSSERVICES not found in library "work" or "__hyper__lib__", but found in library CORESYSSERVICES_LIB @N:CG775 : coreahbtoapb3.v(8) | Component COREAHBTOAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAHBTOAPB3_LIB @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : AHBMASTER_FIC.v(4) | Synthesizing module AHBMASTER_FIC in library work. Idle=4'b0000 Read_NVM_0=4'b0001 Read_NVM_1=4'b0010 Read_NVM_2=4'b0011 Write_RAM_0=4'b0100 Write_RAM_1=4'b0101 Write_RAM_2=4'b0110 Write_RAM_3=4'b0111 Write_RAM_4=4'b1000 Write_RAM_5=4'b1001 Write_RAM_6=4'b1010 Write_RAM_7=4'b1011 Write_RAM_8=4'b1100 Write_RAM_9=4'b1101 Write_RAM_10=4'b1110 Write_RAM_11=4'b1111 Data_size=32'b00000000000000000000000000001000 Generated name = AHBMASTER_FIC_Z1 Running optimization stage 1 on AHBMASTER_FIC_Z1 ....... @W:CL113 : AHBMASTER_FIC.v(74) | Feedback mux created for signal HWDATA[31:8]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL250 : AHBMASTER_FIC.v(74) | All reachable assignments to HWDATA[31:8] assign 0, register removed by optimization @W:CL190 : AHBMASTER_FIC.v(74) | Optimizing register bit HTRANS[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : AHBMASTER_FIC.v(74) | Pruning register bit 0 of HTRANS[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : coreahbtoapb3_ahbtoapbsm.v(8) | Synthesizing module CAHBtoAPB3O in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 CAHBtoAPB3O0=2'b00 CAHBtoAPB3I0=2'b01 CAHBtoAPB3l0=3'b000 CAHBtoAPB3O1=3'b001 CAHBtoAPB3I1=3'b010 CAHBtoAPB3l1=3'b011 CAHBtoAPB3OOI=3'b100 Generated name = CAHBtoAPB3O_0s_0_1_0_1_2_3_4 Running optimization stage 1 on CAHBtoAPB3O_0s_0_1_0_1_2_3_4 ....... @N:CG364 : coreahbtoapb3_penablescheduler.v(8) | Synthesizing module CAHBtoAPB3OIl in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 CAHBtoAPB3l0=2'b00 CAHBtoAPB3OOI=2'b01 CAHBtoAPB3IIl=2'b10 Generated name = CAHBtoAPB3OIl_0s_0_1_2 Running optimization stage 1 on CAHBtoAPB3OIl_0s_0_1_2 ....... @N:CG364 : coreahbtoapb3_apbaddrdata.v(8) | Synthesizing module CAHBtoAPB3l1I in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CAHBtoAPB3l1I_0s Running optimization stage 1 on CAHBtoAPB3l1I_0s ....... @N:CG364 : coreahbtoapb3.v(8) | Synthesizing module COREAHBTOAPB3 in library COREAHBTOAPB3_LIB. FAMILY=32'b00000000000000000000000000011000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBTOAPB3_24s_0s Running optimization stage 1 on COREAHBTOAPB3_24s_0s ....... @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b011100 UPR_NIBBLE_POSN=4'b0110 FAMILY=32'b00000000000000000000000000011000 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z2 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z2 ....... @N:CG364 : mem_apb_wrp.v(19) | Synthesizing module mem_apb_wrp in library work. DATA_WIDTH=32'b00000000000000000000000000001000 ADDR_WIDTH=32'b00000000000000000000000000001000 Generated name = mem_apb_wrp_8s_8s Running optimization stage 1 on mem_apb_wrp_8s_8s ....... @N:CG364 : mux_blk.v(19) | Synthesizing module mux_blk in library work. Running optimization stage 1 on mux_blk ....... @N:CG364 : igloo2.v(382) | Synthesizing module RAM1K18 in library work. Running optimization stage 1 on RAM1K18 ....... @N:CG364 : igloo2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : igloo2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : RAM_with_wrapper_SRAM_64x8_0_TPSRAM.v(5) | Synthesizing module RAM_with_wrapper_SRAM_64x8_0_TPSRAM in library work. Running optimization stage 1 on RAM_with_wrapper_SRAM_64x8_0_TPSRAM ....... @N:CG364 : RAM_with_wrapper.v(9) | Synthesizing module RAM_with_wrapper in library work. Running optimization stage 1 on RAM_with_wrapper ....... @N:CG364 : AHBMASTER_FIC_RAM.v(9) | Synthesizing module AHBMASTER_FIC_RAM in library work. Running optimization stage 1 on AHBMASTER_FIC_RAM ....... @N:CG364 : counter_delay.v(21) | Synthesizing module counter_delay in library work. @N:CG179 : counter_delay.v(42) | Removing redundant assignment. Running optimization stage 1 on counter_delay ....... @N:CG364 : cnt34.v(7) | Synthesizing module cnt34 in library work. Running optimization stage 1 on cnt34 ....... @N:CG364 : CoreSysServices_UserIF.v(30) | Synthesizing module CoreSysServices_UserIF in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000001 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000000 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = CoreSysServices_UserIF_Z3 Running optimization stage 1 on CoreSysServices_UserIF_Z3 ....... @W:CL169 : CoreSysServices_UserIF.v(789) | Pruning unused register cuhprior_flushdone_d3. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(738) | Pruning unused register pord_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(738) | Pruning unused register pord_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(592) | Pruning unused register custatus_out_en_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(522) | Pruning unused register pord_comb_d1. Make sure that there are no unused intermediate registers. @W:CL207 : CoreSysServices_UserIF.v(719) | All reachable assignments to pord assign 0, register removed by optimization. @W:CL190 : CoreSysServices_UserIF.v(505) | Optimizing register bit hprior_kp_busy_high to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 5 to 2 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_UserIF.v(653) | Pruning register bit 0 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 7 to 5 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_UserIF.v(653) | Pruning register bit 3 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 1 to 0 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL169 : CoreSysServices_UserIF.v(505) | Pruning unused register hprior_kp_busy_high. Make sure that there are no unused intermediate registers. @N:CG364 : igloo2.v(837) | Synthesizing module FLASH_FREEZE in library work. Running optimization stage 1 on FLASH_FREEZE ....... @N:CG364 : CoreSysServices_CmdDec.v(30) | Synthesizing module CoreSysServices_CmdDec in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000001 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000000 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 C_IDLE=2'b00 C_REQ_PHASE=2'b01 C_RESP_PHASE=2'b10 REQ_IDLE=6'b000000 REQ_WAIT_MEMWR1=6'b000001 REQ_MEMWR_DESC=6'b000010 REQ_WAIT_MEMWR2=6'b000011 REQ_MEMWR_DATA=6'b000100 REQ_PHASE=6'b000101 REQ_FIIC_INT=6'b000111 REQ_POLL_CINT1=6'b001000 REQ_RDCOMM_STATUS1=6'b001001 REQ_WRCOMM_CTRL=6'b001010 REQ_WRCOMM_INT=6'b001011 REQ_WRCOMM_FRM=6'b001100 REQ_WRCOMM_DATA=6'b001101 REQ_POLL_CINT2=6'b001110 REQ_RDCOMM_STATUS2=6'b001111 REQ_WAIT_REG1=6'b010000 REQ_WAIT_REG2=6'b010001 REQ_WAIT_REG3=6'b010010 REQ_WAIT_REG4=6'b010011 REQ_WAIT_REG5=6'b010100 REQ_WAIT_REG6=6'b010101 REQ_WAIT_REG7=6'b010110 REQ_WAIT_REG8=6'b010111 REQ_WAIT_REG9=6'b011000 REQ_RD_INT=6'b011011 REQ_RDCOMM_INT=6'b011100 REQ_WAIT_REG10=6'b100001 REQ_WAIT_REG11=6'b100010 REQ_WAIT_REG12=6'b100011 REQ_WAIT_REG13=6'b100100 REQ_WRCOMM_CTRL2=6'b100101 REQ_WRCOMM_CTRL3=6'b100110 REQ_WRCOMM_CTRL4=6'b100111 REQ_WRCOMM_INT2=6'b101000 REQ_WAIT_MEMWR22=6'b101001 REQ_MEMWR_DATA1=6'b101010 REQ_WAIT_ASYNCRD1=6'b101011 REQ_RDCOMM_ASYNCFRM1=6'b101100 REQ_WAIT_ASYNCRD2=6'b101101 REQ_RDCOMM_ASYNCFRM2=6'b101110 REQ_ASYNC_OUT1=6'b110000 REQ_ASYNC_OUT2=6'b110001 REQ_WAIT_REG14=6'b110010 REQ_WRCOMM_DESC2=6'b110011 REQ_WAIT_REG15=6'b110100 RESP_IDLE=6'b000000 RESP_PHASE=6'b000001 RESP_RDCOMM_STATUS=6'b000011 RESP_RDCOMM_FRM=6'b000100 RESP_RDCOMM_DESC=6'b000101 RESP_RDCOMM_DATA=6'b000110 RESP_WAIT_MEMRD=6'b000111 RESP_MEMRD=6'b001000 RESP_POLL_CINT1=6'b001001 RESP_POLL_CINT4=6'b001100 RESP_REG1=6'b001101 RESP_REG4=6'b010000 RESP_REG5=6'b010001 RESP_REG6=6'b010010 RESP_REG7=6'b010011 RESP_REG8=6'b010100 RESP_REG9=6'b010101 RESP_WRCOMM_CTRL1=6'b010110 RESP_WAIT_REG11=6'b010111 RESP_WRCOMM_CTRL2=6'b011000 RESP_WAIT_REG12=6'b011001 RESP_RDCOMM_STATUS3=6'b011011 RESP_WRCOMM_INT3=6'b100100 RESP_WAIT_REG13=6'b100101 RESP_FIIC_INT=6'b100110 RESP_WAIT_REG14=6'b100111 RESP_WAIT_ASYNCRD1=6'b101000 RESP_RDCOMM_ASYNCFRM1=6'b101001 RESP_ASYNC_OUT1=6'b101100 RESP_WAIT_ASYNCRD3=6'b101110 RESP_RDCOMM_ASYNCFRM3=6'b101111 RESP_ASYNC_OUT3=6'b110000 ASYNCEVENT_POLL_IDLE=4'b0000 ASYNCEVENT_POLL_WAIT=4'b0001 ASYNCEVENT_POLL_CINT=4'b0010 ASYNCEVENT_REG1=4'b0011 ASYNCEVENT_RDCOMM_STATUS=4'b0100 ASYNCEVENT_WAIT_RD1=4'b0101 ASYNCEVENT_RDCOMM_FRM1=4'b0110 ASYNCEVENT_RDCOMM_OUT1=4'b0111 ASYNCEVENT_WAIT=4'b1000 ASYNCEVENT_PHASE=4'b1001 ASYNCEVENT_WAIT_REG11=4'b1010 ASYNCEVENT_WRCOMM_CTRL1=4'b1011 ASYNCEVENT_WAIT_REG13=4'b1100 ASYNCEVENT_FIIC_INT=4'b1101 ASYNCEVENT_WAIT_REG14=4'b1110 ASYNCEVENT_WRCOMM_INT3=4'b1111 COMM_CTRL_REG=32'b01000000000000010110000000000000 COMM_STATUS_REG=32'b01000000000000010110000000000100 COMM_INTEN_REG=32'b01000000000000010110000000001000 COMM_DATA8_REG=32'b01000000000000010110000000010000 COMM_DATA32_REG=32'b01000000000000010110000000010100 COMM_FRM8_REG=32'b01000000000000010110000000011000 COMM_FRM32_REG=32'b01000000000000010110000000011100 Generated name = CoreSysServices_CmdDec_Z4 @N:CG179 : CoreSysServices_CmdDec.v(1912) | Removing redundant assignment. @W:CG133 : CoreSysServices_CmdDec.v(418) | Object cfwr_req_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(436) | Object cfsrc_addr_int is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(437) | Object cfdst_addr_int is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(447) | Object memwr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(470) | Object req_srcreg_addr is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(472) | Object req_srcreg_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(512) | Object cuhprior_flushdone_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : CoreSysServices_CmdDec.v(555) | Removing wire cfwr_req_int, as there is no assignment to it. @W:CG360 : CoreSysServices_CmdDec.v(557) | Removing wire cfwr_req_c, as there is no assignment to it. @W:CG360 : CoreSysServices_CmdDec.v(563) | Removing wire cfdata_w_o, as there is no assignment to it. Running optimization stage 1 on CoreSysServices_CmdDec_Z4 ....... @W:CL318 : CoreSysServices_CmdDec.v(372) | *Output cutrans_done_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL168 : CoreSysServices_CmdDec.v(2927) | Removing instance FLASH_FREEZE_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL169 : CoreSysServices_CmdDec.v(2980) | Pruning unused register FF_exit. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2962) | Pruning unused register FF_exit_led. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2949) | Pruning unused register FF_entry_led. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2939) | Pruning unused register FF_entry. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2889) | Pruning unused register cunvm_bfr_iapverify_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2770) | Pruning unused register latchen_hrdata_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register fiicreg_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register commctrlreg_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register commpoll_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1924) | Pruning unused register set_puf_getkcnum_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1906) | Pruning unused register wait_count[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1731) | Pruning unused register fctrans_done_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1611) | Pruning unused register pord_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1611) | Pruning unused register pord_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1582) | Pruning unused register req_phase_active_pulse. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1532) | Pruning unused register resp_data_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1532) | Pruning unused register req_phase_active_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1033) | Pruning unused register resp_desc_done. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1033) | Pruning unused register resp_frm_done. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1015) | Pruning unused register req_desc_done. Make sure that there are no unused intermediate registers. @W:CL271 : CoreSysServices_CmdDec.v(1924) | Pruning unused bits 31 to 8 of fcdataout_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL113 : CoreSysServices_CmdDec.v(2811) | Feedback mux created for signal cutamper_msg[7:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL207 : CoreSysServices_CmdDec.v(2786) | All reachable assignments to cutamper_msg_valid assign 0, register removed by optimization. @W:CL177 : CoreSysServices_CmdDec.v(2461) | Sharing sequential element fcpop_d1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element tamper_fail_valid_r. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element tamper_detect_valid_r. Add a syn_preserve attribute to the element to prevent sharing. @W:CL207 : CoreSysServices_CmdDec.v(1594) | All reachable assignments to pord assign 0, register removed by optimization. @W:CL250 : CoreSysServices_CmdDec.v(2811) | All reachable assignments to cutamper_msg[7:0] assign 0, register removed by optimization @W:CL190 : CoreSysServices_CmdDec.v(1944) | Optimizing register bit cutamper_detect_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1944) | Optimizing register bit cutamper_fail_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 31 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 29 to 17 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 15 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 12 to 5 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 1 to 0 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 31 to 30 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 28 to 8 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 6 to 5 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 2 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 0 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL169 : CoreSysServices_CmdDec.v(1944) | Pruning unused register cutamper_detect_valid. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1944) | Pruning unused register cutamper_fail_valid. Make sure that there are no unused intermediate registers. @N:CG364 : CoreSysServices_FSMCtrl.v(30) | Synthesizing module CoreSysServices_FSMCtrl in library CORESYSSERVICES_LIB. @W:CG133 : CoreSysServices_FSMCtrl.v(236) | Object rvalid_out_en_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_FSMCtrl.v(237) | Object rvalid_out_en_d2 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : CoreSysServices_FSMCtrl.v(245) | Removing wire fmhaddr_lat, as there is no assignment to it. Running optimization stage 1 on CoreSysServices_FSMCtrl ....... @W:CL169 : CoreSysServices_FSMCtrl.v(952) | Pruning unused register busreq_prev. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(934) | Pruning unused register pop_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(868) | Pruning unused register fmhtrans_int2[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(732) | Pruning unused register haddr_prev[29:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(709) | Pruning unused register latch_addr_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(709) | Pruning unused register latch_addr_d3. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(639) | Pruning unused register latch_addr_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(627) | Pruning unused register state_prev_clk[3:0]. Make sure that there are no unused intermediate registers. @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_FSMCtrl.v(853) | Optimizing register bit fmhtrans_int[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CoreSysServices_FSMCtrl.v(853) | Pruning register bit 0 of fmhtrans_int[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_FSMCtrl.v(293) | Pruning register bits 2 to 1 of fmhburst_d1[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : CoreSysServices_AHBLMasterIF.v(30) | Synthesizing module CoreSysServices_AHBLMasterIF in library CORESYSSERVICES_LIB. Running optimization stage 1 on CoreSysServices_AHBLMasterIF ....... @N:CG364 : CoreSysServices.v(30) | Synthesizing module top_CORESYSSERVICES_0_CORESYSSERVICES in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000000 CRYPTOAES128DATAPTR=32'b00100000000000000000000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000000000000000000 CRYPTODSTADPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000001 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000000 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = top_CORESYSSERVICES_0_CORESYSSERVICES_Z5 @W:CG360 : CoreSysServices.v(259) | Removing wire cfburst_len_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(265) | Removing wire ustatus_resp_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(266) | Removing wire ubusy_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(267) | Removing wire udata_en_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(268) | Removing wire udata_valid_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(269) | Removing wire udata_r_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(275) | Removing wire uclatchpord_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(281) | Removing wire uccrypto_opmode_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(304) | Removing wire cudata_wen_o, as there is no assignment to it. Running optimization stage 1 on top_CORESYSSERVICES_0_CORESYSSERVICES_Z5 ....... @N:CG364 : FF_FSM.v(1) | Synthesizing module ff_fsm in library work. Running optimization stage 1 on ff_fsm ....... @W:CL190 : FF_FSM.v(232) | Optimizing register bit serv_cmdbyte_req[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : FF_FSM.v(232) | Optimizing register bit serv_cmdbyte_req[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : FF_FSM.v(232) | Optimizing register bit serv_cmdbyte_req[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : FF_FSM.v(232) | Optimizing register bit serv_cmdbyte_req[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : FF_FSM.v(232) | Optimizing register bit serv_cmdbyte_req[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : FF_FSM.v(232) | Optimizing register bit serv_cmdbyte_req[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : FF_FSM.v(232) | Optimizing register bit serv_cmdbyte_req[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : FF_FSM.v(232) | Pruning register bits 7 to 2 of serv_cmdbyte_req[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : FF_FSM.v(232) | Pruning register bit 0 of serv_cmdbyte_req[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : FF_BLKS.v(9) | Synthesizing module FF_BLKS in library work. Running optimization stage 1 on FF_BLKS ....... @N:CG775 : coreahblite.v(23) | Component SystemBuilder_CoreAHBLite_0_CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @N:CG364 : igloo2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... @N:CG364 : SystemBuilder_CCC_0_FCCC.v(5) | Synthesizing module SystemBuilder_CCC_0_FCCC in library work. Running optimization stage 1 on SystemBuilder_CCC_0_FCCC ....... @W:CG1283 : coreahblite.v(568) | Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(568) | Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(568) | Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(568) | Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_matrix4x16.v(2813) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_masterstage.v(217) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000010 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z6 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z6 ....... @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 Running optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65538_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_65538_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(633) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @W:CG1283 : coreahblite_matrix4x16.v(2879) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_matrix4x16.v(2945) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_masterstage.v(217) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z7 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z7 ....... @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(633) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @W:CG1283 : coreahblite_matrix4x16.v(3011) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z8 Running optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z8 ....... @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 Running optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M0_AHBSLOTENABLE=17'b10000000000000010 M1_AHBSLOTENABLE=17'b10000000000000010 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65538_65538_0_0_0s Running optimization stage 1 on COREAHBLITE_MATRIX4X16_1_1_85_65538_65538_0_0_0s ....... @N:CG364 : coreahblite.v(23) | Synthesizing module SystemBuilder_CoreAHBLite_0_CoreAHBLite in library COREAHBLITE_LIB. FAMILY=6'b011000 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b1 SC_1=1'b0 SC_2=1'b1 SC_3=1'b0 SC_4=1'b1 SC_5=1'b0 SC_6=1'b1 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b1 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b1 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b1 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b1 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 MASTER0_INTERFACE=1'b1 MASTER1_INTERFACE=1'b1 MASTER2_INTERFACE=1'b1 MASTER3_INTERFACE=1'b1 SLAVE0_INTERFACE=1'b1 SLAVE1_INTERFACE=1'b1 SLAVE2_INTERFACE=1'b1 SLAVE3_INTERFACE=1'b1 SLAVE4_INTERFACE=1'b1 SLAVE5_INTERFACE=1'b1 SLAVE6_INTERFACE=1'b1 SLAVE7_INTERFACE=1'b1 SLAVE8_INTERFACE=1'b1 SLAVE9_INTERFACE=1'b1 SLAVE10_INTERFACE=1'b1 SLAVE11_INTERFACE=1'b1 SLAVE12_INTERFACE=1'b1 SLAVE13_INTERFACE=1'b1 SLAVE14_INTERFACE=1'b1 SLAVE15_INTERFACE=1'b1 SLAVE16_INTERFACE=1'b1 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b10000000000000010 M1_AHBSLOTENABLE=17'b10000000000000010 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000001010101 Generated name = SystemBuilder_CoreAHBLite_0_CoreAHBLite_Z9 Running optimization stage 1 on SystemBuilder_CoreAHBLite_0_CoreAHBLite_Z9 ....... @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 INCL_FF_SUPPORT=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z10 Running optimization stage 1 on CoreResetP_Z10 ....... @W:CL169 : coreresetp.v(1728) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1696) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1664) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1632) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1600) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1480) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1415) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1350) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1285) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1204) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1503) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1548) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1204) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1548) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1548) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(868) | Pruning unused register sm2_areset_n_q2. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(868) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... @N:CG364 : SystemBuilder_FABOSC_0_OSC.v(5) | Synthesizing module SystemBuilder_FABOSC_0_OSC in library work. Running optimization stage 1 on SystemBuilder_FABOSC_0_OSC ....... @W:CL318 : SystemBuilder_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SystemBuilder_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SystemBuilder_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SystemBuilder_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : igloo2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... @N:CG364 : SystemBuilder_HPMS_syn.v(5) | Synthesizing module MSS_010 in library work. Running optimization stage 1 on MSS_010 ....... @N:CG364 : SystemBuilder_HPMS.v(9) | Synthesizing module SystemBuilder_HPMS in library work. Running optimization stage 1 on SystemBuilder_HPMS ....... @N:CG364 : SystemBuilder.v(9) | Synthesizing module SystemBuilder in library work. Running optimization stage 1 on SystemBuilder ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on SystemBuilder ....... Running optimization stage 2 on SystemBuilder_HPMS ....... @W:CL247 : SystemBuilder_HPMS.v(53) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused Running optimization stage 2 on MSS_010 ....... Running optimization stage 2 on SYSRESET ....... Running optimization stage 2 on SystemBuilder_FABOSC_0_OSC ....... @N:CL159 : SystemBuilder_FABOSC_0_OSC.v(14) | Input XTL is unused. Running optimization stage 2 on RCOSC_25_50MHZ ....... Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Running optimization stage 2 on CoreResetP_Z10 ....... @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif3_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1480) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1415) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1350) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1285) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1204) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(67) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(70) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(79) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(83) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(87) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(101) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(102) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(103) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(104) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(105) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(106) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(107) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(108) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(109) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(110) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(111) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(112) | Input SDIF3_PRDATA is unused. @N:CL159 : coreresetp.v(118) | Input SOFT_EXT_RESET_OUT is unused. @N:CL159 : coreresetp.v(119) | Input SOFT_RESET_F2M is unused. @N:CL159 : coreresetp.v(120) | Input SOFT_M3_RESET is unused. @N:CL159 : coreresetp.v(121) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused. @N:CL159 : coreresetp.v(122) | Input SOFT_FDDR_CORE_RESET is unused. @N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_PHY_RESET is unused. @N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_CORE_RESET is unused. @N:CL159 : coreresetp.v(125) | Input SOFT_SDIF1_PHY_RESET is unused. @N:CL159 : coreresetp.v(126) | Input SOFT_SDIF1_CORE_RESET is unused. @N:CL159 : coreresetp.v(127) | Input SOFT_SDIF2_PHY_RESET is unused. @N:CL159 : coreresetp.v(128) | Input SOFT_SDIF2_CORE_RESET is unused. @N:CL159 : coreresetp.v(129) | Input SOFT_SDIF3_PHY_RESET is unused. @N:CL159 : coreresetp.v(130) | Input SOFT_SDIF3_CORE_RESET is unused. @N:CL159 : coreresetp.v(134) | Input SOFT_SDIF0_0_CORE_RESET is unused. @N:CL159 : coreresetp.v(135) | Input SOFT_SDIF0_1_CORE_RESET is unused. Running optimization stage 2 on SystemBuilder_CoreAHBLite_0_CoreAHBLite_Z9 ....... @W:CL247 : coreahblite.v(184) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(197) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(210) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(223) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(236) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(249) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(262) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(275) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(288) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(301) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(314) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(327) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(340) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(353) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(366) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(379) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(392) | Input port bit 1 of HRESP_S16[1:0] is unused @N:CL159 : coreahblite.v(145) | Input HPROT_M0 is unused. @N:CL159 : coreahblite.v(156) | Input HPROT_M1 is unused. @N:CL159 : coreahblite.v(167) | Input HPROT_M2 is unused. @N:CL159 : coreahblite.v(178) | Input HPROT_M3 is unused. Running optimization stage 2 on COREAHBLITE_MATRIX4X16_1_1_85_65538_65538_0_0_0s ....... @N:CL159 : coreahblite_matrix4x16.v(63) | Input HWDATA_M2 is unused. @N:CL159 : coreahblite_matrix4x16.v(73) | Input HWDATA_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(77) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(78) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(79) | Input HRESP_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(101) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(102) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(103) | Input HRESP_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(113) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(114) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(115) | Input HRESP_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(125) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(126) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(127) | Input HRESP_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(137) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(138) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(139) | Input HRESP_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(149) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(150) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(151) | Input HRESP_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(173) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(174) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(175) | Input HRESP_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(185) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(186) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(187) | Input HRESP_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(197) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(198) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(199) | Input HRESP_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(209) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(210) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(211) | Input HRESP_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(221) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(222) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(223) | Input HRESP_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(233) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(234) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(235) | Input HRESP_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(245) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(246) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(247) | Input HRESP_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(257) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(258) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(259) | Input HRESP_S15 is unused. Running optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... @N:CL159 : coreahblite_slavestage.v(39) | Input MPREVDATASLAVEREADY is unused. Running optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z8 ....... @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState. Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 ....... @N:CL159 : coreahblite_masterstage.v(43) | Input SDATAREADY is unused. @N:CL159 : coreahblite_masterstage.v(44) | Input SHRESP is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S5 is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z7 ....... Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_1_1_85_65538_0s_0_1_0 ....... @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 2 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL247 : coreahblite_masterstage.v(43) | Input port bit 0 of SDATAREADY[16:0] is unused @W:CL246 : coreahblite_masterstage.v(44) | Input port bits 15 to 2 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL247 : coreahblite_masterstage.v(44) | Input port bit 0 of SHRESP[16:0] is unused Running optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z6 ....... Running optimization stage 2 on SystemBuilder_CCC_0_FCCC ....... Running optimization stage 2 on CCC ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on FF_BLKS ....... Running optimization stage 2 on ff_fsm ....... @N:CL135 : FF_FSM.v(57) | Found sequential shift sync3 with address depth of 3 words and data bit width of 1. @W:CL169 : FF_FSM.v(232) | Pruning unused register serv_cmdbyte_req[1]. Make sure that there are no unused intermediate registers. @N:CL201 : FF_FSM.v(187) | Trying to extract state machine for register pres_state. Extracted state machine for register pres_state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : FF_FSM.v(104) | Trying to extract state machine for register mux_sel_state. Extracted state machine for register mux_sel_state State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on top_CORESYSSERVICES_0_CORESYSSERVICES_Z5 ....... Running optimization stage 2 on CoreSysServices_AHBLMasterIF ....... Running optimization stage 2 on CoreSysServices_FSMCtrl ....... @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : CoreSysServices_FSMCtrl.v(293) | Pruning unused register fmhburst_d1[0]. Make sure that there are no unused intermediate registers. @N:CL201 : CoreSysServices_FSMCtrl.v(326) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 7 reachable states with original encodings of: 0000 0001 0010 0101 1000 1001 1011 Running optimization stage 2 on CoreSysServices_CmdDec_Z4 ....... @W:CL190 : CoreSysServices_CmdDec.v(997) | Optimizing register bit burstlen_memwr_data_r[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : CoreSysServices_CmdDec.v(1096) | Pruning register bits 31 to 16 of cfburst_len_rd_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(997) | Pruning register bit 31 of burstlen_memwr_data_r[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element fcdataout_d1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_wr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CoreSysServices_CmdDec.v(1096) | Pruning register bit 31 of cfburst_len_wr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : CoreSysServices_CmdDec.v(3426) | Trying to extract state machine for register asynchevent_curr_state. Extracted state machine for register asynchevent_curr_state State machine has 2 reachable states with original encodings of: 0000 1001 @N:CL201 : CoreSysServices_CmdDec.v(3004) | Trying to extract state machine for register resp_curr_state. Extracted state machine for register resp_curr_state State machine has 31 reachable states with original encodings of: 000000 000001 000011 000101 000110 000111 001000 001001 001100 001101 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011011 100100 100101 100110 100111 101000 101001 101100 101110 101111 110000 @N:CL201 : CoreSysServices_CmdDec.v(1970) | Trying to extract state machine for register req_curr_state. Extracted state machine for register req_curr_state State machine has 37 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 100001 100010 100101 100110 101000 101001 101010 101011 101100 101101 101110 110000 110001 110010 110011 110100 @N:CL201 : CoreSysServices_CmdDec.v(1640) | Trying to extract state machine for register main_curr_state. @W:CL190 : CoreSysServices_CmdDec.v(1895) | Optimizing register bit cfrd_asyncevent_o to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : CoreSysServices_CmdDec.v(2889) | Pruning unused register resp_srcreg_addr_d1[30]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1895) | Pruning unused register cfrd_asyncevent_o. Make sure that there are no unused intermediate registers. Running optimization stage 2 on FLASH_FREEZE ....... Running optimization stage 2 on CoreSysServices_UserIF_Z3 ....... @N:CL135 : CoreSysServices_UserIF.v(772) | Found sequential shift zer_new_serv_d1 with address depth of 3 words and data bit width of 1. Running optimization stage 2 on cnt34 ....... Running optimization stage 2 on counter_delay ....... Running optimization stage 2 on AHBMASTER_FIC_RAM ....... Running optimization stage 2 on RAM_with_wrapper ....... Running optimization stage 2 on RAM_with_wrapper_SRAM_64x8_0_TPSRAM ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on RAM1K18 ....... Running optimization stage 2 on mux_blk ....... Running optimization stage 2 on mem_apb_wrp_8s_8s ....... @N:CL201 : mem_apb_wrp.v(78) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on CoreAPB3_Z2 ....... Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Running optimization stage 2 on COREAHBTOAPB3_24s_0s ....... @W:CL247 : coreahbtoapb3.v(40) | Input port bit 0 of HTRANS[1:0] is unused Running optimization stage 2 on CAHBtoAPB3l1I_0s ....... Running optimization stage 2 on CAHBtoAPB3OIl_0s_0_1_2 ....... @N:CL201 : coreahbtoapb3_penablescheduler.v(196) | Trying to extract state machine for register CAHBtoAPB3lIl. Extracted state machine for register CAHBtoAPB3lIl State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on CAHBtoAPB3O_0s_0_1_0_1_2_3_4 ....... @N:CL201 : coreahbtoapb3_ahbtoapbsm.v(690) | Trying to extract state machine for register CAHBtoAPB3IOI. Extracted state machine for register CAHBtoAPB3IOI State machine has 5 reachable states with original encodings of: 000 001 010 011 100 Running optimization stage 2 on AHBMASTER_FIC_Z1 ....... @N:CL201 : AHBMASTER_FIC.v(74) | Trying to extract state machine for register ahb_fsm_current_state. Extracted state machine for register ahb_fsm_current_state State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 131MB peak: 152MB) Process took 0h:00m:13s realtime, 0h:00m:12s cputime Process completed successfully. # Wed Mar 31 12:54:32 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode File C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 106MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Mar 31 12:54:33 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 23MB peak: 23MB) Process took 0h:00m:13s realtime, 0h:00m:13s cputime Process completed successfully. # Wed Mar 31 12:54:33 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode File C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\synwork\top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 116MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Mar 31 12:54:35 2021 ###########################################################] Premap Report # Wed Mar 31 12:54:35 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) Reading constraint file: C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(8) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 154MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 155MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 155MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 155MB peak: 157MB) @W:BN132 : coresysservices_userif.v(653) | Removing sequential instance CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_hold[4] because it is equivalent to instance CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_hold[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_userif.v(653) | Removing sequential instance CORESYSSERVICES_0.U_UserIF.uclatchoptions_hold[1] because it is equivalent to instance CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_hold[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3837) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_15 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3786) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_14 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3735) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_13 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3684) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_12 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3633) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_11 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3531) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_9 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3480) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_8 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3429) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_7 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3378) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_6 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3327) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_5 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3276) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_4 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3225) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_3 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3174) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_2 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3582) | Removing user instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_10 because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1204) | Removing sequential instance SystemBuilder_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance SystemBuilder_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : coresysservices_cmddec.v(372) | Tristate driver cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) on net cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) has its enable tied to GND. @N:MO111 : systembuilder_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : systembuilder_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : systembuilder_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : systembuilder_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(755) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(774) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(793) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(812) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(851) | Sequential instance SystemBuilder_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(755) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(774) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(793) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(812) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(851) | Sequential instance SystemBuilder_0.CORERESETP_0.sm1_areset_n_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(755) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(774) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(793) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(812) | Sequential instance SystemBuilder_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1503) | Sequential instance SystemBuilder_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : coresysservices_userif.v(653) | Removing sequential instance ucmdbyte_req_hold[2] (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coresysservices.v(700) | Removing instance U_AHBLMasterIF (in view: CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) of type view:CORESYSSERVICES_LIB.CoreSysServices_AHBLMasterIF(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(647) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(217) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z7_0(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(647) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(217) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z7_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2945) | Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65538_65538_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(3011) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65538_65538_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because it does not drive other instances. @N:BN362 : coresysservices_fsmctrl.v(305) | Removing sequential instance clr_req (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1285) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1285) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1350) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1350) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1415) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1415) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1480) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1480) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : mem_apb_wrp.v(78) | Removing sequential instance INT_OUT (in view: work.mem_apb_wrp_8s_8s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(3072) | Removing instance slavestage_0 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65538_65538_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_2(verilog) because it does not drive other instances. @N:BN362 : coresysservices_fsmctrl.v(838) | Removing sequential instance fmhsel_o (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(619) | Removing sequential instance ustatus_valid_o (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(605) | Removing sequential instance ustatus_resp_o[7:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(416) | Removing sequential instance ucmd_error (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1285) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1350) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1415) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1480) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(538) | Removing sequential instance ustatus_resp_lat[7:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(84) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(439) | Removing sequential instance udata_wrdy_d2 (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(578) | Removing sequential instance ustatus_valid_lat (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(885) | Removing sequential instance sdif0_areset_n_q2 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(902) | Removing sequential instance sdif1_areset_n_q2 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(919) | Removing sequential instance sdif2_areset_n_q2 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(936) | Removing sequential instance sdif3_areset_n_q2 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_slavestage.v(92) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z8_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(885) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(902) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(919) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(936) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z10(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2461) | Removing sequential instance cudata_wrdy_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2733) | Removing sequential instance cudata_rvalid_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2747) | Removing sequential instance custatus_valid_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z8_0(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=21 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 194MB) @W:MT688 : synthesis.fdc(8) | No path from master pin (-source) to source of clock SystemBuilder_0/CCC_0/GL0 due to black box SystemBuilder_0.CCC_0.CCC_INST Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 26 1 . SystemBuilder_0/CCC_0/GL0 50.0 MHz 20.000 generated (from SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 1076 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - top|rclk_user 100.0 MHz 10.000 inferred Inferred_clkgroup_0 3 0 - top|wclk_user 100.0 MHz 10.000 inferred Inferred_clkgroup_1 1 ============================================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 26 SystemBuilder_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) SystemBuilder_0.CORERESETP_0.release_sdif0_core.C - SystemBuilder_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) SystemBuilder_0/CCC_0/GL0 1076 SystemBuilder_0.CCC_0.CCC_INST.GL0(CCC) SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST.CLK_BASE - SystemBuilder_0.CCC_0.GL0_INST.I(BUFG) System 0 - - - - top|rclk_user 3 rclk_user(port) AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.SRAM_64x8_0.RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0.B_DOUT_CLK - AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.mux_blk_0.rclk.B[0](mux) top|wclk_user 1 wclk_user(port) AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.SRAM_64x8_0.RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0.B_CLK - AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.mux_blk_0.wclk.B[0](mux) ==================================================================================================================================================================================================================================================================================================================================== @W:MT530 : ram_with_wrapper_sram_64x8_0_tpsram.v(33) | Found inferred clock top|rclk_user which controls 3 sequential elements including AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.SRAM_64x8_0.RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : ram_with_wrapper_sram_64x8_0_tpsram.v(33) | Found inferred clock top|wclk_user which controls 1 sequential elements including AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.SRAM_64x8_0.RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 195MB) Encoding state machine ahb_fsm_current_state[15:0] (in view: work.AHBMASTER_FIC_Z1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine CAHBtoAPB3IOI[4:0] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3O_0s_0_1_0_1_2_3_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine CAHBtoAPB3lIl[2:0] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3OIl_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine fsm[3:0] (in view: work.mem_apb_wrp_8s_8s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : mem_apb_wrp.v(78) | There are no possible illegal states for state machine fsm[3:0] (in view: work.mem_apb_wrp_8s_8s(verilog)); safe FSM implementation is not required. Encoding state machine resp_curr_state[30:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) original code -> new code 000000 -> 0000000000000000000000000000001 000001 -> 0000000000000000000000000000010 000011 -> 0000000000000000000000000000100 000101 -> 0000000000000000000000000001000 000110 -> 0000000000000000000000000010000 000111 -> 0000000000000000000000000100000 001000 -> 0000000000000000000000001000000 001001 -> 0000000000000000000000010000000 001100 -> 0000000000000000000000100000000 001101 -> 0000000000000000000001000000000 010000 -> 0000000000000000000010000000000 010001 -> 0000000000000000000100000000000 010010 -> 0000000000000000001000000000000 010011 -> 0000000000000000010000000000000 010100 -> 0000000000000000100000000000000 010101 -> 0000000000000001000000000000000 010110 -> 0000000000000010000000000000000 010111 -> 0000000000000100000000000000000 011000 -> 0000000000001000000000000000000 011001 -> 0000000000010000000000000000000 011011 -> 0000000000100000000000000000000 100100 -> 0000000001000000000000000000000 100101 -> 0000000010000000000000000000000 100110 -> 0000000100000000000000000000000 100111 -> 0000001000000000000000000000000 101000 -> 0000010000000000000000000000000 101001 -> 0000100000000000000000000000000 101100 -> 0001000000000000000000000000000 101110 -> 0010000000000000000000000000000 101111 -> 0100000000000000000000000000000 110000 -> 1000000000000000000000000000000 Encoding state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) original code -> new code 0000 -> 0 1001 -> 1 @N:MO225 : coresysservices_cmddec.v(3426) | There are no possible illegal states for state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)); safe FSM implementation is not required. Encoding state machine req_curr_state[36:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) original code -> new code 000000 -> 0000000000000000000000000000000000001 000001 -> 0000000000000000000000000000000000010 000010 -> 0000000000000000000000000000000000100 000011 -> 0000000000000000000000000000000001000 000100 -> 0000000000000000000000000000000010000 000101 -> 0000000000000000000000000000000100000 000111 -> 0000000000000000000000000000001000000 001000 -> 0000000000000000000000000000010000000 001001 -> 0000000000000000000000000000100000000 001010 -> 0000000000000000000000000001000000000 001011 -> 0000000000000000000000000010000000000 001100 -> 0000000000000000000000000100000000000 001101 -> 0000000000000000000000001000000000000 001110 -> 0000000000000000000000010000000000000 001111 -> 0000000000000000000000100000000000000 010000 -> 0000000000000000000001000000000000000 010001 -> 0000000000000000000010000000000000000 010010 -> 0000000000000000000100000000000000000 010011 -> 0000000000000000001000000000000000000 010100 -> 0000000000000000010000000000000000000 010101 -> 0000000000000000100000000000000000000 100001 -> 0000000000000001000000000000000000000 100010 -> 0000000000000010000000000000000000000 100101 -> 0000000000000100000000000000000000000 100110 -> 0000000000001000000000000000000000000 101000 -> 0000000000010000000000000000000000000 101001 -> 0000000000100000000000000000000000000 101010 -> 0000000001000000000000000000000000000 101011 -> 0000000010000000000000000000000000000 101100 -> 0000000100000000000000000000000000000 101101 -> 0000001000000000000000000000000000000 101110 -> 0000010000000000000000000000000000000 110000 -> 0000100000000000000000000000000000000 110001 -> 0001000000000000000000000000000000000 110010 -> 0010000000000000000000000000000000000 110011 -> 0100000000000000000000000000000000000 110100 -> 1000000000000000000000000000000000000 Encoding state machine curr_state[6:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0101 -> 0001000 1000 -> 0010000 1001 -> 0100000 1011 -> 1000000 @N:BN362 : coresysservices_fsmctrl.v(612) | Removing sequential instance burstwrflag_last_n (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. Encoding state machine pres_state[2:0] (in view: work.ff_fsm(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine mux_sel_state[2:0] (in view: work.ff_fsm(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z8_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z8_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z10(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 204MB peak: 204MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 207MB peak: 207MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 103MB peak: 207MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Wed Mar 31 12:54:39 2021 ###########################################################] Map & Optimize Report # Wed Mar 31 12:54:39 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB) @N:MO111 : coresysservices_cmddec.v(372) | Tristate driver cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) on net cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) has its enable tied to GND. @N:MO111 : systembuilder_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : systembuilder_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : systembuilder_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : systembuilder_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.SystemBuilder_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(1078) | Removing sequential instance SystemBuilder_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance SystemBuilder_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1061) | Removing sequential instance SystemBuilder_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance SystemBuilder_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1061) | Removing sequential instance SystemBuilder_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance SystemBuilder_0.CORERESETP_0.fpll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1044) | Removing sequential instance SystemBuilder_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance SystemBuilder_0.CORERESETP_0.fpll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found @W:BN132 : coresysservices_cmddec.v(3030) | Removing user instance CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data[7] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(2889) | Removing sequential instance CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data_d1[7] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.resp_srcreg_data_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) @N:MO231 : cnt34.v(13) | Found counter in view:work.top(verilog) instance cnt34_0.CNT[33:0] Encoding state machine ahb_fsm_current_state[15:0] (in view: work.AHBMASTER_FIC_Z1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : ahbmaster_fic.v(74) | Register bit HSIZE[2] (in view view:work.AHBMASTER_FIC_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : ahbmaster_fic.v(74) | Register bit HSIZE[0] (in view view:work.AHBMASTER_FIC_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : ahbmaster_fic.v(74) | Removing sequential instance NVM_ADDR[0] (in view: work.AHBMASTER_FIC_Z1(verilog)) because it does not drive other instances. @N:BN362 : ahbmaster_fic.v(74) | Removing sequential instance NVM_ADDR[1] (in view: work.AHBMASTER_FIC_Z1(verilog)) because it does not drive other instances. @N:BN362 : ahbmaster_fic.v(74) | Removing sequential instance RAM_ADDR[0] (in view: work.AHBMASTER_FIC_Z1(verilog)) because it does not drive other instances. @N:BN362 : ahbmaster_fic.v(74) | Removing sequential instance RAM_ADDR[1] (in view: work.AHBMASTER_FIC_Z1(verilog)) because it does not drive other instances. @W:BN132 : ahbmaster_fic.v(74) | Removing instance AHBMASTER_FIC_RAM_0.AHBMASTER_FIC_0.HADDR[1] because it is equivalent to instance AHBMASTER_FIC_RAM_0.AHBMASTER_FIC_0.HADDR[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[12] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[13] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[14] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[15] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[12] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[13] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[14] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[15] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[24] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[25] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[26] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[27] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[12] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[13] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[14] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[15] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[31] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[30] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[29] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[28] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[27] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[26] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[25] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[24] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[23] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[22] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[21] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[20] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[19] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[18] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[17] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[16] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[15] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[14] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[13] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[12] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[11] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[10] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[9] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[8] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_24s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine CAHBtoAPB3IOI[4:0] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3O_0s_0_1_0_1_2_3_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @W:BN132 : coreahbtoapb3_ahbtoapbsm.v(690) | Removing sequential instance AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3lll.PWRITE because it is equivalent to instance AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine CAHBtoAPB3lIl[2:0] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3OIl_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:BN132 : coreahbtoapb3_penablescheduler.v(196) | Removing instance AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3O0l.PENABLE because it is equivalent to instance AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3O0l.CAHBtoAPB3lIl[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine fsm[3:0] (in view: work.mem_apb_wrp_8s_8s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : mem_apb_wrp.v(78) | There are no possible illegal states for state machine fsm[3:0] (in view: work.mem_apb_wrp_8s_8s(verilog)); safe FSM implementation is not required. @N:MO231 : counter_delay.v(30) | Found counter in view:work.counter_delay(verilog) instance q_int[9:0] @W:MO160 : coresysservices_userif.v(696) | Register bit U_UserIF.ucmdbyte_req_d1[7] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit U_UserIF.ucmdbyte_req_d1[6] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit U_UserIF.ucmdbyte_req_d1[5] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit U_UserIF.ucmdbyte_req_d1[4] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit U_UserIF.ucmdbyte_req_d1[3] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit U_UserIF.ucmdbyte_req_d1[2] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit U_UserIF.ucmdbyte_req_d1[0] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit U_UserIF.uclatchcmd_o[7] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit U_UserIF.uclatchcmd_o[6] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit U_UserIF.uclatchcmd_o[5] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit U_UserIF.uclatchcmd_o[4] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit U_UserIF.uclatchcmd_o[3] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit U_UserIF.uclatchcmd_o[2] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit U_UserIF.uclatchcmd_o[0] (in view view:CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine resp_curr_state[30:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) original code -> new code 000000 -> 0000000000000000000000000000001 000001 -> 0000000000000000000000000000010 000011 -> 0000000000000000000000000000100 000101 -> 0000000000000000000000000001000 000110 -> 0000000000000000000000000010000 000111 -> 0000000000000000000000000100000 001000 -> 0000000000000000000000001000000 001001 -> 0000000000000000000000010000000 001100 -> 0000000000000000000000100000000 001101 -> 0000000000000000000001000000000 010000 -> 0000000000000000000010000000000 010001 -> 0000000000000000000100000000000 010010 -> 0000000000000000001000000000000 010011 -> 0000000000000000010000000000000 010100 -> 0000000000000000100000000000000 010101 -> 0000000000000001000000000000000 010110 -> 0000000000000010000000000000000 010111 -> 0000000000000100000000000000000 011000 -> 0000000000001000000000000000000 011001 -> 0000000000010000000000000000000 011011 -> 0000000000100000000000000000000 100100 -> 0000000001000000000000000000000 100101 -> 0000000010000000000000000000000 100110 -> 0000000100000000000000000000000 100111 -> 0000001000000000000000000000000 101000 -> 0000010000000000000000000000000 101001 -> 0000100000000000000000000000000 101100 -> 0001000000000000000000000000000 101110 -> 0010000000000000000000000000000 101111 -> 0100000000000000000000000000000 110000 -> 1000000000000000000000000000000 Encoding state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) original code -> new code 0000 -> 0 1001 -> 1 @N:MO225 : coresysservices_cmddec.v(3426) | There are no possible illegal states for state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)); safe FSM implementation is not required. Encoding state machine req_curr_state[36:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) original code -> new code 000000 -> 0000000000000000000000000000000000001 000001 -> 0000000000000000000000000000000000010 000010 -> 0000000000000000000000000000000000100 000011 -> 0000000000000000000000000000000001000 000100 -> 0000000000000000000000000000000010000 000101 -> 0000000000000000000000000000000100000 000111 -> 0000000000000000000000000000001000000 001000 -> 0000000000000000000000000000010000000 001001 -> 0000000000000000000000000000100000000 001010 -> 0000000000000000000000000001000000000 001011 -> 0000000000000000000000000010000000000 001100 -> 0000000000000000000000000100000000000 001101 -> 0000000000000000000000001000000000000 001110 -> 0000000000000000000000010000000000000 001111 -> 0000000000000000000000100000000000000 010000 -> 0000000000000000000001000000000000000 010001 -> 0000000000000000000010000000000000000 010010 -> 0000000000000000000100000000000000000 010011 -> 0000000000000000001000000000000000000 010100 -> 0000000000000000010000000000000000000 010101 -> 0000000000000000100000000000000000000 100001 -> 0000000000000001000000000000000000000 100010 -> 0000000000000010000000000000000000000 100101 -> 0000000000000100000000000000000000000 100110 -> 0000000000001000000000000000000000000 101000 -> 0000000000010000000000000000000000000 101001 -> 0000000000100000000000000000000000000 101010 -> 0000000001000000000000000000000000000 101011 -> 0000000010000000000000000000000000000 101100 -> 0000000100000000000000000000000000000 101101 -> 0000001000000000000000000000000000000 101110 -> 0000010000000000000000000000000000000 110000 -> 0000100000000000000000000000000000000 110001 -> 0001000000000000000000000000000000000 110010 -> 0010000000000000000000000000000000000 110011 -> 0100000000000000000000000000000000000 110100 -> 1000000000000000000000000000000000000 @N:MO231 : coresysservices_cmddec.v(2481) | Found counter in view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog) instance desc_datasel_cntr[31:0] @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[8] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[9] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[10] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[11] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[12] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[13] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[14] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[15] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[16] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[17] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[18] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[19] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[20] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[21] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[22] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[23] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[24] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[25] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[26] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[27] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[28] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[29] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[30] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(2711) | Removing sequential instance cudata_r_o[31] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[31] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[30] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[17] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[16] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[14] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[13] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[12] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[7] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[6] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[5] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[4] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[3] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[2] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[0] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[30] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[29] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[17] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[16] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[14] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[13] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[12] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[7] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[6] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[5] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[31] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(2668) | Register bit cfdatain_d1[30] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z4(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Only the first 100 messages of id 'MO160' are reported. To see all messages use 'report_messages -log C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\synlog\top_fpga_mapper.srr -id MO160' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {MO160} -count unlimited' in the Tcl shell. @W:BN132 : coresysservices_cmddec.v(2889) | Removing instance CORESYSSERVICES_0.U_CmdDec.resp_srcreg_addr_d1[14] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.resp_srcreg_addr_d1[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine curr_state[6:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0101 -> 0001000 1000 -> 0010000 1001 -> 0100000 1011 -> 1000000 @N:BN362 : coresysservices_fsmctrl.v(612) | Removing sequential instance burstwrflag_last_n (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. @N:MO231 : coresysservices_fsmctrl.v(760) | Found counter in view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog) instance word_count[31:0] Encoding state machine pres_state[2:0] (in view: work.ff_fsm(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine mux_sel_state[2:0] (in view: work.ff_fsm(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z8_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z8_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z10(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 211MB) @W:BN132 : coresysservices_fsmctrl.v(780) | Removing instance CORESYSSERVICES_0.U_fsm_ctrl.fmhaddr_o[1] because it is equivalent to instance CORESYSSERVICES_0.U_fsm_ctrl.fmhaddr_o[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coresysservices_fsmctrl.v(780) | Removing sequential instance U_fsm_ctrl.fmhaddr_o[0] (in view: CORESYSSERVICES_LIB.top_CORESYSSERVICES_0_CORESYSSERVICES_Z5(verilog)) because it does not drive other instances. @W:BN132 : coreahblite_masterstage.v(166) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS[1] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_masterstage.v(166) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[2] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavestage.v(84) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] (in view: work.SystemBuilder(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(84) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] (in view: work.SystemBuilder(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(84) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[3] (in view: work.SystemBuilder(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(84) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[2] (in view: work.SystemBuilder(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(166) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[0] (in view: work.SystemBuilder(verilog)) because it does not drive other instances. @N:BN362 : ahbmaster_fic.v(74) | Removing sequential instance AHBMASTER_FIC_RAM_0.AHBMASTER_FIC_0.HADDR[0] (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 211MB) @W:BN132 : coreahblite_masterstage.v(166) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[1] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_masterstage.v(166) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[1] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahbtoapb3_apbaddrdata.v(229) | Removing instance AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3IOl[1] because it is equivalent to instance AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3IOl[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahbtoapb3_apbaddrdata.v(146) | Removing instance AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3OOl[1] because it is equivalent to instance AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3OOl[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[3] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[7] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[3] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[15] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[15] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[14] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[13] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[12] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[11] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[10] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[9] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[8] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[8] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[7] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[6] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[5] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(997) | Removing instance CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[5] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(997) | Removing instance CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[2] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[23] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[22] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[21] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[20] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[19] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[18] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[17] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[16] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[15] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[14] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[13] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[12] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[11] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[10] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[9] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[30] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[29] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[28] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[27] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[26] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[25] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[24] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(2668) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[6] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(2668) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfdatain_d1[5] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[14] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[6] because it is equivalent to instance SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. Only the first 100 messages of id 'BN362' are reported. To see all messages use 'report_messages -log C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\synlog\top_fpga_mapper.srr -id BN362' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN362} -count unlimited' in the Tcl shell. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 197MB peak: 211MB) @W:BN132 : coresysservices_cmddec.v(997) | Removing instance CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[3] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1970) | Removing instance CORESYSSERVICES_0.U_CmdDec.req_curr_state[27] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.req_curr_state[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coresysservices_cmddec.v(1096) | Removing instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[3] because it is equivalent to instance CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 197MB peak: 211MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 198MB peak: 211MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:06s; Memory used current: 198MB peak: 211MB) @N:MO106 : coresysservices_cmddec.v(1466) | Found ROM CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[3:0] (in view: work.top(verilog)) with 1 words by 4 bits. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[33] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[32] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[31] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[30] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[29] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[28] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[27] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 198MB peak: 211MB) Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 216MB peak: 216MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:07s 5.38ns 1107 / 658 @N:FP130 : | Promoting Net INIT_DONE_arst on CLKINT I_250 @N:FP130 : | Promoting Net SystemBuilder_0.MSS_HPMS_READY_arst on CLKINT I_251 @N:FP130 : | Promoting Net SystemBuilder_0.CORERESETP_0.sm0_areset_n_q2 on CLKINT I_252 @N:FP130 : | Promoting Net SystemBuilder_0.CORERESETP_0.sm0_areset_n_arst on CLKINT I_253 @N:FP130 : | Promoting Net AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.mux_blk_0_rclk on CLKINT I_254 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 216MB peak: 217MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 217MB peak: 217MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 26 clock pin(s) of sequential element(s) 3 gated/generated clock tree(s) driving 639 clock pin(s) of sequential element(s) 0 instances converted, 639 sequential instances remain driven by gated/generated clocks ============================================================= Non-Gated/Non-Generated Clocks ============================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0004 SystemBuilder_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 26 SystemBuilder_0.CORERESETP_0.ddr_settled ========================================================================================================================================================== ======================================================================================================================== Gated/Generated Clocks ========================================================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 SystemBuilder_0.CCC_0.CCC_INST CCC 635 SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_010 ClockId0002 AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.mux_blk_0.rclk CFG3 3 AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.SRAM_64x8_0.RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0 No gated clock conversion method for cell cell:ACG4.RAM1K18 ClockId0003 AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.mux_blk_0.wclk CFG3 1 AHBMASTER_FIC_RAM_0.RAM_with_wrapper_0.SRAM_64x8_0.RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0 No gated clock conversion method for cell cell:ACG4.RAM1K18 ========================================================================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 178MB peak: 217MB) Writing Analyst data base C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 211MB peak: 217MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 212MB peak: 217MB) Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 208MB peak: 217MB) @W:MT246 : systembuilder_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : ff_blks.v(84) | Blackbox FLASH_FREEZE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock SystemBuilder_0/CCC_0/GL0 with period 20.00ns @W:MT420 : | Found inferred clock top|rclk_user with period 10.00ns. Please declare a user-defined clock on port rclk_user. @W:MT420 : | Found inferred clock top|wclk_user with period 10.00ns. Please declare a user-defined clock on port wclk_user. ##### START OF TIMING REPORT #####[ # Timing report written on Wed Mar 31 12:54:49 2021 # Top view: top Requested Frequency: 50.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 8.990 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SystemBuilder_0/CCC_0/GL0 50.0 MHz 90.8 MHz 20.000 11.010 8.990 generated (from SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 487.3 MHz 20.000 2.052 17.948 declared default_clkgroup top|rclk_user 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 top|wclk_user 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 System 100.0 MHz NA 10.000 NA 18.987 system system_clkgroup ================================================================================================================================================================================================================= Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System SystemBuilder_0/CCC_0/GL0 | 20.000 18.987 | No paths - | No paths - | No paths - SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 17.948 | No paths - | No paths - | No paths - SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SystemBuilder_0/CCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - SystemBuilder_0/CCC_0/GL0 SystemBuilder_0/CCC_0/GL0 | 20.000 8.990 | No paths - | No paths - | No paths - SystemBuilder_0/CCC_0/GL0 top|rclk_user | Diff grp - | No paths - | No paths - | No paths - SystemBuilder_0/CCC_0/GL0 top|wclk_user | Diff grp - | No paths - | No paths - | No paths - top|rclk_user SystemBuilder_0/CCC_0/GL0 | Diff grp - | No paths - | No paths - | No paths - =========================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SystemBuilder_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST SystemBuilder_0/CCC_0/GL0 MSS_010 F_FM0_READYOUT CoreAHBLite_0_AHBmslave16_HREADY 3.086 8.990 SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST SystemBuilder_0/CCC_0/GL0 MSS_010 F_FM0_RESP CoreAHBLite_0_AHBmslave16_HRESP 3.189 9.923 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel SystemBuilder_0/CCC_0/GL0 SLE Q masterRegAddrSel 0.094 10.081 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[1] SystemBuilder_0/CCC_0/GL0 SLE Q MDATASEL[0] 0.076 10.324 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[8] SystemBuilder_0/CCC_0/GL0 SLE Q SDATASELInt[8] 0.076 10.332 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[9] SystemBuilder_0/CCC_0/GL0 SLE Q SDATASELInt[9] 0.076 10.419 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3] SystemBuilder_0/CCC_0/GL0 SLE Q SDATASELInt[3] 0.094 10.469 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[12] SystemBuilder_0/CCC_0/GL0 SLE Q SDATASELInt[12] 0.076 10.491 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[10] SystemBuilder_0/CCC_0/GL0 SLE Q SDATASELInt[10] 0.076 10.527 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[14] SystemBuilder_0/CCC_0/GL0 SLE Q SDATASELInt[14] 0.076 10.528 ================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST SystemBuilder_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[0] CoreAHBLite_0_AHBmslave16_HWDATA[0] 19.888 8.990 SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST SystemBuilder_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[2] CoreAHBLite_0_AHBmslave16_HWDATA[2] 19.949 9.051 SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST SystemBuilder_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[7] CoreAHBLite_0_AHBmslave16_HWDATA[7] 19.893 9.141 SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST SystemBuilder_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[1] CoreAHBLite_0_AHBmslave16_HWDATA[1] 19.926 9.174 SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST SystemBuilder_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[4] CoreAHBLite_0_AHBmslave16_HWDATA[4] 19.953 9.201 SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST SystemBuilder_0/CCC_0/GL0 MSS_010 F_FM0_WDATA[29] N_786 19.902 9.476 AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3lOl[0] SystemBuilder_0/CCC_0/GL0 SLE D SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWDATA[0] 19.778 9.635 AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3lOl[2] SystemBuilder_0/CCC_0/GL0 SLE D SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWDATA[2] 19.778 9.635 AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3lOl[1] SystemBuilder_0/CCC_0/GL0 SLE D SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWDATA[1] 19.778 9.782 AHBMASTER_FIC_RAM_0.COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3lOl[4] SystemBuilder_0/CCC_0/GL0 SLE D SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWDATA[4] 19.778 9.782 ======================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.112 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.888 - Propagation time: 10.898 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 8.990 Number of logic level(s): 8 Starting point: SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST / F_FM0_WDATA[0] The start point is clocked by SystemBuilder_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK_BASE The end point is clocked by SystemBuilder_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST MSS_010 F_FM0_READYOUT Out 3.086 3.086 f - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.971 - 13 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre_20_u_i_o2_2_o2_0 CFG4 B In - 4.057 f - SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre_20_u_i_o2_2_o2_0 CFG4 Y Out 0.129 4.186 r - HREADY_M_pre_20_u_i_o2_2_o2_0 Net - - 0.432 - 2 SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre_20_u_i_o2_2_o2_0_RNI9ETM CFG3 B In - 4.619 r - SystemBuilder_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre_20_u_i_o2_2_o2_0_RNI9ETM CFG3 Y Out 0.125 4.743 f - N_923_i Net - - 1.017 - 23 CORESYSSERVICES_0.U_fsm_ctrl.pop_0_o2 CFG3 A In - 5.761 f - CORESYSSERVICES_0.U_fsm_ctrl.pop_0_o2 CFG3 Y Out 0.076 5.836 f - N_54 Net - - 0.708 - 4 CORESYSSERVICES_0.U_CmdDec.cfdatain_o26_0_a2 CFG3 C In - 6.545 f - CORESYSSERVICES_0.U_CmdDec.cfdatain_o26_0_a2 CFG3 Y Out 0.182 6.727 f - cfdatain_o26 Net - - 0.216 - 1 CORESYSSERVICES_0.U_CmdDec.un1_cfdatain_o26 CFG4 D In - 6.943 f - CORESYSSERVICES_0.U_CmdDec.un1_cfdatain_o26 CFG4 Y Out 0.250 7.193 f - N_3688 Net - - 0.779 - 6 CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_9_0 CFG2 A In - 7.972 f - CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_9_0 CFG2 Y Out 0.076 8.048 f - un2_cudata_wrdy_int_9_0 Net - - 0.779 - 6 CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv[0] CFG4 D In - 8.826 f - CORESYSSERVICES_0.U_CmdDec.cfdatain_o_0_iv[0] CFG4 Y Out 0.276 9.102 r - CORESYSSERVICES_0_AHBL_MASTER_HWDATA[0] Net - - 0.648 - 3 SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA_0_0_0[0] CFG4 C In - 9.750 r - SystemBuilder_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA_0_0_0[0] CFG4 Y Out 0.177 9.927 r - CoreAHBLite_0_AHBmslave16_HWDATA[0] Net - - 0.971 - 1 SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST MSS_010 F_FM0_WDATA[0] In - 10.898 r - ========================================================================================================================================================================= Total path delay (propagation time + setup) of 11.010 is 4.488(40.8%) logic and 6.522(59.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------- CLK_Sync_CNTR_Dly_0.q_int[4] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[4] 0.094 17.948 CLK_Sync_CNTR_Dly_0.q_int[0] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[0] 0.094 18.015 CLK_Sync_CNTR_Dly_0.q_int[5] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[5] 0.094 18.016 CLK_Sync_CNTR_Dly_0.q_int[6] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[6] 0.094 18.055 CLK_Sync_CNTR_Dly_0.q_int[1] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[1] 0.094 18.083 CLK_Sync_CNTR_Dly_0.q_int[7] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[7] 0.094 18.122 CLK_Sync_CNTR_Dly_0.q_int[2] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[2] 0.094 18.123 CLK_Sync_CNTR_Dly_0.q_int[3] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[3] 0.094 18.190 CLK_Sync_CNTR_Dly_0.q_int[8] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[8] 0.076 18.209 CLK_Sync_CNTR_Dly_0.q_int[9] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q q_int[9] 0.094 18.525 ====================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------- CLK_Sync_CNTR_Dly_0.q_int[9] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[9] 19.778 17.948 CLK_Sync_CNTR_Dly_0.q_int[8] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[8] 19.778 17.960 CLK_Sync_CNTR_Dly_0.q_int[7] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[7] 19.778 17.973 CLK_Sync_CNTR_Dly_0.q_int[6] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[6] 19.778 17.986 CLK_Sync_CNTR_Dly_0.q_int[5] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[5] 19.778 17.998 CLK_Sync_CNTR_Dly_0.q_int[4] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[4] 19.778 18.011 CLK_Sync_CNTR_Dly_0.q_int[3] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[3] 19.778 18.024 CLK_Sync_CNTR_Dly_0.q_int[2] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[2] 19.778 18.037 CLK_Sync_CNTR_Dly_0.q_int[1] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[1] 19.778 18.049 CLK_Sync_CNTR_Dly_0.q_int[0] SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D q_int_s[0] 19.778 18.062 ========================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.778 - Propagation time: 1.830 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.948 Number of logic level(s): 12 Starting point: CLK_Sync_CNTR_Dly_0.q_int[4] / Q Ending point: CLK_Sync_CNTR_Dly_0.q_int[9] / D The start point is clocked by SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ CLK_Sync_CNTR_Dly_0.q_int[4] SLE Q Out 0.094 0.094 f - q_int[4] Net - - 0.432 - 2 CLK_Sync_CNTR_Dly_0.count_done_int6_6 CFG4 D In - 0.526 f - CLK_Sync_CNTR_Dly_0.count_done_int6_6 CFG4 Y Out 0.250 0.776 f - count_done_int6_6 Net - - 0.432 - 2 CLK_Sync_CNTR_Dly_0.count_done_int6_5_RNI0KKJ ARI1 C In - 1.209 f - CLK_Sync_CNTR_Dly_0.count_done_int6_5_RNI0KKJ ARI1 FCO Out 0.228 1.437 r - q_int_cry_cy Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNIKOLR[0] ARI1 FCI In - 1.437 r - CLK_Sync_CNTR_Dly_0.q_int_RNIKOLR[0] ARI1 FCO Out 0.013 1.449 r - q_int_cry[0] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNI9UM31[1] ARI1 FCI In - 1.449 r - CLK_Sync_CNTR_Dly_0.q_int_RNI9UM31[1] ARI1 FCO Out 0.013 1.462 r - q_int_cry[1] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNIV4OB1[2] ARI1 FCI In - 1.462 r - CLK_Sync_CNTR_Dly_0.q_int_RNIV4OB1[2] ARI1 FCO Out 0.013 1.475 r - q_int_cry[2] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNIMCPJ1[3] ARI1 FCI In - 1.475 r - CLK_Sync_CNTR_Dly_0.q_int_RNIMCPJ1[3] ARI1 FCO Out 0.013 1.487 r - q_int_cry[3] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNIELQR1[4] ARI1 FCI In - 1.487 r - CLK_Sync_CNTR_Dly_0.q_int_RNIELQR1[4] ARI1 FCO Out 0.013 1.500 r - q_int_cry[4] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNI7VR32[5] ARI1 FCI In - 1.500 r - CLK_Sync_CNTR_Dly_0.q_int_RNI7VR32[5] ARI1 FCO Out 0.013 1.513 r - q_int_cry[5] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNI1ATB2[6] ARI1 FCI In - 1.513 r - CLK_Sync_CNTR_Dly_0.q_int_RNI1ATB2[6] ARI1 FCO Out 0.013 1.525 r - q_int_cry[6] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNISLUJ2[7] ARI1 FCI In - 1.525 r - CLK_Sync_CNTR_Dly_0.q_int_RNISLUJ2[7] ARI1 FCO Out 0.013 1.538 r - q_int_cry[7] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNIO20S2[8] ARI1 FCI In - 1.538 r - CLK_Sync_CNTR_Dly_0.q_int_RNIO20S2[8] ARI1 FCO Out 0.013 1.551 r - q_int_cry[8] Net - - 0.000 - 1 CLK_Sync_CNTR_Dly_0.q_int_RNO[9] ARI1 FCI In - 1.551 r - CLK_Sync_CNTR_Dly_0.q_int_RNO[9] ARI1 S Out 0.063 1.614 r - q_int_s[9] Net - - 0.216 - 1 CLK_Sync_CNTR_Dly_0.q_int[9] SLE D In - 1.830 r - ============================================================================================================ Total path delay (propagation time + setup) of 2.052 is 0.972(47.4%) logic and 1.080(52.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- FF_BLKS_0.FLASH_FREEZE_0 System FLASH_FREEZE FF_TO_START FLASH_FREEZE_0_FF_TO_START 0.000 18.987 ============================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ FF_BLKS_0.ff_fsm_0.mux_sel_state[1] System SLE D mux_sel_state_ns[1] 19.778 18.987 FF_BLKS_0.ff_fsm_0.mux_sel_state[0] System SLE D mux_sel_state_ns[0] 19.778 19.001 ================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.778 - Propagation time: 0.791 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 18.987 Number of logic level(s): 1 Starting point: FF_BLKS_0.FLASH_FREEZE_0 / FF_TO_START Ending point: FF_BLKS_0.ff_fsm_0.mux_sel_state[1] / D The start point is clocked by System [rising] The end point is clocked by SystemBuilder_0/CCC_0/GL0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- FF_BLKS_0.FLASH_FREEZE_0 FLASH_FREEZE FF_TO_START Out 0.000 0.000 r - FLASH_FREEZE_0_FF_TO_START Net - - 0.432 - 2 FF_BLKS_0.ff_fsm_0.mux_sel_state_ns_0_a2[1] CFG2 B In - 0.432 r - FF_BLKS_0.ff_fsm_0.mux_sel_state_ns_0_a2[1] CFG2 Y Out 0.143 0.575 r - mux_sel_state_ns[1] Net - - 0.216 - 1 FF_BLKS_0.ff_fsm_0.mux_sel_state[1] SLE D In - 0.791 r - ========================================================================================================================= Total path delay (propagation time + setup) of 1.013 is 0.365(36.0%) logic and 0.648(64.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(10) | Timing constraint (from [get_cells { SystemBuilder_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { SystemBuilder_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(11) | Timing constraint (from [get_cells { SystemBuilder_0.CORERESETP_0.MSS_HPMS_READY_int SystemBuilder_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { SystemBuilder_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(12) | Timing constraint (through [get_nets { SystemBuilder_0.CORERESETP_0.CONFIG1_DONE SystemBuilder_0.CORERESETP_0.CONFIG2_DONE SystemBuilder_0.CORERESETP_0.SDIF*_PERST_N SystemBuilder_0.CORERESETP_0.SDIF*_PSEL SystemBuilder_0.CORERESETP_0.SDIF*_PWRITE SystemBuilder_0.CORERESETP_0.SDIF*_PRDATA[*] SystemBuilder_0.CORERESETP_0.SOFT_EXT_RESET_OUT SystemBuilder_0.CORERESETP_0.SOFT_RESET_F2M SystemBuilder_0.CORERESETP_0.SOFT_M3_RESET SystemBuilder_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET SystemBuilder_0.CORERESETP_0.SOFT_FDDR_CORE_RESET SystemBuilder_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET SystemBuilder_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET SystemBuilder_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET SystemBuilder_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(13) | Timing constraint (through [get_pins { SystemBuilder_0.SystemBuilder_HPMS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(14) | Timing constraint (through [get_pins { SystemBuilder_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 209MB peak: 217MB) Finished timing report (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 209MB peak: 217MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2gl010tsvf400-1 Cell usage: CCC 1 use CLKINT 7 uses FLASH_FREEZE 1 use MSS_010 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use CFG1 7 uses CFG2 224 uses CFG3 235 uses CFG4 424 uses Carry cells: ARI1 161 uses - used for arithmetic functions Sequential Cells: SLE 660 uses DSP Blocks: 0 of 22 (0%) I/O ports: 57 I/O primitives: 56 INBUF 30 uses OUTBUF 26 uses Global Clock Buffers: 7 RAM/ROM usage summary Total Block RAMs (RAM1K18) : 1 of 21 (4%) Total LUTs: 1051 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 36; LUTs = 36; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 660 + 0 + 36 + 0 = 696; Total number of LUTs after P&R: 1051 + 0 + 36 + 0 = 1087; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 70MB peak: 217MB) Process took 0h:00m:09s realtime, 0h:00m:09s cputime # Wed Mar 31 12:54:49 2021 ###########################################################]