| Project Settings |
|---|
| Project Name | top_syn | Device Name | synthesis: Microchip IGLOO2 : M2GL010TS |
| Implementation Name | synthesis | Top Module | top |
| Retiming | 0 | Resource Sharing | 1 |
| Fanout Guide | 10000 | Disable I/O Insertion | 0 |
| Disable Sequential Optimizations | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
175 |
271 |
0 |
- |
00m:14s |
- |
31-03-2021
12.54.33 PM |
| (premap) | Complete |
62 |
37 |
0 |
0m:03s |
0m:03s |
207MB |
31-03-2021
12.54.39 PM |
| (fpga_mapper) | Complete |
163 |
276 |
0 |
0m:09s |
0m:09s |
217MB |
31-03-2021
12.54.49 PM |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 31-03-2021
12.54.35 PM |
| Area Summary |
|---|
| |
| Carry Cells | 161 |
Sequential Cells | 660 |
| DSP Blocks
(dsp_used) | 0 |
I/O Cells | 56 |
| Global Clock Buffers | 7 |
RAM1K18
(v_ram) | 1 |
| LUTs
(total_luts) | 1051 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| SystemBuilder_0/CCC_0/GL0 | 50.0 MHz | 90.8 MHz | 8.990 |
| SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | 487.3 MHz | 17.948 |
| top|rclk_user | 100.0 MHz | NA | NA |
| top|wclk_user | 100.0 MHz | NA | NA |
| System | 100.0 MHz | NA | 18.987 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 3 |
| |
|