@W: CL113 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\AHBMASTER_FIC.v":74:0:74:5|Feedback mux created for signal HWDATA[31:8]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\AHBMASTER_FIC.v":74:0:74:5|All reachable assignments to HWDATA[31:8] assign 0, register removed by optimization
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\AHBMASTER_FIC.v":74:0:74:5|Optimizing register bit HTRANS[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\AHBMASTER_FIC.v":74:0:74:5|Pruning register bit 0 of HTRANS[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":789:3:789:8|Pruning unused register cuhprior_flushdone_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":738:3:738:8|Pruning unused register pord_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":738:3:738:8|Pruning unused register pord_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":592:3:592:8|Pruning unused register custatus_out_en_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":522:3:522:8|Pruning unused register pord_comb_d1. Make sure that there are no unused intermediate registers.
@W: CL207 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":719:3:719:8|All reachable assignments to pord assign 0, register removed by optimization.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":505:3:505:8|Optimizing register bit hprior_kp_busy_high to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit uclatchoptions_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Optimizing register bit ucmdbyte_req_hold[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 5 to 2 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bit 0 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 7 to 5 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bit 3 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":653:3:653:8|Pruning register bits 1 to 0 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v":505:3:505:8|Pruning unused register hprior_kp_busy_high. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":418:30:418:40|Object cfwr_req_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":436:30:436:43|Object cfsrc_addr_int is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":437:30:437:43|Object cfdst_addr_int is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":447:30:447:39|Object memwr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":470:30:470:44|Object req_srcreg_addr is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":472:30:472:44|Object req_srcreg_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":512:30:512:50|Object cuhprior_flushdone_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":555:30:555:41|Removing wire cfwr_req_int, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":557:30:557:39|Removing wire cfwr_req_c, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":563:30:563:39|Removing wire cfdata_w_o, as there is no assignment to it.
@W: CL318 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":372:29:372:42|*Output cutrans_done_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL168 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2927:16:2927:29|Removing instance FLASH_FREEZE_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2980:3:2980:8|Pruning unused register FF_exit. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2962:3:2962:8|Pruning unused register FF_exit_led. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2949:3:2949:8|Pruning unused register FF_entry_led. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2939:3:2939:8|Pruning unused register FF_entry. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning unused register cunvm_bfr_iapverify_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2770:3:2770:8|Pruning unused register latchen_hrdata_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register fiicreg_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register commctrlreg_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Pruning unused register commpoll_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Pruning unused register set_puf_getkcnum_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1906:3:1906:8|Pruning unused register wait_count[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1731:3:1731:8|Pruning unused register fctrans_done_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1611:3:1611:8|Pruning unused register pord_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1611:3:1611:8|Pruning unused register pord_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1582:3:1582:8|Pruning unused register req_phase_active_pulse. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1532:3:1532:8|Pruning unused register resp_data_done_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1532:3:1532:8|Pruning unused register req_phase_active_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1033:3:1033:8|Pruning unused register resp_desc_done. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1033:3:1033:8|Pruning unused register resp_frm_done. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1015:3:1015:8|Pruning unused register req_desc_done. Make sure that there are no unused intermediate registers.
@W: CL271 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Pruning unused bits 31 to 8 of fcdataout_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL113 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2811:3:2811:8|Feedback mux created for signal cutamper_msg[7:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL207 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2786:3:2786:8|All reachable assignments to cutamper_msg_valid assign 0, register removed by optimization.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2461:3:2461:8|Sharing sequential element fcpop_d1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element tamper_fail_valid_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element tamper_detect_valid_r. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL207 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1594:3:1594:8|All reachable assignments to pord assign 0, register removed by optimization.
@W: CL250 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2811:3:2811:8|All reachable assignments to cutamper_msg[7:0] assign 0, register removed by optimization
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Optimizing register bit cutamper_detect_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Optimizing register bit cutamper_fail_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_addr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Optimizing register bit resp_srcreg_data_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 31 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 29 to 17 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 15 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 12 to 5 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 1 to 0 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 31 to 30 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 28 to 8 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bits 6 to 5 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 2 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning register bit 0 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Pruning unused register cutamper_detect_valid. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1944:3:1944:8|Pruning unused register cutamper_fail_valid. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":236:21:236:36|Object rvalid_out_en_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":237:21:237:36|Object rvalid_out_en_d2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":245:21:245:31|Removing wire fmhaddr_lat, as there is no assignment to it.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":952:3:952:8|Pruning unused register busreq_prev. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":934:6:934:11|Pruning unused register pop_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":868:5:868:10|Pruning unused register fmhtrans_int2[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":732:3:732:8|Pruning unused register haddr_prev[29:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":709:2:709:7|Pruning unused register latch_addr_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":709:2:709:7|Pruning unused register latch_addr_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":639:2:639:7|Pruning unused register latch_addr_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":627:2:627:7|Pruning unused register state_prev_clk[3:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":853:5:853:10|Optimizing register bit fmhtrans_int[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":853:5:853:10|Pruning register bit 0 of fmhtrans_int[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Pruning register bits 2 to 1 of fmhburst_d1[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":259:29:259:41|Removing wire cfburst_len_o, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":265:29:265:42|Removing wire ustatus_resp_o, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":266:29:266:35|Removing wire ubusy_o, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":267:29:267:38|Removing wire udata_en_o, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":268:29:268:41|Removing wire udata_valid_o, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":269:29:269:37|Removing wire udata_r_o, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":275:29:275:41|Removing wire uclatchpord_o, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":281:29:281:45|Removing wire uccrypto_opmode_o, as there is no assignment to it.
@W: CG360 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v":304:29:304:40|Removing wire cudata_wen_o, as there is no assignment to it.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Optimizing register bit serv_cmdbyte_req[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Optimizing register bit serv_cmdbyte_req[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Optimizing register bit serv_cmdbyte_req[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Optimizing register bit serv_cmdbyte_req[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Optimizing register bit serv_cmdbyte_req[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Optimizing register bit serv_cmdbyte_req[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Optimizing register bit serv_cmdbyte_req[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Pruning register bits 7 to 2 of serv_cmdbyte_req[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Pruning register bit 0 of serv_cmdbyte_req[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":568:2:568:11|Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":568:2:568:11|Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":568:2:568:11|Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":568:2:568:11|Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":2813:2:2813:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":217:2:217:15|Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":633:0:633:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":2879:2:2879:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":2945:2:2945:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":217:2:217:15|Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":633:0:633:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG1283 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":3011:2:3011:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1728:4:1728:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1696:4:1696:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1664:4:1664:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1632:4:1632:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1600:4:1600:9|Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1480:4:1480:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1415:4:1415:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1350:4:1350:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1285:4:1285:9|Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1204:4:1204:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1503:4:1503:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1548:4:1548:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1204:4:1204:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1548:4:1548:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1548:4:1548:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":868:4:868:9|Pruning unused register sm2_areset_n_q2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":868:4:868:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL318 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\FABOSC_0\SystemBuilder_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\FABOSC_0\SystemBuilder_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\FABOSC_0\SystemBuilder_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\FABOSC_0\SystemBuilder_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder_HPMS\SystemBuilder_HPMS.v":53:14:53:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif3_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":184:15:184:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":197:15:197:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":210:15:210:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":223:15:223:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":236:15:236:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":249:15:249:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":262:15:262:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":275:15:275:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":288:15:288:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":301:15:301:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":314:15:314:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":327:15:327:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":340:15:340:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":353:15:353:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":366:15:366:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":379:15:379:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v":392:15:392:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL246 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:25|Input port bits 15 to 2 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:25|Input port bit 0 of SDATAREADY[16:0] is unused
@W: CL246 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":44:16:44:21|Input port bits 15 to 2 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":44:16:44:21|Input port bit 0 of SHRESP[16:0] is unused
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v":232:4:232:9|Pruning unused register serv_cmdbyte_req[1]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Optimizing register bit fmhburst_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v":293:3:293:8|Pruning unused register fmhburst_d1[0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":997:3:997:8|Optimizing register bit burstlen_memwr_data_r[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_rd_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Pruning register bits 31 to 16 of cfburst_len_rd_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":997:3:997:8|Pruning register bit 31 of burstlen_memwr_data_r[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL177 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1924:3:1924:8|Sharing sequential element fcdataout_d1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Optimizing register bit cfburst_len_wr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1096:3:1096:8|Pruning register bit 31 of cfburst_len_wr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1895:3:1895:8|Optimizing register bit cfrd_asyncevent_o to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":2889:3:2889:8|Pruning unused register resp_srcreg_addr_d1[30]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v":1895:3:1895:8|Pruning unused register cfrd_asyncevent_o. Make sure that there are no unused intermediate registers.
@W: CL247 :"C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3.v":40:0:40:5|Input port bit 0 of HTRANS[1:0] is unused

