set_device -family {IGLOO2} -die {M2GL010TS} -speed {-1}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\AHBMASTER_FIC.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\RAM_with_wrapper\SRAM_64x8_0\RAM_with_wrapper_SRAM_64x8_0_TPSRAM.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\mem_apb_wrp.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\mux_blk.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\RAM_with_wrapper\RAM_with_wrapper.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3_ahbtoapbsm.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3_penablescheduler.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core_obfuscated\coreahbtoapb3.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\AHBMASTER_FIC_RAM\AHBMASTER_FIC_RAM.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\FF_FSM.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\FF_BLKS\FF_BLKS.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CCC_0\SystemBuilder_CCC_0_FCCC.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\FABOSC_0\SystemBuilder_FABOSC_0_OSC.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder_HPMS\SystemBuilder_HPMS.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_slavearbiter.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_slavestage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_defaultslavesm.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_addrdec.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\CoreAHBLite_0\rtl\vlog\core\coreahblite.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\SystemBuilder\SystemBuilder.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\cnt34.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\hdl\counter_delay.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_CmdDec.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_FSMCtrl.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\Actel\DirectCore\CORESYSSERVICES\3.2.102\rtl\vlog\core\CoreSysServices_UserIF.v}
read_verilog -mode system_verilog -lib CORESYSSERVICES_LIB {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v}
read_verilog -mode system_verilog {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\component\work\top\top.v}
set_top_level {top}
map_netlist
read_sdc {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\constraint\top_derived_constraints.sdc}
check_constraints {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\constraint\synthesis_sdc_errors.log}
write_fdc {C:\tcl_update\igl2\ac412\AC412_IGL2_Flash_Freeze_Entry_Exit\Libero_Project\designer\top\synthesis.fdc}
