# Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Wed Mar 31 12:56:42 2021

Design | top
Family | IGLOO2
Die | M2GL010TS
Package | 484 FBGA
Temperature Range | 0 - 85 C
Voltage Range | 1.14 - 1.26 V
Speed Grade | -1
Design State | Post-Layout
Data source | Production
Multi Corner Report Operating Conditions | BEST, TYPICAL, WORST
Scenario for Timing Analysis | timing_analysis

## Summary

Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions
--- | --- | --- | --- | ---
SystemBuilder_0/CCC_0/GL0 | 20.000 | 50.000 | 12.793 | WORST
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 | 50.000 | 16.853 | WORST

| Worst Slack (ns) | Operating Conditions
--- | --- | ---
Input to Output |  | WORST

## Clock Domain SystemBuilder_0/CCC_0/GL0

### SET Register to Register

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE | CORESYSSERVICES_0/U_CmdDec/unreg_cmd:EN | 6.547 | 12.793 | 11.035 | 23.828 | 0.308 | 7.207 | WORST
Path 2 | CORESYSSERVICES_0/U_fsm_ctrl/fmhaddr_o[29]:CLK | AHBMASTER_FIC_RAM_0/COREAHBTOAPB3_0/CAHBtoAPB3lll/HREADYOUT:D | 6.475 | 13.228 | 10.646 | 23.874 | 0.254 | 6.772 | WORST
Path 3 | CORESYSSERVICES_0/U_fsm_ctrl/fmhaddr_o[29]:CLK | AHBMASTER_FIC_RAM_0/COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3lII:EN | 6.399 | 13.243 | 10.570 | 23.813 | 0.308 | 6.757 | WORST
Path 4 | SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE | CORESYSSERVICES_0/U_fsm_ctrl/word_count[30]:D | 6.135 | 13.271 | 10.623 | 23.894 | 0.254 | 6.729 | WORST
Path 5 | SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE | AHBMASTER_FIC_RAM_0/AHBMASTER_FIC_0/RAM_ADDR[10]:EN | 6.081 | 13.289 | 10.569 | 23.858 | 0.308 | 6.711 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE |  |  |  |  |  |  |  |
To: CORESYSSERVICES_0/U_CmdDec/unreg_cmd:EN |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 23.828 |  |
data arrival time |  |  |  | - |  | 11.035 |  |
slack |  |  |  |  |  | 12.793 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 2.784 | 2.784 |  |
SystemBuilder_0/CCC_0/GL0_INST:An | net | SystemBuilder_0/CCC_0/GL0_net |  | + | 0.197 | 2.981 |  | r
SystemBuilder_0/CCC_0/GL0_INST:YNn | cell |  | ADLIB:GB | + | 0.165 | 3.146 | 4 | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1:An | net | SystemBuilder_0/CCC_0/GL0_INST/U0_YNn |  | + | 0.282 | 3.428 |  | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.250 | 3.678 | 1 | r
SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B | net | SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_YR |  | + | 0.385 | 4.063 |  | r
SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB | cell |  | ADLIB:IP_INTERFACE | + | 0.209 | 4.272 | 1 | r
SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE | net | SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net |  | + | 0.216 | 4.488 |  | r
SystemBuilder_0/SystemBuilder_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_RDATA[23] | cell |  | ADLIB:MSS_010_IP | + | 1.441 | 5.929 | 2 | r
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_23_tz_8:B | net | SystemBuilder_0.CoreAHBLite_0_AHBmslave16_HRDATA[23] |  | + | 1.097 | 7.026 |  | r
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_23_tz_8:Y | cell |  | ADLIB:CFG4 | + | 0.326 | 7.352 | 1 | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_23_tz:A | net | CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_23_tz_8_Z |  | + | 0.623 | 7.975 |  | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_23_tz:Y | cell |  | ADLIB:CFG4 | + | 0.164 | 8.139 | 1 | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_5:B | net | CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_23_tz_Z |  | + | 0.224 | 8.363 |  | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_5:Y | cell |  | ADLIB:CFG4 | + | 0.087 | 8.450 | 1 | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_10:C | net | CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_5_Z |  | + | 0.689 | 9.139 |  | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_10:Y | cell |  | ADLIB:CFG3 | + | 0.087 | 9.226 | 1 | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5:C | net | CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_10_Z |  | + | 0.094 | 9.320 |  | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd5:Y | cell |  | ADLIB:CFG4 | + | 0.087 | 9.407 | 2 | f
CORESYSSERVICES_0/U_CmdDec/un1_resp_curr_state_16:A | net | CORESYSSERVICES_0/U_CmdDec/unreg_cmd5_Z |  | + | 0.882 | 10.289 |  | f
CORESYSSERVICES_0/U_CmdDec/un1_resp_curr_state_16:Y | cell |  | ADLIB:CFG2 | + | 0.198 | 10.487 | 1 | f
CORESYSSERVICES_0/U_CmdDec/unreg_cmd:EN | net | CORESYSSERVICES_0/U_CmdDec/un1_resp_curr_state_16_Z |  | + | 0.548 | 11.035 |  | f
data arrival time |  |  |  |  |  | 11.035 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 | Clock Constraint |  |  |  | 20.000 | 20.000 |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 20.000 |  | r
| Clock generation |  |  | + | 2.784 | 22.784 |  |
SystemBuilder_0/CCC_0/GL0_INST:An | net | SystemBuilder_0/CCC_0/GL0_net |  | + | 0.197 | 22.981 |  | r
SystemBuilder_0/CCC_0/GL0_INST:YSn | cell |  | ADLIB:GB | + | 0.166 | 23.147 | 8 | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An | net | SystemBuilder_0/CCC_0/GL0_INST/U0_YNn_GSouth |  | + | 0.282 | 23.429 |  | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR | cell |  | ADLIB:RGB | + | 0.250 | 23.679 | 37 | r
CORESYSSERVICES_0/U_CmdDec/unreg_cmd:CLK | net | SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1 |  | + | 0.457 | 24.136 |  | r
CORESYSSERVICES_0/U_CmdDec/unreg_cmd:EN | Library setup time |  | ADLIB:SLE | - | 0.308 | 23.828 |  |
data required time |  |  |  |  |  | 23.828 |  |
Operating Conditions | WORST

### SET External Setup

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | External Setup (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | wr_enable_user | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[5] | 5.409 |  | 5.409 |  | 0.267 | 0.026 | WORST
Path 2 | wr_enable_user | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[6] | 5.386 |  | 5.386 |  | 0.285 | 0.021 | WORST
Path 3 | wr_enable_user | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[4] | 3.568 |  | 3.568 |  | 0.324 | -0.009 | BEST
Path 4 | wr_enable_user | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[3] | 3.532 |  | 3.532 |  | 0.332 | -0.037 | BEST
Path 5 | wr_enable_user | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_BLK[2] | 3.684 |  | 3.684 |  | 0.151 | -0.066 | BEST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: wr_enable_user |  |  |  |  |  |  |  |
To: AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[5] |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | N/C |  |
data arrival time |  |  |  | - |  | 5.409 |  |
slack |  |  |  |  |  | N/C |  |
Data arrival time calculation |  |  |  |  |  |  |  |
wr_enable_user |  |  |  |  | 0.000 | 0.000 |  | f
wr_enable_user_ibuf/U0/U_IOPAD:PAD | net | wr_enable_user |  | + | 0.000 | 0.000 |  | f
wr_enable_user_ibuf/U0/U_IOPAD:Y | cell |  | ADLIB:IOPAD_IN | + | 1.171 | 1.171 | 1 | f
wr_enable_user_ibuf/U0/U_IOINFF:A | net | wr_enable_user_ibuf/U0/YIN1 |  | + | -0.004 | 1.167 |  | f
wr_enable_user_ibuf/U0/U_IOINFF:Y | cell |  | ADLIB:IOINFF_BYPASS | + | 0.079 | 1.246 | 1 | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/wr_en:B | net | wr_enable_user_c |  | + | 1.932 | 3.178 |  | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/wr_en:Y | cell |  | ADLIB:CFG3 | + | 0.209 | 3.387 | 7 | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/un7_waddr[2]:B | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0_wr_en |  | + | 0.865 | 4.252 |  | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/un7_waddr[2]:Y | cell |  | ADLIB:CFG4 | + | 0.099 | 4.351 | 1 | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/CFG_13:C | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0_waddr[2] |  | + | 0.807 | 5.158 |  | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/CFG_13:IPC | cell |  | ADLIB:CFG2_IP_BC | + | 0.205 | 5.363 | 1 | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[5] | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/B_ADDR_net[5] |  | + | 0.046 | 5.409 |  | r
data arrival time |  |  |  |  |  | 5.409 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 |  |  |  |  | N/C | N/C |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | N/C |  | r
| Clock generation |  |  | + | 2.700 | N/C |  |
SystemBuilder_0/CCC_0/GL0_INST:An | net | SystemBuilder_0/CCC_0/GL0_net |  | + | 0.191 | N/C |  | r
SystemBuilder_0/CCC_0/GL0_INST:YSn | cell |  | ADLIB:GB | + | 0.161 | N/C | 8 | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An | net | SystemBuilder_0/CCC_0/GL0_INST/U0_YNn_GSouth |  | + | 0.274 | N/C |  | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YL | cell |  | ADLIB:RGB | + | 0.243 | N/C | 2 | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/wclk:B | net | SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbl_net_1 |  | + | 0.388 | N/C |  | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/wclk:Y | cell |  | ADLIB:CFG3 | + | 0.185 | N/C | 1 | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/FF_24:CLK | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0_wclk |  | + | 1.366 | N/C |  | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/FF_24:IPCLKn | cell |  | ADLIB:SLE_IP_CLK | + | 0.057 | N/C | 1 | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_CLK | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/B_CLK_net |  | + | 0.085 | N/C |  | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_ADDR[5] | Library setup time |  | ADLIB:RAM1K18_IP | - | 0.267 | N/C |  |
Operating Conditions | WORST

### SET Clock to Output

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_CLK | rdata_user[3] | 7.006 |  | 14.309 |  | 14.309 | WORST
Path 2 | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_CLK | rdata_user[6] | 6.902 |  | 14.205 |  | 14.205 | WORST
Path 3 | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_CLK | rdata_user[5] | 6.896 |  | 14.199 |  | 14.199 | WORST
Path 4 | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_CLK | rdata_user[4] | 6.458 |  | 13.761 |  | 13.761 | WORST
Path 5 | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_CLK | rdata_user[7] | 6.340 |  | 13.643 |  | 13.643 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_CLK |  |  |  |  |  |  |  |
To: rdata_user[3] |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | N/C |  |
data arrival time |  |  |  | - |  | 14.309 |  |
slack |  |  |  |  |  | N/C |  |
Data arrival time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 2.784 | 2.784 |  |
SystemBuilder_0/CCC_0/GL0_INST:An | net | SystemBuilder_0/CCC_0/GL0_net |  | + | 0.197 | 2.981 |  | r
SystemBuilder_0/CCC_0/GL0_INST:YSn | cell |  | ADLIB:GB | + | 0.166 | 3.147 | 8 | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An | net | SystemBuilder_0/CCC_0/GL0_INST/U0_YNn_GSouth |  | + | 0.282 | 3.429 |  | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YL | cell |  | ADLIB:RGB | + | 0.251 | 3.680 | 2 | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk:B | net | SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbl_net_1 |  | + | 0.404 | 4.084 |  | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk:Y | cell |  | ADLIB:CFG3 | + | 0.191 | 4.275 | 1 | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk_RNINKRC:An | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk_Z |  | + | 1.641 | 5.916 |  | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk_RNINKRC:YSn | cell |  | ADLIB:GB | + | 0.221 | 6.137 | 1 | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk_RNINKRC/U0_RGB1:An | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk_RNINKRC/U0_YNn_GSouth |  | + | 0.303 | 6.440 |  | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk_RNINKRC/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.250 | 6.690 | 3 | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/FF_1:CLK | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rclk_RNINKRC/U0_RGB1_YR |  | + | 0.466 | 7.156 |  | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/FF_1:IPCLKn | cell |  | ADLIB:SLE_IP_CLK | + | 0.059 | 7.215 | 1 | f
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT_CLK | net | AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/A_DOUT_CLK_net |  | + | 0.088 | 7.303 |  | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_DOUT[3] | cell |  | ADLIB:RAM1K18_IP | + | 0.294 | 7.597 | 2 | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rdata_user[3]:A | net | AHBMASTER_FIC_RAM_0/CoreAPB3_0_APBmslave0_PRDATA[3] |  | + | 1.390 | 8.987 |  | r
AHBMASTER_FIC_RAM_0/RAM_with_wrapper_0/mux_blk_0/rdata_user[3]:Y | cell |  | ADLIB:CFG2 | + | 0.074 | 9.061 | 1 | r
rdata_user_obuf[3]/U0/U_IOOUTFF:A | net | rdata_user_c[3] |  | + | 1.531 | 10.592 |  | r
rdata_user_obuf[3]/U0/U_IOOUTFF:Y | cell |  | ADLIB:IOOUTFF_BYPASS | + | 0.186 | 10.778 | 1 | r
rdata_user_obuf[3]/U0/U_IOPAD:D | net | rdata_user_obuf[3]/U0/DOUT |  | + | 0.363 | 11.141 |  | r
rdata_user_obuf[3]/U0/U_IOPAD:PAD | cell |  | ADLIB:IOPAD_TRI | + | 3.168 | 14.309 | 0 | r
rdata_user[3] | net | rdata_user[3] |  | + | 0.000 | 14.309 |  | r
data arrival time |  |  |  |  |  | 14.309 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 |  |  |  |  | N/C | N/C |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | N/C |  | r
| Clock generation |  |  | + | 2.784 | N/C |  |
rdata_user[3] |  |  |  |  |  | N/C |  | r
Operating Conditions | WORST

### SET Register to Asynchronous

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | SystemBuilder_0/CORERESETP_0/sm0_areset_n_q1:ALn | 2.953 | 16.686 | 7.103 | 23.789 | 0.353 | 3.314 | 0.008 | WORST
Path 2 | SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | SystemBuilder_0/CORERESETP_0/sm0_areset_n_q2:ALn | 2.953 | 16.699 | 7.103 | 23.802 | 0.353 | 3.301 | -0.005 | WORST
Path 3 | SystemBuilder_0/CORERESETP_0/sm0_areset_n_q2:CLK | SystemBuilder_0/CORERESETP_0/sm0_state[2]:ALn | 2.848 | 16.770 | 7.018 | 23.788 | 0.353 | 3.230 | 0.029 | WORST
Path 4 | SystemBuilder_0/CORERESETP_0/sm0_areset_n_q2:CLK | SystemBuilder_0/CORERESETP_0/sm0_state[0]:ALn | 2.848 | 16.770 | 7.018 | 23.788 | 0.353 | 3.230 | 0.029 | WORST
Path 5 | SystemBuilder_0/CORERESETP_0/sm0_areset_n_q2:CLK | SystemBuilder_0/CORERESETP_0/INIT_DONE_int_rep:ALn | 2.848 | 16.770 | 7.018 | 23.788 | 0.353 | 3.230 | 0.029 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:CLK |  |  |  |  |  |  |  |
To: SystemBuilder_0/CORERESETP_0/sm0_areset_n_q1:ALn |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 23.789 |  |
data arrival time |  |  |  | - |  | 7.103 |  |
slack |  |  |  |  |  | 16.686 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 2.784 | 2.784 |  |
SystemBuilder_0/CCC_0/GL0_INST:An | net | SystemBuilder_0/CCC_0/GL0_net |  | + | 0.197 | 2.981 |  | r
SystemBuilder_0/CCC_0/GL0_INST:YNn | cell |  | ADLIB:GB | + | 0.165 | 3.146 | 4 | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An | net | SystemBuilder_0/CCC_0/GL0_INST/U0_YNn |  | + | 0.272 | 3.418 |  | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR | cell |  | ADLIB:RGB | + | 0.250 | 3.668 | 13 | r
SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | net | SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1 |  | + | 0.482 | 4.150 |  | r
SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:Q | cell |  | ADLIB:SLE | + | 0.087 | 4.237 | 1 | r
SystemBuilder_0/CORERESETP_0/sdif0_areset_n:A | net | SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY |  | + | 0.311 | 4.548 |  | r
SystemBuilder_0/CORERESETP_0/sdif0_areset_n:Y | cell |  | ADLIB:CFG2 | + | 0.074 | 4.622 | 1 | r
SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567:An | net | SystemBuilder_0/CORERESETP_0/sm0_areset_n |  | + | 1.256 | 5.878 |  | f
SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567:YNn | cell |  | ADLIB:GB | + | 0.220 | 6.098 | 1 | f
SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567/U0_RGB1:An | net | SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567/U0_YNn |  | + | 0.281 | 6.379 |  | f
SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.250 | 6.629 | 2 | r
SystemBuilder_0/CORERESETP_0/sm0_areset_n_q1:ALn | net | SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567/U0_RGB1_YR |  | + | 0.474 | 7.103 |  | r
data arrival time |  |  |  |  |  | 7.103 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 | Clock Constraint |  |  |  | 20.000 | 20.000 |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 20.000 |  | r
| Clock generation |  |  | + | 2.784 | 22.784 |  |
SystemBuilder_0/CCC_0/GL0_INST:An | net | SystemBuilder_0/CCC_0/GL0_net |  | + | 0.197 | 22.981 |  | r
SystemBuilder_0/CCC_0/GL0_INST:YNn | cell |  | ADLIB:GB | + | 0.165 | 23.146 | 4 | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An | net | SystemBuilder_0/CCC_0/GL0_INST/U0_YNn |  | + | 0.271 | 23.417 |  | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR | cell |  | ADLIB:RGB | + | 0.250 | 23.667 | 96 | r
SystemBuilder_0/CORERESETP_0/sm0_areset_n_q1:CLK | net | SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 |  | + | 0.475 | 24.142 |  | r
SystemBuilder_0/CORERESETP_0/sm0_areset_n_q1:ALn | Library recovery time |  | ADLIB:SLE | - | 0.353 | 23.789 |  |
data required time |  |  |  |  |  | 23.789 |  |
Operating Conditions | WORST

### SET External Recovery

No Path

### SET Asynchronous to Register

No Path

### SET SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to SystemBuilder_0/CCC_0/GL0

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | SystemBuilder_0/CORERESETP_0/ddr_settled:CLK | SystemBuilder_0/CORERESETP_0/ddr_settled_q1:D | 0.835 | 18.064 | 5.837 | 23.901 | 0.254 | WORST
Path 2 | SystemBuilder_0/CORERESETP_0/release_sdif1_core:CLK | SystemBuilder_0/CORERESETP_0/release_sdif1_core_q1:D | 0.789 | 18.118 | 5.783 | 23.901 | 0.254 | WORST
Path 3 | SystemBuilder_0/CORERESETP_0/release_sdif2_core:CLK | SystemBuilder_0/CORERESETP_0/release_sdif2_core_q1:D | 0.784 | 18.123 | 5.778 | 23.901 | 0.254 | WORST
Path 4 | SystemBuilder_0/CORERESETP_0/release_sdif0_core:CLK | SystemBuilder_0/CORERESETP_0/release_sdif0_core_q1:D | 0.615 | 18.244 | 5.644 | 23.888 | 0.254 | WORST
Path 5 | SystemBuilder_0/CORERESETP_0/release_sdif3_core:CLK | SystemBuilder_0/CORERESETP_0/release_sdif3_core_q1:D | 0.618 | 18.296 | 5.604 | 23.900 | 0.254 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: SystemBuilder_0/CORERESETP_0/ddr_settled:CLK |  |  |  |  |  |  |  |
To: SystemBuilder_0/CORERESETP_0/ddr_settled_q1:D |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 23.901 |  |
data arrival time |  |  |  | - |  | 5.837 |  |
slack |  |  |  |  |  | 18.064 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT |  |  |  |  | 0.000 | 0.000 |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 0.000 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SystemBuilder_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 2.027 | 2.027 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 2.179 | 1 | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SystemBuilder_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 1.583 | 3.762 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn | cell |  | ADLIB:GB | + | 0.220 | 3.982 | 2 | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn |  | + | 0.300 | 4.282 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell |  | ADLIB:RGB | + | 0.251 | 4.533 | 13 | r
SystemBuilder_0/CORERESETP_0/ddr_settled:CLK | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 |  | + | 0.469 | 5.002 |  | r
SystemBuilder_0/CORERESETP_0/ddr_settled:Q | cell |  | ADLIB:SLE | + | 0.087 | 5.089 | 1 | r
SystemBuilder_0/CORERESETP_0/ddr_settled_q1:D | net | SystemBuilder_0/CORERESETP_0/ddr_settled_Z |  | + | 0.748 | 5.837 |  | r
data arrival time |  |  |  |  |  | 5.837 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 | Clock Constraint |  |  |  | 20.000 | 20.000 |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 20.000 |  | r
| Clock generation |  |  | + | 2.784 | 22.784 |  |
SystemBuilder_0/CCC_0/GL0_INST:An | net | SystemBuilder_0/CCC_0/GL0_net |  | + | 0.197 | 22.981 |  | r
SystemBuilder_0/CCC_0/GL0_INST:YNn | cell |  | ADLIB:GB | + | 0.165 | 23.146 | 4 | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An | net | SystemBuilder_0/CCC_0/GL0_INST/U0_YNn |  | + | 0.271 | 23.417 |  | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR | cell |  | ADLIB:RGB | + | 0.250 | 23.667 | 96 | r
SystemBuilder_0/CORERESETP_0/ddr_settled_q1:CLK | net | SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 |  | + | 0.488 | 24.155 |  | r
SystemBuilder_0/CORERESETP_0/ddr_settled_q1:D | Library setup time |  | ADLIB:SLE | - | 0.254 | 23.901 |  |
data required time |  |  |  |  |  | 23.901 |  |
Operating Conditions | WORST

## Clock Domain SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

### SET Register to Register

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | CLK_Sync_CNTR_Dly_0/q_int[3]:CLK | CLK_Sync_CNTR_Dly_0/q_int[7]:D | 2.878 | 16.853 | 7.908 | 24.761 | 0.254 | 3.147 | WORST
Path 2 | CLK_Sync_CNTR_Dly_0/q_int[3]:CLK | CLK_Sync_CNTR_Dly_0/q_int[9]:D | 2.865 | 16.866 | 7.895 | 24.761 | 0.254 | 3.134 | WORST
Path 3 | CLK_Sync_CNTR_Dly_0/q_int[5]:CLK | CLK_Sync_CNTR_Dly_0/q_int[7]:D | 2.845 | 16.886 | 7.875 | 24.761 | 0.254 | 3.114 | WORST
Path 4 | CLK_Sync_CNTR_Dly_0/q_int[3]:CLK | CLK_Sync_CNTR_Dly_0/q_int[4]:D | 2.850 | 16.894 | 7.880 | 24.774 | 0.254 | 3.106 | WORST
Path 5 | CLK_Sync_CNTR_Dly_0/q_int[5]:CLK | CLK_Sync_CNTR_Dly_0/q_int[9]:D | 2.832 | 16.899 | 7.862 | 24.761 | 0.254 | 3.101 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: CLK_Sync_CNTR_Dly_0/q_int[3]:CLK |  |  |  |  |  |  |  |
To: CLK_Sync_CNTR_Dly_0/q_int[7]:D |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 24.761 |  |
data arrival time |  |  |  | - |  | 7.908 |  |
slack |  |  |  |  |  | 16.853 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT |  |  |  |  | 0.000 | 0.000 |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 0.000 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SystemBuilder_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 2.027 | 2.027 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 2.179 | 1 | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SystemBuilder_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 1.583 | 3.762 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn | cell |  | ADLIB:GB | + | 0.220 | 3.982 | 2 | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn |  | + | 0.306 | 4.288 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.250 | 4.538 | 11 | r
CLK_Sync_CNTR_Dly_0/q_int[3]:CLK | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR |  | + | 0.492 | 5.030 |  | r
CLK_Sync_CNTR_Dly_0/q_int[3]:Q | cell |  | ADLIB:SLE | + | 0.087 | 5.117 | 2 | r
CLK_Sync_CNTR_Dly_0/count_done_int6_5:A | net | CLK_Sync_CNTR_Dly_0/q_int_Z[3] |  | + | 0.693 | 5.810 |  | r
CLK_Sync_CNTR_Dly_0/count_done_int6_5:Y | cell |  | ADLIB:CFG4 | + | 0.270 | 6.080 | 2 | r
CLK_Sync_CNTR_Dly_0/count_done_int6_5_RNI0KKJ:B | net | CLK_Sync_CNTR_Dly_0/count_done_int6_5_Z |  | + | 0.537 | 6.617 |  | r
CLK_Sync_CNTR_Dly_0/count_done_int6_5_RNI0KKJ:P | cell |  | ADLIB:ARI1_CC | + | 0.408 | 7.025 | 1 | f
CLK_Sync_CNTR_Dly_0/count_done_int6_5_RNI0KKJ_CC_0:P[0] | net | NET_CC_CONFIG2 |  | + | 0.000 | 7.025 |  | f
CLK_Sync_CNTR_Dly_0/count_done_int6_5_RNI0KKJ_CC_0:CC[8] | cell |  | ADLIB:CC_CONFIG | + | 0.739 | 7.764 | 1 | r
CLK_Sync_CNTR_Dly_0/q_int_RNISLUJ2[7]:CC | net | NET_CC_CONFIG28 |  | + | 0.000 | 7.764 |  | r
CLK_Sync_CNTR_Dly_0/q_int_RNISLUJ2[7]:S | cell |  | ADLIB:ARI1_CC | + | 0.066 | 7.830 | 1 | r
CLK_Sync_CNTR_Dly_0/q_int[7]:D | net | CLK_Sync_CNTR_Dly_0/q_int_s[7] |  | + | 0.078 | 7.908 |  | r
data arrival time |  |  |  |  |  | 7.908 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint |  |  |  | 20.000 | 20.000 |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 20.000 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SystemBuilder_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 2.027 | 22.027 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 22.179 | 1 | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SystemBuilder_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 1.583 | 23.762 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn | cell |  | ADLIB:GB | + | 0.220 | 23.982 | 2 | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn |  | + | 0.306 | 24.288 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.250 | 24.538 | 11 | r
CLK_Sync_CNTR_Dly_0/q_int[7]:CLK | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR |  | + | 0.477 | 25.015 |  | r
CLK_Sync_CNTR_Dly_0/q_int[7]:D | Library setup time |  | ADLIB:SLE | - | 0.254 | 24.761 |  |
data required time |  |  |  |  |  | 24.761 |  |
Operating Conditions | WORST

### SET External Setup

No Path

### SET Clock to Output

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | CLK_Sync_CNTR_Dly_0/count_done_int:CLK | Y | 5.190 |  | 10.233 |  | 10.233 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: CLK_Sync_CNTR_Dly_0/count_done_int:CLK |  |  |  |  |  |  |  |
To: Y |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | N/C |  |
data arrival time |  |  |  | - |  | 10.233 |  |
slack |  |  |  |  |  | N/C |  |
Data arrival time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT |  |  |  |  | 0.000 | 0.000 |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 0.000 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SystemBuilder_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 2.027 | 2.027 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 2.179 | 1 | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SystemBuilder_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 1.583 | 3.762 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn | cell |  | ADLIB:GB | + | 0.220 | 3.982 | 2 | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn |  | + | 0.306 | 4.288 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.250 | 4.538 | 11 | r
CLK_Sync_CNTR_Dly_0/count_done_int:CLK | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR |  | + | 0.505 | 5.043 |  | r
CLK_Sync_CNTR_Dly_0/count_done_int:Q | cell |  | ADLIB:SLE | + | 0.108 | 5.151 | 1 | f
Y_obuf/U0/U_IOOUTFF:A | net | Y_c |  | + | 1.955 | 7.106 |  | f
Y_obuf/U0/U_IOOUTFF:Y | cell |  | ADLIB:IOOUTFF_BYPASS | + | 0.330 | 7.436 | 1 | f
Y_obuf/U0/U_IOPAD:D | net | Y_obuf/U0/DOUT |  | + | 0.095 | 7.531 |  | f
Y_obuf/U0/U_IOPAD:PAD | cell |  | ADLIB:IOPAD_TRI | + | 2.702 | 10.233 | 0 | f
Y | net | Y |  | + | 0.000 | 10.233 |  | f
data arrival time |  |  |  |  |  | 10.233 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT |  |  |  |  | N/C | N/C |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | N/C |  | r
Y |  |  |  |  |  | N/C |  | f
Operating Conditions | WORST

### SET Register to Asynchronous

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:CLK | SystemBuilder_0/CORERESETP_0/ddr_settled:ALn | 1.486 | 18.120 | 6.515 | 24.635 | 0.353 | 1.880 | 0.041 | WORST
Path 2 | SystemBuilder_0/CORERESETP_0/sdif1_areset_n_rcosc_q2:CLK | SystemBuilder_0/CORERESETP_0/release_sdif1_core:ALn | 1.333 | 18.265 | 6.362 | 24.627 | 0.353 | 1.735 | 0.049 | WORST
Path 3 | SystemBuilder_0/CORERESETP_0/sdif3_areset_n_rcosc_q2:CLK | SystemBuilder_0/CORERESETP_0/release_sdif3_core:ALn | 1.162 | 18.417 | 6.202 | 24.619 | 0.353 | 1.583 | 0.068 | WORST
Path 4 | SystemBuilder_0/CORERESETP_0/sdif0_areset_n_rcosc_q2:CLK | SystemBuilder_0/CORERESETP_0/release_sdif0_core:ALn | 1.166 | 18.454 | 6.207 | 24.661 | 0.353 | 1.546 | 0.027 | WORST
Path 5 | SystemBuilder_0/CORERESETP_0/sdif2_areset_n_rcosc_q2:CLK | SystemBuilder_0/CORERESETP_0/release_sdif2_core:ALn | 0.773 | 18.813 | 5.814 | 24.627 | 0.353 | 1.187 | 0.061 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:CLK |  |  |  |  |  |  |  |
To: SystemBuilder_0/CORERESETP_0/ddr_settled:ALn |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 24.635 |  |
data arrival time |  |  |  | - |  | 6.515 |  |
slack |  |  |  |  |  | 18.120 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT |  |  |  |  | 0.000 | 0.000 |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 0.000 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SystemBuilder_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 2.027 | 2.027 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 2.179 | 1 | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SystemBuilder_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 1.583 | 3.762 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn | cell |  | ADLIB:GB | + | 0.220 | 3.982 | 2 | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn |  | + | 0.300 | 4.282 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell |  | ADLIB:RGB | + | 0.251 | 4.533 | 13 | r
SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:CLK | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 |  | + | 0.496 | 5.029 |  | r
SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:Q | cell |  | ADLIB:SLE | + | 0.087 | 5.116 | 1 | r
SystemBuilder_0/CORERESETP_0/ddr_settled:ALn | net | SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc |  | + | 1.399 | 6.515 |  | r
data arrival time |  |  |  |  |  | 6.515 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint |  |  |  | 20.000 | 20.000 |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 20.000 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SystemBuilder_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 2.027 | 22.027 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 22.179 | 1 | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SystemBuilder_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 1.583 | 23.762 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn | cell |  | ADLIB:GB | + | 0.220 | 23.982 | 2 | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn |  | + | 0.300 | 24.282 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell |  | ADLIB:RGB | + | 0.251 | 24.533 | 13 | r
SystemBuilder_0/CORERESETP_0/ddr_settled:CLK | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 |  | + | 0.455 | 24.988 |  | r
SystemBuilder_0/CORERESETP_0/ddr_settled:ALn | Library recovery time |  | ADLIB:SLE | - | 0.353 | 24.635 |  |
data required time |  |  |  |  |  | 24.635 |  |
Operating Conditions | WORST

### SET External Recovery

No Path

### SET Asynchronous to Register

No Path

### SET SystemBuilder_0/CCC_0/GL0 to SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:ALn | 3.004 | 17.507 | 7.154 | 24.661 |  | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:CLK |  |  |  |  |  |  |  |
To: SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:ALn |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 24.661 |  |
data arrival time |  |  |  | - |  | 7.154 |  |
slack |  |  |  |  |  | 17.507 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
SystemBuilder_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 2.784 | 2.784 |  |
SystemBuilder_0/CCC_0/GL0_INST:An | net | SystemBuilder_0/CCC_0/GL0_net |  | + | 0.197 | 2.981 |  | r
SystemBuilder_0/CCC_0/GL0_INST:YNn | cell |  | ADLIB:GB | + | 0.165 | 3.146 | 4 | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An | net | SystemBuilder_0/CCC_0/GL0_INST/U0_YNn |  | + | 0.272 | 3.418 |  | f
SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR | cell |  | ADLIB:RGB | + | 0.250 | 3.668 | 13 | r
SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | net | SystemBuilder_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1 |  | + | 0.482 | 4.150 |  | r
SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY_int:Q | cell |  | ADLIB:SLE | + | 0.087 | 4.237 | 1 | r
SystemBuilder_0/CORERESETP_0/sdif0_areset_n:A | net | SystemBuilder_0/CORERESETP_0/MSS_HPMS_READY |  | + | 0.311 | 4.548 |  | r
SystemBuilder_0/CORERESETP_0/sdif0_areset_n:Y | cell |  | ADLIB:CFG2 | + | 0.074 | 4.622 | 1 | r
SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567:An | net | SystemBuilder_0/CORERESETP_0/sm0_areset_n |  | + | 1.256 | 5.878 |  | f
SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567:YNn | cell |  | ADLIB:GB | + | 0.220 | 6.098 | 1 | f
SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567/U0_RGB1:An | net | SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567/U0_YNn |  | + | 0.281 | 6.379 |  | f
SystemBuilder_0/CORERESETP_0/sdif0_areset_n_RNI8567/U0_RGB1:YL | cell |  | ADLIB:RGB | + | 0.251 | 6.630 | 10 | r
SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:ALn | net | SystemBuilder_0/CORERESETP_0/sm0_areset_n_arst |  | + | 0.524 | 7.154 |  | r
data arrival time |  |  |  |  |  | 7.154 |  |
Data required time calculation |  |  |  |  |  |  |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint |  |  |  | 20.000 | 20.000 |  |
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 20.000 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SystemBuilder_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 2.027 | 22.027 |  | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 22.179 | 1 | r
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SystemBuilder_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 1.583 | 23.762 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YNn | cell |  | ADLIB:GB | + | 0.220 | 23.982 | 2 | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YNn |  | + | 0.300 | 24.282 |  | f
SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell |  | ADLIB:RGB | + | 0.251 | 24.533 | 13 | r
SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:CLK | net | SystemBuilder_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 |  | + | 0.481 | 25.014 |  | r
SystemBuilder_0/CORERESETP_0/sm0_areset_n_rcosc_q2:ALn | Library recovery time |  | ADLIB:SLE | - | 0.353 | 24.661 |  |
data required time |  |  |  |  |  | 24.661 |  |
Operating Conditions | WORST

## Path Set Pin to Pin

### SET Input to Output

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | ---
Path 1 | DIP3_On_0_K21 | DIP3_output | 6.747 |  | 6.747 |  | WORST
Path 2 | DIP4_On_0_K20 | DIP4_output | 6.252 |  | 6.252 |  | WORST
Path 3 | DIP2_On_1_L18 | DIP2_output | 6.140 |  | 6.140 |  | WORST
Path 4 | DIP1_On_1_L19 | DIP1_output | 6.108 |  | 6.108 |  | WORST
Path 5 | Wake_On_Change_SW4_J18 | SW4_Output | 6.045 |  | 6.045 |  | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: DIP3_On_0_K21 |  |  |  |  |  |  |  |
To: DIP3_output |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | N/C |  |
data arrival time |  |  |  | - |  | 6.747 |  |
slack |  |  |  |  |  | N/C |  |
Data arrival time calculation |  |  |  |  |  |  |  |
DIP3_On_0_K21 |  |  |  |  | 0.000 | 0.000 |  | f
DIP3_On_0_K21_ibuf/U0/U_IOPAD:PAD | net | DIP3_On_0_K21 |  | + | 0.000 | 0.000 |  | f
DIP3_On_0_K21_ibuf/U0/U_IOPAD:Y | cell |  | ADLIB:IOPAD_IN | + | 1.400 | 1.400 | 1 | f
DIP3_On_0_K21_ibuf/U0/U_IOINFF:A | net | DIP3_On_0_K21_ibuf/U0/YIN1 |  | + | 0.392 | 1.792 |  | f
DIP3_On_0_K21_ibuf/U0/U_IOINFF:Y | cell |  | ADLIB:IOINFF_BYPASS | + | 0.159 | 1.951 | 1 | f
DIP3_output_obuf/U0/U_IOOUTFF:A | net | DIP3_On_0_K21_c |  | + | 2.482 | 4.433 |  | f
DIP3_output_obuf/U0/U_IOOUTFF:Y | cell |  | ADLIB:IOOUTFF_BYPASS | + | 0.330 | 4.763 | 1 | f
DIP3_output_obuf/U0/U_IOPAD:D | net | DIP3_output_obuf/U0/DOUT |  | + | 0.074 | 4.837 |  | f
DIP3_output_obuf/U0/U_IOPAD:PAD | cell |  | ADLIB:IOPAD_TRI | + | 1.910 | 6.747 | 0 | f
DIP3_output | net | DIP3_output |  | + | 0.000 | 6.747 |  | f
data arrival time |  |  |  |  |  | 6.747 |  |
Data required time calculation |  |  |  |  |  |  |  |
DIP3_On_0_K21 |  |  |  |  | N/C | N/C |  | f
DIP3_output |  |  |  |  |  | N/C |  | f
data required time |  |  |  |  |  | N/C |  |
Operating Conditions | WORST

## Path Set User Sets