///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: <Name>
//
// File: counter_delay.v
// File history:
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//
// Description: 
//
// <Description here>
//
// Targeted device: <Family::IGLOO2> <Die::M2GL050> <Package::896 FBGA>
// Author: <Name>
//
/////////////////////////////////////////////////////////////////////////////////////////////////// 

//`timescale <time_units> / <precision>

module counter_delay( clk, clr, en, q, count_done );
input clk, clr, en;
    //output [3:0] q;
    output [9:0] q;
    output count_done;

    reg [9:0] q_int;
    reg count_done_int;

always @(posedge clk or negedge clr)

begin
  if(!clr) 
    begin
        count_done_int <= 0;
        q_int <= 10'b0;
    end
    else if(en)
        begin
            if(q_int == 10'b1111111111) begin
                count_done_int <= 1'b1;
                q_int <= q_int;
        end
    else 
        begin
            q_int <= q_int + 1'b1;
            count_done_int <= 1'b0;
        end
    end
 end

    assign q = q_int;
    assign count_done = count_done_int;

endmodule

