//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Thu Mar 25 16:15:32 2021
// Version: v12.6 12.900.20.24
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// top
module top(
    // Inputs
    DEVRST_N,
    DIP1_On_1_L19,
    DIP2_On_1_L18,
    DIP3_On_0_K21,
    DIP4_On_0_K20,
    Wake_On_Change_SW4_J18,
    ff_trig_SW2_K16,
    raddr_user,
    rclk_user,
    rd_enable_user,
    waddr_user,
    wclk_user,
    wdata_user,
    wr_enable_user,
    // Outputs
    DIP1_output,
    DIP2_output,
    DIP3_output,
    DIP4_output,
    FF_DONE,
    LED_1,
    LED_2,
    LED_3,
    LED_4,
    MCCC_MPLL_LOCK,
    RESP_err,
    SEL,
    SERV_BUSY,
    SW4_Output,
    Y,
    ahb_busy,
    ram_init_done,
    rdata_user
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input        DEVRST_N;
input        DIP1_On_1_L19;
input        DIP2_On_1_L18;
input        DIP3_On_0_K21;
input        DIP4_On_0_K20;
input        Wake_On_Change_SW4_J18;
input        ff_trig_SW2_K16;
input  [5:0] raddr_user;
input        rclk_user;
input        rd_enable_user;
input  [5:0] waddr_user;
input        wclk_user;
input  [7:0] wdata_user;
input        wr_enable_user;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output       DIP1_output;
output       DIP2_output;
output       DIP3_output;
output       DIP4_output;
output       FF_DONE;
output       LED_1;
output       LED_2;
output       LED_3;
output       LED_4;
output       MCCC_MPLL_LOCK;
output [1:0] RESP_err;
output       SEL;
output       SERV_BUSY;
output       SW4_Output;
output       Y;
output       ahb_busy;
output       ram_init_done;
output [7:0] rdata_user;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire           ahb_busy_net_0;
wire   [31:0]  AHBMASTER_FIC_RAM_0_BIF_1_HADDR;
wire   [2:0]   AHBMASTER_FIC_RAM_0_BIF_1_HBURST;
wire   [3:0]   AHBMASTER_FIC_RAM_0_BIF_1_HPROT;
wire   [31:0]  AHBMASTER_FIC_RAM_0_BIF_1_HRDATA;
wire           AHBMASTER_FIC_RAM_0_BIF_1_HREADY;
wire   [1:0]   AHBMASTER_FIC_RAM_0_BIF_1_HRESP;
wire   [2:0]   AHBMASTER_FIC_RAM_0_BIF_1_HSIZE;
wire   [1:0]   AHBMASTER_FIC_RAM_0_BIF_1_HTRANS;
wire   [31:0]  AHBMASTER_FIC_RAM_0_BIF_1_HWDATA;
wire           AHBMASTER_FIC_RAM_0_BIF_1_HWRITE;
wire   [31:0]  CORESYSSERVICES_0_AHBL_MASTER_HADDR;
wire   [2:0]   CORESYSSERVICES_0_AHBL_MASTER_HBURST;
wire   [31:0]  CORESYSSERVICES_0_AHBL_MASTER_HRDATA;
wire           CORESYSSERVICES_0_AHBL_MASTER_HREADY;
wire   [2:0]   CORESYSSERVICES_0_AHBL_MASTER_HSIZE;
wire   [1:0]   CORESYSSERVICES_0_AHBL_MASTER_HTRANS;
wire   [31:0]  CORESYSSERVICES_0_AHBL_MASTER_HWDATA;
wire           CORESYSSERVICES_0_AHBL_MASTER_HWRITE;
wire           DEVRST_N;
wire           DIP1_On_1_L19;
wire           DIP2_On_1_L18;
wire           DIP3_On_0_K21;
wire           DIP4_On_0_K20;
wire   [7:0]   FF_BLKS_0_serv_cmdbyte_req;
wire           FF_BLKS_0_serv_enable_req;
wire           FF_DONE_net_0;
wire           ff_trig_SW2_K16;
wire   [23:23] LED_1_net_0;
wire   [24:24] LED_2_net_0;
wire   [25:25] LED_3_net_0;
wire   [26:26] LED_4_net_0;
wire           MCCC_MPLL_LOCK_net_0;
wire   [5:0]   raddr_user;
wire           ram_init_done_net_0;
wire           rclk_user;
wire           rd_enable_user;
wire   [7:0]   rdata_user_net_0;
wire   [1:0]   RESP_err_net_0;
wire           SEL_net_0;
wire           SERV_BUSY_net_0;
wire   [31:0]  SystemBuilder_0_AMBA_SLAVE_0_SRAM_HADDR;
wire   [2:0]   SystemBuilder_0_AMBA_SLAVE_0_SRAM_HBURST;
wire           SystemBuilder_0_AMBA_SLAVE_0_SRAM_HMASTLOCK;
wire   [3:0]   SystemBuilder_0_AMBA_SLAVE_0_SRAM_HPROT;
wire   [31:0]  SystemBuilder_0_AMBA_SLAVE_0_SRAM_HRDATA;
wire           SystemBuilder_0_AMBA_SLAVE_0_SRAM_HREADY;
wire           SystemBuilder_0_AMBA_SLAVE_0_SRAM_HREADYOUT;
wire   [1:0]   SystemBuilder_0_AMBA_SLAVE_0_SRAM_HRESP;
wire           SystemBuilder_0_AMBA_SLAVE_0_SRAM_HSELx;
wire   [2:0]   SystemBuilder_0_AMBA_SLAVE_0_SRAM_HSIZE;
wire   [1:0]   SystemBuilder_0_AMBA_SLAVE_0_SRAM_HTRANS;
wire   [31:0]  SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWDATA;
wire           SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWRITE;
wire           SystemBuilder_0_COMM_BLK_INT;
wire           SystemBuilder_0_FIC_0_CLK;
wire           SystemBuilder_0_INIT_DONE;
wire           SystemBuilder_0_MCCC_GLMUX_SEL;
wire           SystemBuilder_0_RCOSC_25_50MHZ_O2F;
wire   [5:0]   waddr_user;
wire           Wake_On_Change_SW4_J18;
wire           wclk_user;
wire   [7:0]   wdata_user;
wire           wr_enable_user;
wire           Y_net_0;
wire           SERV_BUSY_net_1;
wire           LED_2_net_1;
wire           LED_3_net_1;
wire           LED_1_net_1;
wire           LED_4_net_1;
wire           ram_init_done_net_1;
wire           SEL_net_1;
wire           ahb_busy_net_1;
wire           DIP2_On_1_L18_net_0;
wire           DIP3_output_net_0;
wire           Wake_On_Change_SW4_J18_net_0;
wire           DIP1_On_1_L19_net_0;
wire           DIP4_On_0_K20_net_0;
wire           FF_DONE_net_1;
wire           Y_net_1;
wire           MCCC_MPLL_LOCK_net_1;
wire   [1:0]   RESP_err_net_1;
wire   [7:0]   rdata_user_net_1;
wire   [0:22]  CNT_slice_0;
wire   [27:33] CNT_slice_1;
wire   [33:0]  CNT_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   [5:0]   SERV_OPTIONS_MODE_const_net_0;
wire           GND_net;
wire   [31:0]  SERV_DATA_W_const_net_0;
wire           VCC_net;
wire   [255:0] SERV_CRYPTO_KEY_const_net_0;
wire   [127:0] SERV_CRYPTO_IV_const_net_0;
wire   [7:0]   SERV_CRYPTO_MODE_const_net_0;
wire   [15:0]  SERV_CRYPTO_NBLOCKS_const_net_0;
wire   [31:0]  SERV_CRYPTO_LENGTH_const_net_0;
wire   [7:0]   SERV_NRBG_LENGTH_const_net_0;
wire   [7:0]   SERV_NRBG_HANDLE_const_net_0;
wire   [7:0]   SERV_NRBG_ADDLENGTH_const_net_0;
wire   [7:0]   SERV_NRBG_PRREQ_const_net_0;
wire   [255:0] SERV_DPA_KEY_const_net_0;
wire   [7:0]   SERV_DPA_OPTYPE_const_net_0;
wire   [127:0] SERV_DPA_PATH_const_net_0;
wire   [7:0]   SERV_PUF_SUBCMD_const_net_0;
wire   [7:0]   SERV_PUF_INKEYNUM_const_net_0;
wire   [7:0]   SERV_PUF_KEYSIZE_const_net_0;
wire   [31:0]  SERV_PUFUSERKEYADDR_const_net_0;
wire   [31:0]  SERV_USEREXTRINSICKEYADDR_const_net_0;
wire   [31:0]  SERV_SPIADDR_const_net_0;
wire   [3:0]   HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0_const_net_0;
//--------------------------------------------------------------------
// Inverted Nets
//--------------------------------------------------------------------
wire           en_IN_POST_INV0_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [0:0]   CORESYSSERVICES_0_AHBL_MASTER_HRESP_0_0to0;
wire           CORESYSSERVICES_0_AHBL_MASTER_HRESP_0;
wire   [1:0]   CORESYSSERVICES_0_AHBL_MASTER_HRESP;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign SERV_OPTIONS_MODE_const_net_0                       = 6'h00;
assign GND_net                                             = 1'b0;
assign SERV_DATA_W_const_net_0                             = 32'h00000000;
assign VCC_net                                             = 1'b1;
assign SERV_CRYPTO_KEY_const_net_0                         = 256'h0000000000000000000000000000000000000000000000000000000000000000;
assign SERV_CRYPTO_IV_const_net_0                          = 128'h00000000000000000000000000000000;
assign SERV_CRYPTO_MODE_const_net_0                        = 8'h00;
assign SERV_CRYPTO_NBLOCKS_const_net_0                     = 16'h0000;
assign SERV_CRYPTO_LENGTH_const_net_0                      = 32'h00000000;
assign SERV_NRBG_LENGTH_const_net_0                        = 8'h00;
assign SERV_NRBG_HANDLE_const_net_0                        = 8'h00;
assign SERV_NRBG_ADDLENGTH_const_net_0                     = 8'h00;
assign SERV_NRBG_PRREQ_const_net_0                         = 8'h00;
assign SERV_DPA_KEY_const_net_0                            = 256'h0000000000000000000000000000000000000000000000000000000000000000;
assign SERV_DPA_OPTYPE_const_net_0                         = 8'h00;
assign SERV_DPA_PATH_const_net_0                           = 128'h00000000000000000000000000000000;
assign SERV_PUF_SUBCMD_const_net_0                         = 8'h00;
assign SERV_PUF_INKEYNUM_const_net_0                       = 8'h00;
assign SERV_PUF_KEYSIZE_const_net_0                        = 8'h00;
assign SERV_PUFUSERKEYADDR_const_net_0                     = 32'h00000000;
assign SERV_USEREXTRINSICKEYADDR_const_net_0               = 32'h00000000;
assign SERV_SPIADDR_const_net_0                            = 32'h00000000;
assign HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0_const_net_0 = 4'h0;
//--------------------------------------------------------------------
// Inversions
//--------------------------------------------------------------------
assign en_IN_POST_INV0_0 = ~ SystemBuilder_0_MCCC_GLMUX_SEL;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign SERV_BUSY_net_1              = SERV_BUSY_net_0;
assign SERV_BUSY                    = SERV_BUSY_net_1;
assign LED_2_net_1                  = LED_2_net_0[24];
assign LED_2                        = LED_2_net_1;
assign LED_3_net_1                  = LED_3_net_0[25];
assign LED_3                        = LED_3_net_1;
assign LED_1_net_1                  = LED_1_net_0[23];
assign LED_1                        = LED_1_net_1;
assign LED_4_net_1                  = LED_4_net_0[26];
assign LED_4                        = LED_4_net_1;
assign ram_init_done_net_1          = ram_init_done_net_0;
assign ram_init_done                = ram_init_done_net_1;
assign SEL_net_1                    = SEL_net_0;
assign SEL                          = SEL_net_1;
assign ahb_busy_net_1               = ahb_busy_net_0;
assign ahb_busy                     = ahb_busy_net_1;
assign DIP2_On_1_L18_net_0          = DIP2_On_1_L18;
assign DIP2_output                  = DIP2_On_1_L18_net_0;
assign DIP3_output_net_0            = DIP3_On_0_K21;
assign DIP3_output                  = DIP3_output_net_0;
assign Wake_On_Change_SW4_J18_net_0 = Wake_On_Change_SW4_J18;
assign SW4_Output                   = Wake_On_Change_SW4_J18_net_0;
assign DIP1_On_1_L19_net_0          = DIP1_On_1_L19;
assign DIP1_output                  = DIP1_On_1_L19_net_0;
assign DIP4_On_0_K20_net_0          = DIP4_On_0_K20;
assign DIP4_output                  = DIP4_On_0_K20_net_0;
assign FF_DONE_net_1                = FF_DONE_net_0;
assign FF_DONE                      = FF_DONE_net_1;
assign Y_net_1                      = Y_net_0;
assign Y                            = Y_net_1;
assign MCCC_MPLL_LOCK_net_1         = MCCC_MPLL_LOCK_net_0;
assign MCCC_MPLL_LOCK               = MCCC_MPLL_LOCK_net_1;
assign RESP_err_net_1               = RESP_err_net_0;
assign RESP_err[1:0]                = RESP_err_net_1;
assign rdata_user_net_1             = rdata_user_net_0;
assign rdata_user[7:0]              = rdata_user_net_1;
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign LED_1_net_0[23] = CNT_net_0[23:23];
assign LED_2_net_0[24] = CNT_net_0[24:24];
assign LED_3_net_0[25] = CNT_net_0[25:25];
assign LED_4_net_0[26] = CNT_net_0[26:26];
assign CNT_slice_0     = { CNT_net_0[0] , CNT_net_0[1] , CNT_net_0[2] , CNT_net_0[3] , CNT_net_0[4] , CNT_net_0[5] , CNT_net_0[6] , CNT_net_0[7] , CNT_net_0[8] , CNT_net_0[9] , CNT_net_0[10] , CNT_net_0[11] , CNT_net_0[12] , CNT_net_0[13] , CNT_net_0[14] , CNT_net_0[15] , CNT_net_0[16] , CNT_net_0[17] , CNT_net_0[18] , CNT_net_0[19] , CNT_net_0[20] , CNT_net_0[21] , CNT_net_0[22] };
assign CNT_slice_1     = { CNT_net_0[27] , CNT_net_0[28] , CNT_net_0[29] , CNT_net_0[30] , CNT_net_0[31] , CNT_net_0[32] , CNT_net_0[33] };
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign CORESYSSERVICES_0_AHBL_MASTER_HRESP_0_0to0 = CORESYSSERVICES_0_AHBL_MASTER_HRESP[0:0];
assign CORESYSSERVICES_0_AHBL_MASTER_HRESP_0 = { CORESYSSERVICES_0_AHBL_MASTER_HRESP_0_0to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------AHBMASTER_FIC_RAM
AHBMASTER_FIC_RAM AHBMASTER_FIC_RAM_0(
        // Inputs
        .HREADY         ( AHBMASTER_FIC_RAM_0_BIF_1_HREADY ),
        .HWRITE_0       ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWRITE ),
        .HSEL           ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HSELx ),
        .HREADY_0       ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HREADY ),
        .START          ( SystemBuilder_0_INIT_DONE ),
        .HRESETn        ( SystemBuilder_0_INIT_DONE ),
        .HCLK           ( SystemBuilder_0_FIC_0_CLK ),
        .rd_enable_user ( rd_enable_user ),
        .wr_enable_user ( wr_enable_user ),
        .rclk_user      ( rclk_user ),
        .wclk_user      ( wclk_user ),
        .HRDATA         ( AHBMASTER_FIC_RAM_0_BIF_1_HRDATA ),
        .HRESP          ( AHBMASTER_FIC_RAM_0_BIF_1_HRESP ),
        .HADDR_0        ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HADDR ),
        .HTRANS_0       ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HTRANS ),
        .HWDATA_0       ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWDATA ),
        .raddr_user     ( raddr_user ),
        .waddr_user     ( waddr_user ),
        .wdata_user     ( wdata_user ),
        // Outputs
        .HWRITE         ( AHBMASTER_FIC_RAM_0_BIF_1_HWRITE ),
        .HREADYOUT      ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HREADYOUT ),
        .ram_init_done  ( ram_init_done_net_0 ),
        .ahb_busy       ( ahb_busy_net_0 ),
        .SEL            ( SEL_net_0 ),
        .HADDR          ( AHBMASTER_FIC_RAM_0_BIF_1_HADDR ),
        .HTRANS         ( AHBMASTER_FIC_RAM_0_BIF_1_HTRANS ),
        .HSIZE          ( AHBMASTER_FIC_RAM_0_BIF_1_HSIZE ),
        .HBURST         ( AHBMASTER_FIC_RAM_0_BIF_1_HBURST ),
        .HPROT          ( AHBMASTER_FIC_RAM_0_BIF_1_HPROT ),
        .HWDATA         ( AHBMASTER_FIC_RAM_0_BIF_1_HWDATA ),
        .HRDATA_0       ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HRDATA ),
        .HRESP_0        ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HRESP ),
        .RESP_err       ( RESP_err_net_0 ),
        .rdata_user     ( rdata_user_net_0 ) 
        );

//--------counter_delay
counter_delay CLK_Sync_CNTR_Dly_0(
        // Inputs
        .clk        ( SystemBuilder_0_RCOSC_25_50MHZ_O2F ),
        .clr        ( MCCC_MPLL_LOCK_net_0 ),
        .en         ( en_IN_POST_INV0_0 ),
        // Outputs
        .q          (  ),
        .count_done ( Y_net_0 ) 
        );

//--------cnt34
cnt34 cnt34_0(
        // Inputs
        .RSTN ( SystemBuilder_0_INIT_DONE ),
        .CLK  ( SystemBuilder_0_FIC_0_CLK ),
        // Outputs
        .CNT  ( CNT_net_0 ) 
        );

//--------top_CORESYSSERVICES_0_CORESYSSERVICES   -   Actel:DirectCore:CORESYSSERVICES:3.2.102
top_CORESYSSERVICES_0_CORESYSSERVICES #( 
        .CHRESPKEYADDR        ( 'h20000000 ),
        .CHRESPPTR            ( 'h20000000 ),
        .CHRESPSERVICE        ( 0 ),
        .CRYPTOAES128DATAPTR  ( 'h20000000 ),
        .CRYPTOAES128SERVICE  ( 0 ),
        .CRYPTOAES256DATAPTR  ( 'h20000000 ),
        .CRYPTOAES256SERVICE  ( 0 ),
        .CRYPTODATAINPPTR     ( 'h20000000 ),
        .CRYPTODSTADPTR       ( 'h20000000 ),
        .CRYPTOHMACDATAPTR    ( 'h20000000 ),
        .CRYPTOHMACSERVICE    ( 0 ),
        .CRYPTORSLTPTR        ( 'h20000000 ),
        .CRYPTOSHA256DATAPTR  ( 'h20000000 ),
        .CRYPTOSHA256SERVICE  ( 0 ),
        .CRYPTOSRCADPTR       ( 'h20000000 ),
        .DCSERVICE            ( 0 ),
        .DESIGNVERPTR         ( 'h20000000 ),
        .DEVICECERTPTR        ( 'h20000000 ),
        .DSNPTR               ( 'h20000000 ),
        .ECCPADDDESC          ( 'h20000000 ),
        .ECCPADDPPTR          ( 'h20000000 ),
        .ECCPADDQPTR          ( 'h20000000 ),
        .ECCPADDRPTR          ( 'h20000000 ),
        .ECCPMULTDESC         ( 'h20000000 ),
        .ECCPMULTDPTR         ( 'h20000000 ),
        .ECCPMULTPPTR         ( 'h20000000 ),
        .ECCPMULTQPTR         ( 'h20000000 ),
        .ECCPOINTADDSERVICE   ( 0 ),
        .ECCPOINTMULTSERVICE  ( 0 ),
        .FFSERVICE            ( 1 ),
        .KEYTREEDATAPTR       ( 'h20000000 ),
        .KEYTREESERVICE       ( 0 ),
        .NRBGADDINPPTR        ( 'h20000000 ),
        .NRBGGENPTR           ( 'h20000000 ),
        .NRBGINSTPTR          ( 'h20000000 ),
        .NRBGPERSTRINGPTR     ( 'h20000000 ),
        .NRBGREQDATAPTR       ( 'h20000000 ),
        .NRBGRESEEDPTR        ( 'h20000000 ),
        .NRBGSERVICE          ( 0 ),
        .PORDSERVICE          ( 0 ),
        .PROGIAPSERVICE       ( 0 ),
        .PROGNVMDISERVICE     ( 0 ),
        .PUFPUBLICKEYADDR     ( 'h20000000 ),
        .PUFPUBLICKEYPTR      ( 'h20000000 ),
        .PUFSEEDADDR          ( 'h20000000 ),
        .PUFSEEDPTR           ( 'h20000000 ),
        .PUFSERVICE           ( 0 ),
        .PUFUSERACPTR         ( 'h20000000 ),
        .PUFUSERKCPTR         ( 'h20000000 ),
        .PUFUSERKEYPTR        ( 'h20000000 ),
        .SECDCSERVICE         ( 0 ),
        .SECONDECCCERTPTR     ( 'h20000000 ),
        .SNSERVICE            ( 0 ),
        .TAMPERCONTROLSERVICE ( 0 ),
        .TAMPERDETECTSERVICE  ( 0 ),
        .UCSERVICE            ( 0 ),
        .UDVSERVICE           ( 0 ),
        .USERCODEPTR          ( 'h20000000 ),
        .ZERSERVICE           ( 0 ) )
CORESYSSERVICES_0(
        // Inputs
        .CLK                       ( SystemBuilder_0_FIC_0_CLK ),
        .RESETN                    ( SystemBuilder_0_INIT_DONE ),
        .HCLK                      ( SystemBuilder_0_FIC_0_CLK ),
        .HRESETN                   ( SystemBuilder_0_INIT_DONE ),
        .HRESP                     ( CORESYSSERVICES_0_AHBL_MASTER_HRESP_0 ),
        .HREADY                    ( CORESYSSERVICES_0_AHBL_MASTER_HREADY ),
        .HRDATA                    ( CORESYSSERVICES_0_AHBL_MASTER_HRDATA ),
        .SERV_ENABLE_REQ           ( FF_BLKS_0_serv_enable_req ),
        .SERV_CMDBYTE_REQ          ( FF_BLKS_0_serv_cmdbyte_req ),
        .SERV_OPTIONS_MODE         ( SERV_OPTIONS_MODE_const_net_0 ),
        .SERV_DATA_WVALID          ( GND_net ),
        .SERV_DATA_W               ( SERV_DATA_W_const_net_0 ),
        .COMM_BLK_INT              ( SystemBuilder_0_COMM_BLK_INT ),
        .SERV_CRYPTO_KEY           ( SERV_CRYPTO_KEY_const_net_0 ), // tied to 256'h0000000000000000000000000000000000000000000000000000000000000000 from definition
        .SERV_CRYPTO_IV            ( SERV_CRYPTO_IV_const_net_0 ), // tied to 128'h00000000000000000000000000000000 from definition
        .SERV_CRYPTO_MODE          ( SERV_CRYPTO_MODE_const_net_0 ), // tied to 8'h00 from definition
        .SERV_CRYPTO_NBLOCKS       ( SERV_CRYPTO_NBLOCKS_const_net_0 ), // tied to 16'h0000 from definition
        .SERV_CRYPTO_LENGTH        ( SERV_CRYPTO_LENGTH_const_net_0 ), // tied to 32'h00000000 from definition
        .SERV_NRBG_LENGTH          ( SERV_NRBG_LENGTH_const_net_0 ), // tied to 8'h00 from definition
        .SERV_NRBG_HANDLE          ( SERV_NRBG_HANDLE_const_net_0 ), // tied to 8'h00 from definition
        .SERV_NRBG_ADDLENGTH       ( SERV_NRBG_ADDLENGTH_const_net_0 ), // tied to 8'h00 from definition
        .SERV_NRBG_PRREQ           ( SERV_NRBG_PRREQ_const_net_0 ), // tied to 8'h00 from definition
        .SERV_DPA_KEY              ( SERV_DPA_KEY_const_net_0 ), // tied to 256'h0000000000000000000000000000000000000000000000000000000000000000 from definition
        .SERV_DPA_OPTYPE           ( SERV_DPA_OPTYPE_const_net_0 ), // tied to 8'h00 from definition
        .SERV_DPA_PATH             ( SERV_DPA_PATH_const_net_0 ), // tied to 128'h00000000000000000000000000000000 from definition
        .SERV_PUF_SUBCMD           ( SERV_PUF_SUBCMD_const_net_0 ), // tied to 8'h00 from definition
        .SERV_PUF_INKEYNUM         ( SERV_PUF_INKEYNUM_const_net_0 ), // tied to 8'h00 from definition
        .SERV_PUF_KEYSIZE          ( SERV_PUF_KEYSIZE_const_net_0 ), // tied to 8'h00 from definition
        .SERV_PUFUSERKEYADDR       ( SERV_PUFUSERKEYADDR_const_net_0 ), // tied to 32'h00000000 from definition
        .SERV_USEREXTRINSICKEYADDR ( SERV_USEREXTRINSICKEYADDR_const_net_0 ), // tied to 32'h00000000 from definition
        .SERV_SPIADDR              ( SERV_SPIADDR_const_net_0 ), // tied to 32'h00000000 from definition
        // Outputs
        .HSEL                      (  ),
        .HADDR                     ( CORESYSSERVICES_0_AHBL_MASTER_HADDR ),
        .HWRITE                    ( CORESYSSERVICES_0_AHBL_MASTER_HWRITE ),
        .HWDATA                    ( CORESYSSERVICES_0_AHBL_MASTER_HWDATA ),
        .HTRANS                    ( CORESYSSERVICES_0_AHBL_MASTER_HTRANS ),
        .HBURST                    ( CORESYSSERVICES_0_AHBL_MASTER_HBURST ),
        .HSIZE                     ( CORESYSSERVICES_0_AHBL_MASTER_HSIZE ),
        .SERV_BUSY                 ( SERV_BUSY_net_0 ),
        .SERV_STATUS_VALID         (  ),
        .SERV_STATUS_RESP          (  ),
        .SERV_DATA_WRDY            (  ),
        .SERV_DATA_RVALID          (  ),
        .SERV_DATA_R               (  ),
        .SERV_CMD_ERROR            (  ),
        .SERV_TAMPER_MSGVALID      (  ),
        .SERV_TAMPER_MSG           (  ) 
        );

//--------FF_BLKS
FF_BLKS FF_BLKS_0(
        // Inputs
        .reset            ( SystemBuilder_0_INIT_DONE ),
        .ff_trig          ( ff_trig_SW2_K16 ),
        .serv_busy        ( SERV_BUSY_net_0 ),
        .clk              ( SystemBuilder_0_FIC_0_CLK ),
        // Outputs
        .serv_enable_req  ( FF_BLKS_0_serv_enable_req ),
        .FF_DONE          ( FF_DONE_net_0 ),
        .serv_cmdbyte_req ( FF_BLKS_0_serv_cmdbyte_req ) 
        );

//--------SystemBuilder
SystemBuilder SystemBuilder_0(
        // Inputs
        .FAB_RESET_N                                 ( VCC_net ),
        .DEVRST_N                                    ( DEVRST_N ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HWRITE_M0    ( CORESYSSERVICES_0_AHBL_MASTER_HWRITE ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HMASTLOCK_M0 ( GND_net ), // tied to 1'b0 from definition
        .HWRITE_M0_0                                 ( AHBMASTER_FIC_RAM_0_BIF_1_HWRITE ),
        .HMASTLOCK_M0_0                              ( GND_net ), // tied to 1'b0 from definition
        .AMBA_SLAVE_0_SRAM_HREADYOUT_S1              ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HREADYOUT ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HADDR_M0     ( CORESYSSERVICES_0_AHBL_MASTER_HADDR ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HTRANS_M0    ( CORESYSSERVICES_0_AHBL_MASTER_HTRANS ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HSIZE_M0     ( CORESYSSERVICES_0_AHBL_MASTER_HSIZE ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HBURST_M0    ( CORESYSSERVICES_0_AHBL_MASTER_HBURST ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0     ( HPMS_FIC_0_SYS_SERVICES_MASTER_HPROT_M0_const_net_0 ), // tied to 4'h0 from definition
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HWDATA_M0    ( CORESYSSERVICES_0_AHBL_MASTER_HWDATA ),
        .HADDR_M0_0                                  ( AHBMASTER_FIC_RAM_0_BIF_1_HADDR ),
        .HTRANS_M0_0                                 ( AHBMASTER_FIC_RAM_0_BIF_1_HTRANS ),
        .HSIZE_M0_0                                  ( AHBMASTER_FIC_RAM_0_BIF_1_HSIZE ),
        .HBURST_M0_0                                 ( AHBMASTER_FIC_RAM_0_BIF_1_HBURST ),
        .HPROT_M0_0                                  ( AHBMASTER_FIC_RAM_0_BIF_1_HPROT ),
        .HWDATA_M0_0                                 ( AHBMASTER_FIC_RAM_0_BIF_1_HWDATA ),
        .AMBA_SLAVE_0_SRAM_HRDATA_S1                 ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HRDATA ),
        .AMBA_SLAVE_0_SRAM_HRESP_S1                  ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HRESP ),
        // Outputs
        .POWER_ON_RESET_N                            (  ),
        .INIT_DONE                                   ( SystemBuilder_0_INIT_DONE ),
        .FIC_0_CLK                                   ( SystemBuilder_0_FIC_0_CLK ),
        .FIC_0_LOCK                                  (  ),
        .HPMS_READY                                  (  ),
        .COMM_BLK_INT                                ( SystemBuilder_0_COMM_BLK_INT ),
        .MCCC_MPLL_LOCK                              ( MCCC_MPLL_LOCK_net_0 ),
        .MCCC_GLMUX_SEL                              ( SystemBuilder_0_MCCC_GLMUX_SEL ),
        .RCOSC_25_50MHZ_O2F                          ( SystemBuilder_0_RCOSC_25_50MHZ_O2F ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HREADY_M0    ( CORESYSSERVICES_0_AHBL_MASTER_HREADY ),
        .HREADY_M0_0                                 ( AHBMASTER_FIC_RAM_0_BIF_1_HREADY ),
        .AMBA_SLAVE_0_SRAM_HWRITE_S1                 ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWRITE ),
        .AMBA_SLAVE_0_SRAM_HSEL_S1                   ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HSELx ),
        .AMBA_SLAVE_0_SRAM_HREADY_S1                 ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HREADY ),
        .AMBA_SLAVE_0_SRAM_HMASTLOCK_S1              ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HMASTLOCK ),
        .HPMS_INT_M2F                                (  ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HRDATA_M0    ( CORESYSSERVICES_0_AHBL_MASTER_HRDATA ),
        .HPMS_FIC_0_SYS_SERVICES_MASTER_HRESP_M0     ( CORESYSSERVICES_0_AHBL_MASTER_HRESP ),
        .HRDATA_M0_0                                 ( AHBMASTER_FIC_RAM_0_BIF_1_HRDATA ),
        .HRESP_M0_0                                  ( AHBMASTER_FIC_RAM_0_BIF_1_HRESP ),
        .AMBA_SLAVE_0_SRAM_HADDR_S1                  ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HADDR ),
        .AMBA_SLAVE_0_SRAM_HTRANS_S1                 ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HTRANS ),
        .AMBA_SLAVE_0_SRAM_HSIZE_S1                  ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HSIZE ),
        .AMBA_SLAVE_0_SRAM_HWDATA_S1                 ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HWDATA ),
        .AMBA_SLAVE_0_SRAM_HBURST_S1                 ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HBURST ),
        .AMBA_SLAVE_0_SRAM_HPROT_S1                  ( SystemBuilder_0_AMBA_SLAVE_0_SRAM_HPROT ) 
        );


endmodule
