#-- Synplicity, Inc.
#-- Version 9.0
#-- Project file E:\OLD_HD_BACKUP\01_Actel\10_Power_Sequencer\02_vhdl_prj\Actel1review\aug30_2008\power_sequencer\synthesis\run_options.txt
#-- Written on Sat Aug 30 18:09:22 2008


#add_file options
add_file -vhdl -lib work "E:/OLD_HD_BACKUP/01_Actel/10_Power_Sequencer/02_vhdl_prj/Actel1review/aug30_2008/power_sequencer/smartgen/pll_4_40/pll_4_40.vhd"
add_file -vhdl -lib work "E:/OLD_HD_BACKUP/01_Actel/10_Power_Sequencer/02_vhdl_prj/Actel1review/aug30_2008/power_sequencer/smartgen/FlashROM_cmp/FlashROM_cmp.vhd"
add_file -vhdl -lib work "E:/OLD_HD_BACKUP/01_Actel/10_Power_Sequencer/02_vhdl_prj/Actel1review/aug30_2008/power_sequencer/smartgen/addr_counter/addr_counter.vhd"
add_file -vhdl -lib work "E:/OLD_HD_BACKUP/01_Actel/10_Power_Sequencer/02_vhdl_prj/Actel1review/aug30_2008/power_sequencer/smartgen/data_counter/data_counter.vhd"
add_file -vhdl -lib work "E:/OLD_HD_BACKUP/01_Actel/10_Power_Sequencer/02_vhdl_prj/Actel1review/aug30_2008/power_sequencer/hdl/power_sequencer.vhd"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology IGLOO
set_option -part M1AGL600V2
set_option -speed_grade Std

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -top_module "work.power_sequencer"

#map options
set_option -frequency 100.000
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file "./power_sequencer.edn"
impl -active "synthesis"
