KEY LIBERO "10.1"
KEY CAPTURE "10.1.1.6"
KEY DEFAULT_IMPORT_LOC "X:\Projects\Interrupts_MSS_GPIO\Design\Verilog"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "0afd9c48-310a-4f45-b10a-4f45310a4f45"
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "SmartFusion"
KEY VendorTechnology_Die "IP4X3M1"
KEY VendorTechnology_Package "fg484"
KEY VendorTechnology_Speed "STD"
KEY VendorTechnology_DieVoltage "1.5"
KEY VendorTechnology_IO_DEFT_STD "LVTTL"
KEY VendorTechnology_OPCONR "COM"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "C:\SF_UART_SW_flow_DF\EVAL_KIT\SC_standalone\polled_uart\UART"
KEY ProjectDescription ""
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "UART_MSS::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
MSS_BFM_LIB
ENDLIST
LIST LIBRARY_MSS_BFM_LIB
ALIAS=..\component\Actel\SmartFusionMSS\MSS\2.5.106\mti\user_verilog\MSS_BFM_LIB
COMPILE_OPTION=REFRESH_AND_COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf,actgen_cxf"
STATE="utd"
TIME="1352919899"
SIZE="945"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v,hdl"
STATE="utd"
TIME="1348513917"
SIZE="11243"
PARENT="<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CCC\2.0.106\MSS_CCC.cxf,actgen_cxf"
STATE="utd"
TIME="1352919887"
SIZE="252"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CM3\1.0.200\MSS_CM3.cxf,actgen_cxf"
STATE="utd"
TIME="1352919887"
SIZE="252"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_COM\1.0.200\MSS_COM.cxf,actgen_cxf"
STATE="utd"
TIME="1352919887"
SIZE="252"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_DMA\1.0.101\MSS_DMA.cxf,actgen_cxf"
STATE="utd"
TIME="1352919887"
SIZE="252"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_ENVM\2.3.102\MSS_ENVM.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="253"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_FIO\1.0.203\MSS_FIO.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="252"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_GPIO\1.0.101\MSS_GPIO.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="253"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_INTR\1.0.101\MSS_INTR.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="253"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RESET\1.0.101\MSS_RESET.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="254"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RTC\1.0.100\MSS_RTC.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="252"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_TIMER\1.0.100\MSS_TIMER.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="254"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UART\1.0.101\MSS_UART.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="253"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UFROM\1.0.100\MSS_UFROM.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="254"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_WATCHDOG\1.0.101\MSS_WATCHDOG.cxf,actgen_cxf"
STATE="utd"
TIME="1352919889"
SIZE="257"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf"
STATE="utd"
TIME="1334613491"
SIZE="2712"
ENDFILE
VALUE "<project>\component\work\DESIGN_IO\DESIGN_IO.cxf,actgen_cxf"
STATE="utd"
TIME="1334613529"
SIZE="413"
ENDFILE
VALUE "<project>\component\work\UART\testbench.v,tb_hdl"
STATE="utd"
TIME="1352919809"
SIZE="1473"
PARENT="<project>\component\work\UART\UART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\UART\UART.cxf,actgen_cxf"
STATE="utd"
TIME="1352919809"
SIZE="2847"
ENDFILE
VALUE "<project>\component\work\UART\UART.pdc,pdc"
STATE="utd"
TIME="1352919808"
SIZE="7133"
PARENT="<project>\component\work\UART\UART.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideDESIGNER"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\UART\UART.v,hdl"
STATE="utd"
TIME="1352919809"
SIZE="1651"
PARENT="<project>\component\work\UART\UART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\UART_MSS\MSS_CCC_0\UART_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf,actgen_cxf"
STATE="utd"
TIME="1352919887"
SIZE="483"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\work\UART_MSS\MSS_CCC_0\UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v,hdl"
STATE="utd"
TIME="1352919887"
SIZE="2862"
PARENT="<project>\component\work\UART_MSS\MSS_CCC_0\UART_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\UART_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
STATE="utd"
TIME="1352919889"
SIZE="15503"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\UART_MSS\mss_tshell.v,hdl"
STATE="utd"
TIME="1352919890"
SIZE="12226"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\UART_MSS\testbench.v,tb_hdl"
STATE="utd"
TIME="1352919899"
SIZE="1485"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\UART_MSS\UART_MSS.cxf,actgen_cxf"
STATE="utd"
TIME="1352919902"
SIZE="9225"
ENDFILE
VALUE "<project>\component\work\UART_MSS\UART_MSS.pdc,pdc"
STATE="utd"
TIME="1352919882"
SIZE="1042"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideDESIGNER"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\UART_MSS\UART_MSS.v,hdl"
STATE="utd"
TIME="1352919901"
SIZE="16857"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\designer\impl1\UART.ide_des,ide_des"
STATE="utd"
TIME="1352919809"
SIZE="321"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS.adb,adb"
STATE="utd"
TIME="1352920002"
SIZE="244736"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS.fdb,fdb"
STATE="utd"
TIME="1352920001"
SIZE="42421"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS.ide_des,ide_des"
STATE="utd"
TIME="1352920002"
SIZE="1129"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS_compile_log.rpt,log"
STATE="utd"
TIME="1352919946"
SIZE="27101"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS_fp\projectData\UART_MSS.pdb,pdb"
STATE="utd"
TIME="1353591832"
SIZE="51200"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS_fp\UART_MSS.pdb,pdb"
STATE="utd"
TIME="1352920032"
SIZE="51200"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS_fp\UART_MSS.pro,pro"
STATE="utd"
TIME="1352920120"
SIZE="2056"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS_placeroute_log.rpt,log"
STATE="utd"
TIME="1352919974"
SIZE="2419"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS_prgdata_log.rpt,log"
STATE="utd"
TIME="1352920002"
SIZE="768"
ENDFILE
VALUE "<project>\designer\impl1\UART_MSS_verifytiming_log.rpt,log"
STATE="utd"
TIME="1352919982"
SIZE="1200"
ENDFILE
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
STATE="utd"
TIME="1348513894"
SIZE="41"
PARENT="<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1352919809"
SIZE="598"
PARENT="<project>\component\work\UART\UART.cxf"
ENDFILE
VALUE "<project>\simulation\test.bfm,sim"
STATE="utd"
TIME="1352919888"
SIZE="5460"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\simulation\user.bfm,sim"
STATE="utd"
TIME="1334613503"
SIZE="670"
PARENT="<project>\component\work\UART_MSS\UART_MSS.cxf"
ENDFILE
VALUE "<project>\synthesis\UART_MSS.edn,syn_edn"
STATE="utd"
TIME="1352919927"
SIZE="96758"
ENDFILE
VALUE "<project>\synthesis\UART_MSS.so,so"
STATE="utd"
TIME="1352919927"
SIZE="247"
ENDFILE
VALUE "<project>\synthesis\UART_MSS_sdc.sdc,sdc"
STATE="utd"
TIME="1352919927"
SIZE="310"
ENDFILE
VALUE "<project>\synthesis\UART_MSS_syn.prj,prj"
STATE="utd"
TIME="1352919929"
SIZE="1942"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "UART::work"
FILE "<project>\component\work\UART\UART.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\UART\testbench.v,tb_hdl"
VALUE "<project>\component\work\UART\UART.pdc,pdc"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\UART\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "UART_MSS::work"
FILE "<project>\component\work\UART_MSS\UART_MSS.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\UART_MSS\testbench.v,tb_hdl"
VALUE "<project>\component\work\UART_MSS\UART_MSS.pdc,pdc"
VALUE "<project>\component\work\UART_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\UART_MSS\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideDESIGNER(<project>\designer\impl1\UART_MSS.adb,adb)=StateSuccess
ideSYNTHESIS(<project>\synthesis\UART_MSS.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST UART
VALUE "<project>\component\work\UART\testbench.v,tb_hdl"
ENDLIST
LIST UART_MSS
VALUE "<project>\component\work\UART_MSS\testbench.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST UART
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\UART\testbench.v,tb_hdl"
VALUE "<project>\component\work\UART\UART.pdc,pdc"
ENDLIST
LIST UART_MSS
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\UART_MSS\testbench.v,tb_hdl"
VALUE "<project>\component\work\UART_MSS\UART_MSS.pdc,pdc"
VALUE "<project>\component\work\UART_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=TRUE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=fdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="C:\Microsemi\Libero_v10.1\SoftConsole\Eclipse\eclipse.exe"
PARAM=""
BATCH=0
EndProfile
NAME="Synplify Pro AE"
FUNCTION="Synthesis"
TOOL="Synplify Pro AE"
LOCATION="C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\bin\synplify_pro.exe"
PARAM=""
BATCH=0
EndProfile
NAME="ModelSim AE"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_v10.1\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="WFL"
FUNCTION="Stimulus"
TOOL="WFL"
LOCATION="syncad.exe"
PARAM="-p waveform"
BATCH=0
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_v10.1\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "UART::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "UART_MSS::work"
LIST Impl1
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideDESIGNER(<project>\designer\impl1\UART_MSS.adb,adb)=StateSuccess
ideSYNTHESIS(<project>\synthesis\UART_MSS.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
StartPage;StartPage
SmartDesign;UART_MSS
Reports;Reports
SmartDesign;UART
SmartDesign;DESIGN_FIRMWARE
ACTIVEVIEW;Reports
ENDLIST
LIST ModuleSubBlockList
LIST "BIBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "BIBUF_OPEND_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
SUBBLOCK "HAL::work","","FALSE","FALSE"
SUBBLOCK "MSS_GPIO_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_IAP_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_NVM_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_PDMA_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_RTC_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_Timer_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_UART_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_Watchdog_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion_CMSIS_PAL::work","","FALSE","FALSE"
ENDLIST
LIST "DESIGN_IO::work","component\work\DESIGN_IO\DESIGN_IO.cxf","TRUE","FALSE"
ENDLIST
LIST "HAL::work","","FALSE","FALSE"
ENDLIST
LIST "INBUF_LVDS_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_LVPECL_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_ALL::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_APB::work","component\work\UART_MSS\mss_tshell.v","FALSE","FALSE"
ENDLIST
LIST "MSS_CCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_GPIO_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_IAP_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_LPXTLOSC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_NVM_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_PDMA_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_RTC_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_UART_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_Watchdog_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_XTLOSC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSSINT::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "OUTBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "SmartFusion_CMSIS_PAL::work","","FALSE","FALSE"
ENDLIST
LIST "TRIBUFF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "UART::work","component\work\UART\UART.v","TRUE","FALSE"
SUBBLOCK "UART_MSS::work","component\work\UART_MSS\UART_MSS.v","TRUE","FALSE"
ENDLIST
LIST "UART_MSS::work","component\work\UART_MSS\UART_MSS.v","TRUE","FALSE"
SUBBLOCK "MSS_APB::work","component\work\UART_MSS\mss_tshell.v","FALSE","FALSE"
SUBBLOCK "UART_MSS_tmp_MSS_CCC_0_MSS_CCC::work","component\work\UART_MSS\MSS_CCC_0\UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v","FALSE","FALSE"
SUBBLOCK "INBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
SUBBLOCK "OUTBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "UART_MSS_tmp_MSS_CCC_0_MSS_CCC::work","component\work\UART_MSS\MSS_CCC_0\UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v","FALSE","FALSE"
SUBBLOCK "MSS_CCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "testbench::work","component\work\UART\testbench.v","FALSE","TRUE"
SUBBLOCK "UART::work","component\work\UART\UART.v","TRUE","FALSE"
ENDLIST
LIST "testbench::work","component\work\UART_MSS\testbench.v","FALSE","TRUE"
SUBBLOCK "UART_MSS::work","component\work\UART_MSS\UART_MSS.v","TRUE","FALSE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
LIST "UART_MSS::work"
ACTIVETESTBENCH "","","FALSE"
ENDLIST
ENDLIST
