#Build: Synplify Pro F-2011.09M, Build 005R, Sep 20 2011
#install: C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M
#OS: Windows 7 6.1
#Hostname: VW7-SHARMAT

$ Start of Compile
#Wed May 02 17:08:53 2012

Synopsys Verilog Compiler, version comp560rc, Build 042R, built Sep 19 2011
@N|Running in 32-bit mode
Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\smartfusion.v"
@I::"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\vlog\scemi_objects.v"
@I::"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\vlog\hypermods.v"
@I::"C:\SmartFusion_UART\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v"
@I::"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\mss_tshell.v"
@I::"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.v"
@I::"C:\SmartFusion_UART\component\work\SmartFusion_UART\SmartFusion_UART.v"
Verilog syntax check successful!
Selecting top level module SmartFusion_UART
@N: CG364 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\smartfusion.v":1868:7:1868:9|Synthesizing module VCC

@N: CG364 :"C:\SmartFusion_UART\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":23:7:23:15|Synthesizing module INBUF_MSS

@N: CG364 :"C:\SmartFusion_UART\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":37:7:37:16|Synthesizing module OUTBUF_MSS

@N: CG364 :"C:\SmartFusion_UART\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":151:7:151:13|Synthesizing module MSS_CCC

@N: CG364 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\smartfusion.v":2620:7:2620:11|Synthesizing module RCOSC

@N: CG364 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\smartfusion.v":1141:7:1141:9|Synthesizing module GND

@N: CG364 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":5:7:5:48|Synthesizing module SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC

@N: CG364 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\mss_tshell.v":1:7:1:13|Synthesizing module MSS_APB

@N: CG364 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.v":5:7:5:26|Synthesizing module SmartFusion_UART_MSS

@N: CG364 :"C:\SmartFusion_UART\component\work\SmartFusion_UART\SmartFusion_UART.v":5:7:5:22|Synthesizing module SmartFusion_UART

@W: CL168 :"C:\SmartFusion_UART\component\work\SmartFusion_UART\SmartFusion_UART.v":20:8:20:10|Pruning instance GND -- not in use ...

@W: CL168 :"C:\SmartFusion_UART\component\work\SmartFusion_UART\SmartFusion_UART.v":16:8:16:10|Pruning instance VCC -- not in use ...

@W: CL157 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":62:7:62:18|*Output RCOSC_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL157 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":63:7:63:20|*Output MAINXIN_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL157 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":64:7:64:18|*Output LPXIN_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":36:7:36:10|Input CLKA is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":37:7:37:14|Input CLKA_PAD is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":38:7:38:15|Input CLKA_PADP is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":39:7:39:15|Input CLKA_PADN is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":40:7:40:10|Input CLKB is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":41:7:41:14|Input CLKB_PAD is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":42:7:42:15|Input CLKB_PADP is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":43:7:43:15|Input CLKB_PADN is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":44:7:44:10|Input CLKC is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":45:7:45:14|Input CLKC_PAD is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":46:7:46:15|Input CLKC_PADP is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":47:7:47:15|Input CLKC_PADN is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":48:7:48:13|Input MAINXIN is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":49:7:49:11|Input LPXIN is unused
@W: CL159 :"C:\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":50:7:50:13|Input MAC_CLK is unused
@END
Premap Report (contents appended below)
@N:"C:\SmartFusion_UART\synthesis\synlog\SmartFusion_UART_premap.srr"
Synopsys Actel Technology Mapper, Version map201109rcp1, Build 024R, Built Sep 28 2011 11:20:53
Copyright (C) 1994-2011, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2011.09M

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB)


Finished Pre Mapping Phase. (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

@N: BN225 |Writing default property annotation file C:\SmartFusion_UART\synthesis\SmartFusion_UART.sap.
Pre Mapping successful!

At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 23MB peak: 57MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 02 17:08:56 2012

###########################################################]
Map & Optimize Report (contents appended below)
@N:"C:\SmartFusion_UART\synthesis\synlog\SmartFusion_UART_fpga_mapper.srr"
Synopsys Actel Technology Mapper, Version map201109rcp1, Build 024R, Built Sep 28 2011 11:20:53
Copyright (C) 1994-2011, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2011.09M

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)



Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

@W: MO111 :"c:\smartfusion_uart\component\work\smartfusion_uart_mss\mss_ccc_0\smartfusion_uart_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\smartfusion_uart\component\work\smartfusion_uart_mss\mss_ccc_0\smartfusion_uart_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\smartfusion_uart\component\work\smartfusion_uart_mss\mss_ccc_0\smartfusion_uart_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC) 

Available hyper_sources - for debug and ip models
	None Found

@W: MT462 :"c:\smartfusion_uart\component\work\smartfusion_uart_mss\mss_ccc_0\smartfusion_uart_mss_tmp_mss_ccc_0_mss_ccc.v":80:40:80:47|Net SmartFusion_UART_MSS_0.MSS_ADLIB_INST_FCLK appears to be an unidentified clock source. Assuming default frequency. 

Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)

Writing Analyst data base C:\SmartFusion_UART\synthesis\SmartFusion_UART.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)

Writing EDIF Netlist and constraint files
F-2011.09M

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)

@W: MT420 |Found inferred clock SmartFusion_UART_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SmartFusion_UART_MSS_0.MSS_ADLIB_INST_EMCCLK"



##### START OF TIMING REPORT #####[
# Timing Report written on Wed May 02 17:08:59 2012
#


Top view:               SmartFusion_UART
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: NA






Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found


##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA484_STD
Report for cell SmartFusion_UART.verilog
  Core Cell usage:
              cell count     area count*area
               GND     3      0.0        0.0
           MSS_CCC     1      0.0        0.0
             RCOSC     1      0.0        0.0
               VCC     3      0.0        0.0


           MSS_APB     1      0.0        0.0
                   -----          ----------
             TOTAL     9                 0.0


  IO Cell usage:
              cell count
         INBUF_MSS     2
        OUTBUF_MSS     1
                   -----
             TOTAL     3


Core Cells         : 0 of 4608 (0%)
IO Cells           : 3

  RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)

Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 23MB peak: 56MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Wed May 02 17:08:59 2012

###########################################################]
