KEY LIBERO "10.0"
KEY CAPTURE "10.0.10.4"
KEY DEFAULT_IMPORT_LOC "C:\Actel_M1A3P\Sample Design\LiberoProject\Example_M1A3P_UJTAG\coreconsole\Example_M1A3P_UJTAG"
KEY ProjectID "362f3746-737d-4be8-b37d-bbe8737dbbe8"
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "SmartFusion"
KEY VendorTechnology_Die "IP6X5M2"
KEY VendorTechnology_Package "fg484"
KEY VendorTechnology_Speed "-1"
KEY VendorTechnology_DieVoltage "1.5"
KEY VendorTechnology_IO_DEFT_STD "LVTTL"
KEY VendorTechnology_OPCONR "COM"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "C:\SmartFusion_UART"
KEY ProjectDescription ""
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "SmartFusion_UART::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
MSS_BFM_LIB
ENDLIST
LIST LIBRARY_MSS_BFM_LIB
ALIAS=..\component\Actel\SmartFusionMSS\MSS\2.5.106\mti\user_verilog\MSS_BFM_LIB
COMPILE_OPTION=REFRESH_AND_COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf,actgen_cxf"
STATE="utd"
TIME="1336021630"
SIZE="945"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v,hdl"
STATE="utd"
TIME="1333097126"
SIZE="11243"
PARENT="<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CCC\2.0.106\MSS_CCC.cxf,actgen_cxf"
STATE="utd"
TIME="1336021614"
SIZE="252"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CM3\1.0.200\MSS_CM3.cxf,actgen_cxf"
STATE="utd"
TIME="1336021614"
SIZE="252"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_COM\1.0.200\MSS_COM.cxf,actgen_cxf"
STATE="utd"
TIME="1336021614"
SIZE="252"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_DMA\1.0.101\MSS_DMA.cxf,actgen_cxf"
STATE="utd"
TIME="1336021615"
SIZE="252"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_ENVM\2.3.102\MSS_ENVM.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="253"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_FIO\1.0.203\MSS_FIO.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="252"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_GPIO\1.0.101\MSS_GPIO.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="253"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_INTR\1.0.101\MSS_INTR.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="253"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RESET\1.0.101\MSS_RESET.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="254"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RTC\1.0.100\MSS_RTC.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="252"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_TIMER\1.0.100\MSS_TIMER.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="254"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UART\1.0.101\MSS_UART.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="253"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UFROM\1.0.100\MSS_UFROM.cxf,actgen_cxf"
STATE="utd"
TIME="1336021618"
SIZE="254"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART\SmartFusion_UART.cxf,actgen_cxf"
STATE="utd"
TIME="1336021659"
SIZE="3008"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART\SmartFusion_UART.pdc,pdc"
STATE="utd"
TIME="1336021633"
SIZE="5755"
PARENT="<project>\component\work\SmartFusion_UART\SmartFusion_UART.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideDESIGNER"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART\SmartFusion_UART.v,hdl"
STATE="utd"
TIME="1336021635"
SIZE="472"
PARENT="<project>\component\work\SmartFusion_UART\SmartFusion_UART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART\testbench.v,tb_hdl"
STATE="utd"
TIME="1336021635"
SIZE="1509"
PARENT="<project>\component\work\SmartFusion_UART\SmartFusion_UART.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf,actgen_cxf"
STATE="utd"
TIME="1336021614"
SIZE="507"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v,hdl"
STATE="utd"
TIME="1336021614"
SIZE="2875"
PARENT="<project>\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
STATE="utd"
TIME="1336021618"
SIZE="15875"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART_MSS\mss_tshell.v,hdl"
STATE="utd"
TIME="1336021618"
SIZE="12226"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf,actgen_cxf"
STATE="utd"
TIME="1336021632"
SIZE="9055"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.pdc,pdc"
STATE="utd"
TIME="1336021608"
SIZE="663"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideDESIGNER"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.v,hdl"
STATE="utd"
TIME="1336021631"
SIZE="9304"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SmartFusion_UART_MSS\testbench.v,tb_hdl"
STATE="utd"
TIME="1336021631"
SIZE="1521"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART.adb,adb"
STATE="utd"
TIME="1336021718"
SIZE="257536"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART.fdb,fdb"
STATE="utd"
TIME="1336021811"
SIZE="76010"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART.ide_des,ide_des"
STATE="utd"
TIME="1336021469"
SIZE="187"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART_compile_log.rpt,log"
STATE="utd"
TIME="1336021718"
SIZE="29777"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART_fp\projectData\SmartFusion_UART.pdb,pdb"
STATE="utd"
TIME="1336022034"
SIZE="85504"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART_fp\SmartFusion_UART.pdb,pdb"
STATE="utd"
TIME="1336021861"
SIZE="85504"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART_fp\SmartFusion_UART.pro,pro"
STATE="utd"
TIME="1336022034"
SIZE="1986"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART_MSS.ide_des,ide_des"
STATE="utd"
TIME="1336021555"
SIZE="191"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART_placeroute_log.rpt,log"
STATE="utd"
TIME="1336021756"
SIZE="2399"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART_prgdata_log.rpt,log"
STATE="utd"
TIME="1336021812"
SIZE="624"
ENDFILE
VALUE "<project>\designer\impl1\SmartFusion_UART_verifytiming_log.rpt,log"
STATE="utd"
TIME="1336021770"
SIZE="1180"
ENDFILE
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
STATE="utd"
TIME="1333097104"
SIZE="41"
PARENT="<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1336021635"
SIZE="598"
PARENT="<project>\component\work\SmartFusion_UART\SmartFusion_UART.cxf"
ENDFILE
VALUE "<project>\simulation\test.bfm,sim"
STATE="utd"
TIME="1336021616"
SIZE="5460"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\simulation\user.bfm,sim"
STATE="utd"
TIME="1336021616"
SIZE="670"
PARENT="<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.cxf"
ENDFILE
VALUE "<project>\synthesis\SmartFusion_UART.edn,syn_edn"
STATE="utd"
TIME="1336021691"
SIZE="90328"
ENDFILE
VALUE "<project>\synthesis\SmartFusion_UART.so,so"
STATE="utd"
TIME="1336021691"
SIZE="221"
ENDFILE
VALUE "<project>\synthesis\SmartFusion_UART_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1336021691"
SIZE="310"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "SmartFusion_UART::work"
FILE "<project>\component\work\SmartFusion_UART\SmartFusion_UART.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\SmartFusion_UART\testbench.v,tb_hdl"
VALUE "<project>\component\work\SmartFusion_UART\SmartFusion_UART.pdc,pdc"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\SmartFusion_UART\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideDESIGNER(<project>\designer\impl1\SmartFusion_UART.adb,adb)=StateSuccess
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\SmartFusion_UART.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "SmartFusion_UART_MSS::work"
FILE "<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\SmartFusion_UART_MSS\testbench.v,tb_hdl"
VALUE "<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.pdc,pdc"
VALUE "<project>\component\work\SmartFusion_UART_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\SmartFusion_UART_MSS\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST SmartFusion_UART
VALUE "<project>\component\work\SmartFusion_UART\testbench.v,tb_hdl"
ENDLIST
LIST SmartFusion_UART_MSS
VALUE "<project>\component\work\SmartFusion_UART_MSS\testbench.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST SmartFusion_UART
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\SmartFusion_UART\testbench.v,tb_hdl"
VALUE "<project>\component\work\SmartFusion_UART\SmartFusion_UART.pdc,pdc"
ENDLIST
LIST SmartFusion_UART_MSS
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\SmartFusion_UART_MSS\testbench.v,tb_hdl"
VALUE "<project>\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.pdc,pdc"
VALUE "<project>\component\work\SmartFusion_UART_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=TRUE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=fdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="Soft console"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="C:\Microsemi\Libero_v10.0\SoftConsole\Eclipse\eclipse.exe"
PARAM=""
BATCH=0
EndProfile
NAME="Synplify"
FUNCTION="Synthesis"
TOOL="Synplify Pro AE"
LOCATION="C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\bin\synplify_pro.exe"
PARAM="-licensetype synplifypro_actel -batch -log synplify.log"
BATCH=1
EndProfile
NAME="Modelsim"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_v10.0\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="Flash pro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_v10.0\Designer\bin\flashpro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "SmartFusion_UART::work"
LIST Impl1
LiberoState=Post_Layout
ideDESIGNER(<project>\designer\impl1\SmartFusion_UART.adb,adb)=StateSuccess
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\SmartFusion_UART.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "SmartFusion_UART_MSS::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
StartPage;StartPage
SmartDesign;SmartFusion_UART
SmartDesign;SmartFusion_UART_MSS
Reports;Reports
ACTIVEVIEW;Reports
ENDLIST
