Actel Designer Software
Version: 10.1.1.6
Release: v10.1 SP1

Info: The design SmartFusion_UART.adb was last modified by software version 10.1.1.6.
Opened an existing Libero design SmartFusion_UART.adb.
'BA_NAME' set to 'SmartFusion_UART_ba'
'IDE_DESIGNERVIEW_NAME' set to 'Impl1'
'IDE_DESIGNERVIEW_COUNT' set to '1'
'IDE_DESIGNERVIEW_REV0' set to 'Impl1'
'IDE_DESIGNERVIEW_REVNUM0' set to '1'
'IDE_DESIGNERVIEW_ROOTDIR' set to
'C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\designer'
'IDE_DESIGNERVIEW_LASTREV' set to '1'
***** Layout Variables *********************************************

Mode: TIMING_DRIVEN
Power-driven Layout: OFF
Incremental Placement: OFF
Incremental Route: OFF


Info: I/O Bank Assigner detected (1) out of (6) I/O Bank(s) with locked I/O technologies.

Running I/O Bank Assigner.

I/O Bank Assigner completed successfully.
 

Planning global net placement...


Global net placement completed successfully.


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Timing-driven Placer Started: Mon Nov 19 14:11:23 2012



Placer Finished: Mon Nov 19 14:11:26 2012

Total Placer CPU Time:     00:00:03



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Timing-driven Router 

Design: SmartFusion_UART                Started: Mon Nov 19 14:11:29 2012



 



Timing-driven Router completed successfully.



Design: SmartFusion_UART                

Finished: Mon Nov 19 14:11:40 2012

Total CPU Time:     00:00:11            Total Elapsed Time: 00:00:11

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Loading the Timing data for the design.
Finished loading the Timing data.
TIMER: Max delay timing requirements have been met.
TIMER: Min delay timing requirements have been met.

The Layout command succeeded ( 00:00:22 )
Wrote status report to file: SmartFusion_UART_place_and_route_report.txt

The Report command succeeded ( 00:00:00 )
Wrote globalnet report to file: SmartFusion_UART_globalnet_report.txt

The Report command succeeded ( 00:00:00 )
Wrote globalusage report to file: SmartFusion_UART_globalusage_report.txt

The Report command succeeded ( 00:00:00 )
Wrote iobank report to file: SmartFusion_UART_iobank_report.txt

The Report command succeeded ( 00:00:00 )
Design saved to file
C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\designer\impl1\SmartFusion_UART.\
adb.

The Execute Script command succeeded ( 00:00:27 )
Design closed.

