#--  Synopsys, Inc.
#--  Version F-2012.03M-SP1 
#--  Project file C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SF_UART\synthesis\run_options.txt
#--  Written on Mon Nov 19 14:01:22 2012


#project files
add_file -verilog "C:/SF_UART_LiberoSC_DF/DEV_KIT/UART_Libero_SC/SF_UART/component/Actel/SmartFusionMSS/MSS/2.5.106/mss_comps.v"
add_file -verilog "C:/SF_UART_LiberoSC_DF/DEV_KIT/UART_Libero_SC/SF_UART/component/work/SF_UART_MSS/MSS_CCC_0/SF_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v"
add_file -verilog "C:/SF_UART_LiberoSC_DF/DEV_KIT/UART_Libero_SC/SF_UART/component/work/SF_UART_MSS/mss_tshell.v"
add_file -verilog "C:/SF_UART_LiberoSC_DF/DEV_KIT/UART_Libero_SC/SF_UART/component/work/SF_UART_MSS/SF_UART_MSS.v"
add_file -verilog "C:/SF_UART_LiberoSC_DF/DEV_KIT/UART_Libero_SC/SF_UART/component/work/SF_UART/SF_UART.v"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion
set_option -part A2F500M3G
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "SF_UART"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./SF_UART.edn"
impl -active "synthesis"
