#Build: Synplify Pro F-2012.03M-SP1 , Build 084R, Jun 15 2012
#install: C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1
#OS: Windows 7 6.1
#Hostname: VW7-ONTEDDHUS

#Implementation: synthesis

$ Start of Compile
#Mon Nov 19 14:10:39 2012

Synopsys Verilog Compiler, version comp201203rcp1, Build 084R, built Jun 15 2012
@N|Running in 32-bit mode
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v"
@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\vlog\umr_capim.v"
@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\vlog\scemi_objects.v"
@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\vlog\scemi_pipes.svh"
@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\vlog\hypermods.v"
@I::"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\mss_tshell.v"
@I::"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v"
@I::"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.v"
@I::"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART\SmartFusion_UART.v"
Verilog syntax check successful!
Selecting top level module SmartFusion_UART
@N: CG364 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\mss_tshell.v":1:7:1:13|Synthesizing module MSS_APB

@N: CG364 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":151:7:151:13|Synthesizing module MSS_CCC

@N: CG364 :"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v":2620:7:2620:11|Synthesizing module RCOSC

@N: CG364 :"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v":1141:7:1141:9|Synthesizing module GND

@N: CG364 :"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v":1868:7:1868:9|Synthesizing module VCC

@N: CG364 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":5:7:5:48|Synthesizing module SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC

@N: CG364 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":23:7:23:15|Synthesizing module INBUF_MSS

@N: CG364 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":37:7:37:16|Synthesizing module OUTBUF_MSS

@N: CG364 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\SmartFusion_UART_MSS.v":9:7:9:26|Synthesizing module SmartFusion_UART_MSS

@N: CG364 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART\SmartFusion_UART.v":9:7:9:22|Synthesizing module SmartFusion_UART

@W: CL157 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":62:7:62:18|*Output RCOSC_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL157 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":63:7:63:20|*Output MAINXIN_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL157 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":64:7:64:18|*Output LPXIN_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":36:7:36:10|Input CLKA is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":37:7:37:14|Input CLKA_PAD is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":38:7:38:15|Input CLKA_PADP is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":39:7:39:15|Input CLKA_PADN is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":40:7:40:10|Input CLKB is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":41:7:41:14|Input CLKB_PAD is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":42:7:42:15|Input CLKB_PADP is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":43:7:43:15|Input CLKB_PADN is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":44:7:44:10|Input CLKC is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":45:7:45:14|Input CLKC_PAD is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":46:7:46:15|Input CLKC_PADP is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":47:7:47:15|Input CLKC_PADN is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":48:7:48:13|Input MAINXIN is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":49:7:49:11|Input LPXIN is unused
@W: CL159 :"C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\component\work\SmartFusion_UART_MSS\MSS_CCC_0\SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC.v":50:7:50:13|Input MAC_CLK is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 19 14:10:40 2012

###########################################################]
Premap Report

Synopsys Actel Technology Pre-mapping, Version mapact, Build 729R, Built Jun 20 2012 09:20:46
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP1 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@L: C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\synthesis\SmartFusion_UART_scck.rpt 
Printing clock  summary report in "C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\synthesis\SmartFusion_UART_scck.rpt" file 
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB)



Clock Summary
**************

Start      Requested     Requested     Clock      Clock          
Clock      Frequency     Period        Type       Group          
-----------------------------------------------------------------
System     1.0 MHz       1000.000      system     system_clkgroup
=================================================================


Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

@N: BN225 |Writing default property annotation file C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\synthesis\SmartFusion_UART.sap.
Pre-mapping successful!

At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 57MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 19 14:10:42 2012

###########################################################]
Map & Optimize Report

Synopsys Actel Technology Mapper, Version mapact, Build 729R, Built Jun 20 2012 09:20:46
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP1 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)



Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

@W: MO111 :"c:\sf_uart_liberosc_df\dev_kit\uart_libero_sc\smartfusion_uart\component\work\smartfusion_uart_mss\mss_ccc_0\smartfusion_uart_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\sf_uart_liberosc_df\dev_kit\uart_libero_sc\smartfusion_uart\component\work\smartfusion_uart_mss\mss_ccc_0\smartfusion_uart_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\sf_uart_liberosc_df\dev_kit\uart_libero_sc\smartfusion_uart\component\work\smartfusion_uart_mss\mss_ccc_0\smartfusion_uart_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SmartFusion_UART_MSS_tmp_MSS_CCC_0_MSS_CCC) 

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

Writing Analyst data base C:\SF_UART_LiberoSC_DF\DEV_KIT\UART_Libero_SC\SmartFusion_UART\synthesis\SmartFusion_UART.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

Writing EDIF Netlist and constraint files
F-2012.03M-SP1 

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)



##### START OF TIMING REPORT #####[
# Timing Report written on Mon Nov 19 14:10:43 2012
#


Top view:               SmartFusion_UART
Library name:           smartfusion
Operating conditions:   COMWC-1 ( T = 70.0, V = 1.42, P = 1.48, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 5.038

                   Requested     Estimated     Requested     Estimated               Clock      Clock          
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
---------------------------------------------------------------------------------------------------------------
System             100.0 MHz     201.5 MHz     10.000        4.962         5.038     system     system_clkgroup
===============================================================================================================





Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
System    System  |  10.000      5.038  |  No paths    -      |  No paths    -      |  No paths    -    
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                             Starting                                                       Arrival          
Instance                                     Reference     Type        Pin        Net                       Time        Slack
                                             Clock                                                                           
-----------------------------------------------------------------------------------------------------------------------------
SmartFusion_UART_MSS_0.MSS_CCC_0.I_RCOSC     System        RCOSC       CLKOUT     N_CLKA_RCOSC              0.000       5.038
SmartFusion_UART_MSS_0.MSS_ADLIB_INST        System        MSS_APB     EMCCLK     MSS_ADLIB_INST_EMCCLK     0.000       9.726
=============================================================================================================================


Ending Points with Worst Slack
******************************

                                          Starting                                                           Required          
Instance                                  Reference     Type        Pin           Net                        Time         Slack
                                          Clock                                                                                
-------------------------------------------------------------------------------------------------------------------------------
SmartFusion_UART_MSS_0.MSS_ADLIB_INST     System        MSS_APB     PLLLOCK       MSS_ADLIB_INST_PLLLOCK     10.000       5.038
SmartFusion_UART_MSS_0.MSS_ADLIB_INST     System        MSS_APB     FCLK          MSS_ADLIB_INST_FCLK        10.000       5.312
SmartFusion_UART_MSS_0.MSS_ADLIB_INST     System        MSS_APB     EMCCLKRTN     MSS_ADLIB_INST_EMCCLK      10.000       9.726
===============================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      4.962
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     5.038

    Number of logic level(s):                1
    Starting point:                          SmartFusion_UART_MSS_0.MSS_CCC_0.I_RCOSC / CLKOUT
    Ending point:                            SmartFusion_UART_MSS_0.MSS_ADLIB_INST / PLLLOCK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                            Pin         Pin               Arrival     No. of    
Name                                          Type        Name        Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
SmartFusion_UART_MSS_0.MSS_CCC_0.I_RCOSC      RCOSC       CLKOUT      Out     0.000     0.000       -         
N_CLKA_RCOSC                                  Net         -           -       0.274     -           1         
SmartFusion_UART_MSS_0.MSS_CCC_0.I_MSSCCC     MSS_CCC     CLKA        In      -         0.274       -         
SmartFusion_UART_MSS_0.MSS_CCC_0.I_MSSCCC     MSS_CCC     LOCKMSS     Out     4.415     4.688       -         
MSS_ADLIB_INST_PLLLOCK                        Net         -           -       0.274     -           1         
SmartFusion_UART_MSS_0.MSS_ADLIB_INST         MSS_APB     PLLLOCK     In      -         4.962       -         
==============================================================================================================
Total path delay (propagation time + setup) of 4.962 is 4.415(89.0%) logic and 0.547(11.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F500M3G_FBGA484_-1
Report for cell SmartFusion_UART.verilog
  Core Cell usage:
              cell count     area count*area
               GND     3      0.0        0.0
           MSS_APB     1      0.0        0.0
           MSS_CCC     1      0.0        0.0
             RCOSC     1      0.0        0.0
               VCC     3      0.0        0.0


                   -----          ----------
             TOTAL     9                 0.0


  IO Cell usage:
              cell count
         INBUF_MSS     2
        OUTBUF_MSS     1
                   -----
             TOTAL     3


Core Cells         : 0 of 11520 (0%)
IO Cells           : 3

  RAM/ROM Usage Summary
Block Rams : 0 of 24 (0%)

Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 57MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 19 14:10:43 2012

###########################################################]
