I_MSSCCC
I_RCOSC
MSS_ACE_0_TM0
MSS_ACE_0_VAREF0
MSS_ADLIB_INST
MSS_CCC_0
MSS_GPIO_0_GPIO_28_OUT
MSS_GPIO_0_GPIO_29_OUT
MSS_GPIO_0_GPIO_30_OUT
MSS_GPIO_0_GPIO_31_OUT
MSS_RESET_0_MSS_RESET_N
MSS_UART_0_RXD
MSS_UART_0_TXD
sign
zero
mul
genblk
begin
Bus
Bit
Core
LUT
cout
inter
push
pop
decode
encode
write
read
cache
shift
store
ADD
AND
MUX
BUF
BIN
BIT
COUNT
BYTE
CLK
SEL
CNT
FF
DSP
LUT
DLY
TRI
CNT
XOR
OR
NOT
div
add
and
mux
buf
bin
bit
count
byte
clk
sel
cnt
ff
dsp
dly
tri
cnt
xor
off
not
hex
HEX
sub
tran
state
mac
load
pass
next
log
inst
start
ibuf
obuf
DEC
DDR
OFF
OUT
FIR
memClk
cry
pipe
ret
U0
U1
U2
U3
U4
U5
core
reg
lock
co
di
enc
dec
pri
comp
Dly
clr
CLR
rst
RST
pre
PRE
ena
ENA
mult
MULT
rx
RX
tx
TX
lut
LUT
dsp
DSP
ram
RAM
so
mi
Bi
dir
in
out
get
put
gen
fft
fifo
ext
gate
net
Tri
end
cap
mod
pri
at
isbi
bu
to
at
ba
se
en
de
ar
fa
co
ca
vi
th
wa
tr
st
co
CO
ER
HE
CA
SH
TH
DE
EC
TR
OS
LO
LI
DR
RE
CL
GO
AA
NO
IN
or
BL
DF
FDa
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
0
1
2
3
4
5
6
7
8
