<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>C:\SF_LiberoSC_POT_DF\DEV_KIT\POT_LED_Libero_SC\Voltage_Monitor\synthesis\synlog\Voltage_Monitor_fpga_mapper.srr</data>
<title>##### START OF TIMING REPORT #####[</title>
</report_link>
<row>
<data>Clock Name</data>
<data>Req Freq</data>
<data>Est Freq</data>
<data>Slack</data>
</row>
<row>
<data>System</data>
<data>100.0 MHz</data>
<data>171.5 MHz</data>
<data>4.169</data>
</row>
</report_table>
