#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
#install: F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1
#OS:  6.1
#Hostname: W7-DONTHUS

#Implementation: synthesis

#Tue Nov 15 16:09:52 2011

$ Start of Compile
#Tue Nov 15 16:09:52 2011

Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
@N|Running in 32-bit mode
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@I::"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v"
@I::"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
@I::"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v"
@I::"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\mss_tshell.v"
@I::"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\Voltage_Monitor_MSS.v"
@I::"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor\Voltage_Monitor.v"
Verilog syntax check successful!
Selecting top level module Voltage_Monitor
@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":2609:7:2609:13|Synthesizing module INBUF_A

@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":1133:7:1133:9|Synthesizing module GND

@N: CG364 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":145:7:145:12|Synthesizing module MSSINT

@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":1814:7:1814:9|Synthesizing module VCC

@N: CG364 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\mss_tshell.v":1:7:1:13|Synthesizing module MSS_APB

@N: CG364 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":37:7:37:16|Synthesizing module OUTBUF_MSS

@N: CG364 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":23:7:23:15|Synthesizing module INBUF_MSS

@N: CG364 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":151:7:151:13|Synthesizing module MSS_CCC

@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":2566:7:2566:11|Synthesizing module RCOSC

@N: CG364 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":5:7:5:47|Synthesizing module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC

@N: CG364 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\Voltage_Monitor_MSS.v":5:7:5:25|Synthesizing module Voltage_Monitor_MSS

@N: CG364 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor\Voltage_Monitor.v":5:7:5:21|Synthesizing module Voltage_Monitor

@W: CL168 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor\Voltage_Monitor.v":34:8:34:10|Pruning instance GND - not in use ...

@W: CL168 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor\Voltage_Monitor.v":33:8:33:10|Pruning instance VCC - not in use ...

@W: CL157 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":62:7:62:18|*Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible 
@W: CL157 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":63:7:63:20|*Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W: CL157 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":64:7:64:18|*Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":36:7:36:10|Input CLKA is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":37:7:37:14|Input CLKA_PAD is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":38:7:38:15|Input CLKA_PADP is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":39:7:39:15|Input CLKA_PADN is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":40:7:40:10|Input CLKB is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":41:7:41:14|Input CLKB_PAD is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":42:7:42:15|Input CLKB_PADP is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":43:7:43:15|Input CLKB_PADN is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":44:7:44:10|Input CLKC is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":45:7:45:14|Input CLKC_PAD is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":46:7:46:15|Input CLKC_PADP is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":47:7:47:15|Input CLKC_PADN is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":48:7:48:13|Input MAINXIN is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":49:7:49:11|Input LPXIN is unused
@W: CL159 :"C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\component\work\Voltage_Monitor_MSS\MSS_CCC_0\Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC.v":50:7:50:13|Input MAC_CLK is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 15 16:09:52 2011

###########################################################]
Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version E-2010.09A-1
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 

@W: MO111 :"c:\microsemiprj\pot_led_libero_softconsole_old\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\microsemiprj\pot_led_libero_softconsole_old\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\microsemiprj\pot_led_libero_softconsole_old\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 

Available hyper_sources - for debug and ip models
	None Found

@W:"c:\microsemiprj\pot_led_libero_softconsole_old\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":80:40:80:47|Net Voltage_Monitor_MSS_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. 
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Writing Analyst data base C:\Microsemiprj\POT_LED_Libero_SoftConsole_old\Voltage_Monitor\synthesis\Voltage_Monitor.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

Writing EDIF Netlist and constraint files
E-2010.09A-1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

@W: MT246 :"c:\microsemiprj\pot_led_libero_softconsole_old\voltage_monitor\component\work\voltage_monitor_mss\voltage_monitor_mss.v":166:11:166:23|Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock Voltage_Monitor_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:Voltage_Monitor_MSS_0.MSS_ADLIB_INST_EMCCLK"

@W: MT420 |Found inferred clock Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:Voltage_Monitor_MSS_0.MSS_ADLIB_INST_FCLK"



##### START OF TIMING REPORT #####[
# Timing Report written on Tue Nov 15 16:09:54 2011
#


Top view:               Voltage_Monitor
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 5.547

                                                                                 Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                                                                   Frequency     Frequency     Period        Period        Slack     Type         Group              
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     100.0 MHz     224.5 MHz     10.000        4.453         5.547     inferred     Inferred_clkgroup_1
System                                                                           100.0 MHz     NA            10.000        NA            NA        system       system_clkgroup    
===================================================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                                      Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock  System  |  10.000      5.547  |  No paths    -      |  No paths    -      |  No paths    -    
============================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                                                                                                     Arrival          
Instance                                 Reference                                                                        Type        Pin         Net                 Time        Slack
                                         Clock                                                                                                                                         
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     MSS_APB     GPO[28]     MSSINT_GPO_28_A     4.132       5.547
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     MSS_APB     GPO[29]     MSSINT_GPO_29_A     4.132       5.547
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     MSS_APB     GPO[30]     MSSINT_GPO_30_A     4.132       5.547
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     MSS_APB     GPO[31]     MSSINT_GPO_31_A     4.132       5.547
=======================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                        Starting                                                                                                                Required          
Instance                                Reference                                                                        Type       Pin     Net                 Time         Slack
                                        Clock                                                                                                                                     
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Voltage_Monitor_MSS_0.MSSINT_GPO_28     Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     MSSINT     A       MSSINT_GPO_28_A     10.000       5.547
Voltage_Monitor_MSS_0.MSSINT_GPO_29     Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     MSSINT     A       MSSINT_GPO_29_A     10.000       5.547
Voltage_Monitor_MSS_0.MSSINT_GPO_30     Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     MSSINT     A       MSSINT_GPO_30_A     10.000       5.547
Voltage_Monitor_MSS_0.MSSINT_GPO_31     Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock     MSSINT     A       MSSINT_GPO_31_A     10.000       5.547
==================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      4.453
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     5.547

    Number of logic level(s):                0
    Starting point:                          Voltage_Monitor_MSS_0.MSS_ADLIB_INST / GPO[28]
    Ending point:                            Voltage_Monitor_MSS_0.MSSINT_GPO_28 / A
    The start point is clocked by            Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK
    The end   point is clocked by            System [rising]

Instance / Net                                       Pin         Pin               Arrival     No. of    
Name                                     Type        Name        Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     MSS_APB     GPO[28]     Out     4.132     4.132       -         
MSSINT_GPO_28_A                          Net         -           -       0.322     -           1         
Voltage_Monitor_MSS_0.MSSINT_GPO_28      MSSINT      A           In      -         4.453       -         
=========================================================================================================
Total path delay (propagation time + setup) of 4.453 is 4.132(92.8%) logic and 0.322(7.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA484_STD
Report for cell Voltage_Monitor.verilog
  Core Cell usage:
              cell count     area count*area
               GND     3      0.0        0.0
            MSSINT     4      0.0        0.0
           MSS_CCC     1      0.0        0.0
             RCOSC     1      0.0        0.0
               VCC     3      0.0        0.0


           MSS_APB     1      0.0        0.0
                   -----          ----------
             TOTAL    13                 0.0


  IO Cell usage:
              cell count
           INBUF_A     2
         INBUF_MSS     2
            OUTBUF     4
        OUTBUF_MSS     1
                   -----
             TOTAL     9


Core Cells         : 0 of 4608 (0%)
IO Cells           : 9

  RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)

Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 15 16:09:54 2011

###########################################################]
