Timing Report Max Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Mon Nov 12 12:10:54 2012


Design: Voltage_Monitor
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


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SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      9.236
Max Clock-To-Out (ns):      18.322

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Voltage_Monitor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
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Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

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SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_28
  Delay (ns):                  14.318
  Slack (ns):
  Arrival (ns):                18.322
  Required (ns):
  Clock to Out (ns):           18.322

Path 2
  From:                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_30
  Delay (ns):                  14.246
  Slack (ns):
  Arrival (ns):                18.250
  Required (ns):
  Clock to Out (ns):           18.250

Path 3
  From:                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_29
  Delay (ns):                  14.129
  Slack (ns):
  Arrival (ns):                18.133
  Required (ns):
  Clock to Out (ns):           18.133

Path 4
  From:                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_31
  Delay (ns):                  13.648
  Slack (ns):
  Arrival (ns):                17.652
  Required (ns):
  Clock to Out (ns):           17.652


Expanded Path 1
  From: Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_28
  data required time                             N/C
  data arrival time                          -   18.322
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  4.004
               +     4.095          cell: ADLIB:MSS_APB_IP
  8.099                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:GPO[28] (f)
               +     0.490          net: Voltage_Monitor_MSS_0/MSS_ADLIB_INST/GPO[28]INT_NET
  8.589                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_6:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  8.677                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_6:PIN1 (f)
               +     5.676          net: Voltage_Monitor_MSS_0/MSSINT_GPO_28_A
  14.353                       M2F_GPO_28_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  14.953                       M2F_GPO_28_pad/U0/U1:DOUT (f)
               +     0.000          net: M2F_GPO_28_pad/U0/NET1
  14.953                       M2F_GPO_28_pad/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  18.322                       M2F_GPO_28_pad/U0/U0:PAD (f)
               +     0.000          net: M2F_GPO_28
  18.322                       M2F_GPO_28 (f)
                                    
  18.322                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_28 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -5.206


Expanded Path 1
  From: MSS_RESET_N
  To: Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        Voltage_Monitor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        Voltage_Monitor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: Voltage_Monitor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          Voltage_Monitor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.459          net: Voltage_Monitor_MSS_0/MSS_ADLIB_INST_FCLK
  N/C                          Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          Voltage_Monitor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Voltage_Monitor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

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Path set User Sets

