@W: MO111 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MT462 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":80:40:80:47|Net Voltage_Monitor_MSS_0.MSS_ADLIB_INST_FCLK appears to be an unidentified clock source. Assuming default frequency. 
@W: MT420 |Found inferred clock Voltage_Monitor_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Voltage_Monitor_MSS_0.MSS_ADLIB_INST_EMCCLK"
