Synopsys Actel Technology Mapper, Version map201109rcp1, Build 024R, Built Sep 28 2011 11:20:53
Copyright (C) 1994-2011, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2011.09M

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)



Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)

@W: MO111 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar_old\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar_old\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar_old\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module Voltage_Monitor_MSS_tmp_MSS_CCC_0_MSS_CCC) 

Available hyper_sources - for debug and ip models
	None Found

@W: MT462 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar_old\voltage_monitor\component\work\voltage_monitor_mss\mss_ccc_0\voltage_monitor_mss_tmp_mss_ccc_0_mss_ccc.v":80:40:80:47|Net Voltage_Monitor_MSS_0.MSS_ADLIB_INST_FCLK appears to be an unidentified clock source. Assuming default frequency. 

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)


Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB)


Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)

Writing Analyst data base C:\SF_LiberoIAR_POTlevel_tutorial_DF\EVAL_KIT\POT_LED_Libero_IAR_old\Voltage_Monitor\synthesis\Voltage_Monitor.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)

Writing EDIF Netlist and constraint files
F-2011.09M

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB)

@W: MT246 :"c:\sf_liberoiar_potlevel_tutorial_df\eval_kit\pot_led_libero_iar_old\voltage_monitor\component\work\voltage_monitor_mss\voltage_monitor_mss.v":166:11:166:23|Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock Voltage_Monitor_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Voltage_Monitor_MSS_0.MSS_ADLIB_INST_EMCCLK"



##### START OF TIMING REPORT #####[
# Timing Report written on Mon Apr 23 19:46:48 2012
#


Top view:               Voltage_Monitor
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 5.547

                   Requested     Estimated     Requested     Estimated               Clock      Clock          
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
---------------------------------------------------------------------------------------------------------------
System             100.0 MHz     224.5 MHz     10.000        4.453         5.547     system     system_clkgroup
===============================================================================================================





Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
System    System  |  10.000      5.547  |  No paths    -      |  No paths    -      |  No paths    -    
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                                  Arrival          
Instance                                 Reference     Type        Pin         Net                 Time        Slack
                                         Clock                                                                      
--------------------------------------------------------------------------------------------------------------------
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     System        MSS_APB     GPO[28]     MSSINT_GPO_28_A     4.132       5.547
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     System        MSS_APB     GPO[29]     MSSINT_GPO_29_A     4.132       5.547
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     System        MSS_APB     GPO[30]     MSSINT_GPO_30_A     4.132       5.547
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     System        MSS_APB     GPO[31]     MSSINT_GPO_31_A     4.132       5.547
====================================================================================================================


Ending Points with Worst Slack
******************************

                                        Starting                                             Required          
Instance                                Reference     Type       Pin     Net                 Time         Slack
                                        Clock                                                                  
---------------------------------------------------------------------------------------------------------------
Voltage_Monitor_MSS_0.MSSINT_GPO_28     System        MSSINT     A       MSSINT_GPO_28_A     10.000       5.547
Voltage_Monitor_MSS_0.MSSINT_GPO_29     System        MSSINT     A       MSSINT_GPO_29_A     10.000       5.547
Voltage_Monitor_MSS_0.MSSINT_GPO_30     System        MSSINT     A       MSSINT_GPO_30_A     10.000       5.547
Voltage_Monitor_MSS_0.MSSINT_GPO_31     System        MSSINT     A       MSSINT_GPO_31_A     10.000       5.547
===============================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      4.453
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     5.547

    Number of logic level(s):                0
    Starting point:                          Voltage_Monitor_MSS_0.MSS_ADLIB_INST / GPO[28]
    Ending point:                            Voltage_Monitor_MSS_0.MSSINT_GPO_28 / A
    The start point is clocked by            System [rising] on pin FCLK
    The end   point is clocked by            System [rising]

Instance / Net                                       Pin         Pin               Arrival     No. of    
Name                                     Type        Name        Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
Voltage_Monitor_MSS_0.MSS_ADLIB_INST     MSS_APB     GPO[28]     Out     4.132     4.132       -         
MSSINT_GPO_28_A                          Net         -           -       0.322     -           1         
Voltage_Monitor_MSS_0.MSSINT_GPO_28      MSSINT      A           In      -         4.453       -         
=========================================================================================================
Total path delay (propagation time + setup) of 4.453 is 4.132(92.8%) logic and 0.322(7.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA484_STD
Report for cell Voltage_Monitor.verilog
  Core Cell usage:
              cell count     area count*area
               GND     3      0.0        0.0
            MSSINT     4      0.0        0.0
           MSS_CCC     1      0.0        0.0
             RCOSC     1      0.0        0.0
               VCC     3      0.0        0.0


           MSS_APB     1      0.0        0.0
                   -----          ----------
             TOTAL    13                 0.0


  IO Cell usage:
              cell count
           INBUF_A     2
         INBUF_MSS     2
            OUTBUF     4
        OUTBUF_MSS     1
                   -----
             TOTAL     9


Core Cells         : 0 of 4608 (0%)
IO Cells           : 9

  RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)

Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 23MB peak: 56MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Apr 23 19:46:49 2012

###########################################################]
