#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: WXP-AKKOOLH #Implementation: synthesis #Tue Nov 15 18:41:00 2011 $ Start of Compile #Tue Nov 15 18:41:00 2011 Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : Top_55TFT32bit_QVGA_EthMAC.vhd(18) | Top entity is set to Top_55TFT32bit_QVGA_EthMAC. VHDL syntax check successful! Options changed - recompiling @N:CD630 : Top_55TFT32bit_QVGA_EthMAC.vhd(18) | Synthesizing work.top_55tft32bit_qvga_ethmac.def_arch @N:CD630 : coreahbtoapb3.vhd(9) | Synthesizing coreahbtoapb3_lib.coreahbtoapb3.cahbtoapb3lol @N:CD630 : apbaddrdata.vhd(9) | Synthesizing coreahbtoapb3_lib.cahbtoapb3ioi.cahbtoapb3lol Post processing for coreahbtoapb3_lib.cahbtoapb3ioi.cahbtoapb3lol @N:CD630 : penablescheduler.vhd(9) | Synthesizing coreahbtoapb3_lib.cahbtoapb3oii.cahbtoapb3lol Post processing for coreahbtoapb3_lib.cahbtoapb3oii.cahbtoapb3lol @N:CD630 : ahbtoapbsm.vhd(9) | Synthesizing coreahbtoapb3_lib.cahbtoapb3o.cahbtoapb3lol @W:CD604 : ahbtoapbsm.vhd(275) | OTHERS clause is not synthesized Post processing for coreahbtoapb3_lib.cahbtoapb3o.cahbtoapb3lol Post processing for coreahbtoapb3_lib.coreahbtoapb3.cahbtoapb3lol @N:CD630 : coregpio.vhd(13) | Synthesizing coregpio_lib.coregpio.cgpioo @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(536) | Removed redundant assignment @N:CD364 : coregpio.vhd(556) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @W:CD434 : coregpio.vhd(909) | Signal paddr in the sensitivity list is not used in the process Post processing for coregpio_lib.coregpio.cgpioo @N:CD630 : CoreTFTahbMasterAdvQVGA.vhd(57) | Synthesizing work.coretftahbmaster.s_rtl @N:CD231 : CoreTFTahbMasterAdvQVGA.vhd(275) | Using onehot encoding for type sfahbm_state (st_idle="10000") @W:CD275 : CoreTFTahbMasterAdvQVGA.vhd(214) | Component declarations with different initial values are not supported. Port a of component clkint may have been given a different initial value in two different component declarations @N:CD364 : CoreTFTahbMasterAdvQVGA.vhd(721) | Removed redundant assignment @W:CD604 : CoreTFTahbMasterAdvQVGA.vhd(821) | OTHERS clause is not synthesized @W:CD638 : CoreTFTahbMasterAdvQVGA.vhd(370) | Signal i_fifo_full_ris is undriven @W:CD638 : CoreTFTahbMasterAdvQVGA.vhd(372) | Signal i_fifo_empty_ris is undriven @W:CD638 : CoreTFTahbMasterAdvQVGA.vhd(394) | Signal i_hw_n_reset is undriven @W:CD796 : CoreTFTahbMasterAdvQVGA.vhd(409) | Bit 16 of signal i_ram_rd_data_mux is undriven @W:CD796 : CoreTFTahbMasterAdvQVGA.vhd(409) | Bit 17 of signal i_ram_rd_data_mux is undriven @W:CD638 : CoreTFTahbMasterAdvQVGA.vhd(467) | Signal i_tftdata_start is undriven @W:CD638 : CoreTFTahbMasterAdvQVGA.vhd(477) | Signal i_tft_ctrl_en_ris is undriven @N:CD630 : sync_level.vhd(42) | Synthesizing work.sync_level.rtl Post processing for work.sync_level.rtl @N:CD630 : pulses2f_rf.vhd(37) | Synthesizing work.pulses2f_rf.rtl Post processing for work.pulses2f_rf.rtl @N:CD630 : smartfusion.vhd(412) | Synthesizing smartfusion.bufd.syn_black_box Post processing for smartfusion.bufd.syn_black_box @N:CD630 : top_timing_LUCA.vhd(9) | Synthesizing work.top_timing_luca.rtl @N:CD630 : vga7_timing_LUCA.vhd(7) | Synthesizing work.vga_timing_luca.rtl Post processing for work.vga_timing_luca.rtl Post processing for work.top_timing_luca.rtl @N:CD630 : fifo_512x16high.vhd(8) | Synthesizing work.fifo_512x16high.def_arch @N:CD630 : smartfusion.vhd(1945) | Synthesizing smartfusion.inv.syn_black_box Post processing for smartfusion.inv.syn_black_box @N:CD630 : smartfusion.vhd(3215) | Synthesizing smartfusion.fifo4k18.syn_black_box Post processing for smartfusion.fifo4k18.syn_black_box @N:CD630 : smartfusion.vhd(13) | Synthesizing smartfusion.and2.syn_black_box Post processing for smartfusion.and2.syn_black_box @N:CD630 : smartfusion.vhd(2043) | Synthesizing smartfusion.nand2.syn_black_box Post processing for smartfusion.nand2.syn_black_box @N:CD630 : smartfusion.vhd(2209) | Synthesizing smartfusion.or2.syn_black_box Post processing for smartfusion.or2.syn_black_box @N:CD630 : smartfusion.vhd(2051) | Synthesizing smartfusion.nand2a.syn_black_box Post processing for smartfusion.nand2a.syn_black_box @N:CD630 : smartfusion.vhd(1784) | Synthesizing smartfusion.gnd.syn_black_box Post processing for smartfusion.gnd.syn_black_box @N:CD630 : smartfusion.vhd(2742) | Synthesizing smartfusion.vcc.syn_black_box Post processing for smartfusion.vcc.syn_black_box Post processing for work.fifo_512x16high.def_arch @N:CD630 : smartfusion.vhd(2879) | Synthesizing smartfusion.clkint.syn_black_box Post processing for smartfusion.clkint.syn_black_box @N:CD630 : res_ctrl.vhd(37) | Synthesizing work.res_ctrl.rtl Post processing for work.res_ctrl.rtl Post processing for work.coretftahbmaster.s_rtl @W:CL240 : CoreTFTahbMasterAdvQVGA.vhd(89) | HWDATA is not assigned a value (floating) - a simulation mismatch is possible @W:CL169 : CoreTFTahbMasterAdvQVGA.vhd(953) | Pruning Register I_FIFO_WR_CNT(20 downto 0) @W:CL169 : CoreTFTahbMasterAdvQVGA.vhd(879) | Pruning Register MemDataIn(31 downto 0) @W:CL111 : CoreTFTahbMasterAdvQVGA.vhd(953) | All reachable assignments to I_RAM_WR_ADDR(0) assign '0', register removed by optimization @N:CD630 : MSS_new_top.vhd(8) | Synthesizing work.mss_new_top.def_arch @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch Post processing for work.outbuf_mss.def_arch @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch Post processing for work.inbuf_mss.def_arch @N:CD630 : mss_comps.vhd(65) | Synthesizing work.bibuf_mss.def_arch Post processing for work.bibuf_mss.def_arch @N:CD630 : mss_comps.vhd(168) | Synthesizing work.mssint.def_arch Post processing for work.mssint.def_arch @N:CD630 : smartfusion.vhd(1797) | Synthesizing smartfusion.inbuf_a.syn_black_box Post processing for smartfusion.inbuf_a.syn_black_box @N:CD630 : mss_comps.vhd(87) | Synthesizing work.bibuf_opend_mss.def_arch Post processing for work.bibuf_opend_mss.def_arch @N:CD630 : mss_comps.vhd(44) | Synthesizing work.tribuff_mss.def_arch Post processing for work.tribuff_mss.def_arch @N:CD630 : mss_tshell.vhd(4) | Synthesizing work.mss_ahb.def_arch Post processing for work.mss_ahb.def_arch @N:CD630 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.mss_new_top_tmp_mss_ccc_0_mss_ccc.def_arch @N:CD630 : mss_comps.vhd(432) | Synthesizing work.mss_xtlosc.def_arch Post processing for work.mss_xtlosc.def_arch @N:CD630 : mss_comps.vhd(472) | Synthesizing work.mss_ccc.def_arch Post processing for work.mss_ccc.def_arch Post processing for work.mss_new_top_tmp_mss_ccc_0_mss_ccc.def_arch @W:CL240 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible Post processing for work.mss_new_top.def_arch @N:CD630 : toggle_div.vhd(10) | Synthesizing work.toggle_div.structural Post processing for work.toggle_div.structural @N:CD630 : coreahblite.vhd(34) | Synthesizing coreahblite_lib.coreahblite.coreahblite_arch @N:CD630 : coreahblite_matrix2x16.vhd(34) | Synthesizing coreahblite_lib.coreahblite_matrix2x16.coreahblite_matrix2x16_arch @N:CD630 : coreahblite_initcfg.vhd(37) | Synthesizing coreahblite_lib.coreahblite_initcfg.coreahblite_initcfg_arch @N:CD630 : coreahblite_initcfg_awrap.vhd(36) | Synthesizing coreahblite_lib.coreahblite_initcfg_awrap.coreahblite_initcfg_awrap_arch Post processing for coreahblite_lib.coreahblite_initcfg_awrap.coreahblite_initcfg_awrap_arch @W:CL169 : coreahblite_initcfg_awrap.vhd(123) | Pruning Register HREADYOUT_int_s1 @N:CD630 : coreahblite_slavearbiter.vhd(31) | Synthesizing coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch @W:CD604 : coreahblite_slavearbiter.vhd(177) | OTHERS clause is not synthesized Post processing for coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch Post processing for coreahblite_lib.coreahblite_initcfg.coreahblite_initcfg_arch @N:CD630 : coreahblite_slavestage.vhd(33) | Synthesizing coreahblite_lib.coreahblite_slavestage.trans Post processing for coreahblite_lib.coreahblite_slavestage.trans @N:CD630 : coreahblite_masterstage.vhd(33) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_shg in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_shg in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal cldataready in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal clhresp in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_cl in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(821) | OTHERS clause is not synthesized @N:CD630 : coreahblite_defaultslavesm.vhd(31) | Synthesizing coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch @W:CD604 : coreahblite_defaultslavesm.vhd(65) | OTHERS clause is not synthesized Post processing for coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch @N:CD630 : coreahblite_addrdec.vhd(31) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(828) | Sharing sequential element addrRegSMCurrentState. @N:CD630 : coreahblite_masterstage.vhd(33) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal cldataready in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal clhresp in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_cl in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(821) | OTHERS clause is not synthesized @N:CD630 : coreahblite_addrdec.vhd(31) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(828) | Sharing sequential element addrRegSMCurrentState. Post processing for coreahblite_lib.coreahblite_matrix2x16.coreahblite_matrix2x16_arch Post processing for coreahblite_lib.coreahblite.coreahblite_arch @N:CD630 : coreapb3.vhd(14) | Synthesizing coreapb3_lib.coreapb3.capb3i0l @W:CD604 : coreapb3.vhd(439) | OTHERS clause is not synthesized @N:CD630 : coreapb3_muxptob3.vhd(14) | Synthesizing coreapb3_lib.capb3o.capb3ll @W:CD604 : coreapb3_muxptob3.vhd(152) | OTHERS clause is not synthesized @W:CD604 : coreapb3_muxptob3.vhd(195) | OTHERS clause is not synthesized @W:CD604 : coreapb3_muxptob3.vhd(238) | OTHERS clause is not synthesized Post processing for coreapb3_lib.capb3o.capb3ll Post processing for coreapb3_lib.coreapb3.capb3i0l Post processing for work.top_55tft32bit_qvga_ethmac.def_arch @W:CL246 : coreapb3.vhd(35) | Input port bits 23 to 12 of paddr(23 downto 0) are unused @W:CL159 : coreapb3.vhd(33) | Input presetn is unused @W:CL159 : coreapb3.vhd(34) | Input pclk is unused @W:CL246 : coreahblite_masterstage.vhd(52) | Input port bits 15 to 0 of sdataready(16 downto 0) are unused @W:CL246 : coreahblite_masterstage.vhd(53) | Input port bits 15 to 0 of shresp(16 downto 0) are unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input CLDATAREADY is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input CLHRESP is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(87) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(88) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(89) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(90) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(91) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(92) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(93) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(94) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(95) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(96) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(97) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(98) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(99) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(102) | Input HREADYOUT_CL is unused @W:CL246 : coreahblite_masterstage.vhd(52) | Input port bits 16 to 6 of sdataready(16 downto 0) are unused @W:CL246 : coreahblite_masterstage.vhd(52) | Input port bits 4 to 0 of sdataready(16 downto 0) are unused @W:CL246 : coreahblite_masterstage.vhd(53) | Input port bits 16 to 6 of shresp(16 downto 0) are unused @W:CL246 : coreahblite_masterstage.vhd(53) | Input port bits 4 to 0 of shresp(16 downto 0) are unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input CLDATAREADY is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input CLHRESP is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(87) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(88) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(89) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(90) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(91) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(92) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(93) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(94) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(95) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(96) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(97) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(98) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(99) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(100) | Input HRDATA_SHG is unused @W:CL159 : coreahblite_masterstage.vhd(101) | Input HREADYOUT_SHG is unused @W:CL159 : coreahblite_masterstage.vhd(102) | Input HREADYOUT_CL is unused @N:CL201 : coreahblite_slavearbiter.vhd(184) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 8 reachable states with original encodings of: 000 001 010 011 100 101 110 111 @W:CL246 : coreahblite_initcfg_awrap.vhd(43) | Input port bits 31 to 12 of haddr(31 downto 0) are unused @W:CL247 : coreahblite_initcfg_awrap.vhd(47) | Input port bit 0 of htrans(1 downto 0) is unused @W:CL159 : coreahblite_initcfg.vhd(47) | Input CLADDRSEL_M0 is unused @W:CL159 : coreahblite_initcfg.vhd(48) | Input CLADDRSEL_M1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(64) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix2x16.vhd(65) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix2x16.vhd(66) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix2x16.vhd(75) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(76) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(77) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(86) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix2x16.vhd(87) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix2x16.vhd(88) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix2x16.vhd(97) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix2x16.vhd(98) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix2x16.vhd(99) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix2x16.vhd(108) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix2x16.vhd(109) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix2x16.vhd(110) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix2x16.vhd(130) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix2x16.vhd(131) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix2x16.vhd(132) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix2x16.vhd(141) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix2x16.vhd(142) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix2x16.vhd(143) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix2x16.vhd(152) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix2x16.vhd(153) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix2x16.vhd(154) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix2x16.vhd(163) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix2x16.vhd(164) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix2x16.vhd(165) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix2x16.vhd(174) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix2x16.vhd(175) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix2x16.vhd(176) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix2x16.vhd(185) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix2x16.vhd(186) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix2x16.vhd(187) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix2x16.vhd(196) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix2x16.vhd(197) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix2x16.vhd(198) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix2x16.vhd(207) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix2x16.vhd(208) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix2x16.vhd(209) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix2x16.vhd(218) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix2x16.vhd(219) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix2x16.vhd(220) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix2x16.vhd(229) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix2x16.vhd(230) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix2x16.vhd(231) | Input HRESP_S15 is unused @W:CL247 : coreahblite.vhd(113) | Input port bit 0 of htrans_m0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(124) | Input port bit 0 of htrans_m1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(134) | Input port bit 1 of hresp_s0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(147) | Input port bit 1 of hresp_s1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(160) | Input port bit 1 of hresp_s2(1 downto 0) is unused @W:CL247 : coreahblite.vhd(173) | Input port bit 1 of hresp_s3(1 downto 0) is unused @W:CL247 : coreahblite.vhd(186) | Input port bit 1 of hresp_s4(1 downto 0) is unused @W:CL247 : coreahblite.vhd(199) | Input port bit 1 of hresp_s5(1 downto 0) is unused @W:CL247 : coreahblite.vhd(212) | Input port bit 1 of hresp_s6(1 downto 0) is unused @W:CL247 : coreahblite.vhd(225) | Input port bit 1 of hresp_s7(1 downto 0) is unused @W:CL247 : coreahblite.vhd(238) | Input port bit 1 of hresp_s8(1 downto 0) is unused @W:CL247 : coreahblite.vhd(251) | Input port bit 1 of hresp_s9(1 downto 0) is unused @W:CL247 : coreahblite.vhd(264) | Input port bit 1 of hresp_s10(1 downto 0) is unused @W:CL247 : coreahblite.vhd(277) | Input port bit 1 of hresp_s11(1 downto 0) is unused @W:CL247 : coreahblite.vhd(290) | Input port bit 1 of hresp_s12(1 downto 0) is unused @W:CL247 : coreahblite.vhd(303) | Input port bit 1 of hresp_s13(1 downto 0) is unused @W:CL247 : coreahblite.vhd(316) | Input port bit 1 of hresp_s14(1 downto 0) is unused @W:CL247 : coreahblite.vhd(329) | Input port bit 1 of hresp_s15(1 downto 0) is unused @W:CL247 : coreahblite.vhd(342) | Input port bit 1 of hresp_shg(1 downto 0) is unused @W:CL159 : coreahblite.vhd(116) | Input HBURST_M0 is unused @W:CL159 : coreahblite.vhd(117) | Input HPROT_M0 is unused @W:CL159 : coreahblite.vhd(127) | Input HBURST_M1 is unused @W:CL159 : coreahblite.vhd(128) | Input HPROT_M1 is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused @W:CL159 : MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused @W:CL190 : CoreTFTahbMasterAdvQVGA.vhd(711) | Optimizing register bit HaddrReg(0) to a constant 0 @W:CL260 : CoreTFTahbMasterAdvQVGA.vhd(711) | Pruning Register bit 0 of HaddrReg(31 downto 0) @N:CL201 : CoreTFTahbMasterAdvQVGA.vhd(831) | Trying to extract state machine for register MemCntlState Extracted state machine for register MemCntlState State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @W:CL246 : CoreTFTahbMasterAdvQVGA.vhd(80) | Input port bits 31 to 16 of hrdata(31 downto 0) are unused @W:CL246 : CoreTFTahbMasterAdvQVGA.vhd(100) | Input port bits 7 to 6 of paddr(7 downto 0) are unused @W:CL246 : CoreTFTahbMasterAdvQVGA.vhd(100) | Input port bits 1 to 0 of paddr(7 downto 0) are unused @N:CL134 : coregpio.vhd(479) | Found RAM CGPIOOI, depth=32, width=8 @N:CL201 : ahbtoapbsm.vhd(214) | Trying to extract state machine for register CAHBtoAPB3iol Extracted state machine for register CAHBtoAPB3iol State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @N:CL201 : penablescheduler.vhd(84) | Trying to extract state machine for register CAHBtoAPB3III Extracted state machine for register CAHBtoAPB3III State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL247 : coreahbtoapb3.vhd(16) | Input port bit 0 of htrans(1 downto 0) is unused @END Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue Nov 15 18:41:03 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 Reading constraint file: D:\Display\Posting\A2F500_7TFTLCD_WVGA_16bit_HW\constraint\Top_55TFT32bit_QVGA_EthMAC_syn.sdc Adding property syn_global_buffers, value 7 to view:work.Top_55TFT32bit_QVGA_EthMAC(def_arch) @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @N:BN116 : coreahblite_initcfg.vhd(231) | Removing sequential instance masterDataInProg[1:0] of view:PrimLib.dffre(prim) because there are no references to its outputs @N:BN115 : coreahblite_initcfg.vhd(163) | Removing instance init_cfg_client_arbiter of view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_init_cfg_client_arbiter(coreahblite_slavearbiter_arch) because there are no references to its outputs @N:BN116 : pulses2f_rf.vhd(66) | Removing sequential instance I_SRAM_CSN_START_PULSE.OUTR_PULSE of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : pulses2f_rf.vhd(66) | Removing sequential instance I_TFTDATA_START_PULSE.OUTR_PULSE of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : res_ctrl.vhd(80) | Removing sequential instance RESCTRL.I_HWRES66M_2 of view:PrimLib.dff(prim) because there are no references to its outputs @N:BN116 : res_ctrl.vhd(80) | Removing sequential instance RESCTRL.I_HWRES66M_1 of view:PrimLib.dff(prim) because there are no references to its outputs @N:BN116 : toggle_div.vhd(69) | Removing sequential instance TOGGLE_DIV_0.DIVREG_GEN\.3\.TOGGLEDIV_REG\.I_DIVREG[3] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : coreahblite_slavestage.vhd(110) | Removing sequential instance masterDataInProg[1:0] of view:PrimLib.dffre(prim) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found @W: : mss_new_top_tmp_mss_ccc_0_mss_ccc.vhd(116) | Net MSS_new_top_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_new_top_tmp_mss_ccc_0_mss_ccc.vhd(116) | Net MSS_new_top_0.MSS_ADLIB_INST_MACCLKCCC appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_new_top_tmp_mss_ccc_0_mss_ccc.vhd(116) | Net COREAHBTOAPB3_0.CAHBTOAPB3il0/HCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) @N:MO106 : coreapb3.vhd(406) | Found ROM, 'CoreAPB3_0.CAPB3iool_17[15:0]', 16 words by 16 bits @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[23] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[23] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[22] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[22] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[21] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[21] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[20] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[20] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[19] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[19] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[18] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[18] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[17] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[17] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[16] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[16] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[15] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[15] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[14] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[14] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[13] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(54) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[12] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(54) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3LLI[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[23] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[23] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[22] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[22] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[21] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[21] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[20] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[20] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[19] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[19] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[18] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[18] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[17] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[17] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[16] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[16] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[15] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[15] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[14] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[14] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[13] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : apbaddrdata.vhd(36) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[12] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : apbaddrdata.vhd(36) | Boundary register COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHSIZE[2] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHSIZE[1] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[0] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit SDATASELInt[4] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHSIZE[2] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[31] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[30] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[29] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[28] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[27] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[26] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[25] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[24] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[23] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[22] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[21] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit regHADDR[20] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit SDATASELInt[4] is always 0, optimizing ... Encoding state machine coreahblite_lib.COREAHBLITE_SLAVEARBITER_slave_arbiter_slave_arbiter(coreahblite_slavearbiter_arch)-arbRegSMCurrentState[0:7] original code -> new code 000 -> 00000001 001 -> 00000010 010 -> 00000100 011 -> 00001000 100 -> 00010000 101 -> 00100000 110 -> 01000000 111 -> 10000000 @N:BN116 : coreahblite_slavearbiter.vhd(154) | Removing sequential instance arbRegSMCurrentState[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : coreahblite_slavearbiter.vhd(132) | Removing sequential instance arbRegSMCurrentState[3] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : coreahblite_slavearbiter.vhd(92) | Removing sequential instance arbRegSMCurrentState[4] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : coreahblite_slavearbiter.vhd(66) | Removing sequential instance arbRegSMCurrentState[7] of view:PrimLib.dffs(prim) because there are no references to its outputs @W:MO129 : coreahblite_slavearbiter.vhd(118) | Sequential instance CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[6] has been reduced to a combinational gate by constant propagation @W:MO129 : coreahblite_slavearbiter.vhd(125) | Sequential instance CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[5] has been reduced to a combinational gate by constant propagation @W:MO129 : coreahblite_slavearbiter.vhd(147) | Sequential instance CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[1] has been reduced to a combinational gate by constant propagation @W:MO129 : coreahblite_slavearbiter.vhd(169) | Sequential instance CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[0] has been reduced to a combinational gate by constant propagation Encoding state machine coreahblite_lib.COREAHBLITE_SLAVEARBITER_slave_arbiter(coreahblite_slavearbiter_arch)-arbRegSMCurrentState[0:7] original code -> new code 000 -> 00000001 001 -> 00000010 010 -> 00000100 011 -> 00001000 100 -> 00010000 101 -> 00100000 110 -> 01000000 111 -> 10000000 @W:MO161 : coreahblite_slavearbiter.vhd(118) | Register bit arbRegSMCurrentState[6] is always 0, optimizing ... Encoding state machine coreahblite_lib.COREAHBLITE_SLAVEARBITER(coreahblite_slavearbiter_arch)-arbRegSMCurrentState[0:7] original code -> new code 000 -> 00000001 001 -> 00000010 010 -> 00000100 011 -> 00001000 100 -> 00010000 101 -> 00100000 110 -> 01000000 111 -> 10000000 @W:MO161 : coreahblite_slavearbiter.vhd(125) | Register bit arbRegSMCurrentState[5] is always 0, optimizing ... Encoding state machine work.CoreTFTahbMaster(s_rtl)-MemCntlState[0:4] original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N:MF176 : | Default generator successful @N:MF238 : vga7_timing_luca.vhd(51) | Found 11 bit incrementor, 'un3_v_cnt_1[10:0]' @N:MF238 : vga7_timing_luca.vhd(73) | Found 11 bit incrementor, 'un4_h_cnt[10:0]' @N:MF135 : coregpio.vhd(479) | Found RAM, 'CGPIOOI[7:0]', 32 words by 8 bits @N:MF135 : coregpio.vhd(479) | Found RAM, 'CGPIOOI[7:0]', 32 words by 8 bits @N:BN116 : coregpio.vhd(479) | Removing sequential instance CGPIOOI[7:0] of view:PrimLib.ram1(prim) because there are no references to its outputs Encoding state machine coreahbtoapb3_lib.CAHBTOAPB3O(cahbtoapb3lol)-CAHBtoAPB3iol[0:4] original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine coreahbtoapb3_lib.CAHBtoAPB3oii(cahbtoapb3lol)-CAHBtoAPB3III[0:2] original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit SDATASELInt[16] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(356) | Register bit RESERVEDDATASELInt is always 0, optimizing ... @W:BN132 : ahbtoapbsm.vhd(214) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3LL0.PWRITE, because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3LL0.CAHBtoAPB3iol[2] @W:BN132 : penablescheduler.vhd(84) | Removing sequential instance COREAHBTOAPB3_0.CAHBTOAPB3il0.PENABLE, because it is equivalent to instance COREAHBTOAPB3_0.CAHBTOAPB3il0.CAHBtoAPB3III[1] Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 84MB peak: 85MB) @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_17[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_17[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_18[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_18[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_19[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_19[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_20[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_20[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_21[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_21[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_22[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_22[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_23[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_23[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_24[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_24[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_25[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_25[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_26[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_26[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_27[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_27[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_28[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_28[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_29[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_29[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_30[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_30[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_31[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_31[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_2[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_2[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_3[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_3[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_4[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_4[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_4[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_4[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_5[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_5[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_5[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_5[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_6[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_6[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_6[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_6[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_7[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_7[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_7[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_7[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_8[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_8[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_8[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_8[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_9[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_9[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_9[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_9[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_10[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_10[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_10[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_10[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_11[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_11[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_11[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_11[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_12[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_12[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_12[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_12[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_13[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_13[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_14[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_14[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_15[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_15[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_16[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_16[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_0[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_0[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_1[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coregpio.vhd(479) | Boundary register CoreGPIO_0.CGPIOOI_1[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coretftahbmasteradvqvga.vhd(860) | Removing sequential instance CoreTFTahbMaster_0.DMA_ACTIVE of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coretftahbmasteradvqvga.vhd(860) | Boundary register CoreTFTahbMaster_0.DMA_ACTIVE has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[15] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[15] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[14] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[14] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[13] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[12] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[11] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[11] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[10] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[10] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[9] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[8] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[7] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[6] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[5] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[4] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[3] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[1] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_initcfg_awrap.vhd(123) | Boundary register CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_1.regHSIZE[1] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_1.regHSIZE[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_1.regHSIZE[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_1.regHSIZE[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 81MB peak: 86MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 84MB peak: 86MB) Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 85MB peak: 86MB) Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 85MB peak: 86MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:03s; Memory used current: 85MB peak: 86MB) @W:MO161 : coreahblite_slavearbiter.vhd(147) | Register bit CoreAHBLite_0.matrix2x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[1] is always 0, optimizing ... Finished preparing to map (Time elapsed 0h:00m:04s; Memory used current: 87MB peak: 88MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes --------------------------------------------------------------------------------------------------------------------- MSS_new_top_0.MSS_ADLIB_INST / M2FRESETn 997 : 995 asynchronous set/reset COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[2] / Q 133 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[3] / Q 69 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[4] / Q 37 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[6] / Q 44 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[0] / Q 64 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[1] / Q 73 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[2] / Q 41 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[3] / Q 73 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[4] / Q 41 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[5] / Q 73 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[6] / Q 73 COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[7] / Q 73 COREAHBTOAPB3_0.CAHBtoAPB3LL0.CAHBtoAPB3iol[3] / Q 37 CoreTFTahbMaster_0.SWHWRES_BUF / Y 55 : 54 asynchronous set/reset CoreAHBLite_0.matrix2x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[0] / Q 36 CoreAHBLite_0.matrix2x16.slavestage_5.masterDataInProg[0] / Q 32 CoreAHBLite_0.matrix2x16.slavestage_5.masterDataInProg[1] / Q 33 CoreAHBLite_0.matrix2x16.masterstage_1.masterRegAddrSel / Q 25 CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel / Q 35 CoreGPIO_0.CGPIOOLL_2_sqmuxa_6_i_0_o2 / Y 99 CoreGPIO_0.un1_paddr_1_0_a2_1_a2_0_a2 / Y 29 CoreGPIO_0.CGPIOOIa18_2 / Y 38 CoreGPIO_0.CGPIOOIa18_3 / Y 35 CoreGPIO_0.CGPIOOIa11_1 / Y 40 CoreAPB3_0.CAPB3iool_0_a2[9] / Y 33 CoreAPB3_0.CAPB3iool_0_a2[2] / Y 33 CoreTFTahbMaster_0.RAM_END_ADDR_1_sqmuxa / Y 32 CoreGPIO_0.CGPIOo0_0_sqmuxa_0_a2_3_a3_0_a4 / Y 32 CoreGPIO_0.prdata_0_iv_0_0_o2[28] / Y 33 CoreGPIO_0.prdata_0_iv_0_0_a2_0[28] / Y 33 COREAHBTOAPB3_0.CAHBtoAPB3LL0.CAHBtoAPB3oll_0_sqmuxa_0_a3 / Y 37 CoreGPIO_0.prdata_0_iv_0_0_a2[28] / Y 32 CoreGPIO_0.CGPIOOIa21_3 / Y 34 CoreTFTahbMaster_0.RAM_START_ADDR_1_sqmuxa / Y 32 CoreTFTahbMaster_0.FRAME_UPDATE_CHANGE.un4_i_frame_start / Y 67 CoreAHBLite_0.matrix2x16.masterstage_1.PREVDATASLAVEREADY_iv_0 / Y 33 CoreAHBLite_0.matrix2x16.masterstage_1.hready_m_xhdl384_0_a2 / Y 35 CoreGPIO_0.CGPIOOIa16_3 / Y 35 CoreGPIO_0.CGPIOOIa6_3 / Y 34 CoreAHBLite_0.matrix2x16.masterstage_0.PREVDATASLAVEREADY_iv_i_a2 / Y 34 CoreAHBLite_0.matrix2x16.masterstage_0.masterAddrClockEnable / Y 33 CoreTFTahbMaster_0.un1_MemCntlState_1_0 / Y 31 CoreAHBLite_0.matrix2x16.slavestage_16.slave_arbiter.MASTERADDRINPROG_0[0] / Y 35 CoreTFTahbMaster_0.CTRL_REG_0_sqmuxa / Y 32 ===================================================================================================================== @N:FP130 : | Promoting Net \\CoreAPB3_0_APBmslave2_PADDR_\[2\]\\ on CLKINT I_1084 @N:FP130 : | Promoting Net CoreGPIO_0.N_768 on CLKINT I_1085 Replicating Combinational Instance CoreTFTahbMaster_0.CTRL_REG_0_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance CoreAHBLite_0.matrix2x16.slavestage_16.slave_arbiter.MASTERADDRINPROG_0[0], fanout 35 segments 2 Replicating Combinational Instance CoreTFTahbMaster_0.un1_MemCntlState_1_0, fanout 31 segments 2 Replicating Combinational Instance CoreAHBLite_0.matrix2x16.masterstage_0.masterAddrClockEnable, fanout 33 segments 2 Replicating Combinational Instance CoreAHBLite_0.matrix2x16.masterstage_0.PREVDATASLAVEREADY_iv_i_a2, fanout 34 segments 2 Replicating Combinational Instance CoreGPIO_0.CGPIOOIa6_3, fanout 34 segments 2 Replicating Combinational Instance CoreGPIO_0.CGPIOOIa16_3, fanout 36 segments 2 Replicating Combinational Instance CoreAHBLite_0.matrix2x16.masterstage_1.hready_m_xhdl384_0_a2, fanout 35 segments 2 Replicating Combinational Instance CoreAHBLite_0.matrix2x16.masterstage_1.PREVDATASLAVEREADY_iv_0, fanout 33 segments 2 Replicating Combinational Instance CoreTFTahbMaster_0.FRAME_UPDATE_CHANGE.un4_i_frame_start, fanout 67 segments 3 Replicating Combinational Instance CoreTFTahbMaster_0.RAM_START_ADDR_1_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance CoreGPIO_0.CGPIOOIa21_3, fanout 34 segments 2 Replicating Combinational Instance CoreGPIO_0.prdata_0_iv_0_0_a2[28], fanout 32 segments 2 Replicating Combinational Instance COREAHBTOAPB3_0.CAHBtoAPB3LL0.CAHBtoAPB3oll_0_sqmuxa_0_a3, fanout 37 segments 2 Replicating Combinational Instance CoreGPIO_0.prdata_0_iv_0_0_a2_0[28], fanout 33 segments 2 Replicating Combinational Instance CoreGPIO_0.prdata_0_iv_0_0_o2[28], fanout 33 segments 2 Replicating Combinational Instance CoreGPIO_0.CGPIOo0_0_sqmuxa_0_a2_3_a3_0_a4, fanout 32 segments 2 Replicating Combinational Instance CoreTFTahbMaster_0.RAM_END_ADDR_1_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance CoreAPB3_0.CAPB3iool_0_a2[2], fanout 33 segments 2 Replicating Combinational Instance CoreAPB3_0.CAPB3iool_0_a2[9], fanout 33 segments 2 Replicating Combinational Instance CoreGPIO_0.CGPIOOIa11_1, fanout 41 segments 2 Replicating Combinational Instance CoreGPIO_0.CGPIOOIa18_3, fanout 36 segments 2 Replicating Combinational Instance CoreGPIO_0.CGPIOOIa18_2, fanout 41 segments 2 Replicating Combinational Instance CoreGPIO_0.un1_paddr_1_0_a2_1_a2_0_a2, fanout 29 segments 2 Replicating Sequential Instance CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel, fanout 36 segments 2 Replicating Sequential Instance CoreAHBLite_0.matrix2x16.masterstage_1.masterRegAddrSel, fanout 25 segments 2 Replicating Sequential Instance CoreAHBLite_0.matrix2x16.slavestage_5.masterDataInProg[1], fanout 33 segments 2 Replicating Sequential Instance CoreAHBLite_0.matrix2x16.slavestage_5.masterDataInProg[0], fanout 32 segments 2 Replicating Sequential Instance CoreAHBLite_0.matrix2x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[0], fanout 36 segments 2 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3LL0.CAHBtoAPB3iol[3], fanout 37 segments 2 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[7], fanout 73 segments 4 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[6], fanout 73 segments 4 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[5], fanout 73 segments 4 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[4], fanout 41 segments 2 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[3], fanout 73 segments 4 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[2], fanout 41 segments 2 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[1], fanout 73 segments 4 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBTOAPB3ILi[0], fanout 64 segments 3 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[6], fanout 44 segments 2 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[4], fanout 38 segments 2 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[3], fanout 70 segments 3 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3LL0.CAHBtoAPB3iol[3], fanout 32 segments 2 Replicating Sequential Instance COREAHBTOAPB3_0.CAHBtoAPB3oi0.CAHBtoAPB3oli[5], fanout 25 segments 2 Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 91MB peak: 94MB) @A:BN291 : coretftahbmasteradvqvga.vhd(937) | Boundary register CoreTFTahbMaster_0.I_RAM2_WR_EN has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:05s; Memory used current: 91MB peak: 94MB) Added 0 Buffers Added 56 Cells via replication Added 31 Sequential Cells via replication Added 25 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:05s; Memory used current: 92MB peak: 94MB) @W:BN105 : | Cannot apply constraint syn_maxfan to CCLK @W:BN105 : | Cannot apply constraint syn_maxfan to CoreCAMERA_AHBLMapb_0.SYNC_RES_CCLK Writing Analyst data base D:\Display\Posting\A2F500_7TFTLCD_WVGA_16bit_HW\synthesis\Top_55TFT32bit_QVGA_EthMAC.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:06s; Memory used current: 89MB peak: 94MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:06s; Memory used current: 91MB peak: 94MB) @W:MT246 : mss_new_top.vhd(1271) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_new_top.vhd(1134) | Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_new_top_tmp_mss_ccc_0_mss_ccc.vhd(154) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) Found clock MAINXIN with period 50.00ns Found clock MAC_CLK with period 20.00ns @W:MT420 : | Found inferred clock MSS_new_top|MSS_EMI_0_CLK_D_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:MSS_new_top_0.MSS_EMI_0_CLK_D" @W:MT420 : | Found inferred clock MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:MSS_new_top_0_FAB_CLK" @W:MT420 : | Found inferred clock MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_MACCLKCCC_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:MSS_new_top_0.MSS_ADLIB_INST_MACCLKCCC" @W:MT420 : | Found inferred clock MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:MSS_new_top_0.MSS_ADLIB_INST_FCLK" Found clock TOGGLE_DIV_0.DIVREG_GEN\.0\.TOGGLEDIV_REG\.I_DIVREG[0] with period 26.67ns Found clock TOGGLE_DIV_0.DIVREG_GEN\.1\.TOGGLEDIV_REG\.I_DIVREG[1] with period 53.33ns Found clock TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] with period 106.92ns ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Nov 15 18:41:10 2011 # Top view: Top_55TFT32bit_QVGA_EthMAC Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 1.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): D:\Display\Posting\A2F500_7TFTLCD_WVGA_16bit_HW\constraint\Top_55TFT32bit_QVGA_EthMAC_syn.sdc @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 17.510 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MAC_CLK 50.0 MHz 401.6 MHz 20.000 2.490 17.510 declared default_clkgroup_11 MAINXIN 20.0 MHz NA 50.000 NA NA declared default_clkgroup_8 MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 1.0 MHz 213.3 MHz 1000.000 4.689 995.312 inferred Inferred_clkgroup_1 MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock 1.0 MHz 24.8 MHz 1000.000 40.258 482.105 inferred Inferred_clkgroup_3 TOGGLE_DIV_0.DIVREG_GEN\.0\.TOGGLEDIV_REG\.I_DIVREG[0] 37.5 MHz 401.6 MHz 26.667 2.490 24.176 declared default_clkgroup_1 TOGGLE_DIV_0.DIVREG_GEN\.1\.TOGGLEDIV_REG\.I_DIVREG[1] 18.8 MHz 401.6 MHz 53.333 2.490 50.843 declared default_clkgroup_2 TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] 9.4 MHz 122.2 MHz 106.923 8.180 98.743 declared default_clkgroup_3 System 1.0 MHz 1117.3 MHz 1000.000 0.895 999.105 system system_clkgroup ================================================================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 1000.000 999.163 | No paths - | No paths - | No paths - System MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock | 1000.000 999.105 | No paths - | No paths - | No paths - TOGGLE_DIV_0.DIVREG_GEN\.0\.TOGGLEDIV_REG\.I_DIVREG[0] TOGGLE_DIV_0.DIVREG_GEN\.0\.TOGGLEDIV_REG\.I_DIVREG[0] | 26.667 24.176 | No paths - | No paths - | No paths - TOGGLE_DIV_0.DIVREG_GEN\.1\.TOGGLEDIV_REG\.I_DIVREG[1] TOGGLE_DIV_0.DIVREG_GEN\.1\.TOGGLEDIV_REG\.I_DIVREG[1] | 53.333 50.843 | No paths - | No paths - | No paths - TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] | 106.923 98.743 | No paths - | No paths - | No paths - TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MAC_CLK MAC_CLK | 20.000 17.510 | No paths - | No paths - | No paths - MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock System | 1000.000 995.036 | No paths - | No paths - | No paths - MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] | Diff grp - | No paths - | No paths - | No paths - MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 1000.000 995.312 | No paths - | No paths - | No paths - MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths - MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] | Diff grp - | No paths - | No paths - | No paths - MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock | 1000.000 959.743 | No paths - | 500.000 482.105 | 500.000 498.884 ============================================================================================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_new_top_0.MSS_ADLIB_INST MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB SPI1DO MSS_SPI_1_DO_D 4.643 995.035 MSS_new_top_0.MSS_ADLIB_INST MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB FABHREADYOUT CoreAHBLite_0_AHBmslave16_HREADY 2.980 995.312 MSS_new_top_0.MSS_ADLIB_INST MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB SPI1DOE MSS_SPI_1_DO_E 4.318 995.361 MSS_new_top_0.MSS_ADLIB_INST MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB GPO[24] MSSINT_GPO_24_A 4.132 995.547 MSS_new_top_0.MSS_ADLIB_INST MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB GPO[25] MSSINT_GPO_25_A 4.132 995.547 MSS_new_top_0.MSS_ADLIB_INST MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB GPO[26] MSSINT_GPO_26_A 4.132 995.547 MSS_new_top_0.MSS_ADLIB_INST MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB GPO[27] MSSINT_GPO_27_A 4.132 995.547 =============================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_new_top_0.MSS_SPI_1_DO MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS D MSS_SPI_1_DO_D 1000.000 995.035 MSS_new_top_0.MSS_ADLIB_INST MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB FABHREADY CoreAHBLite_0_AHBmslave16_HREADY 1000.000 995.312 MSS_new_top_0.MSS_SPI_1_DO MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS E MSS_SPI_1_DO_E 1000.000 995.361 MSS_new_top_0.MSSINT_GPO_24 MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSINT A MSSINT_GPO_24_A 1000.000 995.547 MSS_new_top_0.MSSINT_GPO_25 MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSINT A MSSINT_GPO_25_A 1000.000 995.547 MSS_new_top_0.MSSINT_GPO_26 MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSINT A MSSINT_GPO_26_A 1000.000 995.547 MSS_new_top_0.MSSINT_GPO_27 MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSINT A MSSINT_GPO_27_A 1000.000 995.547 ================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1000.000 - Propagation time: 4.965 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 995.035 Number of logic level(s): 0 Starting point: MSS_new_top_0.MSS_ADLIB_INST / SPI1DO Ending point: MSS_new_top_0.MSS_SPI_1_DO / D The start point is clocked by MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- MSS_new_top_0.MSS_ADLIB_INST MSS_AHB SPI1DO Out 4.643 4.643 - MSS_SPI_1_DO_D Net - - 0.322 - 1 MSS_new_top_0.MSS_SPI_1_DO TRIBUFF_MSS D In - 4.965 - ==================================================================================================== Total path delay (propagation time + setup) of 4.965 is 4.643(93.5%) logic and 0.322(6.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[10] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[10] 0.737 482.105 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[8] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[8] 0.737 482.132 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[11] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[11] 0.737 482.244 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[9] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[9] 0.737 482.272 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[6] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[6] 0.737 482.836 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[1] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[1] 0.737 482.878 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[7] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[7] 0.737 482.975 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[2] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[2] 0.737 482.977 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[5] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[5] 0.737 483.017 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[3] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q xhdl1222[3] 0.737 483.116 =============================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreTFTahbMaster_0.I_FIFO_WR_DATA[0] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[1] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[2] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[3] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[4] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[5] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[6] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[7] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[8] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 CoreTFTahbMaster_0.I_FIFO_WR_DATA[9] MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock DFN0E1C0 E N_613 499.392 482.105 ======================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 500.000 - Setup time: 0.608 + Clock delay at ending point: 0.000 (ideal) = Required time: 499.392 - Propagation time: 17.287 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 482.105 Number of logic level(s): 11 Starting point: CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[10] / Q Ending point: CoreTFTahbMaster_0.I_FIFO_WR_DATA[0] / E The start point is clocked by MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------- CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[10] DFN1E1C0 Q Out 0.737 0.737 - xhdl1222[10] Net - - 0.806 - 3 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNINDAF_0[10] NOR2 B In - 1.543 - CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNINDAF_0[10] NOR2 Y Out 0.646 2.190 - N_1050 Net - - 0.386 - 2 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNIS4BP[8] OR2B B In - 2.576 - CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNIS4BP[8] OR2B Y Out 0.516 3.092 - N_1052 Net - - 1.279 - 5 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNI6GBU_1[0] NOR2 B In - 4.371 - CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNI6GBU_1[0] NOR2 Y Out 0.646 5.017 - N_1054 Net - - 0.806 - 3 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNIQKDS1[0] OR3C C In - 5.824 - CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNIQKDS1[0] OR3C Y Out 0.666 6.489 - N_1041 Net - - 0.322 - 1 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNIKEKJ6[0] NOR3C C In - 6.811 - CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNIKEKJ6[0] NOR3C Y Out 0.641 7.452 - HRESP_iv_i_o3_1_2 Net - - 0.322 - 1 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNI8GUOA[0] AO1B A In - 7.774 - CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt_RNI8GUOA[0] AO1B Y Out 0.502 8.276 - N_1044_i Net - - 0.322 - 1 CoreAHBLite_0.matrix2x16.masterstage_0.CLDATASELInt_ORED_RNIFAQQN OR3C C In - 8.597 - CoreAHBLite_0.matrix2x16.masterstage_0.CLDATASELInt_ORED_RNIFAQQN OR3C Y Out 0.641 9.239 - N_1064 Net - - 0.386 - 2 CoreAHBLite_0.matrix2x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState_RNIRQ9RS OR2B A In - 9.624 - CoreAHBLite_0.matrix2x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState_RNIRQ9RS OR2B Y Out 0.488 10.113 - N_1031 Net - - 1.184 - 4 CoreAHBLite_0.matrix2x16.masterstage_0.RESERVEDDATASELInt_RNI99OE01 OR2B B In - 11.296 - CoreAHBLite_0.matrix2x16.masterstage_0.RESERVEDDATASELInt_RNI99OE01 OR2B Y Out 0.627 11.924 - HREADY_M_iv Net - - 0.386 - 2 CoreTFTahbMaster_0.un1_valid NOR2 B In - 12.310 - CoreTFTahbMaster_0.un1_valid NOR2 Y Out 0.514 12.824 - N_707 Net - - 1.776 - 11 CoreTFTahbMaster_0.MemCntlState_RNIJ0J8S1[0] NOR2B A In - 14.600 - CoreTFTahbMaster_0.MemCntlState_RNIJ0J8S1[0] NOR2B Y Out 0.514 15.115 - N_613 Net - - 2.172 - 16 CoreTFTahbMaster_0.I_FIFO_WR_DATA[0] DFN0E1C0 E In - 17.287 - ========================================================================================================================================================== Total path delay (propagation time + setup) of 17.895 is 7.749(43.3%) logic and 10.146(56.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[1] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 Q H_CNT[1] 0.737 98.743 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[0] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 Q V_CNT[0] 0.737 98.793 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[2] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 Q V_CNT[2] 0.737 98.832 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[0] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 Q H_CNT[0] 0.580 98.859 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[2] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 Q H_CNT[2] 0.737 98.955 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[1] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 Q V_CNT[1] 0.737 99.010 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[5] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 Q H_CNT[5] 0.737 99.033 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[8] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 Q H_CNT[8] 0.737 99.172 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[3] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 Q V_CNT[3] 0.737 99.268 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[4] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 Q H_CNT[4] 0.737 99.320 ============================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[10] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 D H_CNT_2[10] 106.350 98.743 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[9] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 D N_93 106.385 98.793 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.I_H_SYNC TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1P0 E un23_h_cnt 106.489 99.033 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[9] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 D I_52 106.385 99.483 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[5] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1C0 D H_CNT_2[5] 106.350 99.593 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[0] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 D N_10 106.385 99.619 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[2] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 D N_12 106.385 99.640 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[3] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 D N_14 106.385 99.640 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.V_CNT[10] TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1C0 D I_56_0 106.385 99.650 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.I_V_SYNC TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] DFN1E1P0 E un23_v_cnt 106.489 99.660 ================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 106.923 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 106.350 - Propagation time: 7.607 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 98.743 Number of logic level(s): 5 Starting point: CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[1] / Q Ending point: CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[10] / D The start point is clocked by TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] [rising] on pin CLK The end point is clocked by TOGGLE_DIV_0.DIVREG_GEN\.2\.TOGGLEDIV_REG\.I_DIVREG[2] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------- CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[1] DFN1C0 Q Out 0.737 0.737 - H_CNT[1] Net - - 1.526 - 7 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.un4_h_cnt.I_16 AND3 B In - 2.263 - CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.un4_h_cnt.I_16 AND3 Y Out 0.607 2.869 - DWACT_FINC_E_0[0] Net - - 1.423 - 6 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.un4_h_cnt.I_48 AND3 A In - 4.293 - CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.un4_h_cnt.I_48 AND3 Y Out 0.464 4.757 - DWACT_FINC_E_0[4] Net - - 0.386 - 2 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.un4_h_cnt.I_55 AND3 A In - 5.143 - CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.un4_h_cnt.I_55 AND3 Y Out 0.464 5.607 - N_4 Net - - 0.322 - 1 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.un4_h_cnt.I_56 XOR2 A In - 5.928 - CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.un4_h_cnt.I_56 XOR2 Y Out 0.408 6.337 - I_56 Net - - 0.322 - 1 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT_RNO[10] NOR2A A In - 6.658 - CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT_RNO[10] NOR2A Y Out 0.627 7.285 - H_CNT_2[10] Net - - 0.322 - 1 CoreTFTahbMaster_0.LCDCTRL.GEN_VGA\.VGA_TIMING0.H_CNT[10] DFN1C0 D In - 7.607 - =============================================================================================================================== Total path delay (propagation time + setup) of 8.180 is 3.881(47.4%) logic and 4.300(52.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------- MSS_new_top_0.MSSINT_GPO_24 System MSSINT Y MSS_new_top_0_M2F_GPO_24 0.000 999.105 MSS_new_top_0.MSSINT_GPO_25 System MSSINT Y MSS_new_top_0_M2F_GPO_25 0.000 999.105 MSS_new_top_0.MSSINT_GPO_26 System MSSINT Y MSS_new_top_0_M2F_GPO_26 0.000 999.105 MSS_new_top_0.MSSINT_GPO_27 System MSSINT Y MSS_new_top_0_M2F_GPO_27 0.000 999.105 MSS_new_top_0.MSSINT_GPI_21 System MSSINT Y MSSINT_GPI_21_Y 0.000 999.163 MSS_new_top_0.MSSINT_GPI_22 System MSSINT Y MSSINT_GPI_22_Y 0.000 999.163 MSS_new_top_0.MSSINT_GPI_23 System MSSINT Y MSSINT_GPI_23_Y 0.000 999.163 MSS_new_top_0.MSSINT_GPI_28 System MSSINT Y MSSINT_GPI_28_Y 0.000 999.163 MSS_new_top_0.MSSINT_GPI_29 System MSSINT Y MSSINT_GPI_29_Y 0.000 999.163 MSS_new_top_0.MSSINT_GPI_30 System MSSINT Y MSSINT_GPI_30_Y 0.000 999.163 ================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- CoreGPIO_0.CGPIOiOI\.9\.CGPIOI1[9] System DFN1C0 D MSS_new_top_0_M2F_GPO_24 999.427 999.105 CoreGPIO_0.CGPIOiOI\.10\.CGPIOI1[10] System DFN1C0 D MSS_new_top_0_M2F_GPO_25 999.427 999.105 CoreGPIO_0.CGPIOiOI\.11\.CGPIOI1[11] System DFN1C0 D MSS_new_top_0_M2F_GPO_26 999.427 999.105 CoreGPIO_0.CGPIOiOI\.12\.CGPIOI1[12] System DFN1C0 D MSS_new_top_0_M2F_GPO_27 999.427 999.105 MSS_new_top_0.MSS_ADLIB_INST System MSS_AHB GPI[21] MSSINT_GPI_21_Y 999.484 999.163 MSS_new_top_0.MSS_ADLIB_INST System MSS_AHB GPI[22] MSSINT_GPI_22_Y 999.484 999.163 MSS_new_top_0.MSS_ADLIB_INST System MSS_AHB GPI[23] MSSINT_GPI_23_Y 999.484 999.163 MSS_new_top_0.MSS_ADLIB_INST System MSS_AHB GPI[28] MSSINT_GPI_28_Y 999.484 999.163 MSS_new_top_0.MSS_ADLIB_INST System MSS_AHB GPI[29] MSSINT_GPI_29_Y 999.484 999.163 MSS_new_top_0.MSS_ADLIB_INST System MSS_AHB GPI[30] MSSINT_GPI_30_Y 999.484 999.163 ================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.427 - Propagation time: 0.322 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 999.105 Number of logic level(s): 0 Starting point: MSS_new_top_0.MSSINT_GPO_24 / Y Ending point: CoreGPIO_0.CGPIOiOI\.9\.CGPIOI1[9] / D The start point is clocked by System [rising] The end point is clocked by MSS_new_top_tmp_MSS_CCC_0_MSS_CCC|MSS_new_top_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- MSS_new_top_0.MSSINT_GPO_24 MSSINT Y Out 0.000 0.000 - MSS_new_top_0_M2F_GPO_24 Net - - 0.322 - 1 CoreGPIO_0.CGPIOiOI\.9\.CGPIOI1[9] DFN1C0 D In - 0.322 - =================================================================================================== Total path delay (propagation time + setup) of 0.895 is 0.573(64.1%) logic and 0.322(35.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA256_Std Report for cell Top_55TFT32bit_QVGA_EthMAC.def_arch Core Cell usage: cell count area count*area AND2 71 1.0 71.0 AND3 18 1.0 18.0 AO1 5 1.0 5.0 AO1A 49 1.0 49.0 AO1B 92 1.0 92.0 AO1C 114 1.0 114.0 AO1D 3 1.0 3.0 AOI1 7 1.0 7.0 AOI1B 125 1.0 125.0 AX1C 4 1.0 4.0 CLKINT 4 0.0 0.0 GND 31 0.0 0.0 INV 9 1.0 9.0 MAJ3 23 1.0 23.0 MSSINT 11 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 311 1.0 311.0 MX2A 1 1.0 1.0 MX2C 70 1.0 70.0 NAND2 27 1.0 27.0 NAND2A 1 1.0 1.0 NOR2 74 1.0 74.0 NOR2A 140 1.0 140.0 NOR2B 238 1.0 238.0 NOR3 9 1.0 9.0 NOR3A 83 1.0 83.0 NOR3B 92 1.0 92.0 NOR3C 128 1.0 128.0 OA1 31 1.0 31.0 OA1A 7 1.0 7.0 OA1B 3 1.0 3.0 OA1C 6 1.0 6.0 OAI1 3 1.0 3.0 OR2 119 1.0 119.0 OR2A 129 1.0 129.0 OR2B 194 1.0 194.0 OR3 12 1.0 12.0 OR3A 20 1.0 20.0 OR3B 168 1.0 168.0 OR3C 90 1.0 90.0 VCC 31 0.0 0.0 XA1 1 1.0 1.0 XA1A 8 1.0 8.0 XA1B 2 1.0 2.0 XNOR2 47 1.0 47.0 XO1A 3 1.0 3.0 XOR2 85 1.0 85.0 XOR3 23 1.0 23.0 ZOR3 1 1.0 1.0 DFI1C0 1 1.0 1.0 DFN0E1C0 16 1.0 16.0 DFN1 2 1.0 2.0 DFN1C0 275 1.0 275.0 DFN1E0C0 111 1.0 111.0 DFN1E1 256 1.0 256.0 DFN1E1C0 614 1.0 614.0 DFN1E1P0 53 1.0 53.0 DFN1P0 10 1.0 10.0 FIFO4K18 2 0.0 0.0 MSS_AHB 1 0.0 0.0 ----- ---------- TOTAL 4065 3984.0 IO Cell usage: cell count BIBUF_MSS 19 BIBUF_OPEND_MSS 2 INBUF 11 INBUF_A 5 INBUF_MSS 7 MSS_XTLOSC 1 OUTBUF 15 OUTBUF_MSS 55 TRIBUFF_MSS 1 ----- TOTAL 116 Core Cells : 3984 of 11520 (35%) IO Cells : 116 RAM/ROM Usage Summary Block Rams : 0 of 24 (0%) Mapper successful! Process took 0h:00m:07s realtime, 0h:00m:07s cputime # Tue Nov 15 18:41:10 2011 ###########################################################]