@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\COREAHBTOAPB3\2.0.116\rtl\vhdl\core_obfuscated\ahbtoapbsm.vhd":275:0:275:13|OTHERS clause is not synthesized 
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":909:17:909:21|Signal paddr in the sensitivity list is not used in the process
@W: CD275 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":214:13:214:18|Component declarations with different initial values are not supported.  Port a of component clkint may have been given a different initial value in two different component declarations
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":821:12:821:25|OTHERS clause is not synthesized 
@W: CD638 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":370:11:370:25|Signal i_fifo_full_ris is undriven 
@W: CD638 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":372:11:372:26|Signal i_fifo_empty_ris is undriven 
@W: CD638 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":394:9:394:20|Signal i_hw_n_reset is undriven 
@W: CD796 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":409:9:409:25|Bit 16 of signal i_ram_rd_data_mux is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":409:9:409:25|Bit 17 of signal i_ram_rd_data_mux is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD638 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":467:11:467:25|Signal i_tftdata_start is undriven 
@W: CD638 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":477:11:477:27|Signal i_tft_ctrl_en_ris is undriven 
@W: CL240 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":89:13:89:18|HWDATA is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL169 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":953:4:953:5|Pruning register I_FIFO_WR_CNT(20 downto 0)  
@W: CL169 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":879:8:879:9|Pruning register MemDataIn(31 downto 0)  
@W: CL111 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":953:4:953:5|All reachable assignments to I_RAM_WR_ADDR(0) assign '0'; register removed by optimization
@W: CL240 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":38:10:38:21|LPXIN_CLKOUT is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":37:10:37:23|MAINXIN_CLKOUT is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":36:10:36:21|RCOSC_CLKOUT is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL169 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_initcfg_awrap.vhd":123:8:123:9|Pruning register HREADYOUT_int_s1  
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_slavearbiter.vhd":177:12:177:25|OTHERS clause is not synthesized 
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:49:372:57|Signal hrdata_s0 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:60:372:71|Signal hreadyout_s0 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:108:372:116|Signal hrdata_s1 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:119:372:130|Signal hreadyout_s1 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:133:372:141|Signal hrdata_s2 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:144:372:155|Signal hreadyout_s2 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:158:372:166|Signal hrdata_s3 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:169:372:180|Signal hreadyout_s3 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:183:372:191|Signal hrdata_s4 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:194:372:205|Signal hreadyout_s4 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:233:372:241|Signal hrdata_s6 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:244:372:255|Signal hreadyout_s6 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:258:372:266|Signal hrdata_s7 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:269:372:280|Signal hreadyout_s7 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:283:372:291|Signal hrdata_s8 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:294:372:305|Signal hreadyout_s8 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:308:372:316|Signal hrdata_s9 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:319:372:330|Signal hreadyout_s9 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:333:372:342|Signal hrdata_s10 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:345:372:357|Signal hreadyout_s10 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:360:372:369|Signal hrdata_s11 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:372:372:384|Signal hreadyout_s11 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:387:372:396|Signal hrdata_s12 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:399:372:411|Signal hreadyout_s12 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:414:372:423|Signal hrdata_s13 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:426:372:438|Signal hreadyout_s13 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:441:372:450|Signal hrdata_s14 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:453:372:465|Signal hreadyout_s14 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:468:372:477|Signal hrdata_s15 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:480:372:492|Signal hreadyout_s15 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:495:372:504|Signal hrdata_shg in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:507:372:519|Signal hreadyout_shg in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:554:372:564|Signal cldataready in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:567:372:573|Signal clhresp in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:576:372:587|Signal hreadyout_cl in the sensitivity list is not used in the process
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":821:12:821:25|OTHERS clause is not synthesized 
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_defaultslavesm.vhd":65:12:65:25|OTHERS clause is not synthesized 
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:49:372:57|Signal hrdata_s0 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:60:372:71|Signal hreadyout_s0 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:108:372:116|Signal hrdata_s1 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:119:372:130|Signal hreadyout_s1 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:133:372:141|Signal hrdata_s2 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:144:372:155|Signal hreadyout_s2 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:158:372:166|Signal hrdata_s3 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:169:372:180|Signal hreadyout_s3 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:183:372:191|Signal hrdata_s4 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:194:372:205|Signal hreadyout_s4 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:208:372:216|Signal hrdata_s5 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:219:372:230|Signal hreadyout_s5 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:233:372:241|Signal hrdata_s6 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:244:372:255|Signal hreadyout_s6 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:258:372:266|Signal hrdata_s7 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:269:372:280|Signal hreadyout_s7 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:283:372:291|Signal hrdata_s8 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:294:372:305|Signal hreadyout_s8 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:308:372:316|Signal hrdata_s9 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:319:372:330|Signal hreadyout_s9 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:333:372:342|Signal hrdata_s10 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:345:372:357|Signal hreadyout_s10 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:360:372:369|Signal hrdata_s11 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:372:372:384|Signal hreadyout_s11 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:387:372:396|Signal hrdata_s12 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:399:372:411|Signal hreadyout_s12 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:414:372:423|Signal hrdata_s13 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:426:372:438|Signal hreadyout_s13 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:441:372:450|Signal hrdata_s14 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:453:372:465|Signal hreadyout_s14 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:468:372:477|Signal hrdata_s15 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:480:372:492|Signal hreadyout_s15 in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:554:372:564|Signal cldataready in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:567:372:573|Signal clhresp in the sensitivity list is not used in the process
@W: CD434 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":372:576:372:587|Signal hreadyout_cl in the sensitivity list is not used in the process
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":821:12:821:25|OTHERS clause is not synthesized 
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":439:0:439:13|OTHERS clause is not synthesized 
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3_muxptob3.vhd":152:0:152:13|OTHERS clause is not synthesized 
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3_muxptob3.vhd":195:0:195:13|OTHERS clause is not synthesized 
@W: CD604 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3_muxptob3.vhd":238:0:238:13|OTHERS clause is not synthesized 
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":35:0:35:4|Input port bits 23 to 12 of paddr(23 downto 0) are unused 
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":33:52:33:58|Input presetn is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":34:0:34:3|Input pclk is unused
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":52:8:52:17|Input port bits 15 to 0 of sdataready(16 downto 0) are unused 
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":53:8:53:13|Input port bits 15 to 0 of shresp(16 downto 0) are unused 
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":55:8:55:18|Input CLDATAREADY is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":56:8:56:14|Input CLHRESP is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":68:8:68:16|Input HRDATA_S0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":69:8:69:19|Input HREADYOUT_S0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":70:8:70:16|Input HRDATA_S1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":71:8:71:19|Input HREADYOUT_S1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":72:8:72:16|Input HRDATA_S2 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":73:8:73:19|Input HREADYOUT_S2 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":74:8:74:16|Input HRDATA_S3 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":75:8:75:19|Input HREADYOUT_S3 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":76:8:76:16|Input HRDATA_S4 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":77:8:77:19|Input HREADYOUT_S4 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":78:8:78:16|Input HRDATA_S5 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":79:8:79:19|Input HREADYOUT_S5 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":80:8:80:16|Input HRDATA_S6 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":81:8:81:19|Input HREADYOUT_S6 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":82:8:82:16|Input HRDATA_S7 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":83:8:83:19|Input HREADYOUT_S7 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":84:8:84:16|Input HRDATA_S8 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":85:8:85:19|Input HREADYOUT_S8 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":86:8:86:16|Input HRDATA_S9 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":87:8:87:19|Input HREADYOUT_S9 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":88:8:88:17|Input HRDATA_S10 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":89:8:89:20|Input HREADYOUT_S10 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":90:8:90:17|Input HRDATA_S11 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":91:8:91:20|Input HREADYOUT_S11 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":92:8:92:17|Input HRDATA_S12 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":93:8:93:20|Input HREADYOUT_S12 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":94:8:94:17|Input HRDATA_S13 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":95:8:95:20|Input HREADYOUT_S13 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":96:8:96:17|Input HRDATA_S14 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":97:8:97:20|Input HREADYOUT_S14 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":98:8:98:17|Input HRDATA_S15 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":99:8:99:20|Input HREADYOUT_S15 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":102:8:102:19|Input HREADYOUT_CL is unused
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":52:8:52:17|Input port bits 16 to 6 of sdataready(16 downto 0) are unused 
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":52:8:52:17|Input port bits 4 to 0 of sdataready(16 downto 0) are unused 
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":53:8:53:13|Input port bits 16 to 6 of shresp(16 downto 0) are unused 
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":53:8:53:13|Input port bits 4 to 0 of shresp(16 downto 0) are unused 
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":55:8:55:18|Input CLDATAREADY is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":56:8:56:14|Input CLHRESP is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":68:8:68:16|Input HRDATA_S0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":69:8:69:19|Input HREADYOUT_S0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":70:8:70:16|Input HRDATA_S1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":71:8:71:19|Input HREADYOUT_S1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":72:8:72:16|Input HRDATA_S2 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":73:8:73:19|Input HREADYOUT_S2 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":74:8:74:16|Input HRDATA_S3 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":75:8:75:19|Input HREADYOUT_S3 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":76:8:76:16|Input HRDATA_S4 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":77:8:77:19|Input HREADYOUT_S4 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":80:8:80:16|Input HRDATA_S6 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":81:8:81:19|Input HREADYOUT_S6 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":82:8:82:16|Input HRDATA_S7 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":83:8:83:19|Input HREADYOUT_S7 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":84:8:84:16|Input HRDATA_S8 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":85:8:85:19|Input HREADYOUT_S8 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":86:8:86:16|Input HRDATA_S9 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":87:8:87:19|Input HREADYOUT_S9 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":88:8:88:17|Input HRDATA_S10 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":89:8:89:20|Input HREADYOUT_S10 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":90:8:90:17|Input HRDATA_S11 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":91:8:91:20|Input HREADYOUT_S11 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":92:8:92:17|Input HRDATA_S12 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":93:8:93:20|Input HREADYOUT_S12 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":94:8:94:17|Input HRDATA_S13 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":95:8:95:20|Input HREADYOUT_S13 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":96:8:96:17|Input HRDATA_S14 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":97:8:97:20|Input HREADYOUT_S14 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":98:8:98:17|Input HRDATA_S15 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":99:8:99:20|Input HREADYOUT_S15 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":100:8:100:17|Input HRDATA_SHG is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":101:8:101:20|Input HREADYOUT_SHG is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":102:8:102:19|Input HREADYOUT_CL is unused
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_initcfg_awrap.vhd":43:8:43:12|Input port bits 31 to 12 of haddr(31 downto 0) are unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_initcfg_awrap.vhd":47:8:47:13|Input port bit 0 of htrans(1 downto 0) is unused 
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_initcfg.vhd":47:8:47:19|Input CLADDRSEL_M0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_initcfg.vhd":48:8:48:19|Input CLADDRSEL_M1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":64:8:64:16|Input HRDATA_S0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":65:8:65:19|Input HREADYOUT_S0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":66:8:66:15|Input HRESP_S0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":75:8:75:16|Input HRDATA_S1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":76:8:76:19|Input HREADYOUT_S1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":77:8:77:15|Input HRESP_S1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":86:8:86:16|Input HRDATA_S2 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":87:8:87:19|Input HREADYOUT_S2 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":88:8:88:15|Input HRESP_S2 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":97:8:97:16|Input HRDATA_S3 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":98:8:98:19|Input HREADYOUT_S3 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":99:8:99:15|Input HRESP_S3 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":108:8:108:16|Input HRDATA_S4 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":109:8:109:19|Input HREADYOUT_S4 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":110:8:110:15|Input HRESP_S4 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":130:8:130:16|Input HRDATA_S6 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":131:8:131:19|Input HREADYOUT_S6 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":132:8:132:15|Input HRESP_S6 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":141:8:141:16|Input HRDATA_S7 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":142:8:142:19|Input HREADYOUT_S7 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":143:8:143:15|Input HRESP_S7 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":152:8:152:16|Input HRDATA_S8 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":153:8:153:19|Input HREADYOUT_S8 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":154:8:154:15|Input HRESP_S8 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":163:8:163:16|Input HRDATA_S9 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":164:8:164:19|Input HREADYOUT_S9 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":165:8:165:15|Input HRESP_S9 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":174:8:174:17|Input HRDATA_S10 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":175:8:175:20|Input HREADYOUT_S10 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":176:8:176:16|Input HRESP_S10 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":185:8:185:17|Input HRDATA_S11 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":186:8:186:20|Input HREADYOUT_S11 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":187:8:187:16|Input HRESP_S11 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":196:8:196:17|Input HRDATA_S12 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":197:8:197:20|Input HREADYOUT_S12 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":198:8:198:16|Input HRESP_S12 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":207:8:207:17|Input HRDATA_S13 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":208:8:208:20|Input HREADYOUT_S13 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":209:8:209:16|Input HRESP_S13 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":218:8:218:17|Input HRDATA_S14 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":219:8:219:20|Input HREADYOUT_S14 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":220:8:220:16|Input HRESP_S14 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":229:8:229:17|Input HRDATA_S15 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":230:8:230:20|Input HREADYOUT_S15 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd":231:8:231:16|Input HRESP_S15 is unused
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":113:0:113:8|Input port bit 0 of htrans_m0(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":124:0:124:8|Input port bit 0 of htrans_m1(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":134:0:134:7|Input port bit 1 of hresp_s0(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":147:0:147:7|Input port bit 1 of hresp_s1(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":160:0:160:7|Input port bit 1 of hresp_s2(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":173:0:173:7|Input port bit 1 of hresp_s3(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":186:0:186:7|Input port bit 1 of hresp_s4(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":199:0:199:7|Input port bit 1 of hresp_s5(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":212:0:212:7|Input port bit 1 of hresp_s6(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":225:0:225:7|Input port bit 1 of hresp_s7(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":238:0:238:7|Input port bit 1 of hresp_s8(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":251:0:251:7|Input port bit 1 of hresp_s9(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":264:0:264:8|Input port bit 1 of hresp_s10(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":277:0:277:8|Input port bit 1 of hresp_s11(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":290:0:290:8|Input port bit 1 of hresp_s12(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":303:0:303:8|Input port bit 1 of hresp_s13(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":316:0:316:8|Input port bit 1 of hresp_s14(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":329:0:329:8|Input port bit 1 of hresp_s15(1 downto 0) is unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":342:0:342:8|Input port bit 1 of hresp_shg(1 downto 0) is unused 
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":116:0:116:8|Input HBURST_M0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":117:0:117:7|Input HPROT_M0 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":127:0:127:8|Input HBURST_M1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd":128:0:128:7|Input HPROT_M1 is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":10:10:10:13|Input CLKA is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":11:10:11:17|Input CLKA_PAD is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":12:10:12:18|Input CLKA_PADP is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":13:10:13:18|Input CLKA_PADN is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":14:10:14:13|Input CLKB is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":15:10:15:17|Input CLKB_PAD is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":16:10:16:18|Input CLKB_PADP is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":17:10:17:18|Input CLKB_PADN is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":18:10:18:13|Input CLKC is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":19:10:19:17|Input CLKC_PAD is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":20:10:20:18|Input CLKC_PADP is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":21:10:21:18|Input CLKC_PADN is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":23:10:23:14|Input LPXIN is unused
@W: CL159 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\work\MSS_new_top\MSS_CCC_0\MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd":24:10:24:16|Input MAC_CLK is unused
@W: CL190 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":711:8:711:9|Optimizing register bit HaddrReg(0) to a constant 0
@W: CL260 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":711:8:711:9|Pruning register bit 0 of HaddrReg(31 downto 0)  
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":80:13:80:18|Input port bits 31 to 16 of hrdata(31 downto 0) are unused 
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":100:13:100:17|Input port bits 7 to 6 of paddr(7 downto 0) are unused 
@W: CL246 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\hdl\CoreTFTahbMasterAdvQVGA.vhd":100:13:100:17|Input port bits 1 to 0 of paddr(7 downto 0) are unused 
@W: CL247 :"C:\SmartFusionOpenGLSC_Demo\A2F500\SevenInchTFTLCD_WVGA_16bit_Interface\component\Actel\DirectCore\COREAHBTOAPB3\2.0.116\rtl\vhdl\core_obfuscated\coreahbtoapb3.vhd":16:0:16:5|Input port bit 0 of htrans(1 downto 0) is unused 

