@W: MO161 :"c:\smartfusionopenglsc_demo\a2f500\seveninchtftlcd_wvga_16bit_interface\hdl\i2c_core.vhd":144:2:144:16|Register bit CAMERA_INIT_0.i2c_core_0.state[3] is always 0, optimizing ...
@W: MT420 |Found inferred clock CAMERA_TOP_LUCA|CLK with period 10.00ns. Please declare a user-defined clock on object "p:CLK"
@W: MT420 |Found inferred clock CAMERA_TOP_LUCA|CCLK with period 10.00ns. Please declare a user-defined clock on object "p:CCLK"
