Timing Report Min Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Fri Nov 23 18:10:04 2012


Design: Top_7TFT16Bit_WVGA_Controller
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                3.088
Frequency (MHz):            323.834
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        6.393
External Hold (ns):         -0.667
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                22.848
Frequency (MHz):            43.768
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        5.145
External Hold (ns):         -0.459
Min Clock-To-Out (ns):      3.690
Max Clock-To-Out (ns):      8.901

Clock Domain:               mss_ccc_glc
Period (ns):                1.845
Frequency (MHz):            542.005
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.662
Max Clock-To-Out (ns):      5.085

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
Period (ns):                1.905
Frequency (MHz):            524.934
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
Period (ns):                1.857
Frequency (MHz):            538.503
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.305
Max Clock-To-Out (ns):      8.494

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
Period (ns):                7.907
Frequency (MHz):            126.470
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.850
Max Clock-To-Out (ns):      11.794

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  Delay (ns):                  2.415
  Slack (ns):
  Arrival (ns):                2.415
  Required (ns):
  Hold (ns):                   1.023


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  data arrival time                              2.415
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.562          cell: ADLIB:MSS_AHB_IP
  1.562                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.080          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  1.642                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  1.683                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     0.287          net: CoreAHBLite_0_AHBmslave16_HREADY
  1.970                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6 (r)
               +     0.036          cell: ADLIB:MSS_IF
  2.006                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6INT (r)
               +     0.409          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYINT_NET
  2.415                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY (r)
                                    
  2.415                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.023          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        SDCARD_CD
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]
  Delay (ns):                  1.021
  Slack (ns):
  Arrival (ns):                1.021
  Required (ns):
  Hold (ns):                   0.354
  External Hold (ns):          -0.667

Path 2
  From:                        SDCARD_WP
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[21]
  Delay (ns):                  1.190
  Slack (ns):
  Arrival (ns):                1.190
  Required (ns):
  Hold (ns):                   0.150
  External Hold (ns):          -1.040

Path 3
  From:                        PBUTTON[1]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  1.776
  Slack (ns):
  Arrival (ns):                1.776
  Required (ns):
  Hold (ns):                   0.354
  External Hold (ns):          -1.422

Path 4
  From:                        PBUTTON[2]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[29]
  Delay (ns):                  3.324
  Slack (ns):
  Arrival (ns):                3.324
  Required (ns):
  Hold (ns):                   0.432
  External Hold (ns):          -2.892

Path 5
  From:                        PBUTTON[0]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23]
  Delay (ns):                  3.464
  Slack (ns):
  Arrival (ns):                3.464
  Required (ns):
  Hold (ns):                   0.435
  External Hold (ns):          -3.029


Expanded Path 1
  From: SDCARD_CD
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]
  data arrival time                              1.021
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SDCARD_CD (f)
               +     0.000          net: SDCARD_CD
  0.000                        SDCARD_CD_pad/U0/U0:PAD (f)
               +     0.292          cell: ADLIB:IOPAD_IN
  0.292                        SDCARD_CD_pad/U0/U0:Y (f)
               +     0.000          net: SDCARD_CD_pad/U0/NET1
  0.292                        SDCARD_CD_pad/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.310                        SDCARD_CD_pad/U0/U1:Y (f)
               +     0.543          net: SDCARD_CD_c
  0.853                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN5 (f)
               +     0.090          cell: ADLIB:MSS_IF
  0.943                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN5INT (f)
               +     0.078          net: MSS_new_top_0/MSS_ADLIB_INST/GPI[22]INT_NET
  1.021                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22] (f)
                                    
  1.021                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     0.354          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          1.283


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MSS_new_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.270          net: MSS_new_top_0/GLA0
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        CoreGPIO_0/CGPIOiOI.18.CGPIOI1[18]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.18.CGPIOOOL[18]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.716
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.6.CGPIOOOL[6]:D
  Delay (ns):                  0.402
  Slack (ns):
  Arrival (ns):                0.772
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        CoreGPIO_0/CGPIOiOI.29.CGPIOI1[29]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.29.CGPIOOOL[29]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.758
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        CoreGPIO_0/CGPIOiOI.15.CGPIOI1[15]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.15.CGPIOOOL[15]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.755
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_RIS1:CLK
  To:                          CoreTFTahbMaster_0/I_TFTDATA_START_RIS2:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.755
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: CoreGPIO_0/CGPIOiOI.18.CGPIOI1[18]:CLK
  To: CoreGPIO_0/CGPIOiOI.18.CGPIOOOL[18]:D
  data arrival time                              0.716
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.319          net: FAB_CLK
  0.319                        CoreGPIO_0/CGPIOiOI.18.CGPIOI1[18]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.567                        CoreGPIO_0/CGPIOiOI.18.CGPIOI1[18]:Q (r)
               +     0.149          net: CoreGPIO_0/CGPIOI1[18]
  0.716                        CoreGPIO_0/CGPIOiOI.18.CGPIOOOL[18]:D (r)
                                    
  0.716                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.355          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOiOI.18.CGPIOOOL[18]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOiOI.18.CGPIOOOL[18]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        DIP_SWITCH[2]
  To:                          CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D
  Delay (ns):                  0.830
  Slack (ns):
  Arrival (ns):                0.830
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.459

Path 2
  From:                        PBUTTON[1]
  To:                          CoreGPIO_0/CGPIOiOI.5.CGPIOI1[5]:D
  Delay (ns):                  1.045
  Slack (ns):
  Arrival (ns):                1.045
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.598

Path 3
  From:                        DIP_SWITCH[0]
  To:                          CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D
  Delay (ns):                  1.109
  Slack (ns):
  Arrival (ns):                1.109
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.725

Path 4
  From:                        DIP_SWITCH[1]
  To:                          CoreGPIO_0/CGPIOiOI.1.CGPIOI1[1]:D
  Delay (ns):                  1.165
  Slack (ns):
  Arrival (ns):                1.165
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.794

Path 5
  From:                        DIP_SWITCH[3]
  To:                          CoreGPIO_0/CGPIOiOI.3.CGPIOI1[3]:D
  Delay (ns):                  1.310
  Slack (ns):
  Arrival (ns):                1.310
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.939


Expanded Path 1
  From: DIP_SWITCH[2]
  To: CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D
  data arrival time                              0.830
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        DIP_SWITCH[2] (f)
               +     0.000          net: DIP_SWITCH[2]
  0.000                        DIP_SWITCH_pad[2]/U0/U0:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        DIP_SWITCH_pad[2]/U0/U0:Y (f)
               +     0.000          net: DIP_SWITCH_pad[2]/U0/NET1
  0.276                        DIP_SWITCH_pad[2]/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.294                        DIP_SWITCH_pad[2]/U0/U1:Y (f)
               +     0.536          net: DIP_SWITCH_c[2]
  0.830                        CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D (f)
                                    
  0.830                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.371          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreTFTahbMaster_0/CTRL_REG[5]/U1:CLK
  To:                          TFT_BACKLIGHT_EN
  Delay (ns):                  3.347
  Slack (ns):
  Arrival (ns):                3.690
  Required (ns):
  Clock to Out (ns):           3.690

Path 2
  From:                        CoreGPIO_0/CGPIOOI_0[0]/U1:CLK
  To:                          LED[0]
  Delay (ns):                  3.452
  Slack (ns):
  Arrival (ns):                3.786
  Required (ns):
  Clock to Out (ns):           3.786

Path 3
  From:                        CoreGPIO_0/CGPIOOI_2[0]/U1:CLK
  To:                          LED[2]
  Delay (ns):                  3.483
  Slack (ns):
  Arrival (ns):                3.807
  Required (ns):
  Clock to Out (ns):           3.807

Path 4
  From:                        CoreGPIO_0/CGPIOOI_1[0]/U1:CLK
  To:                          LED[1]
  Delay (ns):                  3.560
  Slack (ns):
  Arrival (ns):                3.881
  Required (ns):
  Clock to Out (ns):           3.881

Path 5
  From:                        CoreGPIO_0/CGPIOOI_3[0]/U1:CLK
  To:                          LED[3]
  Delay (ns):                  3.689
  Slack (ns):
  Arrival (ns):                4.013
  Required (ns):
  Clock to Out (ns):           4.013


Expanded Path 1
  From: CoreTFTahbMaster_0/CTRL_REG[5]/U1:CLK
  To: TFT_BACKLIGHT_EN
  data arrival time                              3.690
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.343          net: FAB_CLK
  0.343                        CoreTFTahbMaster_0/CTRL_REG[5]/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.591                        CoreTFTahbMaster_0/CTRL_REG[5]/U1:Q (r)
               +     1.735          net: TFT_BACKLIGHT_EN_c
  2.326                        TFT_BACKLIGHT_EN_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  2.605                        TFT_BACKLIGHT_EN_pad/U0/U1:DOUT (r)
               +     0.000          net: TFT_BACKLIGHT_EN_pad/U0/NET1
  2.605                        TFT_BACKLIGHT_EN_pad/U0/U0:D (r)
               +     1.085          cell: ADLIB:IOPAD_TRI
  3.690                        TFT_BACKLIGHT_EN_pad/U0/U0:PAD (r)
               +     0.000          net: TFT_BACKLIGHT_EN
  3.690                        TFT_BACKLIGHT_EN (r)
                                    
  3.690                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          TFT_BACKLIGHT_EN (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  1.770
  Slack (ns):
  Arrival (ns):                2.117
  Required (ns):
  Removal (ns):                0.196
  Skew (ns):                   -0.086

Path 2
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  1.817
  Slack (ns):
  Arrival (ns):                2.185
  Required (ns):
  Removal (ns):                0.196
  Skew (ns):                   -0.065

Path 3
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  2.073
  Slack (ns):
  Arrival (ns):                2.420
  Required (ns):
  Removal (ns):                0.196
  Skew (ns):                   -0.085

Path 4
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  2.120
  Slack (ns):
  Arrival (ns):                2.488
  Required (ns):
  Removal (ns):                0.196
  Skew (ns):                   -0.064


Expanded Path 1
  From: CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  data arrival time                              2.117
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.347          net: FAB_CLK
  0.347                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK (r)
               +     0.319          cell: ADLIB:DFN1C0
  0.666                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:Q (f)
               +     0.499          net: CoreTFTahbMaster_0/I_TFTDATA_START_RIS
  1.165                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:B (f)
               +     0.174          cell: ADLIB:NOR2A
  1.339                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:Y (r)
               +     0.778          net: CoreTFTahbMaster_0/OUTF_PULSE_RNITR1U
  2.117                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET (r)
                                    
  2.117                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.433          net: FAB_CLK
  N/C                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:WCLK (r)
               +     0.196          Library removal time: ADLIB:FIFO4K18
  N/C                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  Delay (ns):                  0.697
  Slack (ns):
  Arrival (ns):                1.007
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  data arrival time                              1.007
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.310          net: MAC_CLK_c
  0.310                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.558                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.144          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  0.702                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:A (r)
               +     0.158          cell: ADLIB:INV
  0.860                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:Y (f)
               +     0.147          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[0]
  1.007                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D (f)
                                    
  1.007                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.326          net: MAC_CLK_c
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          MAC_CLK
  Delay (ns):                  2.662
  Slack (ns):
  Arrival (ns):                2.662
  Required (ns):
  Clock to Out (ns):           2.662


Expanded Path 1
  From: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: MAC_CLK
  data arrival time                              2.662
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     0.957          cell: ADLIB:MSS_CCC_IP
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.310          net: MAC_CLK_c
  1.267                        MAC_CLK_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  1.546                        MAC_CLK_pad/U0/U1:DOUT (r)
               +     0.000          net: MAC_CLK_pad/U0/NET1
  1.546                        MAC_CLK_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.662                        MAC_CLK_pad/U0/U0:PAD (r)
               +     0.000          net: MAC_CLK
  2.662                        MAC_CLK (r)
                                    
  2.662                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          MAC_CLK (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  Delay (ns):                  0.736
  Slack (ns):
  Arrival (ns):                1.267
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  data arrival time                              1.267
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.531          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  0.531                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.779                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.180          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.959                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:A (r)
               +     0.158          cell: ADLIB:INV
  1.117                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:Y (f)
               +     0.150          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[1]
  1.267                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D (f)
                                    
  1.267                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.638          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  Delay (ns):                  0.705
  Slack (ns):
  Arrival (ns):                0.892
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  data arrival time                              0.892
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.187          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.187                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.435                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.148          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.583                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:A (r)
               +     0.158          cell: ADLIB:INV
  0.741                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:Y (f)
               +     0.151          net: TOGGLE_DIV_0/TOGGLE_DIV_0_DIVREG_OUT2to2_i_i
  0.892                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D (f)
                                    
  0.892                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.225          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          IO_2_PADOUT
  Delay (ns):                  4.118
  Slack (ns):
  Arrival (ns):                4.305
  Required (ns):
  Clock to Out (ns):           4.305


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: IO_2_PADOUT
  data arrival time                              4.305
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.187          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.187                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.435                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.683          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.118                        CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  1.859                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.345          net: CLKINT_0_Y
  2.204                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:B (r)
               +     0.221          cell: ADLIB:NOR2B
  2.425                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:Y (r)
               +     0.352          net: CoreTFTahbMaster_0_RGB_CLK
  2.777                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  2.879                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5INT (r)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_2/U0/D_INT
  2.879                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:D (r)
               +     1.426          cell: ADLIB:IOPAD_TRI
  4.305                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:PAD (r)
               +     0.000          net: IO_2_PADOUT
  4.305                        IO_2_PADOUT (r)
                                    
  4.305                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
                                    
  N/C                          IO_2_PADOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q

SET Register to Register

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_SYNC:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:D
  Delay (ns):                  0.392
  Slack (ns):
  Arrival (ns):                2.161
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/I_H_SYNC:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_SYNC:D
  Delay (ns):                  0.393
  Slack (ns):
  Arrival (ns):                2.164
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_1:CLK
  To:                          CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:D
  Delay (ns):                  0.393
  Slack (ns):
  Arrival (ns):                2.142
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/I_INCR_VCNT:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[4]:E
  Delay (ns):                  0.421
  Slack (ns):
  Arrival (ns):                2.209
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/I_INCR_VCNT:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[9]:E
  Delay (ns):                  0.421
  Slack (ns):
  Arrival (ns):                2.209
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_SYNC:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:D
  data arrival time                              2.161
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.683          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.683                        CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  1.424                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.345          net: CLKINT_0_Y
  1.769                        CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_SYNC:CLK (r)
               +     0.248          cell: ADLIB:DFN1P0
  2.017                        CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_SYNC:Q (r)
               +     0.144          net: CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC
  2.161                        CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:D (r)
                                    
  2.161                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.683          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.365          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_data_en:CLK
  To:                          IO_5_PADOUT
  Delay (ns):                  2.081
  Slack (ns):
  Arrival (ns):                3.850
  Required (ns):
  Clock to Out (ns):           3.850

Path 2
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_v_sync:CLK
  To:                          IO_1_PADOUT
  Delay (ns):                  2.217
  Slack (ns):
  Arrival (ns):                3.986
  Required (ns):
  Clock to Out (ns):           3.986

Path 3
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[3]:CLK
  To:                          B_DATA4
  Delay (ns):                  2.277
  Slack (ns):
  Arrival (ns):                4.017
  Required (ns):
  Clock to Out (ns):           4.017

Path 4
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_G[2]:CLK
  To:                          IO_12_PADOUT
  Delay (ns):                  2.404
  Slack (ns):
  Arrival (ns):                4.152
  Required (ns):
  Clock to Out (ns):           4.152

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_h_sync:CLK
  To:                          IO_4_PADOUT
  Delay (ns):                  2.405
  Slack (ns):
  Arrival (ns):                4.174
  Required (ns):
  Clock to Out (ns):           4.174


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/VGA_data_en:CLK
  To: IO_5_PADOUT
  data arrival time                              3.850
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.683          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.683                        CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  1.424                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.345          net: CLKINT_0_Y
  1.769                        CoreTFTahbMaster_0/LCDCTRL/VGA_data_en:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  2.017                        CoreTFTahbMaster_0/LCDCTRL/VGA_data_en:Q (r)
               +     0.370          net: CoreTFTahbMaster_0_DATA_EN
  2.387                        MSS_new_top_0/FIO_OUTBUF_5/U0/U1:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  2.424                        MSS_new_top_0/FIO_OUTBUF_5/U0/U1:PIN5INT (r)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_5/U0/D_INT
  2.424                        MSS_new_top_0/FIO_OUTBUF_5/U0/U0:D (r)
               +     1.426          cell: ADLIB:IOPAD_TRI
  3.850                        MSS_new_top_0/FIO_OUTBUF_5/U0/U0:PAD (r)
               +     0.000          net: IO_5_PADOUT
  3.850                        IO_5_PADOUT (r)
                                    
  3.850                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
                                    
  N/C                          IO_5_PADOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[3]:CLR
  Delay (ns):                  2.028
  Slack (ns):
  Arrival (ns):                3.777
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.063

Path 2
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[5]:CLR
  Delay (ns):                  2.046
  Slack (ns):
  Arrival (ns):                3.795
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.063

Path 3
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/I_H_SYNC:PRE
  Delay (ns):                  2.025
  Slack (ns):
  Arrival (ns):                3.774
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.042

Path 4
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[4]:CLR
  Delay (ns):                  2.046
  Slack (ns):
  Arrival (ns):                3.795
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.063

Path 5
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[6]:CLR
  Delay (ns):                  2.046
  Slack (ns):
  Arrival (ns):                3.795
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.063


Expanded Path 1
  From: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[3]:CLR
  data arrival time                              3.777
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.683          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.683                        CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  1.424                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.325          net: CLKINT_0_Y
  1.749                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK (r)
               +     0.248          cell: ADLIB:DFN1
  1.997                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:Q (r)
               +     0.145          net: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2
  2.142                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:B (r)
               +     0.252          cell: ADLIB:NOR2B
  2.394                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:Y (r)
               +     0.674          net: CoreTFTahbMaster_0/I_SWHW_N_RESET_SRC
  3.068                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:A (r)
               +     0.390          cell: ADLIB:CLKSRC
  3.458                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:Y (r)
               +     0.319          net: CoreTFTahbMaster_0/I_SWHW_N_RESET
  3.777                        CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[3]:CLR (r)
                                    
  3.777                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.683          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.388          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[3]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1E1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/V_CNT[3]:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

