Timing Report Max Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Fri Nov 23 18:09:55 2012


Design: Top_7TFT16Bit_WVGA_Controller
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                3.088
Frequency (MHz):            323.834
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        6.393
External Hold (ns):         -0.667
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                22.848
Frequency (MHz):            43.768
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        5.145
External Hold (ns):         -0.459
Min Clock-To-Out (ns):      3.690
Max Clock-To-Out (ns):      8.901

Clock Domain:               mss_ccc_glc
Period (ns):                1.845
Frequency (MHz):            542.005
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.662
Max Clock-To-Out (ns):      5.085

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
Period (ns):                1.905
Frequency (MHz):            524.934
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
Period (ns):                1.857
Frequency (MHz):            538.503
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.305
Max Clock-To-Out (ns):      8.494

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
Period (ns):                7.907
Frequency (MHz):            126.470
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.850
Max Clock-To-Out (ns):      11.794

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  Delay (ns):                  4.231
  Slack (ns):
  Arrival (ns):                4.231
  Required (ns):
  Setup (ns):                  -1.143
  Minimum Period (ns):         3.088


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  data required time                             N/C
  data arrival time                          -   4.231
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.773          cell: ADLIB:MSS_AHB_IP
  2.773                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.136          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  2.909                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.074          cell: ADLIB:MSS_IF
  2.983                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     0.489          net: CoreAHBLite_0_AHBmslave16_HREADY
  3.472                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6 (r)
               +     0.063          cell: ADLIB:MSS_IF
  3.535                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6INT (r)
               +     0.696          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYINT_NET
  4.231                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY (r)
                                    
  4.231                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               -    -1.143          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        PBUTTON[3]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[30]
  Delay (ns):                  6.043
  Slack (ns):
  Arrival (ns):                6.043
  Required (ns):
  Setup (ns):                  0.350
  External Setup (ns):         6.393

Path 2
  From:                        PBUTTON[4]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[31]
  Delay (ns):                  6.555
  Slack (ns):
  Arrival (ns):                6.555
  Required (ns):
  Setup (ns):                  -0.381
  External Setup (ns):         6.174

Path 3
  From:                        PBUTTON[0]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23]
  Delay (ns):                  5.972
  Slack (ns):
  Arrival (ns):                5.972
  Required (ns):
  Setup (ns):                  -0.378
  External Setup (ns):         5.594

Path 4
  From:                        PBUTTON[2]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[29]
  Delay (ns):                  5.733
  Slack (ns):
  Arrival (ns):                5.733
  Required (ns):
  Setup (ns):                  -0.304
  External Setup (ns):         5.429

Path 5
  From:                        PBUTTON[1]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  3.204
  Slack (ns):
  Arrival (ns):                3.204
  Required (ns):
  Setup (ns):                  -0.228
  External Setup (ns):         2.976


Expanded Path 1
  From: PBUTTON[3]
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[30]
  data required time                             N/C
  data arrival time                          -   6.043
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PBUTTON[3] (r)
               +     0.000          net: PBUTTON[3]
  0.000                        PBUTTON_pad[3]/U0/U0:PAD (r)
               +     0.779          cell: ADLIB:IOPAD_IN
  0.779                        PBUTTON_pad[3]/U0/U0:Y (r)
               +     0.000          net: PBUTTON_pad[3]/U0/NET1
  0.779                        PBUTTON_pad[3]/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.812                        PBUTTON_pad[3]/U0/U1:Y (r)
               +     4.974          net: PBUTTON_c[3]
  5.786                        MSS_new_top_0/MSS_ADLIB_INST/U_6:PIN6 (r)
               +     0.158          cell: ADLIB:MSS_IF
  5.944                        MSS_new_top_0/MSS_ADLIB_INST/U_6:PIN6INT (r)
               +     0.099          net: MSS_new_top_0/MSS_ADLIB_INST/GPI[30]INT_NET
  6.043                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[30] (r)
                                    
  6.043                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               -     0.350          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[30]


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -1.383


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_new_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.382          net: MSS_new_top_0/GLA0
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[14]/U1:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U1:D
  Delay (ns):                  10.877
  Slack (ns):
  Arrival (ns):                11.468
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         22.848

Path 2
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[2]/U1:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U1:D
  Delay (ns):                  10.853
  Slack (ns):
  Arrival (ns):                11.444
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         22.800

Path 3
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U1:D
  Delay (ns):                  10.736
  Slack (ns):
  Arrival (ns):                11.327
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         22.566

Path 4
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[14]/U1:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[0]/U1:D
  Delay (ns):                  10.687
  Slack (ns):
  Arrival (ns):                11.278
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         22.484

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[14]/U1:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[1]/U1:D
  Delay (ns):                  10.687
  Slack (ns):
  Arrival (ns):                11.278
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         22.458


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[14]/U1:CLK
  To: CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U1:D
  data required time                             N/C
  data arrival time                          -   11.468
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.591          net: FAB_CLK
  0.591                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[14]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.150                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[14]/U1:Q (f)
               +     1.628          net: CoreAHBLite_0/matrix2x16/masterstage_0/xhdl1222[14]
  2.778                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIS1BV[12]:A (f)
               +     0.385          cell: ADLIB:OR2
  3.163                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIS1BV[12]:Y (f)
               +     0.727          net: CoreAHBLite_0/matrix2x16/masterstage_0/hready_m_xhdl392_7
  3.890                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIQBMU1[15]:A (f)
               +     0.407          cell: ADLIB:NOR2
  4.297                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIQBMU1[15]:Y (r)
               +     0.308          net: CoreAHBLite_0/matrix2x16/masterstage_0/hready_m_xhdl396_12
  4.605                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIR8CE2[16]:B (r)
               +     0.392          cell: ADLIB:OR2B
  4.997                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIR8CE2[16]:Y (f)
               +     0.337          net: CoreAHBLite_0_matrix2x16_masterstage_0_hready_m_xhdl395_0_a3_0
  5.334                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI0T775[16]:C (f)
               +     0.570          cell: ADLIB:NOR3
  5.904                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI0T775[16]:Y (r)
               +     0.959          net: CoreAHBLite_0_matrix2x16_masterstage_0_hready_m_xhdl395_0
  6.863                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI8CIE5[16]:B (r)
               +     0.473          cell: ADLIB:OR3B
  7.336                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI8CIE5[16]:Y (f)
               +     0.360          net: CoreAHBLite_0_matrix2x16_masterstage_0_N_1024
  7.696                        CoreTFTahbMaster_0/MemCntlState_RNIHNL3C[0]:C (f)
               +     0.517          cell: ADLIB:NOR3C
  8.213                        CoreTFTahbMaster_0/MemCntlState_RNIHNL3C[0]:Y (f)
               +     0.294          net: CoreTFTahbMaster_0/un3_valid_0_a3_m6_0_a2_2_1
  8.507                        CoreTFTahbMaster_0/MemCntlState_RNI7KTED1_0[0]:C (f)
               +     0.486          cell: ADLIB:NOR3C
  8.993                        CoreTFTahbMaster_0/MemCntlState_RNI7KTED1_0[0]:Y (f)
               +     1.844          net: CoreTFTahbMaster_0/N_613_0
  10.837                       CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U0:S (f)
               +     0.364          cell: ADLIB:MX2
  11.201                       CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U0:Y (r)
               +     0.267          net: CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/Y
  11.468                       CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U1:D (r)
                                    
  11.468                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (f)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (f)
               +     0.584          net: FAB_CLK
  N/C                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U1:CLK (f)
               -     0.540          Library setup time: ADLIB:DFN0C0
  N/C                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[14]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        PBUTTON[3]
  To:                          CoreGPIO_0/CGPIOiOI.7.CGPIOI1[7]:D
  Delay (ns):                  5.311
  Slack (ns):
  Arrival (ns):                5.311
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         5.145

Path 2
  From:                        PBUTTON[0]
  To:                          CoreGPIO_0/CGPIOiOI.4.CGPIOI1[4]:D
  Delay (ns):                  4.725
  Slack (ns):
  Arrival (ns):                4.725
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         4.561

Path 3
  From:                        PBUTTON[2]
  To:                          CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D
  Delay (ns):                  4.231
  Slack (ns):
  Arrival (ns):                4.231
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         4.035

Path 4
  From:                        PBUTTON[4]
  To:                          CoreGPIO_0/CGPIOiOI.8.CGPIOI1[8]:D
  Delay (ns):                  3.993
  Slack (ns):
  Arrival (ns):                3.993
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         3.853

Path 5
  From:                        DIP_SWITCH[3]
  To:                          CoreGPIO_0/CGPIOiOI.3.CGPIOI1[3]:D
  Delay (ns):                  2.447
  Slack (ns):
  Arrival (ns):                2.447
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         2.356


Expanded Path 1
  From: PBUTTON[3]
  To: CoreGPIO_0/CGPIOiOI.7.CGPIOI1[7]:D
  data required time                             N/C
  data arrival time                          -   5.311
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PBUTTON[3] (r)
               +     0.000          net: PBUTTON[3]
  0.000                        PBUTTON_pad[3]/U0/U0:PAD (r)
               +     0.779          cell: ADLIB:IOPAD_IN
  0.779                        PBUTTON_pad[3]/U0/U0:Y (r)
               +     0.000          net: PBUTTON_pad[3]/U0/NET1
  0.779                        PBUTTON_pad[3]/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.812                        PBUTTON_pad[3]/U0/U1:Y (r)
               +     4.499          net: PBUTTON_c[3]
  5.311                        CoreGPIO_0/CGPIOiOI.7.CGPIOI1[7]:D (r)
                                    
  5.311                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.601          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOiOI.7.CGPIOI1[7]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOiOI.7.CGPIOI1[7]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreGPIO_0/CGPIOiOI.1.CGPIOI1I.CGPIOo0[1]/U1:CLK
  To:                          LED[1]
  Delay (ns):                  8.311
  Slack (ns):
  Arrival (ns):                8.901
  Required (ns):
  Clock to Out (ns):           8.901

Path 2
  From:                        CoreGPIO_0/CGPIOiOI.3.CGPIOI1I.CGPIOo0[3]/U1:CLK
  To:                          LED[3]
  Delay (ns):                  8.037
  Slack (ns):
  Arrival (ns):                8.621
  Required (ns):
  Clock to Out (ns):           8.621

Path 3
  From:                        CoreGPIO_0/CGPIOiOI.0.CGPIOI1I.CGPIOo0[0]/U1:CLK
  To:                          LED[0]
  Delay (ns):                  7.616
  Slack (ns):
  Arrival (ns):                8.206
  Required (ns):
  Clock to Out (ns):           8.206

Path 4
  From:                        CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]/U1:CLK
  To:                          LED[2]
  Delay (ns):                  7.609
  Slack (ns):
  Arrival (ns):                8.199
  Required (ns):
  Clock to Out (ns):           8.199

Path 5
  From:                        CoreGPIO_0/CGPIOOI_3[0]/U1:CLK
  To:                          LED[3]
  Delay (ns):                  7.513
  Slack (ns):
  Arrival (ns):                8.066
  Required (ns):
  Clock to Out (ns):           8.066


Expanded Path 1
  From: CoreGPIO_0/CGPIOiOI.1.CGPIOI1I.CGPIOo0[1]/U1:CLK
  To: LED[1]
  data required time                             N/C
  data arrival time                          -   8.901
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.590          net: FAB_CLK
  0.590                        CoreGPIO_0/CGPIOiOI.1.CGPIOI1I.CGPIOo0[1]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.149                        CoreGPIO_0/CGPIOiOI.1.CGPIOI1I.CGPIOo0[1]/U1:Q (f)
               +     1.388          net: CoreGPIO_0/CGPIOo0[1]
  2.537                        CoreGPIO_0/CGPIOOI_1_RNIRPLH[0]:A (f)
               +     0.390          cell: ADLIB:NOR2B
  2.927                        CoreGPIO_0/CGPIOOI_1_RNIRPLH[0]:Y (f)
               +     2.724          net: CoreGPIO_0_N_727
  5.651                        LED_pad[1]/U0/U1:D (f)
               +     0.442          cell: ADLIB:IOTRI_OB_EB
  6.093                        LED_pad[1]/U0/U1:DOUT (f)
               +     0.000          net: LED_pad[1]/U0/NET1
  6.093                        LED_pad[1]/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  8.901                        LED_pad[1]/U0/U0:PAD (f)
               +     0.000          net: LED[1]
  8.901                        LED[1] (f)
                                    
  8.901                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          LED[1] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  3.644
  Slack (ns):
  Arrival (ns):                4.271
  Required (ns):
  Recovery (ns):               1.523
  Minimum Period (ns):         5.110
  Skew (ns):                   -0.057

Path 2
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  3.546
  Slack (ns):
  Arrival (ns):                4.138
  Required (ns):
  Recovery (ns):               1.523
  Minimum Period (ns):         4.977
  Skew (ns):                   -0.092

Path 3
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  3.127
  Slack (ns):
  Arrival (ns):                3.754
  Required (ns):
  Recovery (ns):               1.523
  Minimum Period (ns):         4.592
  Skew (ns):                   -0.058

Path 4
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  3.029
  Slack (ns):
  Arrival (ns):                3.621
  Required (ns):
  Recovery (ns):               1.523
  Minimum Period (ns):         4.459
  Skew (ns):                   -0.093


Expanded Path 1
  From: CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  data required time                             N/C
  data arrival time                          -   4.271
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.627          net: FAB_CLK
  0.627                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  1.067                        CoreTFTahbMaster_0/CTRL_REG[6]:Q (r)
               +     0.971          net: CoreTFTahbMaster_0/CTRL_REG[6]
  2.038                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:A (r)
               +     0.392          cell: ADLIB:NOR2A
  2.430                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:Y (r)
               +     1.841          net: CoreTFTahbMaster_0/OUTF_PULSE_RNITR1U
  4.271                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET (r)
                                    
  4.271                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.684          net: FAB_CLK
  N/C                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:WCLK (r)
               -     1.523          Library recovery time: ADLIB:FIFO4K18
  N/C                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  Delay (ns):                  1.436
  Slack (ns):
  Arrival (ns):                1.966
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         1.845


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  data required time                             N/C
  data arrival time                          -   1.966
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.530          net: MAC_CLK_c
  0.530                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.089                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (f)
               +     0.237          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  1.326                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:A (f)
               +     0.385          cell: ADLIB:INV
  1.711                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:Y (r)
               +     0.255          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[0]
  1.966                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D (r)
                                    
  1.966                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.530          net: MAC_CLK_c
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          MAC_CLK
  Delay (ns):                  5.085
  Slack (ns):
  Arrival (ns):                5.085
  Required (ns):
  Clock to Out (ns):           5.085


Expanded Path 1
  From: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: MAC_CLK
  data required time                             N/C
  data arrival time                          -   5.085
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     1.246          cell: ADLIB:MSS_CCC_IP
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (f)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (f)
               +     0.531          net: MAC_CLK_c
  1.777                        MAC_CLK_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  2.277                        MAC_CLK_pad/U0/U1:DOUT (f)
               +     0.000          net: MAC_CLK_pad/U0/NET1
  2.277                        MAC_CLK_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  5.085                        MAC_CLK_pad/U0/U0:PAD (f)
               +     0.000          net: MAC_CLK
  5.085                        MAC_CLK (f)
                                    
  5.085                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          MAC_CLK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  Delay (ns):                  1.496
  Slack (ns):
  Arrival (ns):                2.400
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         1.905


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  data required time                             N/C
  data arrival time                          -   2.400
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.904          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  0.904                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.463                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (f)
               +     0.290          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  1.753                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:A (f)
               +     0.385          cell: ADLIB:INV
  2.138                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:Y (r)
               +     0.262          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[1]
  2.400                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D (r)
                                    
  2.400                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.904          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  Delay (ns):                  1.448
  Slack (ns):
  Arrival (ns):                1.767
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         1.857


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  data required time                             N/C
  data arrival time                          -   1.767
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.319          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.319                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  0.878                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (f)
               +     0.242          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.120                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:A (f)
               +     0.385          cell: ADLIB:INV
  1.505                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:Y (r)
               +     0.262          net: TOGGLE_DIV_0/TOGGLE_DIV_0_DIVREG_OUT2to2_i_i
  1.767                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D (r)
                                    
  1.767                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.319          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          IO_2_PADOUT
  Delay (ns):                  8.175
  Slack (ns):
  Arrival (ns):                8.494
  Required (ns):
  Clock to Out (ns):           8.494


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: IO_2_PADOUT
  data required time                             N/C
  data arrival time                          -   8.494
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.319          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.319                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  0.878                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (f)
               +     1.110          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.988                        CLKINT_0/U_CLKSRC:A (f)
               +     1.316          cell: ADLIB:CLKSRC
  3.304                        CLKINT_0/U_CLKSRC:Y (f)
               +     0.585          net: CLKINT_0_Y
  3.889                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:B (f)
               +     0.476          cell: ADLIB:NOR2B
  4.365                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:Y (f)
               +     0.633          net: CoreTFTahbMaster_0_RGB_CLK
  4.998                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5 (f)
               +     0.158          cell: ADLIB:MSS_IF
  5.156                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5INT (f)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_2/U0/D_INT
  5.156                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:D (f)
               +     3.338          cell: ADLIB:IOPAD_TRI
  8.494                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:PAD (f)
               +     0.000          net: IO_2_PADOUT
  8.494                        IO_2_PADOUT (f)
                                    
  8.494                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
                                    
  N/C                          IO_2_PADOUT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q

SET Register to Register

Path 1
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[3]:D
  Delay (ns):                  7.227
  Slack (ns):
  Arrival (ns):                10.490
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.907

Path 2
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_G[2]:D
  Delay (ns):                  6.761
  Slack (ns):
  Arrival (ns):                10.024
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         7.401

Path 3
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RCLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:REN
  Delay (ns):                  5.967
  Slack (ns):
  Arrival (ns):                9.229
  Required (ns):
  Setup (ns):                  1.397
  Minimum Period (ns):         7.363

Path 4
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:REN
  Delay (ns):                  5.912
  Slack (ns):
  Arrival (ns):                9.175
  Required (ns):
  Setup (ns):                  1.397
  Minimum Period (ns):         7.309

Path 5
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RCLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_G[5]:D
  Delay (ns):                  6.559
  Slack (ns):
  Arrival (ns):                9.821
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         7.192


Expanded Path 1
  From: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To: CoreTFTahbMaster_0/LCDCTRL/VGA_B[3]:D
  data required time                             N/C
  data arrival time                          -   10.490
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     1.164          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.164                        CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  2.479                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.784          net: CLKINT_0_Y
  3.263                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK (r)
               +     2.198          cell: ADLIB:FIFO4K18
  5.461                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RD3 (r)
               +     1.387          net: CoreTFTahbMaster_0/I_FIFO_RD_DATA[3]
  6.848                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO_0[3]:B (r)
               +     0.514          cell: ADLIB:MX2C
  7.362                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO_0[3]:Y (f)
               +     1.566          net: CoreTFTahbMaster_0/LCDCTRL/I_RAM_RD_DATA_MUX[3]
  8.928                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO[3]:B (f)
               +     0.370          cell: ADLIB:NOR2A
  9.298                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO[3]:Y (r)
               +     1.192          net: CoreTFTahbMaster_0/LCDCTRL/VGA_B_3[3]
  10.490                       CoreTFTahbMaster_0/LCDCTRL/VGA_B[3]:D (r)
                                    
  10.490                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     1.164          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.539          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[3]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[3]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To:                          B_DATA1
  Delay (ns):                  8.763
  Slack (ns):
  Arrival (ns):                11.794
  Required (ns):
  Clock to Out (ns):           11.794

Path 2
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:CLK
  To:                          B_DATA3
  Delay (ns):                  8.016
  Slack (ns):
  Arrival (ns):                11.045
  Required (ns):
  Clock to Out (ns):           11.045

Path 3
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To:                          B_DATA0
  Delay (ns):                  7.313
  Slack (ns):
  Arrival (ns):                10.344
  Required (ns):
  Clock to Out (ns):           10.344

Path 4
  From:                        CoreTFTahbMaster_0/LCDCTRL/DATA_START:CLK
  To:                          TFT_PWR_EN
  Delay (ns):                  6.952
  Slack (ns):
  Arrival (ns):                9.976
  Required (ns):
  Clock to Out (ns):           9.976

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/DATA_START:CLK
  To:                          IO_2_PADOUT
  Delay (ns):                  6.855
  Slack (ns):
  Arrival (ns):                9.879
  Required (ns):
  Clock to Out (ns):           9.879


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To: B_DATA1
  data required time                             N/C
  data arrival time                          -   11.794
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     1.164          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.164                        CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  2.479                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.552          net: CLKINT_0_Y
  3.031                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  3.590                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:Q (f)
               +     3.940          net: B_DATA1_c_c
  7.530                        B_DATA1_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  8.030                        B_DATA1_pad/U0/U1:DOUT (f)
               +     0.000          net: B_DATA1_pad/U0/NET1
  8.030                        B_DATA1_pad/U0/U0:D (f)
               +     3.764          cell: ADLIB:IOPAD_TRI
  11.794                       B_DATA1_pad/U0/U0:PAD (f)
               +     0.000          net: B_DATA1
  11.794                       B_DATA1 (f)
                                    
  11.794                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
                                    
  N/C                          B_DATA1 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_CNT[7]:CLR
  Delay (ns):                  3.547
  Slack (ns):
  Arrival (ns):                6.581
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.770
  Skew (ns):                   -0.002

Path 2
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_CNT[9]:CLR
  Delay (ns):                  3.580
  Slack (ns):
  Arrival (ns):                6.614
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.768
  Skew (ns):                   -0.037

Path 3
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/DATA_START:CLR
  Delay (ns):                  3.530
  Slack (ns):
  Arrival (ns):                6.564
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.765
  Skew (ns):                   0.010

Path 4
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_CNT[2]:CLR
  Delay (ns):                  3.551
  Slack (ns):
  Arrival (ns):                6.585
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.755
  Skew (ns):                   -0.021

Path 5
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_CNT[1]:CLR
  Delay (ns):                  3.551
  Slack (ns):
  Arrival (ns):                6.585
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.755
  Skew (ns):                   -0.021


Expanded Path 1
  From: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_CNT[7]:CLR
  data required time                             N/C
  data arrival time                          -   6.581
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     1.164          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.164                        CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  2.479                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.555          net: CLKINT_0_Y
  3.034                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK (r)
               +     0.440          cell: ADLIB:DFN1
  3.474                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:Q (r)
               +     0.247          net: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2
  3.721                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:B (r)
               +     0.448          cell: ADLIB:NOR2B
  4.169                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:Y (r)
               +     1.147          net: CoreTFTahbMaster_0/I_SWHW_N_RESET_SRC
  5.316                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:A (r)
               +     0.691          cell: ADLIB:CLKSRC
  6.007                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:Y (r)
               +     0.574          net: CoreTFTahbMaster_0/I_SWHW_N_RESET
  6.581                        CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_CNT[7]:CLR (r)
                                    
  6.581                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     1.164          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.557          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_CNT[7]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_VGA.VGA_TIMING0/H_CNT[7]:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

