@W: MT532 :"c:\five_work_stp\hdl\toggle_div.vhd":69:15:69:25|Found signal identified as System clock which controls 58 sequential elements including TOGGLE_DIV_0/DIVREG_GEN3TOGGLEDIV_REGI_DIVREG[3].  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
