@W: MT462 :"c:\five_work_stp\component\work\mss_new_top\mss_ccc_0\mss_new_top_tmp_mss_ccc_0_mss_ccc.vhd":116:4:116:11|Net MAC_CLK appears to be an unidentified clock source. Assuming default frequency. 
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHSIZE[2] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHSIZE[1] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[0] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:9|Register bit SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHSIZE[2] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[31] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[30] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[29] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[28] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[27] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[26] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[25] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[24] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[23] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[22] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[21] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":276:8:276:9|Register bit regHADDR[20] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:9|Register bit SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_slavearbiter.vhd":118:12:118:27|Register bit arbRegSMCurrentState[6] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_slavearbiter.vhd":125:12:125:27|Register bit arbRegSMCurrentState[5] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:9|Register bit SDATASELInt[16] is always 0, optimizing ...
@W: MO160 :"c:\five_work_stp\component\actel\directcore\coreahblite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd":356:8:356:9|Register bit RESERVEDDATASELInt is always 0, optimizing ...
@W: BN132 :"c:\five_work_stp\component\actel\directcore\coreahbtoapb3\2.0.116\rtl\vhdl\core_obfuscated\ahbtoapbsm.vhd":214:0:214:1|Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3LL0.PWRITE,  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3LL0.CAHBtoAPB3iol[2]
@W: BN132 :"c:\five_work_stp\component\actel\directcore\coreahbtoapb3\2.0.116\rtl\vhdl\core_obfuscated\penablescheduler.vhd":84:0:84:1|Removing sequential instance COREAHBTOAPB3_0.CAHBTOAPB3il0.PENABLE,  because it is equivalent to instance COREAHBTOAPB3_0.CAHBTOAPB3il0.CAHBtoAPB3III[1]
@W: MT246 :"c:\five_work_stp\component\work\mss_new_top\mss_new_top.vhd":2454:0:2454:12|Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\five_work_stp\component\work\mss_new_top\mss_new_top.vhd":2322:0:2322:11|Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\five_work_stp\component\work\mss_new_top\mss_ccc_0\mss_new_top_tmp_mss_ccc_0_mss_ccc.vhd":154:4:154:11|Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock TOGGLE_DIV|TOGGLE_DIV_0_DIVREG_OUT2to2_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:TOGGLE_DIV_0_DIVREG_OUT2to2"
@W: MT420 |Found inferred clock TOGGLE_DIV|un1_TOGGLE_DIV_0_1_inferred_clock[1] with period 10.00ns. Please declare a user-defined clock on object "n:un1_TOGGLE_DIV_0_1[1]"
@W: MT420 |Found inferred clock TOGGLE_DIV|un1_TOGGLE_DIV_0_1_inferred_clock[0] with period 10.00ns. Please declare a user-defined clock on object "n:un1_TOGGLE_DIV_0_1[0]"
