#--  Synopsys, Inc.
#--  Version F-2012.03M-SP1 
#--  Project file C:\Five_work_stp\synthesis\run_options.txt
#--  Written on Fri Nov 23 18:01:29 2012


#project files
add_file -vhdl -lib work "C:/Five_work_stp/hdl/toggle_div.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/component/Actel/SmartFusionMSS/MSS/2.5.106/mss_comps.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/component/work/MSS_new_top/mss_tshell.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/component/work/MSS_new_top/MSS_CCC_0/MSS_new_top_tmp_MSS_CCC_0_MSS_CCC.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/component/work/MSS_new_top/MSS_new_top.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/res_ctrl.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/fifo1024x32.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/fifo1kx32.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/smartgen/fifo_512x16high/fifo_512x16high.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/qvga55_timing_LUCA.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/vga7_timing_LUCA.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/qvgatest_timing_LUCA.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/top_timing_LUCA.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/pulses2f_rf.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/sync_level.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/hdl/CoreTFTahbMasterAdvQVGA.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_addrdec.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_defaultslavesm.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_masterstage.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_slavearbiter.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_slavestage.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_initcfg_awrap.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_initcfg.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_matrix2x16.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite.vhd"
add_file -vhdl -lib COREAHBTOAPB3_LIB "C:/Five_work_stp/component/Actel/DirectCore/COREAHBTOAPB3/2.0.116/rtl/vhdl/core_obfuscated/ahbtoapbsm.vhd"
add_file -vhdl -lib COREAHBTOAPB3_LIB "C:/Five_work_stp/component/Actel/DirectCore/COREAHBTOAPB3/2.0.116/rtl/vhdl/core_obfuscated/penablescheduler.vhd"
add_file -vhdl -lib COREAHBTOAPB3_LIB "C:/Five_work_stp/component/Actel/DirectCore/COREAHBTOAPB3/2.0.116/rtl/vhdl/core_obfuscated/apbaddrdata.vhd"
add_file -vhdl -lib COREAHBTOAPB3_LIB "C:/Five_work_stp/component/Actel/DirectCore/COREAHBTOAPB3/2.0.116/rtl/vhdl/core_obfuscated/coreahbtoapb3.vhd"
add_file -vhdl -lib COREAPB3_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vhdl/core_obfuscated/coreapb3_muxptob3.vhd"
add_file -vhdl -lib COREAPB3_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vhdl/core_obfuscated/coreapb3.vhd"
add_file -vhdl -lib COREGPIO_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core_obfuscated/coregpio_pkg.vhd"
add_file -vhdl -lib COREGPIO_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core_obfuscated/coregpio.vhd"
add_file -vhdl -lib COREAPB3_LIB "C:/Five_work_stp/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vhdl/core_obfuscated/components.vhd"
add_file -vhdl -lib COREAHBTOAPB3_LIB "C:/Five_work_stp/component/Actel/DirectCore/COREAHBTOAPB3/2.0.116/rtl/vhdl/core_obfuscated/components.vhd"
add_file -vhdl -lib work "C:/Five_work_stp/component/work/Top_55TFT16bit_QVGA_Controller/Top_55TFT16bit_QVGA_Controller.vhd"
add_file -constraint "C:/Five_work_stp/component/work/MSS_new_top/mss_tshell_syn.sdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology SmartFusion
set_option -part A2F500M3G
set_option -package FBGA484
set_option -speed_grade Std
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.Top_55TFT16bit_QVGA_Controller"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./Top_55TFT16bit_QVGA_Controller.edn"
impl -active "synthesis"
