Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Jan 25 14:33:20 2012


Design: Top_55TFT32bit_QVGA_EthMAC
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       26.666
Required Frequency (MHz):   37.501
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.001
Frequency (MHz):            124.984
Required Period (ns):       26.666
Required Frequency (MHz):   37.501
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       26.666
Required Frequency (MHz):   37.501
External Setup (ns):        2.331
External Hold (ns):         2.242
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       13.333
Required Frequency (MHz):   75.002
External Setup (ns):        -4.928
External Hold (ns):         4.007
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                19.373
Frequency (MHz):            51.618
Required Period (ns):       26.667
Required Frequency (MHz):   37.500
External Setup (ns):        -0.792
External Hold (ns):         3.227
Min Clock-To-Out (ns):      7.240
Max Clock-To-Out (ns):      13.487

Clock Domain:               mss_ccc_glc
Period (ns):                1.845
Frequency (MHz):            542.005
Required Period (ns):       20.000
Required Frequency (MHz):   50.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       20.000
Required Frequency (MHz):   50.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.662
Max Clock-To-Out (ns):      5.085

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
Period (ns):                1.888
Frequency (MHz):            529.661
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
Period (ns):                1.843
Frequency (MHz):            542.594
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.239
Max Clock-To-Out (ns):      8.421

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
Period (ns):                9.393
Frequency (MHz):            106.462
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.672
Max Clock-To-Out (ns):      10.907

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  Delay (ns):                  2.391
  Slack (ns):                  1.368
  Arrival (ns):                5.340
  Required (ns):               3.972
  Hold (ns):                   1.023

Path 2
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  5.109
  Slack (ns):                  4.032
  Arrival (ns):                8.058
  Required (ns):               4.026
  Hold (ns):                   1.077


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  data arrival time                              5.340
  data required time                         -   3.972
  slack                                          1.368
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.562          cell: ADLIB:MSS_AHB_IP
  4.511                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.080          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  4.591                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  4.632                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     0.263          net: CoreAHBLite_0_AHBmslave16_HREADY
  4.895                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6 (r)
               +     0.036          cell: ADLIB:MSS_IF
  4.931                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6INT (r)
               +     0.409          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYINT_NET
  5.340                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY (r)
                                    
  5.340                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.023          Library hold time: ADLIB:MSS_AHB_IP
  3.972                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
                                    
  3.972                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_glb to mss_fabric_interface_clock

Path 1
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[16]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  1.281
  Slack (ns):                  1.285
  Arrival (ns):                5.311
  Required (ns):               4.026
  Hold (ns):                   1.077

Path 2
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[9]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSHRDATA[9]
  Delay (ns):                  1.634
  Slack (ns):                  1.374
  Arrival (ns):                5.655
  Required (ns):               4.281
  Hold (ns):                   1.332

Path 3
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[15]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSHRDATA[15]
  Delay (ns):                  1.652
  Slack (ns):                  1.418
  Arrival (ns):                5.699
  Required (ns):               4.281
  Hold (ns):                   1.332

Path 4
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[31]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSHRDATA[31]
  Delay (ns):                  1.716
  Slack (ns):                  1.478
  Arrival (ns):                5.740
  Required (ns):               4.262
  Hold (ns):                   1.313

Path 5
  From:                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[0]
  Delay (ns):                  1.731
  Slack (ns):                  1.522
  Arrival (ns):                5.771
  Required (ns):               4.249
  Hold (ns):                   1.300


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[16]/U1:CLK
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  data arrival time                              5.311
  data required time                         -   4.026
  slack                                          1.285
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.343          net: FAB_CLK
  4.030                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[16]/U1:CLK (r)
               +     0.319          cell: ADLIB:DFN1C0
  4.349                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[16]/U1:Q (f)
               +     0.174          net: CoreAHBLite_0/matrix2x16/xhdl1222[16]
  4.523                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0_RNIAM2JQ1[0]:B (f)
               +     0.317          cell: ADLIB:OA1B
  4.840                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0_RNIAM2JQ1[0]:Y (f)
               +     0.426          net: arbRegSMCurrentState_0_RNIAM2JQ1[0]
  5.266                        MSS_new_top_0/MSS_ADLIB_INST/U_60:PIN4 (f)
               +     0.045          cell: ADLIB:MSS_IF
  5.311                        MSS_new_top_0/MSS_ADLIB_INST/U_60:PIN4INT (f)
               +     0.000          net: MSS_new_top_0/MSS_ADLIB_INST/FABHTRANS1INT_NET
  5.311                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1 (f)
                                    
  5.311                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.077          Library hold time: ADLIB:MSS_AHB_IP
  4.026                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
                                    
  4.026                        data required time


END SET mss_ccc_glb to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        SDCARD_CD
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]
  Delay (ns):                  1.061
  Slack (ns):
  Arrival (ns):                1.061
  Required (ns):
  Hold (ns):                   0.354
  External Hold (ns):          2.242

Path 2
  From:                        SDCARD_WP
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[21]
  Delay (ns):                  1.159
  Slack (ns):
  Arrival (ns):                1.159
  Required (ns):
  Hold (ns):                   0.150
  External Hold (ns):          1.940

Path 3
  From:                        PBUTTON[1]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  1.806
  Slack (ns):
  Arrival (ns):                1.806
  Required (ns):
  Hold (ns):                   0.354
  External Hold (ns):          1.497

Path 4
  From:                        PBUTTON[2]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[29]
  Delay (ns):                  3.524
  Slack (ns):
  Arrival (ns):                3.524
  Required (ns):
  Hold (ns):                   0.432
  External Hold (ns):          -0.143

Path 5
  From:                        PBUTTON[3]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[30]
  Delay (ns):                  3.249
  Slack (ns):
  Arrival (ns):                3.249
  Required (ns):
  Hold (ns):                   0.095
  External Hold (ns):          -0.205


Expanded Path 1
  From: SDCARD_CD
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]
  data arrival time                              1.061
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SDCARD_CD (f)
               +     0.000          net: SDCARD_CD
  0.000                        SDCARD_CD_pad/U0/U0:PAD (f)
               +     0.292          cell: ADLIB:IOPAD_IN
  0.292                        SDCARD_CD_pad/U0/U0:Y (f)
               +     0.000          net: SDCARD_CD_pad/U0/NET1
  0.292                        SDCARD_CD_pad/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.310                        SDCARD_CD_pad/U0/U1:Y (f)
               +     0.583          net: SDCARD_CD_c
  0.893                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN5 (f)
               +     0.090          cell: ADLIB:MSS_IF
  0.983                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN5INT (f)
               +     0.078          net: MSS_new_top_0/MSS_ADLIB_INST/GPI[22]INT_NET
  1.061                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22] (f)
                                    
  1.061                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  N/C
               +     0.354          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          4.007


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MSS_new_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.270          net: MSS_new_top_0/GLA0
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_glb to mss_ccc_gla0

Path 1
  From:                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[25]
  Delay (ns):                  1.450
  Slack (ns):                  1.225
  Arrival (ns):                5.490
  Required (ns):               4.265
  Hold (ns):                   1.271

Path 2
  From:                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0[0]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[7]
  Delay (ns):                  1.634
  Slack (ns):                  1.378
  Arrival (ns):                5.667
  Required (ns):               4.289
  Hold (ns):                   1.295

Path 3
  From:                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0[0]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[4]
  Delay (ns):                  1.658
  Slack (ns):                  1.401
  Arrival (ns):                5.691
  Required (ns):               4.290
  Hold (ns):                   1.296

Path 4
  From:                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[19]
  Delay (ns):                  1.640
  Slack (ns):                  1.420
  Arrival (ns):                5.680
  Required (ns):               4.260
  Hold (ns):                   1.266

Path 5
  From:                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[22]
  Delay (ns):                  1.647
  Slack (ns):                  1.427
  Arrival (ns):                5.687
  Required (ns):               4.260
  Hold (ns):                   1.266


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[25]
  data arrival time                              5.490
  data required time                         -   4.265
  slack                                          1.225
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.353          net: FAB_CLK
  4.040                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.288                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:Q (r)
               +     0.223          net: CoreAHBLite_0/matrix2x16/slavestage_16/masterAddrInProg[1]
  4.511                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNI96B26[0]:B (r)
               +     0.156          cell: ADLIB:NOR3A
  4.667                        CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNI96B26[0]:Y (f)
               +     0.538          net: _CoreAHBLite_0_AHBmslave16_HADDR_[25]_
  5.205                        MSS_new_top_0/MSS_ADLIB_INST/U_45:PIN4 (f)
               +     0.045          cell: ADLIB:MSS_IF
  5.250                        MSS_new_top_0/MSS_ADLIB_INST/U_45:PIN4INT (f)
               +     0.240          net: MSS_new_top_0/MSS_ADLIB_INST/FABHADDR[25]INT_NET
  5.490                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[25] (f)
                                    
  5.490                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.270          net: MSS_new_top_0/GLA0
  2.994                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.271          Library hold time: ADLIB:MSS_AHB_IP
  4.265                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[25]
                                    
  4.265                        data required time


END SET mss_ccc_glb to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        CoreGPIO_0/CGPIOiOI.23.CGPIOI1[23]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.23.CGPIOOOL[23]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.367
  Arrival (ns):                4.403
  Required (ns):               4.036
  Hold (ns):                   0.000

Path 2
  From:                        CoreGPIO_0/CGPIOiOI.13.CGPIOI1[13]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.13.CGPIOOOL[13]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.368
  Arrival (ns):                4.414
  Required (ns):               4.046
  Hold (ns):                   0.000

Path 3
  From:                        CoreGPIO_0/CGPIOiOI.8.CGPIOI1[8]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.8.CGPIOOOL[8]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.373
  Arrival (ns):                4.422
  Required (ns):               4.049
  Hold (ns):                   0.000

Path 4
  From:                        CoreGPIO_0/CGPIOiOI.15.CGPIOI1[15]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.15.CGPIOOOL[15]:D
  Delay (ns):                  0.411
  Slack (ns):                  0.373
  Arrival (ns):                4.450
  Required (ns):               4.077
  Hold (ns):                   0.000

Path 5
  From:                        CoreGPIO_0/CGPIOiOI.10.CGPIOI1[10]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.10.CGPIOOOL[10]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.375
  Arrival (ns):                4.438
  Required (ns):               4.063
  Hold (ns):                   0.000


Expanded Path 1
  From: CoreGPIO_0/CGPIOiOI.23.CGPIOI1[23]:CLK
  To: CoreGPIO_0/CGPIOiOI.23.CGPIOOOL[23]:D
  data arrival time                              4.403
  data required time                         -   4.036
  slack                                          0.367
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.319          net: FAB_CLK
  4.006                        CoreGPIO_0/CGPIOiOI.23.CGPIOI1[23]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.254                        CoreGPIO_0/CGPIOiOI.23.CGPIOI1[23]:Q (r)
               +     0.149          net: CoreGPIO_0/CGPIOI1[23]
  4.403                        CoreGPIO_0/CGPIOiOI.23.CGPIOOOL[23]:D (r)
                                    
  4.403                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.349          net: FAB_CLK
  4.036                        CoreGPIO_0/CGPIOiOI.23.CGPIOOOL[23]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.036                        CoreGPIO_0/CGPIOiOI.23.CGPIOOOL[23]:D
                                    
  4.036                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        DIP_SWITCH[0]
  To:                          CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D
  Delay (ns):                  0.848
  Slack (ns):
  Arrival (ns):                0.848
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          3.227

Path 2
  From:                        DIP_SWITCH[3]
  To:                          CoreGPIO_0/CGPIOiOI.3.CGPIOI1[3]:D
  Delay (ns):                  0.844
  Slack (ns):
  Arrival (ns):                0.844
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          3.214

Path 3
  From:                        PBUTTON[1]
  To:                          CoreGPIO_0/CGPIOiOI.5.CGPIOI1[5]:D
  Delay (ns):                  0.995
  Slack (ns):
  Arrival (ns):                0.995
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          3.098

Path 4
  From:                        DIP_SWITCH[1]
  To:                          CoreGPIO_0/CGPIOiOI.1.CGPIOI1[1]:D
  Delay (ns):                  1.256
  Slack (ns):
  Arrival (ns):                1.256
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          2.805

Path 5
  From:                        DIP_SWITCH[2]
  To:                          CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D
  Delay (ns):                  1.306
  Slack (ns):
  Arrival (ns):                1.306
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          2.765


Expanded Path 1
  From: DIP_SWITCH[0]
  To: CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D
  data arrival time                              0.848
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        DIP_SWITCH[0] (f)
               +     0.000          net: DIP_SWITCH[0]
  0.000                        DIP_SWITCH_pad[0]/U0/U0:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        DIP_SWITCH_pad[0]/U0/U0:Y (f)
               +     0.000          net: DIP_SWITCH_pad[0]/U0/NET1
  0.276                        DIP_SWITCH_pad[0]/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.294                        DIP_SWITCH_pad[0]/U0/U1:Y (f)
               +     0.554          net: DIP_SWITCH_c[0]
  0.848                        CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D (f)
                                    
  0.848                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  N/C
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.388          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreGPIO_0/CGPIOOI_2[0]/U1:CLK
  To:                          LED[2]
  Delay (ns):                  3.245
  Slack (ns):
  Arrival (ns):                7.240
  Required (ns):
  Clock to Out (ns):           7.240

Path 2
  From:                        CoreGPIO_0/CGPIOOI_1[0]/U1:CLK
  To:                          LED[1]
  Delay (ns):                  3.267
  Slack (ns):
  Arrival (ns):                7.262
  Required (ns):
  Clock to Out (ns):           7.262

Path 3
  From:                        CoreGPIO_0/CGPIOOI_3[0]/U1:CLK
  To:                          LED[3]
  Delay (ns):                  3.304
  Slack (ns):
  Arrival (ns):                7.310
  Required (ns):
  Clock to Out (ns):           7.310

Path 4
  From:                        CoreGPIO_0/CGPIOiOI.0.CGPIOI1I.CGPIOo0[0]/U1:CLK
  To:                          LED[0]
  Delay (ns):                  3.408
  Slack (ns):
  Arrival (ns):                7.407
  Required (ns):
  Clock to Out (ns):           7.407

Path 5
  From:                        CoreGPIO_0/CGPIOOI_0[0]/U1:CLK
  To:                          LED[0]
  Delay (ns):                  3.419
  Slack (ns):
  Arrival (ns):                7.429
  Required (ns):
  Clock to Out (ns):           7.429


Expanded Path 1
  From: CoreGPIO_0/CGPIOOI_2[0]/U1:CLK
  To: LED[2]
  data arrival time                              7.240
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.308          net: FAB_CLK
  3.995                        CoreGPIO_0/CGPIOOI_2[0]/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.243                        CoreGPIO_0/CGPIOOI_2[0]/U1:Q (r)
               +     0.181          net: CoreGPIO_0/CGPIOOI_2[0]
  4.424                        CoreGPIO_0/CGPIOOI_2_RNI6VPM[0]:B (r)
               +     0.221          cell: ADLIB:NOR2B
  4.645                        CoreGPIO_0/CGPIOOI_2_RNI6VPM[0]:Y (r)
               +     1.223          net: CoreGPIO_0_N_731
  5.868                        LED_pad[2]/U0/U1:D (r)
               +     0.256          cell: ADLIB:IOTRI_OB_EB
  6.124                        LED_pad[2]/U0/U1:DOUT (r)
               +     0.000          net: LED_pad[2]/U0/NET1
  6.124                        LED_pad[2]/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  7.240                        LED_pad[2]/U0/U0:PAD (r)
               +     0.000          net: LED[2]
  7.240                        LED[2] (r)
                                    
  7.240                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  N/C
                                    
  N/C                          LED[2] (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  1.418
  Slack (ns):                  1.139
  Arrival (ns):                5.454
  Required (ns):               4.315
  Removal (ns):                0.196
  Skew (ns):                   -0.083

Path 2
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  1.552
  Slack (ns):                  1.272
  Arrival (ns):                5.588
  Required (ns):               4.316
  Removal (ns):                0.196
  Skew (ns):                   -0.084

Path 3
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  2.444
  Slack (ns):                  2.146
  Arrival (ns):                6.461
  Required (ns):               4.315
  Removal (ns):                0.196
  Skew (ns):                   -0.102

Path 4
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  2.578
  Slack (ns):                  2.279
  Arrival (ns):                6.595
  Required (ns):               4.316
  Removal (ns):                0.196
  Skew (ns):                   -0.103


Expanded Path 1
  From: CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  data arrival time                              5.454
  data required time                         -   4.315
  slack                                          1.139
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.349          net: FAB_CLK
  4.036                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK (r)
               +     0.319          cell: ADLIB:DFN1C0
  4.355                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:Q (f)
               +     0.142          net: CoreTFTahbMaster_0/I_TFTDATA_START_RIS
  4.497                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:B (f)
               +     0.174          cell: ADLIB:NOR2A
  4.671                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:Y (r)
               +     0.783          net: CoreTFTahbMaster_0/OUTF_PULSE_RNITR1U
  5.454                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET (r)
                                    
  5.454                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.432          net: FAB_CLK
  4.119                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:WCLK (r)
               +     0.196          Library removal time: ADLIB:FIFO4K18
  4.315                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
                                    
  4.315                        data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_glb

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/U1:D
  Delay (ns):                  2.256
  Slack (ns):                  1.144
  Arrival (ns):                5.205
  Required (ns):               4.061
  Hold (ns):                   0.000

Path 2
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[4]/U1:D
  Delay (ns):                  2.359
  Slack (ns):                  1.247
  Arrival (ns):                5.308
  Required (ns):               4.061
  Hold (ns):                   0.000

Path 3
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[18]/U1:D
  Delay (ns):                  2.383
  Slack (ns):                  1.271
  Arrival (ns):                5.332
  Required (ns):               4.061
  Hold (ns):                   0.000

Path 4
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[9]/U1:D
  Delay (ns):                  2.404
  Slack (ns):                  1.304
  Arrival (ns):                5.353
  Required (ns):               4.049
  Hold (ns):                   0.000

Path 5
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[6]/U1:D
  Delay (ns):                  2.397
  Slack (ns):                  1.306
  Arrival (ns):                5.346
  Required (ns):               4.040
  Hold (ns):                   0.000


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/U1:D
  data arrival time                              5.205
  data required time                         -   4.061
  slack                                          1.144
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.325          cell: ADLIB:MSS_AHB_IP
  4.274                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSHADDR[12] (r)
               +     0.058          net: MSS_new_top_0/MSS_ADLIB_INST/MSSHADDR[12]INT_NET
  4.332                        MSS_new_top_0/MSS_ADLIB_INST/U_34:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  4.373                        MSS_new_top_0/MSS_ADLIB_INST/U_34:PIN1 (r)
               +     0.433          net: _MSS_new_top_0_MSS_MASTER_AHB_LITE_HADDR_[12]_
  4.806                        CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/U0:B (r)
               +     0.250          cell: ADLIB:MX2
  5.056                        CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/U0:Y (r)
               +     0.149          net: CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/Y
  5.205                        CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/U1:D (r)
                                    
  5.205                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.374          net: FAB_CLK
  4.061                        CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.061                        CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/U1:D
                                    
  4.061                        data required time


END SET mss_fabric_interface_clock to mss_ccc_glb

----------------------------------------------------

SET mss_pclk1 to mss_ccc_glb

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          CoreGPIO_0/CGPIOiOI.10.CGPIOI1[10]:D
  Delay (ns):                  2.607
  Slack (ns):                  1.493
  Arrival (ns):                5.556
  Required (ns):               4.063
  Hold (ns):                   0.000

Path 2
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          CoreGPIO_0/CGPIOiOI.9.CGPIOI1[9]:D
  Delay (ns):                  2.624
  Slack (ns):                  1.520
  Arrival (ns):                5.573
  Required (ns):               4.053
  Hold (ns):                   0.000

Path 3
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          CoreGPIO_0/CGPIOiOI.11.CGPIOI1[11]:D
  Delay (ns):                  2.814
  Slack (ns):                  1.706
  Arrival (ns):                5.763
  Required (ns):               4.057
  Hold (ns):                   0.000

Path 4
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          CoreGPIO_0/CGPIOiOI.12.CGPIOI1[12]:D
  Delay (ns):                  2.827
  Slack (ns):                  1.721
  Arrival (ns):                5.776
  Required (ns):               4.055
  Hold (ns):                   0.000


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: CoreGPIO_0/CGPIOiOI.10.CGPIOI1[10]:D
  data arrival time                              5.556
  data required time                         -   4.063
  slack                                          1.493
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  2.949
               +     1.905          cell: ADLIB:MSS_AHB_IP
  4.854                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPO[25] (f)
               +     0.244          net: MSS_new_top_0/MSS_ADLIB_INST/GPO[25]INT_NET
  5.098                        MSS_new_top_0/MSS_ADLIB_INST/U_5:PIN1INT (f)
               +     0.042          cell: ADLIB:MSS_IF
  5.140                        MSS_new_top_0/MSS_ADLIB_INST/U_5:PIN1 (f)
               +     0.416          net: MSS_new_top_0/MSSINT_GPO_25_A
  5.556                        CoreGPIO_0/CGPIOiOI.10.CGPIOI1[10]:D (f)
                                    
  5.556                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.376          net: FAB_CLK
  4.063                        CoreGPIO_0/CGPIOiOI.10.CGPIOI1[10]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.063                        CoreGPIO_0/CGPIOiOI.10.CGPIOI1[10]:D
                                    
  4.063                        data required time


END SET mss_pclk1 to mss_ccc_glb

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glb

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3LLI[10]/U1:CLR
  Delay (ns):                  2.305
  Slack (ns):                  1.190
  Arrival (ns):                5.254
  Required (ns):               4.064
  Hold (ns):

Path 2
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR[12]/U1:CLR
  Delay (ns):                  2.309
  Slack (ns):                  1.197
  Arrival (ns):                5.258
  Required (ns):               4.061
  Hold (ns):

Path 3
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreTFTahbMaster_0/I_RAM_WR_ADDR[26]:CLR
  Delay (ns):                  2.311
  Slack (ns):                  1.199
  Arrival (ns):                5.260
  Required (ns):               4.061
  Hold (ns):

Path 4
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLR
  Delay (ns):                  2.311
  Slack (ns):                  1.199
  Arrival (ns):                5.260
  Required (ns):               4.061
  Hold (ns):

Path 5
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreTFTahbMaster_0/I_RAM_WR_ADDR[29]:CLR
  Delay (ns):                  2.311
  Slack (ns):                  1.199
  Arrival (ns):                5.260
  Required (ns):               4.061
  Hold (ns):


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3LLI[10]/U1:CLR
  data arrival time                              5.254
  data required time                         -   4.064
  slack                                          1.190
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.225          net: MSS_new_top_0/GLA0
  2.949                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.564          cell: ADLIB:MSS_AHB_IP
  4.513                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.059          net: MSS_new_top_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.572                        MSS_new_top_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.044          cell: ADLIB:MSS_IF
  4.616                        MSS_new_top_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.638          net: MSS_new_top_0_M2F_RESET_N
  5.254                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3LLI[10]/U1:CLR (r)
                                    
  5.254                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.377          net: FAB_CLK
  4.064                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3LLI[10]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.064                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3LLI[10]/U1:CLR
                                    
  4.064                        data required time


END SET mss_ccc_gla0 to mss_ccc_glb

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  Delay (ns):                  0.697
  Slack (ns):                  0.681
  Arrival (ns):                1.964
  Required (ns):               1.283
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  data arrival time                              1.964
  data required time                         -   1.283
  slack                                          0.681
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.310          net: MAC_CLK_c
  1.267                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  1.515                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.144          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  1.659                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:A (r)
               +     0.158          cell: ADLIB:INV
  1.817                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:Y (f)
               +     0.147          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[0]
  1.964                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D (f)
                                    
  1.964                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.326          net: MAC_CLK_c
  1.283                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  1.283                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
                                    
  1.283                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glc

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLR
  Delay (ns):                  4.041
  Slack (ns):                  5.707
  Arrival (ns):                6.990
  Required (ns):               1.283
  Hold (ns):


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLR
  data arrival time                              6.990
  data required time                         -   1.283
  slack                                          5.707
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.225          net: MSS_new_top_0/GLA0
  2.949                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.564          cell: ADLIB:MSS_AHB_IP
  4.513                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.059          net: MSS_new_top_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.572                        MSS_new_top_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.044          cell: ADLIB:MSS_IF
  4.616                        MSS_new_top_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     2.374          net: MSS_new_top_0_M2F_RESET_N
  6.990                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLR (r)
                                    
  6.990                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.326          net: MAC_CLK_c
  1.283                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  1.283                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLR
                                    
  1.283                        data required time


END SET mss_ccc_gla0 to mss_ccc_glc

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          MAC_CLK
  Delay (ns):                  2.662
  Slack (ns):
  Arrival (ns):                2.662
  Required (ns):
  Clock to Out (ns):           2.662


Expanded Path 1
  From: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: MAC_CLK
  data arrival time                              2.662
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     0.957          cell: ADLIB:MSS_CCC_IP
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.310          net: MAC_CLK_c
  1.267                        MAC_CLK_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  1.546                        MAC_CLK_pad/U0/U1:DOUT (r)
               +     0.000          net: MAC_CLK_pad/U0/NET1
  1.546                        MAC_CLK_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.662                        MAC_CLK_pad/U0/U0:PAD (r)
               +     0.000          net: MAC_CLK
  2.662                        MAC_CLK (r)
                                    
  2.662                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          MAC_CLK (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  Delay (ns):                  0.727
  Slack (ns):
  Arrival (ns):                1.206
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  data arrival time                              1.206
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.479          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  0.479                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.727                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.174          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.901                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:A (r)
               +     0.158          cell: ADLIB:INV
  1.059                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:Y (f)
               +     0.147          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[1]
  1.206                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D (f)
                                    
  1.206                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.576          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  Delay (ns):                  0.697
  Slack (ns):
  Arrival (ns):                0.877
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  data arrival time                              0.877
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.180          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.180                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.428                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.144          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.572                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:A (r)
               +     0.158          cell: ADLIB:INV
  0.730                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:Y (f)
               +     0.147          net: TOGGLE_DIV_0/TOGGLE_DIV_0_DIVREG_OUT2to2_i_i
  0.877                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D (f)
                                    
  0.877                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.216          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          IO_2_PADOUT
  Delay (ns):                  4.059
  Slack (ns):
  Arrival (ns):                4.239
  Required (ns):
  Clock to Out (ns):           4.239


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: IO_2_PADOUT
  data arrival time                              4.239
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.180          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.180                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.428                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.510          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.938                        CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  1.679                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.333          net: CLKINT_0_Y
  2.012                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:B (r)
               +     0.221          cell: ADLIB:NOR2B
  2.233                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:Y (r)
               +     0.478          net: CoreTFTahbMaster_0_RGB_CLK
  2.711                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  2.813                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5INT (r)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_2/U0/D_INT
  2.813                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:D (r)
               +     1.426          cell: ADLIB:IOPAD_TRI
  4.239                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:PAD (r)
               +     0.000          net: IO_2_PADOUT
  4.239                        IO_2_PADOUT (r)
                                    
  4.239                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
                                    
  N/C                          IO_2_PADOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q

SET Register to Register

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:D
  Delay (ns):                  0.393
  Slack (ns):
  Arrival (ns):                1.965
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:D
  Delay (ns):                  0.393
  Slack (ns):
  Arrival (ns):                1.965
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_1:CLK
  To:                          CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:D
  Delay (ns):                  0.393
  Slack (ns):
  Arrival (ns):                1.976
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        CoreTFTahbMaster_0/TFT_MEMDATA_EN_SYNCLEV/INTERNAL_IN_LEVEL:CLK
  To:                          CoreTFTahbMaster_0/TFT_MEMDATA_EN_SYNCLEV/OUT_LEVEL:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                1.976
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_H_SYNC:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/H_SYNC:D
  Delay (ns):                  0.400
  Slack (ns):
  Arrival (ns):                1.979
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:D
  data arrival time                              1.965
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.510          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.510                        CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  1.251                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.321          net: CLKINT_0_Y
  1.572                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:CLK (r)
               +     0.248          cell: ADLIB:DFN1P0
  1.820                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:Q (r)
               +     0.145          net: CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC
  1.965                        CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:D (r)
                                    
  1.965                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.510          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.339          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/I_V_SYNC1:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_R[2]:CLK
  To:                          IO_6_PADOUT
  Delay (ns):                  2.082
  Slack (ns):
  Arrival (ns):                3.672
  Required (ns):
  Clock to Out (ns):           3.672

Path 2
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_R[3]:CLK
  To:                          IO_11_PADOUT
  Delay (ns):                  2.176
  Slack (ns):
  Arrival (ns):                3.753
  Required (ns):
  Clock to Out (ns):           3.753

Path 3
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_data_en:CLK
  To:                          IO_5_PADOUT
  Delay (ns):                  2.216
  Slack (ns):
  Arrival (ns):                3.806
  Required (ns):
  Clock to Out (ns):           3.806

Path 4
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_h_sync:CLK
  To:                          IO_4_PADOUT
  Delay (ns):                  2.237
  Slack (ns):
  Arrival (ns):                3.827
  Required (ns):
  Clock to Out (ns):           3.827

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_R[4]:CLK
  To:                          IO_7_PADOUT
  Delay (ns):                  2.251
  Slack (ns):
  Arrival (ns):                3.827
  Required (ns):
  Clock to Out (ns):           3.827


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/VGA_R[2]:CLK
  To: IO_6_PADOUT
  data arrival time                              3.672
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.510          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.510                        CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  1.251                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.339          net: CLKINT_0_Y
  1.590                        CoreTFTahbMaster_0/LCDCTRL/VGA_R[2]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  1.838                        CoreTFTahbMaster_0/LCDCTRL/VGA_R[2]:Q (r)
               +     0.371          net: CoreTFTahbMaster_0_R_DATA3to3
  2.209                        MSS_new_top_0/FIO_OUTBUF_6/U0/U1:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  2.246                        MSS_new_top_0/FIO_OUTBUF_6/U0/U1:PIN5INT (r)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_6/U0/D_INT
  2.246                        MSS_new_top_0/FIO_OUTBUF_6/U0/U0:D (r)
               +     1.426          cell: ADLIB:IOPAD_TRI
  3.672                        MSS_new_top_0/FIO_OUTBUF_6/U0/U0:PAD (r)
               +     0.000          net: IO_6_PADOUT
  3.672                        IO_6_PADOUT (r)
                                    
  3.672                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
                                    
  N/C                          IO_6_PADOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:PRE
  Delay (ns):                  1.921
  Slack (ns):
  Arrival (ns):                3.500
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.011

Path 2
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[8]:CLR
  Delay (ns):                  1.921
  Slack (ns):
  Arrival (ns):                3.500
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.011

Path 3
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[0]:CLR
  Delay (ns):                  1.921
  Slack (ns):
  Arrival (ns):                3.500
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.011

Path 4
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[6]:CLR
  Delay (ns):                  1.918
  Slack (ns):
  Arrival (ns):                3.497
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.005

Path 5
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[7]:CLR
  Delay (ns):                  1.921
  Slack (ns):
  Arrival (ns):                3.500
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.006


Expanded Path 1
  From: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:PRE
  data arrival time                              3.500
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.510          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.510                        CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  1.251                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.328          net: CLKINT_0_Y
  1.579                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK (r)
               +     0.248          cell: ADLIB:DFN1
  1.827                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:Q (r)
               +     0.145          net: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2
  1.972                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:B (r)
               +     0.252          cell: ADLIB:NOR2B
  2.224                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:Y (r)
               +     0.587          net: CoreTFTahbMaster_0/I_SWHW_N_RESET_SRC
  2.811                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:A (r)
               +     0.390          cell: ADLIB:CLKSRC
  3.201                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:Y (r)
               +     0.299          net: CoreTFTahbMaster_0/I_SWHW_N_RESET
  3.500                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:PRE (r)
                                    
  3.500                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.510          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     0.741          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.339          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1E1P0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:PRE


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

