Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Jan 25 14:33:18 2012


Design: Top_55TFT32bit_QVGA_EthMAC
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       26.666
Required Frequency (MHz):   37.501
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.001
Frequency (MHz):            124.984
Required Period (ns):       26.666
Required Frequency (MHz):   37.501
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       26.666
Required Frequency (MHz):   37.501
External Setup (ns):        2.331
External Hold (ns):         2.242
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       13.333
Required Frequency (MHz):   75.002
External Setup (ns):        -4.928
External Hold (ns):         4.007
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                19.373
Frequency (MHz):            51.618
Required Period (ns):       26.667
Required Frequency (MHz):   37.500
External Setup (ns):        -0.792
External Hold (ns):         3.227
Min Clock-To-Out (ns):      7.240
Max Clock-To-Out (ns):      13.487

Clock Domain:               mss_ccc_glc
Period (ns):                1.845
Frequency (MHz):            542.005
Required Period (ns):       20.000
Required Frequency (MHz):   50.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       20.000
Required Frequency (MHz):   50.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.662
Max Clock-To-Out (ns):      5.085

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
Period (ns):                1.888
Frequency (MHz):            529.661
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
Period (ns):                1.843
Frequency (MHz):            542.594
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.239
Max Clock-To-Out (ns):      8.421

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
Period (ns):                9.393
Frequency (MHz):            106.462
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.672
Max Clock-To-Out (ns):      10.907

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  9.177
  Slack (ns):                  18.665
  Arrival (ns):                13.104
  Required (ns):               31.769
  Setup (ns):                  -1.176
  Minimum Period (ns):         8.001

Path 2
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  Delay (ns):                  4.189
  Slack (ns):                  23.620
  Arrival (ns):                8.116
  Required (ns):               31.736
  Setup (ns):                  -1.143
  Minimum Period (ns):         3.046


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  data required time                             31.769
  data arrival time                          -   13.104
  slack                                          18.665
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  3.927
               +     2.773          cell: ADLIB:MSS_AHB_IP
  6.700                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.136          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  6.836                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.074          cell: ADLIB:MSS_IF
  6.910                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     2.171          net: CoreAHBLite_0_AHBmslave16_HREADY
  9.081                        CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNIROKH5:C (r)
               +     0.517          cell: ADLIB:OR3B
  9.598                        CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNIROKH5:Y (r)
               +     0.282          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_1023
  9.880                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI9109J1:C (r)
               +     0.398          cell: ADLIB:OA1A
  10.278                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI9109J1:Y (r)
               +     1.335          net: CoreAHBLite_0/matrix2x16/m0PrevDataSlaveReady_0
  11.613                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0_RNIAM2JQ1[0]:A (r)
               +     0.683          cell: ADLIB:OA1B
  12.296                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0_RNIAM2JQ1[0]:Y (r)
               +     0.743          net: arbRegSMCurrentState_0_RNIAM2JQ1[0]
  13.039                       MSS_new_top_0/MSS_ADLIB_INST/U_60:PIN4 (r)
               +     0.065          cell: ADLIB:MSS_IF
  13.104                       MSS_new_top_0/MSS_ADLIB_INST/U_60:PIN4INT (r)
               +     0.000          net: MSS_new_top_0/MSS_ADLIB_INST/FABHTRANS1INT_NET
  13.104                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1 (r)
                                    
  13.104                       data arrival time
  ________________________________________________________
  Data required time calculation
  26.666                       mss_fabric_interface_clock
               +     0.000          Clock source
  26.666                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  30.593
               -    -1.176          Library setup time: ADLIB:MSS_AHB_IP
  31.769                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
                                    
  31.769                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_glb to mss_fabric_interface_clock

Path 1
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[1]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  13.615
  Slack (ns):                  12.766
  Arrival (ns):                19.003
  Required (ns):               31.769
  Setup (ns):                  -1.176

Path 2
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[2]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  13.422
  Slack (ns):                  12.959
  Arrival (ns):                18.810
  Required (ns):               31.769
  Setup (ns):                  -1.176

Path 3
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  13.298
  Slack (ns):                  13.089
  Arrival (ns):                18.680
  Required (ns):               31.769
  Setup (ns):                  -1.176

Path 4
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[10]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  12.933
  Slack (ns):                  13.463
  Arrival (ns):                18.306
  Required (ns):               31.769
  Setup (ns):                  -1.176

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[8]/U1:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  12.886
  Slack (ns):                  13.501
  Arrival (ns):                18.268
  Required (ns):               31.769
  Setup (ns):                  -1.176


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[1]/U1:CLK
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  data required time                             31.769
  data arrival time                          -   19.003
  slack                                          12.766
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.590          net: FAB_CLK
  5.388                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[1]/U1:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  5.828                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[1]/U1:Q (r)
               +     1.038          net: CoreAHBLite_0/matrix2x16/masterstage_0/xhdl1222[1]
  6.866                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIQM0A[1]:B (r)
               +     0.390          cell: ADLIB:NOR2
  7.256                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIQM0A[1]:Y (f)
               +     0.823          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_24_6
  8.079                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIJD1K_0[1]:A (f)
               +     0.353          cell: ADLIB:OR2A
  8.432                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIJD1K_0[1]:Y (r)
               +     1.427          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_1053
  9.859                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt_ORED_RNIV3GA1:C (r)
               +     0.486          cell: ADLIB:AND3C
  10.345                       CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt_ORED_RNIV3GA1:Y (f)
               +     0.768          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_1057
  11.113                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI5KRO2[0]:A (f)
               +     0.390          cell: ADLIB:NOR2B
  11.503                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI5KRO2[0]:Y (f)
               +     0.255          net: CoreAHBLite_0_matrix2x16_masterstage_0_N_1058
  11.758                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI0T775[13]:B (f)
               +     0.479          cell: ADLIB:OR2B
  12.237                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI0T775[13]:Y (r)
               +     0.255          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_1046
  12.492                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI0NNLF[13]:C (r)
               +     0.505          cell: ADLIB:OR3C
  12.997                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI0NNLF[13]:Y (f)
               +     0.255          net: SDATASELInt_RNI0NNLF[13]
  13.252                       CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNI7QR1L:C (f)
               +     0.504          cell: ADLIB:OR3
  13.756                       CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNI7QR1L:Y (f)
               +     0.245          net: CoreAHBLite_0/matrix2x16/masterstage_0/HRESP_iv_i_o3_0_1
  14.001                       CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNI2ORE41:C (f)
               +     0.302          cell: ADLIB:AOI1
  14.303                       CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNI2ORE41:Y (r)
               +     1.190          net: CoreAHBLite_0_matrix2x16_masterstage_0_N_1064
  15.493                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI9109J1:B (r)
               +     0.684          cell: ADLIB:OA1A
  16.177                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI9109J1:Y (r)
               +     1.335          net: CoreAHBLite_0/matrix2x16/m0PrevDataSlaveReady_0
  17.512                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0_RNIAM2JQ1[0]:A (r)
               +     0.683          cell: ADLIB:OA1B
  18.195                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0_RNIAM2JQ1[0]:Y (r)
               +     0.743          net: arbRegSMCurrentState_0_RNIAM2JQ1[0]
  18.938                       MSS_new_top_0/MSS_ADLIB_INST/U_60:PIN4 (r)
               +     0.065          cell: ADLIB:MSS_IF
  19.003                       MSS_new_top_0/MSS_ADLIB_INST/U_60:PIN4INT (r)
               +     0.000          net: MSS_new_top_0/MSS_ADLIB_INST/FABHTRANS1INT_NET
  19.003                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1 (r)
                                    
  19.003                       data arrival time
  ________________________________________________________
  Data required time calculation
  26.666                       mss_fabric_interface_clock
               +     0.000          Clock source
  26.666                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  30.593
               -    -1.176          Library setup time: ADLIB:MSS_AHB_IP
  31.769                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
                                    
  31.769                       data required time


END SET mss_ccc_glb to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        PBUTTON[0]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23]
  Delay (ns):                  6.636
  Slack (ns):
  Arrival (ns):                6.636
  Required (ns):
  Setup (ns):                  -0.378
  External Setup (ns):         2.331

Path 2
  From:                        PBUTTON[3]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[30]
  Delay (ns):                  5.623
  Slack (ns):
  Arrival (ns):                5.623
  Required (ns):
  Setup (ns):                  0.350
  External Setup (ns):         2.046

Path 3
  From:                        PBUTTON[4]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[31]
  Delay (ns):                  6.228
  Slack (ns):
  Arrival (ns):                6.228
  Required (ns):
  Setup (ns):                  -0.381
  External Setup (ns):         1.920

Path 4
  From:                        PBUTTON[2]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[29]
  Delay (ns):                  6.086
  Slack (ns):
  Arrival (ns):                6.086
  Required (ns):
  Setup (ns):                  -0.304
  External Setup (ns):         1.855

Path 5
  From:                        PBUTTON[1]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  3.273
  Slack (ns):
  Arrival (ns):                3.273
  Required (ns):
  Setup (ns):                  -0.228
  External Setup (ns):         -0.882


Expanded Path 1
  From: PBUTTON[0]
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23]
  data required time                             N/C
  data arrival time                          -   6.636
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PBUTTON[0] (r)
               +     0.000          net: PBUTTON[0]
  0.000                        PBUTTON_pad[0]/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        PBUTTON_pad[0]/U0/U0:Y (r)
               +     0.000          net: PBUTTON_pad[0]/U0/NET1
  0.806                        PBUTTON_pad[0]/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        PBUTTON_pad[0]/U0/U1:Y (r)
               +     5.515          net: PBUTTON_c[0]
  6.354                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN4 (r)
               +     0.180          cell: ADLIB:MSS_IF
  6.534                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN4INT (r)
               +     0.102          net: MSS_new_top_0/MSS_ADLIB_INST/GPI[23]INT_NET
  6.636                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23] (r)
                                    
  6.636                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.927          Clock generation
  N/C
               -    -0.378          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23]


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -4.928


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_new_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.382          net: MSS_new_top_0/GLA0
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_glb to mss_ccc_gla0

Path 1
  From:                        CoreTFTahbMaster_0/MemCntlState[2]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[6]
  Delay (ns):                  10.555
  Slack (ns):                  2.167
  Arrival (ns):                15.944
  Required (ns):               18.111
  Setup (ns):                  -0.851

Path 2
  From:                        CoreTFTahbMaster_0/MemCntlState[3]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[6]
  Delay (ns):                  10.432
  Slack (ns):                  2.276
  Arrival (ns):                15.835
  Required (ns):               18.111
  Setup (ns):                  -0.851

Path 3
  From:                        CoreTFTahbMaster_0/MemCntlState[2]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[5]
  Delay (ns):                  10.362
  Slack (ns):                  2.337
  Arrival (ns):                15.751
  Required (ns):               18.088
  Setup (ns):                  -0.828

Path 4
  From:                        CoreTFTahbMaster_0/MemCntlState[2]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[2]
  Delay (ns):                  10.374
  Slack (ns):                  2.359
  Arrival (ns):                15.763
  Required (ns):               18.122
  Setup (ns):                  -0.862

Path 5
  From:                        CoreTFTahbMaster_0/MemCntlState[2]:CLK
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[4]
  Delay (ns):                  10.283
  Slack (ns):                  2.410
  Arrival (ns):                15.672
  Required (ns):               18.082
  Setup (ns):                  -0.822


Expanded Path 1
  From: CoreTFTahbMaster_0/MemCntlState[2]:CLK
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[6]
  data required time                             18.111
  data arrival time                          -   15.944
  slack                                          2.167
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.591          net: FAB_CLK
  5.389                        CoreTFTahbMaster_0/MemCntlState[2]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  5.948                        CoreTFTahbMaster_0/MemCntlState[2]:Q (f)
               +     0.387          net: CoreTFTahbMaster_0/Z_CoreTFTahbMaster_0_AHB_bif_HTRANS_[0]_
  6.335                        CoreTFTahbMaster_0/MemCntlState_RNI1FKU[2]:B (f)
               +     0.490          cell: ADLIB:OR2
  6.825                        CoreTFTahbMaster_0/MemCntlState_RNI1FKU[2]:Y (f)
               +     0.852          net: _CoreTFTahbMaster_0_AHB_bif_HSIZE_[0]_
  7.677                        CoreAHBLite_0/matrix2x16/masterstage_0/regHTRANS_RNISG5J1:A (f)
               +     0.469          cell: ADLIB:MX2
  8.146                        CoreAHBLite_0/matrix2x16/masterstage_0/regHTRANS_RNISG5J1:Y (f)
               +     1.281          net: CoreAHBLite_0/matrix2x16/M0GATEDHTRANS
  9.427                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR_RNIUCAF2[31]:A (f)
               +     0.390          cell: ADLIB:NOR2B
  9.817                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR_RNIUCAF2[31]:Y (f)
               +     0.829          net: CoreAHBLite_0/matrix2x16/xhdl1221[16]
  10.646                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNI0Q6H2[4]:A (f)
               +     0.293          cell: ADLIB:NOR2B
  10.939                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNI0Q6H2[4]:Y (f)
               +     0.308          net: CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/N_114
  11.247                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNI7LA45[6]:C (f)
               +     0.504          cell: ADLIB:OR3
  11.751                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNI7LA45[6]:Y (f)
               +     1.515          net: CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/masterAddrInProg_0[0]
  13.266                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0_RNITFNV5[0]:A (f)
               +     0.518          cell: ADLIB:NOR3A
  13.784                       CoreAHBLite_0/matrix2x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_0_RNITFNV5[0]:Y (f)
               +     1.658          net: _CoreAHBLite_0_AHBmslave16_HADDR_[6]_
  15.442                       MSS_new_top_0/MSS_ADLIB_INST/U_32:PIN5 (f)
               +     0.079          cell: ADLIB:MSS_IF
  15.521                       MSS_new_top_0/MSS_ADLIB_INST/U_32:PIN5INT (f)
               +     0.423          net: MSS_new_top_0/MSS_ADLIB_INST/FABHADDR[6]INT_NET
  15.944                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[6] (f)
                                    
  15.944                       data arrival time
  ________________________________________________________
  Data required time calculation
  13.333                       mss_ccc_gla0
               +     0.000          Clock source
  13.333                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  16.878
               +     0.382          net: MSS_new_top_0/GLA0
  17.260                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -0.851          Library setup time: ADLIB:MSS_AHB_IP
  18.111                       MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[6]
                                    
  18.111                       data required time


END SET mss_ccc_glb to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]/U1:CLK
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[3]/U1:D
  Delay (ns):                  18.942
  Slack (ns):                  7.294
  Arrival (ns):                24.341
  Required (ns):               31.635
  Setup (ns):                  0.435
  Minimum Period (ns):         19.373

Path 2
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]/U1:CLK
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[7]/U1:D
  Delay (ns):                  18.917
  Slack (ns):                  7.308
  Arrival (ns):                24.316
  Required (ns):               31.624
  Setup (ns):                  0.435
  Minimum Period (ns):         19.359

Path 3
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]/U1:CLK
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[1]/U1:D
  Delay (ns):                  18.539
  Slack (ns):                  7.662
  Arrival (ns):                23.938
  Required (ns):               31.600
  Setup (ns):                  0.435
  Minimum Period (ns):         19.005

Path 4
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]/U1:CLK
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[6]/U1:D
  Delay (ns):                  18.256
  Slack (ns):                  7.960
  Arrival (ns):                23.655
  Required (ns):               31.615
  Setup (ns):                  0.435
  Minimum Period (ns):         18.707

Path 5
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]/U1:CLK
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[4]/U1:D
  Delay (ns):                  17.674
  Slack (ns):                  8.536
  Arrival (ns):                23.073
  Required (ns):               31.609
  Setup (ns):                  0.435
  Minimum Period (ns):         18.131


Expanded Path 1
  From: COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]/U1:CLK
  To: COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[3]/U1:D
  data required time                             31.635
  data arrival time                          -   24.341
  slack                                          7.294
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.601          net: FAB_CLK
  5.399                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  5.958                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]/U1:Q (f)
               +     3.220          net: COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[2]
  9.178                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli_RNI8KPE[2]/U_CLKSRC:A (f)
               +     0.599          cell: ADLIB:CLKSRC
  9.777                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli_RNI8KPE[2]/U_CLKSRC:Y (f)
               +     0.571          net: _CoreAPB3_0_APBmslave2_PADDR_[2]_
  10.348                       CoreGPIO_0/CGPIOOIa23_1:B (f)
               +     0.476          cell: ADLIB:NOR2B
  10.824                       CoreGPIO_0/CGPIOOIa23_1:Y (f)
               +     0.728          net: CoreGPIO_0/CGPIOOIa23_1
  11.552                       CoreGPIO_0/CGPIOOIa31_3:C (f)
               +     0.517          cell: ADLIB:NOR3C
  12.069                       CoreGPIO_0/CGPIOOIa31_3:Y (f)
               +     0.847          net: CoreGPIO_0/CGPIOOIa31_3
  12.916                       CoreGPIO_0/CGPIOOIa15:A (f)
               +     0.476          cell: ADLIB:NOR2A
  13.392                       CoreGPIO_0/CGPIOOIa15:Y (f)
               +     0.308          net: CoreGPIO_0/CGPIOOIa15
  13.700                       CoreGPIO_0/CGPIOOIrff_15_RNIVVRM4:B (f)
               +     0.684          cell: ADLIB:AOI1B
  14.384                       CoreGPIO_0/CGPIOOIrff_15_RNIVVRM4:Y (r)
               +     0.255          net: CoreGPIO_0/CGPIOOIror_4
  14.639                       CoreGPIO_0/CGPIOOIrff_15_RNICH9P9:C (r)
               +     0.505          cell: ADLIB:NOR3C
  15.144                       CoreGPIO_0/CGPIOOIrff_15_RNICH9P9:Y (r)
               +     0.865          net: CoreGPIO_0/CGPIOOIror_11
  16.009                       CoreGPIO_0/CGPIOOIrff_11_RNIB6IIJ:C (r)
               +     0.505          cell: ADLIB:NOR3C
  16.514                       CoreGPIO_0/CGPIOOIrff_11_RNIB6IIJ:Y (r)
               +     0.255          net: CoreGPIO_0/CGPIOOIror_14
  16.769                       CoreGPIO_0/CGPIOOIrff_30_RNI8OPR11:C (r)
               +     0.505          cell: ADLIB:NOR3C
  17.274                       CoreGPIO_0/CGPIOOIrff_30_RNI8OPR11:Y (r)
               +     0.991          net: CoreGPIO_0/CGPIOOIror_17
  18.265                       CoreGPIO_0/CGPIOOIrff_4_RNINK5OP1:A (r)
               +     0.398          cell: ADLIB:NOR3C
  18.663                       CoreGPIO_0/CGPIOOIrff_4_RNINK5OP1:Y (r)
               +     0.255          net: CoreGPIO_0/CGPIOOIror_28
  18.918                       CoreGPIO_0/CGPIOOIrff_22_RNI9LFRC2:B (r)
               +     0.482          cell: ADLIB:AOI1
  19.400                       CoreGPIO_0/CGPIOOIrff_22_RNI9LFRC2:Y (f)
               +     1.637          net: CoreGPIO_0/N_1818
  21.037                       CoreGPIO_0/CGPIOiOI.3.CGPIOI1I.CGPIOo0_RNIQR8A43[3]:A (f)
               +     0.381          cell: ADLIB:AO1B
  21.418                       CoreGPIO_0/CGPIOiOI.3.CGPIOI1I.CGPIOo0_RNIQR8A43[3]:Y (f)
               +     1.491          net: _CoreAPB3_0_APBmslave2_PRDATA_[3]_
  22.909                       CoreAPB3_0/CAPB3O1II/PRDATA_0[3]:B (f)
               +     0.461          cell: ADLIB:AO1B
  23.370                       CoreAPB3_0/CAPB3O1II/PRDATA_0[3]:Y (f)
               +     0.255          net: _COREAHBTOAPB3_0_APBmaster_PRDATA_[3]_
  23.625                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[3]/U0:A (f)
               +     0.469          cell: ADLIB:MX2
  24.094                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[3]/U0:Y (f)
               +     0.247          net: COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[3]/Y
  24.341                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[3]/U1:D (f)
                                    
  24.341                       data arrival time
  ________________________________________________________
  Data required time calculation
  26.667                       mss_ccc_glb
               +     0.000          Clock source
  26.667                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  31.465
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  31.465                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  31.465                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.605          net: FAB_CLK
  32.070                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[3]/U1:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  31.635                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[3]/U1:D
                                    
  31.635                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        PBUTTON[2]
  To:                          CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D
  Delay (ns):                  4.152
  Slack (ns):
  Arrival (ns):                4.152
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         -0.792

Path 2
  From:                        PBUTTON[4]
  To:                          CoreGPIO_0/CGPIOiOI.8.CGPIOI1[8]:D
  Delay (ns):                  4.065
  Slack (ns):
  Arrival (ns):                4.065
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         -0.874

Path 3
  From:                        PBUTTON[0]
  To:                          CoreGPIO_0/CGPIOiOI.4.CGPIOI1[4]:D
  Delay (ns):                  4.027
  Slack (ns):
  Arrival (ns):                4.027
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         -0.912

Path 4
  From:                        PBUTTON[3]
  To:                          CoreGPIO_0/CGPIOiOI.7.CGPIOI1[7]:D
  Delay (ns):                  3.397
  Slack (ns):
  Arrival (ns):                3.397
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         -1.562

Path 5
  From:                        DIP_SWITCH[2]
  To:                          CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D
  Delay (ns):                  2.446
  Slack (ns):
  Arrival (ns):                2.446
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         -2.462


Expanded Path 1
  From: PBUTTON[2]
  To: CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D
  data required time                             N/C
  data arrival time                          -   4.152
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PBUTTON[2] (r)
               +     0.000          net: PBUTTON[2]
  0.000                        PBUTTON_pad[2]/U0/U0:PAD (r)
               +     0.779          cell: ADLIB:IOPAD_IN
  0.779                        PBUTTON_pad[2]/U0/U0:Y (r)
               +     0.000          net: PBUTTON_pad[2]/U0/NET1
  0.779                        PBUTTON_pad[2]/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.812                        PBUTTON_pad[2]/U0/U1:Y (r)
               +     3.340          net: PBUTTON_c[2]
  4.152                        CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D (r)
                                    
  4.152                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  N/C
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.581          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]/U1:CLK
  To:                          LED[2]
  Delay (ns):                  8.093
  Slack (ns):
  Arrival (ns):                13.487
  Required (ns):
  Clock to Out (ns):           13.487

Path 2
  From:                        CoreGPIO_0/CGPIOiOI.3.CGPIOI1I.CGPIOo0[3]/U1:CLK
  To:                          LED[3]
  Delay (ns):                  7.660
  Slack (ns):
  Arrival (ns):                13.029
  Required (ns):
  Clock to Out (ns):           13.029

Path 3
  From:                        CoreGPIO_0/CGPIOiOI.1.CGPIOI1I.CGPIOo0[1]/U1:CLK
  To:                          LED[1]
  Delay (ns):                  7.497
  Slack (ns):
  Arrival (ns):                12.871
  Required (ns):
  Clock to Out (ns):           12.871

Path 4
  From:                        CoreGPIO_0/CGPIOOI_0[0]/U1:CLK
  To:                          LED[0]
  Delay (ns):                  7.064
  Slack (ns):
  Arrival (ns):                12.413
  Required (ns):
  Clock to Out (ns):           12.413

Path 5
  From:                        CoreGPIO_0/CGPIOiOI.0.CGPIOI1I.CGPIOo0[0]/U1:CLK
  To:                          LED[0]
  Delay (ns):                  6.982
  Slack (ns):
  Arrival (ns):                12.313
  Required (ns):
  Clock to Out (ns):           12.313


Expanded Path 1
  From: CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]/U1:CLK
  To: LED[2]
  data required time                             N/C
  data arrival time                          -   13.487
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.596          net: FAB_CLK
  5.394                        CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  5.953                        CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]/U1:Q (f)
               +     1.737          net: CoreGPIO_0/CGPIOo0[2]
  7.690                        CoreGPIO_0/CGPIOOI_2_RNI6VPM[0]:A (f)
               +     0.390          cell: ADLIB:NOR2B
  8.080                        CoreGPIO_0/CGPIOOI_2_RNI6VPM[0]:Y (f)
               +     2.157          net: CoreGPIO_0_N_731
  10.237                       LED_pad[2]/U0/U1:D (f)
               +     0.442          cell: ADLIB:IOTRI_OB_EB
  10.679                       LED_pad[2]/U0/U1:DOUT (f)
               +     0.000          net: LED_pad[2]/U0/NET1
  10.679                       LED_pad[2]/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  13.487                       LED_pad[2]/U0/U0:PAD (f)
               +     0.000          net: LED[2]
  13.487                       LED[2] (f)
                                    
  13.487                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  N/C
                                    
  N/C                          LED[2] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  4.424
  Slack (ns):                  20.843
  Arrival (ns):                9.784
  Required (ns):               30.627
  Recovery (ns):               1.523
  Minimum Period (ns):         5.824
  Skew (ns):                   -0.123

Path 2
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  4.195
  Slack (ns):                  21.071
  Arrival (ns):                9.555
  Required (ns):               30.626
  Recovery (ns):               1.523
  Minimum Period (ns):         5.596
  Skew (ns):                   -0.122

Path 3
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  2.666
  Slack (ns):                  22.567
  Arrival (ns):                8.060
  Required (ns):               30.627
  Recovery (ns):               1.523
  Minimum Period (ns):         4.100
  Skew (ns):                   -0.089

Path 4
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  2.437
  Slack (ns):                  22.795
  Arrival (ns):                7.831
  Required (ns):               30.626
  Recovery (ns):               1.523
  Minimum Period (ns):         3.872
  Skew (ns):                   -0.088


Expanded Path 1
  From: CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  data required time                             30.627
  data arrival time                          -   9.784
  slack                                          20.843
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.562          net: FAB_CLK
  5.360                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  5.800                        CoreTFTahbMaster_0/CTRL_REG[6]:Q (r)
               +     2.030          net: CoreTFTahbMaster_0/CTRL_REG[6]
  7.830                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:A (r)
               +     0.392          cell: ADLIB:NOR2A
  8.222                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:Y (r)
               +     1.562          net: CoreTFTahbMaster_0/OUTF_PULSE_RNITR1U
  9.784                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET (r)
                                    
  9.784                        data arrival time
  ________________________________________________________
  Data required time calculation
  26.667                       mss_ccc_glb
               +     0.000          Clock source
  26.667                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  31.465
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  31.465                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  31.465                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.685          net: FAB_CLK
  32.150                       CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:WCLK (r)
               -     1.523          Library recovery time: ADLIB:FIFO4K18
  30.627                       CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
                                    
  30.627                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_glb

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[10]/U1:D
  Delay (ns):                  17.207
  Slack (ns):                  -16.143
  Arrival (ns):                21.134
  Required (ns):               4.991
  Setup (ns):                  0.409

Path 2
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[4]/U1:D
  Delay (ns):                  16.973
  Slack (ns):                  -15.909
  Arrival (ns):                20.900
  Required (ns):               4.991
  Setup (ns):                  0.409

Path 3
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[5]/U1:D
  Delay (ns):                  16.970
  Slack (ns):                  -15.909
  Arrival (ns):                20.897
  Required (ns):               4.988
  Setup (ns):                  0.409

Path 4
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[0]/U1:D
  Delay (ns):                  16.973
  Slack (ns):                  -15.909
  Arrival (ns):                20.900
  Required (ns):               4.991
  Setup (ns):                  0.409

Path 5
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[11]/U1:D
  Delay (ns):                  16.967
  Slack (ns):                  -15.906
  Arrival (ns):                20.894
  Required (ns):               4.988
  Setup (ns):                  0.409


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[10]/U1:D
  data required time                             4.991
  data arrival time                          -   21.134
  slack                                          -16.143
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  3.927
               +     2.392          cell: ADLIB:MSS_AHB_IP
  6.319                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSHADDR[17] (f)
               +     0.131          net: MSS_new_top_0/MSS_ADLIB_INST/MSSHADDR[17]INT_NET
  6.450                        MSS_new_top_0/MSS_ADLIB_INST/U_35:PIN3INT (f)
               +     0.072          cell: ADLIB:MSS_IF
  6.522                        MSS_new_top_0/MSS_ADLIB_INST/U_35:PIN3 (f)
               +     0.918          net: _MSS_new_top_0_MSS_MASTER_AHB_LITE_HADDR_[17]_
  7.440                        CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR_RNITFQO[17]:A (f)
               +     0.439          cell: ADLIB:MX2
  7.879                        CoreAHBLite_0/matrix2x16/masterstage_1/regHADDR_RNITFQO[17]:Y (f)
               +     0.574          net: CoreAHBLite_0/matrix2x16/masterstage_1/M1GATEDHADDR[17]
  8.453                        CoreAHBLite_0/matrix2x16/masterstage_1/address_decode/cdec_20_sqmuxa_0_a2_0:B (f)
               +     0.490          cell: ADLIB:NOR2
  8.943                        CoreAHBLite_0/matrix2x16/masterstage_1/address_decode/cdec_20_sqmuxa_0_a2_0:Y (r)
               +     0.760          net: CoreAHBLite_0/matrix2x16/masterstage_1/N_80
  9.703                        CoreAHBLite_0/matrix2x16/masterstage_1/regHTRANS_RNIOSIE2:A (r)
               +     0.370          cell: ADLIB:OR2B
  10.073                       CoreAHBLite_0/matrix2x16/masterstage_1/regHTRANS_RNIOSIE2:Y (f)
               +     0.501          net: CoreAHBLite_0/matrix2x16/masterstage_1/SADDRSEL_0[1]
  10.574                       CoreAHBLite_0/matrix2x16/masterstage_1/regHTRANS_RNIIS704:B (f)
               +     0.490          cell: ADLIB:NOR2
  11.064                       CoreAHBLite_0/matrix2x16/masterstage_1/regHTRANS_RNIIS704:Y (r)
               +     0.278          net: CoreAHBLite_0/matrix2x16/xhdl1226[5]
  11.342                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_ns_o3[0]:A (r)
               +     0.392          cell: ADLIB:NOR2A
  11.734                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_ns_o3[0]:Y (r)
               +     0.269          net: CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/N_92
  12.003                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIPJOR5[5]:A (r)
               +     0.494          cell: ADLIB:AOI1
  12.497                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIPJOR5[5]:Y (f)
               +     0.292          net: CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/N_102
  12.789                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIOC0BB[0]:B (f)
               +     0.476          cell: ADLIB:OR2B
  13.265                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIOC0BB[0]:Y (r)
               +     1.142          net: CoreAHBLite_0/matrix2x16/slavestage_5/masterAddrInProg[1]
  14.407                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI57HNB[1]:A (r)
               +     0.407          cell: ADLIB:OR2A
  14.814                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI57HNB[1]:Y (f)
               +     0.849          net: CoreAHBLite_0_matrix2x16_slavestage_5_hsel3
  15.663                       COREAHBTOAPB3_0/CAHBtoAPB3LL0/HREADYOUT_RNIP9ISL1:C (f)
               +     0.504          cell: ADLIB:OR3A
  16.167                       COREAHBTOAPB3_0/CAHBtoAPB3LL0/HREADYOUT_RNIP9ISL1:Y (f)
               +     0.441          net: COREAHBTOAPB3_0/hsel_1
  16.608                       COREAHBTOAPB3_0/CAHBtoAPB3LL0/CAHBtoAPB3iol_RNIGO82M1[2]:A (f)
               +     0.479          cell: ADLIB:NOR2A
  17.087                       COREAHBTOAPB3_0/CAHBtoAPB3LL0/CAHBtoAPB3iol_RNIGO82M1[2]:Y (f)
               +     0.351          net: COREAHBTOAPB3_0/CAHBtoAPB3LL0/N_178
  17.438                       COREAHBTOAPB3_0/CAHBtoAPB3LL0/CAHBTOAPB3oil_RNIO2FBM1:A (f)
               +     0.293          cell: ADLIB:OR2B
  17.731                       COREAHBTOAPB3_0/CAHBtoAPB3LL0/CAHBTOAPB3oil_RNIO2FBM1:Y (r)
               +     0.931          net: COREAHBTOAPB3_0/CAHBtoAPB3l1
  18.662                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli_1_sqmuxa:B (r)
               +     0.392          cell: ADLIB:NOR2B
  19.054                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli_1_sqmuxa:Y (r)
               +     1.440          net: COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli_1_sqmuxa
  20.494                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[10]/U0:S (r)
               +     0.385          cell: ADLIB:MX2
  20.879                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[10]/U0:Y (r)
               +     0.255          net: COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[10]/Y
  21.134                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[10]/U1:D (r)
                                    
  21.134                       data arrival time
  ________________________________________________________
  Data required time calculation
  0.001                        mss_ccc_glb
               +     0.000          Clock source
  0.001                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.799
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.799                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.799                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.601          net: FAB_CLK
  5.400                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[10]/U1:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  4.991                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBtoAPB3oli[10]/U1:D
                                    
  4.991                        data required time


END SET mss_fabric_interface_clock to mss_ccc_glb

----------------------------------------------------

SET mss_pclk1 to mss_ccc_glb

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          CoreGPIO_0/CGPIOiOI.12.CGPIOI1[12]:D
  Delay (ns):                  4.952
  Slack (ns):                  -3.896
  Arrival (ns):                8.879
  Required (ns):               4.983
  Setup (ns):                  0.409

Path 2
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          CoreGPIO_0/CGPIOiOI.11.CGPIOI1[11]:D
  Delay (ns):                  4.934
  Slack (ns):                  -3.875
  Arrival (ns):                8.861
  Required (ns):               4.986
  Setup (ns):                  0.409

Path 3
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          CoreGPIO_0/CGPIOiOI.10.CGPIOI1[10]:D
  Delay (ns):                  4.700
  Slack (ns):                  -3.634
  Arrival (ns):                8.627
  Required (ns):               4.993
  Setup (ns):                  0.409

Path 4
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          CoreGPIO_0/CGPIOiOI.9.CGPIOI1[9]:D
  Delay (ns):                  4.610
  Slack (ns):                  -3.556
  Arrival (ns):                8.537
  Required (ns):               4.981
  Setup (ns):                  0.409


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: CoreGPIO_0/CGPIOiOI.12.CGPIOI1[12]:D
  data required time                             4.983
  data arrival time                          -   8.879
  slack                                          -3.896
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.927          Clock generation
  3.927
               +     3.259          cell: ADLIB:MSS_AHB_IP
  7.186                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPO[27] (r)
               +     0.352          net: MSS_new_top_0/MSS_ADLIB_INST/GPO[27]INT_NET
  7.538                        MSS_new_top_0/MSS_ADLIB_INST/U_5:PIN3INT (r)
               +     0.072          cell: ADLIB:MSS_IF
  7.610                        MSS_new_top_0/MSS_ADLIB_INST/U_5:PIN3 (r)
               +     1.269          net: MSS_new_top_0/MSSINT_GPO_27_A
  8.879                        CoreGPIO_0/CGPIOiOI.12.CGPIOI1[12]:D (r)
                                    
  8.879                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.001                        mss_ccc_glb
               +     0.000          Clock source
  0.001                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.799
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.799                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.799                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.593          net: FAB_CLK
  5.392                        CoreGPIO_0/CGPIOiOI.12.CGPIOI1[12]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  4.983                        CoreGPIO_0/CGPIOiOI.12.CGPIOI1[12]:D
                                    
  4.983                        data required time


END SET mss_pclk1 to mss_ccc_glb

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glb

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[0]/U1:D
  Delay (ns):                  12.165
  Slack (ns):                  -11.121
  Arrival (ns):                16.092
  Required (ns):               4.971
  Setup (ns):                  0.409

Path 2
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreGPIO_0/CGPIOiOI.8.CGPIOI1[8]:CLR
  Delay (ns):                  9.141
  Slack (ns):                  -7.918
  Arrival (ns):                13.068
  Required (ns):               5.150
  Setup (ns):

Path 3
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreGPIO_0/CGPIOOI_8[3]/U1:CLR
  Delay (ns):                  9.043
  Slack (ns):                  -7.815
  Arrival (ns):                12.970
  Required (ns):               5.155
  Setup (ns):

Path 4
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreGPIO_0/CGPIOOI_12[6]/U1:CLR
  Delay (ns):                  8.947
  Slack (ns):                  -7.757
  Arrival (ns):                12.874
  Required (ns):               5.117
  Setup (ns):

Path 5
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreGPIO_0/CGPIOiOI.4.CGPIOI1I.CGPIOlll[4]/U1:CLR
  Delay (ns):                  8.847
  Slack (ns):                  -7.624
  Arrival (ns):                12.774
  Required (ns):               5.150
  Setup (ns):


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[0]/U1:D
  data required time                             4.971
  data arrival time                          -   16.092
  slack                                          -11.121
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.382          net: MSS_new_top_0/GLA0
  3.927                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     2.776          cell: ADLIB:MSS_AHB_IP
  6.703                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.101          net: MSS_new_top_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  6.804                        MSS_new_top_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  6.883                        MSS_new_top_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     3.676          net: MSS_new_top_0_M2F_RESET_N
  10.559                       CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:A (r)
               +     0.370          cell: ADLIB:NOR2B
  10.929                       CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:Y (r)
               +     1.000          net: CoreTFTahbMaster_0/I_SWHW_N_RESET_SRC
  11.929                       CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:A (r)
               +     0.691          cell: ADLIB:CLKSRC
  12.620                       CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:Y (r)
               +     0.537          net: CoreTFTahbMaster_0/I_SWHW_N_RESET
  13.157                       CoreTFTahbMaster_0/SWHWRES_BUF_RNIG9HT1:A (r)
               +     0.370          cell: ADLIB:OR2B
  13.527                       CoreTFTahbMaster_0/SWHWRES_BUF_RNIG9HT1:Y (f)
               +     0.271          net: CoreTFTahbMaster_0_I_SWHW_N_RESET_m_i
  13.798                       CoreAPB3_0/CAPB3O1II/PRDATA_0_a3[0]:B (f)
               +     0.452          cell: ADLIB:AO1B
  14.250                       CoreAPB3_0/CAPB3O1II/PRDATA_0_a3[0]:Y (f)
               +     0.279          net: CoreAPB3_0/CAPB3O1II/N_52
  14.529                       CoreAPB3_0/CAPB3O1II/PRDATA_0[0]:C (f)
               +     0.535          cell: ADLIB:AO1B
  15.064                       CoreAPB3_0/CAPB3O1II/PRDATA_0[0]:Y (r)
               +     0.268          net: _COREAHBTOAPB3_0_APBmaster_PRDATA_[0]_
  15.332                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[0]/U0:A (r)
               +     0.505          cell: ADLIB:MX2
  15.837                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[0]/U0:Y (r)
               +     0.255          net: COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[0]/Y
  16.092                       COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[0]/U1:D (r)
                                    
  16.092                       data arrival time
  ________________________________________________________
  Data required time calculation
  0.001                        mss_ccc_glb
               +     0.000          Clock source
  0.001                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.799
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.799                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.799                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.581          net: FAB_CLK
  5.380                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[0]/U1:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  4.971                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/HRDATA[0]/U1:D
                                    
  4.971                        data required time


END SET mss_ccc_gla0 to mss_ccc_glb

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  Delay (ns):                  1.436
  Slack (ns):                  18.155
  Arrival (ns):                3.212
  Required (ns):               21.367
  Setup (ns):                  0.409
  Minimum Period (ns):         1.845


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  data required time                             21.367
  data arrival time                          -   3.212
  slack                                          18.155
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  1.246
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.530          net: MAC_CLK_c
  1.776                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  2.335                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (f)
               +     0.237          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  2.572                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:A (f)
               +     0.385          cell: ADLIB:INV
  2.957                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:Y (r)
               +     0.255          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[0]
  3.212                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D (r)
                                    
  3.212                        data arrival time
  ________________________________________________________
  Data required time calculation
  20.000                       mss_ccc_glc
               +     0.000          Clock source
  20.000                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  21.246
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  21.246                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  21.246                       MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.530          net: MAC_CLK_c
  21.776                       TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  21.367                       TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
                                    
  21.367                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glc

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLR
  Delay (ns):                  6.999
  Slack (ns):                  -2.708
  Arrival (ns):                10.926
  Required (ns):               8.218
  Setup (ns):


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLR
  data required time                             8.218
  data arrival time                          -   10.926
  slack                                          -2.708
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.382          net: MSS_new_top_0/GLA0
  3.927                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     2.776          cell: ADLIB:MSS_AHB_IP
  6.703                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.101          net: MSS_new_top_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  6.804                        MSS_new_top_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  6.883                        MSS_new_top_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     4.043          net: MSS_new_top_0_M2F_RESET_N
  10.926                       TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLR (r)
                                    
  10.926                       data arrival time
  ________________________________________________________
  Data required time calculation
  6.667                        mss_ccc_glc
               +     0.000          Clock source
  6.667                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  7.913
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  7.913                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  7.913                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.530          net: MAC_CLK_c
  8.443                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  8.218                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLR
                                    
  8.218                        data required time


END SET mss_ccc_gla0 to mss_ccc_glc

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          MAC_CLK
  Delay (ns):                  5.085
  Slack (ns):
  Arrival (ns):                5.085
  Required (ns):
  Clock to Out (ns):           5.085


Expanded Path 1
  From: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: MAC_CLK
  data required time                             N/C
  data arrival time                          -   5.085
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     1.246          cell: ADLIB:MSS_CCC_IP
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (f)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (f)
               +     0.531          net: MAC_CLK_c
  1.777                        MAC_CLK_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  2.277                        MAC_CLK_pad/U0/U1:DOUT (f)
               +     0.000          net: MAC_CLK_pad/U0/NET1
  2.277                        MAC_CLK_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  5.085                        MAC_CLK_pad/U0/U0:PAD (f)
               +     0.000          net: MAC_CLK
  5.085                        MAC_CLK (f)
                                    
  5.085                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          MAC_CLK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  Delay (ns):                  1.479
  Slack (ns):
  Arrival (ns):                2.295
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         1.888


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  data required time                             N/C
  data arrival time                          -   2.295
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.816          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  0.816                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.375                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (f)
               +     0.280          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  1.655                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:A (f)
               +     0.385          cell: ADLIB:INV
  2.040                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:Y (r)
               +     0.255          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[1]
  2.295                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D (r)
                                    
  2.295                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.816          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  Delay (ns):                  1.434
  Slack (ns):
  Arrival (ns):                1.740
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         1.843


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  data required time                             N/C
  data arrival time                          -   1.740
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.306          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.306                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  0.865                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (f)
               +     0.235          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.100                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:A (f)
               +     0.385          cell: ADLIB:INV
  1.485                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:Y (r)
               +     0.255          net: TOGGLE_DIV_0/TOGGLE_DIV_0_DIVREG_OUT2to2_i_i
  1.740                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D (r)
                                    
  1.740                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.306          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          IO_2_PADOUT
  Delay (ns):                  8.115
  Slack (ns):
  Arrival (ns):                8.421
  Required (ns):
  Clock to Out (ns):           8.421


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: IO_2_PADOUT
  data required time                             N/C
  data arrival time                          -   8.421
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.306          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.306                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  0.865                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (f)
               +     0.827          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.692                        CLKINT_0/U_CLKSRC:A (f)
               +     1.316          cell: ADLIB:CLKSRC
  3.008                        CLKINT_0/U_CLKSRC:Y (f)
               +     0.568          net: CLKINT_0_Y
  3.576                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:B (f)
               +     0.476          cell: ADLIB:NOR2B
  4.052                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:Y (f)
               +     0.873          net: CoreTFTahbMaster_0_RGB_CLK
  4.925                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5 (f)
               +     0.158          cell: ADLIB:MSS_IF
  5.083                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5INT (f)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_2/U0/D_INT
  5.083                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:D (f)
               +     3.338          cell: ADLIB:IOPAD_TRI
  8.421                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:PAD (f)
               +     0.000          net: IO_2_PADOUT
  8.421                        IO_2_PADOUT (f)
                                    
  8.421                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
                                    
  N/C                          IO_2_PADOUT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q

SET Register to Register

Path 1
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D
  Delay (ns):                  8.750
  Slack (ns):
  Arrival (ns):                11.718
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         9.393

Path 2
  From:                        CoreTFTahbMaster_0/TFT_MEMDATA_EN_SYNCLEV/OUT_LEVEL:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_G[1]:D
  Delay (ns):                  7.990
  Slack (ns):
  Arrival (ns):                10.733
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         8.404

Path 3
  From:                        CoreTFTahbMaster_0/LCDCTRL/DATA_START:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D
  Delay (ns):                  7.917
  Slack (ns):
  Arrival (ns):                10.658
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         8.333

Path 4
  From:                        CoreTFTahbMaster_0/LCDCTRL/DATA_START:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_G[3]:D
  Delay (ns):                  7.829
  Slack (ns):
  Arrival (ns):                10.570
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         8.256

Path 5
  From:                        CoreTFTahbMaster_0/TFT_MEMDATA_EN_SYNCLEV/OUT_LEVEL:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D
  Delay (ns):                  7.454
  Slack (ns):
  Arrival (ns):                10.197
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.898


Expanded Path 1
  From: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To: CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D
  data required time                             N/C
  data arrival time                          -   11.718
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.869          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.869                        CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  2.184                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.784          net: CLKINT_0_Y
  2.968                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK (r)
               +     2.165          cell: ADLIB:FIFO4K18
  5.133                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RD2 (f)
               +     2.286          net: CoreTFTahbMaster_0/I_FIFO_RD_DATA[2]
  7.419                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO_0[2]:B (f)
               +     0.469          cell: ADLIB:MX2C
  7.888                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO_0[2]:Y (r)
               +     1.834          net: CoreTFTahbMaster_0/LCDCTRL/I_RAM_RD_DATA_MUX[2]
  9.722                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO[2]:B (r)
               +     0.390          cell: ADLIB:NOR2A
  10.112                       CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO[2]:Y (f)
               +     1.606          net: CoreTFTahbMaster_0/LCDCTRL/VGA_B_3[2]
  11.718                       CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D (f)
                                    
  11.718                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.869          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.550          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To:                          B_DATA1
  Delay (ns):                  8.173
  Slack (ns):
  Arrival (ns):                10.907
  Required (ns):
  Clock to Out (ns):           10.907

Path 2
  From:                        CoreTFTahbMaster_0/LCDCTRL/DATA_START:CLK
  To:                          IO_2_PADOUT
  Delay (ns):                  7.288
  Slack (ns):
  Arrival (ns):                10.029
  Required (ns):
  Clock to Out (ns):           10.029

Path 3
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_G[4]:CLK
  To:                          G_DATA4
  Delay (ns):                  6.814
  Slack (ns):
  Arrival (ns):                9.555
  Required (ns):
  Clock to Out (ns):           9.555

Path 4
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[3]:CLK
  To:                          B_DATA4
  Delay (ns):                  6.757
  Slack (ns):
  Arrival (ns):                9.491
  Required (ns):
  Clock to Out (ns):           9.491

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To:                          B_DATA0
  Delay (ns):                  6.697
  Slack (ns):
  Arrival (ns):                9.431
  Required (ns):
  Clock to Out (ns):           9.431


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To: B_DATA1
  data required time                             N/C
  data arrival time                          -   10.907
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.869          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.869                        CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  2.184                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.550          net: CLKINT_0_Y
  2.734                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  3.293                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:Q (f)
               +     3.350          net: B_DATA1_c_c
  6.643                        B_DATA1_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  7.143                        B_DATA1_pad/U0/U1:DOUT (f)
               +     0.000          net: B_DATA1_pad/U0/NET1
  7.143                        B_DATA1_pad/U0/U0:D (f)
               +     3.764          cell: ADLIB:IOPAD_TRI
  10.907                       B_DATA1_pad/U0/U0:PAD (f)
               +     0.000          net: B_DATA1
  10.907                       B_DATA1 (f)
                                    
  10.907                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
                                    
  N/C                          B_DATA1 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[4]:CLR
  Delay (ns):                  3.388
  Slack (ns):
  Arrival (ns):                6.132
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.621
  Skew (ns):                   0.008

Path 2
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/VALID_PIXEL:CLR
  Delay (ns):                  3.391
  Slack (ns):
  Arrival (ns):                6.135
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.621
  Skew (ns):                   0.005

Path 3
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_R[1]:CLR
  Delay (ns):                  3.388
  Slack (ns):
  Arrival (ns):                6.132
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.612
  Skew (ns):                   -0.001

Path 4
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/DATA_START:CLR
  Delay (ns):                  3.384
  Slack (ns):
  Arrival (ns):                6.128
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.612
  Skew (ns):                   0.003

Path 5
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/TFT_MEMDATA_EN_SYNCLEV/OUT_LEVEL:CLR
  Delay (ns):                  3.384
  Slack (ns):
  Arrival (ns):                6.128
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.610
  Skew (ns):                   0.001


Expanded Path 1
  From: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/VGA_B[4]:CLR
  data required time                             N/C
  data arrival time                          -   6.132
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.869          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.869                        CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  2.184                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.560          net: CLKINT_0_Y
  2.744                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK (r)
               +     0.440          cell: ADLIB:DFN1
  3.184                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:Q (r)
               +     0.247          net: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2
  3.431                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:B (r)
               +     0.448          cell: ADLIB:NOR2B
  3.879                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:Y (r)
               +     1.000          net: CoreTFTahbMaster_0/I_SWHW_N_RESET_SRC
  4.879                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:A (r)
               +     0.691          cell: ADLIB:CLKSRC
  5.570                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:Y (r)
               +     0.562          net: CoreTFTahbMaster_0/I_SWHW_N_RESET
  6.132                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[4]:CLR (r)
                                    
  6.132                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.869          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     1.315          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.552          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[4]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[4]:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

