Timing Report Min Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Fri Nov 23 18:14:12 2012


Design: Top_55TFT16bit_QVGA_Controller
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                3.107
Frequency (MHz):            321.854
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        6.714
External Hold (ns):         -0.667
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                26.672
Frequency (MHz):            37.493
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        5.767
External Hold (ns):         -0.010
Min Clock-To-Out (ns):      3.555
Max Clock-To-Out (ns):      9.336

Clock Domain:               mss_ccc_glc
Period (ns):                1.845
Frequency (MHz):            542.005
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.662
Max Clock-To-Out (ns):      5.085

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
Period (ns):                1.845
Frequency (MHz):            542.005
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
Period (ns):                1.865
Frequency (MHz):            536.193
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.047
Max Clock-To-Out (ns):      7.961

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
Period (ns):                8.665
Frequency (MHz):            115.407
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.265
Max Clock-To-Out (ns):      10.608

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  Delay (ns):                  2.426
  Slack (ns):
  Arrival (ns):                2.426
  Required (ns):
  Hold (ns):                   1.023


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  data arrival time                              2.426
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.562          cell: ADLIB:MSS_AHB_IP
  1.562                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.080          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  1.642                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  1.683                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     0.298          net: CoreAHBLite_0_AHBmslave16_HREADY
  1.981                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6 (r)
               +     0.036          cell: ADLIB:MSS_IF
  2.017                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6INT (r)
               +     0.409          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYINT_NET
  2.426                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY (r)
                                    
  2.426                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.023          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        SDCARD_CD
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]
  Delay (ns):                  1.021
  Slack (ns):
  Arrival (ns):                1.021
  Required (ns):
  Hold (ns):                   0.354
  External Hold (ns):          -0.667

Path 2
  From:                        SDCARD_WP
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[21]
  Delay (ns):                  1.186
  Slack (ns):
  Arrival (ns):                1.186
  Required (ns):
  Hold (ns):                   0.150
  External Hold (ns):          -1.036

Path 3
  From:                        PBUTTON[1]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  1.776
  Slack (ns):
  Arrival (ns):                1.776
  Required (ns):
  Hold (ns):                   0.354
  External Hold (ns):          -1.422

Path 4
  From:                        PBUTTON[4]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[31]
  Delay (ns):                  3.188
  Slack (ns):
  Arrival (ns):                3.188
  Required (ns):
  Hold (ns):                   0.458
  External Hold (ns):          -2.730

Path 5
  From:                        PBUTTON[3]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[30]
  Delay (ns):                  3.045
  Slack (ns):
  Arrival (ns):                3.045
  Required (ns):
  Hold (ns):                   0.095
  External Hold (ns):          -2.950


Expanded Path 1
  From: SDCARD_CD
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]
  data arrival time                              1.021
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SDCARD_CD (f)
               +     0.000          net: SDCARD_CD
  0.000                        SDCARD_CD_pad/U0/U0:PAD (f)
               +     0.292          cell: ADLIB:IOPAD_IN
  0.292                        SDCARD_CD_pad/U0/U0:Y (f)
               +     0.000          net: SDCARD_CD_pad/U0/NET1
  0.292                        SDCARD_CD_pad/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.310                        SDCARD_CD_pad/U0/U1:Y (f)
               +     0.543          net: SDCARD_CD_c
  0.853                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN5 (f)
               +     0.090          cell: ADLIB:MSS_IF
  0.943                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN5INT (f)
               +     0.078          net: MSS_new_top_0/MSS_ADLIB_INST/GPI[22]INT_NET
  1.021                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22] (f)
                                    
  1.021                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     0.354          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[22]


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          1.283


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MSS_new_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.270          net: MSS_new_top_0/GLA0
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBTOAPB3ILi_1[6]:CLK
  To:                          CoreTFTahbMaster_0/CTRL_REG[6]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.746
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBTOAPB3ILi[9]:CLK
  To:                          CoreTFTahbMaster_0/DEFAULT_RGB_DATA[9]:D
  Delay (ns):                  0.408
  Slack (ns):
  Arrival (ns):                0.738
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        CoreGPIO_0/CGPIOiOI.24.CGPIOI1[24]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.24.CGPIOOOL[24]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.724
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        CoreGPIO_0/CGPIOiOI.27.CGPIOOOL[27]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.27.CGPIOlol[27]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.724
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        CoreGPIO_0/CGPIOiOI.5.CGPIOI1[5]:CLK
  To:                          CoreGPIO_0/CGPIOiOI.5.CGPIOOOL[5]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.772
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBTOAPB3ILi_1[6]:CLK
  To: CoreTFTahbMaster_0/CTRL_REG[6]:D
  data arrival time                              0.746
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.349          net: FAB_CLK
  0.349                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBTOAPB3ILi_1[6]:CLK (r)
               +     0.248          cell: ADLIB:DFN1E1C0
  0.597                        COREAHBTOAPB3_0/CAHBtoAPB3oi0/CAHBTOAPB3ILi_1[6]:Q (r)
               +     0.149          net: _CoreAPB3_0_APBmslave2_PWDATA_[6]__1
  0.746                        CoreTFTahbMaster_0/CTRL_REG[6]:D (r)
                                    
  0.746                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.399          net: FAB_CLK
  N/C                          CoreTFTahbMaster_0/CTRL_REG[6]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1E1C0
  N/C                          CoreTFTahbMaster_0/CTRL_REG[6]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        PBUTTON[1]
  To:                          CoreGPIO_0/CGPIOiOI.5.CGPIOI1[5]:D
  Delay (ns):                  0.461
  Slack (ns):
  Arrival (ns):                0.461
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.010

Path 2
  From:                        DIP_SWITCH[1]
  To:                          CoreGPIO_0/CGPIOiOI.1.CGPIOI1[1]:D
  Delay (ns):                  1.380
  Slack (ns):
  Arrival (ns):                1.380
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.006

Path 3
  From:                        DIP_SWITCH[3]
  To:                          CoreGPIO_0/CGPIOiOI.3.CGPIOI1[3]:D
  Delay (ns):                  1.394
  Slack (ns):
  Arrival (ns):                1.394
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.023

Path 4
  From:                        DIP_SWITCH[0]
  To:                          CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D
  Delay (ns):                  1.525
  Slack (ns):
  Arrival (ns):                1.525
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.141

Path 5
  From:                        DIP_SWITCH[2]
  To:                          CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D
  Delay (ns):                  2.109
  Slack (ns):
  Arrival (ns):                2.109
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.673


Expanded Path 1
  From: PBUTTON[1]
  To: CoreGPIO_0/CGPIOiOI.5.CGPIOI1[5]:D
  data arrival time                              0.461
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PBUTTON[1] (f)
               +     0.000          net: PBUTTON[1]
  0.000                        PBUTTON_pad[1]/U0/U0:PAD (f)
               +     0.292          cell: ADLIB:IOPAD_IN
  0.292                        PBUTTON_pad[1]/U0/U0:Y (f)
               +     0.000          net: PBUTTON_pad[1]/U0/NET1
  0.292                        PBUTTON_pad[1]/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.310                        PBUTTON_pad[1]/U0/U1:Y (f)
               +     0.151          net: PBUTTON_c[1]
  0.461                        CoreGPIO_0/CGPIOiOI.5.CGPIOI1[5]:D (f)
                                    
  0.461                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.451          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOiOI.5.CGPIOI1[5]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOiOI.5.CGPIOI1[5]:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreTFTahbMaster_0/CTRL_REG[5]:CLK
  To:                          TFT_BACKLIGHT_EN
  Delay (ns):                  3.201
  Slack (ns):
  Arrival (ns):                3.555
  Required (ns):
  Clock to Out (ns):           3.555

Path 2
  From:                        CoreGPIO_0/CGPIOOI_0[0]:CLK
  To:                          LED[0]
  Delay (ns):                  3.605
  Slack (ns):
  Arrival (ns):                3.934
  Required (ns):
  Clock to Out (ns):           3.934

Path 3
  From:                        CoreGPIO_0/CGPIOOI_3[0]:CLK
  To:                          LED[3]
  Delay (ns):                  3.823
  Slack (ns):
  Arrival (ns):                4.158
  Required (ns):
  Clock to Out (ns):           4.158

Path 4
  From:                        CoreGPIO_0/CGPIOOI_2[0]:CLK
  To:                          LED[2]
  Delay (ns):                  3.981
  Slack (ns):
  Arrival (ns):                4.310
  Required (ns):
  Clock to Out (ns):           4.310

Path 5
  From:                        CoreGPIO_0/CGPIOOI_1[0]:CLK
  To:                          LED[1]
  Delay (ns):                  4.059
  Slack (ns):
  Arrival (ns):                4.394
  Required (ns):
  Clock to Out (ns):           4.394


Expanded Path 1
  From: CoreTFTahbMaster_0/CTRL_REG[5]:CLK
  To: TFT_BACKLIGHT_EN
  data arrival time                              3.555
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.354          net: FAB_CLK
  0.354                        CoreTFTahbMaster_0/CTRL_REG[5]:CLK (r)
               +     0.248          cell: ADLIB:DFN1E1C0
  0.602                        CoreTFTahbMaster_0/CTRL_REG[5]:Q (r)
               +     1.589          net: TFT_BACKLIGHT_EN_c
  2.191                        TFT_BACKLIGHT_EN_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  2.470                        TFT_BACKLIGHT_EN_pad/U0/U1:DOUT (r)
               +     0.000          net: TFT_BACKLIGHT_EN_pad/U0/NET1
  2.470                        TFT_BACKLIGHT_EN_pad/U0/U0:D (r)
               +     1.085          cell: ADLIB:IOPAD_TRI
  3.555                        TFT_BACKLIGHT_EN_pad/U0/U0:PAD (r)
               +     0.000          net: TFT_BACKLIGHT_EN
  3.555                        TFT_BACKLIGHT_EN (r)
                                    
  3.555                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          TFT_BACKLIGHT_EN (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  2.010
  Slack (ns):
  Arrival (ns):                2.383
  Required (ns):
  Removal (ns):                0.196
  Skew (ns):                   -0.059

Path 2
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  2.318
  Slack (ns):
  Arrival (ns):                2.691
  Required (ns):
  Removal (ns):                0.196
  Skew (ns):                   -0.060

Path 3
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  2.342
  Slack (ns):
  Arrival (ns):                2.691
  Required (ns):
  Removal (ns):                0.196
  Skew (ns):                   -0.083

Path 4
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  2.650
  Slack (ns):
  Arrival (ns):                2.999
  Required (ns):
  Removal (ns):                0.196
  Skew (ns):                   -0.084


Expanded Path 1
  From: CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  data arrival time                              2.383
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.373          net: FAB_CLK
  0.373                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK (r)
               +     0.248          cell: ADLIB:DFN1E1C0
  0.621                        CoreTFTahbMaster_0/CTRL_REG[6]:Q (r)
               +     0.517          net: CoreTFTahbMaster_0/CTRL_REG[6]
  1.138                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:A (r)
               +     0.221          cell: ADLIB:NOR2A
  1.359                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:Y (r)
               +     1.024          net: CoreTFTahbMaster_0/OUTF_PULSE_RNITR1U
  2.383                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET (r)
                                    
  2.383                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.432          net: FAB_CLK
  N/C                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:WCLK (r)
               +     0.196          Library removal time: ADLIB:FIFO4K18
  N/C                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  Delay (ns):                  0.697
  Slack (ns):
  Arrival (ns):                1.015
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  data arrival time                              1.015
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.318          net: MAC_CLK_c
  0.318                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.566                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.144          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  0.710                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:A (r)
               +     0.158          cell: ADLIB:INV
  0.868                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:Y (f)
               +     0.147          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[0]
  1.015                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D (f)
                                    
  1.015                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.333          net: MAC_CLK_c
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          MAC_CLK
  Delay (ns):                  2.662
  Slack (ns):
  Arrival (ns):                2.662
  Required (ns):
  Clock to Out (ns):           2.662


Expanded Path 1
  From: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: MAC_CLK
  data arrival time                              2.662
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     0.957          cell: ADLIB:MSS_CCC_IP
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.310          net: MAC_CLK_c
  1.267                        MAC_CLK_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  1.546                        MAC_CLK_pad/U0/U1:DOUT (r)
               +     0.000          net: MAC_CLK_pad/U0/NET1
  1.546                        MAC_CLK_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.662                        MAC_CLK_pad/U0/U0:PAD (r)
               +     0.000          net: MAC_CLK
  2.662                        MAC_CLK (r)
                                    
  2.662                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          MAC_CLK (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  Delay (ns):                  0.697
  Slack (ns):
  Arrival (ns):                1.281
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  data arrival time                              1.281
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.584          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  0.584                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.832                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.144          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.976                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:A (r)
               +     0.158          cell: ADLIB:INV
  1.134                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:Y (f)
               +     0.147          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[1]
  1.281                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D (f)
                                    
  1.281                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.701          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  Delay (ns):                  0.710
  Slack (ns):
  Arrival (ns):                1.235
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  data arrival time                              1.235
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.525          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.525                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.773                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.157          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.930                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:A (r)
               +     0.158          cell: ADLIB:INV
  1.088                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:Y (f)
               +     0.147          net: TOGGLE_DIV_0/TOGGLE_DIV_0_DIVREG_OUT2to2_i_i
  1.235                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D (f)
                                    
  1.235                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.631          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          IO_2_PADOUT
  Delay (ns):                  3.522
  Slack (ns):
  Arrival (ns):                4.047
  Required (ns):
  Clock to Out (ns):           4.047


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: IO_2_PADOUT
  data arrival time                              4.047
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.525          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.525                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.773                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.571          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.344                        CLKINT_0/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  1.673                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.330          net: CLKINT_0_Y
  2.003                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:A (r)
               +     0.209          cell: ADLIB:NOR2B
  2.212                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:Y (r)
               +     0.307          net: CoreTFTahbMaster_0_RGB_CLK
  2.519                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  2.621                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5INT (r)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_2/U0/D_INT
  2.621                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:D (r)
               +     1.426          cell: ADLIB:IOPAD_TRI
  4.047                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:PAD (r)
               +     0.000          net: IO_2_PADOUT
  4.047                        IO_2_PADOUT (r)
                                    
  4.047                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
                                    
  N/C                          IO_2_PADOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q

SET Register to Register

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:D
  Delay (ns):                  0.393
  Slack (ns):
  Arrival (ns):                1.626
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_1:CLK
  To:                          CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:D
  Delay (ns):                  0.393
  Slack (ns):
  Arrival (ns):                1.611
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/H_SYNC:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/I_H_SYNC1:D
  Delay (ns):                  0.393
  Slack (ns):
  Arrival (ns):                1.619
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        CoreTFTahbMaster_0/TFT_MEMDATA_EN_SYNCLEV/INTERNAL_IN_LEVEL:CLK
  To:                          CoreTFTahbMaster_0/TFT_MEMDATA_EN_SYNCLEV/OUT_LEVEL:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                1.627
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/I_H_SYNC1:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_h_sync:D
  Delay (ns):                  0.750
  Slack (ns):
  Arrival (ns):                1.973
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:D
  data arrival time                              1.626
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.571          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.571                        CLKINT_0/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  0.900                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.333          net: CLKINT_0_Y
  1.233                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:CLK (r)
               +     0.248          cell: ADLIB:DFN1E1P0
  1.481                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:Q (r)
               +     0.145          net: CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA_VGA_TIMING0/I_V_SYNC_0
  1.626                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:D (r)
                                    
  1.626                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.571          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.351          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_R[3]:CLK
  To:                          IO_11_PADOUT
  Delay (ns):                  2.035
  Slack (ns):
  Arrival (ns):                3.265
  Required (ns):
  Clock to Out (ns):           3.265

Path 2
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_data_en:CLK
  To:                          IO_5_PADOUT
  Delay (ns):                  2.081
  Slack (ns):
  Arrival (ns):                3.314
  Required (ns):
  Clock to Out (ns):           3.314

Path 3
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_G[0]:CLK
  To:                          IO_9_PADOUT
  Delay (ns):                  2.228
  Slack (ns):
  Arrival (ns):                3.451
  Required (ns):
  Clock to Out (ns):           3.451

Path 4
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_G[4]:CLK
  To:                          G_DATA4
  Delay (ns):                  2.277
  Slack (ns):
  Arrival (ns):                3.492
  Required (ns):
  Clock to Out (ns):           3.492

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[4]:CLK
  To:                          B_DATA5
  Delay (ns):                  2.277
  Slack (ns):
  Arrival (ns):                3.495
  Required (ns):
  Clock to Out (ns):           3.495


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/VGA_R[3]:CLK
  To: IO_11_PADOUT
  data arrival time                              3.265
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.571          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.571                        CLKINT_0/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  0.900                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.330          net: CLKINT_0_Y
  1.230                        CoreTFTahbMaster_0/LCDCTRL/VGA_R[3]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  1.478                        CoreTFTahbMaster_0/LCDCTRL/VGA_R[3]:Q (r)
               +     0.324          net: CoreTFTahbMaster_0_R_DATA4to4
  1.802                        MSS_new_top_0/FIO_OUTBUF_11/U0/U1:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  1.839                        MSS_new_top_0/FIO_OUTBUF_11/U0/U1:PIN5INT (r)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_11/U0/D_INT
  1.839                        MSS_new_top_0/FIO_OUTBUF_11/U0/U0:D (r)
               +     1.426          cell: ADLIB:IOPAD_TRI
  3.265                        MSS_new_top_0/FIO_OUTBUF_11/U0/U0:PAD (r)
               +     0.000          net: IO_11_PADOUT
  3.265                        IO_11_PADOUT (r)
                                    
  3.265                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
                                    
  N/C                          IO_11_PADOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[4]:CLR
  Delay (ns):                  1.672
  Slack (ns):
  Arrival (ns):                2.890
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.039

Path 2
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[3]:CLR
  Delay (ns):                  1.672
  Slack (ns):
  Arrival (ns):                2.890
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.039

Path 3
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[5]:CLR
  Delay (ns):                  1.672
  Slack (ns):
  Arrival (ns):                2.890
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.039

Path 4
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[2]:CLR
  Delay (ns):                  1.668
  Slack (ns):
  Arrival (ns):                2.886
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.033

Path 5
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/I_V_SYNC:PRE
  Delay (ns):                  1.668
  Slack (ns):
  Arrival (ns):                2.886
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.033


Expanded Path 1
  From: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[4]:CLR
  data arrival time                              2.890
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.571          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.571                        CLKINT_0/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  0.900                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.318          net: CLKINT_0_Y
  1.218                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK (r)
               +     0.248          cell: ADLIB:DFN1
  1.466                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:Q (r)
               +     0.145          net: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2
  1.611                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:B (r)
               +     0.252          cell: ADLIB:NOR2B
  1.863                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:Y (r)
               +     0.324          net: CoreTFTahbMaster_0/I_SWHW_N_RESET_SRC
  2.187                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:A (r)
               +     0.390          cell: ADLIB:CLKSRC
  2.577                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:Y (r)
               +     0.313          net: CoreTFTahbMaster_0/I_SWHW_N_RESET
  2.890                        CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[4]:CLR (r)
                                    
  2.890                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.571          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.357          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[4]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1E1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_CNT[4]:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

