Timing Report Max Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Fri Nov 23 18:14:09 2012


Design: Top_55TFT16bit_QVGA_Controller
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                3.107
Frequency (MHz):            321.854
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        6.714
External Hold (ns):         -0.667
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                26.672
Frequency (MHz):            37.493
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        5.767
External Hold (ns):         -0.010
Min Clock-To-Out (ns):      3.555
Max Clock-To-Out (ns):      9.336

Clock Domain:               mss_ccc_glc
Period (ns):                1.845
Frequency (MHz):            542.005
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.662
Max Clock-To-Out (ns):      5.085

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
Period (ns):                1.845
Frequency (MHz):            542.005
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
Period (ns):                1.865
Frequency (MHz):            536.193
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.047
Max Clock-To-Out (ns):      7.961

Clock Domain:               TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
Period (ns):                8.665
Frequency (MHz):            115.407
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.265
Max Clock-To-Out (ns):      10.608

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  Delay (ns):                  4.250
  Slack (ns):
  Arrival (ns):                4.250
  Required (ns):
  Setup (ns):                  -1.143
  Minimum Period (ns):         3.107


Expanded Path 1
  From: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY
  data required time                             N/C
  data arrival time                          -   4.250
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.773          cell: ADLIB:MSS_AHB_IP
  2.773                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.136          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  2.909                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.074          cell: ADLIB:MSS_IF
  2.983                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     0.508          net: CoreAHBLite_0_AHBmslave16_HREADY
  3.491                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6 (r)
               +     0.063          cell: ADLIB:MSS_IF
  3.554                        MSS_new_top_0/MSS_ADLIB_INST/U_92:PIN6INT (r)
               +     0.696          net: MSS_new_top_0/MSS_ADLIB_INST/FABHREADYINT_NET
  4.250                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY (r)
                                    
  4.250                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               -    -1.143          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FABHREADY


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        PBUTTON[0]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23]
  Delay (ns):                  7.092
  Slack (ns):
  Arrival (ns):                7.092
  Required (ns):
  Setup (ns):                  -0.378
  External Setup (ns):         6.714

Path 2
  From:                        PBUTTON[2]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[29]
  Delay (ns):                  6.304
  Slack (ns):
  Arrival (ns):                6.304
  Required (ns):
  Setup (ns):                  -0.304
  External Setup (ns):         6.000

Path 3
  From:                        PBUTTON[3]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[30]
  Delay (ns):                  5.296
  Slack (ns):
  Arrival (ns):                5.296
  Required (ns):
  Setup (ns):                  0.350
  External Setup (ns):         5.646

Path 4
  From:                        PBUTTON[4]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[31]
  Delay (ns):                  5.529
  Slack (ns):
  Arrival (ns):                5.529
  Required (ns):
  Setup (ns):                  -0.381
  External Setup (ns):         5.148

Path 5
  From:                        PBUTTON[1]
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  3.204
  Slack (ns):
  Arrival (ns):                3.204
  Required (ns):
  Setup (ns):                  -0.228
  External Setup (ns):         2.976


Expanded Path 1
  From: PBUTTON[0]
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23]
  data required time                             N/C
  data arrival time                          -   7.092
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PBUTTON[0] (r)
               +     0.000          net: PBUTTON[0]
  0.000                        PBUTTON_pad[0]/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        PBUTTON_pad[0]/U0/U0:Y (r)
               +     0.000          net: PBUTTON_pad[0]/U0/NET1
  0.806                        PBUTTON_pad[0]/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        PBUTTON_pad[0]/U0/U1:Y (r)
               +     5.971          net: PBUTTON_c[0]
  6.810                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN4 (r)
               +     0.180          cell: ADLIB:MSS_IF
  6.990                        MSS_new_top_0/MSS_ADLIB_INST/U_4:PIN4INT (r)
               +     0.102          net: MSS_new_top_0/MSS_ADLIB_INST/GPI[23]INT_NET
  7.092                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23] (r)
                                    
  7.092                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               -    -0.378          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:GPI[23]


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -1.383


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_new_top_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_new_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.382          net: MSS_new_top_0/GLA0
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[7]:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[15]:E
  Delay (ns):                  11.058
  Slack (ns):
  Arrival (ns):                11.638
  Required (ns):
  Setup (ns):                  0.461
  Minimum Period (ns):         22.994

Path 2
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[7]:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[12]:E
  Delay (ns):                  11.043
  Slack (ns):
  Arrival (ns):                11.623
  Required (ns):
  Setup (ns):                  0.461
  Minimum Period (ns):         22.984

Path 3
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[7]:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[13]:E
  Delay (ns):                  10.948
  Slack (ns):
  Arrival (ns):                11.528
  Required (ns):
  Setup (ns):                  0.461
  Minimum Period (ns):         22.784

Path 4
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[6]:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[15]:E
  Delay (ns):                  10.942
  Slack (ns):
  Arrival (ns):                11.510
  Required (ns):
  Setup (ns):                  0.461
  Minimum Period (ns):         22.738

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[6]:CLK
  To:                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[12]:E
  Delay (ns):                  10.927
  Slack (ns):
  Arrival (ns):                11.495
  Required (ns):
  Setup (ns):                  0.461
  Minimum Period (ns):         22.728


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[7]:CLK
  To: CoreTFTahbMaster_0/I_FIFO_WR_DATA[15]:E
  data required time                             N/C
  data arrival time                          -   11.638
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.580          net: FAB_CLK
  0.580                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[7]:CLK (r)
               +     0.559          cell: ADLIB:DFN1E1C0
  1.139                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[7]:Q (f)
               +     0.289          net: CoreAHBLite_0/matrix2x16/masterstage_0/xhdl1222[7]
  1.428                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI1N0A_0[6]:B (f)
               +     0.490          cell: ADLIB:NOR2
  1.918                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI1N0A_0[6]:Y (r)
               +     1.630          net: CoreAHBLite_0/matrix2x16/masterstage_0/hready_m_xhdl396_4
  3.548                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNITRBJ1[6]:C (r)
               +     0.505          cell: ADLIB:OR3C
  4.053                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNITRBJ1[6]:Y (f)
               +     0.700          net: CoreAHBLite_0/matrix2x16/masterstage_0/HRESP_iv_i_o3_0_3_m8_0_o4_0
  4.753                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIG9D72[1]:C (f)
               +     0.504          cell: ADLIB:OR3A
  5.257                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIG9D72[1]:Y (f)
               +     0.255          net: CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIG9D72[1]
  5.512                        CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNIP8ET5:B (f)
               +     0.482          cell: ADLIB:AO1A
  5.994                        CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNIP8ET5:Y (f)
               +     0.247          net: CoreAHBLite_0/matrix2x16/masterstage_0/HRESP_iv_i_o3_0_3_m8_0_0
  6.241                        CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNIVUASG:C (f)
               +     0.480          cell: ADLIB:AO1
  6.721                        CoreAHBLite_0/matrix2x16/masterstage_0/RESERVEDDATASELInt_RNIVUASG:Y (f)
               +     1.688          net: RESERVEDDATASELInt_RNIVUASG
  8.409                        CoreTFTahbMaster_0/un3_valid_0_a3_0_1:A (f)
               +     0.486          cell: ADLIB:NOR3A
  8.895                        CoreTFTahbMaster_0/un3_valid_0_a3_0_1:Y (f)
               +     0.247          net: CoreTFTahbMaster_0/un3_valid_0_a3_0_1
  9.142                        CoreTFTahbMaster_0/MemCntlState_RNIS46691[0]:B (f)
               +     0.460          cell: ADLIB:NOR3B
  9.602                        CoreTFTahbMaster_0/MemCntlState_RNIS46691[0]:Y (f)
               +     2.036          net: CoreTFTahbMaster_0/N_613
  11.638                       CoreTFTahbMaster_0/I_FIFO_WR_DATA[15]:E (f)
                                    
  11.638                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (f)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (f)
               +     0.602          net: FAB_CLK
  N/C                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[15]:CLK (f)
               -     0.461          Library setup time: ADLIB:DFN0E1C0
  N/C                          CoreTFTahbMaster_0/I_FIFO_WR_DATA[15]:E


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        PBUTTON[2]
  To:                          CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D
  Delay (ns):                  5.945
  Slack (ns):
  Arrival (ns):                5.945
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         5.767

Path 2
  From:                        PBUTTON[0]
  To:                          CoreGPIO_0/CGPIOiOI.4.CGPIOI1[4]:D
  Delay (ns):                  5.327
  Slack (ns):
  Arrival (ns):                5.327
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         5.116

Path 3
  From:                        PBUTTON[4]
  To:                          CoreGPIO_0/CGPIOiOI.8.CGPIOI1[8]:D
  Delay (ns):                  4.245
  Slack (ns):
  Arrival (ns):                4.245
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         4.034

Path 4
  From:                        PBUTTON[3]
  To:                          CoreGPIO_0/CGPIOiOI.7.CGPIOI1[7]:D
  Delay (ns):                  3.933
  Slack (ns):
  Arrival (ns):                3.933
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         3.746

Path 5
  From:                        DIP_SWITCH[2]
  To:                          CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D
  Delay (ns):                  3.738
  Slack (ns):
  Arrival (ns):                3.738
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         3.555


Expanded Path 1
  From: PBUTTON[2]
  To: CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D
  data required time                             N/C
  data arrival time                          -   5.945
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PBUTTON[2] (r)
               +     0.000          net: PBUTTON[2]
  0.000                        PBUTTON_pad[2]/U0/U0:PAD (r)
               +     0.779          cell: ADLIB:IOPAD_IN
  0.779                        PBUTTON_pad[2]/U0/U0:Y (r)
               +     0.000          net: PBUTTON_pad[2]/U0/NET1
  0.779                        PBUTTON_pad[2]/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.812                        PBUTTON_pad[2]/U0/U1:Y (r)
               +     5.133          net: PBUTTON_c[2]
  5.945                        CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D (r)
                                    
  5.945                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.613          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOiOI.6.CGPIOI1[6]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]:CLK
  To:                          LED[2]
  Delay (ns):                  8.714
  Slack (ns):
  Arrival (ns):                9.336
  Required (ns):
  Clock to Out (ns):           9.336

Path 2
  From:                        CoreGPIO_0/CGPIOiOI.3.CGPIOI1I.CGPIOo0[3]:CLK
  To:                          LED[3]
  Delay (ns):                  8.675
  Slack (ns):
  Arrival (ns):                9.297
  Required (ns):
  Clock to Out (ns):           9.297

Path 3
  From:                        CoreGPIO_0/CGPIOiOI.0.CGPIOI1I.CGPIOo0[0]:CLK
  To:                          LED[0]
  Delay (ns):                  8.606
  Slack (ns):
  Arrival (ns):                9.178
  Required (ns):
  Clock to Out (ns):           9.178

Path 4
  From:                        CoreGPIO_0/CGPIOiOI.1.CGPIOI1I.CGPIOo0[1]:CLK
  To:                          LED[1]
  Delay (ns):                  8.270
  Slack (ns):
  Arrival (ns):                8.842
  Required (ns):
  Clock to Out (ns):           8.842

Path 5
  From:                        CoreGPIO_0/CGPIOOI_1[0]:CLK
  To:                          LED[1]
  Delay (ns):                  8.121
  Slack (ns):
  Arrival (ns):                8.693
  Required (ns):
  Clock to Out (ns):           8.693


Expanded Path 1
  From: CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]:CLK
  To: LED[2]
  data required time                             N/C
  data arrival time                          -   9.336
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.622          net: FAB_CLK
  0.622                        CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]:CLK (r)
               +     0.559          cell: ADLIB:DFN1E1C0
  1.181                        CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0[2]:Q (f)
               +     0.883          net: CoreGPIO_0/CGPIOo0[2]
  2.064                        CoreGPIO_0/CGPIOOI_2_RNI6VPM[0]:B (f)
               +     0.476          cell: ADLIB:NOR2B
  2.540                        CoreGPIO_0/CGPIOOI_2_RNI6VPM[0]:Y (f)
               +     3.546          net: CoreGPIO_0_N_731
  6.086                        LED_pad[2]/U0/U1:D (f)
               +     0.442          cell: ADLIB:IOTRI_OB_EB
  6.528                        LED_pad[2]/U0/U1:DOUT (f)
               +     0.000          net: LED_pad[2]/U0/NET1
  6.528                        LED_pad[2]/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  9.336                        LED_pad[2]/U0/U0:PAD (f)
               +     0.000          net: LED[2]
  9.336                        LED[2] (f)
                                    
  9.336                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          LED[2] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  4.522
  Slack (ns):
  Arrival (ns):                5.118
  Required (ns):
  Recovery (ns):               1.523
  Minimum Period (ns):         5.956
  Skew (ns):                   -0.089

Path 2
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  Delay (ns):                  3.982
  Slack (ns):
  Arrival (ns):                4.618
  Required (ns):
  Recovery (ns):               1.523
  Minimum Period (ns):         5.456
  Skew (ns):                   -0.049

Path 3
  From:                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  3.996
  Slack (ns):
  Arrival (ns):                4.592
  Required (ns):
  Recovery (ns):               1.523
  Minimum Period (ns):         5.431
  Skew (ns):                   -0.088

Path 4
  From:                        CoreTFTahbMaster_0/CTRL_REG[6]:CLK
  To:                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RESET
  Delay (ns):                  3.456
  Slack (ns):
  Arrival (ns):                4.092
  Required (ns):
  Recovery (ns):               1.523
  Minimum Period (ns):         4.931
  Skew (ns):                   -0.048


Expanded Path 1
  From: CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK
  To: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET
  data required time                             N/C
  data arrival time                          -   5.118
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.596          net: FAB_CLK
  0.596                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.155                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE:Q (f)
               +     1.385          net: CoreTFTahbMaster_0/I_TFTDATA_START_RIS
  2.540                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:B (f)
               +     0.308          cell: ADLIB:NOR2A
  2.848                        CoreTFTahbMaster_0/I_TFTDATA_START_PULSE/OUTF_PULSE_RNITR1U:Y (r)
               +     2.270          net: CoreTFTahbMaster_0/OUTF_PULSE_RNITR1U
  5.118                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET (r)
                                    
  5.118                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.685          net: FAB_CLK
  N/C                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:WCLK (r)
               -     1.523          Library recovery time: ADLIB:FIFO4K18
  N/C                          CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  Delay (ns):                  1.436
  Slack (ns):
  Arrival (ns):                1.981
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         1.845


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D
  data required time                             N/C
  data arrival time                          -   1.981
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.545          net: MAC_CLK_c
  0.545                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.104                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (f)
               +     0.237          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  1.341                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:A (f)
               +     0.385          cell: ADLIB:INV
  1.726                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG_RNO[0]:Y (r)
               +     0.255          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[0]
  1.981                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D (r)
                                    
  1.981                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.545          net: MAC_CLK_c
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_new_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          MAC_CLK
  Delay (ns):                  5.085
  Slack (ns):
  Arrival (ns):                5.085
  Required (ns):
  Clock to Out (ns):           5.085


Expanded Path 1
  From: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: MAC_CLK
  data required time                             N/C
  data arrival time                          -   5.085
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     1.246          cell: ADLIB:MSS_CCC_IP
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (f)
               +     0.000          net: MSS_new_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        MSS_new_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (f)
               +     0.531          net: MAC_CLK_c
  1.777                        MAC_CLK_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  2.277                        MAC_CLK_pad/U0/U1:DOUT (f)
               +     0.000          net: MAC_CLK_pad/U0/NET1
  2.277                        MAC_CLK_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  5.085                        MAC_CLK_pad/U0/U0:PAD (f)
               +     0.000          net: MAC_CLK
  5.085                        MAC_CLK (f)
                                    
  5.085                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_new_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          MAC_CLK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  Delay (ns):                  1.436
  Slack (ns):
  Arrival (ns):                2.431
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         1.845


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D
  data required time                             N/C
  data arrival time                          -   2.431
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.995          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  0.995                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.554                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (f)
               +     0.237          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  1.791                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:A (f)
               +     0.385          cell: ADLIB:INV
  2.176                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG_RNO[1]:Y (r)
               +     0.255          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1_i_i[1]
  2.431                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D (r)
                                    
  2.431                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.0.TOGGLEDIV_REG.I_DIVREG[0]:Q (r)
               +     0.995          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[0]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q

SET Register to Register

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  Delay (ns):                  1.456
  Slack (ns):
  Arrival (ns):                2.351
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         1.865


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D
  data required time                             N/C
  data arrival time                          -   2.351
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.895          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.895                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.454                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (f)
               +     0.257          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  1.711                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:A (f)
               +     0.385          cell: ADLIB:INV
  2.096                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG_RNO[2]:Y (r)
               +     0.255          net: TOGGLE_DIV_0/TOGGLE_DIV_0_DIVREG_OUT2to2_i_i
  2.351                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D (r)
                                    
  2.351                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.895          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To:                          IO_2_PADOUT
  Delay (ns):                  7.066
  Slack (ns):
  Arrival (ns):                7.961
  Required (ns):
  Clock to Out (ns):           7.961


Expanded Path 1
  From: TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK
  To: IO_2_PADOUT
  data required time                             N/C
  data arrival time                          -   7.961
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
               +     0.895          net: TOGGLE_DIV_0/un1_TOGGLE_DIV_0_1[1]
  0.895                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.454                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (f)
               +     0.915          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  2.369                        CLKINT_0/U_CLKSRC:A (f)
               +     0.599          cell: ADLIB:CLKSRC
  2.968                        CLKINT_0/U_CLKSRC:Y (f)
               +     0.559          net: CLKINT_0_Y
  3.527                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:A (f)
               +     0.390          cell: ADLIB:NOR2B
  3.917                        CoreTFTahbMaster_0/LCDCTRL/DATA_START_RNI0TGK:Y (f)
               +     0.548          net: CoreTFTahbMaster_0_RGB_CLK
  4.465                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5 (f)
               +     0.158          cell: ADLIB:MSS_IF
  4.623                        MSS_new_top_0/FIO_OUTBUF_2/U0/U1:PIN5INT (f)
               +     0.000          net: MSS_new_top_0/FIO_OUTBUF_2/U0/D_INT
  4.623                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:D (f)
               +     3.338          cell: ADLIB:IOPAD_TRI
  7.961                        MSS_new_top_0/FIO_OUTBUF_2/U0/U0:PAD (f)
               +     0.000          net: IO_2_PADOUT
  7.961                        IO_2_PADOUT (f)
                                    
  7.961                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.1.TOGGLEDIV_REG.I_DIVREG[1]:Q (r)
                                    
  N/C                          IO_2_PADOUT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q

SET Register to Register

Path 1
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D
  Delay (ns):                  8.080
  Slack (ns):
  Arrival (ns):                10.318
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         8.665

Path 2
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[4]:D
  Delay (ns):                  7.587
  Slack (ns):
  Arrival (ns):                9.825
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         8.163

Path 3
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[3]:D
  Delay (ns):                  6.842
  Slack (ns):
  Arrival (ns):                9.080
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         7.392

Path 4
  From:                        CoreTFTahbMaster_0/TFT_MEMDATA_EN_SYNCLEV/OUT_LEVEL:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D
  Delay (ns):                  6.681
  Slack (ns):
  Arrival (ns):                8.798
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.145

Path 5
  From:                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_1_inst:RCLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_G[4]:D
  Delay (ns):                  6.405
  Slack (ns):
  Arrival (ns):                8.652
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         6.966


Expanded Path 1
  From: CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK
  To: CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D
  data required time                             N/C
  data arrival time                          -   10.318
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.973          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.973                        CLKINT_0/U_CLKSRC:A (r)
               +     0.583          cell: ADLIB:CLKSRC
  1.556                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.682          net: CLKINT_0_Y
  2.238                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RCLK (r)
               +     2.198          cell: ADLIB:FIFO4K18
  4.436                        CoreTFTahbMaster_0/GEN512_HIGHFLAGS.FIFO0/FIFOBLOCK_0_inst:RD2 (r)
               +     0.946          net: CoreTFTahbMaster_0/I_FIFO_RD_DATA[2]
  5.382                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO_0[2]:B (r)
               +     0.514          cell: ADLIB:MX2
  5.896                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO_0[2]:Y (r)
               +     1.609          net: CoreTFTahbMaster_0/LCDCTRL/I_RAM_RD_DATA_MUX[2]
  7.505                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO[2]:A (r)
               +     0.370          cell: ADLIB:NOR2B
  7.875                        CoreTFTahbMaster_0/LCDCTRL/VGA_B_RNO[2]:Y (r)
               +     2.443          net: CoreTFTahbMaster_0/LCDCTRL/VGA_B_3[2]
  10.318                       CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D (r)
                                    
  10.318                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.973          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     0.583          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.532          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To:                          B_DATA1
  Delay (ns):                  8.500
  Slack (ns):
  Arrival (ns):                10.608
  Required (ns):
  Clock to Out (ns):           10.608

Path 2
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_G[3]:CLK
  To:                          G_DATA3
  Delay (ns):                  7.489
  Slack (ns):
  Arrival (ns):                9.607
  Required (ns):
  Clock to Out (ns):           9.607

Path 3
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To:                          B_DATA0
  Delay (ns):                  6.744
  Slack (ns):
  Arrival (ns):                8.852
  Required (ns):
  Clock to Out (ns):           8.852

Path 4
  From:                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[2]:CLK
  To:                          B_DATA3
  Delay (ns):                  6.521
  Slack (ns):
  Arrival (ns):                8.609
  Required (ns):
  Clock to Out (ns):           8.609

Path 5
  From:                        CoreTFTahbMaster_0/LCDCTRL/DATA_START:CLK
  To:                          TFT_PWR_EN
  Delay (ns):                  6.363
  Slack (ns):
  Arrival (ns):                8.471
  Required (ns):
  Clock to Out (ns):           8.471


Expanded Path 1
  From: CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK
  To: B_DATA1
  data required time                             N/C
  data arrival time                          -   10.608
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.973          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.973                        CLKINT_0/U_CLKSRC:A (r)
               +     0.583          cell: ADLIB:CLKSRC
  1.556                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.552          net: CLKINT_0_Y
  2.108                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  2.667                        CoreTFTahbMaster_0/LCDCTRL/VGA_B[0]:Q (f)
               +     3.677          net: B_DATA1_c_c
  6.344                        B_DATA1_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  6.844                        B_DATA1_pad/U0/U1:DOUT (f)
               +     0.000          net: B_DATA1_pad/U0/NET1
  6.844                        B_DATA1_pad/U0/U0:D (f)
               +     3.764          cell: ADLIB:IOPAD_TRI
  10.608                       B_DATA1_pad/U0/U0:PAD (f)
               +     0.000          net: B_DATA1
  10.608                       B_DATA1 (f)
                                    
  10.608                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
                                    
  N/C                          B_DATA1 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/I_H_SYNC1:CLR
  Delay (ns):                  2.934
  Slack (ns):
  Arrival (ns):                5.031
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.148
  Skew (ns):                   -0.011

Path 2
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/V_SYNC:PRE
  Delay (ns):                  2.948
  Slack (ns):
  Arrival (ns):                5.045
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.145
  Skew (ns):                   -0.028

Path 3
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/H_CNT[8]:CLR
  Delay (ns):                  2.948
  Slack (ns):
  Arrival (ns):                5.045
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.145
  Skew (ns):                   -0.028

Path 4
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/VGA_R[3]:CLR
  Delay (ns):                  2.939
  Slack (ns):
  Arrival (ns):                5.036
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.143
  Skew (ns):                   -0.021

Path 5
  From:                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To:                          CoreTFTahbMaster_0/LCDCTRL/GEN_QVGA.VGA_TIMING0/H_SYNC:PRE
  Delay (ns):                  2.931
  Slack (ns):
  Arrival (ns):                5.028
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.141
  Skew (ns):                   -0.015


Expanded Path 1
  From: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK
  To: CoreTFTahbMaster_0/LCDCTRL/I_H_SYNC1:CLR
  data required time                             N/C
  data arrival time                          -   5.031
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  0.000                        TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.973          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  0.973                        CLKINT_0/U_CLKSRC:A (r)
               +     0.583          cell: ADLIB:CLKSRC
  1.556                        CLKINT_0/U_CLKSRC:Y (r)
               +     0.541          net: CLKINT_0_Y
  2.097                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:CLK (r)
               +     0.440          cell: ADLIB:DFN1
  2.537                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2:Q (r)
               +     0.247          net: CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2
  2.784                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:B (r)
               +     0.448          cell: ADLIB:NOR2B
  3.232                        CoreTFTahbMaster_0/RESCTRL/I_SWHWRES66M_2_RNIPFL6:Y (r)
               +     0.551          net: CoreTFTahbMaster_0/I_SWHW_N_RESET_SRC
  3.783                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:A (r)
               +     0.691          cell: ADLIB:CLKSRC
  4.474                        CoreTFTahbMaster_0/SWHWRES_BUF/U_CLKSRC:Y (r)
               +     0.557          net: CoreTFTahbMaster_0/I_SWHW_N_RESET
  5.031                        CoreTFTahbMaster_0/LCDCTRL/I_H_SYNC1:CLR (r)
                                    
  5.031                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q
               +     0.000          Clock source
  N/C                          TOGGLE_DIV_0/DIVREG_GEN.2.TOGGLEDIV_REG.I_DIVREG[2]:Q (r)
               +     0.973          net: TOGGLE_DIV_0_DIVREG_OUT2to2
  N/C                          CLKINT_0/U_CLKSRC:A (r)
               +     0.583          cell: ADLIB:CLKSRC
  N/C                          CLKINT_0/U_CLKSRC:Y (r)
               +     0.552          net: CLKINT_0_Y
  N/C                          CoreTFTahbMaster_0/LCDCTRL/I_H_SYNC1:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  N/C                          CoreTFTahbMaster_0/LCDCTRL/I_H_SYNC1:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

