#Build: Synplify Pro 8.5F, Build 001R, Mar 7 2006 #install: D:\Libero72\Synplify\Synplify_85F #OS: Windows XP 5.1 #Hostname: WXP-WONGAL #Tue Sep 25 15:46:52 2007 $ Start of Compile #Tue Sep 25 15:46:52 2007 Synplicity VHDL Compiler, version 3.4.1, Build 137R, built Apr 7 2006 Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved @N: : config_top.vhd(42) | Top entity is set to config_top. VHDL syntax check successful! Options changed - recompiling @N:CD630 : config_top.vhd(26) | Synthesizing work.config_top.rtl @W:CD638 : config_top.vhd(86) | Signal busy1 is undriven @W:CD638 : config_top.vhd(87) | Signal busy2 is undriven @N:CD630 : nvm_2_blocks.vhd(23) | Synthesizing work.nvm_2_blocks.rtl @N:CD630 : nvm2.vhd(8) | Synthesizing work.nvm2.def_arch @N:CD630 : fusion.vhd(4474) | Synthesizing fusion.nvm.syn_black_box Post processing for fusion.nvm.syn_black_box @N:CD630 : fusion.vhd(3021) | Synthesizing fusion.vcc.syn_black_box Post processing for fusion.vcc.syn_black_box @N:CD630 : fusion.vhd(1901) | Synthesizing fusion.gnd.syn_black_box Post processing for fusion.gnd.syn_black_box Post processing for work.nvm2.def_arch @W:CL168 : nvm2.vhd(144) | Pruning instance VCC_power_inst1 - not in use ... @N:CD630 : nvm1.vhd(8) | Synthesizing work.nvm1.def_arch Post processing for work.nvm1.def_arch @W:CL168 : nvm1.vhd(144) | Pruning instance VCC_power_inst1 - not in use ... Post processing for work.nvm_2_blocks.rtl @N:CD630 : sconfig.vhd(26) | Synthesizing work.sconfig.rtl @N:CD630 : ram256x8.vhd(7) | Synthesizing work.ram256x8.def_arch @N:CD630 : fusion.vhd(3184) | Synthesizing fusion.ram4k9.syn_black_box Post processing for fusion.ram4k9.syn_black_box @N:CD630 : fusion.vhd(2119) | Synthesizing fusion.inv.syn_black_box Post processing for fusion.inv.syn_black_box Post processing for work.ram256x8.def_arch Post processing for work.sconfig.rtl @W:CL170 : sconfig.vhd(369) | Pruning bit <7> of wdata(7 downto 0) - not in use ... @W:CL170 : sconfig.vhd(257) | Pruning bit <7> of stat(7 downto 0) - not in use ... @W:CL170 : sconfig.vhd(257) | Pruning bit <6> of stat(7 downto 0) - not in use ... @W:CL170 : sconfig.vhd(257) | Pruning bit <5> of stat(7 downto 0) - not in use ... @N:CL201 : sconfig.vhd(549) | Trying to extract state machine for register state2 Extracted state machine for register state2 State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 @N:CL201 : sconfig.vhd(241) | Trying to extract state machine for register state Extracted state machine for register state State machine has 8 reachable states with original encodings of: 000 001 010 011 100 101 110 111 @N:CD630 : pll_60_40_10.vhd(7) | Synthesizing work.pll_60_40_10.def_arch @N:CD630 : fusion.vhd(4213) | Synthesizing fusion.pll.syn_black_box Post processing for fusion.pll.syn_black_box Post processing for work.pll_60_40_10.def_arch @N:CD630 : rc_osc.vhd(7) | Synthesizing work.rc_osc.def_arch @N:CD630 : fusion.vhd(4457) | Synthesizing fusion.rcosc.syn_black_box Post processing for fusion.rcosc.syn_black_box Post processing for work.rc_osc.def_arch Post processing for work.config_top.rtl @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Sep 25 15:46:54 2007 ###########################################################[ Synplicity Proasic Technology Mapper, Version 8.6.0, Build 155R, Built Apr 11 2006 Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved Version 8.5F @N:MF249 : | Running in 32-bit mode. @N: : | Gated clock conversion disabled @W:BN153 : | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking @W:BN153 : | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking @W:BN154 : | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed Automatic dissolve at startup in view:work.sconfig(rtl) of M1(ram256x8) Automatic dissolve at startup in view:work.NVM_2_blocks(rtl) of M2(NVM2) Automatic dissolve at startup in view:work.NVM_2_blocks(rtl) of M1(NVM1) Automatic dissolve at startup in view:work.config_top(rtl) of U2(NVM_2_blocks) Automatic dissolve at startup in view:work.config_top(rtl) of C2(PLL_60_40_10) Automatic dissolve at startup in view:work.config_top(rtl) of C1(rc_osc) RTL optimization done. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB) Encoding state machine work.sconfig(rtl)-state2[0:9] original code -> new code 0000 -> 0000000001 0001 -> 0000000010 0010 -> 0000000100 0011 -> 0000001000 0100 -> 0000010000 0101 -> 0000100000 0110 -> 0001000000 0111 -> 0010000000 1000 -> 0100000000 1001 -> 1000000000 Encoding state machine work.sconfig(rtl)-state[0:7] original code -> new code 000 -> 00000001 001 -> 00000010 010 -> 00000100 011 -> 00001000 100 -> 00010000 101 -> 00100000 110 -> 01000000 111 -> 10000000 @N:MF176 : | Default generator successful @N:MF238 : sconfig.vhd(296) | Found 19 bit incrementor, 'un1_inc[18:0]' @N:MF176 : | Default generator successful Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 30MB peak: 31MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 30MB peak: 31MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 30MB peak: 31MB) Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 31MB peak: 31MB) Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 31MB peak: 31MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:03s; Memory used current: 30MB peak: 31MB) Finished preparing to map (Time elapsed 0h:00m:05s; Memory used current: 31MB peak: 31MB) Promoting Net CLK_c on CLKBUF CLK_pad Promoting Net RST_c on CLKBUF RST_pad Replicating U1.N_1669, fanout 15 segments 2 Replicating nvm_addr[18], fanout 14 segments 2 Replicating U1.N_1538, fanout 20 segments 2 Replicating U1.addr_ld_0_sqmuxa, fanout 19 segments 2 Replicating U1.N_1371, fanout 20 segments 2 Buffering DI_c, fanout 27 segments 3 Buffering CSn_c, fanout 27 segments 3 Replicating U1.N_1471, fanout 24 segments 2 Replicating U1.state2[9], fanout 22 segments 2 Replicating U1.state2[1], fanout 24 segments 2 Replicating U1.state[4], fanout 13 segments 2 Replicating U1.state[7], fanout 15 segments 2 Replicating U1.bit_cnt[2], fanout 14 segments 2 Replicating U1.bit_cnt[1], fanout 16 segments 2 Replicating U1.bit_cnt[0], fanout 23 segments 2 Replicating U1.N_1783, fanout 13 segments 2 Buffering CSn_c, fanout 14 segments 2 Replicating U1.state2[8], fanout 14 segments 2 Finished technology mapping (Time elapsed 0h:00m:05s; Memory used current: 32MB peak: 33MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:05s; Memory used current: 32MB peak: 33MB) Added 5 Buffers Added 15 Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:05s; Memory used current: 32MB peak: 33MB) @W:BN153 : | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking @W:BN153 : | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking @W:BN154 : | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed @N:BN191 : | Writing property annotation file D:\Actelprj\SPI_SRAM_CONFIG\synthesis\config_top.tap. Writing Analyst data base D:\Actelprj\SPI_SRAM_CONFIG\synthesis\config_top.srm @N:BN225 : | Writing default property annotation file D:\Actelprj\SPI_SRAM_CONFIG\synthesis\config_top.map. Writing EDIF Netlist and constraint files Found clock config_top|CSn with period 1000.00ns Found clock config_top|CLK with period 1000.00ns @W: : pll_60_40_10.vhd(47) | Net clk60M appears to be a clock source which was not identified. Assuming default frequency. ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Sep 25 15:47:05 2007 # Top view: config_top Library name: fusion Operating conditions: COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree ) Requested Frequency: 1.0 MHz Wire load mode: top Wire load model: fusion Paths requested: 5 Constraint File(s): @N:MT195 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT197 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 478.547 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------- config_top|CLK 1.0 MHz 23.3 MHz 1000.000 42.907 478.547 inferred Inferred_clkgroup_0 System 1.0 MHz 30.6 MHz 1000.000 32.669 967.331 system default_clkgroup ======================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------- config_top|CLK config_top|CLK | 1000.000 973.963 | 1000.000 980.369 | 500.000 478.547 | No paths - config_top|CLK config_top|CSn | Diff grp - | No paths - | No paths - | No paths - ============================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: config_top|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------ U1.cmnd[4] config_top|CLK DFN1E1C1 Q cmnd[4] 0.364 478.547 U1.cmnd[3] config_top|CLK DFN1E1C1 Q cmnd[3] 0.364 478.673 U1.cmnd[6] config_top|CLK DFN1E1C1 Q cmnd[6] 0.364 478.974 U1.bit_cnt_0[0] config_top|CLK DFN1C1 Q bit_cnt_0[0] 0.292 480.043 U1.cmnd[5] config_top|CLK DFN1E1C1 Q cmnd[5] 0.364 481.022 U1.cmnd[0] config_top|CLK DFN1E1C1 Q cmnd[0] 0.292 481.150 U1.cmnd[1] config_top|CLK DFN1E1C1 Q cmnd[1] 0.292 481.151 U1.bit_cnt_0[1] config_top|CLK DFN1C1 Q bit_cnt_0[1] 0.292 481.161 U1.cmnd[2] config_top|CLK DFN1E1C1 Q cmnd[2] 0.364 481.218 U1.bit_cnt_0[2] config_top|CLK DFN1C1 Q bit_cnt_0[2] 0.292 481.476 ================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- U1.rdata[1] config_top|CLK DFN0C1 D rdata_4_i_0[1] 499.590 478.547 U1.rdata[4] config_top|CLK DFN0C1 D rdata_4_i_0[4] 499.590 478.547 U1.rdata[2] config_top|CLK DFN0C1 D rdata_4[2] 499.590 478.903 U1.rdata[3] config_top|CLK DFN0C1 D rdata_4[3] 499.590 478.903 U1.rdata[5] config_top|CLK DFN0C1 D rdata_4[5] 499.590 478.903 U1.rdata[6] config_top|CLK DFN0C1 D rdata_4[6] 499.590 478.903 U1.rdata[7] config_top|CLK DFN0C1 D rdata_4[7] 499.590 478.903 U1.rdata[0] config_top|CLK DFN0C1 D rdata_4[0] 499.590 481.939 U1.start[7] config_top|CLK DFN1C1 D start_3[7] 999.690 973.963 U1.start[6] config_top|CLK DFN1C1 D start_3[6] 999.690 975.100 ============================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 500.000 - Setup time: 0.410 = Required time: 499.590 - Propagation time: 21.043 = Slack (critical) : 478.547 Number of logic level(s): 5 Starting point: U1.cmnd[4] / Q Ending point: U1.rdata[1] / D The start point is clocked by config_top|CLK [rising] on pin CLK The end point is clocked by config_top|CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- U1.cmnd[4] DFN1E1C1 Q Out 0.364 0.364 - cmnd[4] Net - - 3.562 - 6 U1.state_ns_i_a2_i_0_o2_0[4] OR3 B In - 3.926 - U1.state_ns_i_a2_i_0_o2_0[4] OR3 Y Out 0.402 4.328 - N_1525 Net - - 4.004 - 7 U1.nxt3_0_a2_1_a2_1_a2_0 NOR3A B In - 8.331 - U1.nxt3_0_a2_1_a2_1_a2_0 NOR3A Y Out 0.276 8.607 - N_1773 Net - - 1.982 - 3 U1.nxt3_0_a2_1_a2_1_a2 NOR2B B In - 10.589 - U1.nxt3_0_a2_1_a2_1_a2 NOR2B Y Out 0.351 10.940 - nvm_read Net - - 4.446 - 8 U1.P5.rdata_4_2_0_a2_2[2] OR2A A In - 15.385 - U1.P5.rdata_4_2_0_a2_2[2] OR2A Y Out 0.305 15.690 - N_1784 Net - - 4.004 - 7 U1.P5.rdata_4_i_0[1] OA1B A In - 19.694 - U1.P5.rdata_4_i_0[1] OA1B Y Out 0.506 20.200 - rdata_4_i_0[1] Net - - 0.844 - 1 U1.rdata[1] DFN0C1 D In - 21.043 - =============================================================================================== Total path delay (propagation time + setup) of 21.453 is 2.614(12.2%) logic and 18.840(87.8%) route. ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------- U1.sbulk System DFN1C1 Q sbulk 0.364 967.331 U1.ssector System DFN1C1 Q ssector 0.364 967.405 U1.xaddr[0] System DFN1E1C1 Q xaddr[0] 0.364 970.615 U1.xaddr[1] System DFN1E1C1 Q xaddr[1] 0.364 972.580 U1.xaddr[2] System DFN1E1C1 Q xaddr[2] 0.364 972.960 U1.xaddr[3] System DFN1E1C1 Q xaddr[3] 0.364 974.978 U1.xaddr[4] System DFN1E1C1 Q xaddr[4] 0.364 975.359 U1.xaddr[5] System DFN1E1C1 Q xaddr[5] 0.364 977.377 U1.xaddr[6] System DFN1E1C1 Q xaddr[6] 0.364 977.758 U1.xaddr[7] System DFN1E1C1 Q xaddr[7] 0.364 979.504 =================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------- U1.xaddr[18] System DFN1E1C1 D xaddr_4[18] 999.590 967.331 U1.xaddr[17] System DFN1E1C1 D xaddr_4[17] 999.590 968.548 U1.xaddr[16] System DFN1E1C1 D xaddr_4[16] 999.590 970.176 U1.xaddr[15] System DFN1E1C1 D xaddr_4[15] 999.590 970.707 U1.xaddr[14] System DFN1E1C1 D xaddr_4[14] 999.710 970.861 U1.xaddr[13] System DFN1E1C1 D xaddr_4[13] 999.590 973.106 U1.xaddr[12] System DFN1E1C1 D xaddr_4[12] 999.710 973.260 U1.xaddr[11] System DFN1E1C1 D xaddr_4[11] 999.590 975.504 U1.xaddr[10] System DFN1E1C1 D xaddr_4[10] 999.710 975.658 U1.xaddr[9] System DFN1E1C1 D xaddr_4[9] 999.590 977.903 ======================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.410 = Required time: 999.590 - Propagation time: 32.260 = Slack (non-critical) : 967.331 Number of logic level(s): 14 Starting point: U1.sbulk / Q Ending point: U1.xaddr[18] / D The start point is clocked by System [rising] on pin CLK The end point is clocked by System [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- U1.sbulk DFN1C1 Q Out 0.364 0.364 - sbulk Net - - 1.982 - 3 U1.state2_tr11_i_0_o2 OR2 B In - 2.346 - U1.state2_tr11_i_0_o2 OR2 Y Out 0.362 2.708 - N_1552 Net - - 4.004 - 7 U1.un2_xaddr.ADD_19x19_slow_I0_un1_CO1 OR2A B In - 6.711 - U1.un2_xaddr.ADD_19x19_slow_I0_un1_CO1 OR2A Y Out 0.362 7.073 - I0_un1_CO1_0 Net - - 1.982 - 3 U1.un2_xaddr.ADD_19x19_slow_I2_un1_CO1 OR3B C In - 9.055 - U1.un2_xaddr.ADD_19x19_slow_I2_un1_CO1 OR3B Y Out 0.417 9.472 - I2_un1_CO1_0 Net - - 1.982 - 3 U1.un2_xaddr.ADD_19x19_slow_I4_un1_CO1 OR3B C In - 11.453 - U1.un2_xaddr.ADD_19x19_slow_I4_un1_CO1 OR3B Y Out 0.417 11.870 - I4_un1_CO1_0 Net - - 1.982 - 3 U1.un2_xaddr.ADD_19x19_slow_I6_un1_CO1 OR3B C In - 13.852 - U1.un2_xaddr.ADD_19x19_slow_I6_un1_CO1 OR3B Y Out 0.417 14.269 - I6_un1_CO1 Net - - 1.419 - 2 U1.un2_xaddr.ADD_19x19_slow_I7_CO1_1 AO1C B In - 15.688 - U1.un2_xaddr.ADD_19x19_slow_I7_CO1_1 AO1C Y Out 0.332 16.020 - N220_1 Net - - 1.982 - 3 U1.un2_xaddr.ADD_19x19_slow_I9_CO1 OR3B C In - 18.002 - U1.un2_xaddr.ADD_19x19_slow_I9_CO1 OR3B Y Out 0.417 18.419 - N226 Net - - 1.982 - 3 U1.un2_xaddr.ADD_19x19_slow_I11_CO1 OR3B C In - 20.400 - U1.un2_xaddr.ADD_19x19_slow_I11_CO1 OR3B Y Out 0.417 20.817 - N234 Net - - 1.982 - 3 U1.un2_xaddr.ADD_19x19_slow_I13_CO1 OR3B C In - 22.799 - U1.un2_xaddr.ADD_19x19_slow_I13_CO1 OR3B Y Out 0.417 23.216 - N242 Net - - 1.982 - 3 U1.un2_xaddr.ADD_19x19_slow_I15_CO1 OR3B C In - 25.198 - U1.un2_xaddr.ADD_19x19_slow_I15_CO1 OR3B Y Out 0.417 25.614 - N250 Net - - 1.419 - 2 U1.un2_xaddr.ADD_19x19_slow_I16_un1_CO1 NOR2A B In - 27.034 - U1.un2_xaddr.ADD_19x19_slow_I16_un1_CO1 NOR2A Y Out 0.232 27.266 - I16_un1_CO1 Net - - 1.419 - 2 U1.un2_xaddr.ADD_19x19_slow_I17_CO1 OR2B B In - 28.685 - U1.un2_xaddr.ADD_19x19_slow_I17_CO1 OR2B Y Out 0.351 29.036 - N258 Net - - 0.844 - 1 U1.P12.xaddr_4_i_a2[18] XA1B A In - 29.880 - U1.P12.xaddr_4_i_a2[18] XA1B Y Out 0.417 30.296 - N_1726 Net - - 0.844 - 1 U1.P12.xaddr_4_r[18] NOR3 A In - 31.140 - U1.P12.xaddr_4_r[18] NOR3 Y Out 0.276 31.416 - xaddr_4[18] Net - - 0.844 - 1 U1.xaddr[18] DFN1E1C1 D In - 32.260 - ========================================================================================================== Total path delay (propagation time + setup) of 32.669 is 6.023(18.4%) logic and 26.646(81.6%) route. ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Report for cell config_top.rtl Cell usage: cell count area count*area DFN1E1C1 60 1.0 60.0 DFN1C1 55 1.0 55.0 MX2 54 1.0 54.0 NOR2B 47 1.0 47.0 XOR2 46 1.0 46.0 NOR3A 29 1.0 29.0 AND3 22 1.0 22.0 OR3B 21 1.0 21.0 NOR3C 19 1.0 19.0 OR2A 19 1.0 19.0 NOR2A 19 1.0 19.0 MX2C 18 1.0 18.0 AO1B 16 1.0 16.0 AND2 16 1.0 16.0 OR2 15 1.0 15.0 NOR2 13 1.0 13.0 XNOR2 13 1.0 13.0 OR2B 12 1.0 12.0 OR3 12 1.0 12.0 AO1C 8 1.0 8.0 GND 8 0.0 0.0 DFN0C1 8 1.0 8.0 DFN1P1 8 1.0 8.0 VCC 8 0.0 0.0 AX1 7 1.0 7.0 OR3A 7 1.0 7.0 INV 7 1.0 7.0 NOR3 7 1.0 7.0 MAJ3 6 1.0 6.0 OR3C 6 1.0 6.0 DFN1E1P1 5 1.0 5.0 AOI1B 5 1.0 5.0 BUFF 5 1.0 5.0 AOI1 5 1.0 5.0 OA1B 5 1.0 5.0 NOR3B 5 1.0 5.0 AO1A 4 1.0 4.0 OA1A 4 1.0 4.0 AO1 3 1.0 3.0 AX1C 3 1.0 3.0 CLKBUF 2 0.0 0.0 NVM 2 0.0 0.0 XA1C 2 1.0 2.0 XA1B 2 1.0 2.0 AO1D 2 1.0 2.0 OAI1 2 1.0 2.0 XA1A 2 1.0 2.0 OA1 2 1.0 2.0 INBUF 2 0.0 0.0 MX2A 1 1.0 1.0 OA1C 1 1.0 1.0 AO13 1 1.0 1.0 TRIBUFF 1 0.0 0.0 XNOR3 1 1.0 1.0 MIN3 1 1.0 1.0 RAM4K9 1 0.0 0.0 PLL 1 0.0 0.0 RCOSC 1 0.0 0.0 ----- ---------- TOTAL 657 631.0 Mapper successful! Process took 0h:00m:08s realtime, 0h:00m:06s cputime # Tue Sep 25 15:47:05 2007 ###########################################################]