m255
13
cModel Technology
dC:\Actelprj\sconfig\simulation
Pall_blocks
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
w1152649714
FC:/Actelprj/vm1/hdl/user_pkg_1.vhd
l0
L20
V4]517>nSoemEoMjDzdWcQ2
OW;C;6.1b;31
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Ecfgnvm
w1171341743
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\ProgrammingSRAM\sconfig\simulation
FD:/ProgrammingSRAM/sconfig/smartgen/cfgnvm/cfgnvm.vhd
l0
L7
V]S002ILQgLlWX?eI5KNP22
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Adef_arch
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work cfgnvm ]S002ILQgLlWX?eI5KNP22
l54
L24
V_ODFcZ80S^jjO<9@XcX7B2
OW;C;6.1b;31
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Econfig_top
w1190759599
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/hdl/config_top.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/hdl/config_top.vhd
l0
L26
Vml?mDA8<U]?<CGD^WN5=l2
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Artl
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work config_top ml?mDA8<U]?<CGD^WN5=l2
l99
L35
Vba^[@fDKdkVNGF^Eo1C@@0
OW;C;6.2g;35
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
Edpram256x16
w1152228808
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/smartgen/dpram256x16/dpram256x16.vhd
l0
L7
Va13@7c0`XD<XD5Z4j6KVD2
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Adef_arch
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work dpram256x16 a13@7c0`XD<XD5Z4j6KVD2
l45
L18
V]gklAL:S=foz3Q]cMbU^52
OW;C;6.1b;31
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Eem_serial
w1157061932
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_textio _f?OZgMaGI`Rh:U4Gni>b2
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\ProgrammingSRAM\sconfig\simulation
FD:/ProgrammingSRAM/sconfig/stimulus/em_serial.vhd
l0
L50
VnFN[F9c1>eFY4a15[A7lB1
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Aem
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_textio _f?OZgMaGI`Rh:U4Gni>b2
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work em_serial nFN[F9c1>eFY4a15[A7lB1
l62
L60
V7ZS0F43zd[J;K;[ZHSUSJ1
OW;C;6.1b;31
31
M5 ieee std_logic_1164
M4 ieee std_logic_unsigned
M3 ieee std_logic_arith
M2 ieee std_logic_textio
M1 std textio
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Envm1
w1190758670
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/smartgen/NVM1/NVM1.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/smartgen/NVM1/NVM1.vhd
l0
L8
Vd:IIIJ7G]OX3>l8?HhEB43
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Adef_arch
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work nvm1 d:IIIJ7G]OX3>l8?HhEB43
l79
L36
VFLW=SK@A8^?BTY:]NBBUF2
OW;C;6.2g;35
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
Envm2
w1190758704
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/smartgen/NVM2/NVM2.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/smartgen/NVM2/NVM2.vhd
l0
L8
VCLIhL:`RIXJcEHLf6neSJ3
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Adef_arch
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work nvm2 CLIhL:`RIXJcEHLf6neSJ3
l79
L36
V8;I4eKT=XzJFW5YNWKko33
OW;C;6.2g;35
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
Envm_2_blocks
w1190757547
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/hdl/NVM_2_blocks.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/hdl/NVM_2_blocks.vhd
l0
L23
VDe1MB;h8Wg87Nz@=?zFjR3
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Artl
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work nvm_2_blocks De1MB;h8Wg87Nz@=?zFjR3
l82
L37
VZP[FF_9BMfI6`4:=Oz^FJ1
OW;C;6.2g;35
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
Epgm_nvm
w1154454766
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/smartgen/pgm_nvm/pgm_nvm.vhd
l0
L7
VaCaXMoA5F10Zn`VRoAla<0
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Adef_arch
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work pgm_nvm aCaXMoA5F10Zn`VRoAla<0
l54
L24
V<8em^_QMj77`aCXdBda6g0
OW;C;6.1b;31
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Epll3x
w1155190146
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/sconfig/smartgen/pll3x/pll3x.vhd
l0
L7
V27iBTnV85[2mSnj[h>_P82
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Adef_arch
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work pll3x 27iBTnV85[2mSnj[h>_P82
l43
L13
V87]ZUKHR9A6hE87Smhh`N0
OW;C;6.1b;31
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Epll_40_10
w1152116760
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/smartgen/pll_40_10/pll_40_10.vhd
l0
L7
V?Nl_GP[75AXcfaP?YbVm[2
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Adef_arch
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work pll_40_10 ?Nl_GP[75AXcfaP?YbVm[2
l43
L13
VDno1A6eQXHLLSc5M3^MJd1
OW;C;6.1b;31
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Epll_60_40_10
w1156480936
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/smartgen/PLL_60_40_10/PLL_60_40_10.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/smartgen/PLL_60_40_10/PLL_60_40_10.vhd
l0
L7
VaP>Snd[NG>I:Do6eKDPYj1
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Adef_arch
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work pll_60_40_10 aP>Snd[NG>I:Do6eKDPYj1
l43
L13
VO<[2ZMK>i;DZV<S7`55gM3
OW;C;6.2g;35
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
Eram256x16
w1152117646
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/hdl/ram256x16.vhd
l0
L7
V5gMY@UXOfQjG264Md=2GW0
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Adef_arch
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work ram256x16 5gMY@UXOfQjG264Md=2GW0
l40
L16
VecPH:N55kjdkNVb@5:fK61
OW;C;6.1b;31
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Eram256x8
w1155781470
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/smartgen/ram256x8/ram256x8.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/smartgen/ram256x8/ram256x8.vhd
l0
L7
Vh`ha[5objEM?oJ;LaH1YR1
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Adef_arch
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work ram256x8 h`ha[5objEM?oJ;LaH1YR1
l48
L17
VK_>n=nSIFiA3[B9n0MdL<3
OW;C;6.2g;35
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
Erc_osc
w1156480844
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/smartgen/rc_osc/rc_osc.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/smartgen/rc_osc/rc_osc.vhd
l0
L7
VgijG2TWQg>j6lU9E55NYg0
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Adef_arch
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work rc_osc gijG2TWQg>j6lU9E55NYg0
l18
L12
V7B1QKS8_iH6HTe8LefXd<0
OW;C;6.2g;35
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
Eschmitt
w1152115992
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/hdl/schmitt.vhd
l0
L21
Ve?X=7HoFY^@m@iU0>n4c`2
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Artl
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work schmitt e?X=7HoFY^@m@iU0>n4c`2
l35
L31
VkmdWR@C>6IXZ2mjjFjU8[0
OW;C;6.1b;31
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Esconfig
w1190757594
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/hdl/sconfig.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/hdl/sconfig.vhd
l0
L26
VCTjPZ:n^9NH1jX90>37`i0
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Artl
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work sconfig CTjPZ:n^9NH1jX90>37`i0
l155
L46
V3?T;1_BA50f5EPl0>ac9m1
OW;C;6.2g;35
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
Esm_slave
w1152115994
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/hdl/SM_SLAVE2.vhd
l0
L32
V=N=e>`Si91bo^bW?4:3fZ1
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Abehav
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work sm_slave =N=e>`Si91bo^bW?4:3fZ1
l94
L57
V6cm9V@cEPm;31<zDoom?V0
OW;C;6.1b;31
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Estack
w1152331508
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/hdl/stack.vhd
l0
L32
VIdJoU>PNgM_lKFNb>jil[0
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Artl
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work stack IdJoU>PNgM_lKFNb>jil[0
l59
L42
V:e3MZJZPSCik>GR8VE=<f3
OW;C;6.1b;31
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Estimulus
w1190759668
DP ieee numeric_bit K1ChclJ;R]bj:<QN8`za13
DP ieee math_real zjAF7SKfg_RPI0GT^n1N`1
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP syncad_vhdl_lib tbdefinitions PMU4]dAG[[aiNNb<^FQc11
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/stimulus/config_top_tbench_new.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/stimulus/config_top_tbench_new.vhd
l0
L25
VN9<ljl^E9Q^R]SS:QzLoK3
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Astimulator
DE syncad_vhdl_lib tb_clock_minmax aM]9B9_YHE>hN00bcbDcf1
DP ieee numeric_bit K1ChclJ;R]bj:<QN8`za13
DP ieee math_real zjAF7SKfg_RPI0GT^n1N`1
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP syncad_vhdl_lib tbdefinitions PMU4]dAG[[aiNNb<^FQc11
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work stimulus N9<ljl^E9Q^R]SS:QzLoK3
l54
L35
VV9>mBP4zlRGU=;V7CP60G0
OW;C;6.2g;35
31
M7 ieee std_logic_1164
M6 syncad_vhdl_lib tbdefinitions
M5 std textio
M4 ieee std_logic_textio
M3 ieee std_logic_arith
M2 ieee math_real
M1 ieee numeric_bit
o-93 -explicit -work presynth -O0
Etestbench
w1190759668
DP ieee numeric_bit K1ChclJ;R]bj:<QN8`za13
DP ieee math_real zjAF7SKfg_RPI0GT^n1N`1
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP syncad_vhdl_lib tbdefinitions PMU4]dAG[[aiNNb<^FQc11
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\Actelprj\SPI_SRAM_CONFIG\simulation
8D:/Actelprj/SPI_SRAM_CONFIG/stimulus/config_top_tbench_new.vhd
FD:/Actelprj/SPI_SRAM_CONFIG/stimulus/config_top_tbench_new.vhd
l0
L158
V:C=DG4BBMJbD_S1KTdoSl0
OW;C;6.2g;35
31
o-93 -explicit -work presynth -O0
Atbgeneratedcode
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DE work config_top ml?mDA8<U]?<CGD^WN5=l2
DE work stimulus N9<ljl^E9Q^R]SS:QzLoK3
DP ieee numeric_bit K1ChclJ;R]bj:<QN8`za13
DP ieee math_real zjAF7SKfg_RPI0GT^n1N`1
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP syncad_vhdl_lib tbdefinitions PMU4]dAG[[aiNNb<^FQc11
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work testbench :C=DG4BBMJbD_S1KTdoSl0
l169
L160
VWLX2M^dPbT[DX;CjVDj102
OW;C;6.2g;35
31
M8 ieee std_logic_1164
M7 syncad_vhdl_lib tbdefinitions
M6 std textio
M5 ieee std_logic_textio
M4 ieee std_logic_arith
M3 ieee math_real
M2 ieee numeric_bit
M1 ieee std_logic_unsigned
o-93 -explicit -work presynth -O0
Abehavior
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work testbench aI<d9UCd[n>SKYhnSdaMa1
l40
L16
VI1?c>Gi^4H<PaDV;UYUFS3
OW;C;6.1b;31
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
FD:/ProgrammingSRAM/sconfig/stimulus/testbench.vhd
w1156795878
dD:\ProgrammingSRAM\sconfig\simulation
Anetlist
DP ieee vital_timing ]B0ziJzR@[G?FAg2VLAF81
DP fusion analog_io D8DD[]^_H]gzAg[57EQFl0
DP ieee math_real C?BzjKU;H=GBT7o1IK8692
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work testbench ejKTzok_=P1R]mKCS0e=51
l66
L23
V67V4:>IM:ejZDSbWBANbF0
OW;C;6.1b;31
31
M6 ieee std_logic_1164
M5 ieee std_logic_unsigned
M4 ieee std_logic_arith
M3 ieee math_real
M2 fusion analog_io
M1 ieee vital_timing
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
FC:/Actelprj/vm1/stimulus/demo_tb.vhd
w1152123686
dD:\ProgrammingSRAM\sconfig\simulation
Evii
w1153084086
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/hdl/VM1.vhd
l0
L48
V[jfiS;^K6:jKK@g^97T:U1
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Artl
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work vii [jfiS;^K6:jKK@g^97T:U1
l200
L77
VGXfKMbM]`Xg5?4UR9<R^91
OW;C;6.1b;31
31
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Evm1
w1152979672
DP work all_blocks 4]517>nSoemEoMjDzdWcQ2
DP ieee vital_timing ]B0ziJzR@[G?FAg2VLAF81
DP fusion components 3Wg60CY^C78:=JYIfdK2>1
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/hdl/ttmv04.vhd
l0
L37
V9HVl06EI6STlQhg[Y1zKV3
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Artl
DP work all_blocks 4]517>nSoemEoMjDzdWcQ2
DP ieee vital_timing ]B0ziJzR@[G?FAg2VLAF81
DP fusion components 3Wg60CY^C78:=JYIfdK2>1
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work vm1 9HVl06EI6STlQhg[Y1zKV3
l96
L74
V`]_5AJnVY41iTNJ7NPn=H3
OW;C;6.1b;31
31
M6 ieee std_logic_1164
M5 ieee std_logic_unsigned
M4 ieee std_logic_arith
M3 fusion components
M2 ieee vital_timing
M1 work all_blocks
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Extl_osc
w1152116422
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
FC:/Actelprj/vm1/smartgen/xtl_osc/xtl_osc.vhd
l0
L7
Vjg4fS^f6]ClEmkn2Q8Td11
OW;C;6.1b;31
31
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
Adef_arch
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work xtl_osc jg4fS^f6]ClEmkn2Q8Td11
l39
L13
V?JPO1M6;cWkEbla3V52aP2
OW;C;6.1b;31
31
M1 ieee std_logic_1164
o-93 -explicit -work presynth -O0
tGenerateLoopIterationMax 100000
