`

    #Build: Synplify Pro 8.5F, Build 001R, Mar  7 2006
    #install: D:\Libero72\Synplify\Synplify_85F
    #OS: Windows XP 5.1
    #Hostname: WXP-WONGAL

    #Thu Feb 08 19:30:01 2007

    $ Running Identify Instrumentor. See log file:
    @N: : identify.log |
    #Thu Feb 08 19:30:01 2007

    $ Start of Compile
    #Thu Feb 08 19:30:07 2007

    Synplicity VHDL Compiler, version 3.4.1, Build 137R, built Apr  7 2006
    Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

    @N: : config_top.vhd(23) | Top entity is set to config_top.
    VHDL syntax check successful!
    File D:\ProgrammingSRAM\sconfig\synthesis\rev_1_identify\instr_sources\.filemap changed - recompiling
    @N:CD630 : config_top.vhd(17) | Synthesizing work.config_top.rtl
    @N:CD630 : syn_dics.vhd(1802) | Synthesizing work.iice_0.structure
    @N:CD630 : syn_dics.vhd(1284) | Synthesizing work.b7_ofwnt9s.b3_vfw
    @N:CD630 : syn_dics.vhd(968) | Synthesizing work.b12_ofwnt9_wmeed.b3_joc
    Post processing for work.b12_ofwnt9_wmeed.b3_joc
    @N:CD630 : syn_dics.vhd(1217) | Synthesizing work.ram_block.struct
    @N:CD630 : syn_dics.vhd(1178) | Synthesizing work.ramsliceram_block.struct
    @N:CD630 : syn_dics.vhd(1026) | Synthesizing work.genericramram_block.struct
    @N:CD630 : fusion.vhd(3267) | Synthesizing work.ram512x18.syn_black_box
    Post processing for work.ram512x18.syn_black_box
    Post processing for work.genericramram_block.struct
    Post processing for work.ramsliceram_block.struct
    Post processing for work.ram_block.struct
    Post processing for work.b7_ofwnt9s.b3_vfw
    @N:CD630 : syn_dics.vhd(1539) | Synthesizing work.b3_ukr.b3_vcj
    @N:CD630 : syn_dics.vhd(1443) | Synthesizing work.b7_plf_6ln.b3_vcj
    Post processing for work.b7_plf_6ln.b3_vcj
    @N:CD630 : syn_dics.vhd(1488) | Synthesizing work.b12_nvmfl_la1xyh.b3_vcj
    Post processing for work.b12_nvmfl_la1xyh.b3_vcj
    Post processing for work.b3_ukr.b3_vcj
    @N:CD630 : syn_dics.vhd(1639) | Synthesizing work.b3_12m.b6_oczobx
    @W:CD638 : syn_dics.vhd(1703) | Signal b11_nutz3qm_tkl is undriven
    @N:CD630 : syn_dics.vhd(565) | Synthesizing work.b7_pffzrny.b6_oczobx
    @N:CD630 : syn_dics.vhd(492) | Synthesizing work.b5_nvmfl.b6_oczobx
    Post processing for work.b5_nvmfl.b6_oczobx
    @N:CD630 : syn_dics.vhd(526) | Synthesizing work.b11_psyil9s1fkt.b3_joc
    @N:CD630 : syn_dics.vhd(412) | Synthesizing work.b8_1lbcqdr1.b3_joc
    Post processing for work.b8_1lbcqdr1.b3_joc
    Post processing for work.b11_psyil9s1fkt.b3_joc
    Post processing for work.b7_pffzrny.b6_oczobx
    @W:CL209 : syn_dics.vhd(567) | Input port bit <1> of b9_slyy_nrgd(0 to 44) is unused
    @N:CD630 : syn_dics.vhd(751) | Synthesizing work.b7_ocbylxc.b3_joc
    @W:CD274 : syn_dics.vhd(867) | Incomplete case statement - add more cases or a when others
    @N:CD630 : syn_dics.vhd(662) | Synthesizing work.b8_nr_ymqrg.b3_joc
    Post processing for work.b8_nr_ymqrg.b3_joc
    Post processing for work.b7_ocbylxc.b3_joc
    @N:CL201 : syn_dics.vhd(849) | Trying to extract state machine for register b13_nAzGfFM_sLsv3
    Extracted state machine for register b13_nAzGfFM_sLsv3
    State machine has 6 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       1101
    Post processing for work.b3_12m.b6_oczobx
    Post processing for work.iice_0.structure
    @N:CD630 : syn_dics.vhd(1746) | Synthesizing work.ldic1_0.structure
    Post processing for work.ldic1_0.structure
    @N:CD630 : syn_dics.vhd(243) | Synthesizing work.comm_block.b3_joc
    @N:CD630 : syn_dics.vhd(5) | Synthesizing work.b9_orbiwxaef.b3_vcj
    Post processing for work.b9_orbiwxaef.b3_vcj
    @N:CD630 : syn_dics.vhd(192) | Synthesizing work.b16_rcmi_qlx9_yhpm7y.b3_vcj
    Post processing for work.b16_rcmi_qlx9_yhpm7y.b3_vcj
    @N:CD630 : syn_dics.vhd(70) | Synthesizing work.jtag_interface.b3_vcj
    @W:CD434 : syn_dics.vhd(159) | Signal identify_clk2_no_clk_buffer_needed in the sensitivity list is not used in the process
    @W:CD434 : syn_dics.vhd(170) | Signal identify_clk2_no_clk_buffer_needed in the sensitivity list is not used in the process
    @W:CD638 : syn_dics.vhd(94) | Signal b14_gir9p_al2ezh2v is undriven
    @N:CD630 : fusion.vhd(4363) | Synthesizing work.ujtag.syn_black_box
    Post processing for work.ujtag.syn_black_box
    Post processing for work.jtag_interface.b3_vcj
    Post processing for work.comm_block.b3_joc
    @N:CD630 : cfgnvm.vhd(7) | Synthesizing work.cfgnvm.def_arch
    @N:CD630 : fusion.vhd(4474) | Synthesizing work.nvm.syn_black_box
    Post processing for work.nvm.syn_black_box
    @N:CD630 : fusion.vhd(3021) | Synthesizing work.vcc.syn_black_box
    Post processing for work.vcc.syn_black_box
    @N:CD630 : fusion.vhd(1901) | Synthesizing work.gnd.syn_black_box
    Post processing for work.gnd.syn_black_box
    Post processing for work.cfgnvm.def_arch
    @W:CL168 : cfgnvm.vhd(119) | Pruning instance VCC_power_inst1 - not in use ...
    @N:CD630 : sconfig.vhd(18) | Synthesizing work.sconfig.rtl
    @N:CD630 : syn_dics.vhd(1771) | Synthesizing work.ldic4_0.structure
    Post processing for work.ldic4_0.structure
    @N:CD630 : ram256x8.vhd(7) | Synthesizing work.ram256x8.def_arch
    @N:CD630 : fusion.vhd(3184) | Synthesizing work.ram4k9.syn_black_box
    Post processing for work.ram4k9.syn_black_box
    @N:CD630 : fusion.vhd(2119) | Synthesizing work.inv.syn_black_box
    Post processing for work.inv.syn_black_box
    Post processing for work.ram256x8.def_arch
    Post processing for work.sconfig.rtl
    @W:CL170 : sconfig.vhd(361) | Pruning bit <7> of wdata(7 downto 0) - not in use ...
    @W:CL170 : sconfig.vhd(249) | Pruning bit <7> of stat(7 downto 0) - not in use ...
    @W:CL170 : sconfig.vhd(249) | Pruning bit <6> of stat(7 downto 0) - not in use ...
    @W:CL170 : sconfig.vhd(249) | Pruning bit <5> of stat(7 downto 0) - not in use ...
    @N:CL201 : sconfig.vhd(541) | Trying to extract state machine for register state2
    Extracted state machine for register state2
    State machine has 10 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1000
       1001
    @N:CL201 : sconfig.vhd(233) | Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 8 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
       111
    @N:CD630 : pll_60_40_10.vhd(7) | Synthesizing work.pll_60_40_10.def_arch
    @N:CD630 : fusion.vhd(4213) | Synthesizing work.pll.syn_black_box
    Post processing for work.pll.syn_black_box
    Post processing for work.pll_60_40_10.def_arch
    @N:CD630 : rc_osc.vhd(7) | Synthesizing work.rc_osc.def_arch
    @N:CD630 : fusion.vhd(4457) | Synthesizing work.rcosc.syn_black_box
    Post processing for work.rcosc.syn_black_box
    Post processing for work.rc_osc.def_arch
    Post processing for work.config_top.rtl
    @END
    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Thu Feb 08 19:30:09 2007

    ###########################################################[
    Synplicity Proasic Technology Mapper, Version 8.6.0, Build 155R, Built Apr 11 2006
    Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
    Version 8.5F
    @N:MF249 :  | Running in 32-bit mode.
    @N: :  | Gated clock conversion disabled
    @W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
    @W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
    @W:BN154 :  | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed

    Automatic dissolve at startup in view:work.sconfig(rtl) of ldic4_inst_0(ldic4_0)
    Automatic dissolve at startup in view:work.sconfig(rtl) of M1(ram256x8)
    Automatic dissolve at startup in view:work.comm_block(b3_joc) of b9_ORb_xNywD(b9_ORbIwXaEF)
    Automatic dissolve at startup in view:work.comm_block(b3_joc) of b7_Rcmi_ql(b16_Rcmi_qlx9_yHpm7y)
    Automatic dissolve at startup in view:work.b7_OCByLXC(b3_joc) of b11_nUTGT_khWqH(b8_nR_ymqrG)
    Automatic dissolve at startup in view:work.b7_PfFzrNY(b6_oczobx) of b5_PbrtL(b5_nvmFL)
    Automatic dissolve at startup in view:work.ramSliceram_block(struct) of GenericRAMInst0(GenericRAMram_block)
    Automatic dissolve at startup in view:work.ram_block(struct) of ramSliceInst2(ramSliceram_block)
    Automatic dissolve at startup in view:work.ram_block(struct) of ramSliceInst1(ramSliceram_block)
    Automatic dissolve at startup in view:work.ram_block(struct) of ramSliceInst0(ramSliceram_block)
    Automatic dissolve at startup in view:work.b7_OFWNT9s(b3_vfw) of b3_SoW(ram_block)
    Automatic dissolve at startup in view:work.config_top(rtl) of ldic1_inst_0(ldic1_0)
    Automatic dissolve at startup in view:work.config_top(rtl) of M2(cfgnvm)
    Automatic dissolve at startup in view:work.config_top(rtl) of M1(cfgnvm)
    Automatic dissolve at startup in view:work.config_top(rtl) of C2(PLL_60_40_10)
    Automatic dissolve at startup in view:work.config_top(rtl) of C1(rc_osc)
    RTL optimization done.

    Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 28MB peak: 28MB)
    Encoding state machine work.sconfig(rtl)-state[0:7]
    original code -> new code
       000 -> 00000001
       001 -> 00000010
       010 -> 00000100
       011 -> 00001000
       100 -> 00010000
       101 -> 00100000
       110 -> 01000000
       111 -> 10000000
    Encoding state machine work.sconfig(rtl)-state2[0:9]
    original code -> new code
       0000 -> 0000000001
       0001 -> 0000000010
       0010 -> 0000000100
       0011 -> 0000001000
       0100 -> 0000010000
       0101 -> 0000100000
       0110 -> 0001000000
       0111 -> 0010000000
       1000 -> 0100000000
       1001 -> 1000000000
    @N:MF176 :  | Default generator successful
    @N:MF238 : sconfig.vhd(288) | Found 19 bit incrementor, 'un1_inc[18:0]'
    @N:MF176 :  | Default generator successful
    Encoding state machine work.b7_OCByLXC(b3_joc)-b13_nAzGfFM_sLsv3[0:5]
    original code -> new code
       0000 -> 000001
       0001 -> 000010
       0010 -> 000100
       0011 -> 001000
       0100 -> 010000
       1101 -> 100000
    @W:MO129 :  | Sequential instance iice_inst_0.b7_12mFLWM.b5_nUTGT.b3_nfs[1] has been reduced to a combinational gate by constant propagation

    Finished factoring (Time elapsed 0h:00m:04s; Memory used current: 30MB peak: 32MB)

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:04s; Memory used current: 30MB peak: 32MB)

    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:05s; Memory used current: 30MB peak: 32MB)

    Starting Early Timing Optimization (Time elapsed 0h:00m:05s; Memory used current: 31MB peak: 32MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:05s; Memory used current: 31MB peak: 32MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:05s; Memory used current: 30MB peak: 32MB)

    Finished preparing to map (Time elapsed 0h:00m:06s; Memory used current: 31MB peak: 32MB)
    Promoting Net b3_PK3 on CLKINT  jtag_block.jtagi.b3_PK3_inferred_clock
    Promoting Net CLK_c on CLKBUF  CLK_pad
    Promoting Net RST_c on CLKBUF  RST_pad
    Promoting Net comm2iice_link_iice_0_a_0[7] on CLKINT  I_64
    Replicating nvm_addr_i_0[18], fanout 14 segments 2
    Replicating U1.G1.0.P4.un12_state, fanout 18 segments 2
    Replicating U1.addr_ld_1_sqmuxa, fanout 17 segments 2
    Replicating U1.addr_ld_0_sqmuxa, fanout 19 segments 2
    Replicating U1.N_439, fanout 20 segments 2
    Buffering DI_c, fanout 26 segments 3
    Buffering CSn_c, fanout 26 segments 3
    Replicating U1.state[7], fanout 13 segments 2
    Replicating U1.state[4], fanout 14 segments 2
    Replicating U1.P6.un21_rstn, fanout 24 segments 2
    Replicating U1.state2[1], fanout 22 segments 2
    Replicating U1.state2[9], fanout 23 segments 2
    Replicating uplink_8_a[7], fanout 13 segments 2
    Replicating uplink_8_a[8], fanout 20 segments 2
    Replicating U1.P2.un6_bit_cnt, fanout 13 segments 2
    Replicating U1.state2[8], fanout 15 segments 2

    Finished technology mapping (Time elapsed 0h:00m:07s; Memory used current: 31MB peak: 32MB)

    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:07s; Memory used current: 31MB peak: 32MB)

    Added 4 Buffers
    Added 14 Cells via replication

    Added 4 Buffers
    Added 14 Cells via replication

    Added 4 Buffers
    Added 14 Cells via replication

    Added 4 Buffers
    Added 14 Cells via replication

    Finished restoring hierarchy (Time elapsed 0h:00m:07s; Memory used current: 31MB peak: 32MB)
    @W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
    @W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
    @W:BN154 :  | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed
    @N:BN191 :  | Writing property annotation file D:\ProgrammingSRAM\sconfig\synthesis\rev_1_identify\config_top.tap.
    Writing Analyst data base D:\ProgrammingSRAM\sconfig\synthesis\rev_1_identify\config_top.srm
    @N:BN225 :  | Writing default property annotation file D:\ProgrammingSRAM\sconfig\synthesis\rev_1_identify\config_top.map.
    Writing EDIF Netlist and constraint files
    Found clock config_top|CSn with period 1000.00ns
    Found clock config_top|CLK with period 1000.00ns
    Found clock jtag_interface|b3_PK3_inferred_clock with period 1000.00ns
    Found clock jtag_interface|b7_oSD_3vW_inferred_clock with period 1000.00ns
    Found clock jtag_interface|identify_clk2_no_clk_buffer_needed with period 1000.00ns
    @W: : pll_60_40_10.vhd(47) | Net mdic_link[5] appears to be a clock source which was not identified. Assuming default frequency.

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Thu Feb 08 19:30:20 2007
    #

    Top view:               config_top
    Library name:           fusion
    Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
    Requested Frequency:    1.0 MHz
    Wire load mode:         top
    Wire load model:        fusion
    Paths requested:        5
    Constraint File(s):
    @N:MT195 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

    @N:MT197 :  | Clock constraints cover only FF-to-FF paths associated with the clock..

    Performance Summary
    *******************

    Worst slack in design: 482.850

                                                          Requested     Estimated     Requested     Estimated                 Clock        Clock
    Starting Clock                                        Frequency     Frequency     Period        Period        Slack       Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------------------------------
    config_top|CLK                                        1.0 MHz       29.2 MHz      1000.000      34.299        482.850     inferred     Inferred_clkgroup_0
    jtag_interface|b3_PK3_inferred_clock                  1.0 MHz       23.9 MHz      1000.000      41.860        958.140     inferred     Inferred_clkgroup_5
    jtag_interface|b7_oSD_3vW_inferred_clock              1.0 MHz       73.1 MHz      1000.000      13.678        986.322     inferred     Inferred_clkgroup_3
    jtag_interface|identify_clk2_no_clk_buffer_needed     1.0 MHz       47.6 MHz      1000.000      21.029        978.971     inferred     Inferred_clkgroup_4
    System                                                1.0 MHz       37.5 MHz      1000.000      26.674        973.326     system       default_clkgroup
    ==========================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                                |    rise  to  rise     |    fall  to  fall     |    rise  to  fall     |    fall  to  rise
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                           Ending                                             |  constraint  slack    |  constraint  slack    |  constraint  slack    |  constraint  slack
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    config_top|CLK                                     config_top|CLK                                     |  1000.000    976.998  |  1000.000    981.246  |  500.000     482.850  |  No paths    -
    config_top|CLK                                     config_top|CSn                                     |  Diff grp    -        |  No paths    -        |  No paths    -        |  No paths    -
    jtag_interface|b7_oSD_3vW_inferred_clock           jtag_interface|b7_oSD_3vW_inferred_clock           |  1000.000    986.322  |  No paths    -        |  No paths    -        |  No paths    -
    jtag_interface|b7_oSD_3vW_inferred_clock           jtag_interface|identify_clk2_no_clk_buffer_needed  |  Diff grp    -        |  No paths    -        |  No paths    -        |  No paths    -
    jtag_interface|identify_clk2_no_clk_buffer_needed  jtag_interface|identify_clk2_no_clk_buffer_needed  |  1000.000    978.971  |  No paths    -        |  No paths    -        |  No paths    -
    jtag_interface|identify_clk2_no_clk_buffer_needed  jtag_interface|b3_PK3_inferred_clock               |  Diff grp    -        |  No paths    -        |  No paths    -        |  No paths    -
    jtag_interface|b3_PK3_inferred_clock               jtag_interface|identify_clk2_no_clk_buffer_needed  |  Diff grp    -        |  No paths    -        |  No paths    -        |  No paths    -
    jtag_interface|b3_PK3_inferred_clock               jtag_interface|b3_PK3_inferred_clock               |  1000.000    958.140  |  No paths    -        |  No paths    -        |  No paths    -
    ==================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    		No IO constraint found

    ====================================
    Detailed Report for Clock: config_top|CLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                        Starting                                                    Arrival
    Instance            Reference          Type         Pin     Net                 Time        Slack
                        Clock
    ---------------------------------------------------------------------------------------------------
    U1.cmnd[5]          config_top|CLK     DFN1E1C1     Q       uplink_8_a[11]      0.364       482.850
    U1.cmnd[3]          config_top|CLK     DFN1E1C1     Q       uplink_8_a[13]      0.364       483.255
    U1.cmnd[4]          config_top|CLK     DFN1E1C1     Q       uplink_8_a[12]      0.364       483.923
    U1.cmnd[6]          config_top|CLK     DFN1E1C1     Q       uplink_8_a[10]      0.364       484.178
    U1.cmnd[2]          config_top|CLK     DFN1E1C1     Q       uplink_8_a[14]      0.364       484.809
    U1.cmnd[1]          config_top|CLK     DFN1E1C1     Q       uplink_8_a[15]      0.364       485.133
    U1.bit_cnt[2]       config_top|CLK     DFN1C1       Q       uplink_8_a[6]       0.364       485.465
    U1.bit_cnt_0[0]     config_top|CLK     DFN1C1       Q       uplink_8_a_0[8]     0.364       485.641
    U1.cmnd[0]          config_top|CLK     DFN1E1C1     Q       uplink_8_a[16]      0.364       485.912
    U1.bit_cnt_0[1]     config_top|CLK     DFN1C1       Q       uplink_8_a_0[7]     0.364       486.981
    ===================================================================================================

    Ending Points with Worst Slack
    ******************************

                    Starting                                             Required
    Instance        Reference          Type       Pin     Net            Time         Slack
                    Clock
    -----------------------------------------------------------------------------------------
    U1.rdata[0]     config_top|CLK     DFN0C1     D       rdata_4[0]     499.590      482.850
    U1.rdata[1]     config_top|CLK     DFN0C1     D       rdata_4[1]     499.590      482.850
    U1.rdata[2]     config_top|CLK     DFN0C1     D       rdata_4[2]     499.590      482.850
    U1.rdata[3]     config_top|CLK     DFN0C1     D       rdata_4[3]     499.590      482.850
    U1.rdata[4]     config_top|CLK     DFN0C1     D       rdata_4[4]     499.590      482.850
    U1.rdata[5]     config_top|CLK     DFN0C1     D       rdata_4[5]     499.590      482.859
    U1.rdata[6]     config_top|CLK     DFN0C1     D       rdata_4[6]     499.590      482.859
    U1.rdata[7]     config_top|CLK     DFN0C1     D       rdata_4[7]     499.590      482.859
    U1.start[7]     config_top|CLK     DFN1C1     D       start_3[7]     999.690      976.998
    U1.start[6]     config_top|CLK     DFN1C1     D       start_3[6]     999.690      977.921
    =========================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
        Requested Period:                        500.000
        - Setup time:                            0.410
        = Required time:                         499.590

        - Propagation time:                      16.740
        = Slack (critical) :                     482.850

        Number of logic level(s):                5
        Starting point:                          U1.cmnd[5] / Q
        Ending point:                            U1.rdata[0] / D
        The start point is clocked by            config_top|CLK [rising] on pin CLK
        The end   point is clocked by            config_top|CLK [falling] on pin CLK

    Instance / Net                       Pin      Pin               Arrival     No. of
    Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    U1.cmnd[5]              DFN1E1C1     Q        Out     0.364     0.364       -
    uplink_8_a[11]          Net          -        -       2.990     -           7
    U1.un2_idis_1_0_a2      NOR2         B        In      -         3.354       -
    U1.un2_idis_1_0_a2      NOR2         Y        Out     0.362     3.716       -
    un2_idis_1              Net          -        -       2.330     -           5
    U1.un10_nxt0_2_0_a2     OR2B         B        In      -         6.046       -
    U1.un10_nxt0_2_0_a2     OR2B         Y        Out     0.351     6.397       -
    nxt3_1                  Net          -        -       2.990     -           7
    U1.nxt3                 NOR2A        B        In      -         9.387       -
    U1.nxt3                 NOR2A        Y        Out     0.232     9.619       -
    nvm_read                Net          -        -       2.660     -           6
    U1.P5.rdata_4_sn_m2     NOR2         A        In      -         12.279      -
    U1.P5.rdata_4_sn_m2     NOR2         Y        Out     0.287     12.566      -
    N_655                   Net          -        -       3.320     -           8
    U1.P5.rdata_4[0]        MX2C         S        In      -         15.886      -
    U1.P5.rdata_4[0]        MX2C         Y        Out     0.224     16.110      -
    rdata_4[0]              Net          -        -       0.630     -           1
    U1.rdata[0]             DFN0C1       D        In      -         16.740      -
    ======================================================================================
    Total path delay (propagation time + setup) of 17.150 is 2.230(13.0%) logic and 14.920(87.0%) route.

    ====================================
    Detailed Report for Clock: jtag_interface|b3_PK3_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                          Starting                                                                          Arrival
    Instance                                                              Reference                                Type       Pin     Net                   Time        Slack
                                                                          Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[5]                                    jtag_interface|b3_PK3_inferred_clock     DFN1       Q       b9_v_mzCDYXs[5]       0.364       980.860
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[6]                                    jtag_interface|b3_PK3_inferred_clock     DFN1       Q       b9_v_mzCDYXs[6]       0.364       981.578
    iice_inst_0.b3_SoW.b7_nYJ_BFM[44]                                     jtag_interface|b3_PK3_inferred_clock     DFN1       Q       b7_nYJ_BFM[44]        0.364       981.744
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[0]                                    jtag_interface|b3_PK3_inferred_clock     DFN1       Q       b9_v_mzCDYXs[0]       0.364       981.848
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[4]                                    jtag_interface|b3_PK3_inferred_clock     DFN1       Q       b9_v_mzCDYXs[4]       0.364       981.853
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[2]                                    jtag_interface|b3_PK3_inferred_clock     DFN1       Q       b9_v_mzCDYXs[2]       0.364       981.860
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[3]                                    jtag_interface|b3_PK3_inferred_clock     DFN1       Q       b9_v_mzCDYXs[3]       0.364       981.914
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[1]                                    jtag_interface|b3_PK3_inferred_clock     DFN1       Q       b9_v_mzCDYXs[1]       0.364       981.921
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b10_nfs_M9kYfr[0]     jtag_interface|b3_PK3_inferred_clock     DFN1E0     Q       b13_nUTQBgfDb_Z4D     0.364       989.172
    iice_inst_0.b7_12mFLWM.b4_PfFz.b5_PbrtL.b6_OKctIF[0]                  jtag_interface|b3_PK3_inferred_clock     DFN1E1     Q       b7_PSyi3wy            0.364       989.324
    ===========================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                             Starting                                                                           Required
    Instance                                                 Reference                                Type       Pin      Net                   Time         Slack
                                                             Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[5]                       jtag_interface|b3_PK3_inferred_clock     DFN1       D        b9_v_mzCDYXs_5[5]     999.690      980.860
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[6]                       jtag_interface|b3_PK3_inferred_clock     DFN1       D        b9_v_mzCDYXs_5[6]     999.690      980.860
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[4]                       jtag_interface|b3_PK3_inferred_clock     DFN1       D        b9_v_mzCDYXs_5[4]     999.690      981.817
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[3]                       jtag_interface|b3_PK3_inferred_clock     DFN1       D        b9_v_mzCDYXs_5[3]     999.690      982.667
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[2]                       jtag_interface|b3_PK3_inferred_clock     DFN1       D        b9_v_mzCDYXs_5[2]     999.690      983.623
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[1]                       jtag_interface|b3_PK3_inferred_clock     DFN1       D        b9_v_mzCDYXs_5[1]     999.690      985.430
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[0]                       jtag_interface|b3_PK3_inferred_clock     DFN1       D        b9_v_mzCDYXs_5[0]     999.590      986.861
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw            jtag_interface|b3_PK3_inferred_clock     UJTAG      UTDO     b6_PLF_Bq             997.000      989.172
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b6_yor0PD[7]          jtag_interface|b3_PK3_inferred_clock     DFN1E0     D        b6_yor0PD_5[7]        999.590      990.392
    iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b7_PSyil9s     jtag_interface|b3_PK3_inferred_clock     DFN1       D        b6_2ZTGIf[0]          999.590      994.416
    ================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
        Requested Period:                        1000.000
        - Setup time:                            0.310
        = Required time:                         999.690

        - Propagation time:                      18.830
        = Slack (non-critical) :                 980.860

        Number of logic level(s):                10
        Starting point:                          iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] / Q
        Ending point:                            iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] / D
        The start point is clocked by            jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK
        The end   point is clocked by            jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK

    Instance / Net                                                      Pin      Pin               Arrival     No. of
    Name                                                      Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[5]                        DFN1      Q        Out     0.364     0.364       -
    b9_v_mzCDYXs[5]                                           Net       -        -       2.990     -           7
    iice_inst_0.b3_SoW.b8_vFsG_vuY.un10_b11_vfsg_9urxbb_0     NOR2B     B        In      -         3.354       -
    iice_inst_0.b3_SoW.b8_vFsG_vuY.un10_b11_vfsg_9urxbb_0     NOR2B     Y        Out     0.351     3.705       -
    un10_b11_vfsg_9urxbb_0                                    Net       -        -       0.630     -           1
    iice_inst_0.b3_SoW.b8_vFsG_vuY.un10_b11_vfsg_9urxbb_4     NOR3C     C        In      -         4.335       -
    iice_inst_0.b3_SoW.b8_vFsG_vuY.un10_b11_vfsg_9urxbb_4     NOR3C     Y        Out     0.370     4.705       -
    un10_b11_vfsg_9urxbb_4                                    Net       -        -       0.630     -           1
    iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa                  AOI1      B        In      -         5.335       -
    iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa                  AOI1      Y        Out     0.517     5.852       -
    b9_v_mzCDYXs_1_sqmuxa                                     Net       -        -       3.990     -           10
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_3                   AND2      A        In      -         9.842       -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_3                   AND2      Y        Out     0.293     10.135      -
    DWACT_ADD_CI_0_TMP[2]                                     Net       -        -       0.630     -           1
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_4                   OR3       C        In      -         10.765      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_4                   OR3       Y        Out     0.416     11.181      -
    DWACT_ADD_CI_0_g_array_0[0]                               Net       -        -       1.060     -           2
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_31                  AO1       B        In      -         12.241      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_31                  AO1       Y        Out     0.327     12.568      -
    DWACT_ADD_CI_0_g_array_1[0]                               Net       -        -       1.480     -           3
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_38                  AO1       B        In      -         14.048      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_38                  AO1       Y        Out     0.327     14.375      -
    DWACT_ADD_CI_0_g_array_2[0]                               Net       -        -       1.480     -           3
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_34                  AO1       B        In      -         15.855      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_34                  AO1       Y        Out     0.327     16.182      -
    DWACT_ADD_CI_0_g_array_12_1[0]                            Net       -        -       0.630     -           1
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_29                  XOR2      B        In      -         16.812      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_29                  XOR2      Y        Out     0.520     17.331      -
    I_29_0                                                    Net       -        -       0.630     -           1
    iice_inst_0.b3_SoW.b8_vFsG_vuY.b9_v_mzCDYXs_5[5]          OA1       C        In      -         17.962      -
    iice_inst_0.b3_SoW.b8_vFsG_vuY.b9_v_mzCDYXs_5[5]          OA1       Y        Out     0.239     18.200      -
    b9_v_mzCDYXs_5[5]                                         Net       -        -       0.630     -           1
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[5]                        DFN1      D        In      -         18.830      -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 19.140 is 4.360(22.8%) logic and 14.780(77.2%) route.

    ====================================
    Detailed Report for Clock: jtag_interface|b7_oSD_3vW_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                   Starting                                                                            Arrival
    Instance                                       Reference                                    Type       Pin     Net                 Time        Slack
                                                   Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[0]     0.364       994.618
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[1]     0.364       998.166
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[2]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[2]     0.364       998.166
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[3]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[3]     0.364       998.166
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[4]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[4]     0.364       998.166
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[5]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[5]     0.364       998.166
    ======================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                      Starting                                                                             Required
    Instance                                          Reference                                    Type       Pin      Net                 Time         Slack
                                                      Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     jtag_interface|b7_oSD_3vW_inferred_clock     UJTAG      UTDO     b6_PLF_Bq           997.000      994.618
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0]        jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D        b9_OvyH3_saL[1]     999.590      998.166
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1]        jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D        b9_OvyH3_saL[2]     999.590      998.166
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[2]        jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D        b9_OvyH3_saL[3]     999.590      998.166
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[3]        jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D        b9_OvyH3_saL[4]     999.590      998.166
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[4]        jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D        b9_OvyH3_saL[5]     999.590      998.166
    ===========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
        Requested Period:                        1000.000
        - Setup time:                            3.000
        = Required time:                         997.000

        - Propagation time:                      2.382
        = Slack (non-critical) :                 994.618

        Number of logic level(s):                1
        Starting point:                          comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] / Q
        Ending point:                            comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw / UTDO
        The start point is clocked by            jtag_interface|b7_oSD_3vW_inferred_clock [rising] on pin CLK
        The end   point is clocked by            jtag_interface|b7_oSD_3vW_inferred_clock [rising]

    Instance / Net                                               Pin      Pin               Arrival     No. of
    Name                                              Type       Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0]        DFN1E1     Q        Out     0.364     0.364       -
    b9_OvyH3_saL[0]                                   Net        -        -       1.060     -           2
    comm_block_inst.b7_Rcmi_ql.b3_PLF                 MX2        A        In      -         1.424       -
    comm_block_inst.b7_Rcmi_ql.b3_PLF                 MX2        Y        Out     0.328     1.752       -
    b6_PLF_Bq                                         Net        -        -       0.630     -           1
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     UJTAG      UTDO     In      -         2.382       -
    ==============================================================================================================
    Total path delay (propagation time + setup) of 5.382 is 3.692(68.6%) logic and 1.690(31.4%) route.

    ====================================
    Detailed Report for Clock: jtag_interface|identify_clk2_no_clk_buffer_needed
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                    Starting                                                                                            Arrival
    Instance                                                        Reference                                             Type         Pin     Net                      Time        Slack
                                                                    Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1C1     Q       b8_vABZ3qsY              0.364       978.971
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[3]                    jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0       Q       b13_nvmFL_fx2rbuQ[2]     0.364       986.326
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[2]                    jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0       Q       b13_nvmFL_fx2rbuQ[1]     0.364       986.487
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[1]                    jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0       Q       b13_nvmFL_fx2rbuQ[0]     0.364       987.959
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[5]                    jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0       Q       b12_ORbIwXaEF_bd         0.364       988.530
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[4]                    jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0       Q       b13_nvmFL_fx2rbuQ[3]     0.364       989.917
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[0]                    jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0       Q       b11_uRrc_WYOFjZ[0]       0.364       990.405
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[0]       jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1       Q       b6_nUT_IF[0]             0.364       998.596
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[1]       jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1       Q       b6_nUT_IF[1]             0.364       998.596
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[2]       jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1       Q       b6_nUT_IF[2]             0.364       998.596
    =======================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                      Starting                                                                                       Required
    Instance                                          Reference                                             Type     Pin     Net                     Time         Slack
                                                      Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b3_SoW.b9_2_mzCDYXs[5]                jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b9_2_mzCDYXs_5_i[5]     999.690      978.971
    iice_inst_0.b3_SoW.b9_2_mzCDYXs[6]                jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b9_2_mzCDYXs_5_i[6]     999.690      978.971
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[5]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b7_nYhI39s_10[5]        999.690      979.324
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[6]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b7_nYhI39s_10[6]        999.690      979.324
    iice_inst_0.b3_SoW.b9_2_mzCDYXs[4]                jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b9_2_mzCDYXs_5_i[4]     999.690      979.928
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[4]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b7_nYhI39s_10[4]        999.690      980.281
    iice_inst_0.b3_SoW.b9_2_mzCDYXs[3]                jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b9_2_mzCDYXs_5_i[3]     999.690      980.778
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[3]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b7_nYhI39s_10[3]        999.690      981.131
    iice_inst_0.b3_SoW.b9_2_mzCDYXs[2]                jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b9_2_mzCDYXs_5_i[2]     999.690      981.735
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[2]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1     D       b7_nYhI39s_10[2]        999.690      982.088
    =====================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
        Requested Period:                        1000.000
        - Setup time:                            0.310
        = Required time:                         999.690

        - Propagation time:                      20.719
        = Slack (non-critical) :                 978.971

        Number of logic level(s):                11
        Starting point:                          iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY / Q
        Ending point:                            iice_inst_0.b3_SoW.b9_2_mzCDYXs[5] / D
        The start point is clocked by            jtag_interface|identify_clk2_no_clk_buffer_needed [rising] on pin CLK
        The end   point is clocked by            jtag_interface|identify_clk2_no_clk_buffer_needed [rising] on pin CLK

    Instance / Net                                                                   Pin      Pin               Arrival     No. of
    Name                                                                Type         Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY         DFN1E1C1     Q        Out     0.364     0.364       -
    b8_vABZ3qsY                                                         Net          -        -       0.630     -           1
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b10_Ocm0f_kKwf.un15_b8_vabz3qsy     OA1          C        In      -         0.994       -
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b10_Ocm0f_kKwf.un15_b8_vabz3qsy     OA1          Y        Out     0.239     1.233       -
    un15_b8_vabz3qsy                                                    Net          -        -       2.330     -           5
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0_a3               OR3B         A        In      -         3.563       -
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0_a3               OR3B         Y        Out     0.297     3.860       -
    N_149                                                               Net          -        -       0.630     -           1
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0                  OR2A         A        In      -         4.490       -
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0                  OR2A         Y        Out     0.305     4.795       -
    b8_SoWGfWYY                                                         Net          -        -       5.050     -           16
    iice_inst_0.b3_SoW.b8_jAA_KlCO_1_sqmuxa_0_a2                        NOR3A        B        In      -         9.845       -
    iice_inst_0.b3_SoW.b8_jAA_KlCO_1_sqmuxa_0_a2                        NOR3A        Y        Out     0.276     10.121      -
    b8_jAA_KlCO_1_sqmuxa                                                Net          -        -       1.480     -           3
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_3                             AND2         A        In      -         11.601      -
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_3                             AND2         Y        Out     0.293     11.894      -
    DWACT_ADD_CI_0_TMP_0[2]                                             Net          -        -       0.630     -           1
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_4                             OR3          C        In      -         12.524      -
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_4                             OR3          Y        Out     0.416     12.940      -
    DWACT_ADD_CI_0_g_array_0_0[0]                                       Net          -        -       1.060     -           2
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_31                            AO1          B        In      -         14.000      -
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_31                            AO1          Y        Out     0.327     14.326      -
    DWACT_ADD_CI_0_g_array_1_0[0]                                       Net          -        -       1.480     -           3
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_38                            AO1          B        In      -         15.807      -
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_38                            AO1          Y        Out     0.327     16.133      -
    DWACT_ADD_CI_0_g_array_2_0[0]                                       Net          -        -       1.480     -           3
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_34                            AO1          B        In      -         17.613      -
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_34                            AO1          Y        Out     0.327     17.940      -
    DWACT_ADD_CI_0_g_array_12_1_0[0]                                    Net          -        -       0.630     -           1
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_29                            XOR2         B        In      -         18.570      -
    iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_29                            XOR2         Y        Out     0.520     19.090      -
    I_29_1                                                              Net          -        -       0.630     -           1
    iice_inst_0.b3_SoW.b8_2FsG_vuY.b9_2_mzCDYXs_5_i[5]                  NOR3A        A        In      -         19.720      -
    iice_inst_0.b3_SoW.b8_2FsG_vuY.b9_2_mzCDYXs_5_i[5]                  NOR3A        Y        Out     0.369     20.089      -
    b9_2_mzCDYXs_5_i[5]                                                 Net          -        -       0.630     -           1
    iice_inst_0.b3_SoW.b9_2_mzCDYXs[5]                                  DFN1         D        In      -         20.719      -
    ==================================================================================================================================
    Total path delay (propagation time + setup) of 21.029 is 4.369(20.8%) logic and 16.660(79.2%) route.

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                      Starting                                             Arrival
    Instance                                          Reference     Type       Pin        Net              Time        Slack
                                                      Clock
    --------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     System        UJTAG      UIREG3     b6_uS_MrX[2]     3.000       958.140
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     System        UJTAG      UIREG5     b6_uS_MrX[4]     3.000       958.154
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     System        UJTAG      UIREG4     b6_uS_MrX[3]     3.000       958.280
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     System        UJTAG      UIREG2     b6_uS_MrX[1]     3.000       959.173
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     System        UJTAG      UIREG6     b3_1Um           3.000       959.292
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     System        UJTAG      UIREG1     b6_uS_MrX[0]     3.000       960.125
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     System        UJTAG      UDRCAP     b7_nFG0rDY       3.000       969.047
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw     System        UJTAG      UDRSH      b5_OvyH3         3.000       970.015
    U1.sbulk                                          System        DFN1C1     Q          sbulk            0.364       973.326
    U1.ssector                                        System        DFN1C1     Q          ssector          0.364       973.401
    ==========================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                           Starting                                             Required
    Instance                               Reference     Type     Pin     Net                   Time         Slack
                                           Clock
    ----------------------------------------------------------------------------------------------------------------
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[5]     System        DFN1     D       b9_v_mzCDYXs_5[5]     999.690      958.140
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[6]     System        DFN1     D       b9_v_mzCDYXs_5[6]     999.690      958.140
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[4]     System        DFN1     D       b9_v_mzCDYXs_5[4]     999.690      959.097
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[3]     System        DFN1     D       b9_v_mzCDYXs_5[3]     999.690      959.947
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[2]     System        DFN1     D       b9_v_mzCDYXs_5[2]     999.690      960.904
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[1]     System        DFN1     D       b9_v_mzCDYXs_5[1]     999.690      962.711
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[0]     System        DFN1     D       b9_v_mzCDYXs_5[0]     999.590      964.141
    iice_inst_0.b3_SoW.b7_nYJ_BFM[0]       System        DFN1     D       b7_nYJ_BFM_1[0]       999.590      971.818
    iice_inst_0.b3_SoW.b7_nYJ_BFM[1]       System        DFN1     D       b7_nYJ_BFM_1[1]       999.590      971.942
    iice_inst_0.b3_SoW.b7_nYJ_BFM[2]       System        DFN1     D       b7_nYJ_BFM_1[2]       999.590      971.942
    ================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
        Requested Period:                        1000.000
        - Setup time:                            0.310
        = Required time:                         999.690

        - Propagation time:                      41.550
        = Slack (non-critical) :                 958.140

        Number of logic level(s):                16
        Starting point:                          comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw / UIREG3
        Ending point:                            iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] / D
        The start point is clocked by            jtag_interface|b3_PK3_inferred_clock [rising]
        The end   point is clocked by            jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK

    Instance / Net                                                           Pin        Pin               Arrival     No. of
    Name                                                           Type      Name       Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw                  UJTAG     UIREG3     Out     0.000     3.000       -
    b6_uS_MrX[2]                                                   Net       -          -       0.630     -           1
    comm_block_inst.jtag_block.jtagi.b9_nv_cLqgOF_2_1              OR3       C          In      -         3.630       -
    comm_block_inst.jtag_block.jtagi.b9_nv_cLqgOF_2_1              OR3       Y          Out     0.416     4.046       -
    b9_nv_cLqgOF_2_1                                               Net       -          -       1.060     -           2
    comm_block_inst.jtag_block.jtagi.b9_nv_cLqgOF_0                OR3A      B          In      -         5.106       -
    comm_block_inst.jtag_block.jtagi.b9_nv_cLqgOF_0                OR3A      Y          Out     0.403     5.509       -
    b9_nv_cLqgOF_0                                                 Net       -          -       1.900     -           4
    comm_block_inst.b11_uRrc_9urXBb[0]                             NOR3B     C          In      -         7.409       -
    comm_block_inst.b11_uRrc_9urXBb[0]                             NOR3B     Y          Out     0.276     7.685       -
    b11_uRrc_9urXBb[0]                                             Net       -          -       2.330     -           5
    iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLH_ab_0_a2_0     OR3A      A          In      -         10.015      -
    iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLH_ab_0_a2_0     OR3A      Y          Out     0.297     10.312      -
    b9_nvmFLH_ab_0_a2_0                                            Net       -          -       1.480     -           3
    iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLH_ab_0_a2       NOR3A     C          In      -         11.792      -
    iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLH_ab_0_a2       NOR3A     Y          Out     0.403     12.195      -
    b14_OFWNT9khWqH_3i                                             Net       -          -       6.700     -           49
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b8_OvyH3_YG                 NOR2B     B          In      -         18.895      -
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b8_OvyH3_YG                 NOR2B     Y          Out     0.351     19.246      -
    b9_OozFwN_ab                                                   Net       -          -       6.680     -           46
    iice_inst_0.b3_SoW.b7_vFsG_9u.un1_b9_oozfwn_ab                 OR2B      A          In      -         25.926      -
    iice_inst_0.b3_SoW.b7_vFsG_9u.un1_b9_oozfwn_ab                 OR2B      Y          Out     0.293     26.219      -
    un1_b9_oozfwn_ab                                               Net       -          -       1.060     -           2
    iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa_0                     AO1       C          In      -         27.279      -
    iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa_0                     AO1       Y          Out     0.363     27.642      -
    b9_v_mzCDYXs_1_sqmuxa_0                                        Net       -          -       0.630     -           1
    iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa                       AOI1      C          In      -         28.272      -
    iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa                       AOI1      Y          Out     0.300     28.572      -
    b9_v_mzCDYXs_1_sqmuxa                                          Net       -          -       3.990     -           10
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_3                        AND2      A          In      -         32.562      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_3                        AND2      Y          Out     0.293     32.855      -
    DWACT_ADD_CI_0_TMP[2]                                          Net       -          -       0.630     -           1
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_4                        OR3       C          In      -         33.485      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_4                        OR3       Y          Out     0.416     33.901      -
    DWACT_ADD_CI_0_g_array_0[0]                                    Net       -          -       1.060     -           2
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_31                       AO1       B          In      -         34.961      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_31                       AO1       Y          Out     0.327     35.288      -
    DWACT_ADD_CI_0_g_array_1[0]                                    Net       -          -       1.480     -           3
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_38                       AO1       B          In      -         36.767      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_38                       AO1       Y          Out     0.327     37.094      -
    DWACT_ADD_CI_0_g_array_2[0]                                    Net       -          -       1.480     -           3
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_34                       AO1       B          In      -         38.574      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_34                       AO1       Y          Out     0.327     38.901      -
    DWACT_ADD_CI_0_g_array_12_1[0]                                 Net       -          -       0.630     -           1
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_29                       XOR2      B          In      -         39.531      -
    iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_29                       XOR2      Y          Out     0.520     40.051      -
    I_29_0                                                         Net       -          -       0.630     -           1
    iice_inst_0.b3_SoW.b8_vFsG_vuY.b9_v_mzCDYXs_5[5]               OA1       C          In      -         40.681      -
    iice_inst_0.b3_SoW.b8_vFsG_vuY.b9_v_mzCDYXs_5[5]               OA1       Y          Out     0.239     40.920      -
    b9_v_mzCDYXs_5[5]                                              Net       -          -       0.630     -           1
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[5]                             DFN1      D          In      -         41.550      -
    ============================================================================================================================
    Total path delay (propagation time + setup) of 41.860 is 5.860(14.0%) logic and 33.000(78.8%) route.

    ##### END OF TIMING REPORT #####]

    --------------------------------------------------------------------------------
    Report for cell config_top.rtl
      Cell usage:
                  cell count     area count*area
                   MX2   168      1.0      168.0
                  DFN1   152      1.0      152.0
                  XOR2   105      1.0      105.0
                 AOI1B    78      1.0       78.0
                DFN1C1    68      1.0       68.0
                 NOR2B    68      1.0       68.0
              DFN1E1C1    53      1.0       53.0
                  OR2B    52      1.0       52.0
                   AO1    50      1.0       50.0
                  AND2    46      1.0       46.0
                 NOR2A    45      1.0       45.0
                 NOR3C    44      1.0       44.0
                  MX2C    40      1.0       40.0
                  NOR2    40      1.0       40.0
                 NOR3A    38      1.0       38.0
                DFN1E0    36      1.0       36.0
                   GND    31      0.0        0.0
                   VCC    31      0.0        0.0
                DFN1E1    29      1.0       29.0
                  AND3    22      1.0       22.0
                   OR2    21      1.0       21.0
                  AO1B    20      1.0       20.0
                  OR2A    19      1.0       19.0
                 NOR3B    18      1.0       18.0
                  OR3B    14      1.0       14.0
                 XNOR2    14      1.0       14.0
                DFN1P1    11      1.0       11.0
                  NOR3    11      1.0       11.0
                  OR3A    10      1.0       10.0
                   OR3     9      1.0        9.0
                   INV     9      1.0        9.0
                DFN0C1     8      1.0        8.0
                   OA1     8      1.0        8.0
              DFN1E0C1     8      1.0        8.0
                  OA1C     7      1.0        7.0
                  AO1C     7      1.0        7.0
                  OR3C     7      1.0        7.0
                   AX1     7      1.0        7.0
                  OA1B     7      1.0        7.0
                  AO1A     6      1.0        6.0
                  MAJ3     6      1.0        6.0
                  AOI1     6      1.0        6.0
              DFN1E1P1     5      1.0        5.0
                  BUFF     4      1.0        4.0
                  OAI1     4      1.0        4.0
                  MX2A     4      1.0        4.0
                  AX1C     3      1.0        3.0
             RAM512X18     3      0.0        0.0
                  OA1A     3      1.0        3.0
                   NVM     2      0.0        0.0
                CLKINT     2      0.0        0.0
                  XA1A     2      1.0        2.0
                 INBUF     2      0.0        0.0
                CLKBUF     2      0.0        0.0
                  XA1C     1      1.0        1.0
                 BIBUF     1      0.0        0.0
                  MIN3     1      1.0        1.0
                  AX1A     1      1.0        1.0
                RAM4K9     1      0.0        0.0
                   PLL     1      0.0        0.0
                 RCOSC     1      0.0        0.0
                 UJTAG     1      0.0        0.0
                 XNOR3     1      1.0        1.0
                  AO13     1      1.0        1.0
                 ZOR3I     1      1.0        1.0
                  AX1B     1      1.0        1.0
                       -----          ----------
                 TOTAL  1477              1399.0
    Mapper successful!
    Process took 0h:00m:09s realtime, 0h:00m:08s cputime
    # Thu Feb 08 19:30:20 2007

    ###########################################################]

`