-- Generated by WaveFormer Lite Version 10.04a at 18:3:52 on 2/9/2007
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       RST
--       CSn
--       DI

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library fusion;
library ieee;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    RST : inout std_logic := '0';
    CSn : inout std_logic := '1';
    CLK : inout std_logic := '0';
    DI : inout std_logic := '0';
    DO : inout std_logic := 'Z');

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Parm Declarations
  signal CLK_MinHL : time := 0 ns;
  signal CLK_MaxHL : time := 0 ns;
  signal CLK_MinLH : time := 0 ns;
  signal CLK_MaxLH : time := 0 ns;
  signal CLK_JFall : time := 0 ns;
  signal CLK_JRise : time := 0 ns;
  signal CLK_Duty : real := 0.0;
  signal CLK_Period : time := 0 ns;
  signal CLK_Offset : time := 0 ns;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 11479000 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
    variable CLK_MinHL_real : real;
    variable CLK_MaxHL_real : real;
    variable CLK_MinLH_real : real;
    variable CLK_MaxLH_real : real;
    variable CLK_JFall_real : real;
    variable CLK_JRise_real : real;
    variable CLK_Duty_real : real;
    variable CLK_Period_real : real;
    variable CLK_Offset_real : real;
  begin
    CLK_MinHL_real := 0.0;
    CLK_MinHL <= CLK_MinHL_real * 1 ns;
    CLK_MaxHL_real := 0.0;
    CLK_MaxHL <= CLK_MaxHL_real * 1 ns;
    CLK_MinLH_real := 0.0;
    CLK_MinLH <= CLK_MinLH_real * 1 ns;
    CLK_MaxLH_real := 0.0;
    CLK_MaxLH <= CLK_MaxLH_real * 1 ns;
    CLK_JFall_real := 0.0;
    CLK_JFall <= CLK_JFall_real * 1 ns;
    CLK_JRise_real := 0.0;
    CLK_JRise <= CLK_JRise_real * 1 ns;
    CLK_Duty_real := 50.0;
    CLK_Duty <= CLK_Duty_real;
    CLK_Period_real := 1000.0;
    CLK_Period <= CLK_Period_real * 1 ns;
    CLK_Offset_real := 0.0;
    CLK_Offset <= CLK_Offset_real * 1 ns;
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocks

  -- Clock Instantiation
  tb_CLK : entity syncad_vhdl_lib.tb_clock_minmax
    generic map (name => "tb_CLK",
                initialize => true,
                state1 => '1',
                state2 => '0')
    port map (tb_status,
              CLK,
              CLK_MinLH,
              CLK_MaxLH,
              CLK_MinHL,
              CLK_MaxHL,
              CLK_Offset,
              CLK_Period,
              CLK_Duty,
              CLK_JRise,
              CLK_JFall);

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 349 ns;
    RST <= '1';
    wait for 336 ns;
    RST <= '0';
    wait for 866 ns;
    CSn <= '0';
--    wait for 616 ns;
--    DI <= '1';
--    wait for 169 ns;
--    DI <= '0';

    wait for 5725 ns;
    DI <= '1';
    wait for 1961 ns;
    DI <= '0';
  
    wait for 3004970 ns;
    CSn <= '1';
    wait for 3019570 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library fusion;
library ieee;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal RST : std_logic;
  signal CSn : std_logic;
  signal CLK : std_logic;
  signal DI : std_logic;
  signal DO : std_logic;
 
  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (RST => RST,
              CSn => CSn,
              CLK => CLK,
              DI => DI,
              DO => DO);

  -- Instantiation of Model Under Test.
  config_top_0 : entity work.config_top
    port map (RST => RST,
              CSn => CSn,
              CLK => CLK,
              DI => DI,
              DO => DO);

end tbGeneratedCode;
