#  
# This is an automatically generated script file for loading the instrumented 
# design into Synplify. 
# 
add_file -vhdl -lib work  "D:/Libero72/Synplify/Synplify_85F/lib/proasic/fusion.vhd"
add_file -vhdl -lib work  "D:/ProgrammingSRAM/sconfig/synthesis/rev_1_identify_1/instr_sources/smartgen/rc_osc/rc_osc.vhd"
add_file -vhdl -lib work  "D:/ProgrammingSRAM/sconfig/synthesis/rev_1_identify_1/instr_sources/smartgen/PLL_60_40_10/PLL_60_40_10.vhd"
add_file -vhdl -lib work  "D:/ProgrammingSRAM/sconfig/synthesis/rev_1_identify_1/instr_sources/smartgen/ram256x8/ram256x8.vhd"
add_file -vhdl -lib work  "D:/ProgrammingSRAM/sconfig/synthesis/rev_1_identify_1/instr_sources/hdl/sconfig.vhd"
add_file -vhdl -lib work  "D:/ProgrammingSRAM/sconfig/synthesis/rev_1_identify_1/instr_sources/smartgen/cfgnvm/cfgnvm.vhd"
add_file -vhdl -lib work  "D:/ProgrammingSRAM/sconfig/synthesis/rev_1_identify_1/instr_sources/hdl/config_top.vhd"
add_file "D:/ProgrammingSRAM/sconfig/synthesis/rev_1_identify_1/instr_sources/syn_dics.vhd"
set_option -top_module config_top
set_option -technology FUSION
set_option -dup 0
