-- NVM_2_blocks.vhd
-- NVM wrapper for NVM1 and NVM2 generated by Smartgen
-- nvm_addr(18) is used to check which block the data is coming from
--****************************************************************************
-- IMPORTANT-READ THESE TERMS CAREFULLY BEFORE UTILIZING THE INFORMATION
-- CONTAINED IN THIS APPLICATION NOTE. 
--
-- NO SUPPORT/NO WARRANTY. THE DESIGN FILES AND DOCUMENTATION ARE PROVIDED
-- WITHOUT SUPPORT OR WARRANTY OF ANY KIND. ACTEL IS NOT OBLIGATED TO 
-- PROVIDE UPDATES, BUG FIXES, OR TECHNICAL SUPPORT AND DISCLAIMS ALL 
-- WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE, AND WARRANTIES OF NON-INFRINGEMENT OF THE
-- RIGHTS OF THIRD PARTIES (INCLUDING, WITHOUT LIMITATION, RIGHTS UNDER PATENT,
-- COPYRIGHT, TRADE SECRET, OR OTHER INTELLECTUAL PROPERTY RIGHTS).  RECIPIENT
-- ACCEPTS THE APPLICATION NOTE DESIGN FILES AND DOCUMENTATION IN "AS-IS"
-- CONDITION.
--*****************************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity NVM_2_blocks is 
port(rstn		: in    std_logic; -- 
     clk60M		: in    std_logic;
     nvm_addr   : in    std_logic_vector(18 downto 0);      
     nvm_read   : in    std_logic;
     nvm_dout	: out	std_logic_vector(7 downto 0);
	 nvm_din	: in	std_logic_vector(31 downto 0);
	 nvm_busy	: out	std_logic;
	 nvm_erase  : in	std_logic;
	 nvm_pgm	: in	std_logic;
	 nvm_we		: in	std_logic
);
end NVM_2_blocks;

architecture rtl of NVM_2_blocks is

component NVM1 is
    port(USER_CLK, USER_RESET : in std_logic; USER_ADD : 
        in std_logic_vector(17 downto 0); USER_AUX_BLOCK : in
         std_logic; USER_DATA : in std_logic_vector(31 downto 0); 
        USER_DISCARD_PAGE, USER_ERASE_PAGE, USER_OVERWRITE_PAGE, 
        USER_OVERWRITE_PROT, USER_PAGELOSS_PROT, USER_PROGRAM, 
        USER_READ, USER_READ_NEXT, USER_LOCK, USER_SPARE_PAGE, 
        USER_UNPROT_PAGE : in std_logic; USER_WIDTH : 
        in std_logic_vector(1 downto 0); USER_WRITE : in
         std_logic; USER_DOUT : out std_logic_vector(31 downto 0); 
        USER_PAGE_STATUS : in std_logic; USER_NVM_STATUS : 
        out std_logic_vector(1 downto 0); USER_NVM_BUSY : out
         std_logic);
end  component;

component NVM2 is
    port(USER_CLK, USER_RESET : in std_logic; USER_ADD : 
        in std_logic_vector(17 downto 0); USER_AUX_BLOCK : in
         std_logic; USER_DATA : in std_logic_vector(31 downto 0); 
        USER_DISCARD_PAGE, USER_ERASE_PAGE, USER_OVERWRITE_PAGE, 
        USER_OVERWRITE_PROT, USER_PAGELOSS_PROT, USER_PROGRAM, 
        USER_READ, USER_READ_NEXT, USER_LOCK, USER_SPARE_PAGE, 
        USER_UNPROT_PAGE : in std_logic; USER_WIDTH : 
        in std_logic_vector(1 downto 0); USER_WRITE : in
         std_logic; USER_DOUT : out std_logic_vector(31 downto 0); 
        USER_PAGE_STATUS : in std_logic; USER_NVM_STATUS : 
        out std_logic_vector(1 downto 0); USER_NVM_BUSY : out
         std_logic);
end  component;

	signal aerase			: std_logic;
	signal berase			: std_logic;
	signal apgm				: std_logic;
	signal bpgm				: std_logic;
	signal awe				: std_logic;
	signal bwe				: std_logic;
	signal awen				: std_logic;
	signal bwen				: std_logic;
	signal busy1			: std_logic;
	signal busy2			: std_logic;
	signal adata			: std_logic_vector(31 downto 0);
	signal bdata			: std_logic_vector(31 downto 0);

begin 

nvm_dout  <= adata(7 downto 0) when (nvm_addr(18) = '0') else
             bdata(7 downto 0);

aerase <= nvm_erase AND NOT(nvm_addr(18));
berase <= nvm_erase AND nvm_addr(18);

apgm   <= nvm_pgm AND NOT(nvm_addr(18));
bpgm   <= nvm_pgm AND nvm_addr(18);

awe    <= nvm_we AND NOT(nvm_addr(18));
bwe    <= nvm_we AND nvm_addr(18);

awen   <= NOT(awe);
bwen   <= NOT(bwe);

nvm_busy <= busy1 OR busy2;

M1:NVM1
port map(USER_RESET                => rstn,
         USER_CLK                  => clk60M,
         USER_ADD                  => nvm_addr(17 downto 0),
         USER_DATA                 => nvm_din,
         USER_DOUT                 => adata,
         USER_NVM_BUSY             => busy1,

         USER_WIDTH                => "00",
         USER_AUX_BLOCK            => '0',          
         USER_DISCARD_PAGE         => '0',
         USER_ERASE_PAGE           => aerase,
         USER_OVERWRITE_PAGE       => '0',
         USER_OVERWRITE_PROT       => '0',
         USER_PAGELOSS_PROT        => '0',
         USER_PROGRAM              => apgm, 
         USER_READ                 => nvm_read,
         USER_READ_NEXT            => nvm_read,   -- 1
         USER_LOCK                 => '0',
         USER_SPARE_PAGE           => '0', 
         USER_UNPROT_PAGE          => '0',
         USER_WRITE                => awe,
         USER_PAGE_STATUS          => '0',
         USER_NVM_STATUS           => open);

M2:NVM2
port map(USER_RESET                => rstn,
         USER_CLK                  => clk60M,
         USER_ADD                  => nvm_addr(17 downto 0),
         USER_DATA                 => nvm_din,
         USER_DOUT                 => bdata,
         USER_NVM_BUSY             => busy2,

         USER_WIDTH                => "00",
         USER_AUX_BLOCK            => '0',          
         USER_DISCARD_PAGE         => '0',
         USER_ERASE_PAGE           => berase,
         USER_OVERWRITE_PAGE       => '0',
         USER_OVERWRITE_PROT       => '0',
         USER_PAGELOSS_PROT        => '0',
         USER_PROGRAM              => bpgm, 
         USER_READ                 => nvm_read,
         USER_READ_NEXT            => nvm_read,   -- 1
         USER_LOCK                 => '0',
         USER_SPARE_PAGE           => '0', 
         USER_UNPROT_PAGE          => '0',
         USER_WRITE                => bwe,
         USER_PAGE_STATUS          => '0',
         USER_NVM_STATUS           => open);

end rtl;