-- Version: 8.0 8.0.0.40

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;

entity NVM2 is

    port( nvm_din  : in    std_logic_vector(7 downto 0);
          nvm_addr : in    std_logic_vector(17 downto 0);
          bdata_7  : out   std_logic;
          bdata_6  : out   std_logic;
          bdata_5  : out   std_logic;
          bdata_4  : out   std_logic;
          bdata_3  : out   std_logic;
          bdata_2  : out   std_logic;
          bdata_1  : out   std_logic;
          bdata_0  : out   std_logic;
          bwe      : in    std_logic;
          RST_c_i  : in    std_logic;
          nvm_read : in    std_logic;
          bpgm     : in    std_logic;
          berase   : in    std_logic;
          clk60M   : in    std_logic;
          \GND\    : in    std_logic;
          busy2    : out   std_logic
        );

end NVM2;

architecture DEF_ARCH of NVM2 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component NVM
    generic (MEMORYFILE:string := "");

    port( RD               : out   std_logic_vector(31 downto 0);
          BUSY             : out   std_logic;
          STATUS           : out   std_logic_vector(1 downto 0);
          ADDR             : in    std_logic_vector(17 downto 0) := (others => 'U');
          WD               : in    std_logic_vector(31 downto 0) := (others => 'U');
          DATAWIDTH        : in    std_logic_vector(1 downto 0) := (others => 'U');
          REN              : in    std_logic := 'U';
          WEN              : in    std_logic := 'U';
          PROGRAM          : in    std_logic := 'U';
          SPAREPAGE        : in    std_logic := 'U';
          AUXBLOCK         : in    std_logic := 'U';
          READNEXT         : in    std_logic := 'U';
          ERASEPAGE        : in    std_logic := 'U';
          UNPROTECTPAGE    : in    std_logic := 'U';
          DISCARDPAGE      : in    std_logic := 'U';
          OVERWRITEPROTECT : in    std_logic := 'U';
          PAGELOSSPROTECT  : in    std_logic := 'U';
          CLK              : in    std_logic := 'U';
          RESET            : in    std_logic := 'U';
          PAGESTATUS       : in    std_logic := 'U';
          OVERWRITEPAGE    : in    std_logic := 'U';
          PIPE             : in    std_logic := 'U';
          LOCKREQUEST      : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, \bdata[8]\, \bdata[9]\, \bdata[10]\, 
        \bdata[11]\, \bdata[12]\, \bdata[13]\, \bdata[14]\, 
        \bdata[15]\, \bdata[16]\, \bdata[17]\, \bdata[18]\, 
        \bdata[19]\, \bdata[20]\, \bdata[21]\, \bdata[22]\, 
        \bdata[23]\, \bdata[24]\, \bdata[25]\, \bdata[26]\, 
        \bdata[27]\, \bdata[28]\, \bdata[29]\, \bdata[30]\, 
        \bdata[31]\, \NVM_INST_STATUS[0]\, \NVM_INST_STATUS[1]\, 
        \VCC\, GND_net_2, VCC_net_1 : std_logic;

begin 

    GND_net_1 <= \GND\;

    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_2);
    
    NVM_INST : NVM
      generic map(MEMORYFILE => "NVM2.mem")

      port map(RD(31) => \bdata[31]\, RD(30) => \bdata[30]\, 
        RD(29) => \bdata[29]\, RD(28) => \bdata[28]\, RD(27) => 
        \bdata[27]\, RD(26) => \bdata[26]\, RD(25) => \bdata[25]\, 
        RD(24) => \bdata[24]\, RD(23) => \bdata[23]\, RD(22) => 
        \bdata[22]\, RD(21) => \bdata[21]\, RD(20) => \bdata[20]\, 
        RD(19) => \bdata[19]\, RD(18) => \bdata[18]\, RD(17) => 
        \bdata[17]\, RD(16) => \bdata[16]\, RD(15) => \bdata[15]\, 
        RD(14) => \bdata[14]\, RD(13) => \bdata[13]\, RD(12) => 
        \bdata[12]\, RD(11) => \bdata[11]\, RD(10) => \bdata[10]\, 
        RD(9) => \bdata[9]\, RD(8) => \bdata[8]\, RD(7) => 
        bdata_7, RD(6) => bdata_6, RD(5) => bdata_5, RD(4) => 
        bdata_4, RD(3) => bdata_3, RD(2) => bdata_2, RD(1) => 
        bdata_1, RD(0) => bdata_0, BUSY => busy2, STATUS(1) => 
        \NVM_INST_STATUS[1]\, STATUS(0) => \NVM_INST_STATUS[0]\, 
        ADDR(17) => nvm_addr(17), ADDR(16) => nvm_addr(16), 
        ADDR(15) => nvm_addr(15), ADDR(14) => nvm_addr(14), 
        ADDR(13) => nvm_addr(13), ADDR(12) => nvm_addr(12), 
        ADDR(11) => nvm_addr(11), ADDR(10) => nvm_addr(10), 
        ADDR(9) => nvm_addr(9), ADDR(8) => nvm_addr(8), ADDR(7)
         => nvm_addr(7), ADDR(6) => nvm_addr(6), ADDR(5) => 
        nvm_addr(5), ADDR(4) => nvm_addr(4), ADDR(3) => 
        nvm_addr(3), ADDR(2) => nvm_addr(2), ADDR(1) => 
        nvm_addr(1), ADDR(0) => nvm_addr(0), WD(31) => GND_net_1, 
        WD(30) => GND_net_1, WD(29) => GND_net_1, WD(28) => 
        GND_net_1, WD(27) => GND_net_1, WD(26) => GND_net_1, 
        WD(25) => GND_net_1, WD(24) => GND_net_1, WD(23) => 
        GND_net_1, WD(22) => GND_net_1, WD(21) => GND_net_1, 
        WD(20) => GND_net_1, WD(19) => GND_net_1, WD(18) => 
        GND_net_1, WD(17) => GND_net_1, WD(16) => GND_net_1, 
        WD(15) => GND_net_1, WD(14) => GND_net_1, WD(13) => 
        GND_net_1, WD(12) => GND_net_1, WD(11) => GND_net_1, 
        WD(10) => GND_net_1, WD(9) => GND_net_1, WD(8) => 
        GND_net_1, WD(7) => nvm_din(7), WD(6) => nvm_din(6), 
        WD(5) => nvm_din(5), WD(4) => nvm_din(4), WD(3) => 
        nvm_din(3), WD(2) => nvm_din(2), WD(1) => nvm_din(1), 
        WD(0) => nvm_din(0), DATAWIDTH(1) => GND_net_1, 
        DATAWIDTH(0) => GND_net_1, REN => nvm_read, WEN => bwe, 
        PROGRAM => bpgm, SPAREPAGE => GND_net_1, AUXBLOCK => 
        GND_net_1, READNEXT => nvm_read, ERASEPAGE => berase, 
        UNPROTECTPAGE => GND_net_1, DISCARDPAGE => GND_net_1, 
        OVERWRITEPROTECT => GND_net_1, PAGELOSSPROTECT => 
        GND_net_1, CLK => clk60M, RESET => RST_c_i, PAGESTATUS
         => GND_net_1, OVERWRITEPAGE => GND_net_1, PIPE => 
        GND_net_1, LOCKREQUEST => GND_net_1);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;

entity NVM1 is

    port( nvm_din  : in    std_logic_vector(7 downto 0);
          nvm_addr : in    std_logic_vector(17 downto 0);
          adata_7  : out   std_logic;
          adata_6  : out   std_logic;
          adata_5  : out   std_logic;
          adata_4  : out   std_logic;
          adata_3  : out   std_logic;
          adata_2  : out   std_logic;
          adata_1  : out   std_logic;
          adata_0  : out   std_logic;
          awe      : in    std_logic;
          RST_c_i  : in    std_logic;
          nvm_read : in    std_logic;
          apgm     : in    std_logic;
          aerase   : in    std_logic;
          clk60M   : in    std_logic;
          \GND\    : in    std_logic;
          busy1    : out   std_logic
        );

end NVM1;

architecture DEF_ARCH of NVM1 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component NVM
    generic (MEMORYFILE:string := "");

    port( RD               : out   std_logic_vector(31 downto 0);
          BUSY             : out   std_logic;
          STATUS           : out   std_logic_vector(1 downto 0);
          ADDR             : in    std_logic_vector(17 downto 0) := (others => 'U');
          WD               : in    std_logic_vector(31 downto 0) := (others => 'U');
          DATAWIDTH        : in    std_logic_vector(1 downto 0) := (others => 'U');
          REN              : in    std_logic := 'U';
          WEN              : in    std_logic := 'U';
          PROGRAM          : in    std_logic := 'U';
          SPAREPAGE        : in    std_logic := 'U';
          AUXBLOCK         : in    std_logic := 'U';
          READNEXT         : in    std_logic := 'U';
          ERASEPAGE        : in    std_logic := 'U';
          UNPROTECTPAGE    : in    std_logic := 'U';
          DISCARDPAGE      : in    std_logic := 'U';
          OVERWRITEPROTECT : in    std_logic := 'U';
          PAGELOSSPROTECT  : in    std_logic := 'U';
          CLK              : in    std_logic := 'U';
          RESET            : in    std_logic := 'U';
          PAGESTATUS       : in    std_logic := 'U';
          OVERWRITEPAGE    : in    std_logic := 'U';
          PIPE             : in    std_logic := 'U';
          LOCKREQUEST      : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, \adata[8]\, \adata[9]\, \adata[10]\, 
        \adata[11]\, \adata[12]\, \adata[13]\, \adata[14]\, 
        \adata[15]\, \adata[16]\, \adata[17]\, \adata[18]\, 
        \adata[19]\, \adata[20]\, \adata[21]\, \adata[22]\, 
        \adata[23]\, \adata[24]\, \adata[25]\, \adata[26]\, 
        \adata[27]\, \adata[28]\, \adata[29]\, \adata[30]\, 
        \adata[31]\, \NVM_INST_STATUS[0]_0\, 
        \NVM_INST_STATUS[1]_0\, \VCC\, GND_net_2, VCC_net_1
         : std_logic;

begin 

    GND_net_1 <= \GND\;

    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_2);
    
    NVM_INST : NVM
      generic map(MEMORYFILE => "NVM1.mem")

      port map(RD(31) => \adata[31]\, RD(30) => \adata[30]\, 
        RD(29) => \adata[29]\, RD(28) => \adata[28]\, RD(27) => 
        \adata[27]\, RD(26) => \adata[26]\, RD(25) => \adata[25]\, 
        RD(24) => \adata[24]\, RD(23) => \adata[23]\, RD(22) => 
        \adata[22]\, RD(21) => \adata[21]\, RD(20) => \adata[20]\, 
        RD(19) => \adata[19]\, RD(18) => \adata[18]\, RD(17) => 
        \adata[17]\, RD(16) => \adata[16]\, RD(15) => \adata[15]\, 
        RD(14) => \adata[14]\, RD(13) => \adata[13]\, RD(12) => 
        \adata[12]\, RD(11) => \adata[11]\, RD(10) => \adata[10]\, 
        RD(9) => \adata[9]\, RD(8) => \adata[8]\, RD(7) => 
        adata_7, RD(6) => adata_6, RD(5) => adata_5, RD(4) => 
        adata_4, RD(3) => adata_3, RD(2) => adata_2, RD(1) => 
        adata_1, RD(0) => adata_0, BUSY => busy1, STATUS(1) => 
        \NVM_INST_STATUS[1]_0\, STATUS(0) => 
        \NVM_INST_STATUS[0]_0\, ADDR(17) => nvm_addr(17), 
        ADDR(16) => nvm_addr(16), ADDR(15) => nvm_addr(15), 
        ADDR(14) => nvm_addr(14), ADDR(13) => nvm_addr(13), 
        ADDR(12) => nvm_addr(12), ADDR(11) => nvm_addr(11), 
        ADDR(10) => nvm_addr(10), ADDR(9) => nvm_addr(9), ADDR(8)
         => nvm_addr(8), ADDR(7) => nvm_addr(7), ADDR(6) => 
        nvm_addr(6), ADDR(5) => nvm_addr(5), ADDR(4) => 
        nvm_addr(4), ADDR(3) => nvm_addr(3), ADDR(2) => 
        nvm_addr(2), ADDR(1) => nvm_addr(1), ADDR(0) => 
        nvm_addr(0), WD(31) => GND_net_1, WD(30) => GND_net_1, 
        WD(29) => GND_net_1, WD(28) => GND_net_1, WD(27) => 
        GND_net_1, WD(26) => GND_net_1, WD(25) => GND_net_1, 
        WD(24) => GND_net_1, WD(23) => GND_net_1, WD(22) => 
        GND_net_1, WD(21) => GND_net_1, WD(20) => GND_net_1, 
        WD(19) => GND_net_1, WD(18) => GND_net_1, WD(17) => 
        GND_net_1, WD(16) => GND_net_1, WD(15) => GND_net_1, 
        WD(14) => GND_net_1, WD(13) => GND_net_1, WD(12) => 
        GND_net_1, WD(11) => GND_net_1, WD(10) => GND_net_1, 
        WD(9) => GND_net_1, WD(8) => GND_net_1, WD(7) => 
        nvm_din(7), WD(6) => nvm_din(6), WD(5) => nvm_din(5), 
        WD(4) => nvm_din(4), WD(3) => nvm_din(3), WD(2) => 
        nvm_din(2), WD(1) => nvm_din(1), WD(0) => nvm_din(0), 
        DATAWIDTH(1) => GND_net_1, DATAWIDTH(0) => GND_net_1, REN
         => nvm_read, WEN => awe, PROGRAM => apgm, SPAREPAGE => 
        GND_net_1, AUXBLOCK => GND_net_1, READNEXT => nvm_read, 
        ERASEPAGE => aerase, UNPROTECTPAGE => GND_net_1, 
        DISCARDPAGE => GND_net_1, OVERWRITEPROTECT => GND_net_1, 
        PAGELOSSPROTECT => GND_net_1, CLK => clk60M, RESET => 
        RST_c_i, PAGESTATUS => GND_net_1, OVERWRITEPAGE => 
        GND_net_1, PIPE => GND_net_1, LOCKREQUEST => GND_net_1);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;

entity NVM_2_blocks is

    port( nvm_din    : in    std_logic_vector(7 downto 0);
          nvm_addr   : in    std_logic_vector(18 downto 0);
          nvm_dout   : out   std_logic_vector(7 downto 0);
          nvm_addr_0 : in    std_logic_vector(18 to 18);
          \GND\      : in    std_logic;
          clk60M     : in    std_logic;
          nvm_read   : in    std_logic;
          RST_c_i    : in    std_logic;
          nvm_busy   : out   std_logic;
          nvm_we     : in    std_logic;
          nvm_pgm    : in    std_logic;
          nvm_erase  : in    std_logic
        );

end NVM_2_blocks;

architecture DEF_ARCH of NVM_2_blocks is 

  component NVM2
    port( nvm_din  : in    std_logic_vector(7 downto 0) := (others => 'U');
          nvm_addr : in    std_logic_vector(17 downto 0) := (others => 'U');
          bdata_7  : out   std_logic;
          bdata_6  : out   std_logic;
          bdata_5  : out   std_logic;
          bdata_4  : out   std_logic;
          bdata_3  : out   std_logic;
          bdata_2  : out   std_logic;
          bdata_1  : out   std_logic;
          bdata_0  : out   std_logic;
          bwe      : in    std_logic := 'U';
          RST_c_i  : in    std_logic := 'U';
          nvm_read : in    std_logic := 'U';
          bpgm     : in    std_logic := 'U';
          berase   : in    std_logic := 'U';
          clk60M   : in    std_logic := 'U';
          \GND\    : in    std_logic := 'U';
          busy2    : out   std_logic
        );
  end component;

  component NOR2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MX2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          S : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component NVM1
    port( nvm_din  : in    std_logic_vector(7 downto 0) := (others => 'U');
          nvm_addr : in    std_logic_vector(17 downto 0) := (others => 'U');
          adata_7  : out   std_logic;
          adata_6  : out   std_logic;
          adata_5  : out   std_logic;
          adata_4  : out   std_logic;
          adata_3  : out   std_logic;
          adata_2  : out   std_logic;
          adata_1  : out   std_logic;
          adata_0  : out   std_logic;
          awe      : in    std_logic := 'U';
          RST_c_i  : in    std_logic := 'U';
          nvm_read : in    std_logic := 'U';
          apgm     : in    std_logic := 'U';
          aerase   : in    std_logic := 'U';
          clk60M   : in    std_logic := 'U';
          \GND\    : in    std_logic := 'U';
          busy1    : out   std_logic
        );
  end component;

  component NOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal GND_net_1, \berase\, \bpgm\, \bwe\, \aerase\, \apgm\, 
        \awe\, \adata[0]\, \bdata[0]\, \adata[1]\, \bdata[1]\, 
        \adata[2]\, \bdata[2]\, \adata[4]\, \bdata[4]\, 
        \adata[5]\, \bdata[5]\, \adata[6]\, \bdata[6]\, 
        \adata[7]\, \bdata[7]\, busy2, busy1, \adata[3]\, 
        \bdata[3]\, \VCC\, GND_net_2, VCC_net_1 : std_logic;

    for all : NVM2
	Use entity work.NVM2(DEF_ARCH);
    for all : NVM1
	Use entity work.NVM1(DEF_ARCH);
begin 

    GND_net_1 <= \GND\;

    M2 : NVM2
      port map(nvm_din(7) => nvm_din(7), nvm_din(6) => nvm_din(6), 
        nvm_din(5) => nvm_din(5), nvm_din(4) => nvm_din(4), 
        nvm_din(3) => nvm_din(3), nvm_din(2) => nvm_din(2), 
        nvm_din(1) => nvm_din(1), nvm_din(0) => nvm_din(0), 
        nvm_addr(17) => nvm_addr(17), nvm_addr(16) => 
        nvm_addr(16), nvm_addr(15) => nvm_addr(15), nvm_addr(14)
         => nvm_addr(14), nvm_addr(13) => nvm_addr(13), 
        nvm_addr(12) => nvm_addr(12), nvm_addr(11) => 
        nvm_addr(11), nvm_addr(10) => nvm_addr(10), nvm_addr(9)
         => nvm_addr(9), nvm_addr(8) => nvm_addr(8), nvm_addr(7)
         => nvm_addr(7), nvm_addr(6) => nvm_addr(6), nvm_addr(5)
         => nvm_addr(5), nvm_addr(4) => nvm_addr(4), nvm_addr(3)
         => nvm_addr(3), nvm_addr(2) => nvm_addr(2), nvm_addr(1)
         => nvm_addr(1), nvm_addr(0) => nvm_addr(0), bdata_7 => 
        \bdata[7]\, bdata_6 => \bdata[6]\, bdata_5 => \bdata[5]\, 
        bdata_4 => \bdata[4]\, bdata_3 => \bdata[3]\, bdata_2 => 
        \bdata[2]\, bdata_1 => \bdata[1]\, bdata_0 => \bdata[0]\, 
        bwe => \bwe\, RST_c_i => RST_c_i, nvm_read => nvm_read, 
        bpgm => \bpgm\, berase => \berase\, clk60M => clk60M, 
        \GND\ => GND_net_1, busy2 => busy2);
    
    bwe : NOR2B
      port map(A => nvm_we, B => nvm_addr_0(18), Y => \bwe\);
    
    berase : NOR2B
      port map(A => nvm_erase, B => nvm_addr_0(18), Y => \berase\);
    
    apgm : NOR2A
      port map(A => nvm_pgm, B => nvm_addr_0(18), Y => \apgm\);
    
    \nvm_dout[6]\ : MX2
      port map(A => \adata[6]\, B => \bdata[6]\, S => 
        nvm_addr(18), Y => nvm_dout(6));
    
    aerase : NOR2A
      port map(A => nvm_erase, B => nvm_addr_0(18), Y => \aerase\);
    
    GND_i_0 : GND
      port map(Y => GND_net_2);
    
    bpgm : NOR2B
      port map(A => nvm_pgm, B => nvm_addr_0(18), Y => \bpgm\);
    
    \nvm_dout[4]\ : MX2
      port map(A => \adata[4]\, B => \bdata[4]\, S => 
        nvm_addr(18), Y => nvm_dout(4));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    M1 : NVM1
      port map(nvm_din(7) => nvm_din(7), nvm_din(6) => nvm_din(6), 
        nvm_din(5) => nvm_din(5), nvm_din(4) => nvm_din(4), 
        nvm_din(3) => nvm_din(3), nvm_din(2) => nvm_din(2), 
        nvm_din(1) => nvm_din(1), nvm_din(0) => nvm_din(0), 
        nvm_addr(17) => nvm_addr(17), nvm_addr(16) => 
        nvm_addr(16), nvm_addr(15) => nvm_addr(15), nvm_addr(14)
         => nvm_addr(14), nvm_addr(13) => nvm_addr(13), 
        nvm_addr(12) => nvm_addr(12), nvm_addr(11) => 
        nvm_addr(11), nvm_addr(10) => nvm_addr(10), nvm_addr(9)
         => nvm_addr(9), nvm_addr(8) => nvm_addr(8), nvm_addr(7)
         => nvm_addr(7), nvm_addr(6) => nvm_addr(6), nvm_addr(5)
         => nvm_addr(5), nvm_addr(4) => nvm_addr(4), nvm_addr(3)
         => nvm_addr(3), nvm_addr(2) => nvm_addr(2), nvm_addr(1)
         => nvm_addr(1), nvm_addr(0) => nvm_addr(0), adata_7 => 
        \adata[7]\, adata_6 => \adata[6]\, adata_5 => \adata[5]\, 
        adata_4 => \adata[4]\, adata_3 => \adata[3]\, adata_2 => 
        \adata[2]\, adata_1 => \adata[1]\, adata_0 => \adata[0]\, 
        awe => \awe\, RST_c_i => RST_c_i, nvm_read => nvm_read, 
        apgm => \apgm\, aerase => \aerase\, clk60M => clk60M, 
        \GND\ => GND_net_1, busy1 => busy1);
    
    \nvm_dout[7]\ : MX2
      port map(A => \adata[7]\, B => \bdata[7]\, S => 
        nvm_addr(18), Y => nvm_dout(7));
    
    GND_i : GND
      port map(Y => GND_net_1);
    
    \nvm_dout[5]\ : MX2
      port map(A => \adata[5]\, B => \bdata[5]\, S => 
        nvm_addr(18), Y => nvm_dout(5));
    
    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \nvm_dout[2]\ : MX2
      port map(A => \adata[2]\, B => \bdata[2]\, S => 
        nvm_addr(18), Y => nvm_dout(2));
    
    \nvm_dout[0]\ : MX2
      port map(A => \adata[0]\, B => \bdata[0]\, S => 
        nvm_addr_0(18), Y => nvm_dout(0));
    
    \nvm_dout[3]\ : MX2
      port map(A => \adata[3]\, B => \bdata[3]\, S => 
        nvm_addr(18), Y => nvm_dout(3));
    
    \nvm_dout[1]\ : MX2
      port map(A => \adata[1]\, B => \bdata[1]\, S => 
        nvm_addr_0(18), Y => nvm_dout(1));
    
    \nvm_busy\ : NOR2
      port map(A => busy2, B => busy1, Y => nvm_busy);
    
    awe : NOR2A
      port map(A => nvm_we, B => nvm_addr_0(18), Y => \awe\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;

entity PLL_60_40_10 is

    port( RST_c_i : in    std_logic;
          \VCC\   : in    std_logic;
          \GND\   : in    std_logic;
          clk100M : in    std_logic;
          clk60M  : out   std_logic
        );

end PLL_60_40_10;

architecture DEF_ARCH of PLL_60_40_10 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component PLL
    generic (VCOFREQUENCY:real := 0.0);

    port( CLKA      : in    std_logic := 'U';
          EXTFB     : in    std_logic := 'U';
          POWERDOWN : in    std_logic := 'U';
          GLA       : out   std_logic;
          LOCK      : out   std_logic;
          GLB       : out   std_logic;
          YB        : out   std_logic;
          GLC       : out   std_logic;
          YC        : out   std_logic;
          OADIV0    : in    std_logic := 'U';
          OADIV1    : in    std_logic := 'U';
          OADIV2    : in    std_logic := 'U';
          OADIV3    : in    std_logic := 'U';
          OADIV4    : in    std_logic := 'U';
          OADIVHALF : in    std_logic := 'U';
          OADIVRST  : in    std_logic := 'U';
          OAMUX0    : in    std_logic := 'U';
          OAMUX1    : in    std_logic := 'U';
          OAMUX2    : in    std_logic := 'U';
          DLYGLA0   : in    std_logic := 'U';
          DLYGLA1   : in    std_logic := 'U';
          DLYGLA2   : in    std_logic := 'U';
          DLYGLA3   : in    std_logic := 'U';
          DLYGLA4   : in    std_logic := 'U';
          OBDIV0    : in    std_logic := 'U';
          OBDIV1    : in    std_logic := 'U';
          OBDIV2    : in    std_logic := 'U';
          OBDIV3    : in    std_logic := 'U';
          OBDIV4    : in    std_logic := 'U';
          OBMUX0    : in    std_logic := 'U';
          OBMUX1    : in    std_logic := 'U';
          OBMUX2    : in    std_logic := 'U';
          DLYYB0    : in    std_logic := 'U';
          DLYYB1    : in    std_logic := 'U';
          DLYYB2    : in    std_logic := 'U';
          DLYYB3    : in    std_logic := 'U';
          DLYYB4    : in    std_logic := 'U';
          DLYGLB0   : in    std_logic := 'U';
          DLYGLB1   : in    std_logic := 'U';
          DLYGLB2   : in    std_logic := 'U';
          DLYGLB3   : in    std_logic := 'U';
          DLYGLB4   : in    std_logic := 'U';
          OCDIV0    : in    std_logic := 'U';
          OCDIV1    : in    std_logic := 'U';
          OCDIV2    : in    std_logic := 'U';
          OCDIV3    : in    std_logic := 'U';
          OCDIV4    : in    std_logic := 'U';
          OCMUX0    : in    std_logic := 'U';
          OCMUX1    : in    std_logic := 'U';
          OCMUX2    : in    std_logic := 'U';
          DLYYC0    : in    std_logic := 'U';
          DLYYC1    : in    std_logic := 'U';
          DLYYC2    : in    std_logic := 'U';
          DLYYC3    : in    std_logic := 'U';
          DLYYC4    : in    std_logic := 'U';
          DLYGLC0   : in    std_logic := 'U';
          DLYGLC1   : in    std_logic := 'U';
          DLYGLC2   : in    std_logic := 'U';
          DLYGLC3   : in    std_logic := 'U';
          DLYGLC4   : in    std_logic := 'U';
          FINDIV0   : in    std_logic := 'U';
          FINDIV1   : in    std_logic := 'U';
          FINDIV2   : in    std_logic := 'U';
          FINDIV3   : in    std_logic := 'U';
          FINDIV4   : in    std_logic := 'U';
          FINDIV5   : in    std_logic := 'U';
          FINDIV6   : in    std_logic := 'U';
          FBDIV0    : in    std_logic := 'U';
          FBDIV1    : in    std_logic := 'U';
          FBDIV2    : in    std_logic := 'U';
          FBDIV3    : in    std_logic := 'U';
          FBDIV4    : in    std_logic := 'U';
          FBDIV5    : in    std_logic := 'U';
          FBDIV6    : in    std_logic := 'U';
          FBDLY0    : in    std_logic := 'U';
          FBDLY1    : in    std_logic := 'U';
          FBDLY2    : in    std_logic := 'U';
          FBDLY3    : in    std_logic := 'U';
          FBDLY4    : in    std_logic := 'U';
          FBSEL0    : in    std_logic := 'U';
          FBSEL1    : in    std_logic := 'U';
          XDLYSEL   : in    std_logic := 'U';
          VCOSEL0   : in    std_logic := 'U';
          VCOSEL1   : in    std_logic := 'U';
          VCOSEL2   : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal VCC_net_1, GND_net_1, clk40M, clk10M, Core_LOCK, 
        Core_YB, Core_YC, GND_net_2, VCC_net_2 : std_logic;

begin 

    VCC_net_1 <= \VCC\;
    GND_net_1 <= \GND\;

    VCC_i_0 : VCC
      port map(Y => VCC_net_2);
    
    Core : PLL
      generic map(VCOFREQUENCY => 120)

      port map(CLKA => clk100M, EXTFB => GND_net_1, POWERDOWN => 
        VCC_net_1, GLA => clk60M, LOCK => Core_LOCK, GLB => 
        clk40M, YB => Core_YB, GLC => clk10M, YC => Core_YC, 
        OADIV0 => VCC_net_1, OADIV1 => GND_net_1, OADIV2 => 
        GND_net_1, OADIV3 => GND_net_1, OADIV4 => GND_net_1, 
        OADIVHALF => GND_net_1, OADIVRST => RST_c_i, OAMUX0 => 
        GND_net_1, OAMUX1 => GND_net_1, OAMUX2 => VCC_net_1, 
        DLYGLA0 => GND_net_1, DLYGLA1 => GND_net_1, DLYGLA2 => 
        GND_net_1, DLYGLA3 => GND_net_1, DLYGLA4 => GND_net_1, 
        OBDIV0 => GND_net_1, OBDIV1 => VCC_net_1, OBDIV2 => 
        GND_net_1, OBDIV3 => GND_net_1, OBDIV4 => GND_net_1, 
        OBMUX0 => GND_net_1, OBMUX1 => VCC_net_1, OBMUX2 => 
        GND_net_1, DLYYB0 => GND_net_1, DLYYB1 => GND_net_1, 
        DLYYB2 => GND_net_1, DLYYB3 => GND_net_1, DLYYB4 => 
        GND_net_1, DLYGLB0 => GND_net_1, DLYGLB1 => GND_net_1, 
        DLYGLB2 => GND_net_1, DLYGLB3 => GND_net_1, DLYGLB4 => 
        GND_net_1, OCDIV0 => VCC_net_1, OCDIV1 => VCC_net_1, 
        OCDIV2 => GND_net_1, OCDIV3 => VCC_net_1, OCDIV4 => 
        GND_net_1, OCMUX0 => GND_net_1, OCMUX1 => VCC_net_1, 
        OCMUX2 => GND_net_1, DLYYC0 => GND_net_1, DLYYC1 => 
        GND_net_1, DLYYC2 => GND_net_1, DLYYC3 => GND_net_1, 
        DLYYC4 => GND_net_1, DLYGLC0 => GND_net_1, DLYGLC1 => 
        GND_net_1, DLYGLC2 => GND_net_1, DLYGLC3 => GND_net_1, 
        DLYGLC4 => GND_net_1, FINDIV0 => VCC_net_1, FINDIV1 => 
        VCC_net_1, FINDIV2 => GND_net_1, FINDIV3 => GND_net_1, 
        FINDIV4 => VCC_net_1, FINDIV5 => GND_net_1, FINDIV6 => 
        GND_net_1, FBDIV0 => VCC_net_1, FBDIV1 => VCC_net_1, 
        FBDIV2 => VCC_net_1, FBDIV3 => GND_net_1, FBDIV4 => 
        VCC_net_1, FBDIV5 => GND_net_1, FBDIV6 => GND_net_1, 
        FBDLY0 => GND_net_1, FBDLY1 => GND_net_1, FBDLY2 => 
        GND_net_1, FBDLY3 => GND_net_1, FBDLY4 => GND_net_1, 
        FBSEL0 => VCC_net_1, FBSEL1 => GND_net_1, XDLYSEL => 
        GND_net_1, VCOSEL0 => GND_net_1, VCOSEL1 => GND_net_1, 
        VCOSEL2 => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_2);
    
    VCC_i : VCC
      port map(Y => VCC_net_1);
    
    GND_i : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;

entity ram256x8 is

    port( wdata    : in    std_logic_vector(6 downto 0);
          wptr     : in    std_logic_vector(7 downto 0);
          waddr    : in    std_logic_vector(7 downto 0);
          nvm_din  : out   std_logic_vector(7 downto 0);
          RST_c_i  : in    std_logic;
          DI_c     : in    std_logic;
          clk60M   : in    std_logic;
          CLK_c    : in    std_logic;
          N_1923_i : in    std_logic;
          \GND\    : in    std_logic;
          \VCC\    : in    std_logic
        );

end ram256x8;

architecture DEF_ARCH of ram256x8 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component INV
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component RAM4K9
    generic (MEMORYFILE:string := "");

    port( ADDRA11 : in    std_logic := 'U';
          ADDRA10 : in    std_logic := 'U';
          ADDRA9  : in    std_logic := 'U';
          ADDRA8  : in    std_logic := 'U';
          ADDRA7  : in    std_logic := 'U';
          ADDRA6  : in    std_logic := 'U';
          ADDRA5  : in    std_logic := 'U';
          ADDRA4  : in    std_logic := 'U';
          ADDRA3  : in    std_logic := 'U';
          ADDRA2  : in    std_logic := 'U';
          ADDRA1  : in    std_logic := 'U';
          ADDRA0  : in    std_logic := 'U';
          ADDRB11 : in    std_logic := 'U';
          ADDRB10 : in    std_logic := 'U';
          ADDRB9  : in    std_logic := 'U';
          ADDRB8  : in    std_logic := 'U';
          ADDRB7  : in    std_logic := 'U';
          ADDRB6  : in    std_logic := 'U';
          ADDRB5  : in    std_logic := 'U';
          ADDRB4  : in    std_logic := 'U';
          ADDRB3  : in    std_logic := 'U';
          ADDRB2  : in    std_logic := 'U';
          ADDRB1  : in    std_logic := 'U';
          ADDRB0  : in    std_logic := 'U';
          DINA8   : in    std_logic := 'U';
          DINA7   : in    std_logic := 'U';
          DINA6   : in    std_logic := 'U';
          DINA5   : in    std_logic := 'U';
          DINA4   : in    std_logic := 'U';
          DINA3   : in    std_logic := 'U';
          DINA2   : in    std_logic := 'U';
          DINA1   : in    std_logic := 'U';
          DINA0   : in    std_logic := 'U';
          DINB8   : in    std_logic := 'U';
          DINB7   : in    std_logic := 'U';
          DINB6   : in    std_logic := 'U';
          DINB5   : in    std_logic := 'U';
          DINB4   : in    std_logic := 'U';
          DINB3   : in    std_logic := 'U';
          DINB2   : in    std_logic := 'U';
          DINB1   : in    std_logic := 'U';
          DINB0   : in    std_logic := 'U';
          WIDTHA0 : in    std_logic := 'U';
          WIDTHA1 : in    std_logic := 'U';
          WIDTHB0 : in    std_logic := 'U';
          WIDTHB1 : in    std_logic := 'U';
          PIPEA   : in    std_logic := 'U';
          PIPEB   : in    std_logic := 'U';
          WMODEA  : in    std_logic := 'U';
          WMODEB  : in    std_logic := 'U';
          BLKA    : in    std_logic := 'U';
          BLKB    : in    std_logic := 'U';
          WENA    : in    std_logic := 'U';
          WENB    : in    std_logic := 'U';
          CLKA    : in    std_logic := 'U';
          CLKB    : in    std_logic := 'U';
          RESET   : in    std_logic := 'U';
          DOUTA8  : out   std_logic;
          DOUTA7  : out   std_logic;
          DOUTA6  : out   std_logic;
          DOUTA5  : out   std_logic;
          DOUTA4  : out   std_logic;
          DOUTA3  : out   std_logic;
          DOUTA2  : out   std_logic;
          DOUTA1  : out   std_logic;
          DOUTA0  : out   std_logic;
          DOUTB8  : out   std_logic;
          DOUTB7  : out   std_logic;
          DOUTB6  : out   std_logic;
          DOUTB5  : out   std_logic;
          DOUTB4  : out   std_logic;
          DOUTB3  : out   std_logic;
          DOUTB2  : out   std_logic;
          DOUTB1  : out   std_logic;
          DOUTB0  : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1, WEAP, ram256x8_R0C0_DOUTA0, 
        ram256x8_R0C0_DOUTA1, ram256x8_R0C0_DOUTA2, 
        ram256x8_R0C0_DOUTA3, ram256x8_R0C0_DOUTA4, 
        ram256x8_R0C0_DOUTA5, ram256x8_R0C0_DOUTA6, 
        ram256x8_R0C0_DOUTA7, ram256x8_R0C0_DOUTA8, 
        ram256x8_R0C0_DOUTB8, WEBP, GND_net_2, VCC_net_2
         : std_logic;

begin 

    GND_net_1 <= \GND\;
    VCC_net_1 <= \VCC\;

    VCC_i_0 : VCC
      port map(Y => VCC_net_2);
    
    GND_i_0 : GND
      port map(Y => GND_net_2);
    
    WEBUBBLEB : INV
      port map(A => VCC_net_1, Y => WEBP);
    
    ram256x8_R0C0 : RAM4K9
      port map(ADDRA11 => GND_net_1, ADDRA10 => GND_net_1, ADDRA9
         => GND_net_1, ADDRA8 => GND_net_1, ADDRA7 => waddr(7), 
        ADDRA6 => waddr(6), ADDRA5 => waddr(5), ADDRA4 => 
        waddr(4), ADDRA3 => waddr(3), ADDRA2 => waddr(2), ADDRA1
         => waddr(1), ADDRA0 => waddr(0), ADDRB11 => GND_net_1, 
        ADDRB10 => GND_net_1, ADDRB9 => GND_net_1, ADDRB8 => 
        GND_net_1, ADDRB7 => wptr(7), ADDRB6 => wptr(6), ADDRB5
         => wptr(5), ADDRB4 => wptr(4), ADDRB3 => wptr(3), ADDRB2
         => wptr(2), ADDRB1 => wptr(1), ADDRB0 => wptr(0), DINA8
         => GND_net_1, DINA7 => wdata(6), DINA6 => wdata(5), 
        DINA5 => wdata(4), DINA4 => wdata(3), DINA3 => wdata(2), 
        DINA2 => wdata(1), DINA1 => wdata(0), DINA0 => DI_c, 
        DINB8 => GND_net_1, DINB7 => GND_net_1, DINB6 => 
        GND_net_1, DINB5 => GND_net_1, DINB4 => GND_net_1, DINB3
         => GND_net_1, DINB2 => GND_net_1, DINB1 => GND_net_1, 
        DINB0 => GND_net_1, WIDTHA0 => VCC_net_1, WIDTHA1 => 
        VCC_net_1, WIDTHB0 => VCC_net_1, WIDTHB1 => VCC_net_1, 
        PIPEA => GND_net_1, PIPEB => GND_net_1, WMODEA => 
        GND_net_1, WMODEB => GND_net_1, BLKA => WEAP, BLKB => 
        WEBP, WENA => N_1923_i, WENB => VCC_net_1, CLKA => CLK_c, 
        CLKB => clk60M, RESET => RST_c_i, DOUTA8 => 
        ram256x8_R0C0_DOUTA8, DOUTA7 => ram256x8_R0C0_DOUTA7, 
        DOUTA6 => ram256x8_R0C0_DOUTA6, DOUTA5 => 
        ram256x8_R0C0_DOUTA5, DOUTA4 => ram256x8_R0C0_DOUTA4, 
        DOUTA3 => ram256x8_R0C0_DOUTA3, DOUTA2 => 
        ram256x8_R0C0_DOUTA2, DOUTA1 => ram256x8_R0C0_DOUTA1, 
        DOUTA0 => ram256x8_R0C0_DOUTA0, DOUTB8 => 
        ram256x8_R0C0_DOUTB8, DOUTB7 => nvm_din(7), DOUTB6 => 
        nvm_din(6), DOUTB5 => nvm_din(5), DOUTB4 => nvm_din(4), 
        DOUTB3 => nvm_din(3), DOUTB2 => nvm_din(2), DOUTB1 => 
        nvm_din(1), DOUTB0 => nvm_din(0));
    
    WEBUBBLEA : INV
      port map(A => VCC_net_1, Y => WEAP);
    
    VCC_i : VCC
      port map(Y => VCC_net_1);
    
    GND_i : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;

entity sconfig is

    port( nvm_din          : out   std_logic_vector(7 downto 0);
          nvm_addr         : out   std_logic_vector(18 downto 0);
          nvm_dout         : in    std_logic_vector(7 downto 0);
          nvm_addr_0       : out   std_logic_vector(18 to 18);
          rdata_7          : out   std_logic;
          \VCC\            : in    std_logic;
          \GND\            : in    std_logic;
          RST_c_i          : in    std_logic;
          CSn_c            : in    std_logic;
          CSn_c_1          : in    std_logic;
          nvm_pgm          : out   std_logic;
          un5_do_0_a2_2_a2 : out   std_logic;
          DI_c             : in    std_logic;
          DI_c_1           : in    std_logic;
          nvm_read         : out   std_logic;
          nvm_we           : out   std_logic;
          nvm_erase        : out   std_logic;
          DI_c_0           : in    std_logic;
          nvm_busy         : in    std_logic;
          CSn_c_0          : in    std_logic;
          CSn_c_0_0        : in    std_logic;
          CLK_c            : in    std_logic;
          RST_c            : in    std_logic;
          clk60M           : in    std_logic
        );

end sconfig;

architecture DEF_ARCH of sconfig is 

  component MX2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          S : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1C1
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component OR3B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MAJ3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AO13
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1E1C1
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component XOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AX1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AO1B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XA1A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component INV
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XA1B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MX2C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          S : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AO1A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR3C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1P1
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          PRE : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component XNOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AOI1B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OA1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN0C1
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component OR3A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AO1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AX1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component AOI1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OA1A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1E1P1
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          PRE : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component AO1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MIN3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MX2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          S : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OA1B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OA1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OAI1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AO1D
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ram256x8
    port( wdata    : in    std_logic_vector(6 downto 0) := (others => 'U');
          wptr     : in    std_logic_vector(7 downto 0) := (others => 'U');
          waddr    : in    std_logic_vector(7 downto 0) := (others => 'U');
          nvm_din  : out   std_logic_vector(7 downto 0);
          RST_c_i  : in    std_logic := 'U';
          DI_c     : in    std_logic := 'U';
          clk60M   : in    std_logic := 'U';
          CLK_c    : in    std_logic := 'U';
          N_1923_i : in    std_logic := 'U';
          \GND\    : in    std_logic := 'U';
          \VCC\    : in    std_logic := 'U'
        );
  end component;

  component XA1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XNOR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal VCC_net_1, GND_net_1, \nvm_pgm\, \nvm_read\, \nvm_we\, 
        \nvm_erase\, \state2_0[8]_net_1\, \state2_tr2_i_0\, 
        N_1783_0, \bit_cnt[0]_net_1\, \bit_cnt[2]_net_1\, 
        \bit_cnt[1]_net_1\, \bit_cnt_0[0]_net_1\, 
        \bit_cnt_i[0]_net_1\, \bit_cnt_0[1]_net_1\, SUM1, 
        \bit_cnt_0[2]_net_1\, SUM2, \state_0[7]_net_1\, 
        \statese_i_0\, \state_0[4]_net_1\, \state[5]_net_1\, 
        \state2_0[1]_net_1\, N_465_i_0, \state2_0[9]_net_1\, 
        \state2_ns_i_a2_0_a2_0_a2[0]_net_1\, N_1471_0, 
        \state2[0]_net_1\, N_1371_0, addr_ld_0_sqmuxa_0, N_1924, 
        N_1538_0, N_1534, \xaddr[18]_net_1\, \raddr[18]\, 
        N_1669_0, \state[3]_net_1\, N_1922, 
        \DWACT_ADD_CI_0_g_array_2[0]\, 
        \DWACT_ADD_CI_0_g_array_1[0]\, 
        \DWACT_ADD_CI_0_pog_array_1[0]\, 
        \DWACT_ADD_CI_0_g_array_3[0]\, 
        \DWACT_ADD_CI_0_pog_array_2[0]\, 
        \DWACT_ADD_CI_0_g_array_1_0[0]\, \DWACT_ADD_CI_0_TMP[0]\, 
        \start[1]_net_1\, \DWACT_ADD_CI_0_g_array_2_0[0]\, 
        \DWACT_ADD_CI_0_pog_array_1_0[0]\, 
        \DWACT_ADD_CI_0_g_array_11[0]\, 
        \DWACT_ADD_CI_0_pog_array_1_1[0]\, 
        \DWACT_ADD_CI_0_g_array_12_1[0]\, \start[4]_net_1\, 
        \DWACT_ADD_CI_0_g_array_12[0]\, \start[2]_net_1\, 
        \DWACT_ADD_CI_0_g_array_12_2[0]\, \start[6]_net_1\, 
        \DWACT_ADD_CI_0_g_array_11_0[0]\, 
        \DWACT_ADD_CI_0_pog_array_1_1_0[0]\, 
        \DWACT_ADD_CI_0_TMP_0[0]\, \waddr[1]_net_1\, 
        \DWACT_ADD_CI_0_g_array_12_1_0[0]\, \waddr[4]_net_1\, 
        \DWACT_ADD_CI_0_g_array_12_0[0]\, \waddr[2]_net_1\, 
        \DWACT_ADD_CI_0_g_array_12_2_0[0]\, \waddr[6]_net_1\, 
        \DWACT_ADD_CI_0_g_array_1_1[0]\, 
        \DWACT_ADD_CI_0_TMP_1[0]\, \wptr[1]_net_1\, 
        \DWACT_ADD_CI_0_g_array_2_1[0]\, 
        \DWACT_ADD_CI_0_pog_array_1_2[0]\, 
        \DWACT_ADD_CI_0_g_array_11_1[0]\, 
        \DWACT_ADD_CI_0_pog_array_1_1_1[0]\, 
        \DWACT_ADD_CI_0_g_array_12_1_1[0]\, \wptr[4]_net_1\, 
        \DWACT_ADD_CI_0_g_array_12_3[0]\, \wptr[2]_net_1\, 
        \DWACT_ADD_CI_0_g_array_12_2_1[0]\, \wptr[6]_net_1\, 
        \bit_cnt_i[2]_net_1\, \N_1923_i\, \un2_buf_we_0_a2_0_a2\, 
        \bit_cnt_i[1]_net_1\, \rdata_4_2_0_0[2]\, \stat[2]_net_1\, 
        N_1803, N_1708, \rdata_4_2_0_0[3]\, \stat[3]_net_1\, 
        N_1711, \rdata_4_i_0_0[4]\, \stat[4]_net_1\, N_1756, 
        \rdata_4_i_0_0[1]\, \webit\, N_1745, 
        \state2_ns_i_a2_i_0_0[9]_net_1\, 
        \state2_ns_i_a2_i_0_a2_0[9]_net_1\, N_1739, 
        \state_ns_i_a2_0_0_2[7]_net_1\, N_1697_1, 
        \state_ns_i_a2_0_0_a2_0[7]\, 
        \state_ns_i_a2_0_0_1[7]_net_1\, N_1699, N_1700, N_1701_i, 
        \state2_tr12_i_0_0\, \state2[6]_net_1\, N_1730, 
        \rdata_4_2_0_a2_0[0]\, \wip\, \cmnd[2]_net_1\, 
        \state2_ns_i_a2_0_0_1[8]_net_1\, N_1705, N_1704, N_1703, 
        N_1799, N_1781, \state_ns_i_a2_i_a2_0[5]\, 
        \cmnd[0]_net_1\, N_1778, \state2[5]_net_1\, N_1801, 
        \state_tr8_0_a2_0_a2_1\, N_1528, 
        \state_ns_i_a2_0_0_a2_3_1[7]_net_1\, \cmnd[5]_net_1\, 
        N_1796, \state_tr0_3_a2_1_0\, \cmnd[6]_net_1\, 
        \state_ns_i_a2_0_0_a2_1_1[7]_net_1\, N_1699_1, 
        \state_ns_i_a2_0_0_a2_1_0[7]_net_1\, 
        \state_ns_i_a2_i_0_a2_0_0[4]_net_1\, un33_state_0_0_a2_0, 
        un89_state_i_i_a2_0, \state_tr0_3_a2_3_1\, 
        \cmnd[4]_net_1\, \cmnd[3]_net_1\, 
        \state2_ns_i_a2_i_0_a2_7_6[9]_net_1\, un3_finished_4_i_0, 
        un3_finished_5_i_0, \state2_ns_i_a2_i_0_a2_7_1[9]_net_1\, 
        \state2_ns_i_a2_i_0_a2_7_5[9]_net_1\, un3_finished_0_i_0, 
        un3_finished_1_i_0, \state2_ns_i_a2_i_0_a2_7_3[9]_net_1\, 
        \waddr[3]_net_1\, \wptr[3]_net_1\, un3_finished_2_i_0, 
        \state2_ns_i_a2_i_0_a2_7_0[9]_net_1\, \waddr[7]_net_1\, 
        \wptr[7]_net_1\, \waddr[8]_net_1\, 
        \state2_ns_i_a2_0_0_a2_2_6[8]_net_1\, \xaddr[15]_net_1\, 
        \xaddr[7]_net_1\, \state2_ns_i_a2_0_0_a2_2_4[8]_net_1\, 
        \state2_ns_i_a2_0_0_a2_2_5[8]_net_1\, \xaddr[12]_net_1\, 
        \xaddr[14]_net_1\, \state2_ns_i_a2_0_0_a2_2_3[8]_net_1\, 
        \xaddr[8]_net_1\, \xaddr[10]_net_1\, \xaddr[9]_net_1\, 
        \xaddr[13]_net_1\, \xaddr[11]_net_1\, 
        \state_ns_i_a2_0_0_a2_4_0[7]_net_1\, \cmnd[7]_net_1\, 
        \cmnd[1]_net_1\, \state2_tr12_i_0_a2_0_16\, 
        \state2_tr12_i_0_a2_0_10\, \state2_tr12_i_0_a2_0_11\, 
        \state2_tr12_i_0_a2_0_12\, \state2_tr12_i_0_a2_0_15\, 
        \state2_tr12_i_0_a2_0_9\, \state2_tr12_i_0_a2_0_13\, 
        \state2_tr12_i_0_a2_0_6\, \state2_tr12_i_0_a2_0_5\, 
        \state2_tr12_i_0_a2_0_7\, \xaddr[2]_net_1\, 
        \xaddr[4]_net_1\, \state2_tr12_i_0_a2_0_0\, 
        \state2_tr12_i_0_a2_0_2\, \xaddr[5]_net_1\, 
        \xaddr[1]_net_1\, \xaddr[3]_net_1\, \xaddr[0]_net_1\, 
        \xaddr[6]_net_1\, \xaddr[17]_net_1\, \xaddr[16]_net_1\, 
        \state_tr0_3_a2_2_1\, \state_tr0_3_a2_2_0\, 
        \state2_tr12_i_0_o2_0_3\, \state2_tr12_i_0_o2_0_2\, 
        \state2_tr12_i_0_o2_0_1\, 
        \state2_ns_i_a2_0_0_a2_5_1[8]_net_1\, 
        \state2_ns_i_a2_0_0_a2_5_0[8]_net_1\, \sbulk\, 
        ADD_19x19_slow_I15_CO1_5, \raddr[11]\, 
        ADD_19x19_slow_I15_CO1_3, \raddr[10]\, \raddr[13]\, 
        ADD_19x19_slow_I15_CO1_1, \raddr[12]\, \raddr[15]\, 
        I8_un1_CO1, \raddr[14]\, \addr_ld_0_sqmuxa_0_a2_0_1\, 
        N_1798, N_1771, \un10_i_a2_0_a2_0_a2_0[2]_net_1\, 
        \state[6]_net_1\, ssector_1_0_0_a2_1, N_1589, 
        \dly_sector\, sbulk_1_0_0_a2_0_1, \dly_bulk\, N_1742_1, 
        \un5_esector_i_0_0\, N_1526_i_0, N_1731, 
        swrite_1_0_0_a2_1, N_1551, dly_write_i, N_897_3, 
        \un6_ewrite_i_0_1\, N_1733, N_1734, \un6_ewrite_i_0_3_0\, 
        \last[5]_net_1\, \last[3]_net_1\, \un5_esector_i_0_o2_0\, 
        N_1530, \un1_end_adr[17]\, \un1_end_adr[18]\, N_1587, 
        N_1529, N_1782, N_1586, N_1802, \last_i_0[2]\, 
        \last_i_0[1]\, N_897_i_0, N_897_2, N_1662, N_1693, 
        N_1789_i, \rdata_4[3]\, N_1784, \raddr[17]\, N_893_i_0, 
        N_1729, N_1765, N_1588_i_0, N_1804, \state2_tr12_i_0\, 
        N_1572, \state2_ns_i_a2_i_0[3]_net_1\, N_1735, \swrite\, 
        N_1755, N_1774, N_1525, N_1175, N_1754, \un2_xaddr[7]\, 
        N_1552, I6_un1_CO1, N_1706, N_1773, N_1523, 
        \state2_ns[7]\, \state2[7]_net_1\, 
        \un10_i_a2_0_a2_1_a2[0]_net_1\, \state[2]_net_1\, N_1768, 
        N_1777, N_1769_i, N_1770, \rdata_4[0]\, N_1707, N_1522, 
        \rdata_4[2]\, \rdata_4_i_0[1]\, \rdata_4_i_0[4]\, N_1690, 
        wena_dly_i, \iwebit_1_0_a2_0_0\, N_1767, N_1740, 
        \un5_ebulk_0_a2_0_a2\, \state_ns[6]\, 
        \un10_i_a2_0_a2_0_a2[2]_net_1\, \state[0]_net_1\, 
        N_1769_1, N_1770_1, N_430_i_0, N_1698_1, 
        \state2_ns_i_a2_i_0[9]_net_1\, N_1738, 
        \state2_ns_i_a2_0_0_o2_0[8]_net_1\, N_1927_tz, N_1557, 
        \xaddr_4_i_0[18]\, \xaddr_4_i_0[17]\, \xaddr_4_i_0[16]\, 
        \raddr[16]\, N220_1, N211, \raddr[1]\, I0_un1_CO1, 
        I2_un1_CO1, \raddr[2]\, N215, \raddr[3]\, I4_un1_CO1, 
        \raddr[4]\, N219, \raddr[5]\, \waddr[5]_net_1\, 
        I6_un1_CO1_0, \raddr[6]\, N223, \raddr[7]\, \raddr[8]\, 
        \xaddr_4[0]\, N_1617, \xaddr_4[1]\, N_1618, \xaddr_4[2]\, 
        N_1619, \xaddr_4[3]\, N_1620, \xaddr_4[4]\, N_1621, 
        \xaddr_4[5]\, N_1622, \xaddr_4[6]\, N_1623, \xaddr_4[7]\, 
        N_1624, \xaddr_4[8]\, N_1538, N_1625, \xaddr_4[9]\, 
        N_1626, \xaddr_4[11]\, N_1628, addr_ld_0_sqmuxa, 
        \xaddr_4[12]\, N_1629, \xaddr_4[13]\, N_1630, 
        \xaddr_4[14]\, N_1631, \xaddr_4[15]\, N_1632, 
        \xaddr_4[16]\, N_1720, \xaddr_4[17]\, N_1723, 
        \xaddr_4[18]\, N_1726, I0_un1_CO1_0, I2_un1_CO1_0, 
        I4_un1_CO1_0, N226, N234, N242, N250, I16_un1_CO1, N258, 
        \un2_xaddr[15]\, \un2_xaddr[14]\, \un2_xaddr[13]\, 
        \un2_xaddr[12]\, \un2_xaddr[11]\, \un2_xaddr[9]\, 
        \un2_xaddr[6]\, \un2_xaddr[5]\, \un2_xaddr[4]\, 
        \un2_xaddr[3]\, \un2_xaddr[2]\, \un2_xaddr[1]\, 
        \un2_xaddr[0]\, \waddr[0]_net_1\, \raddr[0]\, 
        \wptr[5]_net_1\, \wptr[0]_net_1\, N_1669, N_1687, N_1692, 
        \ssector\, \rdata[1]_net_1\, N_1714, \rdata[4]_net_1\, 
        N_1716, \rdata[5]_net_1\, N_1718, \rdata[6]_net_1\, 
        N_1926, wip_1, N_1582, \rdata[0]_net_1\, 
        \un10_i_a2_0_a2_1_a2[1]_net_1\, \rdata[3]_net_1\, 
        un146_state, un54_state, N_1775, \state[1]_net_1\, N_1546, 
        N_1805, un19_state, un26_state, N_1806, un33_state, 
        N_1753_1, un47_state, N_1680_1, \state[4]_net_1\, 
        un61_state, un68_state, un75_state, un117_state, 
        un124_state, un131_state, sbulk_1, iwebit_1, N_1592, 
        ssector_1, N_1371, N_1374, \rdata_4[5]\, \rdata_4[6]\, 
        \rdata_4[7]\, un21_rstn_i_a2_i, N_1486, \un2_idis_0_o2\, 
        \wdis_dly\, N_1598, N_1599, \wptr_4_i_m2[0]\, 
        \DWACT_ADD_CI_0_partial_sum[0]\, \start[0]_net_1\, 
        \wptr_4_i_m2[1]\, I_31_0, \wptr_4_i_m2[2]\, I_32, 
        \wptr_4_i_m2[3]\, I_30, \start[3]_net_1\, 
        \state2[8]_net_1\, \wptr_4_i_m2[4]\, I_28, 
        \wptr_4_i_m2[5]\, I_33, \start[5]_net_1\, 
        \wptr_4_i_m2[6]\, I_27, \wptr_4_i_m2[7]\, I_34, 
        \start[7]_net_1\, N_1608, I_5, N_1609, I_13, N_1610, I_24, 
        N_1611, I_38, N_1612, I_52, N_1615, I_91, N_1616, I_105, 
        \state2[1]_net_1\, \raddr[9]\, \state2[9]_net_1\, N_1652, 
        I_31, N_1654, I_9, N_1655, I_20, N_1656, I_45, N_1657, 
        I_56, N_1658, I_73, N_1660, I_98, \state2_tr11_i_0\, 
        \state2_ns_i_a2_i[2]_net_1\, N_1785, N_1776, un96_state, 
        un40_state, \state_ns[1]\, raddr_0_21, N_1932_i, 
        un12_state_0_0_a2_0, N_1661, I_115, \un2_xaddr[8]\, 
        N_1614, I_77, N_1613, I_66, N_1488, un138_state, 
        un103_state, N_1783, N_1659, I_84, 
        \state2_ns_i_a2_i_0[4]_net_1\, un110_state, I16_un1_CO1_0, 
        \last[4]_net_1\, \last[0]_net_1\, N_1627, \un2_xaddr[10]\, 
        \un1_end_adr[16]\, swrite_1, \rdata[2]_net_1\, 
        \xaddr_4[10]\, \state[7]_net_1\, \wdata[0]_net_1\, 
        \wdata[1]_net_1\, \wdata[2]_net_1\, \wdata[3]_net_1\, 
        \wdata[4]_net_1\, \wdata[5]_net_1\, \wdata[6]_net_1\, 
        \stat[0]_net_1\, \stat[1]_net_1\, 
        \DWACT_ADD_CI_0_partial_sum_0[0]\, \start_3[1]\, 
        \start_3[2]\, \start_3[3]\, \start_3[4]\, \start_3[5]\, 
        \start_3[6]\, \start_3[7]\, 
        \DWACT_ADD_CI_0_partial_sum_1[0]\, \waddr_3[1]\, 
        \waddr_3[2]\, \waddr_3[3]\, \waddr_3[4]\, \waddr_3[5]\, 
        \waddr_3[6]\, \waddr_3[7]\, \waddr_3[8]\, N_80, N_72, 
        \DWACT_FINC_E[0]\, N_49, \DWACT_FINC_E[4]\, N_34, 
        \DWACT_FINC_E[7]\, \DWACT_FINC_E[6]\, N_4, 
        \DWACT_FINC_E[28]\, \DWACT_FINC_E[10]\, 
        \DWACT_FINC_E[12]\, \DWACT_FINC_E[2]\, \DWACT_FINC_E[5]\, 
        N_11, \DWACT_FINC_E[11]\, N_16, \DWACT_FINC_E[9]\, N_21, 
        N_26, \DWACT_FINC_E[8]\, N_31, N_39, N_46, 
        \DWACT_FINC_E[3]\, N_54, N_59, N_64, \DWACT_FINC_E[1]\, 
        N_69, N_77, \DWACT_ADD_CI_0_pog_array_1_2_0[0]\, 
        GND_net_2, VCC_net_2 : std_logic;

    for all : ram256x8
	Use entity work.ram256x8(DEF_ARCH);
begin 

    VCC_net_1 <= \VCC\;
    GND_net_1 <= \GND\;
    nvm_pgm <= \nvm_pgm\;
    nvm_read <= \nvm_read\;
    nvm_we <= \nvm_we\;
    nvm_erase <= \nvm_erase\;

    \addr_i_m2_i_m2[4]\ : MX2
      port map(A => \xaddr[4]_net_1\, B => \raddr[4]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(4));
    
    \P5_rdata_4_2_0_a2_2[2]\ : OR2A
      port map(A => \nvm_read\, B => N_1522, Y => N_1784);
    
    \bit_cnt_0[1]\ : DFN1C1
      port map(D => SUM1, CLK => CLK_c, CLR => CSn_c_0_0, Q => 
        \bit_cnt_0[1]_net_1\);
    
    un5_esector_i_0_o2_0 : OR3B
      port map(A => CSn_c_0, B => \webit\, C => \stat[4]_net_1\, 
        Y => N_1662);
    
    \P12_xaddr_4_i_a2_2[16]\ : OR2B
      port map(A => \state2_0[1]_net_1\, B => N_1538, Y => N_1926);
    
    un5_esector_i_0 : NOR3A
      port map(A => \un5_esector_i_0_0\, B => N_1534, C => N_1662, 
        Y => N_893_i_0);
    
    un1_end_adr_ADD_19x19_slow_I2_un1_CO1 : MAJ3
      port map(A => \raddr[2]\, B => N211, C => \waddr[2]_net_1\, 
        Y => I2_un1_CO1);
    
    \state2[3]\ : DFN1C1
      port map(D => \state2_tr12_i_0\, CLK => clk60M, CLR => 
        RST_c, Q => \nvm_pgm\);
    
    P9_swrite_1_0_0_a2_1 : OR2
      port map(A => \un1_end_adr[17]\, B => N_1526_i_0, Y => 
        N_1782);
    
    \state_ns_i_a2_0_0_a2_7[7]\ : OR2A
      port map(A => N_1781, B => \state_0[4]_net_1\, Y => N_1796);
    
    un1_end_adr_ADD_19x19_slow_I8_un1_CO1 : AO13
      port map(A => \raddr[8]\, B => \waddr[8]_net_1\, C => N223, 
        Y => I8_un1_CO1);
    
    \cmnd[5]\ : DFN1E1C1
      port map(D => \cmnd[4]_net_1\, CLK => CLK_c, CLR => RST_c, 
        E => \state[7]_net_1\, Q => \cmnd[5]_net_1\);
    
    \xaddr[4]\ : DFN1E1C1
      port map(D => \xaddr_4[4]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[4]_net_1\);
    
    \state_ns_i_a2_i_0_a2_0_0[4]\ : OR2A
      port map(A => \state_0[7]_net_1\, B => N_1799, Y => 
        \state_ns_i_a2_i_0_a2_0_0[4]_net_1\);
    
    \cmnd[2]\ : DFN1E1C1
      port map(D => \cmnd[1]_net_1\, CLK => CLK_c, CLR => RST_c, 
        E => \state[7]_net_1\, Q => \cmnd[2]_net_1\);
    
    \wdata[3]\ : DFN1E1C1
      port map(D => \wdata[2]_net_1\, CLK => CLK_c, CLR => 
        N_1471_0, E => \state[2]_net_1\, Q => \wdata[3]_net_1\);
    
    un1_wptr_I_33 : XOR2
      port map(A => \wptr[5]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12_1_1[0]\, Y => I_33);
    
    addr_ld_0_sqmuxa_0_a2_0_0 : NOR2B
      port map(A => \state2_0[8]_net_1\, B => N_1924, Y => 
        addr_ld_0_sqmuxa_0);
    
    state2_tr12_i_0_0 : OR2A
      port map(A => \state2[6]_net_1\, B => N_1730, Y => 
        \state2_tr12_i_0_0\);
    
    \xaddr[0]\ : DFN1E1C1
      port map(D => \xaddr_4[0]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[0]_net_1\);
    
    state2_tr12_i_0_a2 : NOR3
      port map(A => N_1765, B => N_1588_i_0, C => N_1804, Y => 
        N_1729);
    
    \P5_rdata_4_1_0_a2[6]\ : OR2B
      port map(A => \rdata[5]_net_1\, B => N_1522, Y => N_1716);
    
    \state_ns_i_a2_i_0_a2_0[4]\ : NOR3A
      port map(A => N_1774, B => N_1525, C => 
        \state_ns_i_a2_i_0_a2_0_0[4]_net_1\, Y => N_1755);
    
    P6_start_3_I_45 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => 
        \start[6]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_2[0]\);
    
    \P5_rdata_4_2_0_a2[3]\ : OR2B
      port map(A => \rdata[2]_net_1\, B => N_1522, Y => N_1711);
    
    dly_sector : DFN1C1
      port map(D => N_893_i_0, CLK => clk60M, CLR => RST_c, Q => 
        \dly_sector\);
    
    \bit_cnt[2]\ : DFN1C1
      port map(D => SUM2, CLK => CLK_c, CLR => CSn_c, Q => 
        \bit_cnt[2]_net_1\);
    
    un1_end_adr_ADD_19x19_slow_I18_Y : AX1C
      port map(A => \raddr[17]\, B => I16_un1_CO1_0, C => 
        \raddr[18]\, Y => \un1_end_adr[18]\);
    
    state_tr0_3_a2_2 : OR3B
      port map(A => \state_tr0_3_a2_2_1\, B => 
        \state_tr0_3_a2_2_0\, C => N_1769_1, Y => N_1769_i);
    
    \wdata[0]\ : DFN1E1C1
      port map(D => DI_c, CLK => CLK_c, CLR => N_1471_0, E => 
        \state[2]_net_1\, Q => \wdata[0]_net_1\);
    
    \state2_ns_i_a2_i_0_o2_1_tz[9]\ : AO1B
      port map(A => \state2_ns_i_a2_i_0_a2_7_5[9]_net_1\, B => 
        \state2_ns_i_a2_i_0_a2_7_6[9]_net_1\, C => N_1801, Y => 
        N_1927_tz);
    
    statese_i_0 : NOR2A
      port map(A => \state_0[7]_net_1\, B => N_1783_0, Y => 
        \statese_i_0\);
    
    swrite : DFN1C1
      port map(D => swrite_1, CLK => clk60M, CLR => RST_c, Q => 
        \swrite\);
    
    un1_wptr_I_32 : XOR2
      port map(A => \wptr[2]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_1_1[0]\, Y => I_32);
    
    \state2_ns_i_a2_i_0_a2_7_3[9]\ : XA1A
      port map(A => \waddr[3]_net_1\, B => \wptr[3]_net_1\, C => 
        un3_finished_2_i_0, Y => 
        \state2_ns_i_a2_i_0_a2_7_3[9]_net_1\);
    
    un2_iena_0_o2_0 : NOR2A
      port map(A => \cmnd[2]_net_1\, B => N_1522, Y => N_1546);
    
    \state_ns_i_a2_0_0_a2_3_1[7]\ : OR3
      port map(A => N_1799, B => \cmnd[5]_net_1\, C => N_1796, Y
         => \state_ns_i_a2_0_0_a2_3_1[7]_net_1\);
    
    N_1923_i : INV
      port map(A => \un2_buf_we_0_a2_0_a2\, Y => \N_1923_i\);
    
    \G1_4_P4_raddr[4]\ : DFN1E1C1
      port map(D => N_1655, CLK => CLK_c, CLR => RST_c, E => 
        un40_state, Q => \raddr[4]\);
    
    \P12_xaddr_4_r[3]\ : NOR3A
      port map(A => N_1538_0, B => N_1620, C => 
        addr_ld_0_sqmuxa_0, Y => \xaddr_4[3]\);
    
    \state_ns_i_a2_0_0_a2_4[7]\ : OR3
      port map(A => N_1769_1, B => 
        \state_ns_i_a2_0_0_a2_4_0[7]_net_1\, C => N_1530, Y => 
        N_1767);
    
    \state[6]\ : DFN1E1C1
      port map(D => \state_ns[1]\, CLK => CLK_c, CLR => CSn_c_0, 
        E => N_1783_0, Q => \state[6]_net_1\);
    
    \cmnd[6]\ : DFN1E1C1
      port map(D => \cmnd[5]_net_1\, CLK => CLK_c, CLR => RST_c, 
        E => \state[7]_net_1\, Q => \cmnd[6]_net_1\);
    
    state2_tr12_i_0_a2_0_7 : NOR2
      port map(A => \xaddr[9]_net_1\, B => \xaddr[6]_net_1\, Y
         => \state2_tr12_i_0_a2_0_7\);
    
    \last[5]\ : DFN1C1
      port map(D => \un10_i_a2_0_a2_1_a2[0]_net_1\, CLK => CSn_c, 
        CLR => RST_c, Q => \last[5]_net_1\);
    
    \P12_xaddr_4_i_a2[16]\ : XA1B
      port map(A => N250, B => \xaddr[16]_net_1\, C => N_1926, Y
         => N_1720);
    
    G1_10_P4_un82_state_i_i : AO1B
      port map(A => N_1806, B => \state[5]_net_1\, C => N_1669, Y
         => N_1486);
    
    un1_inc_I_114 : AND3
      port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, 
        C => \DWACT_FINC_E[12]\, Y => N_4);
    
    P6_waddr_3_I_44 : NOR2B
      port map(A => \DWACT_ADD_CI_0_TMP_0[0]\, B => 
        \waddr[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1[0]\);
    
    G1_12_P4_un96_state_0_0_m2 : MX2C
      port map(A => \state[3]_net_1\, B => \state[5]_net_1\, S
         => \bit_cnt_0[1]_net_1\, Y => N_1598);
    
    \state2_ns_i_a2_i[2]\ : AO1A
      port map(A => nvm_busy, B => \state2[7]_net_1\, C => 
        N_1371_0, Y => \state2_ns_i_a2_i[2]_net_1\);
    
    \P12_xaddr_4_r[15]\ : NOR3A
      port map(A => N_1538, B => N_1632, C => addr_ld_0_sqmuxa, Y
         => \xaddr_4[15]\);
    
    un6_ewrite_i_0_a2 : OR3C
      port map(A => \un1_end_adr[17]\, B => \un1_end_adr[18]\, C
         => N_1587, Y => N_1733);
    
    P6_start_3_I_48 : AND2
      port map(A => \start[4]_net_1\, B => \start[5]_net_1\, Y
         => \DWACT_ADD_CI_0_pog_array_1_1[0]\);
    
    wdis_dly : DFN1C1
      port map(D => \un2_idis_0_o2\, CLK => clk60M, CLR => RST_c, 
        Q => \wdis_dly\);
    
    \state2_ns_i_a2_0_0[8]\ : NOR3C
      port map(A => \state2_ns_i_a2_0_0_1[8]_net_1\, B => N_1801, 
        C => nvm_busy, Y => N_465_i_0);
    
    \P12_xaddr_4_i_m2[7]\ : MX2C
      port map(A => \raddr[7]\, B => \un2_xaddr[7]\, S => 
        \state2[1]_net_1\, Y => N_1624);
    
    un1_inc_I_90 : AND3
      port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C
         => \DWACT_FINC_E[9]\, Y => N_21);
    
    \P12_wptr_4_i_m2[5]\ : MX2
      port map(A => I_33, B => \start[5]_net_1\, S => 
        \state2[8]_net_1\, Y => \wptr_4_i_m2[5]\);
    
    un6_ewrite_i_0_2 : NOR2
      port map(A => \last[4]_net_1\, B => \last[0]_net_1\, Y => 
        N_897_2);
    
    \xaddr[1]\ : DFN1E1C1
      port map(D => \xaddr_4[1]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[1]_net_1\);
    
    \state_ns_i_a2_0_0_a2_5[7]\ : OR3
      port map(A => N_1523, B => \cmnd[7]_net_1\, C => N_1798, Y
         => N_1768);
    
    un1_wptr_I_45 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_11_1[0]\, B => 
        \wptr[6]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_2_1[0]\);
    
    un1_inc_I_83 : AND3
      port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C
         => \DWACT_FINC_E[8]\, Y => N_26);
    
    un1_end_adr_ADD_19x19_slow_I5_CO1 : MAJ3
      port map(A => \raddr[5]\, B => I4_un1_CO1, C => 
        \waddr[5]_net_1\, Y => N219);
    
    \P12_xaddr_4_r[14]\ : NOR3A
      port map(A => N_1538, B => N_1631, C => addr_ld_0_sqmuxa, Y
         => \xaddr_4[14]\);
    
    \last[2]\ : DFN1P1
      port map(D => \bit_cnt_i[2]_net_1\, CLK => CSn_c, PRE => 
        RST_c, Q => \last_i_0[2]\);
    
    state2_tr12_i_0_o2_0_1 : NOR2B
      port map(A => \xaddr[1]_net_1\, B => \xaddr[6]_net_1\, Y
         => \state2_tr12_i_0_o2_0_1\);
    
    \bit_cnt_0[2]\ : DFN1C1
      port map(D => SUM2, CLK => CLK_c, CLR => CSn_c_0_0, Q => 
        \bit_cnt_0[2]_net_1\);
    
    un2_xaddr_ADD_19x19_slow_I2_un1_CO1 : OR3B
      port map(A => \xaddr[1]_net_1\, B => \xaddr[2]_net_1\, C
         => I0_un1_CO1_0, Y => I2_un1_CO1_0);
    
    \G1_8_P4_raddr_69_i_m2_i_m2[8]\ : MX2
      port map(A => I_45, B => DI_c_1, S => \bit_cnt_0[1]_net_1\, 
        Y => N_1656);
    
    iwebit_1_0_a2_1 : NOR2A
      port map(A => \webit\, B => \state2[0]_net_1\, Y => N_1775);
    
    \state[2]\ : DFN1E1C1
      port map(D => N_1374, CLK => CLK_c, CLR => CSn_c_0, E => 
        N_1783, Q => \state[2]_net_1\);
    
    P9_ssector_1_0_0_a2_1_0 : OR3
      port map(A => N_1589, B => \dly_sector\, C => N_1534, Y => 
        ssector_1_0_0_a2_1);
    
    P6_start_3_I_39 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_2_0[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_11[0]\);
    
    state2_tr12_i_0_a2_0_11 : NOR3A
      port map(A => \state2_tr12_i_0_a2_0_0\, B => 
        \xaddr[12]_net_1\, C => \xaddr[14]_net_1\, Y => 
        \state2_tr12_i_0_a2_0_11\);
    
    P9_swrite_1_0_0_o2 : OR3C
      port map(A => N_1782, B => \un1_end_adr[18]\, C => N_1587, 
        Y => N_1551);
    
    \bit_cnt_i[1]\ : INV
      port map(A => \bit_cnt_0[1]_net_1\, Y => 
        \bit_cnt_i[1]_net_1\);
    
    \state_0[4]\ : DFN1E1C1
      port map(D => \state[5]_net_1\, CLK => CLK_c, CLR => 
        CSn_c_0, E => N_1783_0, Q => \state_0[4]_net_1\);
    
    \state2_ns_i_a2_i_0_a2_7_1[9]\ : XA1A
      port map(A => \waddr[6]_net_1\, B => \wptr[6]_net_1\, C => 
        \state2_ns_i_a2_i_0_a2_7_0[9]_net_1\, Y => 
        \state2_ns_i_a2_i_0_a2_7_1[9]_net_1\);
    
    \P12_xaddr_4_r[18]\ : NOR3
      port map(A => N_1726, B => \xaddr_4_i_0[18]\, C => 
        addr_ld_0_sqmuxa, Y => \xaddr_4[18]\);
    
    statese_i_0_a2_0 : NOR3C
      port map(A => \bit_cnt[0]_net_1\, B => \bit_cnt[2]_net_1\, 
        C => \bit_cnt[1]_net_1\, Y => N_1783_0);
    
    iwebit_1_0_a2_0_0 : OR3
      port map(A => N_1771, B => \cmnd[0]_net_1\, C => N_1557, Y
         => \iwebit_1_0_a2_0_0\);
    
    \xaddr[11]\ : DFN1E1C1
      port map(D => \xaddr_4[11]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[11]_net_1\);
    
    \xaddr[13]\ : DFN1E1C1
      port map(D => \xaddr_4[13]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[13]_net_1\);
    
    \state_ns_i_a2_i_a2_1[5]\ : NOR2
      port map(A => \cmnd[2]_net_1\, B => N_1771, Y => N_1774);
    
    un2_xaddr_ADD_19x19_slow_I14_S : XNOR2
      port map(A => \xaddr[14]_net_1\, B => N242, Y => 
        \un2_xaddr[14]\);
    
    P6_waddr_3_I_21 : XOR2
      port map(A => \waddr[0]_net_1\, B => \un2_buf_we_0_a2_0_a2\, 
        Y => \DWACT_ADD_CI_0_partial_sum_1[0]\);
    
    \state2[7]\ : DFN1C1
      port map(D => \state2_ns_i_a2_i[2]_net_1\, CLK => clk60M, 
        CLR => RST_c, Q => \state2[7]_net_1\);
    
    state2_tr12_i_0_a2_1 : NOR2A
      port map(A => \state2[6]_net_1\, B => N_1801, Y => N_1765);
    
    un2_bit_cnt_1_SUM2 : AX1C
      port map(A => \bit_cnt[0]_net_1\, B => \bit_cnt[1]_net_1\, 
        C => \bit_cnt[2]_net_1\, Y => SUM2);
    
    \xaddr[15]\ : DFN1E1C1
      port map(D => \xaddr_4[15]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[15]_net_1\);
    
    \P12_xaddr_4_i_m2[5]\ : MX2C
      port map(A => \raddr[5]\, B => \un2_xaddr[5]\, S => 
        \state2_0[1]_net_1\, Y => N_1622);
    
    un8_nxt2_i_a2_i : OR2
      port map(A => \state2_0[8]_net_1\, B => \state2_0[1]_net_1\, 
        Y => N_1371);
    
    \state_ns_i_a2_0_0_a2_1_0_0[7]\ : NOR2A
      port map(A => N_1781, B => \state_0[7]_net_1\, Y => 
        \state_ns_i_a2_0_0_a2_1_0[7]_net_1\);
    
    P6_waddr_3_I_46 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_2[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_3[0]\);
    
    \P12_xaddr_4_i_m2[9]\ : MX2C
      port map(A => \raddr[9]\, B => \un2_xaddr[9]\, S => 
        \state2[1]_net_1\, Y => N_1626);
    
    G1_2_P4_un26_state_0_0 : AO1B
      port map(A => N_1806, B => \state_0[4]_net_1\, C => 
        N_1669_0, Y => un26_state);
    
    \waddr[8]\ : DFN1C1
      port map(D => \waddr_3[8]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \waddr[8]_net_1\);
    
    state_tr0_3_a2_3 : OR2
      port map(A => \state_tr0_3_a2_3_1\, B => N_1770_1, Y => 
        N_1770);
    
    un1_wptr_I_36 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_1_1[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_2[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_2_1[0]\);
    
    nxt3_0_a2_1_a2_1_a2 : NOR2B
      port map(A => N_1774, B => N_1773, Y => \nvm_read\);
    
    \addr_i_m2_i_m2[11]\ : MX2
      port map(A => \xaddr[11]_net_1\, B => \raddr[11]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(11));
    
    P6_un146_state_0_a2_0_a2 : NOR2B
      port map(A => \waddr[8]_net_1\, B => \un2_buf_we_0_a2_0_a2\, 
        Y => un146_state);
    
    \state_ns_i_a2_0_0_a2_8[7]\ : OR2A
      port map(A => DI_c_0, B => \cmnd[0]_net_1\, Y => N_1799);
    
    un1_inc_I_72 : NOR2B
      port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y
         => N_34);
    
    \bit_cnt_0[0]\ : DFN1C1
      port map(D => \bit_cnt_i[0]_net_1\, CLK => CLK_c, CLR => 
        CSn_c_0_0, Q => \bit_cnt_0[0]_net_1\);
    
    \state2_ns_i_a2_i_0[3]\ : OR3
      port map(A => \nvm_erase\, B => \nvm_we\, C => N_1735, Y
         => \state2_ns_i_a2_i_0[3]_net_1\);
    
    un2_xaddr_ADD_19x19_slow_I4_un1_CO1 : OR3B
      port map(A => \xaddr[3]_net_1\, B => \xaddr[4]_net_1\, C
         => I2_un1_CO1_0, Y => I4_un1_CO1_0);
    
    \P12_xaddr_4_r[0]\ : NOR3A
      port map(A => N_1538_0, B => N_1617, C => 
        addr_ld_0_sqmuxa_0, Y => \xaddr_4[0]\);
    
    \state_ns_i_a2_i_0_a2_1[4]\ : AOI1B
      port map(A => N_1767, B => N_1768, C => N_1699_1, Y => 
        N_1785);
    
    state2_tr12_i_0_a2_0_10 : NOR3A
      port map(A => \state2_tr12_i_0_a2_0_2\, B => 
        \xaddr[5]_net_1\, C => \xaddr[7]_net_1\, Y => 
        \state2_tr12_i_0_a2_0_10\);
    
    \state2_ns_i_a2_0_0_1[8]\ : NOR3C
      port map(A => N_1705, B => N_1704, C => N_1703, Y => 
        \state2_ns_i_a2_0_0_1[8]_net_1\);
    
    \state_ns_i_a2_i_a2_0_0[5]\ : NOR2A
      port map(A => \state_0[4]_net_1\, B => \cmnd[0]_net_1\, Y
         => \state_ns_i_a2_i_a2_0[5]\);
    
    P6_start_3_I_42 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_2_0[0]\, B => 
        \start[4]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_1[0]\);
    
    un1_inc_I_38 : XOR2
      port map(A => N_59, B => \raddr[7]\, Y => I_38);
    
    \wptr[7]\ : DFN1C1
      port map(D => \wptr_4_i_m2[7]\, CLK => clk60M, CLR => RST_c, 
        Q => \wptr[7]_net_1\);
    
    \waddr[0]\ : DFN1C1
      port map(D => \DWACT_ADD_CI_0_partial_sum_1[0]\, CLK => 
        CLK_c, CLR => un21_rstn_i_a2_i, Q => \waddr[0]_net_1\);
    
    \P12_wptr_4_i_m2[2]\ : MX2
      port map(A => I_32, B => \start[2]_net_1\, S => 
        \state2_0[8]_net_1\, Y => \wptr_4_i_m2[2]\);
    
    \start[5]\ : DFN1C1
      port map(D => \start_3[5]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \start[5]_net_1\);
    
    \waddr[2]\ : DFN1C1
      port map(D => \waddr_3[2]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \waddr[2]_net_1\);
    
    nxt3_0_a2_1_a2_1_a2_0 : NOR3A
      port map(A => \cmnd[0]_net_1\, B => N_1525, C => 
        \cmnd[7]_net_1\, Y => N_1773);
    
    \state2_ns_i_a2_i_0_a2_0_0[9]\ : OA1C
      port map(A => N_1778, B => \state2[5]_net_1\, C => N_1801, 
        Y => \state2_ns_i_a2_i_0_a2_0[9]_net_1\);
    
    \P12_xaddr_4_r[8]\ : NOR3A
      port map(A => N_1538, B => N_1625, C => addr_ld_0_sqmuxa_0, 
        Y => \xaddr_4[8]\);
    
    \un10_i_a2_0_a2_1_a2[1]\ : OR2
      port map(A => \state[5]_net_1\, B => N_1796, Y => 
        \un10_i_a2_0_a2_1_a2[1]_net_1\);
    
    P9_ssector_1_0_0_a2_1 : NOR2
      port map(A => N_1526_i_0, B => \raddr[17]\, Y => N_1802);
    
    un1_inc_I_97 : AND3
      port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C
         => \raddr[15]\, Y => N_16);
    
    un1_wptr_I_34 : XOR2
      port map(A => \wptr[7]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12_2_1[0]\, Y => I_34);
    
    \rdata[1]\ : DFN0C1
      port map(D => \rdata_4_i_0[1]\, CLK => CLK_c, CLR => 
        CSn_c_1, Q => \rdata[1]_net_1\);
    
    \G1_14_P4_raddr[14]\ : DFN1E1C1
      port map(D => N_1659, CLK => CLK_c, CLR => RST_c, E => 
        un110_state, Q => \raddr[14]\);
    
    G1_0_P4_un12_state_0_0_a2_1 : OR3A
      port map(A => \bit_cnt_0[0]_net_1\, B => 
        \bit_cnt_0[1]_net_1\, C => \bit_cnt_0[2]_net_1\, Y => 
        N_1922);
    
    P6_start_3_I_1 : AND2
      port map(A => \start[0]_net_1\, B => un146_state, Y => 
        \DWACT_ADD_CI_0_TMP[0]\);
    
    \last[1]\ : DFN1P1
      port map(D => \bit_cnt_i[1]_net_1\, CLK => CSn_c_0_0, PRE
         => RST_c, Q => \last_i_0[1]\);
    
    un1_inc_I_80 : AND2
      port map(A => \raddr[12]\, B => \raddr[13]\, Y => 
        \DWACT_FINC_E[8]\);
    
    un1_inc_I_23 : AND3
      port map(A => \DWACT_FINC_E[0]\, B => \raddr[3]\, C => 
        \raddr[4]\, Y => N_69);
    
    un1_wptr_I_27 : XOR2
      port map(A => \wptr[6]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_11_1[0]\, Y => I_27);
    
    \start[3]\ : DFN1C1
      port map(D => \start_3[3]\, CLK => CLK_c, CLR => N_1471_0, 
        Q => \start[3]_net_1\);
    
    un2_xaddr_ADD_19x19_slow_I6_un1_CO1 : OR3B
      port map(A => \xaddr[5]_net_1\, B => \xaddr[6]_net_1\, C
         => I4_un1_CO1_0, Y => I6_un1_CO1);
    
    \state2_ns_i_a2_0_0_a2[8]\ : OR3C
      port map(A => \state2_ns_i_a2_i_0_a2_7_5[9]_net_1\, B => 
        \state2_ns_i_a2_i_0_a2_7_6[9]_net_1\, C => \swrite\, Y
         => N_1703);
    
    \G1_5_P4_raddr[5]\ : DFN1E1C1
      port map(D => N_1610, CLK => CLK_c, CLR => RST_c, E => 
        un47_state, Q => \raddr[5]\);
    
    state_tr0_3_a2_1_0 : NOR2B
      port map(A => \cmnd[6]_net_1\, B => \cmnd[2]_net_1\, Y => 
        \state_tr0_3_a2_1_0\);
    
    G1_0_P4_raddr_0_21x : XOR2
      port map(A => N_1669, B => \raddr[0]\, Y => N_1932_i);
    
    \last[0]\ : DFN1C1
      port map(D => \bit_cnt[0]_net_1\, CLK => CSn_c_0_0, CLR => 
        RST_c, Q => \last[0]_net_1\);
    
    \addr_i_m2_i_m2[16]\ : MX2
      port map(A => \xaddr[16]_net_1\, B => \raddr[16]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(16));
    
    G1_13_P4_un103_state_0_0_a2_1 : NOR3A
      port map(A => \bit_cnt[1]_net_1\, B => \bit_cnt[0]_net_1\, 
        C => \bit_cnt_0[2]_net_1\, Y => N_1680_1);
    
    \xaddr[7]\ : DFN1E1C1
      port map(D => \xaddr_4[7]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[7]_net_1\);
    
    \state_ns_i_a2_i_0_o2_0[4]\ : OR3
      port map(A => \cmnd[3]_net_1\, B => \cmnd[4]_net_1\, C => 
        \cmnd[6]_net_1\, Y => N_1525);
    
    un1_inc_I_73 : XOR2
      port map(A => N_34, B => \raddr[12]\, Y => I_73);
    
    \P5_rdata_4_2_0[3]\ : AO1C
      port map(A => N_1784, B => nvm_dout(3), C => 
        \rdata_4_2_0_0[3]\, Y => \rdata_4[3]\);
    
    un2_xaddr_ADD_19x19_slow_I13_S : AX1
      port map(A => N234, B => \xaddr[12]_net_1\, C => 
        \xaddr[13]_net_1\, Y => \un2_xaddr[13]\);
    
    \state2[9]\ : DFN1P1
      port map(D => \state2_ns_i_a2_0_a2_0_a2[0]_net_1\, CLK => 
        clk60M, PRE => RST_c, Q => \state2[9]_net_1\);
    
    GND_i : GND
      port map(Y => GND_net_1);
    
    \state2[2]\ : DFN1C1
      port map(D => \state2_ns[7]\, CLK => clk60M, CLR => RST_c, 
        Q => \nvm_we\);
    
    P9_ssector_1_0_0_a2_0 : OR2A
      port map(A => \ssector\, B => \state2[0]_net_1\, Y => 
        N_1692);
    
    \state2_ns_i_a2_i_0_a2_7_6[9]\ : NOR3C
      port map(A => un3_finished_4_i_0, B => un3_finished_5_i_0, 
        C => \state2_ns_i_a2_i_0_a2_7_1[9]_net_1\, Y => 
        \state2_ns_i_a2_i_0_a2_7_6[9]_net_1\);
    
    un6_ewrite_i_0_3 : OR3C
      port map(A => \last_i_0[2]\, B => \un6_ewrite_i_0_3_0\, C
         => \last_i_0[1]\, Y => N_897_3);
    
    P6_waddr_3_I_51 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_1_1_0[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_2_0[0]\, Y => 
        \DWACT_ADD_CI_0_pog_array_2[0]\);
    
    \P12_wptr_4_i_m2[0]\ : MX2
      port map(A => \DWACT_ADD_CI_0_partial_sum[0]\, B => 
        \start[0]_net_1\, S => \state2_0[8]_net_1\, Y => 
        \wptr_4_i_m2[0]\);
    
    un1_inc_I_76 : AND3
      port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C
         => \raddr[12]\, Y => N_31);
    
    \state_ns_i_a2_0_0_a2_0_1[7]\ : AOI1
      port map(A => N_1776, B => N_1777, C => \wip\, Y => 
        N_1698_1);
    
    un1_inc_I_62 : AND3
      port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C
         => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\);
    
    \state[5]\ : DFN1E1C1
      port map(D => \state[6]_net_1\, CLK => CLK_c, CLR => 
        CSn_c_0, E => N_1783, Q => \state[5]_net_1\);
    
    \P5_rdata_4_2_0_0[3]\ : OA1A
      port map(A => \stat[3]_net_1\, B => N_1803, C => N_1711, Y
         => \rdata_4_2_0_0[3]\);
    
    \P5_rdata_4_2_0_a2_3[2]\ : OR3B
      port map(A => N_1773, B => N_1546, C => N_1523, Y => N_1803);
    
    addr_ld_0_sqmuxa_0_a2_0_1 : OR3A
      port map(A => \cmnd[0]_net_1\, B => N_1798, C => N_1771, Y
         => \addr_ld_0_sqmuxa_0_a2_0_1\);
    
    P9_swrite_1_0_0 : AO1A
      port map(A => \state2[0]_net_1\, B => \swrite\, C => N_1693, 
        Y => swrite_1);
    
    un2_xaddr_ADD_19x19_slow_I3_S : XNOR2
      port map(A => \xaddr[3]_net_1\, B => I2_un1_CO1_0, Y => 
        \un2_xaddr[3]\);
    
    un1_end_adr_ADD_19x19_slow_I15_CO1_3 : NOR3C
      port map(A => \raddr[13]\, B => ADD_19x19_slow_I15_CO1_1, C
         => \raddr[12]\, Y => ADD_19x19_slow_I15_CO1_3);
    
    G1_18_P4_un138_state_0_0 : AO1B
      port map(A => N_1806, B => \state[6]_net_1\, C => N_1669, Y
         => un138_state);
    
    \state2_ns_i_a2_0_0_a2_2_4[8]\ : NOR3C
      port map(A => \xaddr[8]_net_1\, B => \xaddr[10]_net_1\, C
         => \xaddr[9]_net_1\, Y => 
        \state2_ns_i_a2_0_0_a2_2_4[8]_net_1\);
    
    \P5_rdata_4_1_0[6]\ : AO1C
      port map(A => N_1784, B => nvm_dout(6), C => N_1716, Y => 
        \rdata_4[6]\);
    
    G1_17_P4_un131_state_0_0 : AO1B
      port map(A => N_1805, B => \state[6]_net_1\, C => N_1669, Y
         => un131_state);
    
    state_tr0_3_a2_2_0 : NOR2
      port map(A => DI_c_0, B => \cmnd[1]_net_1\, Y => 
        \state_tr0_3_a2_2_0\);
    
    \state_ns_i_a2_0_0_a2_3[7]\ : OR3
      port map(A => N_1525, B => \cmnd[2]_net_1\, C => 
        \state_ns_i_a2_0_0_a2_3_1[7]_net_1\, Y => N_1701_i);
    
    un1_inc_I_115 : XOR2
      port map(A => N_4, B => \raddr[18]\, Y => I_115);
    
    P6_waddr_3_I_53 : AND2
      port map(A => \waddr[4]_net_1\, B => \waddr[5]_net_1\, Y
         => \DWACT_ADD_CI_0_pog_array_1_1_0[0]\);
    
    \un10_i_a2_0_a2_0_a2[2]\ : OR3
      port map(A => \state[2]_net_1\, B => 
        \un10_i_a2_0_a2_0_a2_0[2]_net_1\, C => \state[0]_net_1\, 
        Y => \un10_i_a2_0_a2_0_a2[2]_net_1\);
    
    \stat[1]\ : DFN1E1P1
      port map(D => \stat[0]_net_1\, CLK => CLK_c, PRE => RST_c, 
        E => \state[1]_net_1\, Q => \stat[1]_net_1\);
    
    \start[0]\ : DFN1C1
      port map(D => \DWACT_ADD_CI_0_partial_sum_0[0]\, CLK => 
        CLK_c, CLR => N_1471_0, Q => \start[0]_net_1\);
    
    state2_tr12_i_0_a2_0_15 : NOR2B
      port map(A => \state2_tr12_i_0_a2_0_9\, B => 
        \state2_tr12_i_0_a2_0_13\, Y => \state2_tr12_i_0_a2_0_15\);
    
    \state2_ns_i_a2_i_0_a2_3[9]\ : OR2A
      port map(A => \state2[6]_net_1\, B => \swrite\, Y => N_1778);
    
    \P5_rdata_4_2_0_a2[0]\ : OR3B
      port map(A => N_1773, B => \rdata_4_2_0_a2_0[0]\, C => 
        N_1523, Y => N_1706);
    
    P6_start_3_I_47 : AND2
      port map(A => \start[2]_net_1\, B => \start[3]_net_1\, Y
         => \DWACT_ADD_CI_0_pog_array_1_0[0]\);
    
    \wdata[2]\ : DFN1E1C1
      port map(D => \wdata[1]_net_1\, CLK => CLK_c, CLR => 
        N_1471_0, E => \state[2]_net_1\, Q => \wdata[2]_net_1\);
    
    \wptr[3]\ : DFN1C1
      port map(D => \wptr_4_i_m2[3]\, CLK => clk60M, CLR => RST_c, 
        Q => \wptr[3]_net_1\);
    
    sbulk : DFN1C1
      port map(D => sbulk_1, CLK => clk60M, CLR => RST_c, Q => 
        \sbulk\);
    
    \P12_xaddr_4_i_o2[0]\ : OR2A
      port map(A => \state2[8]_net_1\, B => N_1534, Y => N_1538);
    
    \P12_xaddr_4_r[5]\ : NOR3A
      port map(A => N_1538_0, B => N_1622, C => 
        addr_ld_0_sqmuxa_0, Y => \xaddr_4[5]\);
    
    \addr_i_m2_i_m2[15]\ : MX2
      port map(A => \xaddr[15]_net_1\, B => \raddr[15]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(15));
    
    \waddr[7]\ : DFN1C1
      port map(D => \waddr_3[7]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \waddr[7]_net_1\);
    
    P6_start_3_I_35 : NOR2B
      port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => 
        \start[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1_0[0]\);
    
    \state2_0[9]\ : DFN1P1
      port map(D => \state2_ns_i_a2_0_a2_0_a2[0]_net_1\, CLK => 
        clk60M, PRE => RST_c, Q => \state2_0[9]_net_1\);
    
    un1_wptr_I_31 : XOR2
      port map(A => \wptr[1]_net_1\, B => 
        \DWACT_ADD_CI_0_TMP_1[0]\, Y => I_31_0);
    
    \addr_i_m2_i_m2[6]\ : MX2
      port map(A => \xaddr[6]_net_1\, B => \raddr[6]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(6));
    
    \P12_xaddr_4_r[10]\ : NOR3A
      port map(A => N_1538, B => N_1627, C => addr_ld_0_sqmuxa, Y
         => \xaddr_4[10]\);
    
    \P5_rdata_4_2_0_a2_0[0]\ : OR2B
      port map(A => \nvm_read\, B => nvm_dout(0), Y => N_1707);
    
    state2_tr12_i_0_a2_0_13 : NOR2B
      port map(A => \state2_tr12_i_0_a2_0_6\, B => 
        \state2_tr12_i_0_a2_0_5\, Y => \state2_tr12_i_0_a2_0_13\);
    
    \state_ns_i_a2_0_0[7]\ : OA1A
      port map(A => N_1698_1, B => N_1796, C => 
        \state_ns_i_a2_0_0_2[7]_net_1\, Y => N_430_i_0);
    
    un2_xaddr_ADD_19x19_slow_I2_S : AX1
      port map(A => I0_un1_CO1_0, B => \xaddr[1]_net_1\, C => 
        \xaddr[2]_net_1\, Y => \un2_xaddr[2]\);
    
    \G1_4_P4_raddr_37_i_m2_i_m2[4]\ : MX2
      port map(A => I_20, B => DI_c_1, S => \bit_cnt_0[1]_net_1\, 
        Y => N_1655);
    
    G1_13_P4_un103_state_0_0 : AO1B
      port map(A => N_1680_1, B => \state[5]_net_1\, C => N_1669, 
        Y => un103_state);
    
    un1_inc_I_87 : AND3
      port map(A => \raddr[12]\, B => \raddr[13]\, C => 
        \raddr[14]\, Y => \DWACT_FINC_E[9]\);
    
    un1_inc_I_20 : XOR2
      port map(A => N_72, B => \raddr[4]\, Y => I_20);
    
    un1_inc_I_9 : XOR2
      port map(A => N_80, B => \raddr[2]\, Y => I_9);
    
    un1_end_adr_ADD_19x19_slow_I17_S : XOR2
      port map(A => I16_un1_CO1_0, B => \raddr[17]\, Y => 
        \un1_end_adr[17]\);
    
    \state_ns_i_a2_i[5]\ : AO1
      port map(A => N_1697_1, B => \state_ns_i_a2_i_a2_0[5]\, C
         => \state[2]_net_1\, Y => N_1374);
    
    \xaddr[10]\ : DFN1E1C1
      port map(D => \xaddr_4[10]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[10]_net_1\);
    
    state_tr0_3_a2 : NOR2B
      port map(A => \state_0[7]_net_1\, B => N_1698_1, Y => 
        \state_ns[1]\);
    
    P6_waddr_3_I_33 : XOR2
      port map(A => \waddr[5]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12_1_0[0]\, Y => \waddr_3[5]\);
    
    un1_inc_I_66 : XOR2
      port map(A => N_39, B => \raddr[11]\, Y => I_66);
    
    state_tr0_3_a2_3_1_0 : OR3B
      port map(A => DI_c_0, B => \cmnd[4]_net_1\, C => 
        \cmnd[3]_net_1\, Y => \state_tr0_3_a2_3_1\);
    
    un1_inc_I_69 : AND3
      port map(A => \raddr[9]\, B => \raddr[10]\, C => 
        \raddr[11]\, Y => \DWACT_FINC_E[7]\);
    
    \state_0[7]\ : DFN1P1
      port map(D => \statese_i_0\, CLK => CLK_c, PRE => CSn_c_0, 
        Q => \state_0[7]_net_1\);
    
    \state2_0[8]\ : DFN1C1
      port map(D => \state2_tr2_i_0\, CLK => clk60M, CLR => RST_c, 
        Q => \state2_0[8]_net_1\);
    
    un1_wptr_I_47 : AND2
      port map(A => \wptr[2]_net_1\, B => \wptr[3]_net_1\, Y => 
        \DWACT_ADD_CI_0_pog_array_1_2[0]\);
    
    \xaddr[5]\ : DFN1E1C1
      port map(D => \xaddr_4[5]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[5]_net_1\);
    
    un2_xaddr_ADD_19x19_slow_I13_CO1 : OR3B
      port map(A => \xaddr[12]_net_1\, B => \xaddr[13]_net_1\, C
         => N234, Y => N242);
    
    \wptr[5]\ : DFN1C1
      port map(D => \wptr_4_i_m2[5]\, CLK => clk60M, CLR => RST_c, 
        Q => \wptr[5]_net_1\);
    
    un1_end_adr_ADD_19x19_slow_I7_CO1 : MIN3
      port map(A => \raddr[7]\, B => I6_un1_CO1_0, C => 
        \waddr[7]_net_1\, Y => N223);
    
    \state2_ns_i_a2_0_0_a2_1[8]\ : OR3B
      port map(A => \swrite\, B => N_1588_i_0, C => 
        \state2[5]_net_1\, Y => N_1705);
    
    P6_waddr_3_I_1 : AND2
      port map(A => \waddr[0]_net_1\, B => \un2_buf_we_0_a2_0_a2\, 
        Y => \DWACT_ADD_CI_0_TMP_0[0]\);
    
    \P5_rdata_4_2_0[2]\ : AO1C
      port map(A => N_1784, B => nvm_dout(2), C => 
        \rdata_4_2_0_0[2]\, Y => \rdata_4[2]\);
    
    state2_tr12_i_0_a2_0_16 : NOR3C
      port map(A => \state2_tr12_i_0_a2_0_10\, B => 
        \state2_tr12_i_0_a2_0_11\, C => \state2_tr12_i_0_a2_0_12\, 
        Y => \state2_tr12_i_0_a2_0_16\);
    
    \waddr[6]\ : DFN1C1
      port map(D => \waddr_3[6]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \waddr[6]_net_1\);
    
    G1_0_P4_raddr_0_21 : MX2A
      port map(A => N_1932_i, B => DI_c, S => un12_state_0_0_a2_0, 
        Y => raddr_0_21);
    
    state2_tr13_0_a2_1_a2 : NOR3A
      port map(A => \state2[7]_net_1\, B => N_1552, C => N_1572, 
        Y => \state2_ns[7]\);
    
    G1_11_P4_un89_state_i_i_a2_0 : NOR2A
      port map(A => \state[5]_net_1\, B => \bit_cnt_0[0]_net_1\, 
        Y => un89_state_i_i_a2_0);
    
    \state2_ns_i_a2_i_0[9]\ : OR3C
      port map(A => N_1740, B => \state2_ns_i_a2_i_0_0[9]_net_1\, 
        C => N_1738, Y => \state2_ns_i_a2_i_0[9]_net_1\);
    
    un5_esector_i_0_o2_4 : NOR2B
      port map(A => \stat[3]_net_1\, B => \stat[2]_net_1\, Y => 
        N_1526_i_0);
    
    P9_swrite_1_0_0_a2 : NOR3B
      port map(A => N_897_2, B => swrite_1_0_0_a2_1, C => 
        N_1789_i, Y => N_1693);
    
    G1_3_P4_un33_state_0_0 : AO1B
      port map(A => N_1753_1, B => un33_state_0_0_a2_0, C => 
        N_1669_0, Y => un33_state);
    
    \state2_ns_i_a2_i_0_a2_1[9]\ : OR3B
      port map(A => \state2[7]_net_1\, B => nvm_busy, C => N_1582, 
        Y => N_1739);
    
    un1_inc_I_52 : XOR2
      port map(A => N_49, B => \raddr[9]\, Y => I_52);
    
    \P12_wptr_4_i_m2[3]\ : MX2
      port map(A => I_30, B => \start[3]_net_1\, S => 
        \state2[8]_net_1\, Y => \wptr_4_i_m2[3]\);
    
    G1_8_P4_un68_state_0_0 : AO1B
      port map(A => N_1783_0, B => \state[5]_net_1\, C => 
        N_1669_0, Y => un68_state);
    
    \start[6]\ : DFN1C1
      port map(D => \start_3[6]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \start[6]_net_1\);
    
    un1_end_adr_ADD_19x19_slow_I16_un1_CO1 : NOR3C
      port map(A => \raddr[9]\, B => ADD_19x19_slow_I15_CO1_5, C
         => \raddr[16]\, Y => I16_un1_CO1_0);
    
    state2_tr12_i_0_a2_0_6 : NOR2
      port map(A => \xaddr[13]_net_1\, B => \xaddr[11]_net_1\, Y
         => \state2_tr12_i_0_a2_0_6\);
    
    state_tr0_3_a2_2_1 : OR2A
      port map(A => \cmnd[5]_net_1\, B => \cmnd[4]_net_1\, Y => 
        N_1769_1);
    
    \P5_rdata_4_i_0[4]\ : OA1B
      port map(A => N_1784, B => nvm_dout(4), C => 
        \rdata_4_i_0_0[4]\, Y => \rdata_4_i_0[4]\);
    
    un1_inc_I_44 : AND3
      port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C
         => \DWACT_FINC_E[3]\, Y => N_54);
    
    state_tr0_3_a2_2_1_0 : NOR2A
      port map(A => \cmnd[3]_net_1\, B => \cmnd[0]_net_1\, Y => 
        \state_tr0_3_a2_2_1\);
    
    \bit_cnt_i[0]\ : INV
      port map(A => \bit_cnt_0[0]_net_1\, Y => 
        \bit_cnt_i[0]_net_1\);
    
    un5_esector_i_0_o2_3 : AOI1
      port map(A => \raddr[16]\, B => \stat[2]_net_1\, C => 
        \stat[3]_net_1\, Y => N_1586);
    
    un5_esector_i_0_o2 : OR3A
      port map(A => \un5_esector_i_0_o2_0\, B => N_1529, C => 
        N_1528, Y => N_1534);
    
    \un10_i_a2_0_a2_0_a2_0[2]\ : OR2
      port map(A => \state[6]_net_1\, B => \state_0[4]_net_1\, Y
         => \un10_i_a2_0_a2_0_a2_0[2]_net_1\);
    
    un6_ewrite_i_0_3_0 : NOR2B
      port map(A => \last[5]_net_1\, B => \last[3]_net_1\, Y => 
        \un6_ewrite_i_0_3_0\);
    
    un1_inc_I_12 : AND3
      port map(A => \raddr[0]\, B => \raddr[1]\, C => \raddr[2]\, 
        Y => N_77);
    
    \P12_xaddr_4_i_m2[4]\ : MX2C
      port map(A => \raddr[4]\, B => \un2_xaddr[4]\, S => 
        \state2_0[1]_net_1\, Y => N_1621);
    
    \xaddr[2]\ : DFN1E1C1
      port map(D => \xaddr_4[2]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[2]_net_1\);
    
    un1_inc_I_94 : AND2
      port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, Y
         => \DWACT_FINC_E[10]\);
    
    \state[4]\ : DFN1E1C1
      port map(D => \state[5]_net_1\, CLK => CLK_c, CLR => 
        CSn_c_0, E => N_1783, Q => \state[4]_net_1\);
    
    un1_end_adr_ADD_19x19_slow_I0_un1_CO1 : NOR2B
      port map(A => \waddr[0]_net_1\, B => \raddr[0]\, Y => 
        I0_un1_CO1);
    
    G1_1_P4_un19_state_0_0 : AO1B
      port map(A => N_1805, B => \state_0[4]_net_1\, C => 
        N_1669_0, Y => un19_state);
    
    \P12_xaddr_4_r[13]\ : NOR3A
      port map(A => N_1538, B => N_1630, C => addr_ld_0_sqmuxa, Y
         => \xaddr_4[13]\);
    
    un2_xaddr_ADD_19x19_slow_I0_un1_CO1 : OR2A
      port map(A => \xaddr[0]_net_1\, B => N_1552, Y => 
        I0_un1_CO1_0);
    
    \rdata[2]\ : DFN0C1
      port map(D => \rdata_4[2]\, CLK => CLK_c, CLR => CSn_c_1, Q
         => \rdata[2]_net_1\);
    
    \addr_i_m2_i_m2[7]\ : MX2
      port map(A => \xaddr[7]_net_1\, B => \raddr[7]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(7));
    
    un2_xaddr_ADD_19x19_slow_I5_S : XNOR2
      port map(A => \xaddr[5]_net_1\, B => I4_un1_CO1_0, Y => 
        \un2_xaddr[5]\);
    
    state2_tr12_i_0_a2_0_2 : NOR2
      port map(A => \xaddr[10]_net_1\, B => \xaddr[8]_net_1\, Y
         => \state2_tr12_i_0_a2_0_2\);
    
    \addr_i_m2_i_m2[2]\ : MX2
      port map(A => \xaddr[2]_net_1\, B => \raddr[2]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(2));
    
    P6_un21_rstn_i_a2_i : OR2
      port map(A => \state2[0]_net_1\, B => RST_c, Y => 
        un21_rstn_i_a2_i);
    
    \addr_i_m2_i_m2[8]\ : MX2
      port map(A => \xaddr[8]_net_1\, B => \raddr[8]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(8));
    
    \state2[8]\ : DFN1C1
      port map(D => \state2_tr2_i_0\, CLK => clk60M, CLR => RST_c, 
        Q => \state2[8]_net_1\);
    
    \state2_ns_i_a2_i_0_a2[3]\ : NOR2A
      port map(A => \state2[6]_net_1\, B => nvm_busy, Y => N_1735);
    
    \wptr[6]\ : DFN1C1
      port map(D => \wptr_4_i_m2[6]\, CLK => clk60M, CLR => RST_c, 
        Q => \wptr[6]_net_1\);
    
    \state_ns_i_a2_0_0_a2_1_0[7]\ : NOR3A
      port map(A => N_1774, B => N_1525, C => \cmnd[7]_net_1\, Y
         => N_1697_1);
    
    G1_0_P4_un12_state_0_0_a2_0_0 : OR2A
      port map(A => \state[3]_net_1\, B => N_1922, Y => N_1669_0);
    
    \P12_xaddr_4_i_m2[12]\ : MX2C
      port map(A => \raddr[12]\, B => \un2_xaddr[12]\, S => 
        \state2[1]_net_1\, Y => N_1629);
    
    state_tr8_0_a2_0_o2_0 : OR2
      port map(A => \cmnd[5]_net_1\, B => \cmnd[1]_net_1\, Y => 
        N_1523);
    
    \G1_7_P4_raddr_61_i_m2[7]\ : MX2
      port map(A => DI_c_0, B => I_38, S => \bit_cnt_0[0]_net_1\, 
        Y => N_1611);
    
    \G1_16_P4_raddr[16]\ : DFN1E1C1
      port map(D => N_1660, CLK => CLK_c, CLR => RST_c, E => 
        un124_state, Q => \raddr[16]\);
    
    \P12_xaddr_4_i_0[18]\ : AOI1
      port map(A => N_1538_0, B => \state2_0[1]_net_1\, C => 
        \raddr[18]\, Y => \xaddr_4_i_0[18]\);
    
    \bit_cnt_i[2]\ : INV
      port map(A => \bit_cnt_0[2]_net_1\, Y => 
        \bit_cnt_i[2]_net_1\);
    
    un5_esector_i_0_0 : AOI1B
      port map(A => \raddr[18]\, B => N_1526_i_0, C => N_1731, Y
         => \un5_esector_i_0_0\);
    
    state2_tr12_i_0_o2_0_3 : NOR3C
      port map(A => \xaddr[3]_net_1\, B => \xaddr[5]_net_1\, C
         => \xaddr[0]_net_1\, Y => \state2_tr12_i_0_o2_0_3\);
    
    \P5_rdata_4_1_0[7]\ : AO1C
      port map(A => N_1784, B => nvm_dout(7), C => N_1718, Y => 
        \rdata_4[7]\);
    
    \addr_i_m2_i_m2[13]\ : MX2
      port map(A => \xaddr[13]_net_1\, B => \raddr[13]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(13));
    
    G1_5_P4_un47_state_0_0 : AO1B
      port map(A => N_1680_1, B => \state[4]_net_1\, C => 
        N_1669_0, Y => un47_state);
    
    \state2[5]\ : DFN1C1
      port map(D => \state2_ns_i_a2_i_0[4]_net_1\, CLK => clk60M, 
        CLR => RST_c, Q => \state2[5]_net_1\);
    
    un1_end_adr_ADD_19x19_slow_I16_S : AX1C
      port map(A => \raddr[9]\, B => ADD_19x19_slow_I15_CO1_5, C
         => \raddr[16]\, Y => \un1_end_adr[16]\);
    
    \G1_9_P4_raddr[9]\ : DFN1E1C1
      port map(D => N_1612, CLK => CLK_c, CLR => RST_c, E => 
        un75_state, Q => \raddr[9]\);
    
    un1_inc_I_45 : XOR2
      port map(A => N_54, B => \raddr[8]\, Y => I_45);
    
    un1_inc_I_41 : AND2
      port map(A => \raddr[6]\, B => \raddr[7]\, Y => 
        \DWACT_FINC_E[3]\);
    
    iwebit_1_0_o2 : OR2A
      port map(A => \un2_idis_0_o2\, B => \wdis_dly\, Y => N_1592);
    
    \state_ns_i_a2_i_0_a2[4]\ : OA1
      port map(A => N_1785, B => \nvm_read\, C => 
        \state[4]_net_1\, Y => N_1754);
    
    \addr_i_m2_i_m2[17]\ : MX2
      port map(A => \xaddr[17]_net_1\, B => \raddr[17]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(17));
    
    \state_ns_i_a2_0_0_a2_1[7]\ : AO1B
      port map(A => N_1767, B => N_1768, C => 
        \state_ns_i_a2_0_0_a2_1_1[7]_net_1\, Y => N_1699);
    
    \state2_ns_i_a2_0_0_a2_2_6[8]\ : NOR3C
      port map(A => \xaddr[15]_net_1\, B => \xaddr[7]_net_1\, C
         => \state2_ns_i_a2_0_0_a2_2_4[8]_net_1\, Y => 
        \state2_ns_i_a2_0_0_a2_2_6[8]_net_1\);
    
    \waddr[3]\ : DFN1C1
      port map(D => \waddr_3[3]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \waddr[3]_net_1\);
    
    \last[4]\ : DFN1C1
      port map(D => \un10_i_a2_0_a2_1_a2[1]_net_1\, CLK => CSn_c, 
        CLR => RST_c, Q => \last[4]_net_1\);
    
    G1_4_P4_un40_state_0_0_a2 : NOR3A
      port map(A => \bit_cnt[0]_net_1\, B => \bit_cnt[2]_net_1\, 
        C => N_1599, Y => un40_state);
    
    un2_xaddr_ADD_19x19_slow_I0_S : XNOR2
      port map(A => \xaddr[0]_net_1\, B => N_1552, Y => 
        \un2_xaddr[0]\);
    
    state2_tr2_i_0 : NOR2B
      port map(A => \wip\, B => \state2_0[9]_net_1\, Y => 
        \state2_tr2_i_0\);
    
    \G1_8_P4_raddr[8]\ : DFN1E1C1
      port map(D => N_1656, CLK => CLK_c, CLR => RST_c, E => 
        un68_state, Q => \raddr[8]\);
    
    un1_inc_I_101 : AND2
      port map(A => \raddr[15]\, B => \raddr[16]\, Y => 
        \DWACT_FINC_E[11]\);
    
    wena_dly : DFN1P1
      port map(D => \iwebit_1_0_a2_0_0\, CLK => clk60M, PRE => 
        RST_c, Q => wena_dly_i);
    
    un1_inc_I_91 : XOR2
      port map(A => N_21, B => \raddr[15]\, Y => I_91);
    
    state_tr0_3_a2_1 : AO1B
      port map(A => N_1769_i, B => N_1770, C => 
        \state_tr0_3_a2_1_0\, Y => N_1777);
    
    \P5_rdata_4_2_0_o2[0]\ : OR3
      port map(A => \bit_cnt_0[1]_net_1\, B => 
        \bit_cnt_0[2]_net_1\, C => \bit_cnt_0[0]_net_1\, Y => 
        N_1522);
    
    un1_inc_I_27 : AND2
      port map(A => \raddr[3]\, B => \raddr[4]\, Y => 
        \DWACT_FINC_E[1]\);
    
    un1_inc_I_56 : XOR2
      port map(A => N_46, B => \raddr[10]\, Y => I_56);
    
    un2_xaddr_ADD_19x19_slow_I10_S : XNOR2
      port map(A => \xaddr[10]_net_1\, B => N226, Y => 
        \un2_xaddr[10]\);
    
    P6_start_3_I_36 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_1_0[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_0[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_2_0[0]\);
    
    un1_inc_I_59 : AND3
      port map(A => \raddr[6]\, B => \raddr[7]\, C => \raddr[8]\, 
        Y => \DWACT_FINC_E[5]\);
    
    P9_sbulk_1_0_0 : OAI1
      port map(A => N_1789_i, B => sbulk_1_0_0_a2_0_1, C => 
        N_1687, Y => sbulk_1);
    
    \P12_xaddr_4_r[16]\ : NOR3
      port map(A => N_1720, B => \xaddr_4_i_0[16]\, C => 
        addr_ld_0_sqmuxa, Y => \xaddr_4[16]\);
    
    \stat[2]\ : DFN1E1P1
      port map(D => \stat[1]_net_1\, CLK => CLK_c, PRE => RST_c, 
        E => \state[1]_net_1\, Q => \stat[2]_net_1\);
    
    \P12_xaddr_4_i_m2[14]\ : MX2C
      port map(A => \raddr[14]\, B => \un2_xaddr[14]\, S => 
        \state2[1]_net_1\, Y => N_1631);
    
    iwebit_1_0 : AO1B
      port map(A => N_1592, B => N_1775, C => N_1690, Y => 
        iwebit_1);
    
    \P5_rdata_4_2_0_a2[2]\ : OR2B
      port map(A => \rdata[1]_net_1\, B => N_1522, Y => N_1708);
    
    un3_finished_1 : XNOR2
      port map(A => \wptr[1]_net_1\, B => \waddr[1]_net_1\, Y => 
        un3_finished_1_i_0);
    
    \state_ns_i_a2_0_0_a2_1_1_0[7]\ : NOR2B
      port map(A => N_1699_1, B => 
        \state_ns_i_a2_0_0_a2_1_0[7]_net_1\, Y => 
        \state_ns_i_a2_0_0_a2_1_1[7]_net_1\);
    
    un6_ewrite_i_0_o2 : AO1
      port map(A => \stat[2]_net_1\, B => \un1_end_adr[16]\, C
         => \stat[3]_net_1\, Y => N_1587);
    
    un1_inc_I_8 : NOR2B
      port map(A => \raddr[1]\, B => \raddr[0]\, Y => N_80);
    
    P6_start_3_I_33 : XOR2
      port map(A => \start[5]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => \start_3[5]\);
    
    \stat[3]\ : DFN1E1P1
      port map(D => \stat[2]_net_1\, CLK => CLK_c, PRE => RST_c, 
        E => \state[1]_net_1\, Q => \stat[3]_net_1\);
    
    P6_start_3_I_32 : XOR2
      port map(A => \start[2]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_1_0[0]\, Y => \start_3[2]\);
    
    un1_inc_I_13 : XOR2
      port map(A => N_77, B => \raddr[3]\, Y => I_13);
    
    \state[1]\ : DFN1E1C1
      port map(D => \state_ns[6]\, CLK => CLK_c, CLR => CSn_c_0, 
        E => N_1783, Q => \state[1]_net_1\);
    
    \addr_i_m2_i_m2[1]\ : MX2
      port map(A => \xaddr[1]_net_1\, B => \raddr[1]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(1));
    
    \rdata[7]\ : DFN0C1
      port map(D => \rdata_4[7]\, CLK => CLK_c, CLR => CSn_c_1, Q
         => rdata_7);
    
    state_tr0_3_a2_3_1 : OR2A
      port map(A => \cmnd[0]_net_1\, B => N_1523, Y => N_1770_1);
    
    \P5_rdata_4_2_0_0[2]\ : OA1A
      port map(A => \stat[2]_net_1\, B => N_1803, C => N_1708, Y
         => \rdata_4_2_0_0[2]\);
    
    \P5_rdata_4_1_0[5]\ : AO1C
      port map(A => N_1784, B => nvm_dout(5), C => N_1714, Y => 
        \rdata_4[5]\);
    
    \P12_xaddr_4_i_m2[6]\ : MX2C
      port map(A => \raddr[6]\, B => \un2_xaddr[6]\, S => 
        \state2[1]_net_1\, Y => N_1623);
    
    un1_inc_I_16 : AND3
      port map(A => \raddr[0]\, B => \raddr[1]\, C => \raddr[2]\, 
        Y => \DWACT_FINC_E[0]\);
    
    un1_inc_I_19 : NOR2B
      port map(A => \raddr[3]\, B => \DWACT_FINC_E[0]\, Y => N_72);
    
    un1_inc_I_77 : XOR2
      port map(A => N_31, B => \raddr[13]\, Y => I_77);
    
    \G1_6_P4_raddr_53_i_m2_i_m2[6]\ : MX2
      port map(A => I_31, B => DI_c_1, S => \state[4]_net_1\, Y
         => N_1652);
    
    G1_11_P4_un89_state_i_i_a2_1 : NOR2A
      port map(A => \bit_cnt_0[2]_net_1\, B => \bit_cnt[1]_net_1\, 
        Y => N_1753_1);
    
    un1_end_adr_ADD_19x19_slow_I15_CO1_1 : NOR3C
      port map(A => \raddr[15]\, B => I8_un1_CO1, C => 
        \raddr[14]\, Y => ADD_19x19_slow_I15_CO1_1);
    
    un5_esector_i_0_a2 : OR3B
      port map(A => \raddr[18]\, B => \raddr[17]\, C => N_1586, Y
         => N_1731);
    
    un1_end_adr_ADD_19x19_slow_I15_CO1_5 : NOR3C
      port map(A => \raddr[11]\, B => ADD_19x19_slow_I15_CO1_3, C
         => \raddr[10]\, Y => ADD_19x19_slow_I15_CO1_5);
    
    \P5_rdata_4_i_0_a2[1]\ : NOR2A
      port map(A => N_1522, B => \rdata[0]_net_1\, Y => N_1745);
    
    addr_ld_0_sqmuxa_0_a2 : NOR2B
      port map(A => \state2_0[8]_net_1\, B => N_1924, Y => 
        addr_ld_0_sqmuxa);
    
    \start[1]\ : DFN1C1
      port map(D => \start_3[1]\, CLK => CLK_c, CLR => N_1471_0, 
        Q => \start[1]_net_1\);
    
    G1_9_P4_un75_state_0_0 : AO1B
      port map(A => N_1805, B => \state[5]_net_1\, C => N_1669_0, 
        Y => un75_state);
    
    P6_start_3_I_28 : XOR2
      port map(A => \start[4]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_2_0[0]\, Y => \start_3[4]\);
    
    \waddr[4]\ : DFN1C1
      port map(D => \waddr_3[4]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \waddr[4]_net_1\);
    
    un1_wptr_I_42 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_2_1[0]\, B => 
        \wptr[4]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_1_1[0]\);
    
    P6_waddr_3_I_37 : XOR2
      port map(A => \waddr[3]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12_0[0]\, Y => \waddr_3[3]\);
    
    \P12_xaddr_4_i_a2[18]\ : XA1B
      port map(A => N258, B => \xaddr[18]_net_1\, C => N_1926, Y
         => N_1726);
    
    \cmnd[7]\ : DFN1E1C1
      port map(D => \cmnd[6]_net_1\, CLK => CLK_c, CLR => RST_c, 
        E => \state[7]_net_1\, Q => \cmnd[7]_net_1\);
    
    \state2_ns_i_a2_i_0[4]\ : AO1A
      port map(A => nvm_busy, B => \state2[5]_net_1\, C => 
        \nvm_pgm\, Y => \state2_ns_i_a2_i_0[4]_net_1\);
    
    \P5_rdata_4_i_0_0[4]\ : AO1D
      port map(A => N_1803, B => \stat[4]_net_1\, C => N_1756, Y
         => \rdata_4_i_0_0[4]\);
    
    P9_sbulk_1_0_0_a2_1 : OR3B
      port map(A => CSn_c_0, B => N_1775, C => \stat[4]_net_1\, Y
         => N_1789_i);
    
    \wptr[4]\ : DFN1C1
      port map(D => \wptr_4_i_m2[4]\, CLK => clk60M, CLR => RST_c, 
        Q => \wptr[4]_net_1\);
    
    \P12_xaddr_4_r[6]\ : NOR3A
      port map(A => N_1538_0, B => N_1623, C => 
        addr_ld_0_sqmuxa_0, Y => \xaddr_4[6]\);
    
    state2_tr12_i_0_a2_0 : NOR2B
      port map(A => \state2_tr12_i_0_a2_0_16\, B => 
        \state2_tr12_i_0_a2_0_15\, Y => N_1730);
    
    un1_inc_I_84 : XOR2
      port map(A => N_26, B => \raddr[14]\, Y => I_84);
    
    \state2_ns_i_a2_0_0_a2_2[8]\ : OR3C
      port map(A => \state2_ns_i_a2_0_0_a2_2_6[8]_net_1\, B => 
        \state2_ns_i_a2_0_0_a2_2_5[8]_net_1\, C => 
        \state2_ns_i_a2_0_0_o2_0[8]_net_1\, Y => N_1801);
    
    \addr_i_m2_i_m2[3]\ : MX2
      port map(A => \xaddr[3]_net_1\, B => \raddr[3]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(3));
    
    \P12_wptr_4_i_m2[6]\ : MX2
      port map(A => I_27, B => \start[6]_net_1\, S => 
        \state2[8]_net_1\, Y => \wptr_4_i_m2[6]\);
    
    un6_ewrite_i_0_a2_0 : OR2B
      port map(A => \un1_end_adr[18]\, B => N_1526_i_0, Y => 
        N_1734);
    
    un1_inc_I_30 : AND3
      port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C
         => \raddr[5]\, Y => N_64);
    
    P6_start_3_I_19 : XOR2
      port map(A => \start[0]_net_1\, B => un146_state, Y => 
        \DWACT_ADD_CI_0_partial_sum_0[0]\);
    
    \P12_xaddr_4_r[2]\ : NOR3A
      port map(A => N_1538_0, B => N_1619, C => 
        addr_ld_0_sqmuxa_0, Y => \xaddr_4[2]\);
    
    un2_xaddr_ADD_19x19_slow_I6_S : AX1
      port map(A => I4_un1_CO1_0, B => \xaddr[5]_net_1\, C => 
        \xaddr[6]_net_1\, Y => \un2_xaddr[6]\);
    
    \rdata[5]\ : DFN0C1
      port map(D => \rdata_4[5]\, CLK => CLK_c, CLR => CSn_c_1, Q
         => \rdata[5]_net_1\);
    
    P9_sbulk_1_0_0_a2_0_1 : OR3A
      port map(A => N_1924, B => \dly_bulk\, C => N_1742_1, Y => 
        sbulk_1_0_0_a2_0_1);
    
    \P5_rdata_4_2_0[0]\ : OR3B
      port map(A => N_1706, B => N_1707, C => N_1522, Y => 
        \rdata_4[0]\);
    
    \addr_i_m2_i_m2[18]\ : MX2
      port map(A => \xaddr[18]_net_1\, B => \raddr[18]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(18));
    
    P6_start_3_I_30 : XOR2
      port map(A => \start[3]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12[0]\, Y => \start_3[3]\);
    
    \P12_wptr_4_i_m2[1]\ : MX2
      port map(A => I_31_0, B => \start[1]_net_1\, S => 
        \state2_0[8]_net_1\, Y => \wptr_4_i_m2[1]\);
    
    \G1_17_P4_raddr[17]\ : DFN1E1C1
      port map(D => N_1616, CLK => CLK_c, CLR => RST_c, E => 
        un131_state, Q => \raddr[17]\);
    
    P6_waddr_3_I_43 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_2[0]\);
    
    \P12_xaddr_4_i_m2[2]\ : MX2C
      port map(A => \raddr[2]\, B => \un2_xaddr[2]\, S => 
        \state2_0[1]_net_1\, Y => N_1619);
    
    \addr_i_m2_i_m2[14]\ : MX2
      port map(A => \xaddr[14]_net_1\, B => \raddr[14]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(14));
    
    \state2_ns_i_a2_0_0_a2_2_3[8]\ : NOR2B
      port map(A => \xaddr[13]_net_1\, B => \xaddr[11]_net_1\, Y
         => \state2_ns_i_a2_0_0_a2_2_3[8]_net_1\);
    
    \cmnd[0]\ : DFN1E1C1
      port map(D => DI_c, CLK => CLK_c, CLR => RST_c, E => 
        \state_0[7]_net_1\, Q => \cmnd[0]_net_1\);
    
    \un10_i_a2_0_a2_1_a2[0]\ : OR3A
      port map(A => N_1781, B => \state[2]_net_1\, C => 
        \state[3]_net_1\, Y => \un10_i_a2_0_a2_1_a2[0]_net_1\);
    
    dly_write : DFN1P1
      port map(D => N_897_i_0, CLK => clk60M, PRE => RST_c, Q => 
        dly_write_i);
    
    un1_wptr_I_28 : XOR2
      port map(A => \wptr[4]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_2_1[0]\, Y => I_28);
    
    P6_waddr_3_I_52 : AND2
      port map(A => \waddr[2]_net_1\, B => \waddr[3]_net_1\, Y
         => \DWACT_ADD_CI_0_pog_array_1[0]\);
    
    \G1_17_P4_raddr_141_i_m2[17]\ : MX2
      port map(A => DI_c_1, B => I_105, S => \bit_cnt[0]_net_1\, 
        Y => N_1616);
    
    un1_wptr_I_35 : NOR2B
      port map(A => \DWACT_ADD_CI_0_TMP_1[0]\, B => 
        \wptr[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1_1[0]\);
    
    \G1_1_P4_raddr_13_i_m2[1]\ : MX2
      port map(A => DI_c_0, B => I_5, S => \bit_cnt_0[0]_net_1\, 
        Y => N_1608);
    
    un5_ebulk_0_a2_0_a2 : NOR3A
      port map(A => N_1924, B => N_1742_1, C => N_1662, Y => 
        \un5_ebulk_0_a2_0_a2\);
    
    P6_start_3_I_31 : XOR2
      port map(A => \start[1]_net_1\, B => 
        \DWACT_ADD_CI_0_TMP[0]\, Y => \start_3[1]\);
    
    \addr_i_m2_i_m2[9]\ : MX2
      port map(A => \xaddr[9]_net_1\, B => \raddr[9]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(9));
    
    \wptr[2]\ : DFN1C1
      port map(D => \wptr_4_i_m2[2]\, CLK => clk60M, CLR => RST_c, 
        Q => \wptr[2]_net_1\);
    
    \state[0]\ : DFN1E1C1
      port map(D => N_430_i_0, CLK => CLK_c, CLR => CSn_c_1, E
         => N_1783, Q => \state[0]_net_1\);
    
    G1_14_P4_un110_state_0_a2_0_a2 : OA1B
      port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C
         => N_1922, Y => un110_state);
    
    \rdata[0]\ : DFN0C1
      port map(D => \rdata_4[0]\, CLK => CLK_c, CLR => CSn_c_1, Q
         => \rdata[0]_net_1\);
    
    \G1_3_P4_raddr[3]\ : DFN1E1C1
      port map(D => N_1609, CLK => CLK_c, CLR => RST_c, E => 
        un33_state, Q => \raddr[3]\);
    
    \G1_2_P4_raddr_21_i_m2_i_m2[2]\ : MX2
      port map(A => I_9, B => DI_c_1, S => \bit_cnt_0[2]_net_1\, 
        Y => N_1654);
    
    \bit_cnt[1]\ : DFN1C1
      port map(D => SUM1, CLK => CLK_c, CLR => CSn_c, Q => 
        \bit_cnt[1]_net_1\);
    
    ssector : DFN1C1
      port map(D => ssector_1, CLK => clk60M, CLR => RST_c, Q => 
        \ssector\);
    
    addr_ld_0_sqmuxa_0_a2_0 : NOR2
      port map(A => \addr_ld_0_sqmuxa_0_a2_0_1\, B => N_1529, Y
         => N_1924);
    
    \state2_ns_i_a2_0_0_a2_0[8]\ : OR2
      port map(A => \state2[6]_net_1\, B => \state2[5]_net_1\, Y
         => N_1704);
    
    G1_1_P4_un19_state_0_0_a2_0 : NOR3B
      port map(A => \bit_cnt_0[1]_net_1\, B => 
        \bit_cnt_0[2]_net_1\, C => \bit_cnt_0[0]_net_1\, Y => 
        N_1805);
    
    state2_tr12_i_0_o2 : OR2B
      port map(A => nvm_busy, B => \swrite\, Y => N_1572);
    
    un2_xaddr_ADD_19x19_slow_I15_CO1 : OR3B
      port map(A => \xaddr[14]_net_1\, B => \xaddr[15]_net_1\, C
         => N242, Y => N250);
    
    \un5_do_0_a2_2_a2\ : OA1
      port map(A => N_1785, B => \nvm_read\, C => 
        \state[3]_net_1\, Y => un5_do_0_a2_2_a2);
    
    \state_ns_i_a2_0_0_a2_1_1[7]\ : NOR2A
      port map(A => \cmnd[0]_net_1\, B => \cmnd[6]_net_1\, Y => 
        N_1699_1);
    
    \state_ns_i_a2_0_0_a2_2[7]\ : OR2
      port map(A => \state_0[7]_net_1\, B => N_1796, Y => N_1700);
    
    \state_ns_i_a2_0_0_1[7]\ : NOR3C
      port map(A => N_1699, B => N_1700, C => N_1701_i, Y => 
        \state_ns_i_a2_0_0_1[7]_net_1\);
    
    un5_esector_i_0_o2_6 : OR2B
      port map(A => \cmnd[7]_net_1\, B => \cmnd[6]_net_1\, Y => 
        N_1529);
    
    state2_tr11_i_0 : NOR3C
      port map(A => \state2[7]_net_1\, B => nvm_busy, C => N_1552, 
        Y => \state2_tr11_i_0\);
    
    P6_start_3_I_44 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_1_0[0]\, B => 
        \start[2]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12[0]\);
    
    \xaddr[14]\ : DFN1E1C1
      port map(D => \xaddr_4[14]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[14]_net_1\);
    
    \G1_15_P4_raddr[15]\ : DFN1E1C1
      port map(D => N_1615, CLK => CLK_c, CLR => RST_c, E => 
        un117_state, Q => \raddr[15]\);
    
    \state_ns_i_a2_i_0[4]\ : OR3
      port map(A => N_1755, B => \state[3]_net_1\, C => N_1754, Y
         => N_1175);
    
    \G1_9_P4_raddr_77_i_m2[9]\ : MX2
      port map(A => DI_c_0, B => I_52, S => \bit_cnt_0[0]_net_1\, 
        Y => N_1612);
    
    \addr_i_m2_i_m2[5]\ : MX2
      port map(A => \xaddr[5]_net_1\, B => \raddr[5]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(5));
    
    G1_12_P4_un96_state_0_0_a2 : NOR3A
      port map(A => \bit_cnt[0]_net_1\, B => \bit_cnt[2]_net_1\, 
        C => N_1598, Y => un96_state);
    
    P6_waddr_3_I_32 : XOR2
      port map(A => \waddr[1]_net_1\, B => 
        \DWACT_ADD_CI_0_TMP_0[0]\, Y => \waddr_3[1]\);
    
    \state2_ns_i_a2_i_0_a2_2[9]\ : OR3B
      port map(A => N_1804, B => N_1730, C => N_1572, Y => N_1740);
    
    \P12_xaddr_4_i_m2[10]\ : MX2C
      port map(A => \raddr[10]\, B => \un2_xaddr[10]\, S => 
        \state2[1]_net_1\, Y => N_1627);
    
    P6_waddr_3_I_50 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_11_0[0]\, B => 
        \waddr[6]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_2_0[0]\);
    
    un2_buf_we_0_a2_0_a2 : NOR2B
      port map(A => \state[2]_net_1\, B => N_1783_0, Y => 
        \un2_buf_we_0_a2_0_a2\);
    
    un5_esector_i_0_o2_0_0 : NOR2A
      port map(A => \cmnd[4]_net_1\, B => N_1530, Y => 
        \un5_esector_i_0_o2_0\);
    
    un1_inc_I_104 : AND3
      port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C
         => \DWACT_FINC_E[11]\, Y => N_11);
    
    un1_inc_I_48 : AND3
      port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C
         => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\);
    
    \state2_ns_i_a2_i_0_o2_0[9]\ : OR2
      port map(A => \swrite\, B => N_1552, Y => N_1582);
    
    \stat[4]\ : DFN1E1P1
      port map(D => \stat[3]_net_1\, CLK => CLK_c, PRE => RST_c, 
        E => \state[1]_net_1\, Q => \stat[4]_net_1\);
    
    \cmnd[4]\ : DFN1E1C1
      port map(D => \cmnd[3]_net_1\, CLK => CLK_c, CLR => RST_c, 
        E => \state[7]_net_1\, Q => \cmnd[4]_net_1\);
    
    P6_waddr_3_I_35 : XOR2
      port map(A => \waddr[2]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_1[0]\, Y => \waddr_3[2]\);
    
    un1_inc_I_24 : XOR2
      port map(A => N_69, B => \raddr[5]\, Y => I_24);
    
    \G1_12_P4_raddr[12]\ : DFN1E1C1
      port map(D => N_1658, CLK => CLK_c, CLR => RST_c, E => 
        un96_state, Q => \raddr[12]\);
    
    un1_wptr_I_44 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_1_1[0]\, B => 
        \wptr[2]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_3[0]\);
    
    \rdata[6]\ : DFN0C1
      port map(D => \rdata_4[6]\, CLK => CLK_c, CLR => CSn_c_1, Q
         => \rdata[6]_net_1\);
    
    \state2_ns_i_a2_0_0_a2_2_5[8]\ : NOR3C
      port map(A => \xaddr[12]_net_1\, B => \xaddr[14]_net_1\, C
         => \state2_ns_i_a2_0_0_a2_2_3[8]_net_1\, Y => 
        \state2_ns_i_a2_0_0_a2_2_5[8]_net_1\);
    
    P9_ssector_1_0_0 : OAI1
      port map(A => N_1789_i, B => ssector_1_0_0_a2_1, C => 
        N_1692, Y => ssector_1);
    
    un2_xaddr_ADD_19x19_slow_I8_S : XNOR2
      port map(A => \xaddr[8]_net_1\, B => N220_1, Y => 
        \un2_xaddr[8]\);
    
    un1_inc_I_98 : XOR2
      port map(A => N_16, B => \raddr[16]\, Y => I_98);
    
    \addr_i_m2_i_m2[0]\ : MX2
      port map(A => \xaddr[0]_net_1\, B => \raddr[0]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr(0));
    
    un1_inc_I_37 : AND3
      port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C
         => \raddr[6]\, Y => N_59);
    
    un2_xaddr_ADD_19x19_slow_I7_CO1_1 : AO1C
      port map(A => N_1552, B => I6_un1_CO1, C => 
        \xaddr[7]_net_1\, Y => N220_1);
    
    M1 : ram256x8
      port map(wdata(6) => \wdata[6]_net_1\, wdata(5) => 
        \wdata[5]_net_1\, wdata(4) => \wdata[4]_net_1\, wdata(3)
         => \wdata[3]_net_1\, wdata(2) => \wdata[2]_net_1\, 
        wdata(1) => \wdata[1]_net_1\, wdata(0) => 
        \wdata[0]_net_1\, wptr(7) => \wptr[7]_net_1\, wptr(6) => 
        \wptr[6]_net_1\, wptr(5) => \wptr[5]_net_1\, wptr(4) => 
        \wptr[4]_net_1\, wptr(3) => \wptr[3]_net_1\, wptr(2) => 
        \wptr[2]_net_1\, wptr(1) => \wptr[1]_net_1\, wptr(0) => 
        \wptr[0]_net_1\, waddr(7) => \waddr[7]_net_1\, waddr(6)
         => \waddr[6]_net_1\, waddr(5) => \waddr[5]_net_1\, 
        waddr(4) => \waddr[4]_net_1\, waddr(3) => 
        \waddr[3]_net_1\, waddr(2) => \waddr[2]_net_1\, waddr(1)
         => \waddr[1]_net_1\, waddr(0) => \waddr[0]_net_1\, 
        nvm_din(7) => nvm_din(7), nvm_din(6) => nvm_din(6), 
        nvm_din(5) => nvm_din(5), nvm_din(4) => nvm_din(4), 
        nvm_din(3) => nvm_din(3), nvm_din(2) => nvm_din(2), 
        nvm_din(1) => nvm_din(1), nvm_din(0) => nvm_din(0), 
        RST_c_i => RST_c_i, DI_c => DI_c, clk60M => clk60M, CLK_c
         => CLK_c, N_1923_i => \N_1923_i\, \GND\ => GND_net_1, 
        \VCC\ => VCC_net_1);
    
    \waddr[5]\ : DFN1C1
      port map(D => \waddr_3[5]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \waddr[5]_net_1\);
    
    \xaddr[8]\ : DFN1E1C1
      port map(D => \xaddr_4[8]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[8]_net_1\);
    
    \xaddr[12]\ : DFN1E1C1
      port map(D => \xaddr_4[12]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[12]_net_1\);
    
    \P5_rdata_4_i_0[1]\ : OA1B
      port map(A => N_1784, B => nvm_dout(1), C => 
        \rdata_4_i_0_0[1]\, Y => \rdata_4_i_0[1]\);
    
    \waddr[1]\ : DFN1C1
      port map(D => \waddr_3[1]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \waddr[1]_net_1\);
    
    G1_15_P4_un117_state_0_0 : AO1C
      port map(A => N_1522, B => \state[5]_net_1\, C => N_1669_0, 
        Y => un117_state);
    
    \state2[1]\ : DFN1C1
      port map(D => N_465_i_0, CLK => clk60M, CLR => RST_c, Q => 
        \state2[1]_net_1\);
    
    P9_ssector_1_0_0_o2 : NOR3A
      port map(A => \raddr[18]\, B => N_1586, C => N_1802, Y => 
        N_1589);
    
    \state2_ns_i_a2_i_0_a2_7_0[9]\ : XA1C
      port map(A => \waddr[7]_net_1\, B => \wptr[7]_net_1\, C => 
        \waddr[8]_net_1\, Y => 
        \state2_ns_i_a2_i_0_a2_7_0[9]_net_1\);
    
    \P12_wptr_4_i_m2[7]\ : MX2
      port map(A => I_34, B => \start[7]_net_1\, S => 
        \state2[8]_net_1\, Y => \wptr_4_i_m2[7]\);
    
    \wdata[6]\ : DFN1E1C1
      port map(D => \wdata[5]_net_1\, CLK => CLK_c, CLR => 
        N_1471_0, E => \state[2]_net_1\, Q => \wdata[6]_net_1\);
    
    P6_waddr_3_I_30 : XOR2
      port map(A => \waddr[4]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_2[0]\, Y => \waddr_3[4]\);
    
    G1_7_P4_un61_state_0_0 : AO1C
      port map(A => N_1522, B => \state[4]_net_1\, C => N_1669_0, 
        Y => un61_state);
    
    un2_xaddr_ADD_19x19_slow_I11_CO1 : OR3B
      port map(A => \xaddr[10]_net_1\, B => \xaddr[11]_net_1\, C
         => N226, Y => N234);
    
    \xaddr[3]\ : DFN1E1C1
      port map(D => \xaddr_4[3]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[3]_net_1\);
    
    state_tr8_0_a2_0_a2 : NOR3
      port map(A => N_1525, B => \cmnd[2]_net_1\, C => 
        \state_tr8_0_a2_0_a2_1\, Y => \state_ns[6]\);
    
    \start[2]\ : DFN1C1
      port map(D => \start_3[2]\, CLK => CLK_c, CLR => N_1471_0, 
        Q => \start[2]_net_1\);
    
    un2_xaddr_ADD_19x19_slow_I7_S : XNOR3
      port map(A => N_1552, B => \xaddr[7]_net_1\, C => 
        I6_un1_CO1, Y => \un2_xaddr[7]\);
    
    \P12_xaddr_4_r[4]\ : NOR3A
      port map(A => N_1538_0, B => N_1621, C => 
        addr_ld_0_sqmuxa_0, Y => \xaddr_4[4]\);
    
    G1_16_P4_un124_state_0_0 : AO1B
      port map(A => N_1783_0, B => \state[6]_net_1\, C => N_1669, 
        Y => un124_state);
    
    \xaddr[18]\ : DFN1E1C1
      port map(D => \xaddr_4[18]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[18]_net_1\);
    
    un1_inc_I_108 : AND3
      port map(A => \raddr[15]\, B => \raddr[16]\, C => 
        \raddr[17]\, Y => \DWACT_FINC_E[12]\);
    
    un2_xaddr_ADD_19x19_slow_I15_S : AX1
      port map(A => N242, B => \xaddr[14]_net_1\, C => 
        \xaddr[15]_net_1\, Y => \un2_xaddr[15]\);
    
    \state_ns_i_a2_0_0_a2_6[7]\ : NOR2
      port map(A => \state[1]_net_1\, B => \state[0]_net_1\, Y
         => N_1781);
    
    \state_ns_i_a2_0_0_a2_4_0[7]\ : OR2B
      port map(A => \cmnd[7]_net_1\, B => \cmnd[1]_net_1\, Y => 
        \state_ns_i_a2_0_0_a2_4_0[7]_net_1\);
    
    un3_finished_2 : XNOR2
      port map(A => \wptr[2]_net_1\, B => \waddr[2]_net_1\, Y => 
        un3_finished_2_i_0);
    
    un6_ewrite_i_0_1 : NOR3B
      port map(A => N_1733, B => N_1734, C => N_897_3, Y => 
        \un6_ewrite_i_0_1\);
    
    \state_ns_i_a2_0_0_a2_0_0[7]\ : AOI1B
      port map(A => N_1799, B => \state_0[7]_net_1\, C => N_1781, 
        Y => \state_ns_i_a2_0_0_a2_0[7]\);
    
    \P12_xaddr_4_r[1]\ : NOR3A
      port map(A => N_1538_0, B => N_1618, C => 
        addr_ld_0_sqmuxa_0, Y => \xaddr_4[1]\);
    
    un3_finished_5 : XNOR2
      port map(A => \wptr[5]_net_1\, B => \waddr[5]_net_1\, Y => 
        un3_finished_5_i_0);
    
    dly_bulk : DFN1C1
      port map(D => \un5_ebulk_0_a2_0_a2\, CLK => clk60M, CLR => 
        RST_c, Q => \dly_bulk\);
    
    \P12_xaddr_4_i_m2[3]\ : MX2C
      port map(A => \raddr[3]\, B => \un2_xaddr[3]\, S => 
        \state2_0[1]_net_1\, Y => N_1620);
    
    \G1_6_P4_raddr[6]\ : DFN1E1C1
      port map(D => N_1652, CLK => CLK_c, CLR => RST_c, E => 
        un54_state, Q => \raddr[6]\);
    
    un3_finished_4 : XNOR2
      port map(A => \wptr[4]_net_1\, B => \waddr[4]_net_1\, Y => 
        un3_finished_4_i_0);
    
    un1_wptr_I_48 : AND2
      port map(A => \wptr[4]_net_1\, B => \wptr[5]_net_1\, Y => 
        \DWACT_ADD_CI_0_pog_array_1_1_1[0]\);
    
    \wdata[4]\ : DFN1E1C1
      port map(D => \wdata[3]_net_1\, CLK => CLK_c, CLR => 
        N_1471_0, E => \state[2]_net_1\, Q => \wdata[4]_net_1\);
    
    un1_wptr_I_39 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_2_1[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_1_1[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_11_1[0]\);
    
    state2_tr12_i_0_a2_0_9 : NOR3
      port map(A => \xaddr[1]_net_1\, B => \xaddr[3]_net_1\, C
         => \xaddr[0]_net_1\, Y => \state2_tr12_i_0_a2_0_9\);
    
    P6_waddr_3_I_47 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => 
        \waddr[4]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_1_0[0]\);
    
    \G1_5_P4_raddr_45_i_m2[5]\ : MX2
      port map(A => DI_c_0, B => I_24, S => \bit_cnt_0[0]_net_1\, 
        Y => N_1610);
    
    P6_start_3_I_27 : XOR2
      port map(A => \start[6]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_11[0]\, Y => \start_3[6]\);
    
    \P12_xaddr_4_i_m2[15]\ : MX2C
      port map(A => \raddr[15]\, B => \un2_xaddr[15]\, S => 
        \state2[1]_net_1\, Y => N_1632);
    
    \G1_10_P4_raddr_85_i_m2_i_m2[10]\ : MX2
      port map(A => I_56, B => DI_c_1, S => \bit_cnt_0[2]_net_1\, 
        Y => N_1657);
    
    \P5_rdata_4_1_0_a2[5]\ : OR2B
      port map(A => \rdata[4]_net_1\, B => N_1522, Y => N_1714);
    
    \xaddr[6]\ : DFN1E1C1
      port map(D => \xaddr_4[6]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[6]_net_1\);
    
    \P12_xaddr_4_r[7]\ : NOR3A
      port map(A => N_1538_0, B => N_1624, C => 
        addr_ld_0_sqmuxa_0, Y => \xaddr_4[7]\);
    
    un1_end_adr_ADD_19x19_slow_I3_CO1 : MAJ3
      port map(A => \raddr[3]\, B => I2_un1_CO1, C => 
        \waddr[3]_net_1\, Y => N215);
    
    \G1_13_P4_raddr[13]\ : DFN1E1C1
      port map(D => N_1614, CLK => CLK_c, CLR => RST_c, E => 
        un103_state, Q => \raddr[13]\);
    
    \P12_xaddr_4_i_m2[11]\ : MX2C
      port map(A => \raddr[11]\, B => \un2_xaddr[11]\, S => 
        \state2[1]_net_1\, Y => N_1628);
    
    un5_ebulk_0_a2_0_a2_1 : OR2
      port map(A => \stat[3]_net_1\, B => \stat[2]_net_1\, Y => 
        N_1742_1);
    
    state2_tr12_i_0_o2_0 : NOR3C
      port map(A => \state2_tr12_i_0_o2_0_1\, B => 
        \state2_tr12_i_0_o2_0_2\, C => \state2_tr12_i_0_o2_0_3\, 
        Y => N_1588_i_0);
    
    \P12_xaddr_4_i_0[17]\ : AOI1
      port map(A => N_1538_0, B => \state2_0[1]_net_1\, C => 
        \raddr[17]\, Y => \xaddr_4_i_0[17]\);
    
    \G1_16_P4_raddr_133_i_m2_i_m2[16]\ : MX2
      port map(A => I_98, B => DI_c_1, S => \bit_cnt[1]_net_1\, Y
         => N_1660);
    
    P6_waddr_3_I_54 : AND2
      port map(A => \waddr[6]_net_1\, B => \waddr[7]_net_1\, Y
         => \DWACT_ADD_CI_0_pog_array_1_2_0[0]\);
    
    GND_i_0 : GND
      port map(Y => GND_net_2);
    
    \P12_xaddr_4_i_m2[8]\ : MX2C
      port map(A => \raddr[8]\, B => \un2_xaddr[8]\, S => 
        \state2[1]_net_1\, Y => N_1625);
    
    \state[7]\ : DFN1P1
      port map(D => \statese_i_0\, CLK => CLK_c, PRE => CSn_c_0, 
        Q => \state[7]_net_1\);
    
    P6_waddr_3_I_49 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => 
        \waddr[2]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_0[0]\);
    
    \addr_i_m2_i_m2_0[18]\ : MX2
      port map(A => \xaddr[18]_net_1\, B => \raddr[18]\, S => 
        \state2_0[9]_net_1\, Y => nvm_addr_0(18));
    
    \last[3]\ : DFN1C1
      port map(D => \un10_i_a2_0_a2_0_a2[2]_net_1\, CLK => CSn_c, 
        CLR => RST_c, Q => \last[3]_net_1\);
    
    \P5_rdata_4_i_0_0[1]\ : AO1D
      port map(A => N_1803, B => \webit\, C => N_1745, Y => 
        \rdata_4_i_0_0[1]\);
    
    \P12_wptr_4_i_m2[4]\ : MX2
      port map(A => I_28, B => \start[4]_net_1\, S => 
        \state2[8]_net_1\, Y => \wptr_4_i_m2[4]\);
    
    state2_tr12_i_0_o2_0_2 : NOR2B
      port map(A => \xaddr[4]_net_1\, B => \xaddr[2]_net_1\, Y
         => \state2_tr12_i_0_o2_0_2\);
    
    \state2_ns_i_a2_i_0_0[9]\ : AOI1B
      port map(A => nvm_busy, B => 
        \state2_ns_i_a2_i_0_a2_0[9]_net_1\, C => N_1739, Y => 
        \state2_ns_i_a2_i_0_0[9]_net_1\);
    
    un1_end_adr_ADD_19x19_slow_I6_un1_CO1 : MAJ3
      port map(A => \raddr[6]\, B => N219, C => \waddr[6]_net_1\, 
        Y => I6_un1_CO1_0);
    
    G1_0_P4_un12_state_0_0_a2_0 : NOR2B
      port map(A => \state[4]_net_1\, B => N_1783_0, Y => 
        un12_state_0_0_a2_0);
    
    \P12_xaddr_4_i_0[16]\ : AOI1
      port map(A => N_1538_0, B => \state2_0[1]_net_1\, C => 
        \raddr[16]\, Y => \xaddr_4_i_0[16]\);
    
    state_tr0_3_a2_0 : OR3
      port map(A => N_1525, B => \cmnd[2]_net_1\, C => N_1770_1, 
        Y => N_1776);
    
    \P12_xaddr_4_i_m2[1]\ : MX2C
      port map(A => \raddr[1]\, B => \un2_xaddr[1]\, S => 
        \state2_0[1]_net_1\, Y => N_1618);
    
    \state2_ns_i_a2_0_a2_0_a2[0]\ : AO1A
      port map(A => \wip\, B => \state2_0[9]_net_1\, C => 
        \state2[0]_net_1\, Y => 
        \state2_ns_i_a2_0_a2_0_a2[0]_net_1\);
    
    \G1_7_P4_raddr[7]\ : DFN1E1C1
      port map(D => N_1611, CLK => CLK_c, CLR => RST_c, E => 
        un61_state, Q => \raddr[7]\);
    
    P6_un21_rstn_i_a2_i_0 : OR2
      port map(A => \state2[0]_net_1\, B => RST_c, Y => N_1471_0);
    
    \G1_12_P4_raddr_101_i_m2_i_m2[12]\ : MX2
      port map(A => I_73, B => DI_c_1, S => \bit_cnt[1]_net_1\, Y
         => N_1658);
    
    \rdata[4]\ : DFN0C1
      port map(D => \rdata_4_i_0[4]\, CLK => CLK_c, CLR => 
        CSn_c_1, Q => \rdata[4]_net_1\);
    
    \P12_xaddr_4_i_m2[13]\ : MX2C
      port map(A => \raddr[13]\, B => \un2_xaddr[13]\, S => 
        \state2[1]_net_1\, Y => N_1630);
    
    un2_xaddr_ADD_19x19_slow_I1_S : XNOR2
      port map(A => \xaddr[1]_net_1\, B => I0_un1_CO1_0, Y => 
        \un2_xaddr[1]\);
    
    \state2_0[1]\ : DFN1C1
      port map(D => N_465_i_0, CLK => clk60M, CLR => RST_c, Q => 
        \state2_0[1]_net_1\);
    
    \state2[4]\ : DFN1C1
      port map(D => \state2_tr11_i_0\, CLK => clk60M, CLR => 
        RST_c, Q => \nvm_erase\);
    
    \P12_xaddr_4_r[12]\ : NOR3A
      port map(A => N_1538, B => N_1629, C => addr_ld_0_sqmuxa, Y
         => \xaddr_4[12]\);
    
    G1_3_P4_un33_state_0_0_a2_0 : NOR2A
      port map(A => \state_0[4]_net_1\, B => \bit_cnt_0[0]_net_1\, 
        Y => un33_state_0_0_a2_0);
    
    un2_xaddr_ADD_19x19_slow_I9_CO1 : OR3B
      port map(A => \xaddr[8]_net_1\, B => \xaddr[9]_net_1\, C
         => N220_1, Y => N226);
    
    un1_wptr_I_1 : AND2
      port map(A => \wptr[0]_net_1\, B => \state2[1]_net_1\, Y
         => \DWACT_ADD_CI_0_TMP_1[0]\);
    
    state_tr8_0_a2_0_o2 : OR2
      port map(A => \cmnd[0]_net_1\, B => N_1523, Y => N_1528);
    
    P6_waddr_3_I_34 : XOR2
      port map(A => \waddr[7]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12_2_0[0]\, Y => \waddr_3[7]\);
    
    un2_xaddr_ADD_19x19_slow_I4_S : AX1
      port map(A => I2_un1_CO1_0, B => \xaddr[3]_net_1\, C => 
        \xaddr[4]_net_1\, Y => \un2_xaddr[4]\);
    
    \wptr[0]\ : DFN1C1
      port map(D => \wptr_4_i_m2[0]\, CLK => clk60M, CLR => RST_c, 
        Q => \wptr[0]_net_1\);
    
    un2_xaddr_ADD_19x19_slow_I12_S : XNOR2
      port map(A => \xaddr[12]_net_1\, B => N234, Y => 
        \un2_xaddr[12]\);
    
    \P5_rdata_4_i_0_a2[4]\ : NOR2A
      port map(A => N_1522, B => \rdata[3]_net_1\, Y => N_1756);
    
    \cmnd[3]\ : DFN1E1C1
      port map(D => \cmnd[2]_net_1\, CLK => CLK_c, CLR => RST_c, 
        E => \state[7]_net_1\, Q => \cmnd[3]_net_1\);
    
    un2_idis_0_o2 : NOR2
      port map(A => N_1557, B => N_1528, Y => \un2_idis_0_o2\);
    
    \start[4]\ : DFN1C1
      port map(D => \start_3[4]\, CLK => CLK_c, CLR => N_1471_0, 
        Q => \start[4]_net_1\);
    
    G1_6_P4_un54_state_0_a2_0_a2 : OA1B
      port map(A => \state[3]_net_1\, B => \state_0[4]_net_1\, C
         => N_1922, Y => un54_state);
    
    \P5_rdata_4_2_0_a2_0_0[0]\ : OA1A
      port map(A => nvm_busy, B => \wip\, C => \cmnd[2]_net_1\, Y
         => \rdata_4_2_0_a2_0[0]\);
    
    \rdata[3]\ : DFN0C1
      port map(D => \rdata_4[3]\, CLK => CLK_c, CLR => CSn_c_1, Q
         => \rdata[3]_net_1\);
    
    P9_wip_1_0_a2_0_a2 : OA1B
      port map(A => N_1582, B => \wip\, C => \state2[0]_net_1\, Y
         => wip_1);
    
    \state2_ns_i_a2_0_0_a2_5_1[8]\ : NOR2B
      port map(A => \xaddr[16]_net_1\, B => \xaddr[17]_net_1\, Y
         => \state2_ns_i_a2_0_0_a2_5_1[8]_net_1\);
    
    G1_2_P4_un26_state_0_0_a2_0 : NOR3B
      port map(A => \bit_cnt[0]_net_1\, B => \bit_cnt[2]_net_1\, 
        C => \bit_cnt[1]_net_1\, Y => N_1806);
    
    P9_swrite_1_0_0_a2_1_0 : NOR3B
      port map(A => N_1551, B => dly_write_i, C => N_897_3, Y => 
        swrite_1_0_0_a2_1);
    
    un1_inc_I_5 : XOR2
      port map(A => \raddr[0]\, B => \raddr[1]\, Y => I_5);
    
    un1_inc_I_111 : AND3
      port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C
         => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\);
    
    \G1_14_P4_raddr_117_i_m2_i_m2[14]\ : MX2
      port map(A => I_84, B => DI_c, S => \state[5]_net_1\, Y => 
        N_1659);
    
    \G1_18_P4_raddr[18]\ : DFN1E1C1
      port map(D => N_1661, CLK => CLK_c, CLR => RST_c, E => 
        un138_state, Q => \raddr[18]\);
    
    \xaddr[17]\ : DFN1E1C1
      port map(D => \xaddr_4[17]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[17]_net_1\);
    
    wip : DFN1C1
      port map(D => wip_1, CLK => clk60M, CLR => RST_c, Q => 
        \wip\);
    
    un1_inc_I_65 : AND3
      port map(A => \DWACT_FINC_E[6]\, B => \raddr[9]\, C => 
        \raddr[10]\, Y => N_39);
    
    \G1_2_P4_raddr[2]\ : DFN1E1C1
      port map(D => N_1654, CLK => CLK_c, CLR => RST_c, E => 
        un26_state, Q => \raddr[2]\);
    
    \P12_xaddr_4_r[11]\ : NOR3A
      port map(A => N_1538, B => N_1628, C => addr_ld_0_sqmuxa, Y
         => \xaddr_4[11]\);
    
    \G1_10_P4_raddr[10]\ : DFN1E1C1
      port map(D => N_1657, CLK => CLK_c, CLR => RST_c, E => 
        N_1486, Q => \raddr[10]\);
    
    \G1_0_P4_raddr[0]\ : DFN1C1
      port map(D => raddr_0_21, CLK => CLK_c, CLR => RST_c, Q => 
        \raddr[0]\);
    
    P9_sbulk_1_0_0_a2 : OR2A
      port map(A => \sbulk\, B => \state2[0]_net_1\, Y => N_1687);
    
    \P12_xaddr_4_i_m2[0]\ : MX2C
      port map(A => \raddr[0]\, B => \un2_xaddr[0]\, S => 
        \state2_0[1]_net_1\, Y => N_1617);
    
    \xaddr[16]\ : DFN1E1C1
      port map(D => \xaddr_4[16]\, CLK => clk60M, CLR => RST_c, E
         => N_1371, Q => \xaddr[16]_net_1\);
    
    \G1_18_P4_raddr_149_i_m2_i_m2[18]\ : MX2
      port map(A => I_115, B => DI_c, S => \bit_cnt[2]_net_1\, Y
         => N_1661);
    
    \P12_xaddr_4_r[9]\ : NOR3A
      port map(A => N_1538, B => N_1626, C => addr_ld_0_sqmuxa_0, 
        Y => \xaddr_4[9]\);
    
    \P12_xaddr_4_i_o2_0[0]\ : OR2A
      port map(A => \state2_0[8]_net_1\, B => N_1534, Y => 
        N_1538_0);
    
    state2_tr12_i_0 : NOR3
      port map(A => N_1729, B => \state2_tr12_i_0_0\, C => N_1572, 
        Y => \state2_tr12_i_0\);
    
    state2_tr12_i_0_a2_0_5 : NOR2
      port map(A => \xaddr[17]_net_1\, B => \xaddr[15]_net_1\, Y
         => \state2_tr12_i_0_a2_0_5\);
    
    state2_tr11_i_0_o2 : OR2
      port map(A => \ssector\, B => \sbulk\, Y => N_1552);
    
    VCC_i_0 : VCC
      port map(Y => VCC_net_2);
    
    \G1_13_P4_raddr_109_i_m2[13]\ : MX2
      port map(A => DI_c, B => I_77, S => \bit_cnt[0]_net_1\, Y
         => N_1614);
    
    P6_waddr_3_I_42 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_1_0[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_11_0[0]\);
    
    \state[3]\ : DFN1E1C1
      port map(D => N_1175, CLK => CLK_c, CLR => CSn_c_0, E => 
        N_1783, Q => \state[3]_net_1\);
    
    \state2_ns_i_a2_i_0_a2_7_5[9]\ : NOR3C
      port map(A => un3_finished_0_i_0, B => un3_finished_1_i_0, 
        C => \state2_ns_i_a2_i_0_a2_7_3[9]_net_1\, Y => 
        \state2_ns_i_a2_i_0_a2_7_5[9]_net_1\);
    
    \G1_3_P4_raddr_29_i_m2[3]\ : MX2
      port map(A => DI_c_0, B => I_13, S => \bit_cnt_0[0]_net_1\, 
        Y => N_1609);
    
    un1_wptr_I_19 : XOR2
      port map(A => \wptr[0]_net_1\, B => \state2[1]_net_1\, Y
         => \DWACT_ADD_CI_0_partial_sum[0]\);
    
    \state_ns_i_a2_0_0_2[7]\ : AOI1B
      port map(A => N_1697_1, B => \state_ns_i_a2_0_0_a2_0[7]\, C
         => \state_ns_i_a2_0_0_1[7]_net_1\, Y => 
        \state_ns_i_a2_0_0_2[7]_net_1\);
    
    state2_tr12_i_0_a2_0_0 : NOR2
      port map(A => \xaddr[18]_net_1\, B => \xaddr[16]_net_1\, Y
         => \state2_tr12_i_0_a2_0_0\);
    
    un2_iena_0_a2_0 : OR2A
      port map(A => \cmnd[1]_net_1\, B => \cmnd[5]_net_1\, Y => 
        N_1771);
    
    un1_inc_I_34 : AND3
      port map(A => \raddr[3]\, B => \raddr[4]\, C => \raddr[5]\, 
        Y => \DWACT_FINC_E[2]\);
    
    \state2[6]\ : DFN1C1
      port map(D => \state2_ns_i_a2_i_0[3]_net_1\, CLK => clk60M, 
        CLR => RST_c, Q => \state2[6]_net_1\);
    
    \P5_rdata_4_1_0_a2[7]\ : OR2B
      port map(A => \rdata[6]_net_1\, B => N_1522, Y => N_1718);
    
    un8_nxt2_i_a2_i_0 : OR2
      port map(A => \state2_0[8]_net_1\, B => \state2_0[1]_net_1\, 
        Y => N_1371_0);
    
    un6_ewrite_i_0 : OR3B
      port map(A => N_897_2, B => \un6_ewrite_i_0_1\, C => N_1662, 
        Y => N_897_i_0);
    
    un1_inc_I_105 : XOR2
      port map(A => N_11, B => \raddr[17]\, Y => I_105);
    
    state_tr8_0_a2_0_a2_1 : OR3B
      port map(A => \state_0[7]_net_1\, B => DI_c_0, C => N_1528, 
        Y => \state_tr8_0_a2_0_a2_1\);
    
    P6_waddr_3_I_38 : XOR2
      port map(A => \waddr[6]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_11_0[0]\, Y => \waddr_3[6]\);
    
    un2_iena_0_o2 : OR2A
      port map(A => N_1546, B => N_1525, Y => N_1557);
    
    P6_waddr_3_I_36 : XOR2
      port map(A => \waddr[8]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_3[0]\, Y => \waddr_3[8]\);
    
    \cmnd[1]\ : DFN1E1C1
      port map(D => \cmnd[0]_net_1\, CLK => CLK_c, CLR => RST_c, 
        E => \state[7]_net_1\, Q => \cmnd[1]_net_1\);
    
    VCC_i : VCC
      port map(Y => VCC_net_1);
    
    un2_xaddr_ADD_19x19_slow_I17_CO1 : OR2B
      port map(A => \xaddr[17]_net_1\, B => I16_un1_CO1, Y => 
        N258);
    
    \state_ns_i_a2_0_0_a2_10[7]\ : OR3A
      port map(A => \cmnd[2]_net_1\, B => \cmnd[3]_net_1\, C => 
        \cmnd[4]_net_1\, Y => N_1798);
    
    \state2[0]\ : DFN1C1
      port map(D => \state2_ns_i_a2_i_0[9]_net_1\, CLK => clk60M, 
        CLR => RST_c, Q => \state2[0]_net_1\);
    
    \wptr[1]\ : DFN1C1
      port map(D => \wptr_4_i_m2[1]\, CLK => clk60M, CLR => RST_c, 
        Q => \wptr[1]_net_1\);
    
    \wdata[5]\ : DFN1E1C1
      port map(D => \wdata[4]_net_1\, CLK => CLK_c, CLR => 
        N_1471_0, E => \state[2]_net_1\, Q => \wdata[5]_net_1\);
    
    G1_0_P4_un12_state_0_0_a2 : OR2A
      port map(A => \state[3]_net_1\, B => N_1922, Y => N_1669);
    
    un5_esector_i_0_o2_7 : OR2A
      port map(A => \cmnd[3]_net_1\, B => \cmnd[2]_net_1\, Y => 
        N_1530);
    
    statese_i_0_a2 : NOR3C
      port map(A => \bit_cnt[0]_net_1\, B => \bit_cnt[2]_net_1\, 
        C => \bit_cnt[1]_net_1\, Y => N_1783);
    
    \wdata[1]\ : DFN1E1C1
      port map(D => \wdata[0]_net_1\, CLK => CLK_c, CLR => 
        N_1471_0, E => \state[2]_net_1\, Q => \wdata[1]_net_1\);
    
    G1_11_P4_un89_state_i_i : AO1B
      port map(A => N_1753_1, B => un89_state_i_i_a2_0, C => 
        N_1669, Y => N_1488);
    
    \addr_i_m2_i_m2[12]\ : MX2
      port map(A => \xaddr[12]_net_1\, B => \raddr[12]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(12));
    
    \G1_15_P4_raddr_125_i_m2[15]\ : MX2
      port map(A => DI_c_1, B => I_91, S => \bit_cnt[0]_net_1\, Y
         => N_1615);
    
    un2_xaddr_ADD_19x19_slow_I16_un1_CO1 : NOR2A
      port map(A => \xaddr[16]_net_1\, B => N250, Y => 
        I16_un1_CO1);
    
    \state2_ns_i_a2_i_0_a2_4[9]\ : NOR3C
      port map(A => \state2_ns_i_a2_i_0_a2_7_5[9]_net_1\, B => 
        \state2_ns_i_a2_i_0_a2_7_6[9]_net_1\, C => 
        \state2[6]_net_1\, Y => N_1804);
    
    \start[7]\ : DFN1C1
      port map(D => \start_3[7]\, CLK => CLK_c, CLR => 
        un21_rstn_i_a2_i, Q => \start[7]_net_1\);
    
    un1_end_adr_ADD_19x19_slow_I1_CO1 : MAJ3
      port map(A => \raddr[1]\, B => I0_un1_CO1, C => 
        \waddr[1]_net_1\, Y => N211);
    
    \state2_ns_i_a2_i_0_a2_0[9]\ : OR3B
      port map(A => N_1927_tz, B => \state2[5]_net_1\, C => 
        N_1572, Y => N_1738);
    
    P6_start_3_I_34 : XOR2
      port map(A => \start[7]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => \start_3[7]\);
    
    G1_4_P4_un40_state_0_0_m2 : MX2C
      port map(A => \state[3]_net_1\, B => \state[4]_net_1\, S
         => \bit_cnt_0[1]_net_1\, Y => N_1599);
    
    un2_xaddr_ADD_19x19_slow_I9_S : AX1
      port map(A => N220_1, B => \xaddr[8]_net_1\, C => 
        \xaddr[9]_net_1\, Y => \un2_xaddr[9]\);
    
    \state2_ns_i_a2_0_0_o2_0[8]\ : AO1
      port map(A => \state2_ns_i_a2_0_0_a2_5_0[8]_net_1\, B => 
        \state2_ns_i_a2_0_0_a2_5_1[8]_net_1\, C => \ssector\, Y
         => \state2_ns_i_a2_0_0_o2_0[8]_net_1\);
    
    \stat[0]\ : DFN1E1P1
      port map(D => DI_c, CLK => CLK_c, PRE => RST_c, E => 
        \state[1]_net_1\, Q => \stat[0]_net_1\);
    
    un1_inc_I_31 : XOR2
      port map(A => N_64, B => \raddr[6]\, Y => I_31);
    
    \P12_xaddr_4_r[17]\ : NOR3
      port map(A => N_1723, B => \xaddr_4_i_0[17]\, C => 
        addr_ld_0_sqmuxa, Y => \xaddr_4[17]\);
    
    \xaddr[9]\ : DFN1E1C1
      port map(D => \xaddr_4[9]\, CLK => clk60M, CLR => RST_c, E
         => N_1371_0, Q => \xaddr[9]_net_1\);
    
    state2_tr12_i_0_a2_0_12 : NOR3A
      port map(A => \state2_tr12_i_0_a2_0_7\, B => 
        \xaddr[2]_net_1\, C => \xaddr[4]_net_1\, Y => 
        \state2_tr12_i_0_a2_0_12\);
    
    \state2_ns_i_a2_0_0_a2_5_0[8]\ : NOR2B
      port map(A => \sbulk\, B => \xaddr[18]_net_1\, Y => 
        \state2_ns_i_a2_0_0_a2_5_0[8]_net_1\);
    
    un1_end_adr_ADD_19x19_slow_I4_un1_CO1 : MAJ3
      port map(A => \raddr[4]\, B => N215, C => \waddr[4]_net_1\, 
        Y => I4_un1_CO1);
    
    iwebit_1_0_a2_0 : OR3A
      port map(A => wena_dly_i, B => \iwebit_1_0_a2_0_0\, C => 
        \state2[0]_net_1\, Y => N_1690);
    
    \G1_11_P4_raddr_93_i_m2[11]\ : MX2
      port map(A => DI_c, B => I_66, S => \bit_cnt[0]_net_1\, Y
         => N_1613);
    
    \bit_cnt[0]\ : DFN1C1
      port map(D => \bit_cnt_i[0]_net_1\, CLK => CLK_c, CLR => 
        CSn_c, Q => \bit_cnt[0]_net_1\);
    
    webit : DFN1C1
      port map(D => iwebit_1, CLK => clk60M, CLR => RST_c, Q => 
        \webit\);
    
    un1_wptr_I_30 : XOR2
      port map(A => \wptr[3]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_12_3[0]\, Y => I_30);
    
    un3_finished_0 : XNOR2
      port map(A => \wptr[0]_net_1\, B => \waddr[0]_net_1\, Y => 
        un3_finished_0_i_0);
    
    \G1_1_P4_raddr[1]\ : DFN1E1C1
      port map(D => N_1608, CLK => CLK_c, CLR => RST_c, E => 
        un19_state, Q => \raddr[1]\);
    
    \P12_xaddr_4_i_a2[17]\ : XA1C
      port map(A => I16_un1_CO1, B => \xaddr[17]_net_1\, C => 
        N_1926, Y => N_1723);
    
    \G1_11_P4_raddr[11]\ : DFN1E1C1
      port map(D => N_1613, CLK => CLK_c, CLR => RST_c, E => 
        N_1488, Q => \raddr[11]\);
    
    un1_inc_I_55 : AND3
      port map(A => \DWACT_FINC_E[4]\, B => \raddr[8]\, C => 
        \raddr[9]\, Y => N_46);
    
    un1_inc_I_51 : NOR2B
      port map(A => \raddr[8]\, B => \DWACT_FINC_E[4]\, Y => N_49);
    
    un2_bit_cnt_1_SUM1 : XOR2
      port map(A => \bit_cnt_0[1]_net_1\, B => 
        \bit_cnt_0[0]_net_1\, Y => SUM1);
    
    \addr_i_m2_i_m2[10]\ : MX2
      port map(A => \xaddr[10]_net_1\, B => \raddr[10]\, S => 
        \state2[9]_net_1\, Y => nvm_addr(10));
    
    un2_xaddr_ADD_19x19_slow_I11_S : AX1
      port map(A => N226, B => \xaddr[10]_net_1\, C => 
        \xaddr[11]_net_1\, Y => \un2_xaddr[11]\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;

entity rc_osc is

    port( clk100M : out   std_logic
        );

end rc_osc;

architecture DEF_ARCH of rc_osc is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component RCOSC
    port( CLKOUT : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \VCC\, \GND\, GND_net_1, VCC_net_1 : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    RCOSC1 : RCOSC
      port map(CLKOUT => clk100M);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;

entity config_top is

    port( RST : in    std_logic;
          CSn : in    std_logic;
          CLK : in    std_logic;
          DI  : in    std_logic;
          DO  : out   std_logic
        );

end config_top;

architecture DEF_ARCH of config_top is 

  component NVM_2_blocks
    port( nvm_din    : in    std_logic_vector(7 downto 0) := (others => 'U');
          nvm_addr   : in    std_logic_vector(18 downto 0) := (others => 'U');
          nvm_dout   : out   std_logic_vector(7 downto 0);
          nvm_addr_0 : in    std_logic_vector(18 to 18) := (others => 'U');
          \GND\      : in    std_logic := 'U';
          clk60M     : in    std_logic := 'U';
          nvm_read   : in    std_logic := 'U';
          RST_c_i    : in    std_logic := 'U';
          nvm_busy   : out   std_logic;
          nvm_we     : in    std_logic := 'U';
          nvm_pgm    : in    std_logic := 'U';
          nvm_erase  : in    std_logic := 'U'
        );
  end component;

  component CLKBUF
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component INBUF
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component INV
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component BUFF
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component PLL_60_40_10
    port( RST_c_i : in    std_logic := 'U';
          \VCC\   : in    std_logic := 'U';
          \GND\   : in    std_logic := 'U';
          clk100M : in    std_logic := 'U';
          clk60M  : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component sconfig
    port( nvm_din          : out   std_logic_vector(7 downto 0);
          nvm_addr         : out   std_logic_vector(18 downto 0);
          nvm_dout         : in    std_logic_vector(7 downto 0) := (others => 'U');
          nvm_addr_0       : out   std_logic_vector(18 to 18);
          rdata_7          : out   std_logic;
          \VCC\            : in    std_logic := 'U';
          \GND\            : in    std_logic := 'U';
          RST_c_i          : in    std_logic := 'U';
          CSn_c            : in    std_logic := 'U';
          CSn_c_1          : in    std_logic := 'U';
          nvm_pgm          : out   std_logic;
          un5_do_0_a2_2_a2 : out   std_logic;
          DI_c             : in    std_logic := 'U';
          DI_c_1           : in    std_logic := 'U';
          nvm_read         : out   std_logic;
          nvm_we           : out   std_logic;
          nvm_erase        : out   std_logic;
          DI_c_0           : in    std_logic := 'U';
          nvm_busy         : in    std_logic := 'U';
          CSn_c_0          : in    std_logic := 'U';
          CSn_c_0_0        : in    std_logic := 'U';
          CLK_c            : in    std_logic := 'U';
          RST_c            : in    std_logic := 'U';
          clk60M           : in    std_logic := 'U'
        );
  end component;

  component TRIBUFF
    port( D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component rc_osc
    port( clk100M : out   std_logic
        );
  end component;

    signal CSn_c_0_0, CSn_c, CSn_c_1, CSn_c_0, DI_c_1, DI_c, 
        DI_c_0, RST_c, CLK_c, \RST_c_i\, \U1.rdata[7]\, 
        un5_do_0_a2_2_a2, clk100M, \VCC\, \GND\, clk60M, 
        \nvm_din[0]\, \nvm_din[1]\, \nvm_din[2]\, \nvm_din[3]\, 
        \nvm_din[4]\, \nvm_din[5]\, \nvm_din[6]\, \nvm_din[7]\, 
        \nvm_addr[0]\, \nvm_addr[1]\, \nvm_addr[2]\, 
        \nvm_addr[3]\, \nvm_addr[4]\, \nvm_addr[5]\, 
        \nvm_addr[6]\, \nvm_addr[7]\, \nvm_addr[8]\, 
        \nvm_addr[9]\, \nvm_addr[10]\, \nvm_addr[11]\, 
        \nvm_addr[12]\, \nvm_addr[13]\, \nvm_addr[14]\, 
        \nvm_addr[15]\, \nvm_addr[16]\, \nvm_addr[17]\, 
        \nvm_addr[18]\, \nvm_dout[0]\, \nvm_dout[1]\, 
        \nvm_dout[2]\, \nvm_dout[3]\, \nvm_dout[4]\, 
        \nvm_dout[5]\, \nvm_dout[6]\, \nvm_dout[7]\, 
        \nvm_addr_0[18]\, nvm_pgm, nvm_read, nvm_we, nvm_erase, 
        nvm_busy, GND_net_1, VCC_net_1 : std_logic;

    for all : NVM_2_blocks
	Use entity work.NVM_2_blocks(DEF_ARCH);
    for all : PLL_60_40_10
	Use entity work.PLL_60_40_10(DEF_ARCH);
    for all : sconfig
	Use entity work.sconfig(DEF_ARCH);
    for all : rc_osc
	Use entity work.rc_osc(DEF_ARCH);
begin 


    U2 : NVM_2_blocks
      port map(nvm_din(7) => \nvm_din[7]\, nvm_din(6) => 
        \nvm_din[6]\, nvm_din(5) => \nvm_din[5]\, nvm_din(4) => 
        \nvm_din[4]\, nvm_din(3) => \nvm_din[3]\, nvm_din(2) => 
        \nvm_din[2]\, nvm_din(1) => \nvm_din[1]\, nvm_din(0) => 
        \nvm_din[0]\, nvm_addr(18) => \nvm_addr[18]\, 
        nvm_addr(17) => \nvm_addr[17]\, nvm_addr(16) => 
        \nvm_addr[16]\, nvm_addr(15) => \nvm_addr[15]\, 
        nvm_addr(14) => \nvm_addr[14]\, nvm_addr(13) => 
        \nvm_addr[13]\, nvm_addr(12) => \nvm_addr[12]\, 
        nvm_addr(11) => \nvm_addr[11]\, nvm_addr(10) => 
        \nvm_addr[10]\, nvm_addr(9) => \nvm_addr[9]\, nvm_addr(8)
         => \nvm_addr[8]\, nvm_addr(7) => \nvm_addr[7]\, 
        nvm_addr(6) => \nvm_addr[6]\, nvm_addr(5) => 
        \nvm_addr[5]\, nvm_addr(4) => \nvm_addr[4]\, nvm_addr(3)
         => \nvm_addr[3]\, nvm_addr(2) => \nvm_addr[2]\, 
        nvm_addr(1) => \nvm_addr[1]\, nvm_addr(0) => 
        \nvm_addr[0]\, nvm_dout(7) => \nvm_dout[7]\, nvm_dout(6)
         => \nvm_dout[6]\, nvm_dout(5) => \nvm_dout[5]\, 
        nvm_dout(4) => \nvm_dout[4]\, nvm_dout(3) => 
        \nvm_dout[3]\, nvm_dout(2) => \nvm_dout[2]\, nvm_dout(1)
         => \nvm_dout[1]\, nvm_dout(0) => \nvm_dout[0]\, 
        nvm_addr_0(18) => \nvm_addr_0[18]\, \GND\ => \GND\, 
        clk60M => clk60M, nvm_read => nvm_read, RST_c_i => 
        \RST_c_i\, nvm_busy => nvm_busy, nvm_we => nvm_we, 
        nvm_pgm => nvm_pgm, nvm_erase => nvm_erase);
    
    CLK_pad : CLKBUF
      port map(PAD => CLK, Y => CLK_c);
    
    DI_pad : INBUF
      port map(PAD => DI, Y => DI_c);
    
    RST_c_i : INV
      port map(A => RST_c, Y => \RST_c_i\);
    
    DI_pad_1 : BUFF
      port map(A => DI_c, Y => DI_c_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    CSn_pad_1 : BUFF
      port map(A => CSn_c_0_0, Y => CSn_c_1);
    
    RST_pad : CLKBUF
      port map(PAD => RST, Y => RST_c);
    
    C2 : PLL_60_40_10
      port map(RST_c_i => \RST_c_i\, \VCC\ => \VCC\, \GND\ => 
        \GND\, clk100M => clk100M, clk60M => clk60M);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    U1 : sconfig
      port map(nvm_din(7) => \nvm_din[7]\, nvm_din(6) => 
        \nvm_din[6]\, nvm_din(5) => \nvm_din[5]\, nvm_din(4) => 
        \nvm_din[4]\, nvm_din(3) => \nvm_din[3]\, nvm_din(2) => 
        \nvm_din[2]\, nvm_din(1) => \nvm_din[1]\, nvm_din(0) => 
        \nvm_din[0]\, nvm_addr(18) => \nvm_addr[18]\, 
        nvm_addr(17) => \nvm_addr[17]\, nvm_addr(16) => 
        \nvm_addr[16]\, nvm_addr(15) => \nvm_addr[15]\, 
        nvm_addr(14) => \nvm_addr[14]\, nvm_addr(13) => 
        \nvm_addr[13]\, nvm_addr(12) => \nvm_addr[12]\, 
        nvm_addr(11) => \nvm_addr[11]\, nvm_addr(10) => 
        \nvm_addr[10]\, nvm_addr(9) => \nvm_addr[9]\, nvm_addr(8)
         => \nvm_addr[8]\, nvm_addr(7) => \nvm_addr[7]\, 
        nvm_addr(6) => \nvm_addr[6]\, nvm_addr(5) => 
        \nvm_addr[5]\, nvm_addr(4) => \nvm_addr[4]\, nvm_addr(3)
         => \nvm_addr[3]\, nvm_addr(2) => \nvm_addr[2]\, 
        nvm_addr(1) => \nvm_addr[1]\, nvm_addr(0) => 
        \nvm_addr[0]\, nvm_dout(7) => \nvm_dout[7]\, nvm_dout(6)
         => \nvm_dout[6]\, nvm_dout(5) => \nvm_dout[5]\, 
        nvm_dout(4) => \nvm_dout[4]\, nvm_dout(3) => 
        \nvm_dout[3]\, nvm_dout(2) => \nvm_dout[2]\, nvm_dout(1)
         => \nvm_dout[1]\, nvm_dout(0) => \nvm_dout[0]\, 
        nvm_addr_0(18) => \nvm_addr_0[18]\, rdata_7 => 
        \U1.rdata[7]\, \VCC\ => \VCC\, \GND\ => \GND\, RST_c_i
         => \RST_c_i\, CSn_c => CSn_c, CSn_c_1 => CSn_c_1, 
        nvm_pgm => nvm_pgm, un5_do_0_a2_2_a2 => un5_do_0_a2_2_a2, 
        DI_c => DI_c, DI_c_1 => DI_c_1, nvm_read => nvm_read, 
        nvm_we => nvm_we, nvm_erase => nvm_erase, DI_c_0 => 
        DI_c_0, nvm_busy => nvm_busy, CSn_c_0 => CSn_c_0, 
        CSn_c_0_0 => CSn_c_0_0, CLK_c => CLK_c, RST_c => RST_c, 
        clk60M => clk60M);
    
    GND_i : GND
      port map(Y => \GND\);
    
    CSn_pad_0 : BUFF
      port map(A => CSn_c_0_0, Y => CSn_c_0);
    
    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    DO_pad : TRIBUFF
      port map(D => \U1.rdata[7]\, E => un5_do_0_a2_2_a2, PAD => 
        DO);
    
    CSn_pad_0_0 : BUFF
      port map(A => CSn_c, Y => CSn_c_0_0);
    
    C1 : rc_osc
      port map(clk100M => clk100M);
    
    CSn_pad : INBUF
      port map(PAD => CSn, Y => CSn_c);
    
    DI_pad_0 : BUFF
      port map(A => DI_c, Y => DI_c_0);
    

end DEF_ARCH; 
