#Build: Synplify Pro 9.4A1, Build 169R, Jun 11 2008 #install: D:\Software\Libero\Libero_v8.4\Synplify\synplify_94A1 #OS: Windows XP 5.1 #Hostname: WXP-ALIMS #Implementation: synthesis #Wed Mar 25 16:47:05 2009 $ Start of Compile #Wed Mar 25 16:47:05 2009 Synplicity VHDL Compiler, version 1.0, Build 061R, built Jun 30 2008 Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns Top entity isn't set yet! VHDL syntax check successful! File D:\Appsnotes\2009\SPI_to_I2C\Designs\SPI_I2C\hdl\my_spi_slave_32.vhd changed - recompiling File D:\Appsnotes\2009\SPI_to_I2C\Designs\SPI_I2C\hdl\TinyI2C_master.vhd changed - recompiling File D:\Appsnotes\2009\SPI_to_I2C\Designs\SPI_I2C\hdl\Top_spi_i2c.vhd changed - recompiling File D:\Appsnotes\2009\SPI_to_I2C\Designs\SPI_I2C\hdl\my_spi_slave_32.vhd changed - recompiling File D:\Appsnotes\2009\SPI_to_I2C\Designs\SPI_I2C\hdl\TinyI2C_master.vhd changed - recompiling File D:\Appsnotes\2009\SPI_to_I2C\Designs\SPI_I2C\hdl\Top_spi_i2c.vhd changed - recompiling @N:CD630 : Top_spi_i2c.vhd(33) | Synthesizing work.top_spi_i2c.def_arch @N:CD231 : Top_spi_i2c.vhd(104) | Using onehot encoding for type i2c_state_type (i2c_idle="10000") @N:CD630 : TinyI2C_master.vhd(30) | Synthesizing work.tinyi2c_master.behave @N:CD231 : TinyI2C_master.vhd(70) | Using onehot encoding for type i2c_states (i2c_idle="10000000000") @N:CD630 : iglooplus.vhd(3000) | Synthesizing iglooplus.clkint.syn_black_box Post processing for iglooplus.clkint.syn_black_box @N:CD630 : iglooplus.vhd(3475) | Synthesizing iglooplus.bibuf_lvcmos12u.syn_black_box Post processing for iglooplus.bibuf_lvcmos12u.syn_black_box Post processing for work.tinyi2c_master.behave @W:CL111 : TinyI2C_master.vhd(178) | All reachable assignments to sync_i2c_status(5) assign '0', register removed by optimization @W:CL208 : TinyI2C_master.vhd(178) | All reachable assignments to bit 5 of sync_i2c_status(7 downto 0) assign 0, register removed by optimization @N:CD630 : my_spi_slave_32.vhd(28) | Synthesizing work.my_spi_slave_32.default Post processing for work.my_spi_slave_32.default Post processing for work.top_spi_i2c.def_arch @W:CL169 : Top_spi_i2c.vhd(230) | Pruning Register state_i2c_proc.num_of_data_5(3 downto 0) @W:CL169 : Top_spi_i2c.vhd(176) | Pruning Register send_i2c_status @W:CL169 : Top_spi_i2c.vhd(176) | Pruning Register send_read_data @A: : Top_spi_i2c.vhd(220) | Feedback mux created for signal i2c_rx_data_15_8[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : Top_spi_i2c.vhd(220) | Feedback mux created for signal i2c_rx_data_7_0[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(16) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(17) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(18) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(19) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(20) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(21) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(22) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(23) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(24) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(25) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(26) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(27) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(28) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(29) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(30) to a constant 0 @W:CL190 : Top_spi_i2c.vhd(176) | Optimizing register bit spi_tx_data(31) to a constant 0 @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <31> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <30> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <29> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <28> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <27> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <26> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <25> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <24> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <23> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <22> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <21> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <20> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <19> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <18> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <17> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c.vhd(176) | Pruning Register bit <16> of spi_tx_data(31 downto 0) @N:CL177 : TinyI2C_master.vhd(178) | Sharing sequential element sync_next_addr. @N:CL201 : TinyI2C_master.vhd(499) | Trying to extract state machine for register i2c_presstate Extracted state machine for register i2c_presstate State machine has 11 reachable states with original encodings of: 00000000001 00000000010 00000000100 00000001000 00000010000 00000100000 00001000000 00010000000 00100000000 01000000000 10000000000 @N:CL201 : Top_spi_i2c.vhd(220) | Trying to extract state machine for register current_i2c_state Extracted state machine for register current_i2c_state State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @W: : Top_spi_i2c.vhd(220) | Initial value is not supported on state machine current_i2c_state @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 25 16:47:06 2009 ###########################################################] Synplicity Proasic Technology Mapper, Version 9.4.0, Build 055R, Built Jul 2 2008 07:11:59 Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved Product Version Version 9.4A1 @W:BN246 : | Failed to find top level module 'work.Top_spi_i2c' as specified in project file @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 85MB peak: 87MB) Encoding state machine work.Top_spi_i2c(def_arch)-current_i2c_state[0:4] original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N: : my_spi_slave_32.vhd(53) | Found counter in view:work.my_spi_slave_32(default) inst count[4:0] @N: : tinyi2c_master.vhd(499) | Found counter in view:work.TinyI2C_master(behave) inst bitcnt[2:0] Encoding state machine work.TinyI2C_master(behave)-i2c_presstate[0:10] original code -> new code 00000000001 -> 00000000001 00000000010 -> 00000000010 00000000100 -> 00000000100 00000001000 -> 00000001000 00000010000 -> 00000010000 00000100000 -> 00000100000 00001000000 -> 00001000000 00010000000 -> 00010000000 00100000000 -> 00100000000 01000000000 -> 01000000000 10000000000 -> 10000000000 @N:MF239 : tinyi2c_master.vhd(404) | Found 4 bit decrementor, 'un6_bitcnt_a_4[3:0]' @N:MF239 : tinyi2c_master.vhd(137) | Found 4 bit decrementor, 'un2_byte_count_0[3:0]' @N:MF239 : tinyi2c_master.vhd(137) | Found 4 bit decrementor, 'un2_byte_count_1[3:0]' @N:MF239 : tinyi2c_master.vhd(299) | Found 8 bit decrementor, 'un7_scl_count[7:0]' Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) @N:BN116 : my_spi_slave_32.vhd(77) | Removing sequential instance my_spi_slave_0.command_data_rcv_1[16] of view:PrimLib.dffr(prim) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB) Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 90MB peak: 91MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes --------------------------------------------------------------- PRESET_N_pad / Y 148 : 145 asynchronous set/reset s_mosi_pad / Y 31 =============================================================== Promoting Net PCLK_c on CLKBUF PCLK_pad Promoting Net PRESET_N_c on CLKBUF PRESET_N_pad Buffering s_sck_c, fanout 37 segments 2 Buffering s_mosi_c, fanout 31 segments 2 Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 90MB peak: 92MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 90MB peak: 92MB) Added 2 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 90MB peak: 92MB) Writing Analyst data base D:\Appsnotes\2009\SPI_to_I2C\Review\Design_files\SPI_I2C\synthesis\Top_spi_i2c.srm @N:BN225 : | Writing default property annotation file D:\Appsnotes\2009\SPI_to_I2C\Review\Design_files\SPI_I2C\synthesis\Top_spi_i2c.map. Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current: 89MB peak: 92MB) Writing EDIF Netlist and constraint files Version 9.4A1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:02s; Memory used current: 89MB peak: 92MB) Found clock Top_spi_i2c|PCLK with period 50.00ns Found clock Top_spi_i2c|s_sck with period 50.00ns Found clock Top_spi_i2c|go_inferred_clock with period 50.00ns Found clock TinyI2C_master|scl_clkx2_inferred_clock with period 50.00ns Found clock TinyI2C_master|holdsc_inferred_clock with period 50.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Mar 25 16:47:12 2009 # Top view: Top_spi_i2c Library name: iglool Operating conditions: COMWCSTD ( T = 70.0, V = 1.14, P = 3.70, tree_type = balanced_tree ) Requested Frequency: 20.0 MHz Wire load mode: top Wire load model: iglool Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -3.240 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------- TinyI2C_master|holdsc_inferred_clock 20.0 MHz 17.7 MHz 50.000 56.479 -3.240 inferred Inferred_clkgroup_2 TinyI2C_master|scl_clkx2_inferred_clock 20.0 MHz 167.8 MHz 50.000 5.960 44.040 inferred Inferred_clkgroup_4 Top_spi_i2c|PCLK 20.0 MHz 47.4 MHz 50.000 21.107 14.447 inferred Inferred_clkgroup_0 Top_spi_i2c|s_sck 20.0 MHz 28.5 MHz 50.000 35.039 7.480 inferred Inferred_clkgroup_1 =============================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Top_spi_i2c|PCLK Top_spi_i2c|PCLK | 50.000 32.431 | 50.000 39.676 | 25.000 14.447 | 25.000 20.114 Top_spi_i2c|PCLK Top_spi_i2c|s_sck | No paths - | No paths - | Diff grp - | No paths - Top_spi_i2c|PCLK TinyI2C_master|holdsc_inferred_clock | Diff grp - | No paths - | Diff grp - | Diff grp - Top_spi_i2c|s_sck Top_spi_i2c|PCLK | Diff grp - | No paths - | No paths - | Diff grp - Top_spi_i2c|s_sck Top_spi_i2c|s_sck | No paths - | 50.000 24.057 | No paths - | 25.000 7.480 Top_spi_i2c|s_sck TinyI2C_master|holdsc_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths - TinyI2C_master|holdsc_inferred_clock Top_spi_i2c|PCLK | Diff grp - | No paths - | No paths - | No paths - TinyI2C_master|holdsc_inferred_clock TinyI2C_master|holdsc_inferred_clock | 50.000 19.083 | No paths - | 25.000 -3.240 | No paths - TinyI2C_master|holdsc_inferred_clock TinyI2C_master|scl_clkx2_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - TinyI2C_master|scl_clkx2_inferred_clock TinyI2C_master|scl_clkx2_inferred_clock | No paths - | 50.000 44.040 | No paths - | No paths - ============================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: TinyI2C_master|holdsc_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------- I2C_master_0.bitcnt[1] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 Q bitcnt[1] 1.771 -3.240 I2C_master_0.bitcnt[2] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 Q bitcnt[2] 1.771 -1.895 I2C_master_0.src_cnt[2] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q src_cnt[2] 1.771 -1.837 I2C_master_0.src_cnt[0] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q src_cnt[0] 1.771 -1.177 I2C_master_0.src_cnt[3] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q src_cnt[3] 1.771 -0.392 I2C_master_0.i2c_presstate[0] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q i2c_presstate[0] 1.771 -0.283 I2C_master_0.bitcnt[0] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 Q bitcnt_c0 1.771 -0.220 I2C_master_0.read_act TinyI2C_master|holdsc_inferred_clock DFN1E1C0 Q read_act 1.771 -0.083 I2C_master_0.i2c_presstate[1] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q i2c_presstate[1] 1.771 0.535 I2C_master_0.ack TinyI2C_master|holdsc_inferred_clock DFN1E0C0 Q ack 1.771 0.719 ======================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ I2C_master_0.clr_sda TinyI2C_master|holdsc_inferred_clock DFN0C0 D clr_sda_4 23.288 -3.240 I2C_master_0.src_cnt[3] TinyI2C_master|holdsc_inferred_clock DFN1C0 D src_cnt_4[3] 48.705 19.083 I2C_master_0.src_cnt[2] TinyI2C_master|holdsc_inferred_clock DFN1C0 D src_cnt_4[2] 48.705 21.092 I2C_master_0.sr_out[0] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 D sr_out_5[0] 48.622 23.238 I2C_master_0.src_cnt[1] TinyI2C_master|holdsc_inferred_clock DFN1C0 D src_cnt_4[1] 48.705 23.255 I2C_master_0.sr_out[1] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 D sr_out_5[1] 48.705 23.560 I2C_master_0.sr_out[2] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 D sr_out_5[2] 48.705 23.560 I2C_master_0.sr_out[3] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 D sr_out_5[3] 48.705 23.560 I2C_master_0.sr_out[4] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 D sr_out_5[4] 48.705 23.560 I2C_master_0.sr_out[5] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 D sr_out_5[5] 48.705 23.560 ============================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 25.000 - Setup time: 1.712 = Required time: 23.288 - Propagation time: 26.527 = Slack (critical) : -3.240 Number of logic level(s): 8 Starting point: I2C_master_0.bitcnt[1] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- I2C_master_0.bitcnt[1] DFN1E0C0 Q Out 1.771 1.771 - bitcnt[1] Net - - 1.938 - 3 I2C_master_0.bitcnt_RNIVCB3[2] NOR2 B In - 3.708 - I2C_master_0.bitcnt_RNIVCB3[2] NOR2 Y Out 1.554 5.262 - N_252 Net - - 3.074 - 5 I2C_master_0.bitcnt_RNIDT05[0] OR2B B In - 8.336 - I2C_master_0.bitcnt_RNIDT05[0] OR2B Y Out 1.240 9.576 - N_257 Net - - 1.938 - 3 I2C_master_0.i2c_presstate_RNIQDJ6[7] NOR2A B In - 11.514 - I2C_master_0.i2c_presstate_RNIQDJ6[7] NOR2A Y Out 0.977 12.491 - i2c_presstate_ns[10] Net - - 3.420 - 6 I2C_master_0.clr_sda_RNO_13 NOR2A B In - 15.912 - I2C_master_0.clr_sda_RNO_13 NOR2A Y Out 0.927 16.839 - clr_sda_4_a0_1 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_9 AOI1B C In - 17.611 - I2C_master_0.clr_sda_RNO_9 AOI1B Y Out 0.973 18.584 - clr_sda_4_a0_2 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_5 NOR2A A In - 19.357 - I2C_master_0.clr_sda_RNO_5 NOR2A Y Out 1.508 20.865 - clr_sda_4_a0_3 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_2 NOR3B A In - 21.637 - I2C_master_0.clr_sda_RNO_2 NOR3B Y Out 1.541 23.178 - clr_sda_RNO_2 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO OR3 C In - 23.951 - I2C_master_0.clr_sda_RNO OR3 Y Out 1.804 25.755 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 26.527 - ======================================================================================================== Total path delay (propagation time + setup) of 28.240 is 14.007(49.6%) logic and 14.233(50.4%) route. Path information for path number 2: Requested Period: 25.000 - Setup time: 1.712 = Required time: 23.288 - Propagation time: 25.183 = Slack (non-critical) : -1.895 Number of logic level(s): 8 Starting point: I2C_master_0.bitcnt[2] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- I2C_master_0.bitcnt[2] DFN1E0C0 Q Out 1.771 1.771 - bitcnt[2] Net - - 0.927 - 2 I2C_master_0.bitcnt_RNIVCB3[2] NOR2 A In - 2.698 - I2C_master_0.bitcnt_RNIVCB3[2] NOR2 Y Out 1.219 3.917 - N_252 Net - - 3.074 - 5 I2C_master_0.bitcnt_RNIDT05[0] OR2B B In - 6.991 - I2C_master_0.bitcnt_RNIDT05[0] OR2B Y Out 1.240 8.231 - N_257 Net - - 1.938 - 3 I2C_master_0.i2c_presstate_RNIQDJ6[7] NOR2A B In - 10.169 - I2C_master_0.i2c_presstate_RNIQDJ6[7] NOR2A Y Out 0.977 11.146 - i2c_presstate_ns[10] Net - - 3.420 - 6 I2C_master_0.clr_sda_RNO_13 NOR2A B In - 14.567 - I2C_master_0.clr_sda_RNO_13 NOR2A Y Out 0.927 15.494 - clr_sda_4_a0_1 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_9 AOI1B C In - 16.267 - I2C_master_0.clr_sda_RNO_9 AOI1B Y Out 0.973 17.240 - clr_sda_4_a0_2 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_5 NOR2A A In - 18.012 - I2C_master_0.clr_sda_RNO_5 NOR2A Y Out 1.508 19.520 - clr_sda_4_a0_3 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_2 NOR3B A In - 20.292 - I2C_master_0.clr_sda_RNO_2 NOR3B Y Out 1.541 21.833 - clr_sda_RNO_2 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO OR3 C In - 22.606 - I2C_master_0.clr_sda_RNO OR3 Y Out 1.804 24.410 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 25.183 - ======================================================================================================== Total path delay (propagation time + setup) of 26.895 is 13.673(50.8%) logic and 13.222(49.2%) route. Path information for path number 3: Requested Period: 25.000 - Setup time: 1.712 = Required time: 23.288 - Propagation time: 25.125 = Slack (non-critical) : -1.837 Number of logic level(s): 7 Starting point: I2C_master_0.src_cnt[2] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ I2C_master_0.src_cnt[2] DFN1C0 Q Out 1.771 1.771 - src_cnt[2] Net - - 3.667 - 7 I2C_master_0.src_cnt_RNIVJL6[2] XOR2 B In - 5.438 - I2C_master_0.src_cnt_RNIVJL6[2] XOR2 Y Out 2.251 7.689 - un6_bitcnt_2_i Net - - 0.927 - 2 I2C_master_0.src_cnt_RNIONTE[3] XA1 C In - 8.616 - I2C_master_0.src_cnt_RNIONTE[3] XA1 Y Out 1.549 10.165 - un6_bitcnt_NE_0 Net - - 0.773 - 1 I2C_master_0.src_cnt_RNICGHN[1] OR2B B In - 10.938 - I2C_master_0.src_cnt_RNICGHN[1] OR2B Y Out 1.240 12.178 - un6_bitcnt_NE Net - - 3.667 - 7 I2C_master_0.i2c_presstate_RNITGMQ[2] NOR2A B In - 15.845 - I2C_master_0.i2c_presstate_RNITGMQ[2] NOR2A Y Out 0.977 16.822 - N_261 Net - - 0.927 - 2 I2C_master_0.ack_RNIB9V31 NOR3 C In - 17.749 - I2C_master_0.ack_RNIB9V31 NOR3 Y Out 1.641 19.390 - N_281 Net - - 0.927 - 2 I2C_master_0.clr_sda_RNO_1 NOR3A C In - 20.318 - I2C_master_0.clr_sda_RNO_1 NOR3A Y Out 1.721 22.038 - clr_sda_RNO_1 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO OR3 B In - 22.811 - I2C_master_0.clr_sda_RNO OR3 Y Out 1.541 24.352 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 25.125 - ====================================================================================================== Total path delay (propagation time + setup) of 26.837 is 14.404(53.7%) logic and 12.433(46.3%) route. Path information for path number 4: Requested Period: 25.000 - Setup time: 1.712 = Required time: 23.288 - Propagation time: 24.866 = Slack (non-critical) : -1.578 Number of logic level(s): 7 Starting point: I2C_master_0.src_cnt[2] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- I2C_master_0.src_cnt[2] DFN1C0 Q Out 1.771 1.771 - src_cnt[2] Net - - 3.667 - 7 I2C_master_0.src_cnt_RNIVJL6[2] XOR2 B In - 5.438 - I2C_master_0.src_cnt_RNIVJL6[2] XOR2 Y Out 2.251 7.689 - un6_bitcnt_2_i Net - - 0.927 - 2 I2C_master_0.src_cnt_RNI5OOB[1] XA1 C In - 8.616 - I2C_master_0.src_cnt_RNI5OOB[1] XA1 Y Out 1.549 10.165 - i2c_presstate_ns_a2_6_m7_i_a4_0_1 Net - - 0.773 - 1 I2C_master_0.i2c_presstate_RNIN7LT[3] AO1B B In - 10.938 - I2C_master_0.i2c_presstate_RNIN7LT[3] AO1B Y Out 1.090 12.028 - i2c_presstate_RNIN7LT[3] Net - - 0.773 - 1 I2C_master_0.i2c_presstate_RNIEL841[4] OR2B A In - 12.800 - I2C_master_0.i2c_presstate_RNIEL841[4] OR2B Y Out 1.174 13.974 - i2c_presstate_ns[6] Net - - 0.927 - 2 I2C_master_0.i2c_presstate_RNINJEC1[7] OR2 A In - 14.901 - I2C_master_0.i2c_presstate_RNINJEC1[7] OR2 Y Out 1.219 16.120 - shift_wr Net - - 3.938 - 8 I2C_master_0.clr_sda_RNO_2 NOR3B B In - 20.059 - I2C_master_0.clr_sda_RNO_2 NOR3B Y Out 1.458 21.516 - clr_sda_RNO_2 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO OR3 C In - 22.289 - I2C_master_0.clr_sda_RNO OR3 Y Out 1.804 24.093 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 24.866 - ======================================================================================================= Total path delay (propagation time + setup) of 26.578 is 14.028(52.8%) logic and 12.550(47.2%) route. Path information for path number 5: Requested Period: 25.000 - Setup time: 1.712 = Required time: 23.288 - Propagation time: 24.815 = Slack (non-critical) : -1.528 Number of logic level(s): 7 Starting point: I2C_master_0.src_cnt[2] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- I2C_master_0.src_cnt[2] DFN1C0 Q Out 1.771 1.771 - src_cnt[2] Net - - 3.667 - 7 I2C_master_0.src_cnt_RNIVJL6[2] XOR2 B In - 5.438 - I2C_master_0.src_cnt_RNIVJL6[2] XOR2 Y Out 2.251 7.689 - un6_bitcnt_2_i Net - - 0.927 - 2 I2C_master_0.src_cnt_RNIONTE[3] XA1 C In - 8.616 - I2C_master_0.src_cnt_RNIONTE[3] XA1 Y Out 1.549 10.165 - un6_bitcnt_NE_0 Net - - 0.773 - 1 I2C_master_0.src_cnt_RNICGHN[1] OR2B B In - 10.938 - I2C_master_0.src_cnt_RNICGHN[1] OR2B Y Out 1.240 12.178 - un6_bitcnt_NE Net - - 3.667 - 7 I2C_master_0.i2c_presstate_RNIJ2J21[3] NOR2A A In - 15.845 - I2C_master_0.i2c_presstate_RNIJ2J21[3] NOR2A Y Out 1.508 17.352 - N_284 Net - - 0.927 - 2 I2C_master_0.clr_sda_RNO_5 NOR2A B In - 18.280 - I2C_master_0.clr_sda_RNO_5 NOR2A Y Out 0.977 19.257 - clr_sda_4_a0_3 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_2 NOR3B A In - 20.029 - I2C_master_0.clr_sda_RNO_2 NOR3B Y Out 1.599 21.629 - clr_sda_RNO_2 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO OR3 C In - 22.401 - I2C_master_0.clr_sda_RNO OR3 Y Out 1.641 24.043 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 24.815 - ======================================================================================================= Total path delay (propagation time + setup) of 26.528 is 14.249(53.7%) logic and 12.278(46.3%) route. ==================================== Detailed Report for Clock: TinyI2C_master|scl_clkx2_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ I2C_master_0.start TinyI2C_master|scl_clkx2_inferred_clock DFN0C0 Q start 1.570 44.040 I2C_master_0.stop TinyI2C_master|scl_clkx2_inferred_clock DFN0C0 Q stop 1.570 44.040 ================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- I2C_master_0.start TinyI2C_master|scl_clkx2_inferred_clock DFN0C0 D start_RNO 48.288 44.040 I2C_master_0.stop TinyI2C_master|scl_clkx2_inferred_clock DFN0C0 D stop_RNO 48.288 44.040 ======================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 50.000 - Setup time: 1.712 = Required time: 48.288 - Propagation time: 4.247 = Slack (non-critical) : 44.040 Number of logic level(s): 1 Starting point: I2C_master_0.start / Q Ending point: I2C_master_0.start / D The start point is clocked by TinyI2C_master|scl_clkx2_inferred_clock [falling] on pin CLK The end point is clocked by TinyI2C_master|scl_clkx2_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- I2C_master_0.start DFN0C0 Q Out 1.570 1.570 - start Net - - 0.927 - 2 I2C_master_0.start_RNO NOR2A B In - 2.498 - I2C_master_0.start_RNO NOR2A Y Out 0.977 3.475 - start_RNO Net - - 0.773 - 1 I2C_master_0.start DFN0C0 D In - 4.247 - ======================================================================================= Total path delay (propagation time + setup) of 5.960 is 4.260(71.5%) logic and 1.700(28.5%) route. ==================================== Detailed Report for Clock: Top_spi_i2c|PCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------- I2C_master_0.sc1 Top_spi_i2c|PCLK DFN1P0 Q sc1 1.395 14.447 I2C_master_0.sd1 Top_spi_i2c|PCLK DFN1P0 Q sd1 1.395 14.447 I2C_master_0.sc3 Top_spi_i2c|PCLK DFN1P0 Q sc3 1.395 15.795 I2C_master_0.sd3 Top_spi_i2c|PCLK DFN1P0 Q sd3 1.395 15.795 I2C_master_0.sc2 Top_spi_i2c|PCLK DFN0P0 Q sc2 1.570 20.114 I2C_master_0.sd2 Top_spi_i2c|PCLK DFN0P0 Q sd2 1.570 20.114 i2c_write Top_spi_i2c|PCLK DFN1E1C0 Q i2c_write 1.771 32.431 I2C_master_0.scl_count[1] Top_spi_i2c|PCLK DFN1C0 Q scl_count[1] 1.771 33.145 I2C_master_0.scl_count[3] Top_spi_i2c|PCLK DFN1C0 Q scl_count[3] 1.771 33.161 I2C_master_0.scl_count[2] Top_spi_i2c|PCLK DFN1C0 Q scl_count[2] 1.771 33.287 =========================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- I2C_master_0.holdsd Top_spi_i2c|PCLK DFN0P0 D cleansd_1 23.288 14.447 I2C_master_0.sc2 Top_spi_i2c|PCLK DFN0P0 D sc1 23.288 19.579 I2C_master_0.sd2 Top_spi_i2c|PCLK DFN0P0 D sd1 23.288 19.579 I2C_master_0.sc3 Top_spi_i2c|PCLK DFN1P0 D sc2 23.622 20.114 I2C_master_0.sd3 Top_spi_i2c|PCLK DFN1P0 D sd2 23.622 20.114 current_i2c_state[3] Top_spi_i2c|PCLK DFN1C0 D current_i2c_state_ns[1] 48.622 32.431 go Top_spi_i2c|PCLK DFN1E1C0 E un1_slave_addr_0_sqmuxa 48.538 32.648 I2C_master_0.scl_count[4] Top_spi_i2c|PCLK DFN1C0 D scl_count_4[4] 48.622 33.145 I2C_master_0.raw_sclclk Top_spi_i2c|PCLK DFN1C0 D raw_sclclk_RNO 48.705 33.161 done Top_spi_i2c|PCLK DFN1E0C0 E N_262 48.538 33.378 ======================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 25.000 - Setup time: 1.712 = Required time: 23.288 - Propagation time: 8.841 = Slack (non-critical) : 14.447 Number of logic level(s): 2 Starting point: I2C_master_0.sc1 / Q Ending point: I2C_master_0.holdsc / D The start point is clocked by Top_spi_i2c|PCLK [rising] on pin CLK The end point is clocked by Top_spi_i2c|PCLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ I2C_master_0.sc1 DFN1P0 Q Out 1.395 1.395 - sc1 Net - - 1.938 - 3 I2C_master_0.holdsc_RNO_0 NOR3C C In - 3.333 - I2C_master_0.holdsc_RNO_0 NOR3C Y Out 1.599 4.932 - setsc Net - - 0.773 - 1 I2C_master_0.holdsc_RNO OA1B B In - 5.705 - I2C_master_0.holdsc_RNO OA1B Y Out 2.364 8.069 - cleansc_1 Net - - 0.773 - 1 I2C_master_0.holdsc DFN0P0 D In - 8.841 - ========================================================================================== Total path delay (propagation time + setup) of 10.554 is 7.070(67.0%) logic and 3.483(33.0%) route. ==================================== Detailed Report for Clock: Top_spi_i2c|s_sck ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------- my_spi_slave_0.count[2] Top_spi_i2c|s_sck DFN0P0 Q count[2] 1.570 7.480 my_spi_slave_0.count[4] Top_spi_i2c|s_sck DFN0P0 Q count[4] 1.570 7.923 my_spi_slave_0.count[3] Top_spi_i2c|s_sck DFN0P0 Q count[3] 1.570 8.098 my_spi_slave_0.count[0] Top_spi_i2c|s_sck DFN0P0 Q count[0] 1.570 8.445 my_spi_slave_0.count[1] Top_spi_i2c|s_sck DFN0P0 Q count[1] 1.570 8.550 =================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------- my_spi_slave_0.command_data_rcv_1[14] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_17 23.538 7.480 my_spi_slave_0.command_data_rcv_1[30] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_1 23.538 7.480 my_spi_slave_0.command_data_rcv_1[1] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_30 23.956 7.706 my_spi_slave_0.command_data_rcv_1[17] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_14 23.956 7.706 my_spi_slave_0.command_data_rcv_1[18] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_13 23.538 7.923 my_spi_slave_0.command_data_rcv_1[19] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_12 23.538 7.923 my_spi_slave_0.command_data_rcv_1[20] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_11 23.538 7.923 my_spi_slave_0.command_data_rcv_1[21] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_10 23.538 7.923 my_spi_slave_0.command_data_rcv_1[22] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_9 23.538 7.923 my_spi_slave_0.command_data_rcv_1[23] Top_spi_i2c|s_sck DFN1E1C0 E command_data_rcv_1_sqmuxa_8 23.538 7.923 ======================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 25.000 - Setup time: 1.462 = Required time: 23.538 - Propagation time: 16.058 = Slack (non-critical) : 7.480 Number of logic level(s): 3 Starting point: my_spi_slave_0.count[2] / Q Ending point: my_spi_slave_0.command_data_rcv_1[14] / E The start point is clocked by Top_spi_i2c|s_sck [falling] on pin CLK The end point is clocked by Top_spi_i2c|s_sck [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ my_spi_slave_0.count[2] DFN0P0 Q Out 1.570 1.570 - count[2] Net - - 3.420 - 6 my_spi_slave_0.count_RNIF4I3_1[3] NOR2B B In - 4.991 - my_spi_slave_0.count_RNIF4I3_1[3] NOR2B Y Out 1.508 6.498 - count_RNIF4I3_1[3] Net - - 4.105 - 10 my_spi_slave_0.count_RNIQ847_0[1] NOR2A A In - 10.604 - my_spi_slave_0.count_RNIQ847_0[1] NOR2A Y Out 1.508 12.111 - N_169 Net - - 1.938 - 3 my_spi_slave_0.command_data_rcv_1_RNO[14] NOR2B A In - 14.049 - my_spi_slave_0.command_data_rcv_1_RNO[14] NOR2B Y Out 1.236 15.285 - command_data_rcv_1_sqmuxa_17 Net - - 0.773 - 1 my_spi_slave_0.command_data_rcv_1[14] DFN1E1C0 E In - 16.058 - ============================================================================================================ Total path delay (propagation time + setup) of 17.520 is 7.283(41.6%) logic and 10.236(58.4%) route. ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Report for cell Top_spi_i2c.def_arch Core Cell usage: cell count area count*area AND2 1 1.0 1.0 AO1 4 1.0 4.0 AO1A 2 1.0 2.0 AO1B 3 1.0 3.0 AO1C 3 1.0 3.0 AO1D 1 1.0 1.0 AOI1 2 1.0 2.0 AOI1B 10 1.0 10.0 AX1 1 1.0 1.0 AX1B 3 1.0 3.0 AX1D 1 1.0 1.0 BUFF 2 1.0 2.0 CLKINT 1 0.0 0.0 GND 3 0.0 0.0 INV 5 1.0 5.0 MX2 26 1.0 26.0 MX2A 1 1.0 1.0 MX2B 1 1.0 1.0 MX2C 15 1.0 15.0 NOR2 27 1.0 27.0 NOR2A 31 1.0 31.0 NOR2B 14 1.0 14.0 NOR3 10 1.0 10.0 NOR3A 18 1.0 18.0 NOR3B 20 1.0 20.0 NOR3C 10 1.0 10.0 OA1 3 1.0 3.0 OA1B 5 1.0 5.0 OAI1 3 1.0 3.0 OR2 19 1.0 19.0 OR2A 9 1.0 9.0 OR2B 12 1.0 12.0 OR3 8 1.0 8.0 OR3A 2 1.0 2.0 OR3B 10 1.0 10.0 OR3C 6 1.0 6.0 VCC 3 0.0 0.0 XA1 3 1.0 3.0 XA1B 1 1.0 1.0 XAI1 1 1.0 1.0 XNOR2 13 1.0 13.0 XO1 2 1.0 2.0 XO1A 1 1.0 1.0 XOR2 10 1.0 10.0 DFN0C0 5 1.0 5.0 DFN0P0 9 1.0 9.0 DFN1C0 40 1.0 40.0 DFN1C1 1 1.0 1.0 DFN1E0C0 13 1.0 13.0 DFN1E1 16 1.0 16.0 DFN1E1C0 77 1.0 77.0 DFN1P0 7 1.0 7.0 ----- ---------- TOTAL 494 487.0 IO Cell usage: cell count BIBUF_LVCMOS12U 2 CLKBUF 2 INBUF 3 OUTBUF 2 ----- TOTAL 9 Core Cells : 487 of 3116 (16%) IO Cells : 9 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:03s realtime, 0h:00m:02s cputime # Wed Mar 25 16:47:12 2009 ###########################################################]