#Build: Synplify Pro 9.4A1, Build 169R, Jun 11 2008 #install: D:\Software\Libero\Libero_v8.4\Synplify\synplify_94A1 #OS: Windows XP 5.1 #Hostname: WXP-ALIMS #Implementation: synthesis #Tue Dec 16 16:45:30 2008 $ Start of Compile #Tue Dec 16 16:45:30 2008 Synplicity VHDL Compiler, version 1.0, Build 061R, built Jun 30 2008 Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns Top entity isn't set yet! VHDL syntax check successful! File D:\Appsnotes\2008\SPI_to_I2C\Designs\Final\appsnote_design\SPI_I2C\hdl\Top_spi_i2c_32.vhd changed - recompiling File D:\Appsnotes\2008\SPI_to_I2C\Designs\Final\appsnote_design\SPI_I2C\hdl\Top_spi_i2c_32.vhd changed - recompiling @N:CD630 : Top_spi_i2c_32.vhd(8) | Synthesizing work.top_spi_i2c_32.def_arch @N:CD231 : Top_spi_i2c_32.vhd(78) | Using onehot encoding for type i2c_state_type (i2c_idle="10000") @N:CD630 : TinyI2C_master.vhd(8) | Synthesizing work.tinyi2c_master.behave @N:CD231 : TinyI2C_master.vhd(48) | Using onehot encoding for type i2c_states (i2c_idle="10000000000") @W:CD280 : TinyI2C_master.vhd(39) | Unbound component BIBUF_LVCMOS12U mapped to black box @W:CD280 : TinyI2C_master.vhd(33) | Unbound component clkint mapped to black box @N:CD630 : TinyI2C_master.vhd(33) | Synthesizing work.clkint.syn_black_box Post processing for work.clkint.syn_black_box @N:CD630 : TinyI2C_master.vhd(39) | Synthesizing work.bibuf_lvcmos12u.syn_black_box Post processing for work.bibuf_lvcmos12u.syn_black_box Post processing for work.tinyi2c_master.behave @W:CL111 : TinyI2C_master.vhd(158) | All reachable assignments to sync_i2c_status(5) assign '0', register removed by optimization @W:CL208 : TinyI2C_master.vhd(158) | All reachable assignments to bit 5 of sync_i2c_status(7 downto 0) assign 0, register removed by optimization @N:CD630 : my_spi_slave_32.vhd(8) | Synthesizing work.my_spi_slave_32.default @W:CD610 : my_spi_slave_32.vhd(52) | Index value 0 to 32 could be out of prefix range 31 downto 0 Post processing for work.my_spi_slave_32.default Post processing for work.top_spi_i2c_32.def_arch @W:CL169 : Top_spi_i2c_32.vhd(203) | Pruning Register state_i2c_proc.num_of_data_5(3 downto 0) @W:CL169 : Top_spi_i2c_32.vhd(149) | Pruning Register send_i2c_status @W:CL169 : Top_spi_i2c_32.vhd(149) | Pruning Register send_read_data @A: : Top_spi_i2c_32.vhd(193) | Feedback mux created for signal i2c_rx_data_15_8[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : Top_spi_i2c_32.vhd(193) | Feedback mux created for signal i2c_rx_data_7_0[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @W:CL190 : Top_spi_i2c_32.vhd(149) | Optimizing register bit spi_tx_data(24) to a constant 0 @W:CL190 : Top_spi_i2c_32.vhd(149) | Optimizing register bit spi_tx_data(25) to a constant 0 @W:CL190 : Top_spi_i2c_32.vhd(149) | Optimizing register bit spi_tx_data(26) to a constant 0 @W:CL190 : Top_spi_i2c_32.vhd(149) | Optimizing register bit spi_tx_data(27) to a constant 0 @W:CL190 : Top_spi_i2c_32.vhd(149) | Optimizing register bit spi_tx_data(28) to a constant 0 @W:CL190 : Top_spi_i2c_32.vhd(149) | Optimizing register bit spi_tx_data(29) to a constant 0 @W:CL190 : Top_spi_i2c_32.vhd(149) | Optimizing register bit spi_tx_data(30) to a constant 0 @W:CL190 : Top_spi_i2c_32.vhd(149) | Optimizing register bit spi_tx_data(31) to a constant 0 @W:CL171 : Top_spi_i2c_32.vhd(149) | Pruning Register bit <31> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c_32.vhd(149) | Pruning Register bit <30> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c_32.vhd(149) | Pruning Register bit <29> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c_32.vhd(149) | Pruning Register bit <28> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c_32.vhd(149) | Pruning Register bit <27> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c_32.vhd(149) | Pruning Register bit <26> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c_32.vhd(149) | Pruning Register bit <25> of spi_tx_data(31 downto 0) @W:CL171 : Top_spi_i2c_32.vhd(149) | Pruning Register bit <24> of spi_tx_data(31 downto 0) @N:CL177 : TinyI2C_master.vhd(158) | Sharing sequential element sync_next_addr. @N:CL201 : TinyI2C_master.vhd(481) | Trying to extract state machine for register i2c_presstate Extracted state machine for register i2c_presstate State machine has 11 reachable states with original encodings of: 00000000001 00000000010 00000000100 00000001000 00000010000 00000100000 00001000000 00010000000 00100000000 01000000000 10000000000 @N:CL201 : Top_spi_i2c_32.vhd(193) | Trying to extract state machine for register current_i2c_state Extracted state machine for register current_i2c_state State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @W: : Top_spi_i2c_32.vhd(193) | Initial value is not supported on state machine current_i2c_state @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Dec 16 16:45:30 2008 ###########################################################] Synplicity Proasic Technology Mapper, Version 9.4.0, Build 055R, Built Jul 2 2008 07:11:59 Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved Product Version Version 9.4A1 @W:BN246 : | Failed to find top level module 'work.Top_spi_i2c_32' as specified in project file @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 85MB peak: 87MB) Encoding state machine work.Top_spi_i2c_32(def_arch)-current_i2c_state[0:4] original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N: : my_spi_slave_32.vhd(31) | Found counter in view:work.my_spi_slave_32(default) inst count[5:0] @N: : tinyi2c_master.vhd(481) | Found counter in view:work.TinyI2C_master(behave) inst bitcnt[2:0] Encoding state machine work.TinyI2C_master(behave)-i2c_presstate[0:10] original code -> new code 00000000001 -> 00000000001 00000000010 -> 00000000010 00000000100 -> 00000000100 00000001000 -> 00000001000 00000010000 -> 00000010000 00000100000 -> 00000100000 00001000000 -> 00001000000 00010000000 -> 00010000000 00100000000 -> 00100000000 01000000000 -> 01000000000 10000000000 -> 10000000000 @N:MF239 : tinyi2c_master.vhd(386) | Found 4 bit decrementor, 'un6_bitcnt_a_4[3:0]' @N:MF239 : tinyi2c_master.vhd(117) | Found 4 bit decrementor, 'un2_byte_count_0[3:0]' @N:MF239 : tinyi2c_master.vhd(117) | Found 4 bit decrementor, 'un2_byte_count_1[3:0]' @N:MF239 : tinyi2c_master.vhd(281) | Found 8 bit decrementor, 'un7_scl_count[7:0]' Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) @N:BN116 : my_spi_slave_32.vhd(47) | Removing sequential instance my_spi_slave_0.command_data_rcv_1[16] of view:PrimLib.dffr(prim) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB) Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 88MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 88MB) Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 92MB peak: 93MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ------------------------------------------------------------------------------ my_spi_slave_0.command_data_rcv_1[31] / Q 26 spi_detect_proc.un1_i2c_write3 / Y 26 un1_command_data_rcv_1 / Y 25 PRESET_N_pad / Y 156 : 153 asynchronous set/reset s_mosi_pad / Y 31 ============================================================================== Promoting Net PCLK_c on CLKBUF PCLK_pad Promoting Net PRESET_N_c on CLKBUF PRESET_N_pad Buffering s_sck_c, fanout 38 segments 2 Buffering s_mosi_c, fanout 31 segments 2 Replicating Combinational Instance un1_command_data_rcv_1, fanout 25 segments 2 Replicating Combinational Instance spi_detect_proc.un1_i2c_write3, fanout 26 segments 2 Replicating Sequential Instance my_spi_slave_0.command_data_rcv_1[31], fanout 26 segments 2 Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 91MB peak: 94MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 91MB peak: 94MB) Added 2 Buffers Added 3 Cells via replication Added 1 Sequential Cells via replication Added 2 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 91MB peak: 94MB) Writing Analyst data base D:\Appsnotes\2008\SPI_to_I2C\Designs\Final\appsnote_design\SPI_I2C\synthesis\Top_spi_i2c_32.srm @N:BN225 : | Writing default property annotation file D:\Appsnotes\2008\SPI_to_I2C\Designs\Final\appsnote_design\SPI_I2C\synthesis\Top_spi_i2c_32.map. Finished Writing Netlist Databases (Time elapsed 0h:00m:03s; Memory used current: 91MB peak: 94MB) Writing EDIF Netlist and constraint files Version 9.4A1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:03s; Memory used current: 91MB peak: 94MB) Found clock Top_spi_i2c_32|PCLK with period 10.00ns Found clock Top_spi_i2c_32|s_sck with period 10.00ns Found clock Top_spi_i2c_32|go_inferred_clock with period 10.00ns Found clock TinyI2C_master|scl_clkx2_inferred_clock with period 10.00ns Found clock TinyI2C_master|holdsc_inferred_clock with period 10.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Dec 16 16:45:35 2008 # Top view: Top_spi_i2c_32 Library name: iglool Operating conditions: COMWCSTD ( T = 70.0, V = 1.14, P = 3.70, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: iglool Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -21.770 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------ TinyI2C_master|holdsc_inferred_clock 100.0 MHz 18.7 MHz 10.000 53.540 -21.770 inferred Inferred_clkgroup_2 TinyI2C_master|scl_clkx2_inferred_clock 100.0 MHz 167.8 MHz 10.000 5.960 4.040 inferred Inferred_clkgroup_4 Top_spi_i2c_32|PCLK 100.0 MHz 47.4 MHz 10.000 21.107 -8.488 inferred Inferred_clkgroup_0 Top_spi_i2c_32|s_sck 100.0 MHz 27.6 MHz 10.000 36.200 -13.100 inferred Inferred_clkgroup_1 ================================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Top_spi_i2c_32|PCLK Top_spi_i2c_32|PCLK | 10.000 -8.488 | 10.000 -0.324 | 5.000 -5.554 | 5.000 0.114 Top_spi_i2c_32|PCLK Top_spi_i2c_32|s_sck | Diff grp - | No paths - | No paths - | No paths - Top_spi_i2c_32|PCLK TinyI2C_master|holdsc_inferred_clock | Diff grp - | No paths - | Diff grp - | Diff grp - Top_spi_i2c_32|s_sck Top_spi_i2c_32|PCLK | Diff grp - | No paths - | No paths - | Diff grp - Top_spi_i2c_32|s_sck Top_spi_i2c_32|s_sck | 10.000 -9.754 | No paths - | 5.000 -13.100 | No paths - Top_spi_i2c_32|s_sck TinyI2C_master|holdsc_inferred_clock | No paths - | Diff grp - | No paths - | Diff grp - TinyI2C_master|holdsc_inferred_clock Top_spi_i2c_32|PCLK | Diff grp - | No paths - | No paths - | No paths - TinyI2C_master|holdsc_inferred_clock TinyI2C_master|holdsc_inferred_clock | 10.000 -20.474 | No paths - | 5.000 -21.770 | No paths - TinyI2C_master|holdsc_inferred_clock TinyI2C_master|scl_clkx2_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - TinyI2C_master|scl_clkx2_inferred_clock TinyI2C_master|scl_clkx2_inferred_clock | No paths - | 10.000 4.040 | No paths - | No paths - ============================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: TinyI2C_master|holdsc_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------- I2C_master_0.bitcnt[0] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 Q bitcnt_c0 1.771 -21.770 I2C_master_0.src_cnt[2] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q src_cnt[2] 1.771 -21.565 I2C_master_0.src_cnt[3] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q src_cnt[3] 1.771 -21.060 I2C_master_0.bitcnt[1] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 Q bitcnt[1] 1.771 -20.910 I2C_master_0.src_cnt[0] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q src_cnt[0] 1.771 -20.818 I2C_master_0.bitcnt[2] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 Q bitcnt[2] 1.771 -20.546 I2C_master_0.read_act TinyI2C_master|holdsc_inferred_clock DFN1E1C0 Q read_act 1.395 -19.698 I2C_master_0.ack TinyI2C_master|holdsc_inferred_clock DFN1E0C0 Q ack 1.395 -18.926 I2C_master_0.i2c_presstate[0] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q i2c_presstate[0] 1.771 -18.780 I2C_master_0.src_cnt[1] TinyI2C_master|holdsc_inferred_clock DFN1C0 Q src_cnt[1] 1.771 -18.400 ======================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------- I2C_master_0.clr_sda TinyI2C_master|holdsc_inferred_clock DFN0C0 D clr_sda_4 3.288 -21.770 I2C_master_0.src_cnt[3] TinyI2C_master|holdsc_inferred_clock DFN1C0 D src_cnt_4[3] 8.705 -20.474 I2C_master_0.src_cnt[2] TinyI2C_master|holdsc_inferred_clock DFN1C0 D src_cnt_4[2] 8.705 -18.465 I2C_master_0.sr_out[0] TinyI2C_master|holdsc_inferred_clock DFN1E0C0 D sr_out_5[0] 8.622 -16.319 I2C_master_0.src_cnt[1] TinyI2C_master|holdsc_inferred_clock DFN1C0 D src_cnt_4[1] 8.705 -16.302 I2C_master_0.sr_in[0] TinyI2C_master|holdsc_inferred_clock DFN1E1C0 E shift_rd 8.538 -16.185 I2C_master_0.sr_in[1] TinyI2C_master|holdsc_inferred_clock DFN1E1C0 E shift_rd 8.538 -16.185 I2C_master_0.sr_in[2] TinyI2C_master|holdsc_inferred_clock DFN1E1C0 E shift_rd 8.538 -16.185 I2C_master_0.sr_in[3] TinyI2C_master|holdsc_inferred_clock DFN1E1C0 E shift_rd 8.538 -16.185 I2C_master_0.sr_in[4] TinyI2C_master|holdsc_inferred_clock DFN1E1C0 E shift_rd 8.538 -16.185 =============================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 1.712 = Required time: 3.288 - Propagation time: 25.058 = Slack (critical) : -21.770 Number of logic level(s): 6 Starting point: I2C_master_0.bitcnt[0] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- I2C_master_0.bitcnt[0] DFN1E0C0 Q Out 1.771 1.771 - bitcnt_c0 Net - - 3.074 - 5 I2C_master_0.bitcnt_RNIDT05_0[2] OR3 C In - 4.845 - I2C_master_0.bitcnt_RNIDT05_0[2] OR3 Y Out 1.804 6.649 - N_253 Net - - 2.844 - 4 I2C_master_0.i2c_presstate_RNINDJ6[4] OR2B B In - 9.493 - I2C_master_0.i2c_presstate_RNINDJ6[4] OR2B Y Out 1.508 11.000 - N_255 Net - - 1.938 - 3 I2C_master_0.i2c_presstate_RNIEL841[4] OR2B B In - 12.938 - I2C_master_0.i2c_presstate_RNIEL841[4] OR2B Y Out 1.240 14.178 - i2c_presstate_ns[6] Net - - 0.927 - 2 I2C_master_0.i2c_presstate_RNINJEC1[7] NOR2 A In - 15.106 - I2C_master_0.i2c_presstate_RNINJEC1[7] NOR2 Y Out 1.219 16.325 - shift_wr_i Net - - 3.938 - 8 I2C_master_0.clr_sda_RNO_0 OA1 A In - 20.263 - I2C_master_0.clr_sda_RNO_0 OA1 Y Out 2.364 22.627 - N_19_i Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO AO1C A In - 23.400 - I2C_master_0.clr_sda_RNO AO1C Y Out 0.885 24.285 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 25.058 - ========================================================================================================= Total path delay (propagation time + setup) of 26.770 is 12.503(46.7%) logic and 14.266(53.3%) route. Path information for path number 2: Requested Period: 5.000 - Setup time: 1.712 = Required time: 3.288 - Propagation time: 24.853 = Slack (non-critical) : -21.565 Number of logic level(s): 7 Starting point: I2C_master_0.src_cnt[2] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- I2C_master_0.src_cnt[2] DFN1C0 Q Out 1.771 1.771 - src_cnt[2] Net - - 3.667 - 7 I2C_master_0.src_cnt_RNIVJL6[2] XOR2 B In - 5.438 - I2C_master_0.src_cnt_RNIVJL6[2] XOR2 Y Out 2.251 7.689 - un6_bitcnt_2_i Net - - 0.927 - 2 I2C_master_0.src_cnt_RNI5OOB[1] XA1 C In - 8.616 - I2C_master_0.src_cnt_RNI5OOB[1] XA1 Y Out 1.549 10.165 - i2c_presstate_ns_a2_6_m9_i_a4_0_1 Net - - 0.773 - 1 I2C_master_0.i2c_presstate_RNIN7LT[0] AO1B B In - 10.938 - I2C_master_0.i2c_presstate_RNIN7LT[0] AO1B Y Out 1.090 12.028 - i2c_presstate_RNIN7LT[0] Net - - 0.773 - 1 I2C_master_0.i2c_presstate_RNIEL841[4] OR2B A In - 12.800 - I2C_master_0.i2c_presstate_RNIEL841[4] OR2B Y Out 1.174 13.974 - i2c_presstate_ns[6] Net - - 0.927 - 2 I2C_master_0.i2c_presstate_RNINJEC1[7] NOR2 A In - 14.901 - I2C_master_0.i2c_presstate_RNINJEC1[7] NOR2 Y Out 1.219 16.120 - shift_wr_i Net - - 3.938 - 8 I2C_master_0.clr_sda_RNO_0 OA1 A In - 20.059 - I2C_master_0.clr_sda_RNO_0 OA1 Y Out 2.364 22.422 - N_19_i Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO AO1C A In - 23.195 - I2C_master_0.clr_sda_RNO AO1C Y Out 0.885 24.080 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 24.853 - ======================================================================================================= Total path delay (propagation time + setup) of 26.565 is 14.015(52.8%) logic and 12.550(47.2%) route. Path information for path number 3: Requested Period: 5.000 - Setup time: 1.712 = Required time: 3.288 - Propagation time: 24.431 = Slack (non-critical) : -21.144 Number of logic level(s): 7 Starting point: I2C_master_0.src_cnt[2] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ I2C_master_0.src_cnt[2] DFN1C0 Q Out 1.771 1.771 - src_cnt[2] Net - - 3.667 - 7 I2C_master_0.src_cnt_RNIVJL6[2] XOR2 B In - 5.438 - I2C_master_0.src_cnt_RNIVJL6[2] XOR2 Y Out 2.251 7.689 - un6_bitcnt_2_i Net - - 0.927 - 2 I2C_master_0.src_cnt_RNID86A[0] NOR2B A In - 8.616 - I2C_master_0.src_cnt_RNID86A[0] NOR2B Y Out 1.174 9.789 - un6_bitcnt_NE_1 Net - - 0.773 - 1 I2C_master_0.src_cnt_RNICGHN[1] OR2B A In - 10.562 - I2C_master_0.src_cnt_RNICGHN[1] OR2B Y Out 1.174 11.735 - un6_bitcnt_NE Net - - 3.667 - 7 I2C_master_0.i2c_presstate_RNITGMQ[2] OR2A B In - 15.402 - I2C_master_0.i2c_presstate_RNITGMQ[2] OR2A Y Out 1.554 16.956 - N_261 Net - - 0.927 - 2 I2C_master_0.clr_sda_RNO_6 OR3C C In - 17.883 - I2C_master_0.clr_sda_RNO_6 OR3C Y Out 1.541 19.424 - N_281 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_1 NOR3C C In - 20.197 - I2C_master_0.clr_sda_RNO_1 NOR3C Y Out 1.599 21.796 - G_1_4 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO AO1C B In - 22.569 - I2C_master_0.clr_sda_RNO AO1C Y Out 1.090 23.659 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 24.431 - ====================================================================================================== Total path delay (propagation time + setup) of 26.144 is 13.865(53.0%) logic and 12.278(47.0%) route. Path information for path number 4: Requested Period: 5.000 - Setup time: 1.712 = Required time: 3.288 - Propagation time: 24.348 = Slack (non-critical) : -21.060 Number of logic level(s): 7 Starting point: I2C_master_0.src_cnt[3] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- I2C_master_0.src_cnt[3] DFN1C0 Q Out 1.771 1.771 - src_cnt[3] Net - - 3.074 - 5 I2C_master_0.src_cnt_RNIP388[3] XOR2 B In - 4.845 - I2C_master_0.src_cnt_RNIP388[3] XOR2 Y Out 2.251 7.096 - un6_bitcnt_3_i_0 Net - - 0.927 - 2 I2C_master_0.i2c_presstate_RNID8BD[0] NOR3B A In - 8.023 - I2C_master_0.i2c_presstate_RNID8BD[0] NOR3B Y Out 1.599 9.622 - i2c_presstate_ns_a2_6_m9_i_a4_0_2 Net - - 0.773 - 1 I2C_master_0.i2c_presstate_RNIN7LT[0] AO1B A In - 10.395 - I2C_master_0.i2c_presstate_RNIN7LT[0] AO1B Y Out 1.128 11.522 - i2c_presstate_RNIN7LT[0] Net - - 0.773 - 1 I2C_master_0.i2c_presstate_RNIEL841[4] OR2B A In - 12.295 - I2C_master_0.i2c_presstate_RNIEL841[4] OR2B Y Out 1.174 13.469 - i2c_presstate_ns[6] Net - - 0.927 - 2 I2C_master_0.i2c_presstate_RNINJEC1[7] NOR2 A In - 14.396 - I2C_master_0.i2c_presstate_RNINJEC1[7] NOR2 Y Out 1.219 15.615 - shift_wr_i Net - - 3.938 - 8 I2C_master_0.clr_sda_RNO_0 OA1 A In - 19.553 - I2C_master_0.clr_sda_RNO_0 OA1 Y Out 2.364 21.917 - N_19_i Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO AO1C A In - 22.690 - I2C_master_0.clr_sda_RNO AO1C Y Out 0.885 23.575 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 24.348 - ======================================================================================================= Total path delay (propagation time + setup) of 26.060 is 14.103(54.1%) logic and 11.957(45.9%) route. Path information for path number 5: Requested Period: 5.000 - Setup time: 1.712 = Required time: 3.288 - Propagation time: 24.281 = Slack (non-critical) : -20.993 Number of logic level(s): 7 Starting point: I2C_master_0.src_cnt[3] / Q Ending point: I2C_master_0.clr_sda / D The start point is clocked by TinyI2C_master|holdsc_inferred_clock [rising] on pin CLK The end point is clocked by TinyI2C_master|holdsc_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ I2C_master_0.src_cnt[3] DFN1C0 Q Out 1.771 1.771 - src_cnt[3] Net - - 3.074 - 5 I2C_master_0.src_cnt_RNIP388[3] XOR2 B In - 4.845 - I2C_master_0.src_cnt_RNIP388[3] XOR2 Y Out 2.251 7.096 - un6_bitcnt_3_i_0 Net - - 0.927 - 2 I2C_master_0.src_cnt_RNIV7BD[1] XA1 C In - 8.023 - I2C_master_0.src_cnt_RNIV7BD[1] XA1 Y Out 1.549 9.572 - un6_bitcnt_NE_0 Net - - 0.773 - 1 I2C_master_0.src_cnt_RNICGHN[1] OR2B B In - 10.345 - I2C_master_0.src_cnt_RNICGHN[1] OR2B Y Out 1.240 11.585 - un6_bitcnt_NE Net - - 3.667 - 7 I2C_master_0.i2c_presstate_RNITGMQ[2] OR2A B In - 15.252 - I2C_master_0.i2c_presstate_RNITGMQ[2] OR2A Y Out 1.554 16.805 - N_261 Net - - 0.927 - 2 I2C_master_0.clr_sda_RNO_6 OR3C C In - 17.733 - I2C_master_0.clr_sda_RNO_6 OR3C Y Out 1.541 19.274 - N_281 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO_1 NOR3C C In - 20.046 - I2C_master_0.clr_sda_RNO_1 NOR3C Y Out 1.599 21.646 - G_1_4 Net - - 0.773 - 1 I2C_master_0.clr_sda_RNO AO1C B In - 22.418 - I2C_master_0.clr_sda_RNO AO1C Y Out 1.090 23.508 - clr_sda_4 Net - - 0.773 - 1 I2C_master_0.clr_sda DFN0C0 D In - 24.281 - ====================================================================================================== Total path delay (propagation time + setup) of 25.993 is 14.308(55.0%) logic and 11.685(45.0%) route. ==================================== Detailed Report for Clock: TinyI2C_master|scl_clkx2_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------- I2C_master_0.start TinyI2C_master|scl_clkx2_inferred_clock DFN0C0 Q start 1.570 4.040 I2C_master_0.stop TinyI2C_master|scl_clkx2_inferred_clock DFN0C0 Q stop 1.570 4.040 ================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------- I2C_master_0.start TinyI2C_master|scl_clkx2_inferred_clock DFN0C0 D start_RNO 8.288 4.040 I2C_master_0.stop TinyI2C_master|scl_clkx2_inferred_clock DFN0C0 D stop_RNO 8.288 4.040 ====================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.712 = Required time: 8.288 - Propagation time: 4.247 = Slack (non-critical) : 4.040 Number of logic level(s): 1 Starting point: I2C_master_0.start / Q Ending point: I2C_master_0.start / D The start point is clocked by TinyI2C_master|scl_clkx2_inferred_clock [falling] on pin CLK The end point is clocked by TinyI2C_master|scl_clkx2_inferred_clock [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- I2C_master_0.start DFN0C0 Q Out 1.570 1.570 - start Net - - 0.927 - 2 I2C_master_0.start_RNO NOR2A B In - 2.498 - I2C_master_0.start_RNO NOR2A Y Out 0.977 3.475 - start_RNO Net - - 0.773 - 1 I2C_master_0.start DFN0C0 D In - 4.247 - ======================================================================================= Total path delay (propagation time + setup) of 5.960 is 4.260(71.5%) logic and 1.700(28.5%) route. ==================================== Detailed Report for Clock: Top_spi_i2c_32|PCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------- current_i2c_state[0] Top_spi_i2c_32|PCLK DFN1C0 Q current_i2c_state[0] 1.771 -8.488 i2c_write Top_spi_i2c_32|PCLK DFN1E1C0 Q i2c_write 1.771 -7.954 current_i2c_state[2] Top_spi_i2c_32|PCLK DFN1C0 Q current_i2c_state[2] 1.771 -7.561 i2c_read Top_spi_i2c_32|PCLK DFN1E1C0 Q i2c_read 1.771 -7.382 I2C_master_0.sync_i2c_status[2] Top_spi_i2c_32|PCLK DFN1C0 Q next_addr[1] 1.771 -6.897 I2C_master_0.scl_count[1] Top_spi_i2c_32|PCLK DFN1C0 Q scl_count[1] 1.771 -6.855 I2C_master_0.scl_count[3] Top_spi_i2c_32|PCLK DFN1C0 Q scl_count[3] 1.771 -6.839 I2C_master_0.scl_count[2] Top_spi_i2c_32|PCLK DFN1C0 Q scl_count[2] 1.771 -6.713 I2C_master_0.sync_i2c_status[3] Top_spi_i2c_32|PCLK DFN1C0 Q next_addr[2] 1.771 -6.626 I2C_master_0.sync_i2c_status[4] Top_spi_i2c_32|PCLK DFN1C0 Q next_addr[3] 1.771 -6.605 ============================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------- current_i2c_state[4] Top_spi_i2c_32|PCLK DFN1P0 D current_i2c_state_RNO[4] 8.705 -8.488 current_i2c_state[3] Top_spi_i2c_32|PCLK DFN1C0 D current_i2c_state_ns[1] 8.622 -7.954 done Top_spi_i2c_32|PCLK DFN1E1C0 E done_RNO_0 8.538 -7.904 go Top_spi_i2c_32|PCLK DFN1E0C0 D slave_addr_0_sqmuxa_i 8.622 -7.252 current_i2c_state[2] Top_spi_i2c_32|PCLK DFN1C0 D current_i2c_state_ns[2] 8.622 -6.897 I2C_master_0.scl_count[4] Top_spi_i2c_32|PCLK DFN1C0 D scl_count_4[4] 8.622 -6.855 I2C_master_0.raw_sclclk Top_spi_i2c_32|PCLK DFN1C0 D raw_sclclk_RNO 8.705 -6.839 I2C_master_0.scl_count[5] Top_spi_i2c_32|PCLK DFN1C0 D scl_count_4[5] 8.622 -6.475 data_in[0] Top_spi_i2c_32|PCLK DFN1E1C0 E current_i2c_state_RNI634B[0] 8.956 -6.275 data_in[1] Top_spi_i2c_32|PCLK DFN1E1C0 E current_i2c_state_RNI634B[0] 8.956 -6.275 =============================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 17.194 = Slack (non-critical) : -8.488 Number of logic level(s): 4 Starting point: current_i2c_state[0] / Q Ending point: current_i2c_state[4] / D The start point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- current_i2c_state[0] DFN1C0 Q Out 1.771 1.771 - current_i2c_state[0] Net - - 3.667 - 7 current_i2c_state_RNI6VB1[2] OR2 B In - 5.438 - current_i2c_state_RNI6VB1[2] OR2 Y Out 1.554 6.991 - N_261 Net - - 2.844 - 4 current_i2c_state_RNIPU12[1] NOR2 B In - 9.835 - current_i2c_state_RNIPU12[1] NOR2 Y Out 1.554 11.389 - N_272 Net - - 0.927 - 2 current_i2c_state_RNO_2[4] AO1D B In - 12.316 - current_i2c_state_RNO_2[4] AO1D Y Out 1.529 13.845 - current_i2c_state_ns_i_0[0] Net - - 0.773 - 1 current_i2c_state_RNO[4] NOR3 C In - 14.617 - current_i2c_state_RNO[4] NOR3 Y Out 1.804 16.421 - current_i2c_state_RNO[4] Net - - 0.773 - 1 current_i2c_state[4] DFN1P0 D In - 17.194 - ============================================================================================= Total path delay (propagation time + setup) of 18.488 is 9.505(51.4%) logic and 8.983(48.6%) route. Path information for path number 2: Requested Period: 10.000 - Setup time: 1.378 = Required time: 8.622 - Propagation time: 16.997 = Slack (non-critical) : -8.376 Number of logic level(s): 4 Starting point: current_i2c_state[0] / Q Ending point: current_i2c_state[4] / D The start point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- current_i2c_state[0] DFN1C0 Q Out 1.771 1.771 - current_i2c_state[0] Net - - 3.667 - 7 current_i2c_state_RNI6VB1[2] OR2 B In - 5.438 - current_i2c_state_RNI6VB1[2] OR2 Y Out 1.554 6.991 - N_261 Net - - 2.844 - 4 current_i2c_state_RNIPU12[1] NOR2 B In - 9.835 - current_i2c_state_RNIPU12[1] NOR2 Y Out 1.554 11.389 - N_272 Net - - 0.927 - 2 current_i2c_state_RNO_1[4] NOR3A A In - 12.316 - current_i2c_state_RNO_1[4] NOR3A Y Out 1.595 13.911 - N_282 Net - - 0.773 - 1 current_i2c_state_RNO[4] NOR3 B In - 14.684 - current_i2c_state_RNO[4] NOR3 Y Out 1.541 16.225 - current_i2c_state_RNO[4] Net - - 0.773 - 1 current_i2c_state[4] DFN1P0 D In - 16.997 - ============================================================================================= Total path delay (propagation time + setup) of 18.376 is 9.392(51.1%) logic and 8.983(48.9%) route. Path information for path number 3: Requested Period: 10.000 - Setup time: 1.378 = Required time: 8.622 - Propagation time: 16.576 = Slack (non-critical) : -7.954 Number of logic level(s): 3 Starting point: i2c_write / Q Ending point: current_i2c_state[3] / D The start point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- i2c_write DFN1E1C0 Q Out 1.771 1.771 - i2c_write Net - - 2.844 - 4 i2c_read_RNIFKQ1_0 NOR2 A In - 4.615 - i2c_read_RNIFKQ1_0 NOR2 Y Out 1.219 5.834 - N_263 Net - - 2.844 - 4 current_i2c_state_RNIID7D[4] OR3A B In - 8.678 - current_i2c_state_RNIID7D[4] OR3A Y Out 1.541 10.219 - slave_addr_0_sqmuxa Net - - 4.009 - 9 current_i2c_state_RNO[3] AO1B C In - 14.229 - current_i2c_state_RNO[3] AO1B Y Out 1.574 15.803 - current_i2c_state_ns[1] Net - - 0.773 - 1 current_i2c_state[3] DFN1C0 D In - 16.576 - =============================================================================================== Total path delay (propagation time + setup) of 17.954 is 7.484(41.7%) logic and 10.470(58.3%) route. Path information for path number 4: Requested Period: 10.000 - Setup time: 1.462 = Required time: 8.538 - Propagation time: 16.442 = Slack (non-critical) : -7.904 Number of logic level(s): 4 Starting point: current_i2c_state[0] / Q Ending point: done / E The start point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- current_i2c_state[0] DFN1C0 Q Out 1.771 1.771 - current_i2c_state[0] Net - - 3.667 - 7 current_i2c_state_RNI6VB1[2] OR2 B In - 5.438 - current_i2c_state_RNI6VB1[2] OR2 Y Out 1.554 6.991 - N_261 Net - - 2.844 - 4 done_RNO_6 NOR2B B In - 9.835 - done_RNO_6 NOR2B Y Out 1.508 11.343 - un1_current_i2c_state_0_a0_0 Net - - 0.773 - 1 done_RNO_2 AO1B C In - 12.115 - done_RNO_2 AO1B Y Out 1.520 13.636 - done_RNO_2 Net - - 0.773 - 1 done_RNO_0 OR3C A In - 14.408 - done_RNO_0 OR3C Y Out 1.261 15.669 - done_RNO_0 Net - - 0.773 - 1 done DFN1E1C0 E In - 16.442 - =============================================================================================== Total path delay (propagation time + setup) of 17.904 is 9.075(50.7%) logic and 8.829(49.3%) route. Path information for path number 5: Requested Period: 10.000 - Setup time: 1.295 = Required time: 8.705 - Propagation time: 16.267 = Slack (non-critical) : -7.561 Number of logic level(s): 4 Starting point: current_i2c_state[2] / Q Ending point: current_i2c_state[4] / D The start point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|PCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- current_i2c_state[2] DFN1C0 Q Out 1.771 1.771 - current_i2c_state[2] Net - - 3.074 - 5 current_i2c_state_RNI6VB1[2] OR2 A In - 4.845 - current_i2c_state_RNI6VB1[2] OR2 Y Out 1.219 6.064 - N_261 Net - - 2.844 - 4 current_i2c_state_RNIPU12[1] NOR2 B In - 8.908 - current_i2c_state_RNIPU12[1] NOR2 Y Out 1.554 10.462 - N_272 Net - - 0.927 - 2 current_i2c_state_RNO_2[4] AO1D B In - 11.389 - current_i2c_state_RNO_2[4] AO1D Y Out 1.529 12.917 - current_i2c_state_ns_i_0[0] Net - - 0.773 - 1 current_i2c_state_RNO[4] NOR3 C In - 13.690 - current_i2c_state_RNO[4] NOR3 Y Out 1.804 15.494 - current_i2c_state_RNO[4] Net - - 0.773 - 1 current_i2c_state[4] DFN1P0 D In - 16.267 - ============================================================================================= Total path delay (propagation time + setup) of 17.561 is 9.171(52.2%) logic and 8.390(47.8%) route. ==================================== Detailed Report for Clock: Top_spi_i2c_32|s_sck ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------- my_spi_slave_0.count[4] Top_spi_i2c_32|s_sck DFN1C0 Q count[4] 1.771 -13.100 my_spi_slave_0.count[0] Top_spi_i2c_32|s_sck DFN1C0 Q count[0] 1.771 -12.900 my_spi_slave_0.count[1] Top_spi_i2c_32|s_sck DFN1C0 Q count[1] 1.771 -12.565 my_spi_slave_0.count[3] Top_spi_i2c_32|s_sck DFN1C0 Q count[3] 1.771 -11.496 my_spi_slave_0.count[2] Top_spi_i2c_32|s_sck DFN1C0 Q count[2] 1.771 -11.095 my_spi_slave_0.count[5] Top_spi_i2c_32|s_sck DFN1P0 Q count[5] 1.771 4.061 ======================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------- my_spi_slave_0.command_data_rcv_1[1] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_31 3.538 -13.100 my_spi_slave_0.command_data_rcv_1[5] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_27 3.538 -13.100 my_spi_slave_0.command_data_rcv_1[13] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_19 3.538 -13.100 my_spi_slave_0.command_data_rcv_1[2] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_30 3.538 -13.096 my_spi_slave_0.command_data_rcv_1[3] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_29 3.538 -13.096 my_spi_slave_0.command_data_rcv_1[4] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_24 3.538 -13.096 my_spi_slave_0.command_data_rcv_1[6] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_26 3.538 -13.096 my_spi_slave_0.command_data_rcv_1[7] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_25 3.538 -13.096 my_spi_slave_0.command_data_rcv_1[8] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_20 3.538 -13.096 my_spi_slave_0.command_data_rcv_1[10] Top_spi_i2c_32|s_sck DFN0E1C0 E command_data_rcv_1_sqmuxa_22 3.538 -13.096 ============================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 1.462 = Required time: 3.538 - Propagation time: 16.638 = Slack (non-critical) : -13.100 Number of logic level(s): 2 Starting point: my_spi_slave_0.count[4] / Q Ending point: my_spi_slave_0.command_data_rcv_1[1] / E The start point is clocked by Top_spi_i2c_32|s_sck [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|s_sck [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- my_spi_slave_0.count[4] DFN1C0 Q Out 1.771 1.771 - count[4] Net - - 5.722 - 21 my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 B In - 7.492 - my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 Y Out 1.554 9.046 - N_140 Net - - 5.220 - 16 my_spi_slave_0.command_data_rcv_1_RNO[1] NOR3B A In - 14.266 - my_spi_slave_0.command_data_rcv_1_RNO[1] NOR3B Y Out 1.599 15.866 - command_data_rcv_1_sqmuxa_31 Net - - 0.773 - 1 my_spi_slave_0.command_data_rcv_1[1] DFN0E1C0 E In - 16.638 - =========================================================================================================== Total path delay (propagation time + setup) of 18.100 is 6.386(35.3%) logic and 11.715(64.7%) route. Path information for path number 2: Requested Period: 5.000 - Setup time: 1.462 = Required time: 3.538 - Propagation time: 16.638 = Slack (non-critical) : -13.100 Number of logic level(s): 2 Starting point: my_spi_slave_0.count[4] / Q Ending point: my_spi_slave_0.command_data_rcv_1[5] / E The start point is clocked by Top_spi_i2c_32|s_sck [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|s_sck [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- my_spi_slave_0.count[4] DFN1C0 Q Out 1.771 1.771 - count[4] Net - - 5.722 - 21 my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 B In - 7.492 - my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 Y Out 1.554 9.046 - N_140 Net - - 5.220 - 16 my_spi_slave_0.command_data_rcv_1_RNO[5] NOR3B A In - 14.266 - my_spi_slave_0.command_data_rcv_1_RNO[5] NOR3B Y Out 1.599 15.866 - command_data_rcv_1_sqmuxa_27 Net - - 0.773 - 1 my_spi_slave_0.command_data_rcv_1[5] DFN0E1C0 E In - 16.638 - =========================================================================================================== Total path delay (propagation time + setup) of 18.100 is 6.386(35.3%) logic and 11.715(64.7%) route. Path information for path number 3: Requested Period: 5.000 - Setup time: 1.462 = Required time: 3.538 - Propagation time: 16.638 = Slack (non-critical) : -13.100 Number of logic level(s): 2 Starting point: my_spi_slave_0.count[4] / Q Ending point: my_spi_slave_0.command_data_rcv_1[13] / E The start point is clocked by Top_spi_i2c_32|s_sck [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|s_sck [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ my_spi_slave_0.count[4] DFN1C0 Q Out 1.771 1.771 - count[4] Net - - 5.722 - 21 my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 B In - 7.492 - my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 Y Out 1.554 9.046 - N_140 Net - - 5.220 - 16 my_spi_slave_0.command_data_rcv_1_RNO[13] NOR3B A In - 14.266 - my_spi_slave_0.command_data_rcv_1_RNO[13] NOR3B Y Out 1.599 15.866 - command_data_rcv_1_sqmuxa_19 Net - - 0.773 - 1 my_spi_slave_0.command_data_rcv_1[13] DFN0E1C0 E In - 16.638 - ============================================================================================================ Total path delay (propagation time + setup) of 18.100 is 6.386(35.3%) logic and 11.715(64.7%) route. Path information for path number 4: Requested Period: 5.000 - Setup time: 1.462 = Required time: 3.538 - Propagation time: 16.634 = Slack (non-critical) : -13.096 Number of logic level(s): 2 Starting point: my_spi_slave_0.count[4] / Q Ending point: my_spi_slave_0.command_data_rcv_1[8] / E The start point is clocked by Top_spi_i2c_32|s_sck [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|s_sck [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- my_spi_slave_0.count[4] DFN1C0 Q Out 1.771 1.771 - count[4] Net - - 5.722 - 21 my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 B In - 7.492 - my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 Y Out 1.554 9.046 - N_140 Net - - 5.220 - 16 my_spi_slave_0.command_data_rcv_1_RNO[8] NOR3A A In - 14.266 - my_spi_slave_0.command_data_rcv_1_RNO[8] NOR3A Y Out 1.595 15.862 - command_data_rcv_1_sqmuxa_20 Net - - 0.773 - 1 my_spi_slave_0.command_data_rcv_1[8] DFN0E1C0 E In - 16.634 - =========================================================================================================== Total path delay (propagation time + setup) of 18.096 is 6.381(35.3%) logic and 11.715(64.7%) route. Path information for path number 5: Requested Period: 5.000 - Setup time: 1.462 = Required time: 3.538 - Propagation time: 16.634 = Slack (non-critical) : -13.096 Number of logic level(s): 2 Starting point: my_spi_slave_0.count[4] / Q Ending point: my_spi_slave_0.command_data_rcv_1[11] / E The start point is clocked by Top_spi_i2c_32|s_sck [rising] on pin CLK The end point is clocked by Top_spi_i2c_32|s_sck [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ my_spi_slave_0.count[4] DFN1C0 Q Out 1.771 1.771 - count[4] Net - - 5.722 - 21 my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 B In - 7.492 - my_spi_slave_0.count_RNIPCJ3_0[4] NOR2 Y Out 1.554 9.046 - N_140 Net - - 5.220 - 16 my_spi_slave_0.command_data_rcv_1_RNO[11] NOR3A A In - 14.266 - my_spi_slave_0.command_data_rcv_1_RNO[11] NOR3A Y Out 1.595 15.862 - command_data_rcv_1_sqmuxa_21 Net - - 0.773 - 1 my_spi_slave_0.command_data_rcv_1[11] DFN0E1C0 E In - 16.634 - ============================================================================================================ Total path delay (propagation time + setup) of 18.096 is 6.381(35.3%) logic and 11.715(64.7%) route. ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Report for cell Top_spi_i2c_32.def_arch Core Cell usage: cell count area count*area AND2 1 1.0 1.0 AO1 2 1.0 2.0 AO1A 1 1.0 1.0 AO1B 7 1.0 7.0 AO1C 2 1.0 2.0 AO1D 1 1.0 1.0 AOI1 4 1.0 4.0 AOI1B 5 1.0 5.0 AX1 2 1.0 2.0 AX1B 1 1.0 1.0 AX1D 1 1.0 1.0 BUFF 2 1.0 2.0 CLKINT 1 0.0 0.0 GND 3 0.0 0.0 INV 5 1.0 5.0 MX2 33 1.0 33.0 MX2A 1 1.0 1.0 MX2C 39 1.0 39.0 NOR2 37 1.0 37.0 NOR2A 23 1.0 23.0 NOR2B 10 1.0 10.0 NOR3 9 1.0 9.0 NOR3A 26 1.0 26.0 NOR3B 12 1.0 12.0 NOR3C 4 1.0 4.0 OA1 3 1.0 3.0 OA1B 5 1.0 5.0 OAI1 2 1.0 2.0 OR2 19 1.0 19.0 OR2A 13 1.0 13.0 OR2B 17 1.0 17.0 OR3 9 1.0 9.0 OR3A 2 1.0 2.0 OR3B 4 1.0 4.0 OR3C 6 1.0 6.0 VCC 3 0.0 0.0 XA1 2 1.0 2.0 XA1A 2 1.0 2.0 XAI1 1 1.0 1.0 XNOR2 15 1.0 15.0 XO1A 1 1.0 1.0 XOR2 10 1.0 10.0 DFN0C0 4 1.0 4.0 DFN0E1C0 32 1.0 32.0 DFN0P0 4 1.0 4.0 DFN1C0 46 1.0 46.0 DFN1C1 1 1.0 1.0 DFN1E0C0 20 1.0 20.0 DFN1E1 16 1.0 16.0 DFN1E1C0 47 1.0 47.0 DFN1P0 8 1.0 8.0 ----- ---------- TOTAL 524 517.0 IO Cell usage: cell count BIBUF_LVCMOS12U 2 CLKBUF 2 INBUF 3 OUTBUF 3 ----- TOTAL 10 Core Cells : 517 of 3116 (17%) IO Cells : 10 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue Dec 16 16:45:35 2008 ###########################################################]