# vsim -l iglooplus presynth.top_spi_i2c 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.top_spi_i2c(def_arch)#1
# Loading work.my_spi_slave(default)#1
# Loading work.tinyi2c_master(behave)#1
# ** Warning: (vsim-3473) Component instance "sda_pin : bibuf_lvcmos12u" is not bound.
#    Time: 0 ps  Iteration: 0  Region: /top_spi_i2c/i2c_master_0  File: D:/Appsnotes/2008/SPI_to_I2C/Designs/Final/appsnote_design/SPI_I2C/hdl/TinyI2C_master.vhd
# ** Warning: (vsim-3473) Component instance "scl_pin : bibuf_lvcmos12u" is not bound.
#    Time: 0 ps  Iteration: 0  Region: /top_spi_i2c/i2c_master_0  File: D:/Appsnotes/2008/SPI_to_I2C/Designs/Final/appsnote_design/SPI_I2C/hdl/TinyI2C_master.vhd
# ** Warning: (vsim-3473) Component instance "sclclk : clkint" is not bound.
#    Time: 0 ps  Iteration: 0  Region: /top_spi_i2c/i2c_master_0  File: D:/Appsnotes/2008/SPI_to_I2C/Designs/Final/appsnote_design/SPI_I2C/hdl/TinyI2C_master.vhd
# ** Fatal: (vsim-3471) Slice range (-9 downto -16) does not belong to the prefix index range (31 downto 0).
#    Time: 0 ps  Iteration: 0  Process: /top_spi_i2c/state_i2c_proc File: D:/Appsnotes/2008/SPI_to_I2C/Designs/Final/appsnote_design/SPI_I2C/hdl/Top_spi_i2c.vhd
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design 
#        Pausing macro execution 
# MACRO ./run.do PAUSED at line 20
vsim presynth.tinyi2c_slave
# vsim presynth.tinyi2c_slave 
# ** Note: (vsim-3812) Design is being optimized...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.tinyi2c_slave(behave)#1
# Loading std.textio(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading iglooplus.bibuf_lvcmos33u(vital_act)#1
# Loading iglooplus.vtables
# Loading iglooplus.clkint(vital_act)#1
vsim presynth.top_spi_i2c
# vsim presynth.top_spi_i2c 
# Recursive kernel call. Cannot execute mti_CreateSecondChannel 2372.
vsim presynth.top_spi_i2c
# vsim presynth.top_spi_i2c 
# No client channel!No client channel!No client channel!Error loading design
# Error: No client channel!No client channel!No client channel!Error loading design 
#        Pausing macro execution 
# MACRO ./run.do PAUSED at line 20
vsim presynth.testbench
# vsim presynth.testbench 
# No client channel!No client channel!No client channel!Error loading design
# Error: No client channel!No client channel!No client channel!Error loading design 
#        Pausing macro execution 
# MACRO ./run.do PAUSED at line 20
quit -sim
