| Project Settings |
|---|
| Project Name | MC_System_top_syn | Implementation Name | synthesis |
| Top Module | work.MC_System_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
120 |
73 |
0 |
- |
00m:06s |
- |
01-12-2017
17:24:11 |
| (premap) | Complete |
107 |
18 |
0 |
0m:02s |
0m:03s |
179MB |
01-12-2017
17:24:16 |
| (fpga_mapper) | Complete |
11 |
48 |
0 |
0m:29s |
0m:30s |
277MB |
01-12-2017
17:24:46 |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 01-12-2017
17:24:13 |
| Area Summary |
|---|
| |
| Carry Cells | 2568 |
Sequential Cells | 4578 |
| DSP Blocks (MACC)
(dsp_used) | 12 |
I/O Cells | 35 |
| Global Clock Buffers | 3 |
LUTs
(total_luts) | 6835 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 93.9 MHz | -0.647 |
| MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock | 100.0 MHz | 139.4 MHz | 2.826 |
| System | 100.0 MHz | 1029.4 MHz | 9.029 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 2 |
| |
|