@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO106 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|Found ROM .delname. (in view: work.MC_System_sb(rtl)) with 16 words by 2 bits.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if.vhd":626:8:626:9|Removing sequential instance apb3_if_0.pwm_gain_val_o[0] (in view: work.Bldc_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":435:4:435:5|Removing sequential instance Stepper_Axis_0.apb3_if_st_0.seq_cntl_config_o[0] (in view: work.MC_System_top(rtl)) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":435:4:435:5|Removing sequential instance Stepper_Axis_0.apb3_if_st_0.seq_cntl_config_o[3] (in view: work.MC_System_top(rtl)) because it does not drive other instances.
@N: FP130 |Promoting Net MC_System_0_FIC_0_LOCK on CLKINT  I_171 
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
