--=============================================================================
-- File Name                           : apb3_if_st.vhd

-- Description                         : This module implements the APB3 slave
--                                       interface to communicate with APB3
--                                       master.

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2017 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING
-- RESTRICTIONS FROM MICROSEMI CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN
-- AUTHORIZATION FROM MICROSEMI FOR USE OF THIS FILE, THEN THE FILE SHOULD BE
-- IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=============================================================================

--=============================================================================
-- Libraries
--=============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

--=============================================================================
-- apb3_if_st entity declaration
--=============================================================================
ENTITY apb3_if_st IS
GENERIC (
-- Generic list
    -- Specifies pwdata_i,prdata_o signal width
    g_APB3_IF_DATA_WIDTH               : INTEGER := 32;

    -- Specifies the width of constants
    g_CONST_WIDTH                      : INTEGER := 12;

    -- Specifies the width of adc configuration register
    g_ADC_CONFIG_REG_WIDTH             : INTEGER := 5;

    -- Specifies width of all input and output ports
    g_STD_IO_WIDTH                     : INTEGER := 18
   );
PORT (
-- Port list
    -- APB reset
    preset_i                : IN  STD_LOGIC;

    -- APB clock
    pclk_i                  : IN  STD_LOGIC;

    -- APB slave interface
    psel_i                  : IN  STD_LOGIC;
    pwrite_i                : IN  STD_LOGIC;
    penable_i               : IN  STD_LOGIC;
    paddr_i                 : IN  STD_LOGIC_VECTOR(g_APB3_IF_DATA_WIDTH-1
                                                    DOWNTO 0);
    pwdata_i                : IN  STD_LOGIC_VECTOR(g_APB3_IF_DATA_WIDTH-1
                                                    DOWNTO 0);
    pready_o                : OUT STD_LOGIC;
    pslverr_o               : OUT STD_LOGIC;
    prdata_o                : OUT STD_LOGIC_VECTOR(g_APB3_IF_DATA_WIDTH-1
                                                    DOWNTO 0);

    -- Data Input specifies the ia input of Clarke module
    ia_clarke_in_i          : IN STD_LOGIC_VECTOR((G_STD_IO_WIDTH-1) DOWNTO 0);

    -- Data Input specifies the ib input of Clarke module
    ib_clarke_in_i          : IN STD_LOGIC_VECTOR((G_STD_IO_WIDTH-1) DOWNTO 0);

    -- Data Input specifies the id output of Park module
    id_park_output_i        : IN STD_LOGIC_VECTOR((G_STD_IO_WIDTH-1) DOWNTO 0);

    -- Data Input specifies the iq output of Park module
    iq_park_output_i        : IN STD_LOGIC_VECTOR((G_STD_IO_WIDTH-1) DOWNTO 0);

    -- Data Input specifies the valpha output of IPark module
    valpha_ipark_output_i   : IN STD_LOGIC_VECTOR((G_STD_IO_WIDTH-1) DOWNTO 0);

    -- Data Input specifies the vbeta output of IPark module
    vbeta_ipark_output_i    : IN STD_LOGIC_VECTOR((G_STD_IO_WIDTH-1) DOWNTO 0);

    -- Data Input specifies the output of ID PI controller
    id_pi_out_i             : IN STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Data Input specifies the output of IQ PI controller
    iq_pi_out_i             : IN STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Data Input specifies the step count value
    step_cnt_i              : IN STD_LOGIC_VECTOR(G_STD_IO_WIDTH+5 DOWNTO 0);

    -- Data Input specifies the output angle generated by the stepper theta
    -- gen block
    theta_out_i             : IN STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Data Input specifies the current sequence controller state
    state_i                 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

    -- Data Input specifies the raw ADC channel 0 value
    adc_ch0_val_i           : IN STD_LOGIC_VECTOR(11 DOWNTO 0);

    -- Data Input specifies the raw ADC channel 1 value
    adc_ch1_val_i           : IN STD_LOGIC_VECTOR(11 DOWNTO 0);

    -- Data Input specifies the raw ADC channel 2 value
    adc_ch2_val_i           : IN STD_LOGIC_VECTOR(11 DOWNTO 0);

    -- Data Input specifies the raw ADC channel 3 value
    adc_ch3_val_i           : IN STD_LOGIC_VECTOR(11 DOWNTO 0);

    -- Data Output specifies the Kp constant of current PI controller
    idq_pi_kp_o             : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Data Output specifies the Ki constant of current PI controller
    idq_pi_ki_o             : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Control Output specifies the start motor signal
    start_motor_o           : OUT STD_LOGIC ;

    -- Control Output specifies the stop motor signal
    stop_motor_o            : OUT STD_LOGIC ;

    -- Data Output specifies the sequence controller configuration value
    seq_cntl_config_o       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

    -- Data Output specifies the dv value for olmng block
    olmng_dv_o              : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH -1 DOWNTO 0);

    -- Data Output specifies the ADC configuration register value
    adc_control_reg_val_o   : OUT STD_LOGIC_VECTOR(G_ADC_CONFIG_REG_WIDTH-1
                                                    DOWNTO 0);
    -- Data Output specifies the ADC configuration value corresponding to
    -- channel 0
    adc_channel_ch0_o       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

    -- Data Output specifies the ADC configuration value corresponding to
    -- channel 1
    adc_channel_ch1_o       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

    -- Data Output specifies the ADC configuration value corresponding to
    -- channel 2
    adc_channel_ch2_o       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

    -- Data Output specifies the ADC configuration value corresponding to
    -- channel 3
    adc_channel_ch3_o       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

    -- Data Output specifies the scaling value for adc_scaling block
    adc_scale_val_o         : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH -1 DOWNTO 0);

    -- Data Output specifies the over-current threshold for the adc_scaling
    -- block
    adc_oc_thresh_o         : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH -1 DOWNTO 0);

    -- Data Output specifies the PWM period value
    pwm_period_val_o        : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH -1 DOWNTO 0);

    -- Data Output specifies the PWM dead time value
    pwm_dead_time_val_o     : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Data Output specifies the PWM delay time value
    pwm_delay_time_val_o    : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Control Output specifies the stepper theta gen block mode
    theta_gen_mode_o        : OUT STD_LOGIC;

    -- Data Output specifies the stepper theta gen slew count value
    theta_gen_slew_count_o  : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Data Output specifies the stepper theta gen rate limit value
    theta_gen_rate_limit_o  : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0);

    -- Data Output specifies the stepper theta gen command step number value
    theta_gen_cmd_step_no_o : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH+5 DOWNTO 0);

    -- Data Output specifies the current reference value
    id_ref_val_o            : OUT STD_LOGIC_VECTOR(G_STD_IO_WIDTH-1 DOWNTO 0)
);
END apb3_if_st;
--=============================================================================
-- apb3_if_st architecture body
--=============================================================================
ARCHITECTURE apb3_if_st OF apb3_if_st IS

--=============================================================================
-- Component declarations
--=============================================================================
--NA--

--=============================================================================
-- Synthesis Attributes
--=============================================================================
--NA--

--=============================================================================
-- Signal declarations
--=============================================================================
--ADC Register Addresses
CONSTANT C_ADC_CONFIG_REG_ADDR         : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"000";
CONSTANT C_CH0_CONFIG_VAL_ADDR         : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"004";
CONSTANT C_CH1_CONFIG_VAL_ADDR         : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"008";
CONSTANT C_CH2_CONFIG_VAL_ADDR         : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"00C";
CONSTANT C_CH3_CONFIG_VAL_ADDR         : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"010";
--ADC Scaling Register Addresses
CONSTANT C_ADC_SCALE_VAL_ADDR          : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"020";
CONSTANT C_OVER_CURRENT_THRESHOLD      : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"024";
--PWM Register Addresses
CONSTANT C_PWM_PERIOD_VAL_ADDR         : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"034";
CONSTANT C_PWM_DEAD_TIME_ADDR          : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"038";
CONSTANT C_PWM_DELAY_TIME_ADDR         : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"03C";
--Current PI Controller Register Addresses
CONSTANT C_IDQ_PI_KP_ADDR               : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"060";
CONSTANT C_IDQ_PI_KI_ADDR               : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"064";
--Sequence Manager Register Addresses
CONSTANT C_START_MOTOR_ADDR            : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"094";
CONSTANT C_SEQ_CNTL_CONFIG_ADDR        : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"09C";
CONSTANT C_OLMNG_IQ_REF_ADDR           : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"0A4";
CONSTANT C_STOP_MOTOR_ADDR             : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"0AC";
CONSTANT C_MC_FSM_STATE_ADDR           : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"0B0";
-- Stepper parameters
CONSTANT  C_THETA_GEN_SLEW_COUNT_ADDR  : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"700";
CONSTANT  C_THETA_GEN_RATE_LIMIT_ADDR  : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"704";
CONSTANT  C_THETA_GEN_CMD_STEP_NO_ADDR : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"708";
CONSTANT  C_THETA_GEN_MODE_ADDR        : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"70C";
CONSTANT  C_ID_REF_ADDR                : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"710";
--Plotting
CONSTANT C_IA_REG_ADDR                 : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"800";
CONSTANT C_IB_REG_ADDR                 : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"804";
CONSTANT C_ID_PARK_REG_ADDR            : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"810";
CONSTANT C_IQ_PARK_REG_ADDR            : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"814";
CONSTANT C_VALPHA_IPARK_REG_ADDR       : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"818";
CONSTANT C_VBETA_IPARK_REG_ADDR        : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"81C";
CONSTANT C_ID_PI_OUT_ADDR              : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"828";
CONSTANT C_IQ_PI_OUT_ADDR              : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"82C";
CONSTANT C_CH0_DATA_VAL_ADDR           : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"838";
CONSTANT C_CH1_DATA_VAL_ADDR           : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"83C";
CONSTANT C_CH2_DATA_VAL_ADDR           : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"840";
CONSTANT C_CH3_DATA_VAL_ADDR           : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"844";
--Stepper specific plotting
CONSTANT  C_STEP_CNT_ADDR              : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"E00";
CONSTANT  C_THETA_O_ADDR               : STD_LOGIC_VECTOR(g_CONST_WIDTH-1
                                                    DOWNTO 0) := x"E04";

BEGIN

--=============================================================================
-- Top level output port assignments
--=============================================================================
-- pready_o Is always ready,there will not be any latency from the Fabric
-- modules.
pready_o                              <= '1';
-- Slave error is always '0' as there will not be any slave error.
pslverr_o                             <= '0';

--=============================================================================
-- Generate blocks
--=============================================================================
--NA--

--=============================================================================
-- Asynchronous blocks
--=============================================================================
--------------------------------------------------------------------------
-- Name       : READ_DECODE_PROC
-- Description: Process implements the APB read operation
--------------------------------------------------------------------------
READ_DECODE_PROC:
    PROCESS(paddr_i,ia_clarke_in_i,ib_clarke_in_i,id_park_output_i,
            iq_park_output_i,valpha_ipark_output_i,vbeta_ipark_output_i,
            id_pi_out_i,iq_pi_out_i,adc_ch0_val_i,adc_ch1_val_i,adc_ch2_val_i,
            adc_ch3_val_i,step_cnt_i,theta_out_i, state_i)
BEGIN
    CASE  paddr_i(11 DOWNTO 0)  IS
--------------------
-- C_IA_REG_ADDR
--------------------
        WHEN C_IA_REG_ADDR =>
            prdata_o(g_STD_IO_WIDTH-1   DOWNTO 0) <= ia_clarke_in_i;
            prdata_o(g_APB3_IF_DATA_WIDTH-1 DOWNTO g_STD_IO_WIDTH)
                <= (OTHERS=>ia_clarke_in_i(17));
--------------------
-- C_IB_REG_ADDR
--------------------
        WHEN C_IB_REG_ADDR =>
            prdata_o(g_STD_IO_WIDTH-1   DOWNTO 0) <= ib_clarke_in_i;
            prdata_o(g_APB3_IF_DATA_WIDTH-1 DOWNTO g_STD_IO_WIDTH)
                <= (OTHERS=>ib_clarke_in_i(17));
--------------------
-- C_ID_PARK_REG_ADDR
--------------------
        WHEN C_ID_PARK_REG_ADDR =>
            prdata_o(g_STD_IO_WIDTH -1   DOWNTO 0)
                <= id_park_output_i(g_STD_IO_WIDTH -1 DOWNTO 0);
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO g_STD_IO_WIDTH)
                <= (OTHERS=>id_park_output_i(g_STD_IO_WIDTH -1));
--------------------
-- C_IQ_PARK_REG_ADDR
--------------------
        WHEN C_IQ_PARK_REG_ADDR =>
            prdata_o(g_STD_IO_WIDTH -1   DOWNTO 0)
                <= iq_park_output_i(g_STD_IO_WIDTH -1 DOWNTO 0);
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO g_STD_IO_WIDTH)
                <= (OTHERS=>iq_park_output_i(g_STD_IO_WIDTH -1));
--------------------
-- C_VALPHA_IPARK_REG_ADDR
--------------------
        WHEN C_VALPHA_IPARK_REG_ADDR =>
            prdata_o(g_STD_IO_WIDTH -1   DOWNTO 0)
                <= valpha_ipark_output_i(g_STD_IO_WIDTH -1 DOWNTO 0);
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO g_STD_IO_WIDTH)
                <= (OTHERS=>valpha_ipark_output_i(g_STD_IO_WIDTH -1));
--------------------
-- C_VBETA_IPARK_REG_ADDR
--------------------
        WHEN C_VBETA_IPARK_REG_ADDR =>
            prdata_o(g_STD_IO_WIDTH -1   DOWNTO 0)
                <= vbeta_ipark_output_i(g_STD_IO_WIDTH -1 DOWNTO 0);
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO g_STD_IO_WIDTH)
                <= (OTHERS=>vbeta_ipark_output_i(g_STD_IO_WIDTH -1));
--------------------
-- C_ID_PI_OUT_ADDR
--------------------
        WHEN C_ID_PI_OUT_ADDR =>
            prdata_o(g_STD_IO_WIDTH -1   DOWNTO 0) <= id_pi_out_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO g_STD_IO_WIDTH)
                <= (OTHERS=>id_pi_out_i(g_STD_IO_WIDTH -1));
--------------------
-- C_IQ_PI_OUT_ADDR
--------------------
        WHEN C_IQ_PI_OUT_ADDR =>
            prdata_o(g_STD_IO_WIDTH -1   DOWNTO 0) <= iq_pi_out_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO g_STD_IO_WIDTH)
                <= (OTHERS=>iq_pi_out_i(g_STD_IO_WIDTH -1));
--------------------
-- C_CH0_DATA_VAL_ADDR
--------------------
        WHEN C_CH0_DATA_VAL_ADDR =>
            prdata_o(11   DOWNTO 0) <= adc_ch0_val_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO 12) <= (OTHERS=>'0');
 --------------------
-- C_CH1_DATA_VAL_ADDR
--------------------
        WHEN C_CH1_DATA_VAL_ADDR =>
            prdata_o(11   DOWNTO 0) <= adc_ch1_val_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO 12) <= (OTHERS=>'0');
--------------------
-- C_CH2_DATA_VAL_ADDR
--------------------
        WHEN C_CH2_DATA_VAL_ADDR =>
            prdata_o(11   DOWNTO 0) <= adc_ch2_val_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO 12) <= (OTHERS=>'0');
--------------------
-- C_CH3_DATA_VAL_ADDR
--------------------
        WHEN C_CH3_DATA_VAL_ADDR =>
            prdata_o(11   DOWNTO 0) <= adc_ch3_val_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO 12) <= (OTHERS=>'0');
--------------------
-- C_MC_FSM_STATE_ADDR
--------------------
        WHEN C_MC_FSM_STATE_ADDR =>
            prdata_o(3   DOWNTO 0) <= state_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO 4) <= (OTHERS=>'0');
--------------------
-- C_STEP_CNT_ADDR
--------------------
        WHEN C_STEP_CNT_ADDR =>
            prdata_o(23 downto 0) <= step_cnt_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO 24)
                <= (OTHERS=> step_cnt_i(23));
--------------------
-- C_THETA_O_ADDR
--------------------
        WHEN  C_THETA_O_ADDR =>
            prdata_o(17 downto 0) <= theta_out_i;
            prdata_o(g_APB3_IF_DATA_WIDTH -1 DOWNTO 18)
                <= (OTHERS => theta_out_i(17));
--------------------
-- OTHERS
--------------------
        WHEN OTHERS =>
           prdata_o <= (OTHERS=>'0');
    END CASE;
END PROCESS;

--=============================================================================
-- Synchronous blocks
--=============================================================================
--------------------------------------------------------------------------
-- Name       : WRITE_DECODE_PROC
-- Description: Process implements the APB write operation
--------------------------------------------------------------------------
WRITE_DECODE_PROC:
    PROCESS (preset_i, pclk_i)
    BEGIN
    IF (preset_i = '0') THEN
        start_motor_o                        <= '0'            ;
        stop_motor_o                         <= '0'            ;
        seq_cntl_config_o                    <= (OTHERS => '0');
        adc_scale_val_o                      <= (OTHERS => '0');
        adc_oc_thresh_o                      <= (OTHERS => '0');
        adc_control_reg_val_o                <= (OTHERS => '0');
        adc_channel_ch0_o                    <= (OTHERS => '0');
        adc_channel_ch1_o                    <= (OTHERS => '0');
        adc_channel_ch2_o                    <= (OTHERS => '0');
        adc_channel_ch3_o                    <= (OTHERS => '0');
        olmng_dv_o                           <= (OTHERS => '0');
        pwm_dead_time_val_o                  <= (OTHERS => '0');
        pwm_period_val_o                     <= (OTHERS => '0');
        pwm_delay_time_val_o                 <= (OTHERS => '0');
        idq_pi_kp_o                          <= (OTHERS => '0');
        idq_pi_ki_o                          <= (OTHERS => '0');
        theta_gen_cmd_step_no_o              <= (OTHERS => '0');
        theta_gen_mode_o                     <= '0';
        theta_gen_rate_limit_o               <= (OTHERS => '0');
        theta_gen_slew_count_o               <= (OTHERS => '0');
        id_ref_val_o                         <= (OTHERS => '0');
    ELSIF (pclk_i'EVENT AND pclk_i = '1') THEN
        IF ((psel_i = '1') AND (pwrite_i = '1') AND (penable_i = '1')) THEN
            CASE paddr_i(11 DOWNTO 0)  IS
 --------------------
-- C_IDQ_PI_KP_ADDR
--------------------
                WHEN C_IDQ_PI_KP_ADDR =>
                    idq_pi_kp_o             <= pwdata_i(g_STD_IO_WIDTH-1
                                                            DOWNTO 0);
--------------------
-- C_IDQ_PI_KI_ADDR
--------------------
                WHEN C_IDQ_PI_KI_ADDR =>
                    idq_pi_ki_o             <= pwdata_i(g_STD_IO_WIDTH-1
                                                            DOWNTO 0);
--------------------
-- C_SEQ_CNTL_CONFIG_ADDR
--------------------
                WHEN C_SEQ_CNTL_CONFIG_ADDR =>
                    seq_cntl_config_o       <= pwdata_i(3 DOWNTO 0);
--------------------
-- C_OLMNG_IQ_REF_ADDR
--------------------
                WHEN C_OLMNG_IQ_REF_ADDR =>
                    olmng_dv_o              <= pwdata_i (g_STD_IO_WIDTH-1
                                                            DOWNTO 0);
--------------------
-- C_ADC_SCALE_VAL_ADDR
--------------------
                WHEN C_ADC_SCALE_VAL_ADDR  =>
                    adc_scale_val_o         <= pwdata_i (g_STD_IO_WIDTH-1
                                                            DOWNTO 0);
--------------------
-- C_OVER_CURRENT_THRESHOLD
--------------------
                WHEN C_OVER_CURRENT_THRESHOLD  =>
                    adc_oc_thresh_o         <= pwdata_i (g_STD_IO_WIDTH-1
                                                            DOWNTO 0);
--------------------
-- C_PWM_PERIOD_VAL_ADDR
--------------------
                WHEN C_PWM_PERIOD_VAL_ADDR =>
                    pwm_period_val_o        <= pwdata_i (g_STD_IO_WIDTH-1
                                                            DOWNTO 0);
--------------------
-- C_ADC_CONFIG_REG_ADDR
--------------------
                WHEN C_ADC_CONFIG_REG_ADDR  =>
                    adc_control_reg_val_o
                        <= pwdata_i(g_ADC_CONFIG_REG_WIDTH-1 DOWNTO 0);
--------------------
-- C_PWM_DEAD_TIME_ADDR
--------------------
                WHEN C_PWM_DEAD_TIME_ADDR   =>
                    pwm_dead_time_val_o     <= pwdata_i(g_STD_IO_WIDTH-1
                                                            DOWNTO 0);
--------------------
-- C_PWM_DELAY_TIME_ADDR
--------------------
                WHEN C_PWM_DELAY_TIME_ADDR   =>
                    pwm_delay_time_val_o    <= pwdata_i(g_STD_IO_WIDTH-1
                                                            DOWNTO 0);
--------------------
-- C_CH0_CONFIG_VAL_ADDR
--------------------
                WHEN C_CH0_CONFIG_VAL_ADDR =>
                    adc_channel_ch0_o       <= pwdata_i(15 DOWNTO 0);
--------------------
-- C_CH1_CONFIG_VAL_ADDR
--------------------
                WHEN C_CH1_CONFIG_VAL_ADDR =>
                    adc_channel_ch1_o       <= pwdata_i(15 DOWNTO 0);
--------------------
-- C_CH2_CONFIG_VAL_ADDR
--------------------
                WHEN C_CH2_CONFIG_VAL_ADDR =>
                    adc_channel_ch2_o       <= pwdata_i(15 DOWNTO 0);
--------------------
-- C_CH3_CONFIG_VAL_ADDR
--------------------
                WHEN C_CH3_CONFIG_VAL_ADDR =>
                    adc_channel_ch3_o       <= pwdata_i(15 DOWNTO 0);

-- stepper parameters
--------------------
-- C_THETA_GEN_CMD_STEP_NO_ADDR
--------------------
                WHEN C_THETA_GEN_CMD_STEP_NO_ADDR =>
                    theta_gen_cmd_step_no_o <= pwdata_i(23 DOWNTO 0);
--------------------
-- C_THETA_GEN_MODE_ADDR
--------------------
                WHEN C_THETA_GEN_MODE_ADDR =>
                    theta_gen_mode_o        <= pwdata_i(0);
--------------------
-- C_THETA_GEN_RATE_LIMIT_ADDR
--------------------
                WHEN C_THETA_GEN_RATE_LIMIT_ADDR =>
                    theta_gen_rate_limit_o  <= pwdata_i(17 DOWNTO 0);
--------------------
-- C_THETA_GEN_SLEW_COUNT_ADDR
--------------------
                WHEN C_THETA_GEN_SLEW_COUNT_ADDR =>
                    theta_gen_slew_count_o  <= pwdata_i(17 DOWNTO 0);
--------------------
-- C_ID_REF_ADDR
--------------------
               WHEN C_ID_REF_ADDR =>
                    id_ref_val_o            <= pwdata_i(17 DOWNTO 0);
--------------------
-- C_START_MOTOR_ADDR
--------------------
                WHEN C_START_MOTOR_ADDR =>
                    start_motor_o           <= pwdata_i(0);
--------------------
-- C_STOP_MOTOR_ADDR
--------------------
                WHEN C_STOP_MOTOR_ADDR =>
                    stop_motor_o            <= pwdata_i(0);
--------------------
-- OTHERS
--------------------
                WHEN OTHERS =>
                    NULL;
            END CASE;
        END IF;
    END IF;
END PROCESS;

--=============================================================================
-- Component Instantiations
--=============================================================================
--NA--

END ARCHITECTURE apb3_if_st;
