--=================================================================================================
-- File Name                           : rate_limiter.vhd

-- Description                         : This module implements a rate limiter.

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2016 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
--=================================================================================================
-- rate_limiter entity declaration
--=================================================================================================
ENTITY RATE_LIMITER IS
PORT (
--Port list
    -- system reset
    reset_i                            : IN  STD_LOGIC;

    -- system clock
    sys_clk_i                          : IN  STD_LOGIC;

    -- Control input specifies the start of rate limiter operation
    start_i                            : IN  STD_LOGIC;

    -- Control input enables the soft stop feature
    soft_stop_i                        : IN  STD_LOGIC;

    -- Control input resets the rate limiter output as part of auto-restart feature
    reset_rl_i                         : IN  STD_LOGIC;

    -- Control input specifies the motor direction
    direction_i                        : IN  STD_LOGIC;

    -- Control input specifies when the rate limiter output is updated
    slew_count_i                       : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);

    -- Control input specifies the rate at which the rate limiter output is incremented/decremented
    rate_count_i                       : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);

    -- Data input specifies the input reference value
    rl_in_i                            : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);

    -- Data output specifies the rate limiter output
    rl_out_o                           : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);

    -- Control output specifies the end of rate limiter operation
    rl_done_o                          : OUT STD_LOGIC
);
END rate_limiter;
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