Timing Report Max Delay Analysis

SmartTime Version Libero SoC v11.8 SP1
Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)
Date: Wed Oct 04 15:10:10 2017


Design: MC_System_top
Family: SmartFusion2
Die: M2S010
Package: 484 FBGA
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0                       
Period (ns):                9.154                                                                           
Frequency (MHz):            109.242                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -1.060                                                                          
External Hold (ns):         1.155                                                                           
Min Clock-To-Out (ns):      4.843                                                                           
Max Clock-To-Out (ns):      12.819                                                                          

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1                       
Period (ns):                7.990                                                                           
Frequency (MHz):            125.156                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -0.533                                                                          
External Hold (ns):         0.817                                                                           
Min Clock-To-Out (ns):      4.942                                                                           
Max Clock-To-Out (ns):      10.070                                                                          

Clock Domain:               MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT                     
Period (ns):                N/A                                                                             
Frequency (MHz):            N/A                                                                             
Required Period (ns):       20.000                                                                          
Required Frequency (MHz):   50.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

                            Input to Output                                                                 
Min Delay (ns):             N/A                                                                             
Max Delay (ns):             N/A                                                                             

END SUMMARY
-----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[11]:EN
  Delay (ns):                  8.513                                                                           
  Slack (ns):                  0.846                                                                           
  Arrival (ns):                13.003                                                                          
  Required (ns):               13.849                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.154                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[17]:EN
  Delay (ns):                  8.513                                                                           
  Slack (ns):                  0.846                                                                           
  Arrival (ns):                13.003                                                                          
  Required (ns):               13.849                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.154                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/pwm_gain_val_o[15]:EN
  Delay (ns):                  8.500                                                                           
  Slack (ns):                  0.885                                                                           
  Arrival (ns):                12.990                                                                          
  Required (ns):               13.875                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.115                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/pwm_gain_val_o[13]:EN
  Delay (ns):                  8.500                                                                           
  Slack (ns):                  0.896                                                                           
  Arrival (ns):                12.990                                                                          
  Required (ns):               13.886                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.104                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[16]:EN
  Delay (ns):                  8.396                                                                           
  Slack (ns):                  0.958                                                                           
  Arrival (ns):                12.886                                                                          
  Required (ns):               13.844                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.042                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Bldc_Axis_0/apb3_if_0/angle_ki_o[11]:EN
  data required time                             13.849    
  data arrival time                          -   13.003    
  slack                                          0.846     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.346          cell: ADLIB:MSS_010_IP
  5.836                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[13] (r)
               +     1.004          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[13]
  6.840                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[0]:B (r)
               +     0.143          cell: ADLIB:CFG4
  6.983                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[0]:Y (f)
               +     1.690          net: MC_System_0_AMBA_SLAVE_0_PSELx
  8.673                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:B (f)
               +     0.281          cell: ADLIB:CFG4
  8.954                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:Y (f)
               +     0.916          net: Bldc_Axis_0/apb3_if_0/N_1807
  9.870                        Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:D (f)
               +     0.287          cell: ADLIB:CFG4
  10.157                       Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:Y (f)
               +     0.972          net: Bldc_Axis_0/apb3_if_0/N_1819
  11.129                       Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG3
  11.216                       Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa_0_a2:Y (f)
               +     1.787          net: Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa
  13.003                       Bldc_Axis_0/apb3_if_0/angle_ki_o[11]:EN (f)
                                    
  13.003                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.281          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  13.427                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An (f)
               +     0.250          cell: ADLIB:RGB
  13.677                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YR (r)
               +     0.480          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbr_net_1
  14.157                       Bldc_Axis_0/apb3_if_0/angle_ki_o[11]:CLK (r)
               -     0.308          Library setup time: ADLIB:SLE
  13.849                       Bldc_Axis_0/apb3_if_0/angle_ki_o[11]:EN
                                    
  13.849                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A0_ADC_SDI_I
  To:                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  2.813                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                2.813                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.174                                                                           
  External Setup (ns):         -1.060                                                                          


Expanded Path 1
  From: A0_ADC_SDI_I
  To: Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   2.813     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A0_ADC_SDI_I (f)
               +     0.000          net: A0_ADC_SDI_I
  0.000                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.392          net: A0_ADC_SDI_I_ibuf/U0/YIN1
  1.792                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.159          cell: ADLIB:IOINFF_BYPASS
  1.951                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     0.862          net: A0_ADC_SDI_I_c
  2.813                        Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  2.813                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.160          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.268          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12:YR (r)
               +     0.485          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12_rgbr_net_1
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.174          Library setup time: ADLIB:SLE
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Bldc_Axis_0/MSC_i_11/s_state[8]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  8.654                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                12.819                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           12.819                                                                          

Path 2
  From:                        Bldc_Axis_0/MSC_i_11/s_state[0]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  8.597                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                12.760                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           12.760                                                                          

Path 3
  From:                        Bldc_Axis_0/MSC_i_11/s_state[7]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  8.263                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                12.428                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           12.428                                                                          

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_STP
  Delay (ns):                  6.768                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.258                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.258                                                                          

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_DATA[0]
  Delay (ns):                  6.758                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.248                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.248                                                                          


Expanded Path 1
  From: Bldc_Axis_0/MSC_i_11/s_state[8]:CLK
  To: A0_RUNNING_LED
  data required time                             N/C       
  data arrival time                          -   12.819    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.280          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.426                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An (f)
               +     0.251          cell: ADLIB:RGB
  3.677                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YL (r)
               +     0.488          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbl_net_1
  4.165                        Bldc_Axis_0/MSC_i_11/s_state[8]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.252                        Bldc_Axis_0/MSC_i_11/s_state[8]:Q (r)
               +     0.841          net: Bldc_Axis_0/MSC_i_11/MSC_net_83
  5.093                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:B (r)
               +     0.143          cell: ADLIB:CFG2
  5.236                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:Y (f)
               +     0.232          net: Bldc_Axis_0/MSC_i_11/MSC_net_285
  5.468                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.555                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:Y (f)
               +     3.531          net: A0_PWM_UL_O_c
  9.086                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  9.416                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:Y (f)
               +     0.701          net: A0_RUNNING_LED_obuf/U0/DOUT
  10.117                       A0_RUNNING_LED_obuf/U0/U_IOPAD:D (f)
               +     2.702          cell: ADLIB:IOPAD_TRI
  12.819                       A0_RUNNING_LED_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A0_RUNNING_LED
  12.819                       A0_RUNNING_LED (f)
                                    
  12.819                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A0_RUNNING_LED (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/state_o_Z[3]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  Delay (ns):                  5.444                                                                           
  Slack (ns):                  4.422                                                                           
  Arrival (ns):                9.629                                                                           
  Required (ns):               14.051                                                                          
  Setup (ns):                  0.433                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[2]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[2]
  Delay (ns):                  5.640                                                                           
  Slack (ns):                  4.450                                                                           
  Arrival (ns):                9.824                                                                           
  Required (ns):               14.274                                                                          
  Setup (ns):                  0.210                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[5]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[5]
  Delay (ns):                  5.415                                                                           
  Slack (ns):                  4.656                                                                           
  Arrival (ns):                9.584                                                                           
  Required (ns):               14.240                                                                          
  Setup (ns):                  0.244                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_47/MSC_i_50/iq_pi_output_y_o[11]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[11]
  Delay (ns):                  5.333                                                                           
  Slack (ns):                  4.726                                                                           
  Arrival (ns):                9.507                                                                           
  Required (ns):               14.233                                                                          
  Setup (ns):                  0.251                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_47/MSC_i_50/id_pi_output_y_o[3]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  Delay (ns):                  5.148                                                                           
  Slack (ns):                  4.729                                                                           
  Arrival (ns):                9.322                                                                           
  Required (ns):               14.051                                                                          
  Setup (ns):                  0.433                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/state_o_Z[3]:CLK
  To: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  data required time                             14.051    
  data arrival time                          -   9.629     
  slack                                          4.422     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.288          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.435                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9:An (f)
               +     0.251          cell: ADLIB:RGB
  3.686                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9:YL (r)
               +     0.499          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9_rgbl_net_1
  4.185                        Stepper_Axis_0/MSC_i_42/state_o_Z[3]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.272                        Stepper_Axis_0/MSC_i_42/state_o_Z[3]:Q (r)
               +     1.932          net: Stepper_Axis_0_SEQ_CONTROLLER_1_state_o_0[3]
  6.204                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_5:A (r)
               +     0.225          cell: ADLIB:CFG4
  6.429                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_5:Y (f)
               +     0.217          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_5_Z
  6.646                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9:A (f)
               +     0.164          cell: ADLIB:CFG3
  6.810                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9:Y (f)
               +     1.002          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9_Z
  7.812                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0:C (f)
               +     0.087          cell: ADLIB:CFG3
  7.899                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0:Y (f)
               +     0.224          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_N_12_mux_0
  8.123                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_RNINQHB1:D (f)
               +     0.099          cell: ADLIB:CFG4
  8.222                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_RNINQHB1:Y (r)
               +     0.090          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_N_8_0_i_1
  8.312                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m3_0_a3_5_RNII15M2:C (r)
               +     0.074          cell: ADLIB:CFG4
  8.386                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m3_0_a3_5_RNII15M2:Y (r)
               +     0.827          net: MC_System_0/MC_System_sb_0/PRDATA_N_8_0_i
  9.213                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:A (r)
               +     0.194          cell: ADLIB:IP_INTERFACE
  9.407                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:IPA (r)
               +     0.222          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[3]
  9.629                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3] (r)
                                    
  9.629                        data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  13.430                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  13.680                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  14.065                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  14.274                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.210          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  14.484                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               -     0.433          Library setup time: ADLIB:MSS_010_IP
  14.051                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
                                    
  14.051                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

SET Register to Register

Path 1
  From:                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[15]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[15]:D
  Delay (ns):                  7.718                                                                           
  Slack (ns):                  2.010                                                                           
  Arrival (ns):                11.925                                                                          
  Required (ns):               13.935                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.990                                                                           

Path 2
  From:                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[15]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[11]:D
  Delay (ns):                  7.718                                                                           
  Slack (ns):                  2.011                                                                           
  Arrival (ns):                11.925                                                                          
  Required (ns):               13.936                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.989                                                                           

Path 3
  From:                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[15]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[5]:D
  Delay (ns):                  7.574                                                                           
  Slack (ns):                  2.144                                                                           
  Arrival (ns):                11.781                                                                          
  Required (ns):               13.925                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.856                                                                           

Path 4
  From:                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[15]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[13]:D
  Delay (ns):                  7.575                                                                           
  Slack (ns):                  2.153                                                                           
  Arrival (ns):                11.782                                                                          
  Required (ns):               13.935                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.847                                                                           

Path 5
  From:                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[15]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:D
  Delay (ns):                  7.575                                                                           
  Slack (ns):                  2.154                                                                           
  Arrival (ns):                11.782                                                                          
  Required (ns):               13.936                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.846                                                                           


Expanded Path 1
  From: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[15]:CLK
  To: Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[15]:D
  data required time                             13.935    
  data arrival time                          -   11.925    
  slack                                          2.010     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.436                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB10:An (f)
               +     0.251          cell: ADLIB:RGB
  3.687                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB10:YL (r)
               +     0.520          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB10_rgbl_net_1
  4.207                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[15]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.294                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[15]:Q (r)
               +     1.338          net: Stepper_Axis_0/apb3_if_st_0_sqmng_dv_o[15]
  5.632                        Stepper_Axis_0/MSC_i_47/MSC_i_50/s_pi_sel_RNIVHDL[1]:B (r)
               +     0.158          cell: ADLIB:CFG2
  5.790                        Stepper_Axis_0/MSC_i_47/MSC_i_50/s_pi_sel_RNIVHDL[1]:Y (r)
               +     0.714          net: Stepper_Axis_0/MSC_i_47/MSC_net_453
  6.504                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIEV4HK[25]:D (r)
               +     0.235          cell: ADLIB:ARI1_CC
  6.739                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIEV4HK[25]:UB (f)
               +     0.000          net: NET_CC_CONFIG6776
  6.739                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:UB[6] (f)
               +     0.538          cell: ADLIB:CC_CONFIG
  7.277                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:CO (r)
               +     0.000          net: CI_TO_CO6728
  7.277                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_2:CI (r)
               +     0.158          cell: ADLIB:CC_CONFIG
  7.435                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_2:CC[3] (r)
               +     0.000          net: NET_CC_CONFIG6804
  7.435                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNITIAR01[34]:CC (r)
               +     0.066          cell: ADLIB:ARI1_CC
  7.501                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNITIAR01[34]:S (r)
               +     1.218          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_232
  8.719                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_24_RNO:A (r)
               +     0.100          cell: ADLIB:CFG1
  8.819                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_24_RNO:Y (f)
               +     0.617          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_265
  9.436                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_24:A (f)
               +     0.134          cell: ADLIB:ARI1_CC
  9.570                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_24:P (r)
               +     0.000          net: NET_CC_CONFIG951
  9.570                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:P[8] (r)
               +     0.365          cell: ADLIB:CC_CONFIG
  9.935                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:CO (r)
               +     0.000          net: CI_TO_CO926
  9.935                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CI (r)
               +     0.292          cell: ADLIB:CC_CONFIG
  10.227                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CC[7] (r)
               +     0.000          net: NET_CC_CONFIG986
  10.227                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CC (r)
               +     0.066          cell: ADLIB:FCEND_BUFF_CC
  10.293                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CO (r)
               +     0.831          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_945
  11.124                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:B (r)
               +     0.100          cell: ADLIB:CFG2
  11.224                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:Y (f)
               +     0.528          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_1054
  11.752                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[15]:B (f)
               +     0.099          cell: ADLIB:CFG4
  11.851                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[15]:Y (r)
               +     0.074          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_667
  11.925                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[15]:D (r)
                                    
  11.925                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.436                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB12:An (f)
               +     0.251          cell: ADLIB:RGB
  13.687                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB12:YL (r)
               +     0.502          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB12_rgbl_net_1
  14.189                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[15]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.935                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[15]:D
                                    
  13.935                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A1_ADC_SDI_I
  To:                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  3.353                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                3.353                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.174                                                                           
  External Setup (ns):         -0.533                                                                          


Expanded Path 1
  From: A1_ADC_SDI_I
  To: Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   3.353     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A1_ADC_SDI_I (f)
               +     0.000          net: A1_ADC_SDI_I
  0.000                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.112          net: A1_ADC_SDI_I_ibuf/U0/YIN1
  1.512                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.141          cell: ADLIB:IOINFF_BYPASS
  1.653                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     1.700          net: A1_ADC_SDI_I_c
  3.353                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  3.353                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.161          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.280          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB12:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB12:YR (r)
               +     0.485          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB12_rgbr_net_1
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.174          Library setup time: ADLIB:SLE
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sck:CLK
  To:                          A1_ADC_SCK_O
  Delay (ns):                  5.901                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                10.070                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           10.070                                                                          

Path 2
  From:                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_cs_n:CLK
  To:                          A1_ADC_CS_O
  Delay (ns):                  5.874                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                10.043                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           10.043                                                                          

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  5.033                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.224                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.224                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  4.922                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.112                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.112                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  4.850                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.041                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.041                                                                           


Expanded Path 1
  From: Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sck:CLK
  To: A1_ADC_SCK_O
  data required time                             N/C       
  data arrival time                          -   10.070    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.292          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.439                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB17:An (f)
               +     0.250          cell: ADLIB:RGB
  3.689                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB17:YR (r)
               +     0.480          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB17_rgbr_net_1
  4.169                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sck:CLK (r)
               +     0.108          cell: ADLIB:SLE
  4.277                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sck:Q (f)
               +     2.354          net: A1_ADC_SCK_O_c
  6.631                        A1_ADC_SCK_O_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  6.961                        A1_ADC_SCK_O_obuf/U0/U_IOOUTFF:Y (f)
               +     0.699          net: A1_ADC_SCK_O_obuf/U0/DOUT
  7.660                        A1_ADC_SCK_O_obuf/U0/U_IOPAD:D (f)
               +     2.410          cell: ADLIB:IOPAD_TRI
  10.070                       A1_ADC_SCK_O_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A1_ADC_SCK_O
  10.070                       A1_ADC_SCK_O (f)
                                    
  10.070                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A1_ADC_SCK_O (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[6]:EN
  Delay (ns):                  8.457                                                                           
  Slack (ns):                  0.969                                                                           
  Arrival (ns):                12.947                                                                          
  Required (ns):               13.916                                                                          
  Setup (ns):                  0.254                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[0]:EN
  Delay (ns):                  8.457                                                                           
  Slack (ns):                  0.981                                                                           
  Arrival (ns):                12.947                                                                          
  Required (ns):               13.928                                                                          
  Setup (ns):                  0.254                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[8]:EN
  Delay (ns):                  8.457                                                                           
  Slack (ns):                  0.982                                                                           
  Arrival (ns):                12.947                                                                          
  Required (ns):               13.929                                                                          
  Setup (ns):                  0.254                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/theta_gen_slew_count_o[10]:EN
  Delay (ns):                  8.273                                                                           
  Slack (ns):                  1.168                                                                           
  Arrival (ns):                12.763                                                                          
  Required (ns):               13.931                                                                          
  Setup (ns):                  0.254                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/theta_gen_slew_count_o[8]:EN
  Delay (ns):                  8.273                                                                           
  Slack (ns):                  1.168                                                                           
  Arrival (ns):                12.763                                                                          
  Required (ns):               13.931                                                                          
  Setup (ns):                  0.254                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[6]:EN
  data required time                             13.916    
  data arrival time                          -   12.947    
  slack                                          0.969     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.327          cell: ADLIB:MSS_010_IP
  5.817                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[13] (f)
               +     0.999          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[13]
  6.816                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:B (f)
               +     0.147          cell: ADLIB:CFG4
  6.963                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:Y (r)
               +     1.249          net: MC_System_0_AMBA_SLAVE_1_PSELx
  8.212                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:B (r)
               +     0.158          cell: ADLIB:CFG4
  8.370                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:Y (r)
               +     0.241          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_1
  8.611                        Stepper_Axis_0/apb3_if_st_0/idq_pi_ki_o_1_sqmuxa_7:C (r)
               +     0.202          cell: ADLIB:CFG3
  8.813                        Stepper_Axis_0/apb3_if_st_0/idq_pi_ki_o_1_sqmuxa_7:Y (r)
               +     0.626          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_7
  9.439                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_0:B (r)
               +     0.202          cell: ADLIB:CFG2
  9.641                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_0:Y (r)
               +     0.755          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_0_Z
  10.396                       Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa:D (r)
               +     0.270          cell: ADLIB:CFG4
  10.666                       Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa:Y (r)
               +     2.281          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_Z
  12.947                       Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[6]:EN (r)
                                    
  12.947                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.288          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.435                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9:An (f)
               +     0.251          cell: ADLIB:RGB
  13.686                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9:YL (r)
               +     0.484          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9_rgbl_net_1
  14.170                       Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[6]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.916                       Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[6]:EN
                                    
  13.916                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

No Path 

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path 

END SET Input to Output

----------------------------------------------------

Path set User Sets

