Timing Report Max Delay Analysis

SmartTime Version Libero SoC v11.8 SP1
Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)
Date: Wed Oct 04 15:26:47 2017


Design: MC_System_top
Family: SmartFusion2
Die: M2S010
Package: 484 FBGA
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0                       
Period (ns):                9.786                                                                           
Frequency (MHz):            102.187                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -0.848                                                                          
External Hold (ns):         1.030                                                                           
Min Clock-To-Out (ns):      4.843                                                                           
Max Clock-To-Out (ns):      11.491                                                                          

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1                       
Period (ns):                8.190                                                                           
Frequency (MHz):            122.100                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -0.852                                                                          
External Hold (ns):         1.003                                                                           
Min Clock-To-Out (ns):      4.966                                                                           
Max Clock-To-Out (ns):      10.290                                                                          

Clock Domain:               MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT                     
Period (ns):                N/A                                                                             
Frequency (MHz):            N/A                                                                             
Required Period (ns):       20.000                                                                          
Required Frequency (MHz):   50.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

                            Input to Output                                                                 
Min Delay (ns):             N/A                                                                             
Max Delay (ns):             N/A                                                                             

END SUMMARY
-----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/Rs_pu_o[17]:EN
  Delay (ns):                  9.204                                                                           
  Slack (ns):                  0.214                                                                           
  Arrival (ns):                13.694                                                                          
  Required (ns):               13.908                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.786                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/Rs_pu_o[11]:EN
  Delay (ns):                  9.204                                                                           
  Slack (ns):                  0.226                                                                           
  Arrival (ns):                13.694                                                                          
  Required (ns):               13.920                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.774                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/Rs_pu_o[14]:EN
  Delay (ns):                  9.005                                                                           
  Slack (ns):                  0.412                                                                           
  Arrival (ns):                13.495                                                                          
  Required (ns):               13.907                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.588                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/Rs_pu_o[12]:EN
  Delay (ns):                  9.005                                                                           
  Slack (ns):                  0.412                                                                           
  Arrival (ns):                13.495                                                                          
  Required (ns):               13.907                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.588                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/Rs_pu_o[13]:EN
  Delay (ns):                  9.005                                                                           
  Slack (ns):                  0.424                                                                           
  Arrival (ns):                13.495                                                                          
  Required (ns):               13.919                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.576                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Bldc_Axis_0/apb3_if_0/Rs_pu_o[17]:EN
  data required time                             13.908    
  data arrival time                          -   13.694    
  slack                                          0.214     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.279          cell: ADLIB:MSS_010_IP
  5.769                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[15] (f)
               +     0.831          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[15]
  6.600                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:B (f)
               +     0.147          cell: ADLIB:CFG2
  6.747                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:Y (r)
               +     0.231          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/AMBA_SLAVE_0_PSELS0_i_2
  6.978                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[0]:D (r)
               +     0.074          cell: ADLIB:CFG4
  7.052                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[0]:Y (r)
               +     1.522          net: MC_System_0_AMBA_SLAVE_0_PSELx
  8.574                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:B (r)
               +     0.074          cell: ADLIB:CFG4
  8.648                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:Y (r)
               +     0.873          net: Bldc_Axis_0/apb3_if_0/N_1807
  9.521                        Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:D (r)
               +     0.270          cell: ADLIB:CFG4
  9.791                        Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:Y (r)
               +     1.918          net: Bldc_Axis_0/apb3_if_0/N_1819
  11.709                       Bldc_Axis_0/apb3_if_0/Rs_pu_o_1_sqmuxa_0_a2:A (r)
               +     0.158          cell: ADLIB:CFG2
  11.867                       Bldc_Axis_0/apb3_if_0/Rs_pu_o_1_sqmuxa_0_a2:Y (r)
               +     1.827          net: Bldc_Axis_0/apb3_if_0/Rs_pu_o_1_sqmuxa
  13.694                       Bldc_Axis_0/apb3_if_0/Rs_pu_o[17]:EN (r)
                                    
  13.694                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.281          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  13.427                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An (f)
               +     0.250          cell: ADLIB:RGB
  13.677                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YR (r)
               +     0.485          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbr_net_1
  14.162                       Bldc_Axis_0/apb3_if_0/Rs_pu_o[17]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.908                       Bldc_Axis_0/apb3_if_0/Rs_pu_o[17]:EN
                                    
  13.908                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A0_ADC_SDI_I
  To:                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  3.026                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                3.026                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.174                                                                           
  External Setup (ns):         -0.848                                                                          


Expanded Path 1
  From: A0_ADC_SDI_I
  To: Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   3.026     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A0_ADC_SDI_I (f)
               +     0.000          net: A0_ADC_SDI_I
  0.000                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.392          net: A0_ADC_SDI_I_ibuf/U0/YIN1
  1.792                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.159          cell: ADLIB:IOINFF_BYPASS
  1.951                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     1.075          net: A0_ADC_SDI_I_c
  3.026                        Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  3.026                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.160          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.268          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12:YR (r)
               +     0.486          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB12_rgbr_net_1
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.174          Library setup time: ADLIB:SLE
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Bldc_Axis_0/MSC_i_11/s_state[0]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  7.329                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.491                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.491                                                                          

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_STP
  Delay (ns):                  6.768                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.258                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.258                                                                          

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_DATA[0]
  Delay (ns):                  6.758                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.248                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.248                                                                          

Path 4
  From:                        Bldc_Axis_0/MSC_i_11/s_state[8]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  7.065                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.225                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.225                                                                          

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_DATA[3]
  Delay (ns):                  6.497                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                10.987                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           10.987                                                                          


Expanded Path 1
  From: Bldc_Axis_0/MSC_i_11/s_state[0]:CLK
  To: A0_RUNNING_LED
  data required time                             N/C       
  data arrival time                          -   11.491    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn (f)
               +     0.278          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth
  3.425                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16:An (f)
               +     0.251          cell: ADLIB:RGB
  3.676                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16:YL (r)
               +     0.486          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16_rgbl_net_1
  4.162                        Bldc_Axis_0/MSC_i_11/s_state[0]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.249                        Bldc_Axis_0/MSC_i_11/s_state[0]:Q (r)
               +     0.669          net: Bldc_Axis_0/MSC_i_11/MSC_net_265
  4.918                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:A (r)
               +     0.143          cell: ADLIB:CFG2
  5.061                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:Y (f)
               +     0.229          net: Bldc_Axis_0/MSC_i_11/MSC_net_285
  5.290                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.377                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:Y (f)
               +     2.381          net: A0_PWM_UL_O_c
  7.758                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  8.088                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:Y (f)
               +     0.701          net: A0_RUNNING_LED_obuf/U0/DOUT
  8.789                        A0_RUNNING_LED_obuf/U0/U_IOPAD:D (f)
               +     2.702          cell: ADLIB:IOPAD_TRI
  11.491                       A0_RUNNING_LED_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A0_RUNNING_LED
  11.491                       A0_RUNNING_LED (f)
                                    
  11.491                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A0_RUNNING_LED (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

Path 1
  From:                        Stepper_Axis_0/MSC_i_43/s_ia[3]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  Delay (ns):                  5.900                                                                           
  Slack (ns):                  3.974                                                                           
  Arrival (ns):                10.077                                                                          
  Required (ns):               14.051                                                                          
  Setup (ns):                  0.433                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[2]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[2]
  Delay (ns):                  5.999                                                                           
  Slack (ns):                  4.091                                                                           
  Arrival (ns):                10.183                                                                          
  Required (ns):               14.274                                                                          
  Setup (ns):                  0.210                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[3]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  Delay (ns):                  5.770                                                                           
  Slack (ns):                  4.098                                                                           
  Arrival (ns):                9.953                                                                           
  Required (ns):               14.051                                                                          
  Setup (ns):                  0.433                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_43/s_ia[2]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[2]
  Delay (ns):                  5.866                                                                           
  Slack (ns):                  4.219                                                                           
  Arrival (ns):                10.055                                                                          
  Required (ns):               14.274                                                                          
  Setup (ns):                  0.210                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[0]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[0]
  Delay (ns):                  5.389                                                                           
  Slack (ns):                  4.622                                                                           
  Arrival (ns):                9.563                                                                           
  Required (ns):               14.185                                                                          
  Setup (ns):                  0.299                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_43/s_ia[3]:CLK
  To: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  data required time                             14.051    
  data arrival time                          -   10.077    
  slack                                          3.974     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.288          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.435                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:An (f)
               +     0.250          cell: ADLIB:RGB
  3.685                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:YR (r)
               +     0.492          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13_rgbr_net_1
  4.177                        Stepper_Axis_0/MSC_i_43/s_ia[3]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.264                        Stepper_Axis_0/MSC_i_43/s_ia[3]:Q (r)
               +     1.470          net: Stepper_Axis_0_ADC_SCALING_0_ia_adc_o[3]
  5.734                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_tz:B (r)
               +     0.336          cell: ADLIB:CFG4
  6.070                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_tz:Y (f)
               +     0.442          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_tz_Z
  6.512                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_0:A (f)
               +     0.209          cell: ADLIB:CFG4
  6.721                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_0:Y (f)
               +     0.221          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_0_Z
  6.942                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9:C (f)
               +     0.164          cell: ADLIB:CFG3
  7.106                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9:Y (f)
               +     0.428          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9_Z
  7.534                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0:C (f)
               +     0.164          cell: ADLIB:CFG3
  7.698                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0:Y (f)
               +     0.636          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_N_12_mux_0
  8.334                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_RNINQHB1:D (f)
               +     0.099          cell: ADLIB:CFG4
  8.433                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_RNINQHB1:Y (r)
               +     0.090          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_N_8_0_i_1
  8.523                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m3_0_a3_5_RNII15M2:C (r)
               +     0.074          cell: ADLIB:CFG4
  8.597                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m3_0_a3_5_RNII15M2:Y (r)
               +     1.064          net: MC_System_0/MC_System_sb_0/PRDATA_N_8_0_i
  9.661                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:A (r)
               +     0.194          cell: ADLIB:IP_INTERFACE
  9.855                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:IPA (r)
               +     0.222          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[3]
  10.077                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3] (r)
                                    
  10.077                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  13.430                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  13.680                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  14.065                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  14.274                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.210          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  14.484                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               -     0.433          Library setup time: ADLIB:MSS_010_IP
  14.051                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
                                    
  14.051                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

SET Register to Register

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/s_state[4]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[4]:D
  Delay (ns):                  7.947                                                                           
  Slack (ns):                  1.810                                                                           
  Arrival (ns):                12.132                                                                          
  Required (ns):               13.942                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.190                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_42/s_state[3]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[4]:D
  Delay (ns):                  7.909                                                                           
  Slack (ns):                  1.838                                                                           
  Arrival (ns):                12.104                                                                          
  Required (ns):               13.942                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.162                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[4]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[40]:D
  Delay (ns):                  7.848                                                                           
  Slack (ns):                  1.875                                                                           
  Arrival (ns):                12.033                                                                          
  Required (ns):               13.908                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.125                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[4]:D
  Delay (ns):                  7.872                                                                           
  Slack (ns):                  1.875                                                                           
  Arrival (ns):                12.067                                                                          
  Required (ns):               13.942                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.125                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_42/s_state[4]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[37]:D
  Delay (ns):                  7.847                                                                           
  Slack (ns):                  1.876                                                                           
  Arrival (ns):                12.032                                                                          
  Required (ns):               13.908                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.124                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/s_state[4]:CLK
  To: Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[4]:D
  data required time                             13.942    
  data arrival time                          -   12.132    
  slack                                          1.810     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.436                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB14:An (f)
               +     0.251          cell: ADLIB:RGB
  3.687                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB14:YL (r)
               +     0.498          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB14_rgbl_net_1
  4.185                        Stepper_Axis_0/MSC_i_42/s_state[4]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  4.293                        Stepper_Axis_0/MSC_i_42/s_state[4]:Q (f)
               +     0.321          net: Stepper_Axis_0/MSC_i_42/MSC_net_84
  4.614                        Stepper_Axis_0/MSC_i_42/s_state_RNIRILT[4]:A (f)
               +     0.209          cell: ADLIB:CFG4
  4.823                        Stepper_Axis_0/MSC_i_42/s_state_RNIRILT[4]:Y (f)
               +     0.343          net: Stepper_Axis_0/SEQ_CONTROLLER_1_en_idq_pi_o
  5.166                        Stepper_Axis_0/MSC_i_47/MSC_i_50/en_o:B (f)
               +     0.087          cell: ADLIB:CFG3
  5.253                        Stepper_Axis_0/MSC_i_47/MSC_i_50/en_o:Y (f)
               +     0.986          net: Stepper_Axis_0/MSC_i_47/MSC_net_516
  6.239                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]:B (f)
               +     0.231          cell: ADLIB:ARI1_CC
  6.470                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]:UB (r)
               +     0.000          net: NET_CC_CONFIG6728
  6.470                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_0:UB[0] (r)
               +     0.701          cell: ADLIB:CC_CONFIG
  7.171                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_0:CO (f)
               +     0.000          net: CI_TO_CO6725
  7.171                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:CI (f)
               +     0.185          cell: ADLIB:CC_CONFIG
  7.356                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:CO (f)
               +     0.000          net: CI_TO_CO6726
  7.356                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_2:CI (f)
               +     0.194          cell: ADLIB:CC_CONFIG
  7.550                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_2:CC[1] (f)
               +     0.000          net: NET_CC_CONFIG6804
  7.550                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIBD5721[35]:CC (f)
               +     0.056          cell: ADLIB:ARI1_CC
  7.606                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIBD5721[35]:S (r)
               +     1.356          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_231
  8.962                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_25_RNO:A (r)
               +     0.100          cell: ADLIB:CFG1
  9.062                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_25_RNO:Y (f)
               +     0.425          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_264
  9.487                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_25:A (f)
               +     0.121          cell: ADLIB:ARI1_CC
  9.608                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_25:P (f)
               +     0.000          net: NET_CC_CONFIG954
  9.608                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:P[9] (f)
               +     0.345          cell: ADLIB:CC_CONFIG
  9.953                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:CO (r)
               +     0.000          net: CI_TO_CO926
  9.953                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CI (r)
               +     0.292          cell: ADLIB:CC_CONFIG
  10.245                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CC[7] (r)
               +     0.000          net: NET_CC_CONFIG986
  10.245                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CC (r)
               +     0.066          cell: ADLIB:FCEND_BUFF_CC
  10.311                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CO (r)
               +     0.920          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_945
  11.231                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:B (r)
               +     0.100          cell: ADLIB:CFG2
  11.331                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:Y (f)
               +     0.642          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_1054
  11.973                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[4]:B (f)
               +     0.095          cell: ADLIB:CFG4
  12.068                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[4]:Y (r)
               +     0.064          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_678
  12.132                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[4]:D (r)
                                    
  12.132                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.287          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.434                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB11:An (f)
               +     0.251          cell: ADLIB:RGB
  13.685                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB11:YL (r)
               +     0.511          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB11_rgbl_net_1
  14.196                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[4]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.942                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[4]:D
                                    
  13.942                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A1_ADC_SDI_I
  To:                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  3.062                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                3.062                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.165                                                                           
  External Setup (ns):         -0.852                                                                          


Expanded Path 1
  From: A1_ADC_SDI_I
  To: Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   3.062     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A1_ADC_SDI_I (f)
               +     0.000          net: A1_ADC_SDI_I
  0.000                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.112          net: A1_ADC_SDI_I_ibuf/U0/YIN1
  1.512                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.141          cell: ADLIB:IOINFF_BYPASS
  1.653                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     1.409          net: A1_ADC_SDI_I_c
  3.062                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  3.062                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.161          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.278          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB11:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB11:YR (r)
               +     0.506          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB11_rgbr_net_1
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.165          Library setup time: ADLIB:SLE
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  6.115                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                10.290                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           10.290                                                                          

Path 2
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  6.098                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                10.273                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           10.273                                                                          

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  6.049                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                10.224                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           10.224                                                                          

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  6.032                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                10.207                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           10.207                                                                          

Path 5
  From:                        Stepper_Axis_0/MSC_i_42/s_state[7]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  5.541                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.727                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.727                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To: A1_PWM_WL_O
  data required time                             N/C       
  data arrival time                          -   10.290    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.288          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.435                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:An (f)
               +     0.251          cell: ADLIB:RGB
  3.686                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:YL (r)
               +     0.489          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13_rgbl_net_1
  4.175                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.262                        Stepper_Axis_0/MSC_i_42/s_state[0]:Q (r)
               +     0.543          net: Stepper_Axis_0/MSC_i_42/MSC_net_88
  4.805                        Stepper_Axis_0/MSC_i_42/s_state_RNIUPQE[8]:A (r)
               +     0.100          cell: ADLIB:CFG2
  4.905                        Stepper_Axis_0/MSC_i_42/s_state_RNIUPQE[8]:Y (f)
               +     0.824          net: Stepper_Axis_0/MSC_i_42/MSC_net_255
  5.729                        Stepper_Axis_0/MSC_i_42/ADC_START_PROC.un103_s_state_i_a2_0_a2_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.816                        Stepper_Axis_0/MSC_i_42/ADC_START_PROC.un103_s_state_i_a2_0_a2_0_a2:Y (f)
               +     2.362          net: A1_PWM_WH_O_c
  8.178                        A1_PWM_WL_O_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  8.508                        A1_PWM_WL_O_obuf/U0/U_IOOUTFF:Y (f)
               +     0.096          net: A1_PWM_WL_O_obuf/U0/DOUT
  8.604                        A1_PWM_WL_O_obuf/U0/U_IOPAD:D (f)
               +     1.686          cell: ADLIB:IOPAD_TRI
  10.290                       A1_PWM_WL_O_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A1_PWM_WL_O
  10.290                       A1_PWM_WL_O (f)
                                    
  10.290                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A1_PWM_WL_O (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[0]:EN
  Delay (ns):                  8.345                                                                           
  Slack (ns):                  0.995                                                                           
  Arrival (ns):                12.835                                                                          
  Required (ns):               13.830                                                                          
  Setup (ns):                  0.308                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[5]:EN
  Delay (ns):                  8.345                                                                           
  Slack (ns):                  1.005                                                                           
  Arrival (ns):                12.835                                                                          
  Required (ns):               13.840                                                                          
  Setup (ns):                  0.308                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[1]:EN
  Delay (ns):                  8.345                                                                           
  Slack (ns):                  1.006                                                                           
  Arrival (ns):                12.835                                                                          
  Required (ns):               13.841                                                                          
  Setup (ns):                  0.308                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[3]:EN
  Delay (ns):                  8.034                                                                           
  Slack (ns):                  1.288                                                                           
  Arrival (ns):                12.524                                                                          
  Required (ns):               13.812                                                                          
  Setup (ns):                  0.308                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[7]:EN
  Delay (ns):                  8.034                                                                           
  Slack (ns):                  1.297                                                                           
  Arrival (ns):                12.524                                                                          
  Required (ns):               13.821                                                                          
  Setup (ns):                  0.308                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[0]:EN
  data required time                             13.830    
  data arrival time                          -   12.835    
  slack                                          0.995     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.346          cell: ADLIB:MSS_010_IP
  5.836                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[13] (r)
               +     1.027          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[13]
  6.863                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:B (r)
               +     0.143          cell: ADLIB:CFG4
  7.006                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:Y (f)
               +     1.308          net: MC_System_0_AMBA_SLAVE_1_PSELx
  8.314                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:B (f)
               +     0.209          cell: ADLIB:CFG4
  8.523                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:Y (f)
               +     0.236          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_1
  8.759                        Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7:C (f)
               +     0.087          cell: ADLIB:CFG3
  8.846                        Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7:Y (f)
               +     0.499          net: Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7_Z
  9.345                        Stepper_Axis_0/apb3_if_st_0/adc_scale_val_o_1_sqmuxa_0:B (f)
               +     0.087          cell: ADLIB:CFG2
  9.432                        Stepper_Axis_0/apb3_if_st_0/adc_scale_val_o_1_sqmuxa_0:Y (f)
               +     0.767          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_0
  10.199                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2:D (f)
               +     0.287          cell: ADLIB:CFG4
  10.486                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2:Y (f)
               +     0.221          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2_Z
  10.707                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa:D (f)
               +     0.209          cell: ADLIB:CFG4
  10.916                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa:Y (f)
               +     1.919          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_Z
  12.835                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[0]:EN (f)
                                    
  12.835                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YNn (f)
               +     0.277          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn
  13.423                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB7:An (f)
               +     0.251          cell: ADLIB:RGB
  13.674                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB7:YL (r)
               +     0.464          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB7_rgbl_net_1
  14.138                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[0]:CLK (r)
               -     0.308          Library setup time: ADLIB:SLE
  13.830                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[0]:EN
                                    
  13.830                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

No Path 

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path 

END SET Input to Output

----------------------------------------------------

Path set User Sets

