@W: BN132 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@W: MT530 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface_795x.vhd":632:8:632:9|Found inferred clock MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock which controls 1727 sequential elements including Stepper_Axis_0.adc_interface_795x_0.spi_engine_inst.s_sck_count[5:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablslst10\liberoproject\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface_795x.vhd":632:8:632:9|Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 3491 sequential elements including Bldc_Axis_0.adc_interface_795x_0.spi_engine_inst.s_sck_count[5:0]. This clock has no specified timing constraint which may adversely impact design performance. 
