-- Version: v11.7 SP1 11.7.1.14

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_sb_FABOSC_0_OSC is

    port( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : out   std_logic
        );

end MC_System_sb_FABOSC_0_OSC;

architecture DEF_ARCH of MC_System_sb_FABOSC_0_OSC is 

  component RCOSC_25_50MHZ
    generic (FREQUENCY:real := 50.0);

    port( CLKOUT : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \GND\, \VCC\ : std_logic;

begin 


    I_RCOSC_25_50MHZ : RCOSC_25_50MHZ
      generic map(FREQUENCY => 50.000000)

      port map(CLKOUT => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    GND_Z : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity COREAPB3_MUXPTOB3 is

    port( prdata_o_1_2_0_a2_11_0                            : in    std_logic_vector(1 to 1);
          prdata_o_1_2_0_a2_12_0                            : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_26_0                         : in    std_logic_vector(1 to 1);
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : in    std_logic_vector(12 to 12);
          prdata_o_1_2_0_0_2                                : in    std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_0                                : in    std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_1                                : in    std_logic_vector(2 to 2);
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI                 : in    std_logic_vector(0 to 0);
          prdata_o_1_2_0_a2_17_0                            : in    std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_a2_20_0                         : in    std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_a2_24_0                         : in    std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_0_0_0                           : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1_6_tz                          : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1                               : in    std_logic_vector(7 to 7);
          prdata_o_1_0_iv_0_0                               : in    std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_0_2_tz_tz                       : in    std_logic_vector(0 to 0);
          prdata_o_1_iv_0_0_4_2_1_0                         : in    std_logic_vector(3 to 3);
          SPEED_ID_IQ_PI_1_id_pi_output_o                   : in    std_logic_vector(1 downto 0);
          SPEED_ID_IQ_PI_1_iq_pi_output_o                   : in    std_logic_vector(1 downto 0);
          prdata_o_1_2_0_0_4_2                              : in    std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_5_0                          : in    std_logic_vector(3 to 3);
          STEPPER_THETA_0_theta_output_o                    : in    std_logic_vector(17 to 17);
          MC_System_0_AMBA_SLAVE_1_PADDR_3                  : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PADDR_2                  : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PADDR_1                  : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PADDR_8                  : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PADDR_0                  : in    std_logic;
          prdata_o_1_iv_0_0_a2_45_0                         : in    std_logic_vector(0 to 0);
          adc_measurements_0_adc_result_ch3_o               : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_14_1                         : in    std_logic_vector(1 to 1);
          SEQ_CONTROLLER_1_state_o_0                        : in    std_logic_vector(1 to 1);
          SEQ_CONTROLLER_1_state_o_2                        : in    std_logic;
          SEQ_CONTROLLER_1_state_o_0_d0                     : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_1                          : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_4                          : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_0                          : in    std_logic;
          prdata_o_1_0_iv_0_12_1                            : in    std_logic_vector(7 to 7);
          prdata_o_1_0_iv_0_12_4                            : in    std_logic_vector(8 to 8);
          prdata_o_1_0_iv_0_a2_19_0                         : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1_1                             : in    std_logic_vector(10 to 10);
          FOC_TRANSFORMS_1_valpha_o_0                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_5                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_8                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_9                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_4                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_7                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_10                      : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_6                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_11                      : in    std_logic;
          STEPPER_THETA_1_step_count_o_17                   : in    std_logic;
          STEPPER_THETA_1_step_count_o_3                    : in    std_logic;
          STEPPER_THETA_1_step_count_o_6                    : in    std_logic;
          STEPPER_THETA_1_step_count_o_9                    : in    std_logic;
          STEPPER_THETA_1_step_count_o_0                    : in    std_logic;
          STEPPER_THETA_1_step_count_o_5                    : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_3                        : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_0                        : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_5                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_0                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_3                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_5                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_8                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_12                       : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_15                       : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_7                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_10                       : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_2                        : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_0                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_1                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_5                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_8                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_12                          : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_15                          : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_7                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_10                          : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_6                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_11                          : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_2                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_1                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_4                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_0_d0                        : in    std_logic;
          prdata_o_1_0_iv_0_0_0_2                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_7                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_5                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_0                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_5                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_8                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_9                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_7                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_10                          : in    std_logic;
          FOC_TRANSFORMS_0_id_o_12                          : in    std_logic;
          FOC_TRANSFORMS_0_id_o_15                          : in    std_logic;
          prdata_o_1_0_iv_0_3_0                             : in    std_logic;
          prdata_o_1_0_iv_0_3_3                             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_0             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_5             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_8             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_10            : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_1             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_9             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_7             : in    std_logic;
          adc_interface_0_result_ch0_o_6                    : in    std_logic;
          adc_interface_0_result_ch0_o_11                   : in    std_logic;
          adc_interface_0_result_ch0_o_7                    : in    std_logic;
          adc_interface_0_result_ch0_o_0                    : in    std_logic;
          adc_interface_0_result_ch0_o_5                    : in    std_logic;
          adc_interface_0_result_ch0_o_8                    : in    std_logic;
          adc_interface_0_result_ch0_o_9                    : in    std_logic;
          ADC_SCALING_0_ia_adc_o_0                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_7                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_10                         : in    std_logic;
          ADC_SCALING_0_ia_adc_o_2                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_5                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_8                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_9                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_12                         : in    std_logic;
          ADC_SCALING_0_ia_adc_o_15                         : in    std_logic;
          ADC_SCALING_0_ia_adc_o_4                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_1                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_6                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_11                         : in    std_logic;
          prdata_o_1_0_iv_0_1_o2_0                          : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_11                              : in    std_logic_vector(3 to 3);
          prdata_o_1_2_0_0_5                                : in    std_logic_vector(3 to 3);
          ADC_SCALING_0_ib_adc_o_10                         : in    std_logic;
          ADC_SCALING_0_ib_adc_o_5                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_4                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_7                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_8                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_11                         : in    std_logic;
          ADC_SCALING_0_ib_adc_o_14                         : in    std_logic;
          ADC_SCALING_0_ib_adc_o_3                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_0                          : in    std_logic;
          prdata_o_1_iv_0_0_0_3_tz                          : in    std_logic_vector(1 to 1);
          prdata_o_1_0_1                                    : in    std_logic_vector(16 to 16);
          prdata_o_1_0_2                                    : in    std_logic_vector(16 to 16);
          prdata_o_1_0_0                                    : in    std_logic_vector(16 to 16);
          prdata_o_1_3_0_0_2                                : in    std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_3                                : in    std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_0                                : in    std_logic_vector(11 to 11);
          prdata_o_1_8_2                                    : in    std_logic_vector(6 to 6);
          prdata_o_1_8_3                                    : in    std_logic_vector(6 to 6);
          prdata_o_1_8_0                                    : in    std_logic_vector(6 to 6);
          prdata_o_1_iv_0_0_12_4_3                          : in    std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_4_2                          : in    std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_5_1                             : in    std_logic;
          prdata_o_1_0_iv_0_5_4                             : in    std_logic;
          prdata_o_1_0_iv_0_5_2                             : in    std_logic;
          prdata_o_1_0_iv_0_5_7                             : in    std_logic;
          prdata_o_1_0_iv_0_5_5                             : in    std_logic;
          prdata_o_1_0_iv_0_5_0                             : in    std_logic;
          prdata_o_1_0_iv_0_5_12                            : in    std_logic;
          prdata_o_1_0_iv_0_6                               : in    std_logic_vector(16 to 16);
          MC_System_0_AMBA_SLAVE_1_PRDATA                   : in    std_logic_vector(14 downto 13);
          MC_System_0_AMBA_SLAVE_0_PRDATA_0                 : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_15                : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_12                : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_13                : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_14                : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx                    : in    std_logic;
          N_1342                                            : in    std_logic;
          N_2598                                            : in    std_logic;
          N_2644                                            : in    std_logic;
          N_1396                                            : in    std_logic;
          N_2631                                            : in    std_logic;
          prdata_m2_e_1_1                                   : in    std_logic;
          N_1360                                            : in    std_logic;
          N_1288                                            : in    std_logic;
          prdata_m1_0_a2_0                                  : in    std_logic;
          N_522                                             : in    std_logic;
          N_527                                             : in    std_logic;
          N_542                                             : in    std_logic;
          prdata_m4_e_0                                     : in    std_logic;
          prdata_m1_0_a2_2_0                                : in    std_logic;
          N_509                                             : in    std_logic;
          N_529                                             : in    std_logic;
          N_503                                             : in    std_logic;
          prdata_m2_e_0                                     : in    std_logic;
          N_508                                             : in    std_logic;
          N_106                                             : in    std_logic;
          N_2652                                            : in    std_logic;
          N_768                                             : in    std_logic;
          N_1345                                            : in    std_logic;
          N_2647                                            : in    std_logic;
          N_2531                                            : in    std_logic;
          N_513                                             : in    std_logic;
          N_502                                             : in    std_logic;
          N_534                                             : in    std_logic;
          N_500                                             : in    std_logic;
          N_514                                             : in    std_logic;
          N_506                                             : in    std_logic;
          N_505                                             : in    std_logic;
          N_518                                             : in    std_logic;
          N_2574                                            : in    std_logic;
          N_1346                                            : in    std_logic;
          N_531                                             : in    std_logic;
          N_2640                                            : in    std_logic;
          N_738                                             : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx                    : in    std_logic;
          N_533                                             : in    std_logic;
          N_507                                             : in    std_logic;
          prdata_m1_e_0_1                                   : in    std_logic;
          N_1398                                            : in    std_logic;
          N_1378                                            : in    std_logic;
          N_2627                                            : in    std_logic;
          prdata_m2_0_a2_0                                  : in    std_logic;
          N_455                                             : in    std_logic;
          N_495                                             : in    std_logic;
          N_892                                             : in    std_logic;
          N_771                                             : in    std_logic;
          N_773                                             : in    std_logic;
          N_750                                             : in    std_logic;
          N_2639                                            : in    std_logic;
          N_775                                             : in    std_logic;
          N_763                                             : in    std_logic;
          N_2645                                            : in    std_logic;
          N_1351                                            : in    std_logic;
          N_1169                                            : in    std_logic;
          N_1279                                            : in    std_logic;
          N_793                                             : in    std_logic;
          N_791                                             : in    std_logic;
          N_782                                             : in    std_logic;
          N_893                                             : in    std_logic;
          N_788                                             : in    std_logic;
          N_772                                             : in    std_logic;
          N_749                                             : in    std_logic;
          N_774                                             : in    std_logic;
          N_762                                             : in    std_logic;
          N_1347                                            : in    std_logic;
          N_1165                                            : in    std_logic;
          N_1275                                            : in    std_logic;
          N_792                                             : in    std_logic;
          N_878                                             : in    std_logic;
          N_859                                             : in    std_logic;
          N_880                                             : in    std_logic;
          N_870                                             : in    std_logic;
          prdata_m2_e_0_0                                   : in    std_logic;
          prdata_m1_e_11_0                                  : in    std_logic;
          N_414                                             : in    std_logic;
          N_516                                             : in    std_logic;
          N_397                                             : in    std_logic;
          N_355                                             : in    std_logic;
          N_198                                             : in    std_logic;
          m20_i_2_tz                                        : in    std_logic;
          m20_i_a2_0_1                                      : in    std_logic;
          m20_m2_0_a2_1                                     : in    std_logic;
          N_349                                             : in    std_logic;
          m20_i_a2_5_0                                      : in    std_logic;
          N_517                                             : in    std_logic;
          N_128                                             : in    std_logic;
          N_528                                             : in    std_logic;
          N_524                                             : in    std_logic;
          N_454                                             : in    std_logic;
          N_494                                             : in    std_logic;
          N_894                                             : in    std_logic;
          N_1326                                            : in    std_logic;
          N_2646                                            : in    std_logic;
          N_770                                             : in    std_logic;
          N_777                                             : in    std_logic;
          N_883                                             : in    std_logic;
          N_1333                                            : in    std_logic;
          N_790                                             : in    std_logic;
          N_895                                             : in    std_logic;
          N_769                                             : in    std_logic;
          N_776                                             : in    std_logic;
          N_832                                             : in    std_logic;
          N_1329                                            : in    std_logic;
          N_789                                             : in    std_logic;
          N_876                                             : in    std_logic;
          N_882                                             : in    std_logic;
          prdata_m3_i_0                                     : in    std_logic;
          N_260                                             : in    std_logic;
          N_766                                             : in    std_logic;
          N_739                                             : in    std_logic;
          N_891                                             : in    std_logic;
          N_767                                             : in    std_logic;
          N_875                                             : in    std_logic;
          N_396                                             : in    std_logic;
          N_405                                             : in    std_logic;
          N_354                                             : in    std_logic;
          N_363                                             : in    std_logic;
          prdata_N_7_2                                      : in    std_logic;
          m20_i_10_1                                        : in    std_logic;
          m20_i_10_0                                        : in    std_logic;
          N_215                                             : in    std_logic;
          N_377                                             : in    std_logic;
          N_2495                                            : in    std_logic;
          N_2498                                            : in    std_logic;
          m20_i_11_5                                        : in    std_logic;
          N_122                                             : in    std_logic;
          N_317                                             : in    std_logic;
          N_318                                             : in    std_logic;
          N_319                                             : in    std_logic;
          N_320                                             : in    std_logic;
          N_321                                             : in    std_logic;
          N_315                                             : in    std_logic;
          PRDATA_N_3_mux_i_0                                : out   std_logic
        );

end COREAPB3_MUXPTOB3;

architecture DEF_ARCH of COREAPB3_MUXPTOB3 is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal PRDATA_1_a3_1_1 : std_logic_vector(17 downto 3);
    signal PRDATA_1_a0_8_1_1 : std_logic_vector(8 downto 5);
    signal PRDATA_1_a0_8_1 : std_logic_vector(8 downto 5);
    signal PRDATA_1_a1_1 : std_logic_vector(10 downto 4);
    signal PRDATA_1_a1_3 : std_logic_vector(10 downto 4);
    signal PRDATA_0_1 : std_logic_vector(23 downto 5);
    signal PRDATA_0 : std_logic_vector(9 downto 5);
    signal PRDATA_1_a1_2 : std_logic_vector(10 downto 1);
    signal PRDATA_1_a3_0_1 : std_logic_vector(2 to 2);
    signal PRDATA_1_a0_2_sx : std_logic_vector(10 to 10);
    signal PRDATA_1_a0_2 : std_logic_vector(10 downto 1);
    signal PRDATA_1_a0_0 : std_logic_vector(10 downto 1);
    signal PRDATA_1_a0_9_sx : std_logic_vector(10 downto 7);
    signal PRDATA_1_a0_3 : std_logic_vector(10 downto 4);
    signal PRDATA_1_a0_9 : std_logic_vector(10 downto 1);
    signal PRDATA_1 : std_logic_vector(10 downto 4);
    signal PRDATA_1_0 : std_logic_vector(10 downto 9);
    signal PRDATA_sx : std_logic_vector(10 downto 7);
    signal PRDATA_sx_1 : std_logic_vector(10 to 10);
    signal PRDATA_1_a0_1 : std_logic_vector(9 downto 1);
    signal PRDATA_1_a0_5 : std_logic_vector(7 to 7);
    signal PRDATA_1_a0_4 : std_logic_vector(9 downto 7);
    signal PRDATA_1_a1_4 : std_logic_vector(7 downto 1);
    signal PRDATA_1_a0_6 : std_logic_vector(1 to 1);
    signal PRDATA_1_a3_d : std_logic_vector(3 to 3);
    signal PRDATA_1_a3_1_0 : std_logic_vector(3 to 3);
    signal PRDATA_3_1 : std_logic_vector(23 to 23);
    signal PRDATA_3 : std_logic_vector(23 to 23);
    signal PRDATA_1_a1_0 : std_logic_vector(4 downto 1);
    signal PRDATA_1_a5 : std_logic_vector(23 to 23);
    signal PRDATA_1_1 : std_logic_vector(8 downto 5);
    signal PRDATA_1_2 : std_logic_vector(8 downto 5);
    signal PRDATA_1_a0_7 : std_logic_vector(9 downto 4);
    signal PRDATA_1_2_d : std_logic_vector(23 to 23);
    signal PRDATA_1_a0_8 : std_logic_vector(1 to 1);
    signal PRDATA_1_a1_5 : std_logic_vector(1 to 1);
    signal PRDATA_1_a0_10 : std_logic_vector(1 to 1);
    signal PRDATA_1_a1 : std_logic_vector(4 downto 1);
    signal PRDATA_m3_e_Z, PRDATA_1_a3_1_N_6L9_Z, N_42, 
        PRDATA_1_a3_1_N_6L9_1_0_Z, PRDATA_m8_0_a3_5_1_Z, 
        PRDATA_m8_0_a3_5_Z, PRDATA_m8_0_a3_sx_N_2L1_Z, 
        PRDATA_m8_0_a3_sx_N_3L3_Z, PRDATA_m8_0_a3_sx_N_5L8_Z, 
        PRDATA_m8_0_a3_sx_N_6L10_Z, PRDATA_m8_0_a3_sx_Z, N_100, 
        r_m3_0_a2_0, r_m3_0_a2_1_0, r_m3_0_a2_1_1, r_m3_0_a2_1, 
        PRDATA_m8_0_a3_3_sx_Z, PRDATA_m8_0_a3_3_Z, 
        PRDATA_m8_0_a3_2_Z, PRDATA_N_4, PRDATA_1_a3_1_N_4L5_1_Z, 
        PRDATA_1_a3_1_N_5L8_1, PRDATA_1_a0_6_N_3L4_Z, 
        PRDATA_1_a0_6_N_4L6_Z, PRDATA_m4_0_a2_1_Z, PRDATA_N_9_mux, 
        PRDATA_m6_0_c_1_Z, PRDATA_m2_e_0_1_Z, PRDATA_m2_e_0_Z, 
        PRDATA_m2_e_2_2_Z, PRDATA_m2_e_2_0_Z, PRDATA_m2_e_1_2_Z, 
        PRDATA_m2_e_1_0_Z, PRDATA_m4_0_a2_6_3_Z, 
        PRDATA_m4_0_a2_6_2_Z, PRDATA_m4_0_a2_6_1_Z, 
        PRDATA_m4_0_a2_2_3_Z, PRDATA_m4_0_a2_2_2_Z, 
        PRDATA_m4_0_a2_2_1_Z, PRDATA_m3_0_a3_6_3_Z, 
        PRDATA_m3_0_a3_6_1_Z, PRDATA_m3_0_a3_6_0_Z, 
        PRDATA_m3_0_a3_5_Z, PRDATA_m2_e_2_5_Z, PRDATA_m2_e_2_3_Z, 
        PRDATA_m2_e_1_5_Z, PRDATA_m2_e_1_3_Z, r_N_7_mux_0, 
        PRDATA_N_9_mux_1, r_N_7_mux, PRDATA_N_9_mux_0, 
        PRDATA_m6_0_d_Z, PRDATA_m1_e_2_0_Z, PRDATA_m2_e_2_Z, 
        PRDATA_m2_e_1_Z, PRDATA_m3_0_a3_6_Z, N_72, N_82, N_92, 
        \GND\, \VCC\ : std_logic;

begin 


    \PRDATA_1_a1_2[10]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_791, B => N_782, C => N_2639, D => N_2647, 
        Y => PRDATA_1_a1_2(10));
    
    PRDATA_m2_e_2_0 : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_vbeta_o_12, B => 
        FOC_TRANSFORMS_0_iq_o_12, C => N_533, D => N_531, Y => 
        PRDATA_m2_e_2_0_Z);
    
    PRDATA_m3_e : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_m1_e_0_1, B => N_1398, C => N_1378, D
         => N_2627, Y => PRDATA_m3_e_Z);
    
    \PRDATA_1_a1_2[1]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_892, B => N_771, C => N_2647, D => N_2640, 
        Y => PRDATA_1_a1_2(1));
    
    \PRDATA_1_a0_4[10]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_vbeta_o_10, B => 
        FOC_TRANSFORMS_0_iq_o_10, C => N_533, D => N_531, Y => 
        PRDATA_1_0(10));
    
    \PRDATA[5]\ : CFG4
      generic map(INIT => x"70F0")

      port map(A => PRDATA_1_2(5), B => PRDATA_1_1(5), C => 
        PRDATA_0(5), D => PRDATA_1(5), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5);
    
    PRDATA_m4_0_a2_6 : CFG4
      generic map(INIT => x"2000")

      port map(A => PRDATA_m4_0_a2_6_2_Z, B => N_405, C => 
        PRDATA_m4_0_a2_6_3_Z, D => PRDATA_m4_0_a2_6_1_Z, Y => 
        PRDATA_N_9_mux_1);
    
    PRDATA_m3_0_a3_6_1 : CFG4
      generic map(INIT => x"153F")

      port map(A => m20_i_2_tz, B => m20_i_a2_0_1, C => N_522, D
         => N_514, Y => PRDATA_m3_0_a3_6_1_Z);
    
    \PRDATA_1_a0_2[1]\ : CFG4
      generic map(INIT => x"70F0")

      port map(A => N_517, B => N_128, C => PRDATA_1_a0_0(1), D
         => N_508, Y => PRDATA_1_a0_2(1));
    
    PRDATA_m8_0_a3_3 : CFG4
      generic map(INIT => x"007F")

      port map(A => prdata_o_1_iv_0_0_0_2_tz_tz(0), B => N_505, C
         => N_514, D => PRDATA_m8_0_a3_3_sx_Z, Y => 
        PRDATA_m8_0_a3_3_Z);
    
    \PRDATA_1_a0_9_sx[7]\ : CFG4
      generic map(INIT => x"FF80")

      port map(A => ADC_SCALING_0_ia_adc_o_7, B => N_509, C => 
        N_506, D => prdata_o_1_0_iv_0_0(7), Y => 
        PRDATA_1_a0_9_sx(7));
    
    PRDATA_m1_e_2_0 : CFG4
      generic map(INIT => x"0F2F")

      port map(A => PRDATA_m3_0_a3_5_Z, B => m20_i_10_1, C => 
        MC_System_0_AMBA_SLAVE_1_PSELx, D => m20_i_10_0, Y => 
        PRDATA_m1_e_2_0_Z);
    
    \PRDATA_1[22]\ : CFG4
      generic map(INIT => x"FAEA")

      port map(A => N_42, B => N_122, C => 
        MC_System_0_AMBA_SLAVE_1_PSELx, D => N_317, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22);
    
    \PRDATA_1[12]\ : CFG4
      generic map(INIT => x"4C08")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), B => 
        N_106, C => PRDATA_m2_e_2_Z, D => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12);
    
    PRDATA_m8_0_a3_sx_N_3L3 : CFG3
      generic map(INIT => x"7F")

      port map(A => ADC_SCALING_0_ia_adc_o_0, B => N_509, C => 
        prdata_o_1_iv_0_0_a2_26_0(1), Y => 
        PRDATA_m8_0_a3_sx_N_3L3_Z);
    
    \PRDATA_1[13]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => MC_System_0_AMBA_SLAVE_1_PRDATA(13), B => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13, C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D => 
        N_106, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13);
    
    \PRDATA_1_a3_1[17]\ : CFG4
      generic map(INIT => x"C8CC")

      port map(A => PRDATA_m3_e_Z, B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => 
        PRDATA_1_a3_1_N_6L9_Z, D => PRDATA_1_a3_1_1(17), Y => 
        N_42);
    
    PRDATA_m2_e_2_5 : CFG4
      generic map(INIT => x"135F")

      port map(A => ADC_SCALING_0_ib_adc_o_11, B => 
        ADC_SCALING_0_ia_adc_o_12, C => N_528, D => N_524, Y => 
        PRDATA_m2_e_2_5_Z);
    
    PRDATA_m3_0_a3_6_3 : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_vbeta_o_2, B => 
        FOC_TRANSFORMS_0_iq_o_2, C => N_533, D => N_531, Y => 
        PRDATA_m3_0_a3_6_3_Z);
    
    \PRDATA_1_a0_1[4]\ : CFG4
      generic map(INIT => x"008A")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), B => 
        prdata_m3_i_0, C => N_508, D => prdata_o_1_0_iv_0_5_0, Y
         => PRDATA_1_a0_1(4));
    
    \PRDATA_1_a0_9_sx[10]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => prdata_o_1_0_iv_0_0_0_0(10), B => 
        prdata_o_1_0_iv_0_1_6_tz(10), C => N_514, D => N_522, Y
         => PRDATA_1_a0_9_sx(10));
    
    \PRDATA_0_1[9]\ : CFG4
      generic map(INIT => x"040C")

      port map(A => N_2652, B => PRDATA_1_a1_2(9), C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D => 
        N_768, Y => PRDATA_0_1(9));
    
    PRDATA_m8_0_a3_5 : CFG3
      generic map(INIT => x"70")

      port map(A => prdata_m1_0_a2_0, B => N_522, C => 
        PRDATA_m8_0_a3_5_1_Z, Y => PRDATA_m8_0_a3_5_Z);
    
    \PRDATA_m2_e_0\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_2_0_a2_17_0(1), B => 
        PRDATA_m2_e_0_1_Z, C => N_513, D => 
        prdata_o_1_iv_0_0_a2_45_0(0), Y => PRDATA_m2_e_0_Z);
    
    PRDATA_m6_0_c_1 : CFG4
      generic map(INIT => x"0080")

      port map(A => N_507, B => MC_System_0_AMBA_SLAVE_1_PSELx, C
         => STEPPER_THETA_1_step_count_o_17, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR_2, Y => PRDATA_m6_0_c_1_Z);
    
    \PRDATA_1_a0_9[1]\ : CFG4
      generic map(INIT => x"7000")

      port map(A => prdata_o_1_iv_0_0_0_3_tz(1), B => N_514, C
         => PRDATA_1_a0_6(1), D => PRDATA_1_a0_2(1), Y => 
        PRDATA_1_a0_9(1));
    
    PRDATA_m3_0_a3_5 : CFG4
      generic map(INIT => x"0F7F")

      port map(A => N_509, B => ADC_SCALING_0_ia_adc_o_2, C => 
        N_506, D => m20_i_a2_5_0, Y => PRDATA_m3_0_a3_5_Z);
    
    \PRDATA_1_a0_8_1_1[8]\ : CFG4
      generic map(INIT => x"4CCC")

      port map(A => adc_measurements_0_adc_result_ch1_o_8, B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), C => 
        prdata_m1_0_a2_2_0, D => N_508, Y => PRDATA_1_a0_8_1_1(8));
    
    \PRDATA[9]\ : CFG4
      generic map(INIT => x"7F00")

      port map(A => PRDATA_1_a0_4(9), B => PRDATA_1(9), C => 
        PRDATA_1_0(9), D => PRDATA_0(9), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9);
    
    PRDATA_m8_0_a3_sx_N_2L1 : CFG2
      generic map(INIT => x"7")

      port map(A => prdata_m1_0_a2_2_0, B => 
        adc_measurements_0_adc_result_ch1_o_0, Y => 
        PRDATA_m8_0_a3_sx_N_2L1_Z);
    
    PRDATA_m8_0_a3_2 : CFG4
      generic map(INIT => x"070F")

      port map(A => prdata_m1_e_11_0, B => 
        adc_interface_0_result_ch0_o_0, C => N_198, D => N_508, Y
         => PRDATA_m8_0_a3_2_Z);
    
    \PRDATA_1[16]\ : CFG4
      generic map(INIT => x"FAF8")

      port map(A => MC_System_0_AMBA_SLAVE_1_PSELx, B => 
        prdata_o_1_0_iv_0_5_12, C => N_72, D => 
        prdata_o_1_0_iv_0_6(16), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16);
    
    \PRDATA_0[9]\ : CFG4
      generic map(INIT => x"2AAA")

      port map(A => N_106, B => PRDATA_1_a1_1(9), C => 
        PRDATA_1_a1_3(9), D => PRDATA_0_1(9), Y => PRDATA_0(9));
    
    \PRDATA_1_a1_4[1]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_894, B => N_1326, C => N_2644, D => N_2646, 
        Y => PRDATA_1_a1_4(1));
    
    \PRDATA_1_a3_0[11]\ : CFG4
      generic map(INIT => x"CCC8")

      port map(A => prdata_o_1_3_0_0_2(11), B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => 
        prdata_o_1_3_0_0_3(11), D => prdata_o_1_3_0_0_0(11), Y
         => N_82);
    
    \PRDATA_1_a0_6[4]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => ADC_SCALING_0_ib_adc_o_3, B => 
        ADC_SCALING_0_ia_adc_o_4, C => N_528, D => N_524, Y => 
        PRDATA_1(4));
    
    \PRDATA_1_a0_7[4]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => N_377, B => PRDATA_1_a0_3(4), C => 
        PRDATA_1_a0_2(4), D => PRDATA_1_a0_1(4), Y => 
        PRDATA_1_a0_7(4));
    
    PRDATA_1_a3_1_N_6L9 : CFG4
      generic map(INIT => x"8F00")

      port map(A => N_1396, B => prdata_o_1_2_0_a2_11_0(1), C => 
        PRDATA_1_a3_1_N_6L9_1_0_Z, D => N_2631, Y => 
        PRDATA_1_a3_1_N_6L9_Z);
    
    \PRDATA_1_a0_1[7]\ : CFG4
      generic map(INIT => x"70F0")

      port map(A => prdata_m1_0_a2_2_0, B => 
        adc_measurements_0_adc_result_ch1_o_7, C => 
        PRDATA_1_a0_0(7), D => N_508, Y => PRDATA_1_a0_1(7));
    
    PRDATA_m4_0_a2_2_1 : CFG4
      generic map(INIT => x"1300")

      port map(A => N_522, B => N_355, C => 
        prdata_o_1_0_iv_0_0_0_7, D => 
        MC_System_0_AMBA_SLAVE_1_PSELx, Y => PRDATA_m4_0_a2_2_1_Z);
    
    \PRDATA_1_a0_6[5]\ : CFG3
      generic map(INIT => x"70")

      port map(A => adc_interface_0_result_ch0_o_5, B => N_534, C
         => PRDATA_1_a0_3(5), Y => PRDATA_1_2(5));
    
    PRDATA_1_a3_1_N_6L9_1_0 : CFG4
      generic map(INIT => x"135F")

      port map(A => prdata_m2_e_1_1, B => N_1360, C => N_1288, D
         => prdata_o_1_2_0_a2_12_0(1), Y => 
        PRDATA_1_a3_1_N_6L9_1_0_Z);
    
    \PRDATA_1_a0_7[9]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => ADC_SCALING_0_ib_adc_o_8, B => 
        ADC_SCALING_0_ia_adc_o_9, C => N_528, D => N_524, Y => 
        PRDATA_1_a0_7(9));
    
    \PRDATA_1_a0_3[9]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_1_valpha_o_9, B => 
        FOC_TRANSFORMS_0_id_o_9, C => N_529, D => N_527, Y => 
        PRDATA_1_a0_3(9));
    
    \PRDATA_1_a3_0[2]\ : CFG4
      generic map(INIT => x"CC8C")

      port map(A => prdata_o_1_2_0_0_2(2), B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => PRDATA_1_a3_0_1(2), 
        D => prdata_o_1_2_0_0_0(2), Y => N_100);
    
    \PRDATA_1_a1_1[9]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_775, B => N_763, C => N_2640, D => N_2645, 
        Y => PRDATA_1_a1_1(9));
    
    \PRDATA_1_a1_2[8]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_1351, B => N_1169, C => N_2639, D => N_2647, 
        Y => PRDATA_1_a1_2(8));
    
    \PRDATA_1_a0_6[1]\ : CFG4
      generic map(INIT => x"0700")

      port map(A => N_531, B => FOC_TRANSFORMS_0_iq_o_1, C => 
        PRDATA_1_a0_6_N_3L4_Z, D => PRDATA_1_a0_6_N_4L6_Z, Y => 
        PRDATA_1_a0_6(1));
    
    \PRDATA_1_a0_2_sx[10]\ : CFG4
      generic map(INIT => x"15FF")

      port map(A => prdata_o_1_0_iv_0_a2_20_0(10), B => 
        adc_measurements_0_adc_result_ch1_o_10, C => 
        prdata_m1_0_a2_2_0, D => prdata_o_1_iv_0_0_a2_24_0(1), Y
         => PRDATA_1_a0_2_sx(10));
    
    \PRDATA_1_2_d[23]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_2_0_a2_11_0(1), B => N_1396, C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, D => N_2631, Y => 
        PRDATA_1_2_d(23));
    
    \PRDATA[7]\ : CFG4
      generic map(INIT => x"070F")

      port map(A => PRDATA_1_a0_5(7), B => PRDATA_1_a0_4(7), C
         => PRDATA_sx(7), D => PRDATA_1_a0_9(7), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7);
    
    \PRDATA_1_a0_8[1]\ : CFG4
      generic map(INIT => x"0070")

      port map(A => N_524, B => ADC_SCALING_0_ia_adc_o_1, C => 
        PRDATA_1_a0_1(1), D => N_260, Y => PRDATA_1_a0_8(1));
    
    PRDATA_m4_0_a2_2_2 : CFG4
      generic map(INIT => x"07FF")

      port map(A => STEPPER_THETA_1_step_count_o_5, B => N_509, C
         => prdata_o_1_0_iv_0_a2_6_2_5, D => N_514, Y => 
        PRDATA_m4_0_a2_2_2_Z);
    
    \PRDATA_1_a0_0[10]\ : CFG4
      generic map(INIT => x"2AAA")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), B => 
        N_516, C => prdata_o_1_0_iv_0_1_1(10), D => 
        prdata_o_1_0_iv_0_12_4(8), Y => PRDATA_1_a0_0(10));
    
    \PRDATA_1_RNO_1[6]\ : CFG3
      generic map(INIT => x"7F")

      port map(A => N_506, B => ADC_SCALING_0_ib_adc_o_5, C => 
        N_513, Y => r_m3_0_a2_1_0);
    
    \PRDATA_1_a0_7[8]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => ADC_SCALING_0_ib_adc_o_7, B => 
        ADC_SCALING_0_ia_adc_o_8, C => N_528, D => N_524, Y => 
        PRDATA_1_1(8));
    
    \PRDATA_1[21]\ : CFG4
      generic map(INIT => x"FAEA")

      port map(A => N_42, B => N_122, C => 
        MC_System_0_AMBA_SLAVE_1_PSELx, D => N_318, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21);
    
    \PRDATA_1[11]\ : CFG4
      generic map(INIT => x"FF3A")

      port map(A => MC_System_0_AMBA_SLAVE_1_PSELx, B => 
        r_N_7_mux, C => PRDATA_N_9_mux_0, D => N_82, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11);
    
    \PRDATA_1_a3_d_0[3]\ : CFG4
      generic map(INIT => x"FACA")

      port map(A => MC_System_0_AMBA_SLAVE_1_PSELx, B => 
        prdata_o_1_iv_0_0_12_4_3(3), C => PRDATA_N_9_mux, D => 
        prdata_o_1_iv_0_0_12_4_2(3), Y => PRDATA_1_a3_d(3));
    
    \PRDATA_1_a3_0[16]\ : CFG4
      generic map(INIT => x"CCC8")

      port map(A => prdata_o_1_0_1(16), B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => prdata_o_1_0_2(16), 
        D => prdata_o_1_0_0(16), Y => N_72);
    
    \PRDATA_1[15]\ : CFG4
      generic map(INIT => x"4C08")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), B => 
        N_106, C => PRDATA_m2_e_1_Z, D => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15);
    
    \PRDATA_1_a0_2[4]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_514, B => prdata_o_1_0_iv_0_0_0_0_d0, C => 
        prdata_o_1_0_iv_0_2_tz_0, D => N_522, Y => 
        PRDATA_1_a0_2(4));
    
    PRDATA_m1_e_2_0_RNILBTD1 : CFG4
      generic map(INIT => x"F5FD")

      port map(A => PRDATA_m1_e_2_0_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PSELx, C => N_100, D => 
        PRDATA_m3_0_a3_6_Z, Y => PRDATA_N_3_mux_i_0);
    
    \PRDATA_1_a1_4[5]\ : CFG4
      generic map(INIT => x"040C")

      port map(A => N_2652, B => PRDATA_1_a1_1(5), C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D => 
        N_767, Y => PRDATA_0_1(5));
    
    \PRDATA_1_a1_2[4]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_1347, B => N_1165, C => N_2639, D => N_2647, 
        Y => PRDATA_1_a1_2(4));
    
    PRDATA_m8_0_a3_3_sx : CFG4
      generic map(INIT => x"C0A0")

      port map(A => SPEED_ID_IQ_PI_1_id_pi_output_o(0), B => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0), C => N_518, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR_2, Y => 
        PRDATA_m8_0_a3_3_sx_Z);
    
    \PRDATA_1_a3_1_1[17]\ : CFG3
      generic map(INIT => x"13")

      port map(A => N_1342, B => N_2598, C => N_2644, Y => 
        PRDATA_1_a3_1_1(17));
    
    \PRDATA_1[6]\ : CFG4
      generic map(INIT => x"FF2E")

      port map(A => MC_System_0_AMBA_SLAVE_1_PSELx, B => 
        PRDATA_N_9_mux_1, C => r_N_7_mux_0, D => N_92, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6);
    
    \PRDATA_1_a0_3[4]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_529, B => N_508, C => 
        FOC_TRANSFORMS_1_valpha_o_4, D => prdata_m2_e_0_0, Y => 
        PRDATA_1_a0_3(4));
    
    \PRDATA_1_a1_2[7]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_878, B => N_859, C => N_2639, D => N_2647, 
        Y => PRDATA_1_a1_2(7));
    
    GND_Z : GND
      port map(Y => \GND\);
    
    PRDATA_m4_0_a2_6_3 : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_iq_o_6, B => 
        FOC_TRANSFORMS_1_valpha_o_6, C => N_531, D => N_529, Y
         => PRDATA_m4_0_a2_6_3_Z);
    
    \PRDATA_1_RNO[11]\ : CFG4
      generic map(INIT => x"1300")

      port map(A => ADC_SCALING_0_ia_adc_o_11, B => N_354, C => 
        N_524, D => r_m3_0_a2_1, Y => r_N_7_mux);
    
    PRDATA_1_a3_1_N_4L5 : CFG4
      generic map(INIT => x"4CCC")

      port map(A => N_542, B => PRDATA_1_a3_1_N_4L5_1_Z, C => 
        SEQ_CONTROLLER_1_state_o_2, D => 
        prdata_o_1_iv_0_0_4_2_1_0(3), Y => PRDATA_1_a3_1_N_5L8_1);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \PRDATA_1_a1_1[7]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_880, B => N_870, C => N_2640, D => N_2645, 
        Y => PRDATA_1_a1_1(7));
    
    \PRDATA_1_a3_1_0[3]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => prdata_o_1_iv_0_0_11(3), B => 
        prdata_o_1_2_0_0_5(3), C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D => 
        N_106, Y => PRDATA_1_a3_1_0(3));
    
    PRDATA_1_a3_1_N_5L8 : CFG4
      generic map(INIT => x"0700")

      port map(A => N_2640, B => N_738, C => 
        prdata_o_1_2_0_0_4_2(3), D => PRDATA_1_a3_1_N_5L8_1, Y
         => PRDATA_1_a3_1_1(3));
    
    \PRDATA_1_a1_3[4]\ : CFG4
      generic map(INIT => x"2A3F")

      port map(A => N_832, B => N_1329, C => N_2644, D => N_2646, 
        Y => PRDATA_1_a1_3(4));
    
    \PRDATA_1_a0_9[10]\ : CFG4
      generic map(INIT => x"0800")

      port map(A => PRDATA_1_a0_0(10), B => PRDATA_1_a0_2(10), C
         => PRDATA_1_a0_9_sx(10), D => PRDATA_1_a0_3(10), Y => 
        PRDATA_1_a0_9(10));
    
    \PRDATA_1_RNO_1[11]\ : CFG4
      generic map(INIT => x"7FFF")

      port map(A => N_513, B => ADC_SCALING_0_ib_adc_o_10, C => 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0), D => N_502, Y => 
        r_m3_0_a2_0);
    
    \PRDATA_1_a5[23]\ : CFG3
      generic map(INIT => x"80")

      port map(A => N_2644, B => N_1342, C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, Y => PRDATA_1_a5(23));
    
    PRDATA_m4_0_a2_6_2 : CFG4
      generic map(INIT => x"07FF")

      port map(A => STEPPER_THETA_1_step_count_o_0, B => N_509, C
         => prdata_o_1_0_iv_0_a2_6_2_0, D => N_514, Y => 
        PRDATA_m4_0_a2_6_2_Z);
    
    PRDATA_m8_0_a3_sx_N_5L8 : CFG4
      generic map(INIT => x"D5C0")

      port map(A => PRDATA_m8_0_a3_sx_N_3L3_Z, B => N_529, C => 
        FOC_TRANSFORMS_1_valpha_o_0, D => N_503, Y => 
        PRDATA_m8_0_a3_sx_N_5L8_Z);
    
    \PRDATA_1_a0_4[7]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_vbeta_o_7, B => 
        FOC_TRANSFORMS_0_iq_o_7, C => N_533, D => N_531, Y => 
        PRDATA_1_a0_4(7));
    
    PRDATA_m2_e_1_2 : CFG4
      generic map(INIT => x"007F")

      port map(A => STEPPER_THETA_1_step_count_o_9, B => N_509, C
         => N_514, D => N_495, Y => PRDATA_m2_e_1_2_Z);
    
    \PRDATA_1_a0_8_1[5]\ : CFG4
      generic map(INIT => x"0444")

      port map(A => prdata_o_1_0_iv_0_5_1, B => 
        PRDATA_1_a0_8_1_1(5), C => prdata_o_1_0_iv_0_0_0_1, D => 
        N_522, Y => PRDATA_1_a0_8_1(5));
    
    \PRDATA_1_a0_0[1]\ : CFG4
      generic map(INIT => x"4CCC")

      port map(A => SEQ_CONTROLLER_1_state_o_0(1), B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), C => 
        prdata_o_1_iv_0_0_4_2_1_0(3), D => N_542, Y => 
        PRDATA_1_a0_0(1));
    
    \PRDATA_1_a0_3[10]\ : CFG4
      generic map(INIT => x"0F7F")

      port map(A => N_509, B => ADC_SCALING_0_ia_adc_o_10, C => 
        N_506, D => prdata_o_1_0_iv_0_a2_19_0(10), Y => 
        PRDATA_1_a0_3(10));
    
    \PRDATA_0_1[23]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => prdata_m2_e_1_1, B => N_1360, C => N_1288, D
         => prdata_o_1_2_0_a2_12_0(1), Y => PRDATA_0_1(23));
    
    \PRDATA[0]\ : CFG4
      generic map(INIT => x"4C08")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), B => 
        N_106, C => PRDATA_N_4, D => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0);
    
    PRDATA_m8_0_a3_5_1 : CFG4
      generic map(INIT => x"135F")

      port map(A => N_527, B => N_542, C => 
        FOC_TRANSFORMS_0_id_o_0, D => prdata_m4_e_0, Y => 
        PRDATA_m8_0_a3_5_1_Z);
    
    \PRDATA_1_a0_10[1]\ : CFG4
      generic map(INIT => x"0070")

      port map(A => N_528, B => ADC_SCALING_0_ib_adc_o_0, C => 
        PRDATA_1_a0_8(1), D => N_215, Y => PRDATA_1_a0_10(1));
    
    \PRDATA_1[20]\ : CFG4
      generic map(INIT => x"FAEA")

      port map(A => N_42, B => N_122, C => 
        MC_System_0_AMBA_SLAVE_1_PSELx, D => N_319, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20);
    
    PRDATA_m2_e_0_1 : CFG4
      generic map(INIT => x"0004")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR_1, B => 
        STEPPER_THETA_0_theta_output_o(17), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR_8, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR_0, Y => PRDATA_m2_e_0_1_Z);
    
    \PRDATA[4]\ : CFG4
      generic map(INIT => x"1030")

      port map(A => PRDATA_1_a0_7(4), B => PRDATA_1_a1(4), C => 
        N_106, D => PRDATA_1(4), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4);
    
    \PRDATA_1_a1_1[8]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_1279, B => N_793, C => N_2645, D => N_2640, 
        Y => PRDATA_1_a1_1(8));
    
    PRDATA_m4_0_a2 : CFG4
      generic map(INIT => x"4C00")

      port map(A => N_531, B => PRDATA_m4_0_a2_1_Z, C => 
        FOC_TRANSFORMS_0_iq_o_3, D => 
        MC_System_0_AMBA_SLAVE_1_PSELx, Y => PRDATA_N_9_mux);
    
    \PRDATA_1_a1_4[7]\ : CFG4
      generic map(INIT => x"040C")

      port map(A => N_2652, B => PRDATA_1_a1_1(7), C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D => 
        N_875, Y => PRDATA_1_a1_4(7));
    
    \PRDATA_1_a0_0[7]\ : CFG4
      generic map(INIT => x"2AAA")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), B => 
        N_516, C => prdata_o_1_0_iv_0_12_1(7), D => 
        prdata_o_1_0_iv_0_12_4(8), Y => PRDATA_1_a0_0(7));
    
    \PRDATA_1_a1_1[4]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_1275, B => N_792, C => N_2645, D => N_2640, 
        Y => PRDATA_1_a1_1(4));
    
    \PRDATA_1[14]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => MC_System_0_AMBA_SLAVE_1_PRDATA(14), B => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14, C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D => 
        N_106, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14);
    
    PRDATA_m4_0_a2_1 : CFG4
      generic map(INIT => x"153F")

      port map(A => N_503, B => FOC_TRANSFORMS_0_vbeta_o_3, C => 
        N_533, D => prdata_o_1_iv_0_0_12_5_0(3), Y => 
        PRDATA_m4_0_a2_1_Z);
    
    \PRDATA_0[5]\ : CFG4
      generic map(INIT => x"2AAA")

      port map(A => N_106, B => PRDATA_1_a1_2(5), C => 
        PRDATA_1_a1_3(5), D => PRDATA_0_1(5), Y => PRDATA_0(5));
    
    \PRDATA_1_a1_1[5]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_774, B => N_762, C => N_2640, D => N_2645, 
        Y => PRDATA_1_a1_1(5));
    
    PRDATA_m6_0_d : CFG4
      generic map(INIT => x"CC8C")

      port map(A => PRDATA_m2_e_0_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PSELx, C => prdata_N_7_2, D => 
        prdata_o_1_0_iv_0_1_o2_0(17), Y => PRDATA_m6_0_d_Z);
    
    \PRDATA_1_a1_4[8]\ : CFG4
      generic map(INIT => x"040C")

      port map(A => N_2652, B => PRDATA_1_a1_1(8), C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D => 
        N_739, Y => PRDATA_0_1(8));
    
    \PRDATA_1_a0_9[7]\ : CFG4
      generic map(INIT => x"0200")

      port map(A => PRDATA_1_a0_2(7), B => prdata_o_1_0_iv_0_1(7), 
        C => PRDATA_1_a0_9_sx(7), D => PRDATA_1_a0_1(7), Y => 
        PRDATA_1_a0_9(7));
    
    PRDATA_m2_e_2_2 : CFG4
      generic map(INIT => x"007F")

      port map(A => STEPPER_THETA_1_step_count_o_6, B => N_509, C
         => N_514, D => N_455, Y => PRDATA_m2_e_2_2_Z);
    
    \PRDATA[23]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => PRDATA_3(23), B => PRDATA_m6_0_d_Z, C => 
        PRDATA_1_2_d(23), D => PRDATA_1_a5(23), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31);
    
    \PRDATA[8]\ : CFG4
      generic map(INIT => x"70F0")

      port map(A => PRDATA_1_2(8), B => PRDATA_1_1(8), C => 
        PRDATA_0(8), D => PRDATA_1(8), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8);
    
    \PRDATA_1_a0_2[7]\ : CFG4
      generic map(INIT => x"070F")

      port map(A => prdata_m1_e_11_0, B => 
        adc_interface_0_result_ch0_o_7, C => N_414, D => N_508, Y
         => PRDATA_1_a0_2(7));
    
    PRDATA_m4_0_a2_2_3 : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_iq_o_11, B => 
        FOC_TRANSFORMS_1_valpha_o_11, C => N_531, D => N_529, Y
         => PRDATA_m4_0_a2_2_3_Z);
    
    \PRDATA_0[8]\ : CFG4
      generic map(INIT => x"2AAA")

      port map(A => N_106, B => PRDATA_1_a1_2(8), C => 
        PRDATA_1_a1_3(8), D => PRDATA_0_1(8), Y => PRDATA_0(8));
    
    \PRDATA_1_a0_3[5]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_1_valpha_o_5, B => 
        FOC_TRANSFORMS_0_id_o_5, C => N_529, D => N_527, Y => 
        PRDATA_1_a0_3(5));
    
    \PRDATA_3_1[23]\ : CFG4
      generic map(INIT => x"0031")

      port map(A => N_2631, B => N_2598, C => PRDATA_0_1(23), D
         => PRDATA_m3_e_Z, Y => PRDATA_3_1(23));
    
    \PRDATA_1_a0_8[5]\ : CFG4
      generic map(INIT => x"7000")

      port map(A => N_514, B => prdata_o_1_0_iv_0_2_tz_1, C => 
        PRDATA_1_a0_8_1(5), D => PRDATA_1_a0_2(5), Y => 
        PRDATA_1(5));
    
    PRDATA_m8_0_a3 : CFG4
      generic map(INIT => x"0080")

      port map(A => PRDATA_m8_0_a3_5_Z, B => PRDATA_m8_0_a3_2_Z, 
        C => PRDATA_m8_0_a3_3_Z, D => PRDATA_m8_0_a3_sx_Z, Y => 
        PRDATA_N_4);
    
    \PRDATA_1_a1[1]\ : CFG4
      generic map(INIT => x"1000")

      port map(A => N_2495, B => N_2498, C => PRDATA_1_a1_4(1), D
         => PRDATA_1_a1_5(1), Y => PRDATA_1_a1(1));
    
    \PRDATA_1_a1_1[10]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_893, B => N_788, C => N_2640, D => N_2645, 
        Y => PRDATA_1_a1_1(10));
    
    \PRDATA_1_a0_2[10]\ : CFG4
      generic map(INIT => x"DFFF")

      port map(A => N_500, B => PRDATA_1_a0_2_sx(10), C => 
        prdata_o_1_2_0_a2_17_0(1), D => N_502, Y => 
        PRDATA_1_a0_2(10));
    
    \PRDATA_1_a0_1[9]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => prdata_m2_0_a2_0, B => 
        prdata_o_1_0_iv_0_a2_6_2_3, C => N_508, D => N_514, Y => 
        PRDATA_1_a0_1(9));
    
    \PRDATA_1_a1_3[5]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_769, B => N_776, C => N_2646, D => N_2644, 
        Y => PRDATA_1_a1_3(5));
    
    \PRDATA_1_a0_5[7]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_1_valpha_o_7, B => 
        FOC_TRANSFORMS_0_id_o_7, C => N_529, D => N_527, Y => 
        PRDATA_1_a0_5(7));
    
    PRDATA_m2_e_1 : CFG4
      generic map(INIT => x"8000")

      port map(A => PRDATA_m2_e_1_2_Z, B => PRDATA_m2_e_1_5_Z, C
         => PRDATA_m2_e_1_0_Z, D => PRDATA_m2_e_1_3_Z, Y => 
        PRDATA_m2_e_1_Z);
    
    \PRDATA[1]\ : CFG4
      generic map(INIT => x"1030")

      port map(A => PRDATA_1_a0_10(1), B => PRDATA_1_a1(1), C => 
        N_106, D => PRDATA_1_a0_9(1), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1);
    
    PRDATA_1_a0_6_N_4L6 : CFG4
      generic map(INIT => x"3F5F")

      port map(A => SPEED_ID_IQ_PI_1_id_pi_output_o(1), B => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1), C => N_518, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR_2, Y => 
        PRDATA_1_a0_6_N_4L6_Z);
    
    PRDATA_1_a0_6_N_3L4 : CFG3
      generic map(INIT => x"80")

      port map(A => prdata_m1_0_a2_2_0, B => N_508, C => 
        adc_measurements_0_adc_result_ch1_o_1, Y => 
        PRDATA_1_a0_6_N_3L4_Z);
    
    \PRDATA_1_a1[4]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => PRDATA_1_a1_3(4), B => PRDATA_1_a1_0(4), C
         => PRDATA_1_a1_2(4), D => PRDATA_1_a1_1(4), Y => 
        PRDATA_1_a1(4));
    
    \PRDATA_sx[10]\ : CFG4
      generic map(INIT => x"8F0F")

      port map(A => PRDATA_1_a1_3(10), B => PRDATA_sx_1(10), C
         => N_106, D => PRDATA_1_a1_2(10), Y => PRDATA_sx(10));
    
    PRDATA_m2_e_1_0 : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_vbeta_o_15, B => 
        FOC_TRANSFORMS_0_iq_o_15, C => N_533, D => N_531, Y => 
        PRDATA_m2_e_1_0_Z);
    
    \PRDATA[10]\ : CFG4
      generic map(INIT => x"007F")

      port map(A => PRDATA_1(10), B => PRDATA_1_0(10), C => 
        PRDATA_1_a0_9(10), D => PRDATA_sx(10), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10);
    
    PRDATA_m3_0_a3_6_0 : CFG4
      generic map(INIT => x"007F")

      port map(A => m20_m2_0_a2_1, B => N_513, C => N_503, D => 
        N_349, Y => PRDATA_m3_0_a3_6_0_Z);
    
    PRDATA_m2_e_1_5 : CFG4
      generic map(INIT => x"135F")

      port map(A => ADC_SCALING_0_ib_adc_o_14, B => 
        ADC_SCALING_0_ia_adc_o_15, C => N_528, D => N_524, Y => 
        PRDATA_m2_e_1_5_Z);
    
    \PRDATA_1_a3_0_1[2]\ : CFG4
      generic map(INIT => x"0007")

      port map(A => N_1345, B => N_2647, C => N_2531, D => 
        prdata_o_1_2_0_0_1(2), Y => PRDATA_1_a3_0_1(2));
    
    \PRDATA_1[19]\ : CFG4
      generic map(INIT => x"FAEA")

      port map(A => N_42, B => N_122, C => 
        MC_System_0_AMBA_SLAVE_1_PSELx, D => N_320, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19);
    
    PRDATA_m2_e_2_3 : CFG4
      generic map(INIT => x"0007")

      port map(A => N_527, B => FOC_TRANSFORMS_0_id_o_12, C => 
        N_454, D => prdata_o_1_0_iv_0_3_0, Y => PRDATA_m2_e_2_3_Z);
    
    \PRDATA_1_a3_1[3]\ : CFG4
      generic map(INIT => x"FFDC")

      port map(A => PRDATA_1_a3_1_1(3), B => PRDATA_1_a3_d(3), C
         => MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        PRDATA_1_a3_1_0(3), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3);
    
    \PRDATA_1_a3_0[6]\ : CFG4
      generic map(INIT => x"CCC8")

      port map(A => prdata_o_1_8_2(6), B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => prdata_o_1_8_3(6), D
         => prdata_o_1_8_0(6), Y => N_92);
    
    \PRDATA_1_a1_0[1]\ : CFG4
      generic map(INIT => x"1555")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), B => 
        SEQ_CONTROLLER_1_state_o_0_d0, C => N_542, D => 
        prdata_o_1_iv_0_0_4_2_1_0(3), Y => PRDATA_1_a1_0(1));
    
    \PRDATA_1_a0_2[5]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_vbeta_o_5, B => 
        FOC_TRANSFORMS_0_iq_o_5, C => N_533, D => N_531, Y => 
        PRDATA_1_a0_2(5));
    
    \PRDATA_1_a0_6[8]\ : CFG3
      generic map(INIT => x"70")

      port map(A => adc_interface_0_result_ch0_o_8, B => N_534, C
         => PRDATA_1_a0_3(8), Y => PRDATA_1_2(8));
    
    \PRDATA_1_a0_1[1]\ : CFG4
      generic map(INIT => x"07FF")

      port map(A => adc_measurements_0_adc_result_ch3_o(1), B => 
        N_513, C => prdata_o_1_iv_0_0_a2_14_1(1), D => N_522, Y
         => PRDATA_1_a0_1(1));
    
    \PRDATA_1_a1_3[7]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_876, B => N_882, C => N_2646, D => N_2644, 
        Y => PRDATA_1_a1_3(7));
    
    \PRDATA_1_a0_9[9]\ : CFG4
      generic map(INIT => x"7000")

      port map(A => N_534, B => adc_interface_0_result_ch0_o_9, C
         => PRDATA_1_a0_7(9), D => PRDATA_1_a0_3(9), Y => 
        PRDATA_1(9));
    
    \PRDATA_sx[7]\ : CFG4
      generic map(INIT => x"8F0F")

      port map(A => PRDATA_1_a1_3(7), B => PRDATA_1_a1_4(7), C
         => N_106, D => PRDATA_1_a1_2(7), Y => PRDATA_sx(7));
    
    \PRDATA_1_a1_0[4]\ : CFG3
      generic map(INIT => x"13")

      port map(A => N_2652, B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), C => 
        N_789, Y => PRDATA_1_a1_0(4));
    
    PRDATA_1_a3_1_N_4L5_1 : CFG4
      generic map(INIT => x"1555")

      port map(A => N_2574, B => N_2631, C => 
        prdata_o_1_2_0_a2_12_0(1), D => N_1346, Y => 
        PRDATA_1_a3_1_N_4L5_1_Z);
    
    \PRDATA_1_a0_5[9]\ : CFG4
      generic map(INIT => x"70F0")

      port map(A => prdata_m1_0_a2_2_0, B => 
        adc_measurements_0_adc_result_ch1_o_9, C => 
        PRDATA_1_a0_2(9), D => N_508, Y => PRDATA_1_0(9));
    
    \PRDATA_1[18]\ : CFG4
      generic map(INIT => x"FAEA")

      port map(A => N_42, B => N_122, C => 
        MC_System_0_AMBA_SLAVE_1_PSELx, D => N_321, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18);
    
    \PRDATA_1_a0_2[9]\ : CFG4
      generic map(INIT => x"070F")

      port map(A => N_509, B => STEPPER_THETA_1_step_count_o_3, C
         => prdata_o_1_0_iv_0_5_5, D => N_514, Y => 
        PRDATA_1_a0_2(9));
    
    PRDATA_m8_0_a3_sx_N_6L10 : CFG4
      generic map(INIT => x"3B7F")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR_3, B => 
        prdata_m2_e_0, C => FOC_TRANSFORMS_0_vbeta_o_0, D => 
        FOC_TRANSFORMS_0_iq_o_0, Y => PRDATA_m8_0_a3_sx_N_6L10_Z);
    
    \PRDATA_1_a0_5[10]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_1_valpha_o_10, B => 
        FOC_TRANSFORMS_0_id_o_10, C => N_529, D => N_527, Y => 
        PRDATA_1(10));
    
    \PRDATA_1_a0_3[8]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_1_valpha_o_8, B => 
        FOC_TRANSFORMS_0_id_o_8, C => N_529, D => N_527, Y => 
        PRDATA_1_a0_3(8));
    
    PRDATA_m8_0_a3_sx : CFG4
      generic map(INIT => x"FF70")

      port map(A => PRDATA_m8_0_a3_sx_N_6L10_Z, B => 
        PRDATA_m8_0_a3_sx_N_2L1_Z, C => N_508, D => 
        PRDATA_m8_0_a3_sx_N_5L8_Z, Y => PRDATA_m8_0_a3_sx_Z);
    
    \PRDATA_1_a0_4[9]\ : CFG4
      generic map(INIT => x"40C0")

      port map(A => prdata_o_1_0_iv_0_0_0_5, B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), C => 
        PRDATA_1_a0_1(9), D => N_522, Y => PRDATA_1_a0_4(9));
    
    \PRDATA_1_RNO_0[6]\ : CFG4
      generic map(INIT => x"0070")

      port map(A => N_534, B => adc_interface_0_result_ch0_o_6, C
         => r_m3_0_a2_1_0, D => prdata_o_1_0_iv_0_5_2, Y => 
        r_m3_0_a2_1_1);
    
    PRDATA_m2_e_2 : CFG4
      generic map(INIT => x"8000")

      port map(A => PRDATA_m2_e_2_5_Z, B => PRDATA_m2_e_2_0_Z, C
         => PRDATA_m2_e_2_3_Z, D => PRDATA_m2_e_2_2_Z, Y => 
        PRDATA_m2_e_2_Z);
    
    \PRDATA_1_RNO_0[11]\ : CFG4
      generic map(INIT => x"0070")

      port map(A => N_534, B => adc_interface_0_result_ch0_o_11, 
        C => r_m3_0_a2_0, D => prdata_o_1_0_iv_0_5_7, Y => 
        r_m3_0_a2_1);
    
    \PRDATA_1_a1_3[9]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_770, B => N_777, C => N_2646, D => N_2644, 
        Y => PRDATA_1_a1_3(9));
    
    PRDATA_m2_e_1_3 : CFG4
      generic map(INIT => x"0007")

      port map(A => FOC_TRANSFORMS_0_id_o_15, B => N_527, C => 
        N_494, D => prdata_o_1_0_iv_0_3_3, Y => PRDATA_m2_e_1_3_Z);
    
    \PRDATA_1_RNO[6]\ : CFG4
      generic map(INIT => x"1300")

      port map(A => ADC_SCALING_0_ia_adc_o_6, B => N_396, C => 
        N_524, D => r_m3_0_a2_1_1, Y => r_N_7_mux_0);
    
    PRDATA_m3_0_a3_6 : CFG4
      generic map(INIT => x"4000")

      port map(A => m20_i_11_5, B => PRDATA_m3_0_a3_6_1_Z, C => 
        PRDATA_m3_0_a3_6_3_Z, D => PRDATA_m3_0_a3_6_0_Z, Y => 
        PRDATA_m3_0_a3_6_Z);
    
    \PRDATA_1_a1_3[10]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_790, B => N_895, C => N_2646, D => N_2644, 
        Y => PRDATA_1_a1_3(10));
    
    \PRDATA_1_a0_8_1_1[5]\ : CFG4
      generic map(INIT => x"4CCC")

      port map(A => adc_measurements_0_adc_result_ch1_o_5, B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), C => 
        prdata_m1_0_a2_2_0, D => N_508, Y => PRDATA_1_a0_8_1_1(5));
    
    \PRDATA_1_a0_7[5]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => ADC_SCALING_0_ib_adc_o_4, B => 
        ADC_SCALING_0_ia_adc_o_5, C => N_528, D => N_524, Y => 
        PRDATA_1_1(5));
    
    \PRDATA_1_a1_5[1]\ : CFG4
      generic map(INIT => x"4C00")

      port map(A => N_766, B => PRDATA_1_a1_0(1), C => N_2652, D
         => PRDATA_1_a1_2(1), Y => PRDATA_1_a1_5(1));
    
    PRDATA_m4_0_a2_2 : CFG4
      generic map(INIT => x"2000")

      port map(A => PRDATA_m4_0_a2_2_2_Z, B => N_363, C => 
        PRDATA_m4_0_a2_2_3_Z, D => PRDATA_m4_0_a2_2_1_Z, Y => 
        PRDATA_N_9_mux_0);
    
    \PRDATA_1_a0_2[8]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_vbeta_o_8, B => 
        FOC_TRANSFORMS_0_iq_o_8, C => N_533, D => N_531, Y => 
        PRDATA_1_a0_2(8));
    
    PRDATA_m4_0_a2_6_1 : CFG4
      generic map(INIT => x"1300")

      port map(A => N_522, B => N_397, C => 
        prdata_o_1_0_iv_0_0_0_2, D => 
        MC_System_0_AMBA_SLAVE_1_PSELx, Y => PRDATA_m4_0_a2_6_1_Z);
    
    \PRDATA_1_a1_4[10]\ : CFG4
      generic map(INIT => x"040C")

      port map(A => N_2652, B => PRDATA_1_a1_1(10), C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D => 
        N_891, Y => PRDATA_sx_1(10));
    
    \PRDATA_1_a1_3[8]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_883, B => N_1333, C => N_2644, D => N_2646, 
        Y => PRDATA_1_a1_3(8));
    
    \PRDATA_1_a1_2[9]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_773, B => N_750, C => N_2639, D => N_2647, 
        Y => PRDATA_1_a1_2(9));
    
    \PRDATA_1[17]\ : CFG4
      generic map(INIT => x"FAEA")

      port map(A => N_42, B => N_122, C => 
        MC_System_0_AMBA_SLAVE_1_PSELx, D => N_315, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17);
    
    \PRDATA_1_a1_2[5]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_772, B => N_749, C => N_2639, D => N_2647, 
        Y => PRDATA_1_a1_2(5));
    
    \PRDATA_1_a0_8_1[8]\ : CFG4
      generic map(INIT => x"0444")

      port map(A => prdata_o_1_0_iv_0_5_4, B => 
        PRDATA_1_a0_8_1_1(8), C => prdata_o_1_0_iv_0_0_0_4, D => 
        N_522, Y => PRDATA_1_a0_8_1(8));
    
    \PRDATA_1_a0_8[8]\ : CFG4
      generic map(INIT => x"7000")

      port map(A => N_514, B => prdata_o_1_0_iv_0_2_tz_4, C => 
        PRDATA_1_a0_8_1(8), D => PRDATA_1_a0_2(8), Y => 
        PRDATA_1(8));
    
    \PRDATA_3[23]\ : CFG4
      generic map(INIT => x"AE0C")

      port map(A => N_514, B => MC_System_0_AMBA_SLAVE_0_PSELx, C
         => PRDATA_3_1(23), D => PRDATA_m6_0_c_1_Z, Y => 
        PRDATA_3(23));
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity CoreAPB3 is

    port( MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : in    std_logic_vector(15 downto 12);
          prdata_o_1_2_0_a2_11_0                            : in    std_logic_vector(1 to 1);
          prdata_o_1_2_0_a2_12_0                            : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_26_0                         : in    std_logic_vector(1 to 1);
          prdata_o_1_2_0_0_2                                : in    std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_0                                : in    std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_1                                : in    std_logic_vector(2 to 2);
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI                 : in    std_logic_vector(0 to 0);
          prdata_o_1_2_0_a2_17_0                            : in    std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_a2_20_0                         : in    std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_a2_24_0                         : in    std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_0_0_0                           : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1_6_tz                          : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1                               : in    std_logic_vector(7 to 7);
          prdata_o_1_0_iv_0_0                               : in    std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_0_2_tz_tz                       : in    std_logic_vector(0 to 0);
          prdata_o_1_iv_0_0_4_2_1_0                         : in    std_logic_vector(3 to 3);
          SPEED_ID_IQ_PI_1_id_pi_output_o                   : in    std_logic_vector(1 downto 0);
          SPEED_ID_IQ_PI_1_iq_pi_output_o                   : in    std_logic_vector(1 downto 0);
          prdata_o_1_2_0_0_4_2                              : in    std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_5_0                          : in    std_logic_vector(3 to 3);
          STEPPER_THETA_0_theta_output_o                    : in    std_logic_vector(17 to 17);
          MC_System_0_AMBA_SLAVE_1_PADDR_3                  : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PADDR_2                  : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PADDR_1                  : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PADDR_8                  : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PADDR_0                  : in    std_logic;
          prdata_o_1_iv_0_0_a2_45_0                         : in    std_logic_vector(0 to 0);
          adc_measurements_0_adc_result_ch3_o               : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_14_1                         : in    std_logic_vector(1 to 1);
          SEQ_CONTROLLER_1_state_o_0                        : in    std_logic_vector(1 to 1);
          SEQ_CONTROLLER_1_state_o_2                        : in    std_logic;
          SEQ_CONTROLLER_1_state_o_0_d0                     : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_1                          : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_4                          : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_0                          : in    std_logic;
          prdata_o_1_0_iv_0_12_1                            : in    std_logic_vector(7 to 7);
          prdata_o_1_0_iv_0_12_4                            : in    std_logic_vector(8 to 8);
          prdata_o_1_0_iv_0_a2_19_0                         : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1_1                             : in    std_logic_vector(10 to 10);
          FOC_TRANSFORMS_1_valpha_o_0                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_5                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_8                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_9                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_4                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_7                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_10                      : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_6                       : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_11                      : in    std_logic;
          STEPPER_THETA_1_step_count_o_17                   : in    std_logic;
          STEPPER_THETA_1_step_count_o_3                    : in    std_logic;
          STEPPER_THETA_1_step_count_o_6                    : in    std_logic;
          STEPPER_THETA_1_step_count_o_9                    : in    std_logic;
          STEPPER_THETA_1_step_count_o_0                    : in    std_logic;
          STEPPER_THETA_1_step_count_o_5                    : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_3                        : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_0                        : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_5                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_0                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_3                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_5                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_8                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_12                       : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_15                       : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_7                        : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_10                       : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_2                        : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_0                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_1                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_5                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_8                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_12                          : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_15                          : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_7                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_10                          : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_6                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_11                          : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_2                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_1                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_4                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_0_d0                        : in    std_logic;
          prdata_o_1_0_iv_0_0_0_2                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_7                           : in    std_logic;
          prdata_o_1_0_iv_0_0_0_5                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_0                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_5                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_8                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_9                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_7                           : in    std_logic;
          FOC_TRANSFORMS_0_id_o_10                          : in    std_logic;
          FOC_TRANSFORMS_0_id_o_12                          : in    std_logic;
          FOC_TRANSFORMS_0_id_o_15                          : in    std_logic;
          prdata_o_1_0_iv_0_3_0                             : in    std_logic;
          prdata_o_1_0_iv_0_3_3                             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_0             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_5             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_8             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_10            : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_1             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_9             : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_7             : in    std_logic;
          adc_interface_0_result_ch0_o_6                    : in    std_logic;
          adc_interface_0_result_ch0_o_11                   : in    std_logic;
          adc_interface_0_result_ch0_o_7                    : in    std_logic;
          adc_interface_0_result_ch0_o_0                    : in    std_logic;
          adc_interface_0_result_ch0_o_5                    : in    std_logic;
          adc_interface_0_result_ch0_o_8                    : in    std_logic;
          adc_interface_0_result_ch0_o_9                    : in    std_logic;
          ADC_SCALING_0_ia_adc_o_0                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_7                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_10                         : in    std_logic;
          ADC_SCALING_0_ia_adc_o_2                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_5                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_8                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_9                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_12                         : in    std_logic;
          ADC_SCALING_0_ia_adc_o_15                         : in    std_logic;
          ADC_SCALING_0_ia_adc_o_4                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_1                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_6                          : in    std_logic;
          ADC_SCALING_0_ia_adc_o_11                         : in    std_logic;
          prdata_o_1_0_iv_0_1_o2_0                          : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_11                              : in    std_logic_vector(3 to 3);
          prdata_o_1_2_0_0_5                                : in    std_logic_vector(3 to 3);
          ADC_SCALING_0_ib_adc_o_10                         : in    std_logic;
          ADC_SCALING_0_ib_adc_o_5                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_4                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_7                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_8                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_11                         : in    std_logic;
          ADC_SCALING_0_ib_adc_o_14                         : in    std_logic;
          ADC_SCALING_0_ib_adc_o_3                          : in    std_logic;
          ADC_SCALING_0_ib_adc_o_0                          : in    std_logic;
          prdata_o_1_iv_0_0_0_3_tz                          : in    std_logic_vector(1 to 1);
          prdata_o_1_0_1                                    : in    std_logic_vector(16 to 16);
          prdata_o_1_0_2                                    : in    std_logic_vector(16 to 16);
          prdata_o_1_0_0                                    : in    std_logic_vector(16 to 16);
          prdata_o_1_3_0_0_2                                : in    std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_3                                : in    std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_0                                : in    std_logic_vector(11 to 11);
          prdata_o_1_8_2                                    : in    std_logic_vector(6 to 6);
          prdata_o_1_8_3                                    : in    std_logic_vector(6 to 6);
          prdata_o_1_8_0                                    : in    std_logic_vector(6 to 6);
          prdata_o_1_iv_0_0_12_4_3                          : in    std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_4_2                          : in    std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_5_1                             : in    std_logic;
          prdata_o_1_0_iv_0_5_4                             : in    std_logic;
          prdata_o_1_0_iv_0_5_2                             : in    std_logic;
          prdata_o_1_0_iv_0_5_7                             : in    std_logic;
          prdata_o_1_0_iv_0_5_5                             : in    std_logic;
          prdata_o_1_0_iv_0_5_0                             : in    std_logic;
          prdata_o_1_0_iv_0_5_12                            : in    std_logic;
          prdata_o_1_0_iv_0_6                               : in    std_logic_vector(16 to 16);
          MC_System_0_AMBA_SLAVE_1_PRDATA                   : in    std_logic_vector(14 downto 13);
          MC_System_0_AMBA_SLAVE_0_PRDATA_0                 : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_15                : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_12                : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_13                : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_14                : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx                    : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx                    : out   std_logic;
          N_1342                                            : in    std_logic;
          N_2598                                            : in    std_logic;
          N_2644                                            : in    std_logic;
          N_1396                                            : in    std_logic;
          N_2631                                            : in    std_logic;
          prdata_m2_e_1_1                                   : in    std_logic;
          N_1360                                            : in    std_logic;
          N_1288                                            : in    std_logic;
          prdata_m1_0_a2_0                                  : in    std_logic;
          N_522                                             : in    std_logic;
          N_527                                             : in    std_logic;
          N_542                                             : in    std_logic;
          prdata_m4_e_0                                     : in    std_logic;
          prdata_m1_0_a2_2_0                                : in    std_logic;
          N_509                                             : in    std_logic;
          N_529                                             : in    std_logic;
          N_503                                             : in    std_logic;
          prdata_m2_e_0                                     : in    std_logic;
          N_508                                             : in    std_logic;
          N_2652                                            : in    std_logic;
          N_768                                             : in    std_logic;
          N_1345                                            : in    std_logic;
          N_2647                                            : in    std_logic;
          N_2531                                            : in    std_logic;
          N_513                                             : in    std_logic;
          N_502                                             : in    std_logic;
          N_534                                             : in    std_logic;
          N_500                                             : in    std_logic;
          N_514                                             : in    std_logic;
          N_506                                             : in    std_logic;
          N_505                                             : in    std_logic;
          N_518                                             : in    std_logic;
          N_2574                                            : in    std_logic;
          N_1346                                            : in    std_logic;
          N_531                                             : in    std_logic;
          N_2640                                            : in    std_logic;
          N_738                                             : in    std_logic;
          N_533                                             : in    std_logic;
          N_507                                             : in    std_logic;
          prdata_m1_e_0_1                                   : in    std_logic;
          N_1398                                            : in    std_logic;
          N_1378                                            : in    std_logic;
          N_2627                                            : in    std_logic;
          prdata_m2_0_a2_0                                  : in    std_logic;
          N_455                                             : in    std_logic;
          N_495                                             : in    std_logic;
          N_892                                             : in    std_logic;
          N_771                                             : in    std_logic;
          N_773                                             : in    std_logic;
          N_750                                             : in    std_logic;
          N_2639                                            : in    std_logic;
          N_775                                             : in    std_logic;
          N_763                                             : in    std_logic;
          N_2645                                            : in    std_logic;
          N_1351                                            : in    std_logic;
          N_1169                                            : in    std_logic;
          N_1279                                            : in    std_logic;
          N_793                                             : in    std_logic;
          N_791                                             : in    std_logic;
          N_782                                             : in    std_logic;
          N_893                                             : in    std_logic;
          N_788                                             : in    std_logic;
          N_772                                             : in    std_logic;
          N_749                                             : in    std_logic;
          N_774                                             : in    std_logic;
          N_762                                             : in    std_logic;
          N_1347                                            : in    std_logic;
          N_1165                                            : in    std_logic;
          N_1275                                            : in    std_logic;
          N_792                                             : in    std_logic;
          N_878                                             : in    std_logic;
          N_859                                             : in    std_logic;
          N_880                                             : in    std_logic;
          N_870                                             : in    std_logic;
          prdata_m2_e_0_0                                   : in    std_logic;
          prdata_m1_e_11_0                                  : in    std_logic;
          N_414                                             : in    std_logic;
          N_516                                             : in    std_logic;
          N_397                                             : in    std_logic;
          N_355                                             : in    std_logic;
          N_198                                             : in    std_logic;
          m20_i_2_tz                                        : in    std_logic;
          m20_i_a2_0_1                                      : in    std_logic;
          m20_m2_0_a2_1                                     : in    std_logic;
          N_349                                             : in    std_logic;
          m20_i_a2_5_0                                      : in    std_logic;
          N_517                                             : in    std_logic;
          N_128                                             : in    std_logic;
          N_528                                             : in    std_logic;
          N_524                                             : in    std_logic;
          N_454                                             : in    std_logic;
          N_494                                             : in    std_logic;
          N_894                                             : in    std_logic;
          N_1326                                            : in    std_logic;
          N_2646                                            : in    std_logic;
          N_770                                             : in    std_logic;
          N_777                                             : in    std_logic;
          N_883                                             : in    std_logic;
          N_1333                                            : in    std_logic;
          N_790                                             : in    std_logic;
          N_895                                             : in    std_logic;
          N_769                                             : in    std_logic;
          N_776                                             : in    std_logic;
          N_832                                             : in    std_logic;
          N_1329                                            : in    std_logic;
          N_789                                             : in    std_logic;
          N_876                                             : in    std_logic;
          N_882                                             : in    std_logic;
          prdata_m3_i_0                                     : in    std_logic;
          N_260                                             : in    std_logic;
          N_766                                             : in    std_logic;
          N_739                                             : in    std_logic;
          N_891                                             : in    std_logic;
          N_767                                             : in    std_logic;
          N_875                                             : in    std_logic;
          N_396                                             : in    std_logic;
          N_405                                             : in    std_logic;
          N_354                                             : in    std_logic;
          N_363                                             : in    std_logic;
          prdata_N_7_2                                      : in    std_logic;
          m20_i_10_1                                        : in    std_logic;
          m20_i_10_0                                        : in    std_logic;
          N_215                                             : in    std_logic;
          N_377                                             : in    std_logic;
          N_2495                                            : in    std_logic;
          N_2498                                            : in    std_logic;
          m20_i_11_5                                        : in    std_logic;
          N_122                                             : in    std_logic;
          N_317                                             : in    std_logic;
          N_318                                             : in    std_logic;
          N_319                                             : in    std_logic;
          N_320                                             : in    std_logic;
          N_321                                             : in    std_logic;
          N_315                                             : in    std_logic;
          PRDATA_N_3_mux_i_0                                : out   std_logic
        );

end CoreAPB3;

architecture DEF_ARCH of CoreAPB3 is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component COREAPB3_MUXPTOB3
    port( prdata_o_1_2_0_a2_11_0                            : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_2_0_a2_12_0                            : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_26_0                         : in    std_logic_vector(1 to 1) := (others => 'U');
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : in    std_logic_vector(12 to 12) := (others => 'U');
          prdata_o_1_2_0_0_2                                : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_2_0_0_0                                : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_2_0_0_1                                : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI                 : in    std_logic_vector(0 to 0) := (others => 'U');
          prdata_o_1_2_0_a2_17_0                            : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_iv_0_a2_20_0                         : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_iv_0_0_a2_24_0                         : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_iv_0_0_0_0                           : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1_6_tz                          : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1                               : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_0_iv_0_0                               : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_iv_0_0_0_2_tz_tz                       : in    std_logic_vector(0 to 0) := (others => 'U');
          prdata_o_1_iv_0_0_4_2_1_0                         : in    std_logic_vector(3 to 3) := (others => 'U');
          SPEED_ID_IQ_PI_1_id_pi_output_o                   : in    std_logic_vector(1 downto 0) := (others => 'U');
          SPEED_ID_IQ_PI_1_iq_pi_output_o                   : in    std_logic_vector(1 downto 0) := (others => 'U');
          prdata_o_1_2_0_0_4_2                              : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_iv_0_0_12_5_0                          : in    std_logic_vector(3 to 3) := (others => 'U');
          STEPPER_THETA_0_theta_output_o                    : in    std_logic_vector(17 to 17) := (others => 'U');
          MC_System_0_AMBA_SLAVE_1_PADDR_3                  : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PADDR_2                  : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PADDR_1                  : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PADDR_8                  : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PADDR_0                  : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a2_45_0                         : in    std_logic_vector(0 to 0) := (others => 'U');
          adc_measurements_0_adc_result_ch3_o               : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_14_1                         : in    std_logic_vector(1 to 1) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_0                        : in    std_logic_vector(1 to 1) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_2                        : in    std_logic := 'U';
          SEQ_CONTROLLER_1_state_o_0_d0                     : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_1                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_4                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_0                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_12_1                            : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_0_iv_0_12_4                            : in    std_logic_vector(8 to 8) := (others => 'U');
          prdata_o_1_0_iv_0_a2_19_0                         : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1_1                             : in    std_logic_vector(10 to 10) := (others => 'U');
          FOC_TRANSFORMS_1_valpha_o_0                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_5                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_8                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_9                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_4                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_7                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_10                      : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_6                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_11                      : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_17                   : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_3                    : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_6                    : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_9                    : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_0                    : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_5                    : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_3                        : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_0                        : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_5                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_0                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_3                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_5                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_8                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_12                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_15                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_7                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_10                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_2                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_0                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_1                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_5                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_8                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_12                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_15                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_7                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_10                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_6                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_11                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_2                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_1                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_4                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_0_d0                        : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_2                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_7                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_5                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_0                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_5                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_8                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_9                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_7                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_10                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_12                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_15                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_3_0                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_3_3                             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_0             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_5             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_8             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_10            : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_1             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_9             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_7             : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_6                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_11                   : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_7                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_0                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_5                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_8                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_9                    : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_0                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_7                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_10                         : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_2                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_5                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_8                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_9                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_12                         : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_15                         : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_4                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_1                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_6                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_11                         : in    std_logic := 'U';
          prdata_o_1_0_iv_0_1_o2_0                          : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_11                              : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_2_0_0_5                                : in    std_logic_vector(3 to 3) := (others => 'U');
          ADC_SCALING_0_ib_adc_o_10                         : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_5                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_4                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_7                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_8                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_11                         : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_14                         : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_3                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_0                          : in    std_logic := 'U';
          prdata_o_1_iv_0_0_0_3_tz                          : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_1                                    : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_2                                    : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_0                                    : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_3_0_0_2                                : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_3_0_0_3                                : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_3_0_0_0                                : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_8_2                                    : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_8_3                                    : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_8_0                                    : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_iv_0_0_12_4_3                          : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_iv_0_0_12_4_2                          : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_0_iv_0_5_1                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_4                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_2                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_7                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_5                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_0                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_12                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6                               : in    std_logic_vector(16 to 16) := (others => 'U');
          MC_System_0_AMBA_SLAVE_1_PRDATA                   : in    std_logic_vector(14 downto 13) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA_0                 : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_15                : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_12                : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_13                : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_14                : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx                    : in    std_logic := 'U';
          N_1342                                            : in    std_logic := 'U';
          N_2598                                            : in    std_logic := 'U';
          N_2644                                            : in    std_logic := 'U';
          N_1396                                            : in    std_logic := 'U';
          N_2631                                            : in    std_logic := 'U';
          prdata_m2_e_1_1                                   : in    std_logic := 'U';
          N_1360                                            : in    std_logic := 'U';
          N_1288                                            : in    std_logic := 'U';
          prdata_m1_0_a2_0                                  : in    std_logic := 'U';
          N_522                                             : in    std_logic := 'U';
          N_527                                             : in    std_logic := 'U';
          N_542                                             : in    std_logic := 'U';
          prdata_m4_e_0                                     : in    std_logic := 'U';
          prdata_m1_0_a2_2_0                                : in    std_logic := 'U';
          N_509                                             : in    std_logic := 'U';
          N_529                                             : in    std_logic := 'U';
          N_503                                             : in    std_logic := 'U';
          prdata_m2_e_0                                     : in    std_logic := 'U';
          N_508                                             : in    std_logic := 'U';
          N_106                                             : in    std_logic := 'U';
          N_2652                                            : in    std_logic := 'U';
          N_768                                             : in    std_logic := 'U';
          N_1345                                            : in    std_logic := 'U';
          N_2647                                            : in    std_logic := 'U';
          N_2531                                            : in    std_logic := 'U';
          N_513                                             : in    std_logic := 'U';
          N_502                                             : in    std_logic := 'U';
          N_534                                             : in    std_logic := 'U';
          N_500                                             : in    std_logic := 'U';
          N_514                                             : in    std_logic := 'U';
          N_506                                             : in    std_logic := 'U';
          N_505                                             : in    std_logic := 'U';
          N_518                                             : in    std_logic := 'U';
          N_2574                                            : in    std_logic := 'U';
          N_1346                                            : in    std_logic := 'U';
          N_531                                             : in    std_logic := 'U';
          N_2640                                            : in    std_logic := 'U';
          N_738                                             : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PSELx                    : in    std_logic := 'U';
          N_533                                             : in    std_logic := 'U';
          N_507                                             : in    std_logic := 'U';
          prdata_m1_e_0_1                                   : in    std_logic := 'U';
          N_1398                                            : in    std_logic := 'U';
          N_1378                                            : in    std_logic := 'U';
          N_2627                                            : in    std_logic := 'U';
          prdata_m2_0_a2_0                                  : in    std_logic := 'U';
          N_455                                             : in    std_logic := 'U';
          N_495                                             : in    std_logic := 'U';
          N_892                                             : in    std_logic := 'U';
          N_771                                             : in    std_logic := 'U';
          N_773                                             : in    std_logic := 'U';
          N_750                                             : in    std_logic := 'U';
          N_2639                                            : in    std_logic := 'U';
          N_775                                             : in    std_logic := 'U';
          N_763                                             : in    std_logic := 'U';
          N_2645                                            : in    std_logic := 'U';
          N_1351                                            : in    std_logic := 'U';
          N_1169                                            : in    std_logic := 'U';
          N_1279                                            : in    std_logic := 'U';
          N_793                                             : in    std_logic := 'U';
          N_791                                             : in    std_logic := 'U';
          N_782                                             : in    std_logic := 'U';
          N_893                                             : in    std_logic := 'U';
          N_788                                             : in    std_logic := 'U';
          N_772                                             : in    std_logic := 'U';
          N_749                                             : in    std_logic := 'U';
          N_774                                             : in    std_logic := 'U';
          N_762                                             : in    std_logic := 'U';
          N_1347                                            : in    std_logic := 'U';
          N_1165                                            : in    std_logic := 'U';
          N_1275                                            : in    std_logic := 'U';
          N_792                                             : in    std_logic := 'U';
          N_878                                             : in    std_logic := 'U';
          N_859                                             : in    std_logic := 'U';
          N_880                                             : in    std_logic := 'U';
          N_870                                             : in    std_logic := 'U';
          prdata_m2_e_0_0                                   : in    std_logic := 'U';
          prdata_m1_e_11_0                                  : in    std_logic := 'U';
          N_414                                             : in    std_logic := 'U';
          N_516                                             : in    std_logic := 'U';
          N_397                                             : in    std_logic := 'U';
          N_355                                             : in    std_logic := 'U';
          N_198                                             : in    std_logic := 'U';
          m20_i_2_tz                                        : in    std_logic := 'U';
          m20_i_a2_0_1                                      : in    std_logic := 'U';
          m20_m2_0_a2_1                                     : in    std_logic := 'U';
          N_349                                             : in    std_logic := 'U';
          m20_i_a2_5_0                                      : in    std_logic := 'U';
          N_517                                             : in    std_logic := 'U';
          N_128                                             : in    std_logic := 'U';
          N_528                                             : in    std_logic := 'U';
          N_524                                             : in    std_logic := 'U';
          N_454                                             : in    std_logic := 'U';
          N_494                                             : in    std_logic := 'U';
          N_894                                             : in    std_logic := 'U';
          N_1326                                            : in    std_logic := 'U';
          N_2646                                            : in    std_logic := 'U';
          N_770                                             : in    std_logic := 'U';
          N_777                                             : in    std_logic := 'U';
          N_883                                             : in    std_logic := 'U';
          N_1333                                            : in    std_logic := 'U';
          N_790                                             : in    std_logic := 'U';
          N_895                                             : in    std_logic := 'U';
          N_769                                             : in    std_logic := 'U';
          N_776                                             : in    std_logic := 'U';
          N_832                                             : in    std_logic := 'U';
          N_1329                                            : in    std_logic := 'U';
          N_789                                             : in    std_logic := 'U';
          N_876                                             : in    std_logic := 'U';
          N_882                                             : in    std_logic := 'U';
          prdata_m3_i_0                                     : in    std_logic := 'U';
          N_260                                             : in    std_logic := 'U';
          N_766                                             : in    std_logic := 'U';
          N_739                                             : in    std_logic := 'U';
          N_891                                             : in    std_logic := 'U';
          N_767                                             : in    std_logic := 'U';
          N_875                                             : in    std_logic := 'U';
          N_396                                             : in    std_logic := 'U';
          N_405                                             : in    std_logic := 'U';
          N_354                                             : in    std_logic := 'U';
          N_363                                             : in    std_logic := 'U';
          prdata_N_7_2                                      : in    std_logic := 'U';
          m20_i_10_1                                        : in    std_logic := 'U';
          m20_i_10_0                                        : in    std_logic := 'U';
          N_215                                             : in    std_logic := 'U';
          N_377                                             : in    std_logic := 'U';
          N_2495                                            : in    std_logic := 'U';
          N_2498                                            : in    std_logic := 'U';
          m20_i_11_5                                        : in    std_logic := 'U';
          N_122                                             : in    std_logic := 'U';
          N_317                                             : in    std_logic := 'U';
          N_318                                             : in    std_logic := 'U';
          N_319                                             : in    std_logic := 'U';
          N_320                                             : in    std_logic := 'U';
          N_321                                             : in    std_logic := 'U';
          N_315                                             : in    std_logic := 'U';
          PRDATA_N_3_mux_i_0                                : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \MC_System_0_AMBA_SLAVE_0_PSELx\, 
        \MC_System_0_AMBA_SLAVE_1_PSELx\, N_106, \GND\, \VCC\
         : std_logic;

    for all : COREAPB3_MUXPTOB3
	Use entity work.COREAPB3_MUXPTOB3(DEF_ARCH);
begin 

    MC_System_0_AMBA_SLAVE_0_PSELx <= 
        \MC_System_0_AMBA_SLAVE_0_PSELx\;
    MC_System_0_AMBA_SLAVE_1_PSELx <= 
        \MC_System_0_AMBA_SLAVE_1_PSELx\;

    \iPSELS_raw_0_a2_0[0]\ : CFG4
      generic map(INIT => x"0004")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15), B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, C => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14), D => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13), Y => 
        N_106);
    
    \iPSELS_raw_0_a2[1]\ : CFG2
      generic map(INIT => x"8")

      port map(A => N_106, B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), Y => 
        \MC_System_0_AMBA_SLAVE_1_PSELx\);
    
    \iPSELS_raw_0_a2[0]\ : CFG2
      generic map(INIT => x"2")

      port map(A => N_106, B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), Y => 
        \MC_System_0_AMBA_SLAVE_0_PSELx\);
    
    u_mux_p_to_b3 : COREAPB3_MUXPTOB3
      port map(prdata_o_1_2_0_a2_11_0(1) => 
        prdata_o_1_2_0_a2_11_0(1), prdata_o_1_2_0_a2_12_0(1) => 
        prdata_o_1_2_0_a2_12_0(1), prdata_o_1_iv_0_0_a2_26_0(1)
         => prdata_o_1_iv_0_0_a2_26_0(1), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), 
        prdata_o_1_2_0_0_2(2) => prdata_o_1_2_0_0_2(2), 
        prdata_o_1_2_0_0_0(2) => prdata_o_1_2_0_0_0(2), 
        prdata_o_1_2_0_0_1(2) => prdata_o_1_2_0_0_1(2), 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0) => 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0), 
        prdata_o_1_2_0_a2_17_0(1) => prdata_o_1_2_0_a2_17_0(1), 
        prdata_o_1_0_iv_0_a2_20_0(10) => 
        prdata_o_1_0_iv_0_a2_20_0(10), 
        prdata_o_1_iv_0_0_a2_24_0(1) => 
        prdata_o_1_iv_0_0_a2_24_0(1), prdata_o_1_0_iv_0_0_0_0(10)
         => prdata_o_1_0_iv_0_0_0_0(10), 
        prdata_o_1_0_iv_0_1_6_tz(10) => 
        prdata_o_1_0_iv_0_1_6_tz(10), prdata_o_1_0_iv_0_1(7) => 
        prdata_o_1_0_iv_0_1(7), prdata_o_1_0_iv_0_0(7) => 
        prdata_o_1_0_iv_0_0(7), prdata_o_1_iv_0_0_0_2_tz_tz(0)
         => prdata_o_1_iv_0_0_0_2_tz_tz(0), 
        prdata_o_1_iv_0_0_4_2_1_0(3) => 
        prdata_o_1_iv_0_0_4_2_1_0(3), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0), 
        prdata_o_1_2_0_0_4_2(3) => prdata_o_1_2_0_0_4_2(3), 
        prdata_o_1_iv_0_0_12_5_0(3) => 
        prdata_o_1_iv_0_0_12_5_0(3), 
        STEPPER_THETA_0_theta_output_o(17) => 
        STEPPER_THETA_0_theta_output_o(17), 
        MC_System_0_AMBA_SLAVE_1_PADDR_3 => 
        MC_System_0_AMBA_SLAVE_1_PADDR_3, 
        MC_System_0_AMBA_SLAVE_1_PADDR_2 => 
        MC_System_0_AMBA_SLAVE_1_PADDR_2, 
        MC_System_0_AMBA_SLAVE_1_PADDR_1 => 
        MC_System_0_AMBA_SLAVE_1_PADDR_1, 
        MC_System_0_AMBA_SLAVE_1_PADDR_8 => 
        MC_System_0_AMBA_SLAVE_1_PADDR_8, 
        MC_System_0_AMBA_SLAVE_1_PADDR_0 => 
        MC_System_0_AMBA_SLAVE_1_PADDR_0, 
        prdata_o_1_iv_0_0_a2_45_0(0) => 
        prdata_o_1_iv_0_0_a2_45_0(0), 
        adc_measurements_0_adc_result_ch3_o(1) => 
        adc_measurements_0_adc_result_ch3_o(1), 
        prdata_o_1_iv_0_0_a2_14_1(1) => 
        prdata_o_1_iv_0_0_a2_14_1(1), 
        SEQ_CONTROLLER_1_state_o_0(1) => 
        SEQ_CONTROLLER_1_state_o_0(1), SEQ_CONTROLLER_1_state_o_2
         => SEQ_CONTROLLER_1_state_o_2, 
        SEQ_CONTROLLER_1_state_o_0_d0 => 
        SEQ_CONTROLLER_1_state_o_0_d0, prdata_o_1_0_iv_0_2_tz_1
         => prdata_o_1_0_iv_0_2_tz_1, prdata_o_1_0_iv_0_2_tz_4
         => prdata_o_1_0_iv_0_2_tz_4, prdata_o_1_0_iv_0_2_tz_0
         => prdata_o_1_0_iv_0_2_tz_0, prdata_o_1_0_iv_0_12_1(7)
         => prdata_o_1_0_iv_0_12_1(7), prdata_o_1_0_iv_0_12_4(8)
         => prdata_o_1_0_iv_0_12_4(8), 
        prdata_o_1_0_iv_0_a2_19_0(10) => 
        prdata_o_1_0_iv_0_a2_19_0(10), prdata_o_1_0_iv_0_1_1(10)
         => prdata_o_1_0_iv_0_1_1(10), 
        FOC_TRANSFORMS_1_valpha_o_0 => 
        FOC_TRANSFORMS_1_valpha_o_0, FOC_TRANSFORMS_1_valpha_o_5
         => FOC_TRANSFORMS_1_valpha_o_5, 
        FOC_TRANSFORMS_1_valpha_o_8 => 
        FOC_TRANSFORMS_1_valpha_o_8, FOC_TRANSFORMS_1_valpha_o_9
         => FOC_TRANSFORMS_1_valpha_o_9, 
        FOC_TRANSFORMS_1_valpha_o_4 => 
        FOC_TRANSFORMS_1_valpha_o_4, FOC_TRANSFORMS_1_valpha_o_7
         => FOC_TRANSFORMS_1_valpha_o_7, 
        FOC_TRANSFORMS_1_valpha_o_10 => 
        FOC_TRANSFORMS_1_valpha_o_10, FOC_TRANSFORMS_1_valpha_o_6
         => FOC_TRANSFORMS_1_valpha_o_6, 
        FOC_TRANSFORMS_1_valpha_o_11 => 
        FOC_TRANSFORMS_1_valpha_o_11, 
        STEPPER_THETA_1_step_count_o_17 => 
        STEPPER_THETA_1_step_count_o_17, 
        STEPPER_THETA_1_step_count_o_3 => 
        STEPPER_THETA_1_step_count_o_3, 
        STEPPER_THETA_1_step_count_o_6 => 
        STEPPER_THETA_1_step_count_o_6, 
        STEPPER_THETA_1_step_count_o_9 => 
        STEPPER_THETA_1_step_count_o_9, 
        STEPPER_THETA_1_step_count_o_0 => 
        STEPPER_THETA_1_step_count_o_0, 
        STEPPER_THETA_1_step_count_o_5 => 
        STEPPER_THETA_1_step_count_o_5, 
        prdata_o_1_0_iv_0_a2_6_2_3 => prdata_o_1_0_iv_0_a2_6_2_3, 
        prdata_o_1_0_iv_0_a2_6_2_0 => prdata_o_1_0_iv_0_a2_6_2_0, 
        prdata_o_1_0_iv_0_a2_6_2_5 => prdata_o_1_0_iv_0_a2_6_2_5, 
        FOC_TRANSFORMS_0_vbeta_o_0 => FOC_TRANSFORMS_0_vbeta_o_0, 
        FOC_TRANSFORMS_0_vbeta_o_3 => FOC_TRANSFORMS_0_vbeta_o_3, 
        FOC_TRANSFORMS_0_vbeta_o_5 => FOC_TRANSFORMS_0_vbeta_o_5, 
        FOC_TRANSFORMS_0_vbeta_o_8 => FOC_TRANSFORMS_0_vbeta_o_8, 
        FOC_TRANSFORMS_0_vbeta_o_12 => 
        FOC_TRANSFORMS_0_vbeta_o_12, FOC_TRANSFORMS_0_vbeta_o_15
         => FOC_TRANSFORMS_0_vbeta_o_15, 
        FOC_TRANSFORMS_0_vbeta_o_7 => FOC_TRANSFORMS_0_vbeta_o_7, 
        FOC_TRANSFORMS_0_vbeta_o_10 => 
        FOC_TRANSFORMS_0_vbeta_o_10, FOC_TRANSFORMS_0_vbeta_o_2
         => FOC_TRANSFORMS_0_vbeta_o_2, FOC_TRANSFORMS_0_iq_o_0
         => FOC_TRANSFORMS_0_iq_o_0, FOC_TRANSFORMS_0_iq_o_1 => 
        FOC_TRANSFORMS_0_iq_o_1, FOC_TRANSFORMS_0_iq_o_3 => 
        FOC_TRANSFORMS_0_iq_o_3, FOC_TRANSFORMS_0_iq_o_5 => 
        FOC_TRANSFORMS_0_iq_o_5, FOC_TRANSFORMS_0_iq_o_8 => 
        FOC_TRANSFORMS_0_iq_o_8, FOC_TRANSFORMS_0_iq_o_12 => 
        FOC_TRANSFORMS_0_iq_o_12, FOC_TRANSFORMS_0_iq_o_15 => 
        FOC_TRANSFORMS_0_iq_o_15, FOC_TRANSFORMS_0_iq_o_7 => 
        FOC_TRANSFORMS_0_iq_o_7, FOC_TRANSFORMS_0_iq_o_10 => 
        FOC_TRANSFORMS_0_iq_o_10, FOC_TRANSFORMS_0_iq_o_6 => 
        FOC_TRANSFORMS_0_iq_o_6, FOC_TRANSFORMS_0_iq_o_11 => 
        FOC_TRANSFORMS_0_iq_o_11, FOC_TRANSFORMS_0_iq_o_2 => 
        FOC_TRANSFORMS_0_iq_o_2, prdata_o_1_0_iv_0_0_0_1 => 
        prdata_o_1_0_iv_0_0_0_1, prdata_o_1_0_iv_0_0_0_4 => 
        prdata_o_1_0_iv_0_0_0_4, prdata_o_1_0_iv_0_0_0_0_d0 => 
        prdata_o_1_0_iv_0_0_0_0_d0, prdata_o_1_0_iv_0_0_0_2 => 
        prdata_o_1_0_iv_0_0_0_2, prdata_o_1_0_iv_0_0_0_7 => 
        prdata_o_1_0_iv_0_0_0_7, prdata_o_1_0_iv_0_0_0_5 => 
        prdata_o_1_0_iv_0_0_0_5, FOC_TRANSFORMS_0_id_o_0 => 
        FOC_TRANSFORMS_0_id_o_0, FOC_TRANSFORMS_0_id_o_5 => 
        FOC_TRANSFORMS_0_id_o_5, FOC_TRANSFORMS_0_id_o_8 => 
        FOC_TRANSFORMS_0_id_o_8, FOC_TRANSFORMS_0_id_o_9 => 
        FOC_TRANSFORMS_0_id_o_9, FOC_TRANSFORMS_0_id_o_7 => 
        FOC_TRANSFORMS_0_id_o_7, FOC_TRANSFORMS_0_id_o_10 => 
        FOC_TRANSFORMS_0_id_o_10, FOC_TRANSFORMS_0_id_o_12 => 
        FOC_TRANSFORMS_0_id_o_12, FOC_TRANSFORMS_0_id_o_15 => 
        FOC_TRANSFORMS_0_id_o_15, prdata_o_1_0_iv_0_3_0 => 
        prdata_o_1_0_iv_0_3_0, prdata_o_1_0_iv_0_3_3 => 
        prdata_o_1_0_iv_0_3_3, 
        adc_measurements_0_adc_result_ch1_o_0 => 
        adc_measurements_0_adc_result_ch1_o_0, 
        adc_measurements_0_adc_result_ch1_o_5 => 
        adc_measurements_0_adc_result_ch1_o_5, 
        adc_measurements_0_adc_result_ch1_o_8 => 
        adc_measurements_0_adc_result_ch1_o_8, 
        adc_measurements_0_adc_result_ch1_o_10 => 
        adc_measurements_0_adc_result_ch1_o_10, 
        adc_measurements_0_adc_result_ch1_o_1 => 
        adc_measurements_0_adc_result_ch1_o_1, 
        adc_measurements_0_adc_result_ch1_o_9 => 
        adc_measurements_0_adc_result_ch1_o_9, 
        adc_measurements_0_adc_result_ch1_o_7 => 
        adc_measurements_0_adc_result_ch1_o_7, 
        adc_interface_0_result_ch0_o_6 => 
        adc_interface_0_result_ch0_o_6, 
        adc_interface_0_result_ch0_o_11 => 
        adc_interface_0_result_ch0_o_11, 
        adc_interface_0_result_ch0_o_7 => 
        adc_interface_0_result_ch0_o_7, 
        adc_interface_0_result_ch0_o_0 => 
        adc_interface_0_result_ch0_o_0, 
        adc_interface_0_result_ch0_o_5 => 
        adc_interface_0_result_ch0_o_5, 
        adc_interface_0_result_ch0_o_8 => 
        adc_interface_0_result_ch0_o_8, 
        adc_interface_0_result_ch0_o_9 => 
        adc_interface_0_result_ch0_o_9, ADC_SCALING_0_ia_adc_o_0
         => ADC_SCALING_0_ia_adc_o_0, ADC_SCALING_0_ia_adc_o_7
         => ADC_SCALING_0_ia_adc_o_7, ADC_SCALING_0_ia_adc_o_10
         => ADC_SCALING_0_ia_adc_o_10, ADC_SCALING_0_ia_adc_o_2
         => ADC_SCALING_0_ia_adc_o_2, ADC_SCALING_0_ia_adc_o_5
         => ADC_SCALING_0_ia_adc_o_5, ADC_SCALING_0_ia_adc_o_8
         => ADC_SCALING_0_ia_adc_o_8, ADC_SCALING_0_ia_adc_o_9
         => ADC_SCALING_0_ia_adc_o_9, ADC_SCALING_0_ia_adc_o_12
         => ADC_SCALING_0_ia_adc_o_12, ADC_SCALING_0_ia_adc_o_15
         => ADC_SCALING_0_ia_adc_o_15, ADC_SCALING_0_ia_adc_o_4
         => ADC_SCALING_0_ia_adc_o_4, ADC_SCALING_0_ia_adc_o_1
         => ADC_SCALING_0_ia_adc_o_1, ADC_SCALING_0_ia_adc_o_6
         => ADC_SCALING_0_ia_adc_o_6, ADC_SCALING_0_ia_adc_o_11
         => ADC_SCALING_0_ia_adc_o_11, 
        prdata_o_1_0_iv_0_1_o2_0(17) => 
        prdata_o_1_0_iv_0_1_o2_0(17), prdata_o_1_iv_0_0_11(3) => 
        prdata_o_1_iv_0_0_11(3), prdata_o_1_2_0_0_5(3) => 
        prdata_o_1_2_0_0_5(3), ADC_SCALING_0_ib_adc_o_10 => 
        ADC_SCALING_0_ib_adc_o_10, ADC_SCALING_0_ib_adc_o_5 => 
        ADC_SCALING_0_ib_adc_o_5, ADC_SCALING_0_ib_adc_o_4 => 
        ADC_SCALING_0_ib_adc_o_4, ADC_SCALING_0_ib_adc_o_7 => 
        ADC_SCALING_0_ib_adc_o_7, ADC_SCALING_0_ib_adc_o_8 => 
        ADC_SCALING_0_ib_adc_o_8, ADC_SCALING_0_ib_adc_o_11 => 
        ADC_SCALING_0_ib_adc_o_11, ADC_SCALING_0_ib_adc_o_14 => 
        ADC_SCALING_0_ib_adc_o_14, ADC_SCALING_0_ib_adc_o_3 => 
        ADC_SCALING_0_ib_adc_o_3, ADC_SCALING_0_ib_adc_o_0 => 
        ADC_SCALING_0_ib_adc_o_0, prdata_o_1_iv_0_0_0_3_tz(1) => 
        prdata_o_1_iv_0_0_0_3_tz(1), prdata_o_1_0_1(16) => 
        prdata_o_1_0_1(16), prdata_o_1_0_2(16) => 
        prdata_o_1_0_2(16), prdata_o_1_0_0(16) => 
        prdata_o_1_0_0(16), prdata_o_1_3_0_0_2(11) => 
        prdata_o_1_3_0_0_2(11), prdata_o_1_3_0_0_3(11) => 
        prdata_o_1_3_0_0_3(11), prdata_o_1_3_0_0_0(11) => 
        prdata_o_1_3_0_0_0(11), prdata_o_1_8_2(6) => 
        prdata_o_1_8_2(6), prdata_o_1_8_3(6) => prdata_o_1_8_3(6), 
        prdata_o_1_8_0(6) => prdata_o_1_8_0(6), 
        prdata_o_1_iv_0_0_12_4_3(3) => 
        prdata_o_1_iv_0_0_12_4_3(3), prdata_o_1_iv_0_0_12_4_2(3)
         => prdata_o_1_iv_0_0_12_4_2(3), prdata_o_1_0_iv_0_5_1
         => prdata_o_1_0_iv_0_5_1, prdata_o_1_0_iv_0_5_4 => 
        prdata_o_1_0_iv_0_5_4, prdata_o_1_0_iv_0_5_2 => 
        prdata_o_1_0_iv_0_5_2, prdata_o_1_0_iv_0_5_7 => 
        prdata_o_1_0_iv_0_5_7, prdata_o_1_0_iv_0_5_5 => 
        prdata_o_1_0_iv_0_5_5, prdata_o_1_0_iv_0_5_0 => 
        prdata_o_1_0_iv_0_5_0, prdata_o_1_0_iv_0_5_12 => 
        prdata_o_1_0_iv_0_5_12, prdata_o_1_0_iv_0_6(16) => 
        prdata_o_1_0_iv_0_6(16), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        \MC_System_0_AMBA_SLAVE_0_PSELx\, N_1342 => N_1342, 
        N_2598 => N_2598, N_2644 => N_2644, N_1396 => N_1396, 
        N_2631 => N_2631, prdata_m2_e_1_1 => prdata_m2_e_1_1, 
        N_1360 => N_1360, N_1288 => N_1288, prdata_m1_0_a2_0 => 
        prdata_m1_0_a2_0, N_522 => N_522, N_527 => N_527, N_542
         => N_542, prdata_m4_e_0 => prdata_m4_e_0, 
        prdata_m1_0_a2_2_0 => prdata_m1_0_a2_2_0, N_509 => N_509, 
        N_529 => N_529, N_503 => N_503, prdata_m2_e_0 => 
        prdata_m2_e_0, N_508 => N_508, N_106 => N_106, N_2652 => 
        N_2652, N_768 => N_768, N_1345 => N_1345, N_2647 => 
        N_2647, N_2531 => N_2531, N_513 => N_513, N_502 => N_502, 
        N_534 => N_534, N_500 => N_500, N_514 => N_514, N_506 => 
        N_506, N_505 => N_505, N_518 => N_518, N_2574 => N_2574, 
        N_1346 => N_1346, N_531 => N_531, N_2640 => N_2640, N_738
         => N_738, MC_System_0_AMBA_SLAVE_1_PSELx => 
        \MC_System_0_AMBA_SLAVE_1_PSELx\, N_533 => N_533, N_507
         => N_507, prdata_m1_e_0_1 => prdata_m1_e_0_1, N_1398 => 
        N_1398, N_1378 => N_1378, N_2627 => N_2627, 
        prdata_m2_0_a2_0 => prdata_m2_0_a2_0, N_455 => N_455, 
        N_495 => N_495, N_892 => N_892, N_771 => N_771, N_773 => 
        N_773, N_750 => N_750, N_2639 => N_2639, N_775 => N_775, 
        N_763 => N_763, N_2645 => N_2645, N_1351 => N_1351, 
        N_1169 => N_1169, N_1279 => N_1279, N_793 => N_793, N_791
         => N_791, N_782 => N_782, N_893 => N_893, N_788 => N_788, 
        N_772 => N_772, N_749 => N_749, N_774 => N_774, N_762 => 
        N_762, N_1347 => N_1347, N_1165 => N_1165, N_1275 => 
        N_1275, N_792 => N_792, N_878 => N_878, N_859 => N_859, 
        N_880 => N_880, N_870 => N_870, prdata_m2_e_0_0 => 
        prdata_m2_e_0_0, prdata_m1_e_11_0 => prdata_m1_e_11_0, 
        N_414 => N_414, N_516 => N_516, N_397 => N_397, N_355 => 
        N_355, N_198 => N_198, m20_i_2_tz => m20_i_2_tz, 
        m20_i_a2_0_1 => m20_i_a2_0_1, m20_m2_0_a2_1 => 
        m20_m2_0_a2_1, N_349 => N_349, m20_i_a2_5_0 => 
        m20_i_a2_5_0, N_517 => N_517, N_128 => N_128, N_528 => 
        N_528, N_524 => N_524, N_454 => N_454, N_494 => N_494, 
        N_894 => N_894, N_1326 => N_1326, N_2646 => N_2646, N_770
         => N_770, N_777 => N_777, N_883 => N_883, N_1333 => 
        N_1333, N_790 => N_790, N_895 => N_895, N_769 => N_769, 
        N_776 => N_776, N_832 => N_832, N_1329 => N_1329, N_789
         => N_789, N_876 => N_876, N_882 => N_882, prdata_m3_i_0
         => prdata_m3_i_0, N_260 => N_260, N_766 => N_766, N_739
         => N_739, N_891 => N_891, N_767 => N_767, N_875 => N_875, 
        N_396 => N_396, N_405 => N_405, N_354 => N_354, N_363 => 
        N_363, prdata_N_7_2 => prdata_N_7_2, m20_i_10_1 => 
        m20_i_10_1, m20_i_10_0 => m20_i_10_0, N_215 => N_215, 
        N_377 => N_377, N_2495 => N_2495, N_2498 => N_2498, 
        m20_i_11_5 => m20_i_11_5, N_122 => N_122, N_317 => N_317, 
        N_318 => N_318, N_319 => N_319, N_320 => N_320, N_321 => 
        N_321, N_315 => N_315, PRDATA_N_3_mux_i_0 => 
        PRDATA_N_3_mux_i_0);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    GND_Z : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_sb_CCC_0_FCCC is

    port( MC_System_0_FIC_0_LOCK                             : out   std_logic;
          MC_System_0_FIC_0_CLK                              : out   std_logic;
          MC_System_0_FAB_CCC_GL1                            : out   std_logic;
          FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : in    std_logic
        );

end MC_System_sb_CCC_0_FCCC;

architecture DEF_ARCH of MC_System_sb_CCC_0_FCCC is 

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CCC

            generic (INIT:std_logic_vector(209 downto 0) := "00" & x"0000000000000000000000000000000000000000000000000000"; 
        VCOFREQUENCY:real := 0.0);

    port( Y0              : out   std_logic;
          Y1              : out   std_logic;
          Y2              : out   std_logic;
          Y3              : out   std_logic;
          PRDATA          : out   std_logic_vector(7 downto 0);
          LOCK            : out   std_logic;
          BUSY            : out   std_logic;
          CLK0            : in    std_logic := 'U';
          CLK1            : in    std_logic := 'U';
          CLK2            : in    std_logic := 'U';
          CLK3            : in    std_logic := 'U';
          NGMUX0_SEL      : in    std_logic := 'U';
          NGMUX1_SEL      : in    std_logic := 'U';
          NGMUX2_SEL      : in    std_logic := 'U';
          NGMUX3_SEL      : in    std_logic := 'U';
          NGMUX0_HOLD_N   : in    std_logic := 'U';
          NGMUX1_HOLD_N   : in    std_logic := 'U';
          NGMUX2_HOLD_N   : in    std_logic := 'U';
          NGMUX3_HOLD_N   : in    std_logic := 'U';
          NGMUX0_ARST_N   : in    std_logic := 'U';
          NGMUX1_ARST_N   : in    std_logic := 'U';
          NGMUX2_ARST_N   : in    std_logic := 'U';
          NGMUX3_ARST_N   : in    std_logic := 'U';
          PLL_BYPASS_N    : in    std_logic := 'U';
          PLL_ARST_N      : in    std_logic := 'U';
          PLL_POWERDOWN_N : in    std_logic := 'U';
          GPD0_ARST_N     : in    std_logic := 'U';
          GPD1_ARST_N     : in    std_logic := 'U';
          GPD2_ARST_N     : in    std_logic := 'U';
          GPD3_ARST_N     : in    std_logic := 'U';
          PRESET_N        : in    std_logic := 'U';
          PCLK            : in    std_logic := 'U';
          PSEL            : in    std_logic := 'U';
          PENABLE         : in    std_logic := 'U';
          PWRITE          : in    std_logic := 'U';
          PADDR           : in    std_logic_vector(7 downto 2) := (others => 'U');
          PWDATA          : in    std_logic_vector(7 downto 0) := (others => 'U');
          CLK0_PAD        : in    std_logic := 'U';
          CLK1_PAD        : in    std_logic := 'U';
          CLK2_PAD        : in    std_logic := 'U';
          CLK3_PAD        : in    std_logic := 'U';
          GL0             : out   std_logic;
          GL1             : out   std_logic;
          GL2             : out   std_logic;
          GL3             : out   std_logic;
          RCOSC_25_50MHZ  : in    std_logic := 'U';
          RCOSC_1MHZ      : in    std_logic := 'U';
          XTLOSC          : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal PRDATA : std_logic_vector(7 downto 0);
    signal LOCK, GL0_net, GL1_net, Y0, Y1, Y2, Y3, BUSY, \VCC\, 
        \GND\, GL2, GL3 : std_logic;

begin 


    GL1_INST : CLKINT
      port map(A => GL1_net, Y => MC_System_0_FAB_CCC_GL1);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    GL0_INST : CLKINT
      port map(A => GL0_net, Y => MC_System_0_FIC_0_CLK);
    
    CCC_INST : CCC

              generic map(INIT => "00" & x"000007FB8000044D64000318C6307C1F18C61EC0404040400301",
         VCOFREQUENCY => 800.000000)

      port map(Y0 => Y0, Y1 => Y1, Y2 => Y2, Y3 => Y3, PRDATA(7)
         => PRDATA(7), PRDATA(6) => PRDATA(6), PRDATA(5) => 
        PRDATA(5), PRDATA(4) => PRDATA(4), PRDATA(3) => PRDATA(3), 
        PRDATA(2) => PRDATA(2), PRDATA(1) => PRDATA(1), PRDATA(0)
         => PRDATA(0), LOCK => LOCK, BUSY => BUSY, CLK0 => \VCC\, 
        CLK1 => \VCC\, CLK2 => \VCC\, CLK3 => \VCC\, NGMUX0_SEL
         => \GND\, NGMUX1_SEL => \GND\, NGMUX2_SEL => \GND\, 
        NGMUX3_SEL => \GND\, NGMUX0_HOLD_N => \VCC\, 
        NGMUX1_HOLD_N => \VCC\, NGMUX2_HOLD_N => \VCC\, 
        NGMUX3_HOLD_N => \VCC\, NGMUX0_ARST_N => \VCC\, 
        NGMUX1_ARST_N => \VCC\, NGMUX2_ARST_N => \VCC\, 
        NGMUX3_ARST_N => \VCC\, PLL_BYPASS_N => \VCC\, PLL_ARST_N
         => \VCC\, PLL_POWERDOWN_N => \VCC\, GPD0_ARST_N => \VCC\, 
        GPD1_ARST_N => \VCC\, GPD2_ARST_N => \VCC\, GPD3_ARST_N
         => \VCC\, PRESET_N => \GND\, PCLK => \VCC\, PSEL => 
        \VCC\, PENABLE => \VCC\, PWRITE => \VCC\, PADDR(7) => 
        \VCC\, PADDR(6) => \VCC\, PADDR(5) => \VCC\, PADDR(4) => 
        \VCC\, PADDR(3) => \VCC\, PADDR(2) => \VCC\, PWDATA(7)
         => \VCC\, PWDATA(6) => \VCC\, PWDATA(5) => \VCC\, 
        PWDATA(4) => \VCC\, PWDATA(3) => \VCC\, PWDATA(2) => 
        \VCC\, PWDATA(1) => \VCC\, PWDATA(0) => \VCC\, CLK0_PAD
         => \GND\, CLK1_PAD => \GND\, CLK2_PAD => \GND\, CLK3_PAD
         => \GND\, GL0 => GL0_net, GL1 => GL1_net, GL2 => GL2, 
        GL3 => GL3, RCOSC_25_50MHZ => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        RCOSC_1MHZ => \GND\, XTLOSC => \GND\);
    
    GND_Z : GND
      port map(Y => \GND\);
    
    CCC_INST_RNI2QPF : CLKINT
      port map(A => LOCK, Y => MC_System_0_FIC_0_LOCK);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_sb_MSS is

    port( USB_ULPI_DATA                                     : inout std_logic_vector(7 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_1_PADDR                    : out   std_logic_vector(11 downto 0);
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : out   std_logic_vector(15 downto 12);
          MC_System_0_AMBA_SLAVE_1_PWDATA                   : out   std_logic_vector(23 downto 0);
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : in    std_logic;
          USB_ULPI_XCLK                                     : in    std_logic;
          USB_ULPI_STP                                      : out   std_logic;
          USB_ULPI_NXT                                      : in    std_logic;
          USB_ULPI_DIR                                      : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PENABLE                  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE                   : out   std_logic;
          GPIO_0_M2F_c                                      : out   std_logic;
          PRDATA_N_3_mux_i_0                                : in    std_logic;
          MC_System_0_FIC_0_LOCK                            : in    std_logic;
          MC_System_0_FIC_0_CLK                             : in    std_logic
        );

end MC_System_sb_MSS;

architecture DEF_ARCH of MC_System_sb_MSS is 

  component BIBUF
    generic (IOSTD:string := "");

    port( PAD : inout   std_logic;
          D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MSS_010

            generic (INIT:std_logic_vector(1437 downto 0) := "00" & x"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; 
        ACT_UBITS:std_logic_vector(55 downto 0) := x"FFFFFFFFFFFFFF"; 
        MEMORYFILE:string := ""; RTC_MAIN_XTL_FREQ:real := 0.0; 
        RTC_MAIN_XTL_MODE:string := "1"; DDR_CLK_FREQ:real := 0.0
        );

    port( CAN_RXBUS_MGPIO3A_H2F_A                 : out   std_logic;
          CAN_RXBUS_MGPIO3A_H2F_B                 : out   std_logic;
          CAN_TX_EBL_MGPIO4A_H2F_A                : out   std_logic;
          CAN_TX_EBL_MGPIO4A_H2F_B                : out   std_logic;
          CAN_TXBUS_MGPIO2A_H2F_A                 : out   std_logic;
          CAN_TXBUS_MGPIO2A_H2F_B                 : out   std_logic;
          CLK_CONFIG_APB                          : out   std_logic;
          COMMS_INT                               : out   std_logic;
          CONFIG_PRESET_N                         : out   std_logic;
          EDAC_ERROR                              : out   std_logic_vector(7 downto 0);
          F_FM0_RDATA                             : out   std_logic_vector(31 downto 0);
          F_FM0_READYOUT                          : out   std_logic;
          F_FM0_RESP                              : out   std_logic;
          F_HM0_ADDR                              : out   std_logic_vector(31 downto 0);
          F_HM0_ENABLE                            : out   std_logic;
          F_HM0_SEL                               : out   std_logic;
          F_HM0_SIZE                              : out   std_logic_vector(1 downto 0);
          F_HM0_TRANS1                            : out   std_logic;
          F_HM0_WDATA                             : out   std_logic_vector(31 downto 0);
          F_HM0_WRITE                             : out   std_logic;
          FAB_CHRGVBUS                            : out   std_logic;
          FAB_DISCHRGVBUS                         : out   std_logic;
          FAB_DMPULLDOWN                          : out   std_logic;
          FAB_DPPULLDOWN                          : out   std_logic;
          FAB_DRVVBUS                             : out   std_logic;
          FAB_IDPULLUP                            : out   std_logic;
          FAB_OPMODE                              : out   std_logic_vector(1 downto 0);
          FAB_SUSPENDM                            : out   std_logic;
          FAB_TERMSEL                             : out   std_logic;
          FAB_TXVALID                             : out   std_logic;
          FAB_VCONTROL                            : out   std_logic_vector(3 downto 0);
          FAB_VCONTROLLOADM                       : out   std_logic;
          FAB_XCVRSEL                             : out   std_logic_vector(1 downto 0);
          FAB_XDATAOUT                            : out   std_logic_vector(7 downto 0);
          FACC_GLMUX_SEL                          : out   std_logic;
          FIC32_0_MASTER                          : out   std_logic_vector(1 downto 0);
          FIC32_1_MASTER                          : out   std_logic_vector(1 downto 0);
          FPGA_RESET_N                            : out   std_logic;
          GTX_CLK                                 : out   std_logic;
          H2F_INTERRUPT                           : out   std_logic_vector(15 downto 0);
          H2F_NMI                                 : out   std_logic;
          H2FCALIB                                : out   std_logic;
          I2C0_SCL_MGPIO31B_H2F_A                 : out   std_logic;
          I2C0_SCL_MGPIO31B_H2F_B                 : out   std_logic;
          I2C0_SDA_MGPIO30B_H2F_A                 : out   std_logic;
          I2C0_SDA_MGPIO30B_H2F_B                 : out   std_logic;
          I2C1_SCL_MGPIO1A_H2F_A                  : out   std_logic;
          I2C1_SCL_MGPIO1A_H2F_B                  : out   std_logic;
          I2C1_SDA_MGPIO0A_H2F_A                  : out   std_logic;
          I2C1_SDA_MGPIO0A_H2F_B                  : out   std_logic;
          MDCF                                    : out   std_logic;
          MDOENF                                  : out   std_logic;
          MDOF                                    : out   std_logic;
          MMUART0_CTS_MGPIO19B_H2F_A              : out   std_logic;
          MMUART0_CTS_MGPIO19B_H2F_B              : out   std_logic;
          MMUART0_DCD_MGPIO22B_H2F_A              : out   std_logic;
          MMUART0_DCD_MGPIO22B_H2F_B              : out   std_logic;
          MMUART0_DSR_MGPIO20B_H2F_A              : out   std_logic;
          MMUART0_DSR_MGPIO20B_H2F_B              : out   std_logic;
          MMUART0_DTR_MGPIO18B_H2F_A              : out   std_logic;
          MMUART0_DTR_MGPIO18B_H2F_B              : out   std_logic;
          MMUART0_RI_MGPIO21B_H2F_A               : out   std_logic;
          MMUART0_RI_MGPIO21B_H2F_B               : out   std_logic;
          MMUART0_RTS_MGPIO17B_H2F_A              : out   std_logic;
          MMUART0_RTS_MGPIO17B_H2F_B              : out   std_logic;
          MMUART0_RXD_MGPIO28B_H2F_A              : out   std_logic;
          MMUART0_RXD_MGPIO28B_H2F_B              : out   std_logic;
          MMUART0_SCK_MGPIO29B_H2F_A              : out   std_logic;
          MMUART0_SCK_MGPIO29B_H2F_B              : out   std_logic;
          MMUART0_TXD_MGPIO27B_H2F_A              : out   std_logic;
          MMUART0_TXD_MGPIO27B_H2F_B              : out   std_logic;
          MMUART1_DTR_MGPIO12B_H2F_A              : out   std_logic;
          MMUART1_RTS_MGPIO11B_H2F_A              : out   std_logic;
          MMUART1_RTS_MGPIO11B_H2F_B              : out   std_logic;
          MMUART1_RXD_MGPIO26B_H2F_A              : out   std_logic;
          MMUART1_RXD_MGPIO26B_H2F_B              : out   std_logic;
          MMUART1_SCK_MGPIO25B_H2F_A              : out   std_logic;
          MMUART1_SCK_MGPIO25B_H2F_B              : out   std_logic;
          MMUART1_TXD_MGPIO24B_H2F_A              : out   std_logic;
          MMUART1_TXD_MGPIO24B_H2F_B              : out   std_logic;
          MPLL_LOCK                               : out   std_logic;
          PER2_FABRIC_PADDR                       : out   std_logic_vector(15 downto 2);
          PER2_FABRIC_PENABLE                     : out   std_logic;
          PER2_FABRIC_PSEL                        : out   std_logic;
          PER2_FABRIC_PWDATA                      : out   std_logic_vector(31 downto 0);
          PER2_FABRIC_PWRITE                      : out   std_logic;
          RTC_MATCH                               : out   std_logic;
          SLEEPDEEP                               : out   std_logic;
          SLEEPHOLDACK                            : out   std_logic;
          SLEEPING                                : out   std_logic;
          SMBALERT_NO0                            : out   std_logic;
          SMBALERT_NO1                            : out   std_logic;
          SMBSUS_NO0                              : out   std_logic;
          SMBSUS_NO1                              : out   std_logic;
          SPI0_CLK_OUT                            : out   std_logic;
          SPI0_SDI_MGPIO5A_H2F_A                  : out   std_logic;
          SPI0_SDI_MGPIO5A_H2F_B                  : out   std_logic;
          SPI0_SDO_MGPIO6A_H2F_A                  : out   std_logic;
          SPI0_SDO_MGPIO6A_H2F_B                  : out   std_logic;
          SPI0_SS0_MGPIO7A_H2F_A                  : out   std_logic;
          SPI0_SS0_MGPIO7A_H2F_B                  : out   std_logic;
          SPI0_SS1_MGPIO8A_H2F_A                  : out   std_logic;
          SPI0_SS1_MGPIO8A_H2F_B                  : out   std_logic;
          SPI0_SS2_MGPIO9A_H2F_A                  : out   std_logic;
          SPI0_SS2_MGPIO9A_H2F_B                  : out   std_logic;
          SPI0_SS3_MGPIO10A_H2F_A                 : out   std_logic;
          SPI0_SS3_MGPIO10A_H2F_B                 : out   std_logic;
          SPI0_SS4_MGPIO19A_H2F_A                 : out   std_logic;
          SPI0_SS5_MGPIO20A_H2F_A                 : out   std_logic;
          SPI0_SS6_MGPIO21A_H2F_A                 : out   std_logic;
          SPI0_SS7_MGPIO22A_H2F_A                 : out   std_logic;
          SPI1_CLK_OUT                            : out   std_logic;
          SPI1_SDI_MGPIO11A_H2F_A                 : out   std_logic;
          SPI1_SDI_MGPIO11A_H2F_B                 : out   std_logic;
          SPI1_SDO_MGPIO12A_H2F_A                 : out   std_logic;
          SPI1_SDO_MGPIO12A_H2F_B                 : out   std_logic;
          SPI1_SS0_MGPIO13A_H2F_A                 : out   std_logic;
          SPI1_SS0_MGPIO13A_H2F_B                 : out   std_logic;
          SPI1_SS1_MGPIO14A_H2F_A                 : out   std_logic;
          SPI1_SS1_MGPIO14A_H2F_B                 : out   std_logic;
          SPI1_SS2_MGPIO15A_H2F_A                 : out   std_logic;
          SPI1_SS2_MGPIO15A_H2F_B                 : out   std_logic;
          SPI1_SS3_MGPIO16A_H2F_A                 : out   std_logic;
          SPI1_SS3_MGPIO16A_H2F_B                 : out   std_logic;
          SPI1_SS4_MGPIO17A_H2F_A                 : out   std_logic;
          SPI1_SS5_MGPIO18A_H2F_A                 : out   std_logic;
          SPI1_SS6_MGPIO23A_H2F_A                 : out   std_logic;
          SPI1_SS7_MGPIO24A_H2F_A                 : out   std_logic;
          TCGF                                    : out   std_logic_vector(9 downto 0);
          TRACECLK                                : out   std_logic;
          TRACEDATA                               : out   std_logic_vector(3 downto 0);
          TX_CLK                                  : out   std_logic;
          TX_ENF                                  : out   std_logic;
          TX_ERRF                                 : out   std_logic;
          TXCTL_EN_RIF                            : out   std_logic;
          TXD_RIF                                 : out   std_logic_vector(3 downto 0);
          TXDF                                    : out   std_logic_vector(7 downto 0);
          TXEV                                    : out   std_logic;
          WDOGTIMEOUT                             : out   std_logic;
          F_ARREADY_HREADYOUT1                    : out   std_logic;
          F_AWREADY_HREADYOUT0                    : out   std_logic;
          F_BID                                   : out   std_logic_vector(3 downto 0);
          F_BRESP_HRESP0                          : out   std_logic_vector(1 downto 0);
          F_BVALID                                : out   std_logic;
          F_RDATA_HRDATA01                        : out   std_logic_vector(63 downto 0);
          F_RID                                   : out   std_logic_vector(3 downto 0);
          F_RLAST                                 : out   std_logic;
          F_RRESP_HRESP1                          : out   std_logic_vector(1 downto 0);
          F_RVALID                                : out   std_logic;
          F_WREADY                                : out   std_logic;
          MDDR_FABRIC_PRDATA                      : out   std_logic_vector(15 downto 0);
          MDDR_FABRIC_PREADY                      : out   std_logic;
          MDDR_FABRIC_PSLVERR                     : out   std_logic;
          CAN_RXBUS_F2H_SCP                       : in    std_logic := 'U';
          CAN_TX_EBL_F2H_SCP                      : in    std_logic := 'U';
          CAN_TXBUS_F2H_SCP                       : in    std_logic := 'U';
          COLF                                    : in    std_logic := 'U';
          CRSF                                    : in    std_logic := 'U';
          F2_DMAREADY                             : in    std_logic_vector(1 downto 0) := (others => 'U');
          F2H_INTERRUPT                           : in    std_logic_vector(15 downto 0) := (others => 'U');
          F2HCALIB                                : in    std_logic := 'U';
          F_DMAREADY                              : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_FM0_ADDR                              : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_FM0_ENABLE                            : in    std_logic := 'U';
          F_FM0_MASTLOCK                          : in    std_logic := 'U';
          F_FM0_READY                             : in    std_logic := 'U';
          F_FM0_SEL                               : in    std_logic := 'U';
          F_FM0_SIZE                              : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_FM0_TRANS1                            : in    std_logic := 'U';
          F_FM0_WDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_FM0_WRITE                             : in    std_logic := 'U';
          F_HM0_RDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_HM0_READY                             : in    std_logic := 'U';
          F_HM0_RESP                              : in    std_logic := 'U';
          FAB_AVALID                              : in    std_logic := 'U';
          FAB_HOSTDISCON                          : in    std_logic := 'U';
          FAB_IDDIG                               : in    std_logic := 'U';
          FAB_LINESTATE                           : in    std_logic_vector(1 downto 0) := (others => 'U');
          FAB_M3_RESET_N                          : in    std_logic := 'U';
          FAB_PLL_LOCK                            : in    std_logic := 'U';
          FAB_RXACTIVE                            : in    std_logic := 'U';
          FAB_RXERROR                             : in    std_logic := 'U';
          FAB_RXVALID                             : in    std_logic := 'U';
          FAB_RXVALIDH                            : in    std_logic := 'U';
          FAB_SESSEND                             : in    std_logic := 'U';
          FAB_TXREADY                             : in    std_logic := 'U';
          FAB_VBUSVALID                           : in    std_logic := 'U';
          FAB_VSTATUS                             : in    std_logic_vector(7 downto 0) := (others => 'U');
          FAB_XDATAIN                             : in    std_logic_vector(7 downto 0) := (others => 'U');
          GTX_CLKPF                               : in    std_logic := 'U';
          I2C0_BCLK                               : in    std_logic := 'U';
          I2C0_SCL_F2H_SCP                        : in    std_logic := 'U';
          I2C0_SDA_F2H_SCP                        : in    std_logic := 'U';
          I2C1_BCLK                               : in    std_logic := 'U';
          I2C1_SCL_F2H_SCP                        : in    std_logic := 'U';
          I2C1_SDA_F2H_SCP                        : in    std_logic := 'U';
          MDIF                                    : in    std_logic := 'U';
          MGPIO0A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO10A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO11A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO11B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO12A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO13A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO14A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO15A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO16A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO17B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO18B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO19B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO1A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO20B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO21B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO22B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO24B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO25B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO26B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO27B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO28B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO29B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO2A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO30B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO31B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO3A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO4A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO5A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO6A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO7A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO8A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO9A_F2H_GPIN                        : in    std_logic := 'U';
          MMUART0_CTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DCD_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DSR_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DTR_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_RI_F2H_SCP                      : in    std_logic := 'U';
          MMUART0_RTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_RXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_SCK_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_TXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_CTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_DCD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_DSR_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_RI_F2H_SCP                      : in    std_logic := 'U';
          MMUART1_RTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_RXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_SCK_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_TXD_F2H_SCP                     : in    std_logic := 'U';
          PER2_FABRIC_PRDATA                      : in    std_logic_vector(31 downto 0) := (others => 'U');
          PER2_FABRIC_PREADY                      : in    std_logic := 'U';
          PER2_FABRIC_PSLVERR                     : in    std_logic := 'U';
          RCGF                                    : in    std_logic_vector(9 downto 0) := (others => 'U');
          RX_CLKPF                                : in    std_logic := 'U';
          RX_DVF                                  : in    std_logic := 'U';
          RX_ERRF                                 : in    std_logic := 'U';
          RX_EV                                   : in    std_logic := 'U';
          RXDF                                    : in    std_logic_vector(7 downto 0) := (others => 'U');
          SLEEPHOLDREQ                            : in    std_logic := 'U';
          SMBALERT_NI0                            : in    std_logic := 'U';
          SMBALERT_NI1                            : in    std_logic := 'U';
          SMBSUS_NI0                              : in    std_logic := 'U';
          SMBSUS_NI1                              : in    std_logic := 'U';
          SPI0_CLK_IN                             : in    std_logic := 'U';
          SPI0_SDI_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SDO_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS0_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS1_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS2_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS3_F2H_SCP                        : in    std_logic := 'U';
          SPI1_CLK_IN                             : in    std_logic := 'U';
          SPI1_SDI_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SDO_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS0_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS1_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS2_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS3_F2H_SCP                        : in    std_logic := 'U';
          TX_CLKPF                                : in    std_logic := 'U';
          USER_MSS_GPIO_RESET_N                   : in    std_logic := 'U';
          USER_MSS_RESET_N                        : in    std_logic := 'U';
          XCLK_FAB                                : in    std_logic := 'U';
          CLK_BASE                                : in    std_logic := 'U';
          CLK_MDDR_APB                            : in    std_logic := 'U';
          F_ARADDR_HADDR1                         : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_ARBURST_HTRANS1                       : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARID_HSEL1                            : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_ARLEN_HBURST1                         : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_ARLOCK_HMASTLOCK1                     : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARSIZE_HSIZE1                         : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARVALID_HWRITE1                       : in    std_logic := 'U';
          F_AWADDR_HADDR0                         : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_AWBURST_HTRANS0                       : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWID_HSEL0                            : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_AWLEN_HBURST0                         : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_AWLOCK_HMASTLOCK0                     : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWSIZE_HSIZE0                         : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWVALID_HWRITE0                       : in    std_logic := 'U';
          F_BREADY                                : in    std_logic := 'U';
          F_RMW_AXI                               : in    std_logic := 'U';
          F_RREADY                                : in    std_logic := 'U';
          F_WDATA_HWDATA01                        : in    std_logic_vector(63 downto 0) := (others => 'U');
          F_WID_HREADY01                          : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_WLAST                                 : in    std_logic := 'U';
          F_WSTRB                                 : in    std_logic_vector(7 downto 0) := (others => 'U');
          F_WVALID                                : in    std_logic := 'U';
          FPGA_MDDR_ARESET_N                      : in    std_logic := 'U';
          MDDR_FABRIC_PADDR                       : in    std_logic_vector(10 downto 2) := (others => 'U');
          MDDR_FABRIC_PENABLE                     : in    std_logic := 'U';
          MDDR_FABRIC_PSEL                        : in    std_logic := 'U';
          MDDR_FABRIC_PWDATA                      : in    std_logic_vector(15 downto 0) := (others => 'U');
          MDDR_FABRIC_PWRITE                      : in    std_logic := 'U';
          PRESET_N                                : in    std_logic := 'U';
          CAN_RXBUS_USBA_DATA1_MGPIO3A_IN         : in    std_logic := 'U';
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN        : in    std_logic := 'U';
          CAN_TXBUS_USBA_DATA0_MGPIO2A_IN         : in    std_logic := 'U';
          DM_IN                                   : in    std_logic_vector(2 downto 0) := (others => 'U');
          DRAM_DQ_IN                              : in    std_logic_vector(17 downto 0) := (others => 'U');
          DRAM_DQS_IN                             : in    std_logic_vector(2 downto 0) := (others => 'U');
          DRAM_FIFO_WE_IN                         : in    std_logic_vector(1 downto 0) := (others => 'U');
          I2C0_SCL_USBC_DATA1_MGPIO31B_IN         : in    std_logic := 'U';
          I2C0_SDA_USBC_DATA0_MGPIO30B_IN         : in    std_logic := 'U';
          I2C1_SCL_USBA_DATA4_MGPIO1A_IN          : in    std_logic := 'U';
          I2C1_SDA_USBA_DATA3_MGPIO0A_IN          : in    std_logic := 'U';
          MMUART0_CTS_USBC_DATA7_MGPIO19B_IN      : in    std_logic := 'U';
          MMUART0_DCD_MGPIO22B_IN                 : in    std_logic := 'U';
          MMUART0_DSR_MGPIO20B_IN                 : in    std_logic := 'U';
          MMUART0_DTR_USBC_DATA6_MGPIO18B_IN      : in    std_logic := 'U';
          MMUART0_RI_MGPIO21B_IN                  : in    std_logic := 'U';
          MMUART0_RTS_USBC_DATA5_MGPIO17B_IN      : in    std_logic := 'U';
          MMUART0_RXD_USBC_STP_MGPIO28B_IN        : in    std_logic := 'U';
          MMUART0_SCK_USBC_NXT_MGPIO29B_IN        : in    std_logic := 'U';
          MMUART0_TXD_USBC_DIR_MGPIO27B_IN        : in    std_logic := 'U';
          MMUART1_RXD_USBC_DATA3_MGPIO26B_IN      : in    std_logic := 'U';
          MMUART1_SCK_USBC_DATA4_MGPIO25B_IN      : in    std_logic := 'U';
          MMUART1_TXD_USBC_DATA2_MGPIO24B_IN      : in    std_logic := 'U';
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN     : in    std_logic := 'U';
          RGMII_MDC_RMII_MDC_IN                   : in    std_logic := 'U';
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN      : in    std_logic := 'U';
          RGMII_RX_CLK_IN                         : in    std_logic := 'U';
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN  : in    std_logic := 'U';
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN      : in    std_logic := 'U';
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN      : in    std_logic := 'U';
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN     : in    std_logic := 'U';
          RGMII_RXD3_USBB_DATA4_IN                : in    std_logic := 'U';
          RGMII_TX_CLK_IN                         : in    std_logic := 'U';
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN     : in    std_logic := 'U';
          RGMII_TXD0_RMII_TXD0_USBB_DIR_IN        : in    std_logic := 'U';
          RGMII_TXD1_RMII_TXD1_USBB_STP_IN        : in    std_logic := 'U';
          RGMII_TXD2_USBB_DATA5_IN                : in    std_logic := 'U';
          RGMII_TXD3_USBB_DATA6_IN                : in    std_logic := 'U';
          SPI0_SCK_USBA_XCLK_IN                   : in    std_logic := 'U';
          SPI0_SDI_USBA_DIR_MGPIO5A_IN            : in    std_logic := 'U';
          SPI0_SDO_USBA_STP_MGPIO6A_IN            : in    std_logic := 'U';
          SPI0_SS0_USBA_NXT_MGPIO7A_IN            : in    std_logic := 'U';
          SPI0_SS1_USBA_DATA5_MGPIO8A_IN          : in    std_logic := 'U';
          SPI0_SS2_USBA_DATA6_MGPIO9A_IN          : in    std_logic := 'U';
          SPI0_SS3_USBA_DATA7_MGPIO10A_IN         : in    std_logic := 'U';
          SPI1_SCK_IN                             : in    std_logic := 'U';
          SPI1_SDI_MGPIO11A_IN                    : in    std_logic := 'U';
          SPI1_SDO_MGPIO12A_IN                    : in    std_logic := 'U';
          SPI1_SS0_MGPIO13A_IN                    : in    std_logic := 'U';
          SPI1_SS1_MGPIO14A_IN                    : in    std_logic := 'U';
          SPI1_SS2_MGPIO15A_IN                    : in    std_logic := 'U';
          SPI1_SS3_MGPIO16A_IN                    : in    std_logic := 'U';
          SPI1_SS4_MGPIO17A_IN                    : in    std_logic := 'U';
          SPI1_SS5_MGPIO18A_IN                    : in    std_logic := 'U';
          SPI1_SS6_MGPIO23A_IN                    : in    std_logic := 'U';
          SPI1_SS7_MGPIO24A_IN                    : in    std_logic := 'U';
          USBC_XCLK_IN                            : in    std_logic := 'U';
          CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT        : out   std_logic;
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT       : out   std_logic;
          CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT        : out   std_logic;
          DRAM_ADDR                               : out   std_logic_vector(15 downto 0);
          DRAM_BA                                 : out   std_logic_vector(2 downto 0);
          DRAM_CASN                               : out   std_logic;
          DRAM_CKE                                : out   std_logic;
          DRAM_CLK                                : out   std_logic;
          DRAM_CSN                                : out   std_logic;
          DRAM_DM_RDQS_OUT                        : out   std_logic_vector(2 downto 0);
          DRAM_DQ_OUT                             : out   std_logic_vector(17 downto 0);
          DRAM_DQS_OUT                            : out   std_logic_vector(2 downto 0);
          DRAM_FIFO_WE_OUT                        : out   std_logic_vector(1 downto 0);
          DRAM_ODT                                : out   std_logic;
          DRAM_RASN                               : out   std_logic;
          DRAM_RSTN                               : out   std_logic;
          DRAM_WEN                                : out   std_logic;
          I2C0_SCL_USBC_DATA1_MGPIO31B_OUT        : out   std_logic;
          I2C0_SDA_USBC_DATA0_MGPIO30B_OUT        : out   std_logic;
          I2C1_SCL_USBA_DATA4_MGPIO1A_OUT         : out   std_logic;
          I2C1_SDA_USBA_DATA3_MGPIO0A_OUT         : out   std_logic;
          MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT     : out   std_logic;
          MMUART0_DCD_MGPIO22B_OUT                : out   std_logic;
          MMUART0_DSR_MGPIO20B_OUT                : out   std_logic;
          MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT     : out   std_logic;
          MMUART0_RI_MGPIO21B_OUT                 : out   std_logic;
          MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT     : out   std_logic;
          MMUART0_RXD_USBC_STP_MGPIO28B_OUT       : out   std_logic;
          MMUART0_SCK_USBC_NXT_MGPIO29B_OUT       : out   std_logic;
          MMUART0_TXD_USBC_DIR_MGPIO27B_OUT       : out   std_logic;
          MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT     : out   std_logic;
          MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT     : out   std_logic;
          MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT     : out   std_logic;
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT    : out   std_logic;
          RGMII_MDC_RMII_MDC_OUT                  : out   std_logic;
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT     : out   std_logic;
          RGMII_RX_CLK_OUT                        : out   std_logic;
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT : out   std_logic;
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT     : out   std_logic;
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT     : out   std_logic;
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT    : out   std_logic;
          RGMII_RXD3_USBB_DATA4_OUT               : out   std_logic;
          RGMII_TX_CLK_OUT                        : out   std_logic;
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT    : out   std_logic;
          RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT       : out   std_logic;
          RGMII_TXD1_RMII_TXD1_USBB_STP_OUT       : out   std_logic;
          RGMII_TXD2_USBB_DATA5_OUT               : out   std_logic;
          RGMII_TXD3_USBB_DATA6_OUT               : out   std_logic;
          SPI0_SCK_USBA_XCLK_OUT                  : out   std_logic;
          SPI0_SDI_USBA_DIR_MGPIO5A_OUT           : out   std_logic;
          SPI0_SDO_USBA_STP_MGPIO6A_OUT           : out   std_logic;
          SPI0_SS0_USBA_NXT_MGPIO7A_OUT           : out   std_logic;
          SPI0_SS1_USBA_DATA5_MGPIO8A_OUT         : out   std_logic;
          SPI0_SS2_USBA_DATA6_MGPIO9A_OUT         : out   std_logic;
          SPI0_SS3_USBA_DATA7_MGPIO10A_OUT        : out   std_logic;
          SPI1_SCK_OUT                            : out   std_logic;
          SPI1_SDI_MGPIO11A_OUT                   : out   std_logic;
          SPI1_SDO_MGPIO12A_OUT                   : out   std_logic;
          SPI1_SS0_MGPIO13A_OUT                   : out   std_logic;
          SPI1_SS1_MGPIO14A_OUT                   : out   std_logic;
          SPI1_SS2_MGPIO15A_OUT                   : out   std_logic;
          SPI1_SS3_MGPIO16A_OUT                   : out   std_logic;
          SPI1_SS4_MGPIO17A_OUT                   : out   std_logic;
          SPI1_SS5_MGPIO18A_OUT                   : out   std_logic;
          SPI1_SS6_MGPIO23A_OUT                   : out   std_logic;
          SPI1_SS7_MGPIO24A_OUT                   : out   std_logic;
          USBC_XCLK_OUT                           : out   std_logic;
          CAN_RXBUS_USBA_DATA1_MGPIO3A_OE         : out   std_logic;
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE        : out   std_logic;
          CAN_TXBUS_USBA_DATA0_MGPIO2A_OE         : out   std_logic;
          DM_OE                                   : out   std_logic_vector(2 downto 0);
          DRAM_DQ_OE                              : out   std_logic_vector(17 downto 0);
          DRAM_DQS_OE                             : out   std_logic_vector(2 downto 0);
          I2C0_SCL_USBC_DATA1_MGPIO31B_OE         : out   std_logic;
          I2C0_SDA_USBC_DATA0_MGPIO30B_OE         : out   std_logic;
          I2C1_SCL_USBA_DATA4_MGPIO1A_OE          : out   std_logic;
          I2C1_SDA_USBA_DATA3_MGPIO0A_OE          : out   std_logic;
          MMUART0_CTS_USBC_DATA7_MGPIO19B_OE      : out   std_logic;
          MMUART0_DCD_MGPIO22B_OE                 : out   std_logic;
          MMUART0_DSR_MGPIO20B_OE                 : out   std_logic;
          MMUART0_DTR_USBC_DATA6_MGPIO18B_OE      : out   std_logic;
          MMUART0_RI_MGPIO21B_OE                  : out   std_logic;
          MMUART0_RTS_USBC_DATA5_MGPIO17B_OE      : out   std_logic;
          MMUART0_RXD_USBC_STP_MGPIO28B_OE        : out   std_logic;
          MMUART0_SCK_USBC_NXT_MGPIO29B_OE        : out   std_logic;
          MMUART0_TXD_USBC_DIR_MGPIO27B_OE        : out   std_logic;
          MMUART1_RXD_USBC_DATA3_MGPIO26B_OE      : out   std_logic;
          MMUART1_SCK_USBC_DATA4_MGPIO25B_OE      : out   std_logic;
          MMUART1_TXD_USBC_DATA2_MGPIO24B_OE      : out   std_logic;
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE     : out   std_logic;
          RGMII_MDC_RMII_MDC_OE                   : out   std_logic;
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE      : out   std_logic;
          RGMII_RX_CLK_OE                         : out   std_logic;
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE  : out   std_logic;
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE      : out   std_logic;
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE      : out   std_logic;
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE     : out   std_logic;
          RGMII_RXD3_USBB_DATA4_OE                : out   std_logic;
          RGMII_TX_CLK_OE                         : out   std_logic;
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE     : out   std_logic;
          RGMII_TXD0_RMII_TXD0_USBB_DIR_OE        : out   std_logic;
          RGMII_TXD1_RMII_TXD1_USBB_STP_OE        : out   std_logic;
          RGMII_TXD2_USBB_DATA5_OE                : out   std_logic;
          RGMII_TXD3_USBB_DATA6_OE                : out   std_logic;
          SPI0_SCK_USBA_XCLK_OE                   : out   std_logic;
          SPI0_SDI_USBA_DIR_MGPIO5A_OE            : out   std_logic;
          SPI0_SDO_USBA_STP_MGPIO6A_OE            : out   std_logic;
          SPI0_SS0_USBA_NXT_MGPIO7A_OE            : out   std_logic;
          SPI0_SS1_USBA_DATA5_MGPIO8A_OE          : out   std_logic;
          SPI0_SS2_USBA_DATA6_MGPIO9A_OE          : out   std_logic;
          SPI0_SS3_USBA_DATA7_MGPIO10A_OE         : out   std_logic;
          SPI1_SCK_OE                             : out   std_logic;
          SPI1_SDI_MGPIO11A_OE                    : out   std_logic;
          SPI1_SDO_MGPIO12A_OE                    : out   std_logic;
          SPI1_SS0_MGPIO13A_OE                    : out   std_logic;
          SPI1_SS1_MGPIO14A_OE                    : out   std_logic;
          SPI1_SS2_MGPIO15A_OE                    : out   std_logic;
          SPI1_SS3_MGPIO16A_OE                    : out   std_logic;
          SPI1_SS4_MGPIO17A_OE                    : out   std_logic;
          SPI1_SS5_MGPIO18A_OE                    : out   std_logic;
          SPI1_SS6_MGPIO23A_OE                    : out   std_logic;
          SPI1_SS7_MGPIO24A_OE                    : out   std_logic;
          USBC_XCLK_OE                            : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component TRIBUFF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

    signal EDAC_ERROR : std_logic_vector(7 downto 0);
    signal F_FM0_RDATA : std_logic_vector(31 downto 0);
    signal FIC_0_APB_M_PADDR : std_logic_vector(31 downto 16);
    signal F_HM0_SIZE : std_logic_vector(1 downto 0);
    signal FIC_0_APB_M_PWDATA : std_logic_vector(31 downto 24);
    signal FAB_OPMODE : std_logic_vector(1 downto 0);
    signal FAB_VCONTROL : std_logic_vector(3 downto 0);
    signal FAB_XCVRSEL : std_logic_vector(1 downto 0);
    signal FAB_XDATAOUT : std_logic_vector(7 downto 0);
    signal FIC32_0_MASTER : std_logic_vector(1 downto 0);
    signal FIC32_1_MASTER : std_logic_vector(1 downto 0);
    signal H2F_INTERRUPT : std_logic_vector(15 downto 0);
    signal FIC_2_APB_M_PADDR : std_logic_vector(15 downto 2);
    signal FIC_2_APB_M_PWDATA : std_logic_vector(31 downto 0);
    signal TCGF : std_logic_vector(9 downto 0);
    signal TRACEDATA : std_logic_vector(3 downto 0);
    signal TXD_RIF : std_logic_vector(3 downto 0);
    signal TXDF : std_logic_vector(7 downto 0);
    signal F_BID : std_logic_vector(3 downto 0);
    signal F_BRESP_HRESP0 : std_logic_vector(1 downto 0);
    signal F_RDATA_HRDATA01 : std_logic_vector(63 downto 0);
    signal F_RID : std_logic_vector(3 downto 0);
    signal F_RRESP_HRESP1 : std_logic_vector(1 downto 0);
    signal MDDR_FABRIC_PRDATA : std_logic_vector(15 downto 0);
    signal DRAM_ADDR : std_logic_vector(15 downto 0);
    signal DRAM_BA : std_logic_vector(2 downto 0);
    signal DRAM_DM_RDQS_OUT : std_logic_vector(2 downto 0);
    signal DRAM_DQ_OUT : std_logic_vector(17 downto 0);
    signal DRAM_DQS_OUT : std_logic_vector(2 downto 0);
    signal DRAM_FIFO_WE_OUT : std_logic_vector(1 downto 0);
    signal DM_OE : std_logic_vector(2 downto 0);
    signal DRAM_DQ_OE : std_logic_vector(17 downto 0);
    signal DRAM_DQS_OE : std_logic_vector(2 downto 0);
    signal USB_ULPI_XCLK_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT, 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE, 
        USB_ULPI_NXT_PAD_Y, USB_ULPI_DIR_PAD_Y, 
        USB_ULPI_DATA_7_PAD_Y, 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT, 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE, 
        USB_ULPI_DATA_6_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT, 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE, 
        USB_ULPI_DATA_5_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT, 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE, 
        USB_ULPI_DATA_4_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT, 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE, 
        USB_ULPI_DATA_3_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT, 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE, 
        USB_ULPI_DATA_2_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT, 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE, 
        USB_ULPI_DATA_1_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT, 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE, 
        USB_ULPI_DATA_0_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT, 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE, 
        CAN_RXBUS_MGPIO3A_H2F_A, CAN_RXBUS_MGPIO3A_H2F_B, 
        CAN_TX_EBL_MGPIO4A_H2F_A, CAN_TX_EBL_MGPIO4A_H2F_B, 
        CAN_TXBUS_MGPIO2A_H2F_A, CAN_TXBUS_MGPIO2A_H2F_B, 
        FIC_2_APB_M_PCLK, COMMS_INT, FIC_2_APB_M_PRESET_N, 
        F_FM0_READYOUT, F_FM0_RESP, F_HM0_TRANS1, FAB_CHRGVBUS, 
        FAB_DISCHRGVBUS, FAB_DMPULLDOWN, FAB_DPPULLDOWN, 
        FAB_DRVVBUS, FAB_IDPULLUP, FAB_SUSPENDM, FAB_TERMSEL, 
        FAB_TXVALID, FAB_VCONTROLLOADM, FACC_GLMUX_SEL, 
        MSS_RESET_N_M2F, GTX_CLK, H2F_NMI, H2FCALIB, 
        I2C0_SCL_MGPIO31B_H2F_A, I2C0_SCL_MGPIO31B_H2F_B, 
        I2C0_SDA_MGPIO30B_H2F_A, I2C0_SDA_MGPIO30B_H2F_B, 
        I2C1_SCL_MGPIO1A_H2F_A, I2C1_SCL_MGPIO1A_H2F_B, 
        I2C1_SDA_MGPIO0A_H2F_A, MDCF, MDOENF, MDOF, 
        MMUART0_CTS_MGPIO19B_H2F_A, MMUART0_CTS_MGPIO19B_H2F_B, 
        MMUART0_DCD_MGPIO22B_H2F_A, MMUART0_DCD_MGPIO22B_H2F_B, 
        MMUART0_DSR_MGPIO20B_H2F_A, MMUART0_DSR_MGPIO20B_H2F_B, 
        MMUART0_DTR_MGPIO18B_H2F_A, MMUART0_DTR_MGPIO18B_H2F_B, 
        MMUART0_RI_MGPIO21B_H2F_A, MMUART0_RI_MGPIO21B_H2F_B, 
        MMUART0_RTS_MGPIO17B_H2F_A, MMUART0_RTS_MGPIO17B_H2F_B, 
        MMUART0_RXD_MGPIO28B_H2F_A, MMUART0_RXD_MGPIO28B_H2F_B, 
        MMUART0_SCK_MGPIO29B_H2F_A, MMUART0_SCK_MGPIO29B_H2F_B, 
        MMUART0_TXD_MGPIO27B_H2F_A, MMUART0_TXD_MGPIO27B_H2F_B, 
        MMUART1_DTR_MGPIO12B_H2F_A, MMUART1_RTS_MGPIO11B_H2F_A, 
        MMUART1_RTS_MGPIO11B_H2F_B, MMUART1_RXD_MGPIO26B_H2F_A, 
        MMUART1_RXD_MGPIO26B_H2F_B, MMUART1_SCK_MGPIO25B_H2F_A, 
        MMUART1_SCK_MGPIO25B_H2F_B, MMUART1_TXD_MGPIO24B_H2F_A, 
        MMUART1_TXD_MGPIO24B_H2F_B, MPLL_LOCK, 
        FIC_2_APB_M_PENABLE, FIC_2_APB_M_PSEL, FIC_2_APB_M_PWRITE, 
        RTC_MATCH, SLEEPDEEP, SLEEPHOLDACK, SLEEPING, 
        SMBALERT_NO0, SMBALERT_NO1, SMBSUS_NO0, SMBSUS_NO1, 
        SPI0_CLK_OUT, SPI0_SDI_MGPIO5A_H2F_A, 
        SPI0_SDI_MGPIO5A_H2F_B, SPI0_SDO_MGPIO6A_H2F_A, 
        SPI0_SDO_MGPIO6A_H2F_B, SPI0_SS0_MGPIO7A_H2F_A, 
        SPI0_SS0_MGPIO7A_H2F_B, SPI0_SS1_MGPIO8A_H2F_A, 
        SPI0_SS1_MGPIO8A_H2F_B, SPI0_SS2_MGPIO9A_H2F_A, 
        SPI0_SS2_MGPIO9A_H2F_B, SPI0_SS3_MGPIO10A_H2F_A, 
        SPI0_SS3_MGPIO10A_H2F_B, SPI0_SS4_MGPIO19A_H2F_A, 
        SPI0_SS5_MGPIO20A_H2F_A, SPI0_SS6_MGPIO21A_H2F_A, 
        SPI0_SS7_MGPIO22A_H2F_A, SPI1_CLK_OUT, 
        SPI1_SDI_MGPIO11A_H2F_A, SPI1_SDI_MGPIO11A_H2F_B, 
        SPI1_SDO_MGPIO12A_H2F_A, SPI1_SDO_MGPIO12A_H2F_B, 
        SPI1_SS0_MGPIO13A_H2F_A, SPI1_SS0_MGPIO13A_H2F_B, 
        SPI1_SS1_MGPIO14A_H2F_A, SPI1_SS1_MGPIO14A_H2F_B, 
        SPI1_SS2_MGPIO15A_H2F_A, SPI1_SS2_MGPIO15A_H2F_B, 
        SPI1_SS3_MGPIO16A_H2F_A, SPI1_SS3_MGPIO16A_H2F_B, 
        SPI1_SS4_MGPIO17A_H2F_A, SPI1_SS5_MGPIO18A_H2F_A, 
        SPI1_SS6_MGPIO23A_H2F_A, SPI1_SS7_MGPIO24A_H2F_A, 
        TRACECLK, TX_CLK, TX_ENF, TX_ERRF, TXCTL_EN_RIF, TXEV, 
        WDOGTIMEOUT, F_ARREADY_HREADYOUT1, F_AWREADY_HREADYOUT0, 
        F_BVALID, F_RLAST, F_RVALID, F_WREADY, MDDR_FABRIC_PREADY, 
        MDDR_FABRIC_PSLVERR, \VCC\, \GND\, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT, DRAM_CASN, DRAM_CKE, 
        DRAM_CLK, DRAM_CSN, DRAM_ODT, DRAM_RASN, DRAM_RSTN, 
        DRAM_WEN, I2C0_SCL_USBC_DATA1_MGPIO31B_OUT, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT, 
        MMUART0_DCD_MGPIO22B_OUT, MMUART0_DSR_MGPIO20B_OUT, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT, 
        MMUART0_RI_MGPIO21B_OUT, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT, 
        RGMII_MDC_RMII_MDC_OUT, RGMII_RX_CLK_OUT, 
        RGMII_TX_CLK_OUT, RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT, SPI0_SCK_USBA_XCLK_OUT, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OUT, 
        SPI0_SDO_USBA_STP_MGPIO6A_OUT, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT, SPI1_SCK_OUT, 
        SPI1_SDI_MGPIO11A_OUT, SPI1_SDO_MGPIO12A_OUT, 
        SPI1_SS0_MGPIO13A_OUT, SPI1_SS1_MGPIO14A_OUT, 
        SPI1_SS2_MGPIO15A_OUT, SPI1_SS3_MGPIO16A_OUT, 
        SPI1_SS4_MGPIO17A_OUT, SPI1_SS5_MGPIO18A_OUT, 
        SPI1_SS6_MGPIO23A_OUT, SPI1_SS7_MGPIO24A_OUT, 
        USBC_XCLK_OUT, CAN_RXBUS_USBA_DATA1_MGPIO3A_OE, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE, 
        MMUART0_DCD_MGPIO22B_OE, MMUART0_DSR_MGPIO20B_OE, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OE, 
        MMUART0_RI_MGPIO21B_OE, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE, 
        RGMII_MDC_RMII_MDC_OE, RGMII_RX_CLK_OE, RGMII_TX_CLK_OE, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE, SPI0_SCK_USBA_XCLK_OE, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OE, 
        SPI0_SDO_USBA_STP_MGPIO6A_OE, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OE, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE, SPI1_SCK_OE, 
        SPI1_SDI_MGPIO11A_OE, SPI1_SDO_MGPIO12A_OE, 
        SPI1_SS0_MGPIO13A_OE, SPI1_SS1_MGPIO14A_OE, 
        SPI1_SS2_MGPIO15A_OE, SPI1_SS3_MGPIO16A_OE, 
        SPI1_SS4_MGPIO17A_OE, SPI1_SS5_MGPIO18A_OE, 
        SPI1_SS6_MGPIO23A_OE, SPI1_SS7_MGPIO24A_OE, USBC_XCLK_OE
         : std_logic;

begin 


    USB_ULPI_DATA_5_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(5), D => 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT, E => 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE, Y => 
        USB_ULPI_DATA_5_PAD_Y);
    
    USB_ULPI_DATA_4_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(4), D => 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT, E => 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE, Y => 
        USB_ULPI_DATA_4_PAD_Y);
    
    USB_ULPI_DATA_7_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(7), D => 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT, E => 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE, Y => 
        USB_ULPI_DATA_7_PAD_Y);
    
    USB_ULPI_DATA_3_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(3), D => 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT, E
         => MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE, Y
         => USB_ULPI_DATA_3_PAD_Y);
    
    USB_ULPI_NXT_PAD : INBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_NXT, Y => USB_ULPI_NXT_PAD_Y);
    
    GND_Z : GND
      port map(Y => \GND\);
    
    USB_ULPI_XCLK_PAD : INBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_XCLK, Y => USB_ULPI_XCLK_PAD_Y);
    
    USB_ULPI_DATA_6_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(6), D => 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT, E => 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE, Y => 
        USB_ULPI_DATA_6_PAD_Y);
    
    USB_ULPI_DATA_2_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(2), D => 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT, E
         => MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE, 
        Y => USB_ULPI_DATA_2_PAD_Y);
    
    USB_ULPI_DIR_PAD : INBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DIR, Y => USB_ULPI_DIR_PAD_Y);
    
    MSS_ADLIB_INST : MSS_010

              generic map(INIT => "00" & x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000120481204812048120D8120D8120E00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104003FFFFE4000000000001100000000F0F01C00000182CFFC010842108421000001FE34001FF8000000400000000020091007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
         ACT_UBITS => x"FFFFFFFFFFFFFF",
         MEMORYFILE => "ENVM_init.mem",
         RTC_MAIN_XTL_FREQ => 0.000000, RTC_MAIN_XTL_MODE => "",
         DDR_CLK_FREQ => 0.000000)

      port map(CAN_RXBUS_MGPIO3A_H2F_A => CAN_RXBUS_MGPIO3A_H2F_A, 
        CAN_RXBUS_MGPIO3A_H2F_B => CAN_RXBUS_MGPIO3A_H2F_B, 
        CAN_TX_EBL_MGPIO4A_H2F_A => CAN_TX_EBL_MGPIO4A_H2F_A, 
        CAN_TX_EBL_MGPIO4A_H2F_B => CAN_TX_EBL_MGPIO4A_H2F_B, 
        CAN_TXBUS_MGPIO2A_H2F_A => CAN_TXBUS_MGPIO2A_H2F_A, 
        CAN_TXBUS_MGPIO2A_H2F_B => CAN_TXBUS_MGPIO2A_H2F_B, 
        CLK_CONFIG_APB => FIC_2_APB_M_PCLK, COMMS_INT => 
        COMMS_INT, CONFIG_PRESET_N => FIC_2_APB_M_PRESET_N, 
        EDAC_ERROR(7) => EDAC_ERROR(7), EDAC_ERROR(6) => 
        EDAC_ERROR(6), EDAC_ERROR(5) => EDAC_ERROR(5), 
        EDAC_ERROR(4) => EDAC_ERROR(4), EDAC_ERROR(3) => 
        EDAC_ERROR(3), EDAC_ERROR(2) => EDAC_ERROR(2), 
        EDAC_ERROR(1) => EDAC_ERROR(1), EDAC_ERROR(0) => 
        EDAC_ERROR(0), F_FM0_RDATA(31) => F_FM0_RDATA(31), 
        F_FM0_RDATA(30) => F_FM0_RDATA(30), F_FM0_RDATA(29) => 
        F_FM0_RDATA(29), F_FM0_RDATA(28) => F_FM0_RDATA(28), 
        F_FM0_RDATA(27) => F_FM0_RDATA(27), F_FM0_RDATA(26) => 
        F_FM0_RDATA(26), F_FM0_RDATA(25) => F_FM0_RDATA(25), 
        F_FM0_RDATA(24) => F_FM0_RDATA(24), F_FM0_RDATA(23) => 
        F_FM0_RDATA(23), F_FM0_RDATA(22) => F_FM0_RDATA(22), 
        F_FM0_RDATA(21) => F_FM0_RDATA(21), F_FM0_RDATA(20) => 
        F_FM0_RDATA(20), F_FM0_RDATA(19) => F_FM0_RDATA(19), 
        F_FM0_RDATA(18) => F_FM0_RDATA(18), F_FM0_RDATA(17) => 
        F_FM0_RDATA(17), F_FM0_RDATA(16) => F_FM0_RDATA(16), 
        F_FM0_RDATA(15) => F_FM0_RDATA(15), F_FM0_RDATA(14) => 
        F_FM0_RDATA(14), F_FM0_RDATA(13) => F_FM0_RDATA(13), 
        F_FM0_RDATA(12) => F_FM0_RDATA(12), F_FM0_RDATA(11) => 
        F_FM0_RDATA(11), F_FM0_RDATA(10) => F_FM0_RDATA(10), 
        F_FM0_RDATA(9) => F_FM0_RDATA(9), F_FM0_RDATA(8) => 
        F_FM0_RDATA(8), F_FM0_RDATA(7) => F_FM0_RDATA(7), 
        F_FM0_RDATA(6) => F_FM0_RDATA(6), F_FM0_RDATA(5) => 
        F_FM0_RDATA(5), F_FM0_RDATA(4) => F_FM0_RDATA(4), 
        F_FM0_RDATA(3) => F_FM0_RDATA(3), F_FM0_RDATA(2) => 
        F_FM0_RDATA(2), F_FM0_RDATA(1) => F_FM0_RDATA(1), 
        F_FM0_RDATA(0) => F_FM0_RDATA(0), F_FM0_READYOUT => 
        F_FM0_READYOUT, F_FM0_RESP => F_FM0_RESP, F_HM0_ADDR(31)
         => FIC_0_APB_M_PADDR(31), F_HM0_ADDR(30) => 
        FIC_0_APB_M_PADDR(30), F_HM0_ADDR(29) => 
        FIC_0_APB_M_PADDR(29), F_HM0_ADDR(28) => 
        FIC_0_APB_M_PADDR(28), F_HM0_ADDR(27) => 
        FIC_0_APB_M_PADDR(27), F_HM0_ADDR(26) => 
        FIC_0_APB_M_PADDR(26), F_HM0_ADDR(25) => 
        FIC_0_APB_M_PADDR(25), F_HM0_ADDR(24) => 
        FIC_0_APB_M_PADDR(24), F_HM0_ADDR(23) => 
        FIC_0_APB_M_PADDR(23), F_HM0_ADDR(22) => 
        FIC_0_APB_M_PADDR(22), F_HM0_ADDR(21) => 
        FIC_0_APB_M_PADDR(21), F_HM0_ADDR(20) => 
        FIC_0_APB_M_PADDR(20), F_HM0_ADDR(19) => 
        FIC_0_APB_M_PADDR(19), F_HM0_ADDR(18) => 
        FIC_0_APB_M_PADDR(18), F_HM0_ADDR(17) => 
        FIC_0_APB_M_PADDR(17), F_HM0_ADDR(16) => 
        FIC_0_APB_M_PADDR(16), F_HM0_ADDR(15) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15), 
        F_HM0_ADDR(14) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14), 
        F_HM0_ADDR(13) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13), 
        F_HM0_ADDR(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), 
        F_HM0_ADDR(11) => MC_System_0_AMBA_SLAVE_1_PADDR(11), 
        F_HM0_ADDR(10) => MC_System_0_AMBA_SLAVE_1_PADDR(10), 
        F_HM0_ADDR(9) => MC_System_0_AMBA_SLAVE_1_PADDR(9), 
        F_HM0_ADDR(8) => MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        F_HM0_ADDR(7) => MC_System_0_AMBA_SLAVE_1_PADDR(7), 
        F_HM0_ADDR(6) => MC_System_0_AMBA_SLAVE_1_PADDR(6), 
        F_HM0_ADDR(5) => MC_System_0_AMBA_SLAVE_1_PADDR(5), 
        F_HM0_ADDR(4) => MC_System_0_AMBA_SLAVE_1_PADDR(4), 
        F_HM0_ADDR(3) => MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        F_HM0_ADDR(2) => MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        F_HM0_ADDR(1) => MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        F_HM0_ADDR(0) => MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        F_HM0_ENABLE => MC_System_0_AMBA_SLAVE_1_PENABLE, 
        F_HM0_SEL => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, 
        F_HM0_SIZE(1) => F_HM0_SIZE(1), F_HM0_SIZE(0) => 
        F_HM0_SIZE(0), F_HM0_TRANS1 => F_HM0_TRANS1, 
        F_HM0_WDATA(31) => FIC_0_APB_M_PWDATA(31), 
        F_HM0_WDATA(30) => FIC_0_APB_M_PWDATA(30), 
        F_HM0_WDATA(29) => FIC_0_APB_M_PWDATA(29), 
        F_HM0_WDATA(28) => FIC_0_APB_M_PWDATA(28), 
        F_HM0_WDATA(27) => FIC_0_APB_M_PWDATA(27), 
        F_HM0_WDATA(26) => FIC_0_APB_M_PWDATA(26), 
        F_HM0_WDATA(25) => FIC_0_APB_M_PWDATA(25), 
        F_HM0_WDATA(24) => FIC_0_APB_M_PWDATA(24), 
        F_HM0_WDATA(23) => MC_System_0_AMBA_SLAVE_1_PWDATA(23), 
        F_HM0_WDATA(22) => MC_System_0_AMBA_SLAVE_1_PWDATA(22), 
        F_HM0_WDATA(21) => MC_System_0_AMBA_SLAVE_1_PWDATA(21), 
        F_HM0_WDATA(20) => MC_System_0_AMBA_SLAVE_1_PWDATA(20), 
        F_HM0_WDATA(19) => MC_System_0_AMBA_SLAVE_1_PWDATA(19), 
        F_HM0_WDATA(18) => MC_System_0_AMBA_SLAVE_1_PWDATA(18), 
        F_HM0_WDATA(17) => MC_System_0_AMBA_SLAVE_1_PWDATA(17), 
        F_HM0_WDATA(16) => MC_System_0_AMBA_SLAVE_1_PWDATA(16), 
        F_HM0_WDATA(15) => MC_System_0_AMBA_SLAVE_1_PWDATA(15), 
        F_HM0_WDATA(14) => MC_System_0_AMBA_SLAVE_1_PWDATA(14), 
        F_HM0_WDATA(13) => MC_System_0_AMBA_SLAVE_1_PWDATA(13), 
        F_HM0_WDATA(12) => MC_System_0_AMBA_SLAVE_1_PWDATA(12), 
        F_HM0_WDATA(11) => MC_System_0_AMBA_SLAVE_1_PWDATA(11), 
        F_HM0_WDATA(10) => MC_System_0_AMBA_SLAVE_1_PWDATA(10), 
        F_HM0_WDATA(9) => MC_System_0_AMBA_SLAVE_1_PWDATA(9), 
        F_HM0_WDATA(8) => MC_System_0_AMBA_SLAVE_1_PWDATA(8), 
        F_HM0_WDATA(7) => MC_System_0_AMBA_SLAVE_1_PWDATA(7), 
        F_HM0_WDATA(6) => MC_System_0_AMBA_SLAVE_1_PWDATA(6), 
        F_HM0_WDATA(5) => MC_System_0_AMBA_SLAVE_1_PWDATA(5), 
        F_HM0_WDATA(4) => MC_System_0_AMBA_SLAVE_1_PWDATA(4), 
        F_HM0_WDATA(3) => MC_System_0_AMBA_SLAVE_1_PWDATA(3), 
        F_HM0_WDATA(2) => MC_System_0_AMBA_SLAVE_1_PWDATA(2), 
        F_HM0_WDATA(1) => MC_System_0_AMBA_SLAVE_1_PWDATA(1), 
        F_HM0_WDATA(0) => MC_System_0_AMBA_SLAVE_1_PWDATA(0), 
        F_HM0_WRITE => MC_System_0_AMBA_SLAVE_1_PWRITE, 
        FAB_CHRGVBUS => FAB_CHRGVBUS, FAB_DISCHRGVBUS => 
        FAB_DISCHRGVBUS, FAB_DMPULLDOWN => FAB_DMPULLDOWN, 
        FAB_DPPULLDOWN => FAB_DPPULLDOWN, FAB_DRVVBUS => 
        FAB_DRVVBUS, FAB_IDPULLUP => FAB_IDPULLUP, FAB_OPMODE(1)
         => FAB_OPMODE(1), FAB_OPMODE(0) => FAB_OPMODE(0), 
        FAB_SUSPENDM => FAB_SUSPENDM, FAB_TERMSEL => FAB_TERMSEL, 
        FAB_TXVALID => FAB_TXVALID, FAB_VCONTROL(3) => 
        FAB_VCONTROL(3), FAB_VCONTROL(2) => FAB_VCONTROL(2), 
        FAB_VCONTROL(1) => FAB_VCONTROL(1), FAB_VCONTROL(0) => 
        FAB_VCONTROL(0), FAB_VCONTROLLOADM => FAB_VCONTROLLOADM, 
        FAB_XCVRSEL(1) => FAB_XCVRSEL(1), FAB_XCVRSEL(0) => 
        FAB_XCVRSEL(0), FAB_XDATAOUT(7) => FAB_XDATAOUT(7), 
        FAB_XDATAOUT(6) => FAB_XDATAOUT(6), FAB_XDATAOUT(5) => 
        FAB_XDATAOUT(5), FAB_XDATAOUT(4) => FAB_XDATAOUT(4), 
        FAB_XDATAOUT(3) => FAB_XDATAOUT(3), FAB_XDATAOUT(2) => 
        FAB_XDATAOUT(2), FAB_XDATAOUT(1) => FAB_XDATAOUT(1), 
        FAB_XDATAOUT(0) => FAB_XDATAOUT(0), FACC_GLMUX_SEL => 
        FACC_GLMUX_SEL, FIC32_0_MASTER(1) => FIC32_0_MASTER(1), 
        FIC32_0_MASTER(0) => FIC32_0_MASTER(0), FIC32_1_MASTER(1)
         => FIC32_1_MASTER(1), FIC32_1_MASTER(0) => 
        FIC32_1_MASTER(0), FPGA_RESET_N => MSS_RESET_N_M2F, 
        GTX_CLK => GTX_CLK, H2F_INTERRUPT(15) => 
        H2F_INTERRUPT(15), H2F_INTERRUPT(14) => H2F_INTERRUPT(14), 
        H2F_INTERRUPT(13) => H2F_INTERRUPT(13), H2F_INTERRUPT(12)
         => H2F_INTERRUPT(12), H2F_INTERRUPT(11) => 
        H2F_INTERRUPT(11), H2F_INTERRUPT(10) => H2F_INTERRUPT(10), 
        H2F_INTERRUPT(9) => H2F_INTERRUPT(9), H2F_INTERRUPT(8)
         => H2F_INTERRUPT(8), H2F_INTERRUPT(7) => 
        H2F_INTERRUPT(7), H2F_INTERRUPT(6) => H2F_INTERRUPT(6), 
        H2F_INTERRUPT(5) => H2F_INTERRUPT(5), H2F_INTERRUPT(4)
         => H2F_INTERRUPT(4), H2F_INTERRUPT(3) => 
        H2F_INTERRUPT(3), H2F_INTERRUPT(2) => H2F_INTERRUPT(2), 
        H2F_INTERRUPT(1) => H2F_INTERRUPT(1), H2F_INTERRUPT(0)
         => H2F_INTERRUPT(0), H2F_NMI => H2F_NMI, H2FCALIB => 
        H2FCALIB, I2C0_SCL_MGPIO31B_H2F_A => 
        I2C0_SCL_MGPIO31B_H2F_A, I2C0_SCL_MGPIO31B_H2F_B => 
        I2C0_SCL_MGPIO31B_H2F_B, I2C0_SDA_MGPIO30B_H2F_A => 
        I2C0_SDA_MGPIO30B_H2F_A, I2C0_SDA_MGPIO30B_H2F_B => 
        I2C0_SDA_MGPIO30B_H2F_B, I2C1_SCL_MGPIO1A_H2F_A => 
        I2C1_SCL_MGPIO1A_H2F_A, I2C1_SCL_MGPIO1A_H2F_B => 
        I2C1_SCL_MGPIO1A_H2F_B, I2C1_SDA_MGPIO0A_H2F_A => 
        I2C1_SDA_MGPIO0A_H2F_A, I2C1_SDA_MGPIO0A_H2F_B => 
        GPIO_0_M2F_c, MDCF => MDCF, MDOENF => MDOENF, MDOF => 
        MDOF, MMUART0_CTS_MGPIO19B_H2F_A => 
        MMUART0_CTS_MGPIO19B_H2F_A, MMUART0_CTS_MGPIO19B_H2F_B
         => MMUART0_CTS_MGPIO19B_H2F_B, 
        MMUART0_DCD_MGPIO22B_H2F_A => MMUART0_DCD_MGPIO22B_H2F_A, 
        MMUART0_DCD_MGPIO22B_H2F_B => MMUART0_DCD_MGPIO22B_H2F_B, 
        MMUART0_DSR_MGPIO20B_H2F_A => MMUART0_DSR_MGPIO20B_H2F_A, 
        MMUART0_DSR_MGPIO20B_H2F_B => MMUART0_DSR_MGPIO20B_H2F_B, 
        MMUART0_DTR_MGPIO18B_H2F_A => MMUART0_DTR_MGPIO18B_H2F_A, 
        MMUART0_DTR_MGPIO18B_H2F_B => MMUART0_DTR_MGPIO18B_H2F_B, 
        MMUART0_RI_MGPIO21B_H2F_A => MMUART0_RI_MGPIO21B_H2F_A, 
        MMUART0_RI_MGPIO21B_H2F_B => MMUART0_RI_MGPIO21B_H2F_B, 
        MMUART0_RTS_MGPIO17B_H2F_A => MMUART0_RTS_MGPIO17B_H2F_A, 
        MMUART0_RTS_MGPIO17B_H2F_B => MMUART0_RTS_MGPIO17B_H2F_B, 
        MMUART0_RXD_MGPIO28B_H2F_A => MMUART0_RXD_MGPIO28B_H2F_A, 
        MMUART0_RXD_MGPIO28B_H2F_B => MMUART0_RXD_MGPIO28B_H2F_B, 
        MMUART0_SCK_MGPIO29B_H2F_A => MMUART0_SCK_MGPIO29B_H2F_A, 
        MMUART0_SCK_MGPIO29B_H2F_B => MMUART0_SCK_MGPIO29B_H2F_B, 
        MMUART0_TXD_MGPIO27B_H2F_A => MMUART0_TXD_MGPIO27B_H2F_A, 
        MMUART0_TXD_MGPIO27B_H2F_B => MMUART0_TXD_MGPIO27B_H2F_B, 
        MMUART1_DTR_MGPIO12B_H2F_A => MMUART1_DTR_MGPIO12B_H2F_A, 
        MMUART1_RTS_MGPIO11B_H2F_A => MMUART1_RTS_MGPIO11B_H2F_A, 
        MMUART1_RTS_MGPIO11B_H2F_B => MMUART1_RTS_MGPIO11B_H2F_B, 
        MMUART1_RXD_MGPIO26B_H2F_A => MMUART1_RXD_MGPIO26B_H2F_A, 
        MMUART1_RXD_MGPIO26B_H2F_B => MMUART1_RXD_MGPIO26B_H2F_B, 
        MMUART1_SCK_MGPIO25B_H2F_A => MMUART1_SCK_MGPIO25B_H2F_A, 
        MMUART1_SCK_MGPIO25B_H2F_B => MMUART1_SCK_MGPIO25B_H2F_B, 
        MMUART1_TXD_MGPIO24B_H2F_A => MMUART1_TXD_MGPIO24B_H2F_A, 
        MMUART1_TXD_MGPIO24B_H2F_B => MMUART1_TXD_MGPIO24B_H2F_B, 
        MPLL_LOCK => MPLL_LOCK, PER2_FABRIC_PADDR(15) => 
        FIC_2_APB_M_PADDR(15), PER2_FABRIC_PADDR(14) => 
        FIC_2_APB_M_PADDR(14), PER2_FABRIC_PADDR(13) => 
        FIC_2_APB_M_PADDR(13), PER2_FABRIC_PADDR(12) => 
        FIC_2_APB_M_PADDR(12), PER2_FABRIC_PADDR(11) => 
        FIC_2_APB_M_PADDR(11), PER2_FABRIC_PADDR(10) => 
        FIC_2_APB_M_PADDR(10), PER2_FABRIC_PADDR(9) => 
        FIC_2_APB_M_PADDR(9), PER2_FABRIC_PADDR(8) => 
        FIC_2_APB_M_PADDR(8), PER2_FABRIC_PADDR(7) => 
        FIC_2_APB_M_PADDR(7), PER2_FABRIC_PADDR(6) => 
        FIC_2_APB_M_PADDR(6), PER2_FABRIC_PADDR(5) => 
        FIC_2_APB_M_PADDR(5), PER2_FABRIC_PADDR(4) => 
        FIC_2_APB_M_PADDR(4), PER2_FABRIC_PADDR(3) => 
        FIC_2_APB_M_PADDR(3), PER2_FABRIC_PADDR(2) => 
        FIC_2_APB_M_PADDR(2), PER2_FABRIC_PENABLE => 
        FIC_2_APB_M_PENABLE, PER2_FABRIC_PSEL => FIC_2_APB_M_PSEL, 
        PER2_FABRIC_PWDATA(31) => FIC_2_APB_M_PWDATA(31), 
        PER2_FABRIC_PWDATA(30) => FIC_2_APB_M_PWDATA(30), 
        PER2_FABRIC_PWDATA(29) => FIC_2_APB_M_PWDATA(29), 
        PER2_FABRIC_PWDATA(28) => FIC_2_APB_M_PWDATA(28), 
        PER2_FABRIC_PWDATA(27) => FIC_2_APB_M_PWDATA(27), 
        PER2_FABRIC_PWDATA(26) => FIC_2_APB_M_PWDATA(26), 
        PER2_FABRIC_PWDATA(25) => FIC_2_APB_M_PWDATA(25), 
        PER2_FABRIC_PWDATA(24) => FIC_2_APB_M_PWDATA(24), 
        PER2_FABRIC_PWDATA(23) => FIC_2_APB_M_PWDATA(23), 
        PER2_FABRIC_PWDATA(22) => FIC_2_APB_M_PWDATA(22), 
        PER2_FABRIC_PWDATA(21) => FIC_2_APB_M_PWDATA(21), 
        PER2_FABRIC_PWDATA(20) => FIC_2_APB_M_PWDATA(20), 
        PER2_FABRIC_PWDATA(19) => FIC_2_APB_M_PWDATA(19), 
        PER2_FABRIC_PWDATA(18) => FIC_2_APB_M_PWDATA(18), 
        PER2_FABRIC_PWDATA(17) => FIC_2_APB_M_PWDATA(17), 
        PER2_FABRIC_PWDATA(16) => FIC_2_APB_M_PWDATA(16), 
        PER2_FABRIC_PWDATA(15) => FIC_2_APB_M_PWDATA(15), 
        PER2_FABRIC_PWDATA(14) => FIC_2_APB_M_PWDATA(14), 
        PER2_FABRIC_PWDATA(13) => FIC_2_APB_M_PWDATA(13), 
        PER2_FABRIC_PWDATA(12) => FIC_2_APB_M_PWDATA(12), 
        PER2_FABRIC_PWDATA(11) => FIC_2_APB_M_PWDATA(11), 
        PER2_FABRIC_PWDATA(10) => FIC_2_APB_M_PWDATA(10), 
        PER2_FABRIC_PWDATA(9) => FIC_2_APB_M_PWDATA(9), 
        PER2_FABRIC_PWDATA(8) => FIC_2_APB_M_PWDATA(8), 
        PER2_FABRIC_PWDATA(7) => FIC_2_APB_M_PWDATA(7), 
        PER2_FABRIC_PWDATA(6) => FIC_2_APB_M_PWDATA(6), 
        PER2_FABRIC_PWDATA(5) => FIC_2_APB_M_PWDATA(5), 
        PER2_FABRIC_PWDATA(4) => FIC_2_APB_M_PWDATA(4), 
        PER2_FABRIC_PWDATA(3) => FIC_2_APB_M_PWDATA(3), 
        PER2_FABRIC_PWDATA(2) => FIC_2_APB_M_PWDATA(2), 
        PER2_FABRIC_PWDATA(1) => FIC_2_APB_M_PWDATA(1), 
        PER2_FABRIC_PWDATA(0) => FIC_2_APB_M_PWDATA(0), 
        PER2_FABRIC_PWRITE => FIC_2_APB_M_PWRITE, RTC_MATCH => 
        RTC_MATCH, SLEEPDEEP => SLEEPDEEP, SLEEPHOLDACK => 
        SLEEPHOLDACK, SLEEPING => SLEEPING, SMBALERT_NO0 => 
        SMBALERT_NO0, SMBALERT_NO1 => SMBALERT_NO1, SMBSUS_NO0
         => SMBSUS_NO0, SMBSUS_NO1 => SMBSUS_NO1, SPI0_CLK_OUT
         => SPI0_CLK_OUT, SPI0_SDI_MGPIO5A_H2F_A => 
        SPI0_SDI_MGPIO5A_H2F_A, SPI0_SDI_MGPIO5A_H2F_B => 
        SPI0_SDI_MGPIO5A_H2F_B, SPI0_SDO_MGPIO6A_H2F_A => 
        SPI0_SDO_MGPIO6A_H2F_A, SPI0_SDO_MGPIO6A_H2F_B => 
        SPI0_SDO_MGPIO6A_H2F_B, SPI0_SS0_MGPIO7A_H2F_A => 
        SPI0_SS0_MGPIO7A_H2F_A, SPI0_SS0_MGPIO7A_H2F_B => 
        SPI0_SS0_MGPIO7A_H2F_B, SPI0_SS1_MGPIO8A_H2F_A => 
        SPI0_SS1_MGPIO8A_H2F_A, SPI0_SS1_MGPIO8A_H2F_B => 
        SPI0_SS1_MGPIO8A_H2F_B, SPI0_SS2_MGPIO9A_H2F_A => 
        SPI0_SS2_MGPIO9A_H2F_A, SPI0_SS2_MGPIO9A_H2F_B => 
        SPI0_SS2_MGPIO9A_H2F_B, SPI0_SS3_MGPIO10A_H2F_A => 
        SPI0_SS3_MGPIO10A_H2F_A, SPI0_SS3_MGPIO10A_H2F_B => 
        SPI0_SS3_MGPIO10A_H2F_B, SPI0_SS4_MGPIO19A_H2F_A => 
        SPI0_SS4_MGPIO19A_H2F_A, SPI0_SS5_MGPIO20A_H2F_A => 
        SPI0_SS5_MGPIO20A_H2F_A, SPI0_SS6_MGPIO21A_H2F_A => 
        SPI0_SS6_MGPIO21A_H2F_A, SPI0_SS7_MGPIO22A_H2F_A => 
        SPI0_SS7_MGPIO22A_H2F_A, SPI1_CLK_OUT => SPI1_CLK_OUT, 
        SPI1_SDI_MGPIO11A_H2F_A => SPI1_SDI_MGPIO11A_H2F_A, 
        SPI1_SDI_MGPIO11A_H2F_B => SPI1_SDI_MGPIO11A_H2F_B, 
        SPI1_SDO_MGPIO12A_H2F_A => SPI1_SDO_MGPIO12A_H2F_A, 
        SPI1_SDO_MGPIO12A_H2F_B => SPI1_SDO_MGPIO12A_H2F_B, 
        SPI1_SS0_MGPIO13A_H2F_A => SPI1_SS0_MGPIO13A_H2F_A, 
        SPI1_SS0_MGPIO13A_H2F_B => SPI1_SS0_MGPIO13A_H2F_B, 
        SPI1_SS1_MGPIO14A_H2F_A => SPI1_SS1_MGPIO14A_H2F_A, 
        SPI1_SS1_MGPIO14A_H2F_B => SPI1_SS1_MGPIO14A_H2F_B, 
        SPI1_SS2_MGPIO15A_H2F_A => SPI1_SS2_MGPIO15A_H2F_A, 
        SPI1_SS2_MGPIO15A_H2F_B => SPI1_SS2_MGPIO15A_H2F_B, 
        SPI1_SS3_MGPIO16A_H2F_A => SPI1_SS3_MGPIO16A_H2F_A, 
        SPI1_SS3_MGPIO16A_H2F_B => SPI1_SS3_MGPIO16A_H2F_B, 
        SPI1_SS4_MGPIO17A_H2F_A => SPI1_SS4_MGPIO17A_H2F_A, 
        SPI1_SS5_MGPIO18A_H2F_A => SPI1_SS5_MGPIO18A_H2F_A, 
        SPI1_SS6_MGPIO23A_H2F_A => SPI1_SS6_MGPIO23A_H2F_A, 
        SPI1_SS7_MGPIO24A_H2F_A => SPI1_SS7_MGPIO24A_H2F_A, 
        TCGF(9) => TCGF(9), TCGF(8) => TCGF(8), TCGF(7) => 
        TCGF(7), TCGF(6) => TCGF(6), TCGF(5) => TCGF(5), TCGF(4)
         => TCGF(4), TCGF(3) => TCGF(3), TCGF(2) => TCGF(2), 
        TCGF(1) => TCGF(1), TCGF(0) => TCGF(0), TRACECLK => 
        TRACECLK, TRACEDATA(3) => TRACEDATA(3), TRACEDATA(2) => 
        TRACEDATA(2), TRACEDATA(1) => TRACEDATA(1), TRACEDATA(0)
         => TRACEDATA(0), TX_CLK => TX_CLK, TX_ENF => TX_ENF, 
        TX_ERRF => TX_ERRF, TXCTL_EN_RIF => TXCTL_EN_RIF, 
        TXD_RIF(3) => TXD_RIF(3), TXD_RIF(2) => TXD_RIF(2), 
        TXD_RIF(1) => TXD_RIF(1), TXD_RIF(0) => TXD_RIF(0), 
        TXDF(7) => TXDF(7), TXDF(6) => TXDF(6), TXDF(5) => 
        TXDF(5), TXDF(4) => TXDF(4), TXDF(3) => TXDF(3), TXDF(2)
         => TXDF(2), TXDF(1) => TXDF(1), TXDF(0) => TXDF(0), TXEV
         => TXEV, WDOGTIMEOUT => WDOGTIMEOUT, 
        F_ARREADY_HREADYOUT1 => F_ARREADY_HREADYOUT1, 
        F_AWREADY_HREADYOUT0 => F_AWREADY_HREADYOUT0, F_BID(3)
         => F_BID(3), F_BID(2) => F_BID(2), F_BID(1) => F_BID(1), 
        F_BID(0) => F_BID(0), F_BRESP_HRESP0(1) => 
        F_BRESP_HRESP0(1), F_BRESP_HRESP0(0) => F_BRESP_HRESP0(0), 
        F_BVALID => F_BVALID, F_RDATA_HRDATA01(63) => 
        F_RDATA_HRDATA01(63), F_RDATA_HRDATA01(62) => 
        F_RDATA_HRDATA01(62), F_RDATA_HRDATA01(61) => 
        F_RDATA_HRDATA01(61), F_RDATA_HRDATA01(60) => 
        F_RDATA_HRDATA01(60), F_RDATA_HRDATA01(59) => 
        F_RDATA_HRDATA01(59), F_RDATA_HRDATA01(58) => 
        F_RDATA_HRDATA01(58), F_RDATA_HRDATA01(57) => 
        F_RDATA_HRDATA01(57), F_RDATA_HRDATA01(56) => 
        F_RDATA_HRDATA01(56), F_RDATA_HRDATA01(55) => 
        F_RDATA_HRDATA01(55), F_RDATA_HRDATA01(54) => 
        F_RDATA_HRDATA01(54), F_RDATA_HRDATA01(53) => 
        F_RDATA_HRDATA01(53), F_RDATA_HRDATA01(52) => 
        F_RDATA_HRDATA01(52), F_RDATA_HRDATA01(51) => 
        F_RDATA_HRDATA01(51), F_RDATA_HRDATA01(50) => 
        F_RDATA_HRDATA01(50), F_RDATA_HRDATA01(49) => 
        F_RDATA_HRDATA01(49), F_RDATA_HRDATA01(48) => 
        F_RDATA_HRDATA01(48), F_RDATA_HRDATA01(47) => 
        F_RDATA_HRDATA01(47), F_RDATA_HRDATA01(46) => 
        F_RDATA_HRDATA01(46), F_RDATA_HRDATA01(45) => 
        F_RDATA_HRDATA01(45), F_RDATA_HRDATA01(44) => 
        F_RDATA_HRDATA01(44), F_RDATA_HRDATA01(43) => 
        F_RDATA_HRDATA01(43), F_RDATA_HRDATA01(42) => 
        F_RDATA_HRDATA01(42), F_RDATA_HRDATA01(41) => 
        F_RDATA_HRDATA01(41), F_RDATA_HRDATA01(40) => 
        F_RDATA_HRDATA01(40), F_RDATA_HRDATA01(39) => 
        F_RDATA_HRDATA01(39), F_RDATA_HRDATA01(38) => 
        F_RDATA_HRDATA01(38), F_RDATA_HRDATA01(37) => 
        F_RDATA_HRDATA01(37), F_RDATA_HRDATA01(36) => 
        F_RDATA_HRDATA01(36), F_RDATA_HRDATA01(35) => 
        F_RDATA_HRDATA01(35), F_RDATA_HRDATA01(34) => 
        F_RDATA_HRDATA01(34), F_RDATA_HRDATA01(33) => 
        F_RDATA_HRDATA01(33), F_RDATA_HRDATA01(32) => 
        F_RDATA_HRDATA01(32), F_RDATA_HRDATA01(31) => 
        F_RDATA_HRDATA01(31), F_RDATA_HRDATA01(30) => 
        F_RDATA_HRDATA01(30), F_RDATA_HRDATA01(29) => 
        F_RDATA_HRDATA01(29), F_RDATA_HRDATA01(28) => 
        F_RDATA_HRDATA01(28), F_RDATA_HRDATA01(27) => 
        F_RDATA_HRDATA01(27), F_RDATA_HRDATA01(26) => 
        F_RDATA_HRDATA01(26), F_RDATA_HRDATA01(25) => 
        F_RDATA_HRDATA01(25), F_RDATA_HRDATA01(24) => 
        F_RDATA_HRDATA01(24), F_RDATA_HRDATA01(23) => 
        F_RDATA_HRDATA01(23), F_RDATA_HRDATA01(22) => 
        F_RDATA_HRDATA01(22), F_RDATA_HRDATA01(21) => 
        F_RDATA_HRDATA01(21), F_RDATA_HRDATA01(20) => 
        F_RDATA_HRDATA01(20), F_RDATA_HRDATA01(19) => 
        F_RDATA_HRDATA01(19), F_RDATA_HRDATA01(18) => 
        F_RDATA_HRDATA01(18), F_RDATA_HRDATA01(17) => 
        F_RDATA_HRDATA01(17), F_RDATA_HRDATA01(16) => 
        F_RDATA_HRDATA01(16), F_RDATA_HRDATA01(15) => 
        F_RDATA_HRDATA01(15), F_RDATA_HRDATA01(14) => 
        F_RDATA_HRDATA01(14), F_RDATA_HRDATA01(13) => 
        F_RDATA_HRDATA01(13), F_RDATA_HRDATA01(12) => 
        F_RDATA_HRDATA01(12), F_RDATA_HRDATA01(11) => 
        F_RDATA_HRDATA01(11), F_RDATA_HRDATA01(10) => 
        F_RDATA_HRDATA01(10), F_RDATA_HRDATA01(9) => 
        F_RDATA_HRDATA01(9), F_RDATA_HRDATA01(8) => 
        F_RDATA_HRDATA01(8), F_RDATA_HRDATA01(7) => 
        F_RDATA_HRDATA01(7), F_RDATA_HRDATA01(6) => 
        F_RDATA_HRDATA01(6), F_RDATA_HRDATA01(5) => 
        F_RDATA_HRDATA01(5), F_RDATA_HRDATA01(4) => 
        F_RDATA_HRDATA01(4), F_RDATA_HRDATA01(3) => 
        F_RDATA_HRDATA01(3), F_RDATA_HRDATA01(2) => 
        F_RDATA_HRDATA01(2), F_RDATA_HRDATA01(1) => 
        F_RDATA_HRDATA01(1), F_RDATA_HRDATA01(0) => 
        F_RDATA_HRDATA01(0), F_RID(3) => F_RID(3), F_RID(2) => 
        F_RID(2), F_RID(1) => F_RID(1), F_RID(0) => F_RID(0), 
        F_RLAST => F_RLAST, F_RRESP_HRESP1(1) => 
        F_RRESP_HRESP1(1), F_RRESP_HRESP1(0) => F_RRESP_HRESP1(0), 
        F_RVALID => F_RVALID, F_WREADY => F_WREADY, 
        MDDR_FABRIC_PRDATA(15) => MDDR_FABRIC_PRDATA(15), 
        MDDR_FABRIC_PRDATA(14) => MDDR_FABRIC_PRDATA(14), 
        MDDR_FABRIC_PRDATA(13) => MDDR_FABRIC_PRDATA(13), 
        MDDR_FABRIC_PRDATA(12) => MDDR_FABRIC_PRDATA(12), 
        MDDR_FABRIC_PRDATA(11) => MDDR_FABRIC_PRDATA(11), 
        MDDR_FABRIC_PRDATA(10) => MDDR_FABRIC_PRDATA(10), 
        MDDR_FABRIC_PRDATA(9) => MDDR_FABRIC_PRDATA(9), 
        MDDR_FABRIC_PRDATA(8) => MDDR_FABRIC_PRDATA(8), 
        MDDR_FABRIC_PRDATA(7) => MDDR_FABRIC_PRDATA(7), 
        MDDR_FABRIC_PRDATA(6) => MDDR_FABRIC_PRDATA(6), 
        MDDR_FABRIC_PRDATA(5) => MDDR_FABRIC_PRDATA(5), 
        MDDR_FABRIC_PRDATA(4) => MDDR_FABRIC_PRDATA(4), 
        MDDR_FABRIC_PRDATA(3) => MDDR_FABRIC_PRDATA(3), 
        MDDR_FABRIC_PRDATA(2) => MDDR_FABRIC_PRDATA(2), 
        MDDR_FABRIC_PRDATA(1) => MDDR_FABRIC_PRDATA(1), 
        MDDR_FABRIC_PRDATA(0) => MDDR_FABRIC_PRDATA(0), 
        MDDR_FABRIC_PREADY => MDDR_FABRIC_PREADY, 
        MDDR_FABRIC_PSLVERR => MDDR_FABRIC_PSLVERR, 
        CAN_RXBUS_F2H_SCP => \VCC\, CAN_TX_EBL_F2H_SCP => \VCC\, 
        CAN_TXBUS_F2H_SCP => \VCC\, COLF => \VCC\, CRSF => \VCC\, 
        F2_DMAREADY(1) => \VCC\, F2_DMAREADY(0) => \VCC\, 
        F2H_INTERRUPT(15) => \GND\, F2H_INTERRUPT(14) => \GND\, 
        F2H_INTERRUPT(13) => \GND\, F2H_INTERRUPT(12) => \GND\, 
        F2H_INTERRUPT(11) => \GND\, F2H_INTERRUPT(10) => \GND\, 
        F2H_INTERRUPT(9) => \GND\, F2H_INTERRUPT(8) => \GND\, 
        F2H_INTERRUPT(7) => \GND\, F2H_INTERRUPT(6) => \GND\, 
        F2H_INTERRUPT(5) => \GND\, F2H_INTERRUPT(4) => \GND\, 
        F2H_INTERRUPT(3) => \GND\, F2H_INTERRUPT(2) => \GND\, 
        F2H_INTERRUPT(1) => \GND\, F2H_INTERRUPT(0) => \GND\, 
        F2HCALIB => \VCC\, F_DMAREADY(1) => \VCC\, F_DMAREADY(0)
         => \VCC\, F_FM0_ADDR(31) => \GND\, F_FM0_ADDR(30) => 
        \GND\, F_FM0_ADDR(29) => \GND\, F_FM0_ADDR(28) => \GND\, 
        F_FM0_ADDR(27) => \GND\, F_FM0_ADDR(26) => \GND\, 
        F_FM0_ADDR(25) => \GND\, F_FM0_ADDR(24) => \GND\, 
        F_FM0_ADDR(23) => \GND\, F_FM0_ADDR(22) => \GND\, 
        F_FM0_ADDR(21) => \GND\, F_FM0_ADDR(20) => \GND\, 
        F_FM0_ADDR(19) => \GND\, F_FM0_ADDR(18) => \GND\, 
        F_FM0_ADDR(17) => \GND\, F_FM0_ADDR(16) => \GND\, 
        F_FM0_ADDR(15) => \GND\, F_FM0_ADDR(14) => \GND\, 
        F_FM0_ADDR(13) => \GND\, F_FM0_ADDR(12) => \GND\, 
        F_FM0_ADDR(11) => \GND\, F_FM0_ADDR(10) => \GND\, 
        F_FM0_ADDR(9) => \GND\, F_FM0_ADDR(8) => \GND\, 
        F_FM0_ADDR(7) => \GND\, F_FM0_ADDR(6) => \GND\, 
        F_FM0_ADDR(5) => \GND\, F_FM0_ADDR(4) => \GND\, 
        F_FM0_ADDR(3) => \GND\, F_FM0_ADDR(2) => \GND\, 
        F_FM0_ADDR(1) => \GND\, F_FM0_ADDR(0) => \GND\, 
        F_FM0_ENABLE => \GND\, F_FM0_MASTLOCK => \GND\, 
        F_FM0_READY => \VCC\, F_FM0_SEL => \GND\, F_FM0_SIZE(1)
         => \GND\, F_FM0_SIZE(0) => \GND\, F_FM0_TRANS1 => \GND\, 
        F_FM0_WDATA(31) => \GND\, F_FM0_WDATA(30) => \GND\, 
        F_FM0_WDATA(29) => \GND\, F_FM0_WDATA(28) => \GND\, 
        F_FM0_WDATA(27) => \GND\, F_FM0_WDATA(26) => \GND\, 
        F_FM0_WDATA(25) => \GND\, F_FM0_WDATA(24) => \GND\, 
        F_FM0_WDATA(23) => \GND\, F_FM0_WDATA(22) => \GND\, 
        F_FM0_WDATA(21) => \GND\, F_FM0_WDATA(20) => \GND\, 
        F_FM0_WDATA(19) => \GND\, F_FM0_WDATA(18) => \GND\, 
        F_FM0_WDATA(17) => \GND\, F_FM0_WDATA(16) => \GND\, 
        F_FM0_WDATA(15) => \GND\, F_FM0_WDATA(14) => \GND\, 
        F_FM0_WDATA(13) => \GND\, F_FM0_WDATA(12) => \GND\, 
        F_FM0_WDATA(11) => \GND\, F_FM0_WDATA(10) => \GND\, 
        F_FM0_WDATA(9) => \GND\, F_FM0_WDATA(8) => \GND\, 
        F_FM0_WDATA(7) => \GND\, F_FM0_WDATA(6) => \GND\, 
        F_FM0_WDATA(5) => \GND\, F_FM0_WDATA(4) => \GND\, 
        F_FM0_WDATA(3) => \GND\, F_FM0_WDATA(2) => \GND\, 
        F_FM0_WDATA(1) => \GND\, F_FM0_WDATA(0) => \GND\, 
        F_FM0_WRITE => \GND\, F_HM0_RDATA(31) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(30) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(29) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(28) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(27) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(26) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(25) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(24) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(23) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(22) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22, 
        F_HM0_RDATA(21) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21, 
        F_HM0_RDATA(20) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20, 
        F_HM0_RDATA(19) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19, 
        F_HM0_RDATA(18) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18, 
        F_HM0_RDATA(17) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17, 
        F_HM0_RDATA(16) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16, 
        F_HM0_RDATA(15) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15, 
        F_HM0_RDATA(14) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14, 
        F_HM0_RDATA(13) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13, 
        F_HM0_RDATA(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12, 
        F_HM0_RDATA(11) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11, 
        F_HM0_RDATA(10) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10, 
        F_HM0_RDATA(9) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9, 
        F_HM0_RDATA(8) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8, 
        F_HM0_RDATA(7) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7, 
        F_HM0_RDATA(6) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6, 
        F_HM0_RDATA(5) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5, 
        F_HM0_RDATA(4) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4, 
        F_HM0_RDATA(3) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3, 
        F_HM0_RDATA(2) => PRDATA_N_3_mux_i_0, F_HM0_RDATA(1) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1, 
        F_HM0_RDATA(0) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0, 
        F_HM0_READY => \VCC\, F_HM0_RESP => \GND\, FAB_AVALID => 
        \VCC\, FAB_HOSTDISCON => \VCC\, FAB_IDDIG => \VCC\, 
        FAB_LINESTATE(1) => \VCC\, FAB_LINESTATE(0) => \VCC\, 
        FAB_M3_RESET_N => \VCC\, FAB_PLL_LOCK => 
        MC_System_0_FIC_0_LOCK, FAB_RXACTIVE => \VCC\, 
        FAB_RXERROR => \VCC\, FAB_RXVALID => \VCC\, FAB_RXVALIDH
         => \GND\, FAB_SESSEND => \VCC\, FAB_TXREADY => \VCC\, 
        FAB_VBUSVALID => \VCC\, FAB_VSTATUS(7) => \VCC\, 
        FAB_VSTATUS(6) => \VCC\, FAB_VSTATUS(5) => \VCC\, 
        FAB_VSTATUS(4) => \VCC\, FAB_VSTATUS(3) => \VCC\, 
        FAB_VSTATUS(2) => \VCC\, FAB_VSTATUS(1) => \VCC\, 
        FAB_VSTATUS(0) => \VCC\, FAB_XDATAIN(7) => \VCC\, 
        FAB_XDATAIN(6) => \VCC\, FAB_XDATAIN(5) => \VCC\, 
        FAB_XDATAIN(4) => \VCC\, FAB_XDATAIN(3) => \VCC\, 
        FAB_XDATAIN(2) => \VCC\, FAB_XDATAIN(1) => \VCC\, 
        FAB_XDATAIN(0) => \VCC\, GTX_CLKPF => \VCC\, I2C0_BCLK
         => \VCC\, I2C0_SCL_F2H_SCP => \VCC\, I2C0_SDA_F2H_SCP
         => \VCC\, I2C1_BCLK => \VCC\, I2C1_SCL_F2H_SCP => \VCC\, 
        I2C1_SDA_F2H_SCP => \VCC\, MDIF => \VCC\, 
        MGPIO0A_F2H_GPIN => \VCC\, MGPIO10A_F2H_GPIN => \VCC\, 
        MGPIO11A_F2H_GPIN => \VCC\, MGPIO11B_F2H_GPIN => \VCC\, 
        MGPIO12A_F2H_GPIN => \VCC\, MGPIO13A_F2H_GPIN => \VCC\, 
        MGPIO14A_F2H_GPIN => \VCC\, MGPIO15A_F2H_GPIN => \VCC\, 
        MGPIO16A_F2H_GPIN => \VCC\, MGPIO17B_F2H_GPIN => \VCC\, 
        MGPIO18B_F2H_GPIN => \VCC\, MGPIO19B_F2H_GPIN => \VCC\, 
        MGPIO1A_F2H_GPIN => \VCC\, MGPIO20B_F2H_GPIN => \VCC\, 
        MGPIO21B_F2H_GPIN => \VCC\, MGPIO22B_F2H_GPIN => \VCC\, 
        MGPIO24B_F2H_GPIN => \VCC\, MGPIO25B_F2H_GPIN => \VCC\, 
        MGPIO26B_F2H_GPIN => \VCC\, MGPIO27B_F2H_GPIN => \VCC\, 
        MGPIO28B_F2H_GPIN => \VCC\, MGPIO29B_F2H_GPIN => \VCC\, 
        MGPIO2A_F2H_GPIN => \VCC\, MGPIO30B_F2H_GPIN => \VCC\, 
        MGPIO31B_F2H_GPIN => \VCC\, MGPIO3A_F2H_GPIN => \VCC\, 
        MGPIO4A_F2H_GPIN => \VCC\, MGPIO5A_F2H_GPIN => \VCC\, 
        MGPIO6A_F2H_GPIN => \VCC\, MGPIO7A_F2H_GPIN => \VCC\, 
        MGPIO8A_F2H_GPIN => \VCC\, MGPIO9A_F2H_GPIN => \VCC\, 
        MMUART0_CTS_F2H_SCP => \VCC\, MMUART0_DCD_F2H_SCP => 
        \VCC\, MMUART0_DSR_F2H_SCP => \VCC\, MMUART0_DTR_F2H_SCP
         => \VCC\, MMUART0_RI_F2H_SCP => \VCC\, 
        MMUART0_RTS_F2H_SCP => \VCC\, MMUART0_RXD_F2H_SCP => 
        \VCC\, MMUART0_SCK_F2H_SCP => \VCC\, MMUART0_TXD_F2H_SCP
         => \VCC\, MMUART1_CTS_F2H_SCP => \VCC\, 
        MMUART1_DCD_F2H_SCP => \VCC\, MMUART1_DSR_F2H_SCP => 
        \VCC\, MMUART1_RI_F2H_SCP => \VCC\, MMUART1_RTS_F2H_SCP
         => \VCC\, MMUART1_RXD_F2H_SCP => \VCC\, 
        MMUART1_SCK_F2H_SCP => \VCC\, MMUART1_TXD_F2H_SCP => 
        \VCC\, PER2_FABRIC_PRDATA(31) => \GND\, 
        PER2_FABRIC_PRDATA(30) => \GND\, PER2_FABRIC_PRDATA(29)
         => \GND\, PER2_FABRIC_PRDATA(28) => \GND\, 
        PER2_FABRIC_PRDATA(27) => \GND\, PER2_FABRIC_PRDATA(26)
         => \GND\, PER2_FABRIC_PRDATA(25) => \GND\, 
        PER2_FABRIC_PRDATA(24) => \GND\, PER2_FABRIC_PRDATA(23)
         => \GND\, PER2_FABRIC_PRDATA(22) => \GND\, 
        PER2_FABRIC_PRDATA(21) => \GND\, PER2_FABRIC_PRDATA(20)
         => \GND\, PER2_FABRIC_PRDATA(19) => \GND\, 
        PER2_FABRIC_PRDATA(18) => \GND\, PER2_FABRIC_PRDATA(17)
         => \GND\, PER2_FABRIC_PRDATA(16) => \GND\, 
        PER2_FABRIC_PRDATA(15) => \GND\, PER2_FABRIC_PRDATA(14)
         => \GND\, PER2_FABRIC_PRDATA(13) => \GND\, 
        PER2_FABRIC_PRDATA(12) => \GND\, PER2_FABRIC_PRDATA(11)
         => \GND\, PER2_FABRIC_PRDATA(10) => \GND\, 
        PER2_FABRIC_PRDATA(9) => \GND\, PER2_FABRIC_PRDATA(8) => 
        \GND\, PER2_FABRIC_PRDATA(7) => \GND\, 
        PER2_FABRIC_PRDATA(6) => \GND\, PER2_FABRIC_PRDATA(5) => 
        \GND\, PER2_FABRIC_PRDATA(4) => \GND\, 
        PER2_FABRIC_PRDATA(3) => \GND\, PER2_FABRIC_PRDATA(2) => 
        \GND\, PER2_FABRIC_PRDATA(1) => \GND\, 
        PER2_FABRIC_PRDATA(0) => \GND\, PER2_FABRIC_PREADY => 
        \VCC\, PER2_FABRIC_PSLVERR => \GND\, RCGF(9) => \VCC\, 
        RCGF(8) => \VCC\, RCGF(7) => \VCC\, RCGF(6) => \VCC\, 
        RCGF(5) => \VCC\, RCGF(4) => \VCC\, RCGF(3) => \VCC\, 
        RCGF(2) => \VCC\, RCGF(1) => \VCC\, RCGF(0) => \VCC\, 
        RX_CLKPF => \VCC\, RX_DVF => \VCC\, RX_ERRF => \VCC\, 
        RX_EV => \VCC\, RXDF(7) => \VCC\, RXDF(6) => \VCC\, 
        RXDF(5) => \VCC\, RXDF(4) => \VCC\, RXDF(3) => \VCC\, 
        RXDF(2) => \VCC\, RXDF(1) => \VCC\, RXDF(0) => \VCC\, 
        SLEEPHOLDREQ => \GND\, SMBALERT_NI0 => \VCC\, 
        SMBALERT_NI1 => \VCC\, SMBSUS_NI0 => \VCC\, SMBSUS_NI1
         => \VCC\, SPI0_CLK_IN => \VCC\, SPI0_SDI_F2H_SCP => 
        \VCC\, SPI0_SDO_F2H_SCP => \VCC\, SPI0_SS0_F2H_SCP => 
        \VCC\, SPI0_SS1_F2H_SCP => \VCC\, SPI0_SS2_F2H_SCP => 
        \VCC\, SPI0_SS3_F2H_SCP => \VCC\, SPI1_CLK_IN => \VCC\, 
        SPI1_SDI_F2H_SCP => \VCC\, SPI1_SDO_F2H_SCP => \VCC\, 
        SPI1_SS0_F2H_SCP => \VCC\, SPI1_SS1_F2H_SCP => \VCC\, 
        SPI1_SS2_F2H_SCP => \VCC\, SPI1_SS3_F2H_SCP => \VCC\, 
        TX_CLKPF => \VCC\, USER_MSS_GPIO_RESET_N => \VCC\, 
        USER_MSS_RESET_N => \VCC\, XCLK_FAB => \VCC\, CLK_BASE
         => MC_System_0_FIC_0_CLK, CLK_MDDR_APB => \VCC\, 
        F_ARADDR_HADDR1(31) => \VCC\, F_ARADDR_HADDR1(30) => 
        \VCC\, F_ARADDR_HADDR1(29) => \VCC\, F_ARADDR_HADDR1(28)
         => \VCC\, F_ARADDR_HADDR1(27) => \VCC\, 
        F_ARADDR_HADDR1(26) => \VCC\, F_ARADDR_HADDR1(25) => 
        \VCC\, F_ARADDR_HADDR1(24) => \VCC\, F_ARADDR_HADDR1(23)
         => \VCC\, F_ARADDR_HADDR1(22) => \VCC\, 
        F_ARADDR_HADDR1(21) => \VCC\, F_ARADDR_HADDR1(20) => 
        \VCC\, F_ARADDR_HADDR1(19) => \VCC\, F_ARADDR_HADDR1(18)
         => \VCC\, F_ARADDR_HADDR1(17) => \VCC\, 
        F_ARADDR_HADDR1(16) => \VCC\, F_ARADDR_HADDR1(15) => 
        \VCC\, F_ARADDR_HADDR1(14) => \VCC\, F_ARADDR_HADDR1(13)
         => \VCC\, F_ARADDR_HADDR1(12) => \VCC\, 
        F_ARADDR_HADDR1(11) => \VCC\, F_ARADDR_HADDR1(10) => 
        \VCC\, F_ARADDR_HADDR1(9) => \VCC\, F_ARADDR_HADDR1(8)
         => \VCC\, F_ARADDR_HADDR1(7) => \VCC\, 
        F_ARADDR_HADDR1(6) => \VCC\, F_ARADDR_HADDR1(5) => \VCC\, 
        F_ARADDR_HADDR1(4) => \VCC\, F_ARADDR_HADDR1(3) => \VCC\, 
        F_ARADDR_HADDR1(2) => \VCC\, F_ARADDR_HADDR1(1) => \VCC\, 
        F_ARADDR_HADDR1(0) => \VCC\, F_ARBURST_HTRANS1(1) => 
        \GND\, F_ARBURST_HTRANS1(0) => \GND\, F_ARID_HSEL1(3) => 
        \GND\, F_ARID_HSEL1(2) => \GND\, F_ARID_HSEL1(1) => \GND\, 
        F_ARID_HSEL1(0) => \GND\, F_ARLEN_HBURST1(3) => \GND\, 
        F_ARLEN_HBURST1(2) => \GND\, F_ARLEN_HBURST1(1) => \GND\, 
        F_ARLEN_HBURST1(0) => \GND\, F_ARLOCK_HMASTLOCK1(1) => 
        \GND\, F_ARLOCK_HMASTLOCK1(0) => \GND\, 
        F_ARSIZE_HSIZE1(1) => \GND\, F_ARSIZE_HSIZE1(0) => \GND\, 
        F_ARVALID_HWRITE1 => \GND\, F_AWADDR_HADDR0(31) => \VCC\, 
        F_AWADDR_HADDR0(30) => \VCC\, F_AWADDR_HADDR0(29) => 
        \VCC\, F_AWADDR_HADDR0(28) => \VCC\, F_AWADDR_HADDR0(27)
         => \VCC\, F_AWADDR_HADDR0(26) => \VCC\, 
        F_AWADDR_HADDR0(25) => \VCC\, F_AWADDR_HADDR0(24) => 
        \VCC\, F_AWADDR_HADDR0(23) => \VCC\, F_AWADDR_HADDR0(22)
         => \VCC\, F_AWADDR_HADDR0(21) => \VCC\, 
        F_AWADDR_HADDR0(20) => \VCC\, F_AWADDR_HADDR0(19) => 
        \VCC\, F_AWADDR_HADDR0(18) => \VCC\, F_AWADDR_HADDR0(17)
         => \VCC\, F_AWADDR_HADDR0(16) => \VCC\, 
        F_AWADDR_HADDR0(15) => \VCC\, F_AWADDR_HADDR0(14) => 
        \VCC\, F_AWADDR_HADDR0(13) => \VCC\, F_AWADDR_HADDR0(12)
         => \VCC\, F_AWADDR_HADDR0(11) => \VCC\, 
        F_AWADDR_HADDR0(10) => \VCC\, F_AWADDR_HADDR0(9) => \VCC\, 
        F_AWADDR_HADDR0(8) => \VCC\, F_AWADDR_HADDR0(7) => \VCC\, 
        F_AWADDR_HADDR0(6) => \VCC\, F_AWADDR_HADDR0(5) => \VCC\, 
        F_AWADDR_HADDR0(4) => \VCC\, F_AWADDR_HADDR0(3) => \VCC\, 
        F_AWADDR_HADDR0(2) => \VCC\, F_AWADDR_HADDR0(1) => \VCC\, 
        F_AWADDR_HADDR0(0) => \VCC\, F_AWBURST_HTRANS0(1) => 
        \GND\, F_AWBURST_HTRANS0(0) => \GND\, F_AWID_HSEL0(3) => 
        \GND\, F_AWID_HSEL0(2) => \GND\, F_AWID_HSEL0(1) => \GND\, 
        F_AWID_HSEL0(0) => \GND\, F_AWLEN_HBURST0(3) => \GND\, 
        F_AWLEN_HBURST0(2) => \GND\, F_AWLEN_HBURST0(1) => \GND\, 
        F_AWLEN_HBURST0(0) => \GND\, F_AWLOCK_HMASTLOCK0(1) => 
        \GND\, F_AWLOCK_HMASTLOCK0(0) => \GND\, 
        F_AWSIZE_HSIZE0(1) => \GND\, F_AWSIZE_HSIZE0(0) => \GND\, 
        F_AWVALID_HWRITE0 => \GND\, F_BREADY => \GND\, F_RMW_AXI
         => \GND\, F_RREADY => \GND\, F_WDATA_HWDATA01(63) => 
        \VCC\, F_WDATA_HWDATA01(62) => \VCC\, 
        F_WDATA_HWDATA01(61) => \VCC\, F_WDATA_HWDATA01(60) => 
        \VCC\, F_WDATA_HWDATA01(59) => \VCC\, 
        F_WDATA_HWDATA01(58) => \VCC\, F_WDATA_HWDATA01(57) => 
        \VCC\, F_WDATA_HWDATA01(56) => \VCC\, 
        F_WDATA_HWDATA01(55) => \VCC\, F_WDATA_HWDATA01(54) => 
        \VCC\, F_WDATA_HWDATA01(53) => \VCC\, 
        F_WDATA_HWDATA01(52) => \VCC\, F_WDATA_HWDATA01(51) => 
        \VCC\, F_WDATA_HWDATA01(50) => \VCC\, 
        F_WDATA_HWDATA01(49) => \VCC\, F_WDATA_HWDATA01(48) => 
        \VCC\, F_WDATA_HWDATA01(47) => \VCC\, 
        F_WDATA_HWDATA01(46) => \VCC\, F_WDATA_HWDATA01(45) => 
        \VCC\, F_WDATA_HWDATA01(44) => \VCC\, 
        F_WDATA_HWDATA01(43) => \VCC\, F_WDATA_HWDATA01(42) => 
        \VCC\, F_WDATA_HWDATA01(41) => \VCC\, 
        F_WDATA_HWDATA01(40) => \VCC\, F_WDATA_HWDATA01(39) => 
        \VCC\, F_WDATA_HWDATA01(38) => \VCC\, 
        F_WDATA_HWDATA01(37) => \VCC\, F_WDATA_HWDATA01(36) => 
        \VCC\, F_WDATA_HWDATA01(35) => \VCC\, 
        F_WDATA_HWDATA01(34) => \VCC\, F_WDATA_HWDATA01(33) => 
        \VCC\, F_WDATA_HWDATA01(32) => \VCC\, 
        F_WDATA_HWDATA01(31) => \VCC\, F_WDATA_HWDATA01(30) => 
        \VCC\, F_WDATA_HWDATA01(29) => \VCC\, 
        F_WDATA_HWDATA01(28) => \VCC\, F_WDATA_HWDATA01(27) => 
        \VCC\, F_WDATA_HWDATA01(26) => \VCC\, 
        F_WDATA_HWDATA01(25) => \VCC\, F_WDATA_HWDATA01(24) => 
        \VCC\, F_WDATA_HWDATA01(23) => \VCC\, 
        F_WDATA_HWDATA01(22) => \VCC\, F_WDATA_HWDATA01(21) => 
        \VCC\, F_WDATA_HWDATA01(20) => \VCC\, 
        F_WDATA_HWDATA01(19) => \VCC\, F_WDATA_HWDATA01(18) => 
        \VCC\, F_WDATA_HWDATA01(17) => \VCC\, 
        F_WDATA_HWDATA01(16) => \VCC\, F_WDATA_HWDATA01(15) => 
        \VCC\, F_WDATA_HWDATA01(14) => \VCC\, 
        F_WDATA_HWDATA01(13) => \VCC\, F_WDATA_HWDATA01(12) => 
        \VCC\, F_WDATA_HWDATA01(11) => \VCC\, 
        F_WDATA_HWDATA01(10) => \VCC\, F_WDATA_HWDATA01(9) => 
        \VCC\, F_WDATA_HWDATA01(8) => \VCC\, F_WDATA_HWDATA01(7)
         => \VCC\, F_WDATA_HWDATA01(6) => \VCC\, 
        F_WDATA_HWDATA01(5) => \VCC\, F_WDATA_HWDATA01(4) => 
        \VCC\, F_WDATA_HWDATA01(3) => \VCC\, F_WDATA_HWDATA01(2)
         => \VCC\, F_WDATA_HWDATA01(1) => \VCC\, 
        F_WDATA_HWDATA01(0) => \VCC\, F_WID_HREADY01(3) => \GND\, 
        F_WID_HREADY01(2) => \GND\, F_WID_HREADY01(1) => \GND\, 
        F_WID_HREADY01(0) => \GND\, F_WLAST => \GND\, F_WSTRB(7)
         => \GND\, F_WSTRB(6) => \GND\, F_WSTRB(5) => \GND\, 
        F_WSTRB(4) => \GND\, F_WSTRB(3) => \GND\, F_WSTRB(2) => 
        \GND\, F_WSTRB(1) => \GND\, F_WSTRB(0) => \GND\, F_WVALID
         => \GND\, FPGA_MDDR_ARESET_N => \VCC\, 
        MDDR_FABRIC_PADDR(10) => \VCC\, MDDR_FABRIC_PADDR(9) => 
        \VCC\, MDDR_FABRIC_PADDR(8) => \VCC\, 
        MDDR_FABRIC_PADDR(7) => \VCC\, MDDR_FABRIC_PADDR(6) => 
        \VCC\, MDDR_FABRIC_PADDR(5) => \VCC\, 
        MDDR_FABRIC_PADDR(4) => \VCC\, MDDR_FABRIC_PADDR(3) => 
        \VCC\, MDDR_FABRIC_PADDR(2) => \VCC\, MDDR_FABRIC_PENABLE
         => \VCC\, MDDR_FABRIC_PSEL => \VCC\, 
        MDDR_FABRIC_PWDATA(15) => \VCC\, MDDR_FABRIC_PWDATA(14)
         => \VCC\, MDDR_FABRIC_PWDATA(13) => \VCC\, 
        MDDR_FABRIC_PWDATA(12) => \VCC\, MDDR_FABRIC_PWDATA(11)
         => \VCC\, MDDR_FABRIC_PWDATA(10) => \VCC\, 
        MDDR_FABRIC_PWDATA(9) => \VCC\, MDDR_FABRIC_PWDATA(8) => 
        \VCC\, MDDR_FABRIC_PWDATA(7) => \VCC\, 
        MDDR_FABRIC_PWDATA(6) => \VCC\, MDDR_FABRIC_PWDATA(5) => 
        \VCC\, MDDR_FABRIC_PWDATA(4) => \VCC\, 
        MDDR_FABRIC_PWDATA(3) => \VCC\, MDDR_FABRIC_PWDATA(2) => 
        \VCC\, MDDR_FABRIC_PWDATA(1) => \VCC\, 
        MDDR_FABRIC_PWDATA(0) => \VCC\, MDDR_FABRIC_PWRITE => 
        \VCC\, PRESET_N => \GND\, CAN_RXBUS_USBA_DATA1_MGPIO3A_IN
         => \GND\, CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN => \GND\, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_IN => \GND\, DM_IN(2) => 
        \GND\, DM_IN(1) => \GND\, DM_IN(0) => \GND\, 
        DRAM_DQ_IN(17) => \GND\, DRAM_DQ_IN(16) => \GND\, 
        DRAM_DQ_IN(15) => \GND\, DRAM_DQ_IN(14) => \GND\, 
        DRAM_DQ_IN(13) => \GND\, DRAM_DQ_IN(12) => \GND\, 
        DRAM_DQ_IN(11) => \GND\, DRAM_DQ_IN(10) => \GND\, 
        DRAM_DQ_IN(9) => \GND\, DRAM_DQ_IN(8) => \GND\, 
        DRAM_DQ_IN(7) => \GND\, DRAM_DQ_IN(6) => \GND\, 
        DRAM_DQ_IN(5) => \GND\, DRAM_DQ_IN(4) => \GND\, 
        DRAM_DQ_IN(3) => \GND\, DRAM_DQ_IN(2) => \GND\, 
        DRAM_DQ_IN(1) => \GND\, DRAM_DQ_IN(0) => \GND\, 
        DRAM_DQS_IN(2) => \GND\, DRAM_DQS_IN(1) => \GND\, 
        DRAM_DQS_IN(0) => \GND\, DRAM_FIFO_WE_IN(1) => \GND\, 
        DRAM_FIFO_WE_IN(0) => \GND\, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_IN => \GND\, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_IN => \GND\, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_IN => \GND\, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_IN => \GND\, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_IN => \GND\, 
        MMUART0_DCD_MGPIO22B_IN => \GND\, MMUART0_DSR_MGPIO20B_IN
         => \GND\, MMUART0_DTR_USBC_DATA6_MGPIO18B_IN => \GND\, 
        MMUART0_RI_MGPIO21B_IN => \GND\, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_IN => \GND\, 
        MMUART0_RXD_USBC_STP_MGPIO28B_IN => \GND\, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_IN => \GND\, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_IN => \GND\, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_IN => \GND\, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_IN => \GND\, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_IN => \GND\, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN => 
        USB_ULPI_XCLK_PAD_Y, RGMII_MDC_RMII_MDC_IN => \GND\, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN => 
        USB_ULPI_DATA_7_PAD_Y, RGMII_RX_CLK_IN => \GND\, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN => 
        USB_ULPI_DATA_2_PAD_Y, RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN
         => USB_ULPI_DATA_0_PAD_Y, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN => 
        USB_ULPI_DATA_1_PAD_Y, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN => 
        USB_ULPI_DATA_3_PAD_Y, RGMII_RXD3_USBB_DATA4_IN => 
        USB_ULPI_DATA_4_PAD_Y, RGMII_TX_CLK_IN => \GND\, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN => USB_ULPI_NXT_PAD_Y, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_IN => USB_ULPI_DIR_PAD_Y, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_IN => \GND\, 
        RGMII_TXD2_USBB_DATA5_IN => USB_ULPI_DATA_5_PAD_Y, 
        RGMII_TXD3_USBB_DATA6_IN => USB_ULPI_DATA_6_PAD_Y, 
        SPI0_SCK_USBA_XCLK_IN => \GND\, 
        SPI0_SDI_USBA_DIR_MGPIO5A_IN => \GND\, 
        SPI0_SDO_USBA_STP_MGPIO6A_IN => \GND\, 
        SPI0_SS0_USBA_NXT_MGPIO7A_IN => \GND\, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_IN => \GND\, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_IN => \GND\, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_IN => \GND\, SPI1_SCK_IN => 
        \GND\, SPI1_SDI_MGPIO11A_IN => \GND\, 
        SPI1_SDO_MGPIO12A_IN => \GND\, SPI1_SS0_MGPIO13A_IN => 
        \GND\, SPI1_SS1_MGPIO14A_IN => \GND\, 
        SPI1_SS2_MGPIO15A_IN => \GND\, SPI1_SS3_MGPIO16A_IN => 
        \GND\, SPI1_SS4_MGPIO17A_IN => \GND\, 
        SPI1_SS5_MGPIO18A_IN => \GND\, SPI1_SS6_MGPIO23A_IN => 
        \GND\, SPI1_SS7_MGPIO24A_IN => \GND\, USBC_XCLK_IN => 
        \GND\, CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT => 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT => 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT => 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT, DRAM_ADDR(15) => 
        DRAM_ADDR(15), DRAM_ADDR(14) => DRAM_ADDR(14), 
        DRAM_ADDR(13) => DRAM_ADDR(13), DRAM_ADDR(12) => 
        DRAM_ADDR(12), DRAM_ADDR(11) => DRAM_ADDR(11), 
        DRAM_ADDR(10) => DRAM_ADDR(10), DRAM_ADDR(9) => 
        DRAM_ADDR(9), DRAM_ADDR(8) => DRAM_ADDR(8), DRAM_ADDR(7)
         => DRAM_ADDR(7), DRAM_ADDR(6) => DRAM_ADDR(6), 
        DRAM_ADDR(5) => DRAM_ADDR(5), DRAM_ADDR(4) => 
        DRAM_ADDR(4), DRAM_ADDR(3) => DRAM_ADDR(3), DRAM_ADDR(2)
         => DRAM_ADDR(2), DRAM_ADDR(1) => DRAM_ADDR(1), 
        DRAM_ADDR(0) => DRAM_ADDR(0), DRAM_BA(2) => DRAM_BA(2), 
        DRAM_BA(1) => DRAM_BA(1), DRAM_BA(0) => DRAM_BA(0), 
        DRAM_CASN => DRAM_CASN, DRAM_CKE => DRAM_CKE, DRAM_CLK
         => DRAM_CLK, DRAM_CSN => DRAM_CSN, DRAM_DM_RDQS_OUT(2)
         => DRAM_DM_RDQS_OUT(2), DRAM_DM_RDQS_OUT(1) => 
        DRAM_DM_RDQS_OUT(1), DRAM_DM_RDQS_OUT(0) => 
        DRAM_DM_RDQS_OUT(0), DRAM_DQ_OUT(17) => DRAM_DQ_OUT(17), 
        DRAM_DQ_OUT(16) => DRAM_DQ_OUT(16), DRAM_DQ_OUT(15) => 
        DRAM_DQ_OUT(15), DRAM_DQ_OUT(14) => DRAM_DQ_OUT(14), 
        DRAM_DQ_OUT(13) => DRAM_DQ_OUT(13), DRAM_DQ_OUT(12) => 
        DRAM_DQ_OUT(12), DRAM_DQ_OUT(11) => DRAM_DQ_OUT(11), 
        DRAM_DQ_OUT(10) => DRAM_DQ_OUT(10), DRAM_DQ_OUT(9) => 
        DRAM_DQ_OUT(9), DRAM_DQ_OUT(8) => DRAM_DQ_OUT(8), 
        DRAM_DQ_OUT(7) => DRAM_DQ_OUT(7), DRAM_DQ_OUT(6) => 
        DRAM_DQ_OUT(6), DRAM_DQ_OUT(5) => DRAM_DQ_OUT(5), 
        DRAM_DQ_OUT(4) => DRAM_DQ_OUT(4), DRAM_DQ_OUT(3) => 
        DRAM_DQ_OUT(3), DRAM_DQ_OUT(2) => DRAM_DQ_OUT(2), 
        DRAM_DQ_OUT(1) => DRAM_DQ_OUT(1), DRAM_DQ_OUT(0) => 
        DRAM_DQ_OUT(0), DRAM_DQS_OUT(2) => DRAM_DQS_OUT(2), 
        DRAM_DQS_OUT(1) => DRAM_DQS_OUT(1), DRAM_DQS_OUT(0) => 
        DRAM_DQS_OUT(0), DRAM_FIFO_WE_OUT(1) => 
        DRAM_FIFO_WE_OUT(1), DRAM_FIFO_WE_OUT(0) => 
        DRAM_FIFO_WE_OUT(0), DRAM_ODT => DRAM_ODT, DRAM_RASN => 
        DRAM_RASN, DRAM_RSTN => DRAM_RSTN, DRAM_WEN => DRAM_WEN, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OUT => 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OUT, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT => 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT => 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT => 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT => 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT, 
        MMUART0_DCD_MGPIO22B_OUT => MMUART0_DCD_MGPIO22B_OUT, 
        MMUART0_DSR_MGPIO20B_OUT => MMUART0_DSR_MGPIO20B_OUT, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT => 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT, 
        MMUART0_RI_MGPIO21B_OUT => MMUART0_RI_MGPIO21B_OUT, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT => 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT => 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT => 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT => 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT => 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT => 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT => 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT => 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT, 
        RGMII_MDC_RMII_MDC_OUT => RGMII_MDC_RMII_MDC_OUT, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT => 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT, 
        RGMII_RX_CLK_OUT => RGMII_RX_CLK_OUT, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT => 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT, 
        RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT => 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT => 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT => 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT, 
        RGMII_RXD3_USBB_DATA4_OUT => 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT, 
        RGMII_TX_CLK_OUT => RGMII_TX_CLK_OUT, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT => 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT => 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_OUT => 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT, 
        RGMII_TXD2_USBB_DATA5_OUT => 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT, 
        RGMII_TXD3_USBB_DATA6_OUT => 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT, 
        SPI0_SCK_USBA_XCLK_OUT => SPI0_SCK_USBA_XCLK_OUT, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OUT => 
        SPI0_SDI_USBA_DIR_MGPIO5A_OUT, 
        SPI0_SDO_USBA_STP_MGPIO6A_OUT => 
        SPI0_SDO_USBA_STP_MGPIO6A_OUT, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT => 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT => 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT => 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT => 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT, SPI1_SCK_OUT => 
        SPI1_SCK_OUT, SPI1_SDI_MGPIO11A_OUT => 
        SPI1_SDI_MGPIO11A_OUT, SPI1_SDO_MGPIO12A_OUT => 
        SPI1_SDO_MGPIO12A_OUT, SPI1_SS0_MGPIO13A_OUT => 
        SPI1_SS0_MGPIO13A_OUT, SPI1_SS1_MGPIO14A_OUT => 
        SPI1_SS1_MGPIO14A_OUT, SPI1_SS2_MGPIO15A_OUT => 
        SPI1_SS2_MGPIO15A_OUT, SPI1_SS3_MGPIO16A_OUT => 
        SPI1_SS3_MGPIO16A_OUT, SPI1_SS4_MGPIO17A_OUT => 
        SPI1_SS4_MGPIO17A_OUT, SPI1_SS5_MGPIO18A_OUT => 
        SPI1_SS5_MGPIO18A_OUT, SPI1_SS6_MGPIO23A_OUT => 
        SPI1_SS6_MGPIO23A_OUT, SPI1_SS7_MGPIO24A_OUT => 
        SPI1_SS7_MGPIO24A_OUT, USBC_XCLK_OUT => USBC_XCLK_OUT, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE => 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE => 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE => 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE, DM_OE(2) => DM_OE(2), 
        DM_OE(1) => DM_OE(1), DM_OE(0) => DM_OE(0), 
        DRAM_DQ_OE(17) => DRAM_DQ_OE(17), DRAM_DQ_OE(16) => 
        DRAM_DQ_OE(16), DRAM_DQ_OE(15) => DRAM_DQ_OE(15), 
        DRAM_DQ_OE(14) => DRAM_DQ_OE(14), DRAM_DQ_OE(13) => 
        DRAM_DQ_OE(13), DRAM_DQ_OE(12) => DRAM_DQ_OE(12), 
        DRAM_DQ_OE(11) => DRAM_DQ_OE(11), DRAM_DQ_OE(10) => 
        DRAM_DQ_OE(10), DRAM_DQ_OE(9) => DRAM_DQ_OE(9), 
        DRAM_DQ_OE(8) => DRAM_DQ_OE(8), DRAM_DQ_OE(7) => 
        DRAM_DQ_OE(7), DRAM_DQ_OE(6) => DRAM_DQ_OE(6), 
        DRAM_DQ_OE(5) => DRAM_DQ_OE(5), DRAM_DQ_OE(4) => 
        DRAM_DQ_OE(4), DRAM_DQ_OE(3) => DRAM_DQ_OE(3), 
        DRAM_DQ_OE(2) => DRAM_DQ_OE(2), DRAM_DQ_OE(1) => 
        DRAM_DQ_OE(1), DRAM_DQ_OE(0) => DRAM_DQ_OE(0), 
        DRAM_DQS_OE(2) => DRAM_DQS_OE(2), DRAM_DQS_OE(1) => 
        DRAM_DQS_OE(1), DRAM_DQS_OE(0) => DRAM_DQS_OE(0), 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE => 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE => 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE => 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE => 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE => 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE, 
        MMUART0_DCD_MGPIO22B_OE => MMUART0_DCD_MGPIO22B_OE, 
        MMUART0_DSR_MGPIO20B_OE => MMUART0_DSR_MGPIO20B_OE, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OE => 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OE, 
        MMUART0_RI_MGPIO21B_OE => MMUART0_RI_MGPIO21B_OE, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE => 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE => 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE => 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE => 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE => 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE => 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE => 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE => 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE, 
        RGMII_MDC_RMII_MDC_OE => RGMII_MDC_RMII_MDC_OE, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE => 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE, 
        RGMII_RX_CLK_OE => RGMII_RX_CLK_OE, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE => 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE, 
        RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE => 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE => 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE => 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE, 
        RGMII_RXD3_USBB_DATA4_OE => 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE, RGMII_TX_CLK_OE
         => RGMII_TX_CLK_OE, RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE
         => RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE => 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_OE => 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE, 
        RGMII_TXD2_USBB_DATA5_OE => 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE, 
        RGMII_TXD3_USBB_DATA6_OE => 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE, 
        SPI0_SCK_USBA_XCLK_OE => SPI0_SCK_USBA_XCLK_OE, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OE => 
        SPI0_SDI_USBA_DIR_MGPIO5A_OE, 
        SPI0_SDO_USBA_STP_MGPIO6A_OE => 
        SPI0_SDO_USBA_STP_MGPIO6A_OE, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE => 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OE => 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OE, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE => 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE => 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE, SPI1_SCK_OE => 
        SPI1_SCK_OE, SPI1_SDI_MGPIO11A_OE => SPI1_SDI_MGPIO11A_OE, 
        SPI1_SDO_MGPIO12A_OE => SPI1_SDO_MGPIO12A_OE, 
        SPI1_SS0_MGPIO13A_OE => SPI1_SS0_MGPIO13A_OE, 
        SPI1_SS1_MGPIO14A_OE => SPI1_SS1_MGPIO14A_OE, 
        SPI1_SS2_MGPIO15A_OE => SPI1_SS2_MGPIO15A_OE, 
        SPI1_SS3_MGPIO16A_OE => SPI1_SS3_MGPIO16A_OE, 
        SPI1_SS4_MGPIO17A_OE => SPI1_SS4_MGPIO17A_OE, 
        SPI1_SS5_MGPIO18A_OE => SPI1_SS5_MGPIO18A_OE, 
        SPI1_SS6_MGPIO23A_OE => SPI1_SS6_MGPIO23A_OE, 
        SPI1_SS7_MGPIO24A_OE => SPI1_SS7_MGPIO24A_OE, 
        USBC_XCLK_OE => USBC_XCLK_OE);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    USB_ULPI_DATA_0_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(0), D => 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT, E => 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE, Y => 
        USB_ULPI_DATA_0_PAD_Y);
    
    USB_ULPI_DATA_1_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(1), D => 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT, E => 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE, Y => 
        USB_ULPI_DATA_1_PAD_Y);
    
    USB_ULPI_STP_PAD : TRIBUFF
      generic map(IOSTD => "")

      port map(D => 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT, E => 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE, PAD => 
        USB_ULPI_STP);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_sb is

    port( prdata_o_1_2_0_a2_11_0                 : in    std_logic_vector(1 to 1);
          prdata_o_1_2_0_a2_12_0                 : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_26_0              : in    std_logic_vector(1 to 1);
          prdata_o_1_2_0_0_2                     : in    std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_0                     : in    std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_1                     : in    std_logic_vector(2 to 2);
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI      : in    std_logic_vector(0 to 0);
          prdata_o_1_2_0_a2_17_0                 : in    std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_a2_20_0              : in    std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_a2_24_0              : in    std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_0_0_0                : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1_6_tz               : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1                    : in    std_logic_vector(7 to 7);
          prdata_o_1_0_iv_0_0                    : in    std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_0_2_tz_tz            : in    std_logic_vector(0 to 0);
          prdata_o_1_iv_0_0_4_2_1_0              : in    std_logic_vector(3 to 3);
          SPEED_ID_IQ_PI_1_id_pi_output_o        : in    std_logic_vector(1 downto 0);
          SPEED_ID_IQ_PI_1_iq_pi_output_o        : in    std_logic_vector(1 downto 0);
          prdata_o_1_2_0_0_4_2                   : in    std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_5_0               : in    std_logic_vector(3 to 3);
          STEPPER_THETA_0_theta_output_o         : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_a2_45_0              : in    std_logic_vector(0 to 0);
          adc_measurements_0_adc_result_ch3_o    : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_14_1              : in    std_logic_vector(1 to 1);
          SEQ_CONTROLLER_1_state_o_0             : in    std_logic_vector(1 to 1);
          SEQ_CONTROLLER_1_state_o_2             : in    std_logic;
          SEQ_CONTROLLER_1_state_o_0_d0          : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_1               : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_4               : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_0               : in    std_logic;
          prdata_o_1_0_iv_0_12_1                 : in    std_logic_vector(7 to 7);
          prdata_o_1_0_iv_0_12_4                 : in    std_logic_vector(8 to 8);
          prdata_o_1_0_iv_0_a2_19_0              : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1_1                  : in    std_logic_vector(10 to 10);
          FOC_TRANSFORMS_1_valpha_o_0            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_5            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_8            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_9            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_4            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_7            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_10           : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_6            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_11           : in    std_logic;
          STEPPER_THETA_1_step_count_o_17        : in    std_logic;
          STEPPER_THETA_1_step_count_o_3         : in    std_logic;
          STEPPER_THETA_1_step_count_o_6         : in    std_logic;
          STEPPER_THETA_1_step_count_o_9         : in    std_logic;
          STEPPER_THETA_1_step_count_o_0         : in    std_logic;
          STEPPER_THETA_1_step_count_o_5         : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_3             : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_0             : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_5             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_0             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_3             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_5             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_8             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_12            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_15            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_7             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_10            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_2             : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_0                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_1                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_5                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_8                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_12               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_15               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_7                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_10               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_6                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_11               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_2                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_1                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_4                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_0_d0             : in    std_logic;
          prdata_o_1_0_iv_0_0_0_2                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_7                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_5                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_0                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_5                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_8                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_9                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_7                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_10               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_12               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_15               : in    std_logic;
          prdata_o_1_0_iv_0_3_0                  : in    std_logic;
          prdata_o_1_0_iv_0_3_3                  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_0  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_5  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_8  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_10 : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_1  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_9  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_7  : in    std_logic;
          adc_interface_0_result_ch0_o_6         : in    std_logic;
          adc_interface_0_result_ch0_o_11        : in    std_logic;
          adc_interface_0_result_ch0_o_7         : in    std_logic;
          adc_interface_0_result_ch0_o_0         : in    std_logic;
          adc_interface_0_result_ch0_o_5         : in    std_logic;
          adc_interface_0_result_ch0_o_8         : in    std_logic;
          adc_interface_0_result_ch0_o_9         : in    std_logic;
          ADC_SCALING_0_ia_adc_o_0               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_7               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_10              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_2               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_5               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_8               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_9               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_12              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_15              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_4               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_1               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_6               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_11              : in    std_logic;
          prdata_o_1_0_iv_0_1_o2_0               : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_11                   : in    std_logic_vector(3 to 3);
          prdata_o_1_2_0_0_5                     : in    std_logic_vector(3 to 3);
          ADC_SCALING_0_ib_adc_o_10              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_5               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_4               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_7               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_8               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_11              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_14              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_3               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_0               : in    std_logic;
          prdata_o_1_iv_0_0_0_3_tz               : in    std_logic_vector(1 to 1);
          prdata_o_1_0_1                         : in    std_logic_vector(16 to 16);
          prdata_o_1_0_2                         : in    std_logic_vector(16 to 16);
          prdata_o_1_0_0                         : in    std_logic_vector(16 to 16);
          prdata_o_1_3_0_0_2                     : in    std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_3                     : in    std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_0                     : in    std_logic_vector(11 to 11);
          prdata_o_1_8_2                         : in    std_logic_vector(6 to 6);
          prdata_o_1_8_3                         : in    std_logic_vector(6 to 6);
          prdata_o_1_8_0                         : in    std_logic_vector(6 to 6);
          prdata_o_1_iv_0_0_12_4_3               : in    std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_4_2               : in    std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_5_1                  : in    std_logic;
          prdata_o_1_0_iv_0_5_4                  : in    std_logic;
          prdata_o_1_0_iv_0_5_2                  : in    std_logic;
          prdata_o_1_0_iv_0_5_7                  : in    std_logic;
          prdata_o_1_0_iv_0_5_5                  : in    std_logic;
          prdata_o_1_0_iv_0_5_0                  : in    std_logic;
          prdata_o_1_0_iv_0_5_12                 : in    std_logic;
          prdata_o_1_0_iv_0_6                    : in    std_logic_vector(16 to 16);
          MC_System_0_AMBA_SLAVE_1_PRDATA        : in    std_logic_vector(14 downto 13);
          MC_System_0_AMBA_SLAVE_0_PRDATA_0      : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_15     : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_12     : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_13     : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_14     : in    std_logic;
          USB_ULPI_DATA                          : inout std_logic_vector(7 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_1_PADDR         : inout std_logic_vector(11 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_1_PWDATA        : out   std_logic_vector(23 downto 0);
          MC_System_0_FIC_0_LOCK                 : out   std_logic;
          MC_System_0_FIC_0_CLK                  : out   std_logic;
          MC_System_0_FAB_CCC_GL1                : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx         : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx         : out   std_logic;
          N_1342                                 : in    std_logic;
          N_2598                                 : in    std_logic;
          N_2644                                 : in    std_logic;
          N_1396                                 : in    std_logic;
          N_2631                                 : in    std_logic;
          prdata_m2_e_1_1                        : in    std_logic;
          N_1360                                 : in    std_logic;
          N_1288                                 : in    std_logic;
          prdata_m1_0_a2_0                       : in    std_logic;
          N_522                                  : in    std_logic;
          N_527                                  : in    std_logic;
          N_542                                  : in    std_logic;
          prdata_m4_e_0                          : in    std_logic;
          prdata_m1_0_a2_2_0                     : in    std_logic;
          N_509                                  : in    std_logic;
          N_529                                  : in    std_logic;
          N_503                                  : in    std_logic;
          prdata_m2_e_0                          : in    std_logic;
          N_508                                  : in    std_logic;
          N_2652                                 : in    std_logic;
          N_768                                  : in    std_logic;
          N_1345                                 : in    std_logic;
          N_2647                                 : in    std_logic;
          N_2531                                 : in    std_logic;
          N_513                                  : in    std_logic;
          N_502                                  : in    std_logic;
          N_534                                  : in    std_logic;
          N_500                                  : in    std_logic;
          N_514                                  : in    std_logic;
          N_506                                  : in    std_logic;
          N_505                                  : in    std_logic;
          N_518                                  : in    std_logic;
          N_2574                                 : in    std_logic;
          N_1346                                 : in    std_logic;
          N_531                                  : in    std_logic;
          N_2640                                 : in    std_logic;
          N_738                                  : in    std_logic;
          N_533                                  : in    std_logic;
          N_507                                  : in    std_logic;
          prdata_m1_e_0_1                        : in    std_logic;
          N_1398                                 : in    std_logic;
          N_1378                                 : in    std_logic;
          N_2627                                 : in    std_logic;
          prdata_m2_0_a2_0                       : in    std_logic;
          N_455                                  : in    std_logic;
          N_495                                  : in    std_logic;
          N_892                                  : in    std_logic;
          N_771                                  : in    std_logic;
          N_773                                  : in    std_logic;
          N_750                                  : in    std_logic;
          N_2639                                 : in    std_logic;
          N_775                                  : in    std_logic;
          N_763                                  : in    std_logic;
          N_2645                                 : in    std_logic;
          N_1351                                 : in    std_logic;
          N_1169                                 : in    std_logic;
          N_1279                                 : in    std_logic;
          N_793                                  : in    std_logic;
          N_791                                  : in    std_logic;
          N_782                                  : in    std_logic;
          N_893                                  : in    std_logic;
          N_788                                  : in    std_logic;
          N_772                                  : in    std_logic;
          N_749                                  : in    std_logic;
          N_774                                  : in    std_logic;
          N_762                                  : in    std_logic;
          N_1347                                 : in    std_logic;
          N_1165                                 : in    std_logic;
          N_1275                                 : in    std_logic;
          N_792                                  : in    std_logic;
          N_878                                  : in    std_logic;
          N_859                                  : in    std_logic;
          N_880                                  : in    std_logic;
          N_870                                  : in    std_logic;
          prdata_m2_e_0_0                        : in    std_logic;
          prdata_m1_e_11_0                       : in    std_logic;
          N_414                                  : in    std_logic;
          N_516                                  : in    std_logic;
          N_397                                  : in    std_logic;
          N_355                                  : in    std_logic;
          N_198                                  : in    std_logic;
          m20_i_2_tz                             : in    std_logic;
          m20_i_a2_0_1                           : in    std_logic;
          m20_m2_0_a2_1                          : in    std_logic;
          N_349                                  : in    std_logic;
          m20_i_a2_5_0                           : in    std_logic;
          N_517                                  : in    std_logic;
          N_128                                  : in    std_logic;
          N_528                                  : in    std_logic;
          N_524                                  : in    std_logic;
          N_454                                  : in    std_logic;
          N_494                                  : in    std_logic;
          N_894                                  : in    std_logic;
          N_1326                                 : in    std_logic;
          N_2646                                 : in    std_logic;
          N_770                                  : in    std_logic;
          N_777                                  : in    std_logic;
          N_883                                  : in    std_logic;
          N_1333                                 : in    std_logic;
          N_790                                  : in    std_logic;
          N_895                                  : in    std_logic;
          N_769                                  : in    std_logic;
          N_776                                  : in    std_logic;
          N_832                                  : in    std_logic;
          N_1329                                 : in    std_logic;
          N_789                                  : in    std_logic;
          N_876                                  : in    std_logic;
          N_882                                  : in    std_logic;
          prdata_m3_i_0                          : in    std_logic;
          N_260                                  : in    std_logic;
          N_766                                  : in    std_logic;
          N_739                                  : in    std_logic;
          N_891                                  : in    std_logic;
          N_767                                  : in    std_logic;
          N_875                                  : in    std_logic;
          N_396                                  : in    std_logic;
          N_405                                  : in    std_logic;
          N_354                                  : in    std_logic;
          N_363                                  : in    std_logic;
          prdata_N_7_2                           : in    std_logic;
          m20_i_10_1                             : in    std_logic;
          m20_i_10_0                             : in    std_logic;
          N_215                                  : in    std_logic;
          N_377                                  : in    std_logic;
          N_2495                                 : in    std_logic;
          N_2498                                 : in    std_logic;
          m20_i_11_5                             : in    std_logic;
          N_122                                  : in    std_logic;
          N_317                                  : in    std_logic;
          N_318                                  : in    std_logic;
          N_319                                  : in    std_logic;
          N_320                                  : in    std_logic;
          N_321                                  : in    std_logic;
          N_315                                  : in    std_logic;
          USB_ULPI_XCLK                          : in    std_logic;
          USB_ULPI_STP                           : out   std_logic;
          USB_ULPI_NXT                           : in    std_logic;
          USB_ULPI_DIR                           : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PENABLE       : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE        : out   std_logic;
          GPIO_0_M2F_c                           : out   std_logic
        );

end MC_System_sb;

architecture DEF_ARCH of MC_System_sb is 

  component MC_System_sb_FABOSC_0_OSC
    port( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : out   std_logic
        );
  end component;

  component CoreAPB3
    port( MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : in    std_logic_vector(15 downto 12) := (others => 'U');
          prdata_o_1_2_0_a2_11_0                            : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_2_0_a2_12_0                            : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_26_0                         : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_2_0_0_2                                : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_2_0_0_0                                : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_2_0_0_1                                : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI                 : in    std_logic_vector(0 to 0) := (others => 'U');
          prdata_o_1_2_0_a2_17_0                            : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_iv_0_a2_20_0                         : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_iv_0_0_a2_24_0                         : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_iv_0_0_0_0                           : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1_6_tz                          : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1                               : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_0_iv_0_0                               : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_iv_0_0_0_2_tz_tz                       : in    std_logic_vector(0 to 0) := (others => 'U');
          prdata_o_1_iv_0_0_4_2_1_0                         : in    std_logic_vector(3 to 3) := (others => 'U');
          SPEED_ID_IQ_PI_1_id_pi_output_o                   : in    std_logic_vector(1 downto 0) := (others => 'U');
          SPEED_ID_IQ_PI_1_iq_pi_output_o                   : in    std_logic_vector(1 downto 0) := (others => 'U');
          prdata_o_1_2_0_0_4_2                              : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_iv_0_0_12_5_0                          : in    std_logic_vector(3 to 3) := (others => 'U');
          STEPPER_THETA_0_theta_output_o                    : in    std_logic_vector(17 to 17) := (others => 'U');
          MC_System_0_AMBA_SLAVE_1_PADDR_3                  : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PADDR_2                  : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PADDR_1                  : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PADDR_8                  : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PADDR_0                  : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a2_45_0                         : in    std_logic_vector(0 to 0) := (others => 'U');
          adc_measurements_0_adc_result_ch3_o               : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_14_1                         : in    std_logic_vector(1 to 1) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_0                        : in    std_logic_vector(1 to 1) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_2                        : in    std_logic := 'U';
          SEQ_CONTROLLER_1_state_o_0_d0                     : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_1                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_4                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_0                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_12_1                            : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_0_iv_0_12_4                            : in    std_logic_vector(8 to 8) := (others => 'U');
          prdata_o_1_0_iv_0_a2_19_0                         : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1_1                             : in    std_logic_vector(10 to 10) := (others => 'U');
          FOC_TRANSFORMS_1_valpha_o_0                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_5                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_8                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_9                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_4                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_7                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_10                      : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_6                       : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_11                      : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_17                   : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_3                    : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_6                    : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_9                    : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_0                    : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_5                    : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_3                        : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_0                        : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_5                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_0                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_3                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_5                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_8                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_12                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_15                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_7                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_10                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_2                        : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_0                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_1                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_5                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_8                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_12                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_15                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_7                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_10                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_6                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_11                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_2                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_1                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_4                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_0_d0                        : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_2                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_7                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_5                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_0                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_5                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_8                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_9                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_7                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_10                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_12                          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_15                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_3_0                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_3_3                             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_0             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_5             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_8             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_10            : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_1             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_9             : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_7             : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_6                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_11                   : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_7                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_0                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_5                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_8                    : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_9                    : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_0                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_7                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_10                         : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_2                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_5                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_8                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_9                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_12                         : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_15                         : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_4                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_1                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_6                          : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_11                         : in    std_logic := 'U';
          prdata_o_1_0_iv_0_1_o2_0                          : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_11                              : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_2_0_0_5                                : in    std_logic_vector(3 to 3) := (others => 'U');
          ADC_SCALING_0_ib_adc_o_10                         : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_5                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_4                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_7                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_8                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_11                         : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_14                         : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_3                          : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_0                          : in    std_logic := 'U';
          prdata_o_1_iv_0_0_0_3_tz                          : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_1                                    : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_2                                    : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_0                                    : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_3_0_0_2                                : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_3_0_0_3                                : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_3_0_0_0                                : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_8_2                                    : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_8_3                                    : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_8_0                                    : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_iv_0_0_12_4_3                          : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_iv_0_0_12_4_2                          : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_0_iv_0_5_1                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_4                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_2                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_7                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_5                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_0                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_12                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6                               : in    std_logic_vector(16 to 16) := (others => 'U');
          MC_System_0_AMBA_SLAVE_1_PRDATA                   : in    std_logic_vector(14 downto 13) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA_0                 : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_15                : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_12                : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_13                : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_14                : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PSELx                    : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx                    : out   std_logic;
          N_1342                                            : in    std_logic := 'U';
          N_2598                                            : in    std_logic := 'U';
          N_2644                                            : in    std_logic := 'U';
          N_1396                                            : in    std_logic := 'U';
          N_2631                                            : in    std_logic := 'U';
          prdata_m2_e_1_1                                   : in    std_logic := 'U';
          N_1360                                            : in    std_logic := 'U';
          N_1288                                            : in    std_logic := 'U';
          prdata_m1_0_a2_0                                  : in    std_logic := 'U';
          N_522                                             : in    std_logic := 'U';
          N_527                                             : in    std_logic := 'U';
          N_542                                             : in    std_logic := 'U';
          prdata_m4_e_0                                     : in    std_logic := 'U';
          prdata_m1_0_a2_2_0                                : in    std_logic := 'U';
          N_509                                             : in    std_logic := 'U';
          N_529                                             : in    std_logic := 'U';
          N_503                                             : in    std_logic := 'U';
          prdata_m2_e_0                                     : in    std_logic := 'U';
          N_508                                             : in    std_logic := 'U';
          N_2652                                            : in    std_logic := 'U';
          N_768                                             : in    std_logic := 'U';
          N_1345                                            : in    std_logic := 'U';
          N_2647                                            : in    std_logic := 'U';
          N_2531                                            : in    std_logic := 'U';
          N_513                                             : in    std_logic := 'U';
          N_502                                             : in    std_logic := 'U';
          N_534                                             : in    std_logic := 'U';
          N_500                                             : in    std_logic := 'U';
          N_514                                             : in    std_logic := 'U';
          N_506                                             : in    std_logic := 'U';
          N_505                                             : in    std_logic := 'U';
          N_518                                             : in    std_logic := 'U';
          N_2574                                            : in    std_logic := 'U';
          N_1346                                            : in    std_logic := 'U';
          N_531                                             : in    std_logic := 'U';
          N_2640                                            : in    std_logic := 'U';
          N_738                                             : in    std_logic := 'U';
          N_533                                             : in    std_logic := 'U';
          N_507                                             : in    std_logic := 'U';
          prdata_m1_e_0_1                                   : in    std_logic := 'U';
          N_1398                                            : in    std_logic := 'U';
          N_1378                                            : in    std_logic := 'U';
          N_2627                                            : in    std_logic := 'U';
          prdata_m2_0_a2_0                                  : in    std_logic := 'U';
          N_455                                             : in    std_logic := 'U';
          N_495                                             : in    std_logic := 'U';
          N_892                                             : in    std_logic := 'U';
          N_771                                             : in    std_logic := 'U';
          N_773                                             : in    std_logic := 'U';
          N_750                                             : in    std_logic := 'U';
          N_2639                                            : in    std_logic := 'U';
          N_775                                             : in    std_logic := 'U';
          N_763                                             : in    std_logic := 'U';
          N_2645                                            : in    std_logic := 'U';
          N_1351                                            : in    std_logic := 'U';
          N_1169                                            : in    std_logic := 'U';
          N_1279                                            : in    std_logic := 'U';
          N_793                                             : in    std_logic := 'U';
          N_791                                             : in    std_logic := 'U';
          N_782                                             : in    std_logic := 'U';
          N_893                                             : in    std_logic := 'U';
          N_788                                             : in    std_logic := 'U';
          N_772                                             : in    std_logic := 'U';
          N_749                                             : in    std_logic := 'U';
          N_774                                             : in    std_logic := 'U';
          N_762                                             : in    std_logic := 'U';
          N_1347                                            : in    std_logic := 'U';
          N_1165                                            : in    std_logic := 'U';
          N_1275                                            : in    std_logic := 'U';
          N_792                                             : in    std_logic := 'U';
          N_878                                             : in    std_logic := 'U';
          N_859                                             : in    std_logic := 'U';
          N_880                                             : in    std_logic := 'U';
          N_870                                             : in    std_logic := 'U';
          prdata_m2_e_0_0                                   : in    std_logic := 'U';
          prdata_m1_e_11_0                                  : in    std_logic := 'U';
          N_414                                             : in    std_logic := 'U';
          N_516                                             : in    std_logic := 'U';
          N_397                                             : in    std_logic := 'U';
          N_355                                             : in    std_logic := 'U';
          N_198                                             : in    std_logic := 'U';
          m20_i_2_tz                                        : in    std_logic := 'U';
          m20_i_a2_0_1                                      : in    std_logic := 'U';
          m20_m2_0_a2_1                                     : in    std_logic := 'U';
          N_349                                             : in    std_logic := 'U';
          m20_i_a2_5_0                                      : in    std_logic := 'U';
          N_517                                             : in    std_logic := 'U';
          N_128                                             : in    std_logic := 'U';
          N_528                                             : in    std_logic := 'U';
          N_524                                             : in    std_logic := 'U';
          N_454                                             : in    std_logic := 'U';
          N_494                                             : in    std_logic := 'U';
          N_894                                             : in    std_logic := 'U';
          N_1326                                            : in    std_logic := 'U';
          N_2646                                            : in    std_logic := 'U';
          N_770                                             : in    std_logic := 'U';
          N_777                                             : in    std_logic := 'U';
          N_883                                             : in    std_logic := 'U';
          N_1333                                            : in    std_logic := 'U';
          N_790                                             : in    std_logic := 'U';
          N_895                                             : in    std_logic := 'U';
          N_769                                             : in    std_logic := 'U';
          N_776                                             : in    std_logic := 'U';
          N_832                                             : in    std_logic := 'U';
          N_1329                                            : in    std_logic := 'U';
          N_789                                             : in    std_logic := 'U';
          N_876                                             : in    std_logic := 'U';
          N_882                                             : in    std_logic := 'U';
          prdata_m3_i_0                                     : in    std_logic := 'U';
          N_260                                             : in    std_logic := 'U';
          N_766                                             : in    std_logic := 'U';
          N_739                                             : in    std_logic := 'U';
          N_891                                             : in    std_logic := 'U';
          N_767                                             : in    std_logic := 'U';
          N_875                                             : in    std_logic := 'U';
          N_396                                             : in    std_logic := 'U';
          N_405                                             : in    std_logic := 'U';
          N_354                                             : in    std_logic := 'U';
          N_363                                             : in    std_logic := 'U';
          prdata_N_7_2                                      : in    std_logic := 'U';
          m20_i_10_1                                        : in    std_logic := 'U';
          m20_i_10_0                                        : in    std_logic := 'U';
          N_215                                             : in    std_logic := 'U';
          N_377                                             : in    std_logic := 'U';
          N_2495                                            : in    std_logic := 'U';
          N_2498                                            : in    std_logic := 'U';
          m20_i_11_5                                        : in    std_logic := 'U';
          N_122                                             : in    std_logic := 'U';
          N_317                                             : in    std_logic := 'U';
          N_318                                             : in    std_logic := 'U';
          N_319                                             : in    std_logic := 'U';
          N_320                                             : in    std_logic := 'U';
          N_321                                             : in    std_logic := 'U';
          N_315                                             : in    std_logic := 'U';
          PRDATA_N_3_mux_i_0                                : out   std_logic
        );
  end component;

  component MC_System_sb_CCC_0_FCCC
    port( MC_System_0_FIC_0_LOCK                             : out   std_logic;
          MC_System_0_FIC_0_CLK                              : out   std_logic;
          MC_System_0_FAB_CCC_GL1                            : out   std_logic;
          FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MC_System_sb_MSS
    port( USB_ULPI_DATA                                     : inout   std_logic_vector(7 downto 0);
          MC_System_0_AMBA_SLAVE_1_PADDR                    : out   std_logic_vector(11 downto 0);
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : out   std_logic_vector(15 downto 12);
          MC_System_0_AMBA_SLAVE_1_PWDATA                   : out   std_logic_vector(23 downto 0);
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : in    std_logic := 'U';
          USB_ULPI_XCLK                                     : in    std_logic := 'U';
          USB_ULPI_STP                                      : out   std_logic;
          USB_ULPI_NXT                                      : in    std_logic := 'U';
          USB_ULPI_DIR                                      : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PENABLE                  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE                   : out   std_logic;
          GPIO_0_M2F_c                                      : out   std_logic;
          PRDATA_N_3_mux_i_0                                : in    std_logic := 'U';
          MC_System_0_FIC_0_LOCK                            : in    std_logic := 'U';
          MC_System_0_FIC_0_CLK                             : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \MC_System_0_FIC_0_LOCK\, \MC_System_0_FIC_0_CLK\
         : std_logic;
    signal MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR : 
        std_logic_vector(15 downto 12);
    signal MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA : 
        std_logic_vector(31 downto 0);
    signal FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, 
        PRDATA_N_3_mux_i_0, \GND\, \VCC\ : std_logic;

    for all : MC_System_sb_FABOSC_0_OSC
	Use entity work.MC_System_sb_FABOSC_0_OSC(DEF_ARCH);
    for all : CoreAPB3
	Use entity work.CoreAPB3(DEF_ARCH);
    for all : MC_System_sb_CCC_0_FCCC
	Use entity work.MC_System_sb_CCC_0_FCCC(DEF_ARCH);
    for all : MC_System_sb_MSS
	Use entity work.MC_System_sb_MSS(DEF_ARCH);
begin 

    MC_System_0_FIC_0_LOCK <= \MC_System_0_FIC_0_LOCK\;
    MC_System_0_FIC_0_CLK <= \MC_System_0_FIC_0_CLK\;

    FABOSC_0 : MC_System_sb_FABOSC_0_OSC
      port map(FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
         => FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    CoreAPB3_0 : CoreAPB3
      port map(MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15)
         => MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), 
        prdata_o_1_2_0_a2_11_0(1) => prdata_o_1_2_0_a2_11_0(1), 
        prdata_o_1_2_0_a2_12_0(1) => prdata_o_1_2_0_a2_12_0(1), 
        prdata_o_1_iv_0_0_a2_26_0(1) => 
        prdata_o_1_iv_0_0_a2_26_0(1), prdata_o_1_2_0_0_2(2) => 
        prdata_o_1_2_0_0_2(2), prdata_o_1_2_0_0_0(2) => 
        prdata_o_1_2_0_0_0(2), prdata_o_1_2_0_0_1(2) => 
        prdata_o_1_2_0_0_1(2), 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0) => 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0), 
        prdata_o_1_2_0_a2_17_0(1) => prdata_o_1_2_0_a2_17_0(1), 
        prdata_o_1_0_iv_0_a2_20_0(10) => 
        prdata_o_1_0_iv_0_a2_20_0(10), 
        prdata_o_1_iv_0_0_a2_24_0(1) => 
        prdata_o_1_iv_0_0_a2_24_0(1), prdata_o_1_0_iv_0_0_0_0(10)
         => prdata_o_1_0_iv_0_0_0_0(10), 
        prdata_o_1_0_iv_0_1_6_tz(10) => 
        prdata_o_1_0_iv_0_1_6_tz(10), prdata_o_1_0_iv_0_1(7) => 
        prdata_o_1_0_iv_0_1(7), prdata_o_1_0_iv_0_0(7) => 
        prdata_o_1_0_iv_0_0(7), prdata_o_1_iv_0_0_0_2_tz_tz(0)
         => prdata_o_1_iv_0_0_0_2_tz_tz(0), 
        prdata_o_1_iv_0_0_4_2_1_0(3) => 
        prdata_o_1_iv_0_0_4_2_1_0(3), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0), 
        prdata_o_1_2_0_0_4_2(3) => prdata_o_1_2_0_0_4_2(3), 
        prdata_o_1_iv_0_0_12_5_0(3) => 
        prdata_o_1_iv_0_0_12_5_0(3), 
        STEPPER_THETA_0_theta_output_o(17) => 
        STEPPER_THETA_0_theta_output_o(17), 
        MC_System_0_AMBA_SLAVE_1_PADDR_3 => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        MC_System_0_AMBA_SLAVE_1_PADDR_2 => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        MC_System_0_AMBA_SLAVE_1_PADDR_1 => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR_8 => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        MC_System_0_AMBA_SLAVE_1_PADDR_0 => 
        MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        prdata_o_1_iv_0_0_a2_45_0(0) => 
        prdata_o_1_iv_0_0_a2_45_0(0), 
        adc_measurements_0_adc_result_ch3_o(1) => 
        adc_measurements_0_adc_result_ch3_o(1), 
        prdata_o_1_iv_0_0_a2_14_1(1) => 
        prdata_o_1_iv_0_0_a2_14_1(1), 
        SEQ_CONTROLLER_1_state_o_0(1) => 
        SEQ_CONTROLLER_1_state_o_0(1), SEQ_CONTROLLER_1_state_o_2
         => SEQ_CONTROLLER_1_state_o_2, 
        SEQ_CONTROLLER_1_state_o_0_d0 => 
        SEQ_CONTROLLER_1_state_o_0_d0, prdata_o_1_0_iv_0_2_tz_1
         => prdata_o_1_0_iv_0_2_tz_1, prdata_o_1_0_iv_0_2_tz_4
         => prdata_o_1_0_iv_0_2_tz_4, prdata_o_1_0_iv_0_2_tz_0
         => prdata_o_1_0_iv_0_2_tz_0, prdata_o_1_0_iv_0_12_1(7)
         => prdata_o_1_0_iv_0_12_1(7), prdata_o_1_0_iv_0_12_4(8)
         => prdata_o_1_0_iv_0_12_4(8), 
        prdata_o_1_0_iv_0_a2_19_0(10) => 
        prdata_o_1_0_iv_0_a2_19_0(10), prdata_o_1_0_iv_0_1_1(10)
         => prdata_o_1_0_iv_0_1_1(10), 
        FOC_TRANSFORMS_1_valpha_o_0 => 
        FOC_TRANSFORMS_1_valpha_o_0, FOC_TRANSFORMS_1_valpha_o_5
         => FOC_TRANSFORMS_1_valpha_o_5, 
        FOC_TRANSFORMS_1_valpha_o_8 => 
        FOC_TRANSFORMS_1_valpha_o_8, FOC_TRANSFORMS_1_valpha_o_9
         => FOC_TRANSFORMS_1_valpha_o_9, 
        FOC_TRANSFORMS_1_valpha_o_4 => 
        FOC_TRANSFORMS_1_valpha_o_4, FOC_TRANSFORMS_1_valpha_o_7
         => FOC_TRANSFORMS_1_valpha_o_7, 
        FOC_TRANSFORMS_1_valpha_o_10 => 
        FOC_TRANSFORMS_1_valpha_o_10, FOC_TRANSFORMS_1_valpha_o_6
         => FOC_TRANSFORMS_1_valpha_o_6, 
        FOC_TRANSFORMS_1_valpha_o_11 => 
        FOC_TRANSFORMS_1_valpha_o_11, 
        STEPPER_THETA_1_step_count_o_17 => 
        STEPPER_THETA_1_step_count_o_17, 
        STEPPER_THETA_1_step_count_o_3 => 
        STEPPER_THETA_1_step_count_o_3, 
        STEPPER_THETA_1_step_count_o_6 => 
        STEPPER_THETA_1_step_count_o_6, 
        STEPPER_THETA_1_step_count_o_9 => 
        STEPPER_THETA_1_step_count_o_9, 
        STEPPER_THETA_1_step_count_o_0 => 
        STEPPER_THETA_1_step_count_o_0, 
        STEPPER_THETA_1_step_count_o_5 => 
        STEPPER_THETA_1_step_count_o_5, 
        prdata_o_1_0_iv_0_a2_6_2_3 => prdata_o_1_0_iv_0_a2_6_2_3, 
        prdata_o_1_0_iv_0_a2_6_2_0 => prdata_o_1_0_iv_0_a2_6_2_0, 
        prdata_o_1_0_iv_0_a2_6_2_5 => prdata_o_1_0_iv_0_a2_6_2_5, 
        FOC_TRANSFORMS_0_vbeta_o_0 => FOC_TRANSFORMS_0_vbeta_o_0, 
        FOC_TRANSFORMS_0_vbeta_o_3 => FOC_TRANSFORMS_0_vbeta_o_3, 
        FOC_TRANSFORMS_0_vbeta_o_5 => FOC_TRANSFORMS_0_vbeta_o_5, 
        FOC_TRANSFORMS_0_vbeta_o_8 => FOC_TRANSFORMS_0_vbeta_o_8, 
        FOC_TRANSFORMS_0_vbeta_o_12 => 
        FOC_TRANSFORMS_0_vbeta_o_12, FOC_TRANSFORMS_0_vbeta_o_15
         => FOC_TRANSFORMS_0_vbeta_o_15, 
        FOC_TRANSFORMS_0_vbeta_o_7 => FOC_TRANSFORMS_0_vbeta_o_7, 
        FOC_TRANSFORMS_0_vbeta_o_10 => 
        FOC_TRANSFORMS_0_vbeta_o_10, FOC_TRANSFORMS_0_vbeta_o_2
         => FOC_TRANSFORMS_0_vbeta_o_2, FOC_TRANSFORMS_0_iq_o_0
         => FOC_TRANSFORMS_0_iq_o_0, FOC_TRANSFORMS_0_iq_o_1 => 
        FOC_TRANSFORMS_0_iq_o_1, FOC_TRANSFORMS_0_iq_o_3 => 
        FOC_TRANSFORMS_0_iq_o_3, FOC_TRANSFORMS_0_iq_o_5 => 
        FOC_TRANSFORMS_0_iq_o_5, FOC_TRANSFORMS_0_iq_o_8 => 
        FOC_TRANSFORMS_0_iq_o_8, FOC_TRANSFORMS_0_iq_o_12 => 
        FOC_TRANSFORMS_0_iq_o_12, FOC_TRANSFORMS_0_iq_o_15 => 
        FOC_TRANSFORMS_0_iq_o_15, FOC_TRANSFORMS_0_iq_o_7 => 
        FOC_TRANSFORMS_0_iq_o_7, FOC_TRANSFORMS_0_iq_o_10 => 
        FOC_TRANSFORMS_0_iq_o_10, FOC_TRANSFORMS_0_iq_o_6 => 
        FOC_TRANSFORMS_0_iq_o_6, FOC_TRANSFORMS_0_iq_o_11 => 
        FOC_TRANSFORMS_0_iq_o_11, FOC_TRANSFORMS_0_iq_o_2 => 
        FOC_TRANSFORMS_0_iq_o_2, prdata_o_1_0_iv_0_0_0_1 => 
        prdata_o_1_0_iv_0_0_0_1, prdata_o_1_0_iv_0_0_0_4 => 
        prdata_o_1_0_iv_0_0_0_4, prdata_o_1_0_iv_0_0_0_0_d0 => 
        prdata_o_1_0_iv_0_0_0_0_d0, prdata_o_1_0_iv_0_0_0_2 => 
        prdata_o_1_0_iv_0_0_0_2, prdata_o_1_0_iv_0_0_0_7 => 
        prdata_o_1_0_iv_0_0_0_7, prdata_o_1_0_iv_0_0_0_5 => 
        prdata_o_1_0_iv_0_0_0_5, FOC_TRANSFORMS_0_id_o_0 => 
        FOC_TRANSFORMS_0_id_o_0, FOC_TRANSFORMS_0_id_o_5 => 
        FOC_TRANSFORMS_0_id_o_5, FOC_TRANSFORMS_0_id_o_8 => 
        FOC_TRANSFORMS_0_id_o_8, FOC_TRANSFORMS_0_id_o_9 => 
        FOC_TRANSFORMS_0_id_o_9, FOC_TRANSFORMS_0_id_o_7 => 
        FOC_TRANSFORMS_0_id_o_7, FOC_TRANSFORMS_0_id_o_10 => 
        FOC_TRANSFORMS_0_id_o_10, FOC_TRANSFORMS_0_id_o_12 => 
        FOC_TRANSFORMS_0_id_o_12, FOC_TRANSFORMS_0_id_o_15 => 
        FOC_TRANSFORMS_0_id_o_15, prdata_o_1_0_iv_0_3_0 => 
        prdata_o_1_0_iv_0_3_0, prdata_o_1_0_iv_0_3_3 => 
        prdata_o_1_0_iv_0_3_3, 
        adc_measurements_0_adc_result_ch1_o_0 => 
        adc_measurements_0_adc_result_ch1_o_0, 
        adc_measurements_0_adc_result_ch1_o_5 => 
        adc_measurements_0_adc_result_ch1_o_5, 
        adc_measurements_0_adc_result_ch1_o_8 => 
        adc_measurements_0_adc_result_ch1_o_8, 
        adc_measurements_0_adc_result_ch1_o_10 => 
        adc_measurements_0_adc_result_ch1_o_10, 
        adc_measurements_0_adc_result_ch1_o_1 => 
        adc_measurements_0_adc_result_ch1_o_1, 
        adc_measurements_0_adc_result_ch1_o_9 => 
        adc_measurements_0_adc_result_ch1_o_9, 
        adc_measurements_0_adc_result_ch1_o_7 => 
        adc_measurements_0_adc_result_ch1_o_7, 
        adc_interface_0_result_ch0_o_6 => 
        adc_interface_0_result_ch0_o_6, 
        adc_interface_0_result_ch0_o_11 => 
        adc_interface_0_result_ch0_o_11, 
        adc_interface_0_result_ch0_o_7 => 
        adc_interface_0_result_ch0_o_7, 
        adc_interface_0_result_ch0_o_0 => 
        adc_interface_0_result_ch0_o_0, 
        adc_interface_0_result_ch0_o_5 => 
        adc_interface_0_result_ch0_o_5, 
        adc_interface_0_result_ch0_o_8 => 
        adc_interface_0_result_ch0_o_8, 
        adc_interface_0_result_ch0_o_9 => 
        adc_interface_0_result_ch0_o_9, ADC_SCALING_0_ia_adc_o_0
         => ADC_SCALING_0_ia_adc_o_0, ADC_SCALING_0_ia_adc_o_7
         => ADC_SCALING_0_ia_adc_o_7, ADC_SCALING_0_ia_adc_o_10
         => ADC_SCALING_0_ia_adc_o_10, ADC_SCALING_0_ia_adc_o_2
         => ADC_SCALING_0_ia_adc_o_2, ADC_SCALING_0_ia_adc_o_5
         => ADC_SCALING_0_ia_adc_o_5, ADC_SCALING_0_ia_adc_o_8
         => ADC_SCALING_0_ia_adc_o_8, ADC_SCALING_0_ia_adc_o_9
         => ADC_SCALING_0_ia_adc_o_9, ADC_SCALING_0_ia_adc_o_12
         => ADC_SCALING_0_ia_adc_o_12, ADC_SCALING_0_ia_adc_o_15
         => ADC_SCALING_0_ia_adc_o_15, ADC_SCALING_0_ia_adc_o_4
         => ADC_SCALING_0_ia_adc_o_4, ADC_SCALING_0_ia_adc_o_1
         => ADC_SCALING_0_ia_adc_o_1, ADC_SCALING_0_ia_adc_o_6
         => ADC_SCALING_0_ia_adc_o_6, ADC_SCALING_0_ia_adc_o_11
         => ADC_SCALING_0_ia_adc_o_11, 
        prdata_o_1_0_iv_0_1_o2_0(17) => 
        prdata_o_1_0_iv_0_1_o2_0(17), prdata_o_1_iv_0_0_11(3) => 
        prdata_o_1_iv_0_0_11(3), prdata_o_1_2_0_0_5(3) => 
        prdata_o_1_2_0_0_5(3), ADC_SCALING_0_ib_adc_o_10 => 
        ADC_SCALING_0_ib_adc_o_10, ADC_SCALING_0_ib_adc_o_5 => 
        ADC_SCALING_0_ib_adc_o_5, ADC_SCALING_0_ib_adc_o_4 => 
        ADC_SCALING_0_ib_adc_o_4, ADC_SCALING_0_ib_adc_o_7 => 
        ADC_SCALING_0_ib_adc_o_7, ADC_SCALING_0_ib_adc_o_8 => 
        ADC_SCALING_0_ib_adc_o_8, ADC_SCALING_0_ib_adc_o_11 => 
        ADC_SCALING_0_ib_adc_o_11, ADC_SCALING_0_ib_adc_o_14 => 
        ADC_SCALING_0_ib_adc_o_14, ADC_SCALING_0_ib_adc_o_3 => 
        ADC_SCALING_0_ib_adc_o_3, ADC_SCALING_0_ib_adc_o_0 => 
        ADC_SCALING_0_ib_adc_o_0, prdata_o_1_iv_0_0_0_3_tz(1) => 
        prdata_o_1_iv_0_0_0_3_tz(1), prdata_o_1_0_1(16) => 
        prdata_o_1_0_1(16), prdata_o_1_0_2(16) => 
        prdata_o_1_0_2(16), prdata_o_1_0_0(16) => 
        prdata_o_1_0_0(16), prdata_o_1_3_0_0_2(11) => 
        prdata_o_1_3_0_0_2(11), prdata_o_1_3_0_0_3(11) => 
        prdata_o_1_3_0_0_3(11), prdata_o_1_3_0_0_0(11) => 
        prdata_o_1_3_0_0_0(11), prdata_o_1_8_2(6) => 
        prdata_o_1_8_2(6), prdata_o_1_8_3(6) => prdata_o_1_8_3(6), 
        prdata_o_1_8_0(6) => prdata_o_1_8_0(6), 
        prdata_o_1_iv_0_0_12_4_3(3) => 
        prdata_o_1_iv_0_0_12_4_3(3), prdata_o_1_iv_0_0_12_4_2(3)
         => prdata_o_1_iv_0_0_12_4_2(3), prdata_o_1_0_iv_0_5_1
         => prdata_o_1_0_iv_0_5_1, prdata_o_1_0_iv_0_5_4 => 
        prdata_o_1_0_iv_0_5_4, prdata_o_1_0_iv_0_5_2 => 
        prdata_o_1_0_iv_0_5_2, prdata_o_1_0_iv_0_5_7 => 
        prdata_o_1_0_iv_0_5_7, prdata_o_1_0_iv_0_5_5 => 
        prdata_o_1_0_iv_0_5_5, prdata_o_1_0_iv_0_5_0 => 
        prdata_o_1_0_iv_0_5_0, prdata_o_1_0_iv_0_5_12 => 
        prdata_o_1_0_iv_0_5_12, prdata_o_1_0_iv_0_6(16) => 
        prdata_o_1_0_iv_0_6(16), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(10), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(7), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(3), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(5), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(8), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(1), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(9), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(0), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(16), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(15), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(12), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(11), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(6), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(22), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(21), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(20), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(19), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(18), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(17), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(13), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(31), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(4), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(14), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, 
        MC_System_0_AMBA_SLAVE_1_PSELx => 
        MC_System_0_AMBA_SLAVE_1_PSELx, N_1342 => N_1342, N_2598
         => N_2598, N_2644 => N_2644, N_1396 => N_1396, N_2631
         => N_2631, prdata_m2_e_1_1 => prdata_m2_e_1_1, N_1360
         => N_1360, N_1288 => N_1288, prdata_m1_0_a2_0 => 
        prdata_m1_0_a2_0, N_522 => N_522, N_527 => N_527, N_542
         => N_542, prdata_m4_e_0 => prdata_m4_e_0, 
        prdata_m1_0_a2_2_0 => prdata_m1_0_a2_2_0, N_509 => N_509, 
        N_529 => N_529, N_503 => N_503, prdata_m2_e_0 => 
        prdata_m2_e_0, N_508 => N_508, N_2652 => N_2652, N_768
         => N_768, N_1345 => N_1345, N_2647 => N_2647, N_2531 => 
        N_2531, N_513 => N_513, N_502 => N_502, N_534 => N_534, 
        N_500 => N_500, N_514 => N_514, N_506 => N_506, N_505 => 
        N_505, N_518 => N_518, N_2574 => N_2574, N_1346 => N_1346, 
        N_531 => N_531, N_2640 => N_2640, N_738 => N_738, N_533
         => N_533, N_507 => N_507, prdata_m1_e_0_1 => 
        prdata_m1_e_0_1, N_1398 => N_1398, N_1378 => N_1378, 
        N_2627 => N_2627, prdata_m2_0_a2_0 => prdata_m2_0_a2_0, 
        N_455 => N_455, N_495 => N_495, N_892 => N_892, N_771 => 
        N_771, N_773 => N_773, N_750 => N_750, N_2639 => N_2639, 
        N_775 => N_775, N_763 => N_763, N_2645 => N_2645, N_1351
         => N_1351, N_1169 => N_1169, N_1279 => N_1279, N_793 => 
        N_793, N_791 => N_791, N_782 => N_782, N_893 => N_893, 
        N_788 => N_788, N_772 => N_772, N_749 => N_749, N_774 => 
        N_774, N_762 => N_762, N_1347 => N_1347, N_1165 => N_1165, 
        N_1275 => N_1275, N_792 => N_792, N_878 => N_878, N_859
         => N_859, N_880 => N_880, N_870 => N_870, 
        prdata_m2_e_0_0 => prdata_m2_e_0_0, prdata_m1_e_11_0 => 
        prdata_m1_e_11_0, N_414 => N_414, N_516 => N_516, N_397
         => N_397, N_355 => N_355, N_198 => N_198, m20_i_2_tz => 
        m20_i_2_tz, m20_i_a2_0_1 => m20_i_a2_0_1, m20_m2_0_a2_1
         => m20_m2_0_a2_1, N_349 => N_349, m20_i_a2_5_0 => 
        m20_i_a2_5_0, N_517 => N_517, N_128 => N_128, N_528 => 
        N_528, N_524 => N_524, N_454 => N_454, N_494 => N_494, 
        N_894 => N_894, N_1326 => N_1326, N_2646 => N_2646, N_770
         => N_770, N_777 => N_777, N_883 => N_883, N_1333 => 
        N_1333, N_790 => N_790, N_895 => N_895, N_769 => N_769, 
        N_776 => N_776, N_832 => N_832, N_1329 => N_1329, N_789
         => N_789, N_876 => N_876, N_882 => N_882, prdata_m3_i_0
         => prdata_m3_i_0, N_260 => N_260, N_766 => N_766, N_739
         => N_739, N_891 => N_891, N_767 => N_767, N_875 => N_875, 
        N_396 => N_396, N_405 => N_405, N_354 => N_354, N_363 => 
        N_363, prdata_N_7_2 => prdata_N_7_2, m20_i_10_1 => 
        m20_i_10_1, m20_i_10_0 => m20_i_10_0, N_215 => N_215, 
        N_377 => N_377, N_2495 => N_2495, N_2498 => N_2498, 
        m20_i_11_5 => m20_i_11_5, N_122 => N_122, N_317 => N_317, 
        N_318 => N_318, N_319 => N_319, N_320 => N_320, N_321 => 
        N_321, N_315 => N_315, PRDATA_N_3_mux_i_0 => 
        PRDATA_N_3_mux_i_0);
    
    CCC_0 : MC_System_sb_CCC_0_FCCC
      port map(MC_System_0_FIC_0_LOCK => \MC_System_0_FIC_0_LOCK\, 
        MC_System_0_FIC_0_CLK => \MC_System_0_FIC_0_CLK\, 
        MC_System_0_FAB_CCC_GL1 => MC_System_0_FAB_CCC_GL1, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MC_System_sb_MSS_0 : MC_System_sb_MSS
      port map(USB_ULPI_DATA(7) => USB_ULPI_DATA(7), 
        USB_ULPI_DATA(6) => USB_ULPI_DATA(6), USB_ULPI_DATA(5)
         => USB_ULPI_DATA(5), USB_ULPI_DATA(4) => 
        USB_ULPI_DATA(4), USB_ULPI_DATA(3) => USB_ULPI_DATA(3), 
        USB_ULPI_DATA(2) => USB_ULPI_DATA(2), USB_ULPI_DATA(1)
         => USB_ULPI_DATA(1), USB_ULPI_DATA(0) => 
        USB_ULPI_DATA(0), MC_System_0_AMBA_SLAVE_1_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), 
        MC_System_0_AMBA_SLAVE_1_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), 
        MC_System_0_AMBA_SLAVE_1_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), 
        MC_System_0_AMBA_SLAVE_1_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        MC_System_0_AMBA_SLAVE_1_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), 
        MC_System_0_AMBA_SLAVE_1_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), 
        MC_System_0_AMBA_SLAVE_1_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), 
        MC_System_0_AMBA_SLAVE_1_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), 
        MC_System_0_AMBA_SLAVE_1_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        MC_System_0_AMBA_SLAVE_1_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        MC_System_0_AMBA_SLAVE_1_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(0), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(1), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(3), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(4), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(5), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(6), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(7), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(8), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(9), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(10), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(11), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(12), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(13), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(14), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(15), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(16), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(17), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(18), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(19), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(20), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(21), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(22), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(31), 
        USB_ULPI_XCLK => USB_ULPI_XCLK, USB_ULPI_STP => 
        USB_ULPI_STP, USB_ULPI_NXT => USB_ULPI_NXT, USB_ULPI_DIR
         => USB_ULPI_DIR, MC_System_0_AMBA_SLAVE_1_PENABLE => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, 
        MC_System_0_AMBA_SLAVE_1_PWRITE => 
        MC_System_0_AMBA_SLAVE_1_PWRITE, GPIO_0_M2F_c => 
        GPIO_0_M2F_c, PRDATA_N_3_mux_i_0 => PRDATA_N_3_mux_i_0, 
        MC_System_0_FIC_0_LOCK => \MC_System_0_FIC_0_LOCK\, 
        MC_System_0_FIC_0_CLK => \MC_System_0_FIC_0_CLK\);
    
    GND_Z : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System is

    port( prdata_o_1_2_0_a2_11_0                 : in    std_logic_vector(1 to 1);
          prdata_o_1_2_0_a2_12_0                 : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_26_0              : in    std_logic_vector(1 to 1);
          prdata_o_1_2_0_0_2                     : in    std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_0                     : in    std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_1                     : in    std_logic_vector(2 to 2);
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI      : in    std_logic_vector(0 to 0);
          prdata_o_1_2_0_a2_17_0                 : in    std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_a2_20_0              : in    std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_a2_24_0              : in    std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_0_0_0                : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1_6_tz               : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1                    : in    std_logic_vector(7 to 7);
          prdata_o_1_0_iv_0_0                    : in    std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_0_2_tz_tz            : in    std_logic_vector(0 to 0);
          prdata_o_1_iv_0_0_4_2_1_0              : in    std_logic_vector(3 to 3);
          SPEED_ID_IQ_PI_1_id_pi_output_o        : in    std_logic_vector(1 downto 0);
          SPEED_ID_IQ_PI_1_iq_pi_output_o        : in    std_logic_vector(1 downto 0);
          prdata_o_1_2_0_0_4_2                   : in    std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_5_0               : in    std_logic_vector(3 to 3);
          STEPPER_THETA_0_theta_output_o         : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_a2_45_0              : in    std_logic_vector(0 to 0);
          adc_measurements_0_adc_result_ch3_o    : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_14_1              : in    std_logic_vector(1 to 1);
          SEQ_CONTROLLER_1_state_o_0             : in    std_logic_vector(1 to 1);
          SEQ_CONTROLLER_1_state_o_2             : in    std_logic;
          SEQ_CONTROLLER_1_state_o_0_d0          : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_1               : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_4               : in    std_logic;
          prdata_o_1_0_iv_0_2_tz_0               : in    std_logic;
          prdata_o_1_0_iv_0_12_1                 : in    std_logic_vector(7 to 7);
          prdata_o_1_0_iv_0_12_4                 : in    std_logic_vector(8 to 8);
          prdata_o_1_0_iv_0_a2_19_0              : in    std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_1_1                  : in    std_logic_vector(10 to 10);
          FOC_TRANSFORMS_1_valpha_o_0            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_5            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_8            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_9            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_4            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_7            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_10           : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_6            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_11           : in    std_logic;
          STEPPER_THETA_1_step_count_o_17        : in    std_logic;
          STEPPER_THETA_1_step_count_o_3         : in    std_logic;
          STEPPER_THETA_1_step_count_o_6         : in    std_logic;
          STEPPER_THETA_1_step_count_o_9         : in    std_logic;
          STEPPER_THETA_1_step_count_o_0         : in    std_logic;
          STEPPER_THETA_1_step_count_o_5         : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_3             : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_0             : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_5             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_0             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_3             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_5             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_8             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_12            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_15            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_7             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_10            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_2             : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_0                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_1                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_5                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_8                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_12               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_15               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_7                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_10               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_6                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_11               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_2                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_1                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_4                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_0_d0             : in    std_logic;
          prdata_o_1_0_iv_0_0_0_2                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_7                : in    std_logic;
          prdata_o_1_0_iv_0_0_0_5                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_0                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_5                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_8                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_9                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_7                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_10               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_12               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_15               : in    std_logic;
          prdata_o_1_0_iv_0_3_0                  : in    std_logic;
          prdata_o_1_0_iv_0_3_3                  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_0  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_5  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_8  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_10 : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_1  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_9  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_7  : in    std_logic;
          adc_interface_0_result_ch0_o_6         : in    std_logic;
          adc_interface_0_result_ch0_o_11        : in    std_logic;
          adc_interface_0_result_ch0_o_7         : in    std_logic;
          adc_interface_0_result_ch0_o_0         : in    std_logic;
          adc_interface_0_result_ch0_o_5         : in    std_logic;
          adc_interface_0_result_ch0_o_8         : in    std_logic;
          adc_interface_0_result_ch0_o_9         : in    std_logic;
          ADC_SCALING_0_ia_adc_o_0               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_7               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_10              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_2               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_5               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_8               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_9               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_12              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_15              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_4               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_1               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_6               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_11              : in    std_logic;
          prdata_o_1_0_iv_0_1_o2_0               : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_11                   : in    std_logic_vector(3 to 3);
          prdata_o_1_2_0_0_5                     : in    std_logic_vector(3 to 3);
          ADC_SCALING_0_ib_adc_o_10              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_5               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_4               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_7               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_8               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_11              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_14              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_3               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_0               : in    std_logic;
          prdata_o_1_iv_0_0_0_3_tz               : in    std_logic_vector(1 to 1);
          prdata_o_1_0_1                         : in    std_logic_vector(16 to 16);
          prdata_o_1_0_2                         : in    std_logic_vector(16 to 16);
          prdata_o_1_0_0                         : in    std_logic_vector(16 to 16);
          prdata_o_1_3_0_0_2                     : in    std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_3                     : in    std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_0                     : in    std_logic_vector(11 to 11);
          prdata_o_1_8_2                         : in    std_logic_vector(6 to 6);
          prdata_o_1_8_3                         : in    std_logic_vector(6 to 6);
          prdata_o_1_8_0                         : in    std_logic_vector(6 to 6);
          prdata_o_1_iv_0_0_12_4_3               : in    std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_4_2               : in    std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_5_1                  : in    std_logic;
          prdata_o_1_0_iv_0_5_4                  : in    std_logic;
          prdata_o_1_0_iv_0_5_2                  : in    std_logic;
          prdata_o_1_0_iv_0_5_7                  : in    std_logic;
          prdata_o_1_0_iv_0_5_5                  : in    std_logic;
          prdata_o_1_0_iv_0_5_0                  : in    std_logic;
          prdata_o_1_0_iv_0_5_12                 : in    std_logic;
          prdata_o_1_0_iv_0_6                    : in    std_logic_vector(16 to 16);
          MC_System_0_AMBA_SLAVE_1_PRDATA        : in    std_logic_vector(14 downto 13);
          MC_System_0_AMBA_SLAVE_0_PRDATA_0      : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_15     : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_12     : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_13     : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_14     : in    std_logic;
          USB_ULPI_DATA                          : inout std_logic_vector(7 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_1_PADDR         : inout std_logic_vector(11 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_1_PWDATA        : out   std_logic_vector(23 downto 0);
          MC_System_0_FIC_0_LOCK                 : out   std_logic;
          MC_System_0_FIC_0_CLK                  : out   std_logic;
          MC_System_0_FAB_CCC_GL1                : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx         : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx         : out   std_logic;
          N_1342                                 : in    std_logic;
          N_2598                                 : in    std_logic;
          N_2644                                 : in    std_logic;
          N_1396                                 : in    std_logic;
          N_2631                                 : in    std_logic;
          prdata_m2_e_1_1                        : in    std_logic;
          N_1360                                 : in    std_logic;
          N_1288                                 : in    std_logic;
          prdata_m1_0_a2_0                       : in    std_logic;
          N_522                                  : in    std_logic;
          N_527                                  : in    std_logic;
          N_542                                  : in    std_logic;
          prdata_m4_e_0                          : in    std_logic;
          prdata_m1_0_a2_2_0                     : in    std_logic;
          N_509                                  : in    std_logic;
          N_529                                  : in    std_logic;
          N_503                                  : in    std_logic;
          prdata_m2_e_0                          : in    std_logic;
          N_508                                  : in    std_logic;
          N_2652                                 : in    std_logic;
          N_768                                  : in    std_logic;
          N_1345                                 : in    std_logic;
          N_2647                                 : in    std_logic;
          N_2531                                 : in    std_logic;
          N_513                                  : in    std_logic;
          N_502                                  : in    std_logic;
          N_534                                  : in    std_logic;
          N_500                                  : in    std_logic;
          N_514                                  : in    std_logic;
          N_506                                  : in    std_logic;
          N_505                                  : in    std_logic;
          N_518                                  : in    std_logic;
          N_2574                                 : in    std_logic;
          N_1346                                 : in    std_logic;
          N_531                                  : in    std_logic;
          N_2640                                 : in    std_logic;
          N_738                                  : in    std_logic;
          N_533                                  : in    std_logic;
          N_507                                  : in    std_logic;
          prdata_m1_e_0_1                        : in    std_logic;
          N_1398                                 : in    std_logic;
          N_1378                                 : in    std_logic;
          N_2627                                 : in    std_logic;
          prdata_m2_0_a2_0                       : in    std_logic;
          N_455                                  : in    std_logic;
          N_495                                  : in    std_logic;
          N_892                                  : in    std_logic;
          N_771                                  : in    std_logic;
          N_773                                  : in    std_logic;
          N_750                                  : in    std_logic;
          N_2639                                 : in    std_logic;
          N_775                                  : in    std_logic;
          N_763                                  : in    std_logic;
          N_2645                                 : in    std_logic;
          N_1351                                 : in    std_logic;
          N_1169                                 : in    std_logic;
          N_1279                                 : in    std_logic;
          N_793                                  : in    std_logic;
          N_791                                  : in    std_logic;
          N_782                                  : in    std_logic;
          N_893                                  : in    std_logic;
          N_788                                  : in    std_logic;
          N_772                                  : in    std_logic;
          N_749                                  : in    std_logic;
          N_774                                  : in    std_logic;
          N_762                                  : in    std_logic;
          N_1347                                 : in    std_logic;
          N_1165                                 : in    std_logic;
          N_1275                                 : in    std_logic;
          N_792                                  : in    std_logic;
          N_878                                  : in    std_logic;
          N_859                                  : in    std_logic;
          N_880                                  : in    std_logic;
          N_870                                  : in    std_logic;
          prdata_m2_e_0_0                        : in    std_logic;
          prdata_m1_e_11_0                       : in    std_logic;
          N_414                                  : in    std_logic;
          N_516                                  : in    std_logic;
          N_397                                  : in    std_logic;
          N_355                                  : in    std_logic;
          N_198                                  : in    std_logic;
          m20_i_2_tz                             : in    std_logic;
          m20_i_a2_0_1                           : in    std_logic;
          m20_m2_0_a2_1                          : in    std_logic;
          N_349                                  : in    std_logic;
          m20_i_a2_5_0                           : in    std_logic;
          N_517                                  : in    std_logic;
          N_128                                  : in    std_logic;
          N_528                                  : in    std_logic;
          N_524                                  : in    std_logic;
          N_454                                  : in    std_logic;
          N_494                                  : in    std_logic;
          N_894                                  : in    std_logic;
          N_1326                                 : in    std_logic;
          N_2646                                 : in    std_logic;
          N_770                                  : in    std_logic;
          N_777                                  : in    std_logic;
          N_883                                  : in    std_logic;
          N_1333                                 : in    std_logic;
          N_790                                  : in    std_logic;
          N_895                                  : in    std_logic;
          N_769                                  : in    std_logic;
          N_776                                  : in    std_logic;
          N_832                                  : in    std_logic;
          N_1329                                 : in    std_logic;
          N_789                                  : in    std_logic;
          N_876                                  : in    std_logic;
          N_882                                  : in    std_logic;
          prdata_m3_i_0                          : in    std_logic;
          N_260                                  : in    std_logic;
          N_766                                  : in    std_logic;
          N_739                                  : in    std_logic;
          N_891                                  : in    std_logic;
          N_767                                  : in    std_logic;
          N_875                                  : in    std_logic;
          N_396                                  : in    std_logic;
          N_405                                  : in    std_logic;
          N_354                                  : in    std_logic;
          N_363                                  : in    std_logic;
          prdata_N_7_2                           : in    std_logic;
          m20_i_10_1                             : in    std_logic;
          m20_i_10_0                             : in    std_logic;
          N_215                                  : in    std_logic;
          N_377                                  : in    std_logic;
          N_2495                                 : in    std_logic;
          N_2498                                 : in    std_logic;
          m20_i_11_5                             : in    std_logic;
          N_122                                  : in    std_logic;
          N_317                                  : in    std_logic;
          N_318                                  : in    std_logic;
          N_319                                  : in    std_logic;
          N_320                                  : in    std_logic;
          N_321                                  : in    std_logic;
          N_315                                  : in    std_logic;
          USB_ULPI_XCLK                          : in    std_logic;
          USB_ULPI_STP                           : out   std_logic;
          USB_ULPI_NXT                           : in    std_logic;
          USB_ULPI_DIR                           : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PENABLE       : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE        : out   std_logic;
          GPIO_0_M2F_c                           : out   std_logic
        );

end MC_System;

architecture DEF_ARCH of MC_System is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MC_System_sb
    port( prdata_o_1_2_0_a2_11_0                 : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_2_0_a2_12_0                 : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_26_0              : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_2_0_0_2                     : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_2_0_0_0                     : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_2_0_0_1                     : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI      : in    std_logic_vector(0 to 0) := (others => 'U');
          prdata_o_1_2_0_a2_17_0                 : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_iv_0_a2_20_0              : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_iv_0_0_a2_24_0              : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_iv_0_0_0_0                : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1_6_tz               : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1                    : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_0_iv_0_0                    : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_iv_0_0_0_2_tz_tz            : in    std_logic_vector(0 to 0) := (others => 'U');
          prdata_o_1_iv_0_0_4_2_1_0              : in    std_logic_vector(3 to 3) := (others => 'U');
          SPEED_ID_IQ_PI_1_id_pi_output_o        : in    std_logic_vector(1 downto 0) := (others => 'U');
          SPEED_ID_IQ_PI_1_iq_pi_output_o        : in    std_logic_vector(1 downto 0) := (others => 'U');
          prdata_o_1_2_0_0_4_2                   : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_iv_0_0_12_5_0               : in    std_logic_vector(3 to 3) := (others => 'U');
          STEPPER_THETA_0_theta_output_o         : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_a2_45_0              : in    std_logic_vector(0 to 0) := (others => 'U');
          adc_measurements_0_adc_result_ch3_o    : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_14_1              : in    std_logic_vector(1 to 1) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_0             : in    std_logic_vector(1 to 1) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_2             : in    std_logic := 'U';
          SEQ_CONTROLLER_1_state_o_0_d0          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_1               : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_4               : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_0               : in    std_logic := 'U';
          prdata_o_1_0_iv_0_12_1                 : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_0_iv_0_12_4                 : in    std_logic_vector(8 to 8) := (others => 'U');
          prdata_o_1_0_iv_0_a2_19_0              : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1_1                  : in    std_logic_vector(10 to 10) := (others => 'U');
          FOC_TRANSFORMS_1_valpha_o_0            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_5            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_8            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_9            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_4            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_7            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_10           : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_6            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_11           : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_17        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_3         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_6         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_9         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_0         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_5         : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_3             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_0             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_5             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_0             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_3             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_5             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_8             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_12            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_15            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_7             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_10            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_2             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_0                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_1                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_5                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_8                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_12               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_15               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_7                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_10               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_6                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_11               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_2                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_1                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_4                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_0_d0             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_2                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_7                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_5                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_0                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_5                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_8                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_9                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_7                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_10               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_12               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_15               : in    std_logic := 'U';
          prdata_o_1_0_iv_0_3_0                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_3_3                  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_0  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_5  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_8  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_10 : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_1  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_9  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_7  : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_6         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_11        : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_7         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_0         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_5         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_8         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_9         : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_0               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_7               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_10              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_2               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_5               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_8               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_9               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_12              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_15              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_4               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_1               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_6               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_11              : in    std_logic := 'U';
          prdata_o_1_0_iv_0_1_o2_0               : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_11                   : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_2_0_0_5                     : in    std_logic_vector(3 to 3) := (others => 'U');
          ADC_SCALING_0_ib_adc_o_10              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_5               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_4               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_7               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_8               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_11              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_14              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_3               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_0               : in    std_logic := 'U';
          prdata_o_1_iv_0_0_0_3_tz               : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_1                         : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_2                         : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_0                         : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_3_0_0_2                     : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_3_0_0_3                     : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_3_0_0_0                     : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_8_2                         : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_8_3                         : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_8_0                         : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_iv_0_0_12_4_3               : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_iv_0_0_12_4_2               : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_0_iv_0_5_1                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_4                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_2                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_7                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_5                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_0                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_12                 : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6                    : in    std_logic_vector(16 to 16) := (others => 'U');
          MC_System_0_AMBA_SLAVE_1_PRDATA        : in    std_logic_vector(14 downto 13) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA_0      : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_15     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_12     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_13     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_14     : in    std_logic := 'U';
          USB_ULPI_DATA                          : inout   std_logic_vector(7 downto 0);
          MC_System_0_AMBA_SLAVE_1_PADDR         : inout   std_logic_vector(11 downto 0);
          MC_System_0_AMBA_SLAVE_1_PWDATA        : out   std_logic_vector(23 downto 0);
          MC_System_0_FIC_0_LOCK                 : out   std_logic;
          MC_System_0_FIC_0_CLK                  : out   std_logic;
          MC_System_0_FAB_CCC_GL1                : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx         : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx         : out   std_logic;
          N_1342                                 : in    std_logic := 'U';
          N_2598                                 : in    std_logic := 'U';
          N_2644                                 : in    std_logic := 'U';
          N_1396                                 : in    std_logic := 'U';
          N_2631                                 : in    std_logic := 'U';
          prdata_m2_e_1_1                        : in    std_logic := 'U';
          N_1360                                 : in    std_logic := 'U';
          N_1288                                 : in    std_logic := 'U';
          prdata_m1_0_a2_0                       : in    std_logic := 'U';
          N_522                                  : in    std_logic := 'U';
          N_527                                  : in    std_logic := 'U';
          N_542                                  : in    std_logic := 'U';
          prdata_m4_e_0                          : in    std_logic := 'U';
          prdata_m1_0_a2_2_0                     : in    std_logic := 'U';
          N_509                                  : in    std_logic := 'U';
          N_529                                  : in    std_logic := 'U';
          N_503                                  : in    std_logic := 'U';
          prdata_m2_e_0                          : in    std_logic := 'U';
          N_508                                  : in    std_logic := 'U';
          N_2652                                 : in    std_logic := 'U';
          N_768                                  : in    std_logic := 'U';
          N_1345                                 : in    std_logic := 'U';
          N_2647                                 : in    std_logic := 'U';
          N_2531                                 : in    std_logic := 'U';
          N_513                                  : in    std_logic := 'U';
          N_502                                  : in    std_logic := 'U';
          N_534                                  : in    std_logic := 'U';
          N_500                                  : in    std_logic := 'U';
          N_514                                  : in    std_logic := 'U';
          N_506                                  : in    std_logic := 'U';
          N_505                                  : in    std_logic := 'U';
          N_518                                  : in    std_logic := 'U';
          N_2574                                 : in    std_logic := 'U';
          N_1346                                 : in    std_logic := 'U';
          N_531                                  : in    std_logic := 'U';
          N_2640                                 : in    std_logic := 'U';
          N_738                                  : in    std_logic := 'U';
          N_533                                  : in    std_logic := 'U';
          N_507                                  : in    std_logic := 'U';
          prdata_m1_e_0_1                        : in    std_logic := 'U';
          N_1398                                 : in    std_logic := 'U';
          N_1378                                 : in    std_logic := 'U';
          N_2627                                 : in    std_logic := 'U';
          prdata_m2_0_a2_0                       : in    std_logic := 'U';
          N_455                                  : in    std_logic := 'U';
          N_495                                  : in    std_logic := 'U';
          N_892                                  : in    std_logic := 'U';
          N_771                                  : in    std_logic := 'U';
          N_773                                  : in    std_logic := 'U';
          N_750                                  : in    std_logic := 'U';
          N_2639                                 : in    std_logic := 'U';
          N_775                                  : in    std_logic := 'U';
          N_763                                  : in    std_logic := 'U';
          N_2645                                 : in    std_logic := 'U';
          N_1351                                 : in    std_logic := 'U';
          N_1169                                 : in    std_logic := 'U';
          N_1279                                 : in    std_logic := 'U';
          N_793                                  : in    std_logic := 'U';
          N_791                                  : in    std_logic := 'U';
          N_782                                  : in    std_logic := 'U';
          N_893                                  : in    std_logic := 'U';
          N_788                                  : in    std_logic := 'U';
          N_772                                  : in    std_logic := 'U';
          N_749                                  : in    std_logic := 'U';
          N_774                                  : in    std_logic := 'U';
          N_762                                  : in    std_logic := 'U';
          N_1347                                 : in    std_logic := 'U';
          N_1165                                 : in    std_logic := 'U';
          N_1275                                 : in    std_logic := 'U';
          N_792                                  : in    std_logic := 'U';
          N_878                                  : in    std_logic := 'U';
          N_859                                  : in    std_logic := 'U';
          N_880                                  : in    std_logic := 'U';
          N_870                                  : in    std_logic := 'U';
          prdata_m2_e_0_0                        : in    std_logic := 'U';
          prdata_m1_e_11_0                       : in    std_logic := 'U';
          N_414                                  : in    std_logic := 'U';
          N_516                                  : in    std_logic := 'U';
          N_397                                  : in    std_logic := 'U';
          N_355                                  : in    std_logic := 'U';
          N_198                                  : in    std_logic := 'U';
          m20_i_2_tz                             : in    std_logic := 'U';
          m20_i_a2_0_1                           : in    std_logic := 'U';
          m20_m2_0_a2_1                          : in    std_logic := 'U';
          N_349                                  : in    std_logic := 'U';
          m20_i_a2_5_0                           : in    std_logic := 'U';
          N_517                                  : in    std_logic := 'U';
          N_128                                  : in    std_logic := 'U';
          N_528                                  : in    std_logic := 'U';
          N_524                                  : in    std_logic := 'U';
          N_454                                  : in    std_logic := 'U';
          N_494                                  : in    std_logic := 'U';
          N_894                                  : in    std_logic := 'U';
          N_1326                                 : in    std_logic := 'U';
          N_2646                                 : in    std_logic := 'U';
          N_770                                  : in    std_logic := 'U';
          N_777                                  : in    std_logic := 'U';
          N_883                                  : in    std_logic := 'U';
          N_1333                                 : in    std_logic := 'U';
          N_790                                  : in    std_logic := 'U';
          N_895                                  : in    std_logic := 'U';
          N_769                                  : in    std_logic := 'U';
          N_776                                  : in    std_logic := 'U';
          N_832                                  : in    std_logic := 'U';
          N_1329                                 : in    std_logic := 'U';
          N_789                                  : in    std_logic := 'U';
          N_876                                  : in    std_logic := 'U';
          N_882                                  : in    std_logic := 'U';
          prdata_m3_i_0                          : in    std_logic := 'U';
          N_260                                  : in    std_logic := 'U';
          N_766                                  : in    std_logic := 'U';
          N_739                                  : in    std_logic := 'U';
          N_891                                  : in    std_logic := 'U';
          N_767                                  : in    std_logic := 'U';
          N_875                                  : in    std_logic := 'U';
          N_396                                  : in    std_logic := 'U';
          N_405                                  : in    std_logic := 'U';
          N_354                                  : in    std_logic := 'U';
          N_363                                  : in    std_logic := 'U';
          prdata_N_7_2                           : in    std_logic := 'U';
          m20_i_10_1                             : in    std_logic := 'U';
          m20_i_10_0                             : in    std_logic := 'U';
          N_215                                  : in    std_logic := 'U';
          N_377                                  : in    std_logic := 'U';
          N_2495                                 : in    std_logic := 'U';
          N_2498                                 : in    std_logic := 'U';
          m20_i_11_5                             : in    std_logic := 'U';
          N_122                                  : in    std_logic := 'U';
          N_317                                  : in    std_logic := 'U';
          N_318                                  : in    std_logic := 'U';
          N_319                                  : in    std_logic := 'U';
          N_320                                  : in    std_logic := 'U';
          N_321                                  : in    std_logic := 'U';
          N_315                                  : in    std_logic := 'U';
          USB_ULPI_XCLK                          : in    std_logic := 'U';
          USB_ULPI_STP                           : out   std_logic;
          USB_ULPI_NXT                           : in    std_logic := 'U';
          USB_ULPI_DIR                           : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PENABLE       : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE        : out   std_logic;
          GPIO_0_M2F_c                           : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \GND\, \VCC\ : std_logic;

    for all : MC_System_sb
	Use entity work.MC_System_sb(DEF_ARCH);
begin 


    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MC_System_sb_0 : MC_System_sb
      port map(prdata_o_1_2_0_a2_11_0(1) => 
        prdata_o_1_2_0_a2_11_0(1), prdata_o_1_2_0_a2_12_0(1) => 
        prdata_o_1_2_0_a2_12_0(1), prdata_o_1_iv_0_0_a2_26_0(1)
         => prdata_o_1_iv_0_0_a2_26_0(1), prdata_o_1_2_0_0_2(2)
         => prdata_o_1_2_0_0_2(2), prdata_o_1_2_0_0_0(2) => 
        prdata_o_1_2_0_0_0(2), prdata_o_1_2_0_0_1(2) => 
        prdata_o_1_2_0_0_1(2), 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0) => 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0), 
        prdata_o_1_2_0_a2_17_0(1) => prdata_o_1_2_0_a2_17_0(1), 
        prdata_o_1_0_iv_0_a2_20_0(10) => 
        prdata_o_1_0_iv_0_a2_20_0(10), 
        prdata_o_1_iv_0_0_a2_24_0(1) => 
        prdata_o_1_iv_0_0_a2_24_0(1), prdata_o_1_0_iv_0_0_0_0(10)
         => prdata_o_1_0_iv_0_0_0_0(10), 
        prdata_o_1_0_iv_0_1_6_tz(10) => 
        prdata_o_1_0_iv_0_1_6_tz(10), prdata_o_1_0_iv_0_1(7) => 
        prdata_o_1_0_iv_0_1(7), prdata_o_1_0_iv_0_0(7) => 
        prdata_o_1_0_iv_0_0(7), prdata_o_1_iv_0_0_0_2_tz_tz(0)
         => prdata_o_1_iv_0_0_0_2_tz_tz(0), 
        prdata_o_1_iv_0_0_4_2_1_0(3) => 
        prdata_o_1_iv_0_0_4_2_1_0(3), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0), 
        prdata_o_1_2_0_0_4_2(3) => prdata_o_1_2_0_0_4_2(3), 
        prdata_o_1_iv_0_0_12_5_0(3) => 
        prdata_o_1_iv_0_0_12_5_0(3), 
        STEPPER_THETA_0_theta_output_o(17) => 
        STEPPER_THETA_0_theta_output_o(17), 
        prdata_o_1_iv_0_0_a2_45_0(0) => 
        prdata_o_1_iv_0_0_a2_45_0(0), 
        adc_measurements_0_adc_result_ch3_o(1) => 
        adc_measurements_0_adc_result_ch3_o(1), 
        prdata_o_1_iv_0_0_a2_14_1(1) => 
        prdata_o_1_iv_0_0_a2_14_1(1), 
        SEQ_CONTROLLER_1_state_o_0(1) => 
        SEQ_CONTROLLER_1_state_o_0(1), SEQ_CONTROLLER_1_state_o_2
         => SEQ_CONTROLLER_1_state_o_2, 
        SEQ_CONTROLLER_1_state_o_0_d0 => 
        SEQ_CONTROLLER_1_state_o_0_d0, prdata_o_1_0_iv_0_2_tz_1
         => prdata_o_1_0_iv_0_2_tz_1, prdata_o_1_0_iv_0_2_tz_4
         => prdata_o_1_0_iv_0_2_tz_4, prdata_o_1_0_iv_0_2_tz_0
         => prdata_o_1_0_iv_0_2_tz_0, prdata_o_1_0_iv_0_12_1(7)
         => prdata_o_1_0_iv_0_12_1(7), prdata_o_1_0_iv_0_12_4(8)
         => prdata_o_1_0_iv_0_12_4(8), 
        prdata_o_1_0_iv_0_a2_19_0(10) => 
        prdata_o_1_0_iv_0_a2_19_0(10), prdata_o_1_0_iv_0_1_1(10)
         => prdata_o_1_0_iv_0_1_1(10), 
        FOC_TRANSFORMS_1_valpha_o_0 => 
        FOC_TRANSFORMS_1_valpha_o_0, FOC_TRANSFORMS_1_valpha_o_5
         => FOC_TRANSFORMS_1_valpha_o_5, 
        FOC_TRANSFORMS_1_valpha_o_8 => 
        FOC_TRANSFORMS_1_valpha_o_8, FOC_TRANSFORMS_1_valpha_o_9
         => FOC_TRANSFORMS_1_valpha_o_9, 
        FOC_TRANSFORMS_1_valpha_o_4 => 
        FOC_TRANSFORMS_1_valpha_o_4, FOC_TRANSFORMS_1_valpha_o_7
         => FOC_TRANSFORMS_1_valpha_o_7, 
        FOC_TRANSFORMS_1_valpha_o_10 => 
        FOC_TRANSFORMS_1_valpha_o_10, FOC_TRANSFORMS_1_valpha_o_6
         => FOC_TRANSFORMS_1_valpha_o_6, 
        FOC_TRANSFORMS_1_valpha_o_11 => 
        FOC_TRANSFORMS_1_valpha_o_11, 
        STEPPER_THETA_1_step_count_o_17 => 
        STEPPER_THETA_1_step_count_o_17, 
        STEPPER_THETA_1_step_count_o_3 => 
        STEPPER_THETA_1_step_count_o_3, 
        STEPPER_THETA_1_step_count_o_6 => 
        STEPPER_THETA_1_step_count_o_6, 
        STEPPER_THETA_1_step_count_o_9 => 
        STEPPER_THETA_1_step_count_o_9, 
        STEPPER_THETA_1_step_count_o_0 => 
        STEPPER_THETA_1_step_count_o_0, 
        STEPPER_THETA_1_step_count_o_5 => 
        STEPPER_THETA_1_step_count_o_5, 
        prdata_o_1_0_iv_0_a2_6_2_3 => prdata_o_1_0_iv_0_a2_6_2_3, 
        prdata_o_1_0_iv_0_a2_6_2_0 => prdata_o_1_0_iv_0_a2_6_2_0, 
        prdata_o_1_0_iv_0_a2_6_2_5 => prdata_o_1_0_iv_0_a2_6_2_5, 
        FOC_TRANSFORMS_0_vbeta_o_0 => FOC_TRANSFORMS_0_vbeta_o_0, 
        FOC_TRANSFORMS_0_vbeta_o_3 => FOC_TRANSFORMS_0_vbeta_o_3, 
        FOC_TRANSFORMS_0_vbeta_o_5 => FOC_TRANSFORMS_0_vbeta_o_5, 
        FOC_TRANSFORMS_0_vbeta_o_8 => FOC_TRANSFORMS_0_vbeta_o_8, 
        FOC_TRANSFORMS_0_vbeta_o_12 => 
        FOC_TRANSFORMS_0_vbeta_o_12, FOC_TRANSFORMS_0_vbeta_o_15
         => FOC_TRANSFORMS_0_vbeta_o_15, 
        FOC_TRANSFORMS_0_vbeta_o_7 => FOC_TRANSFORMS_0_vbeta_o_7, 
        FOC_TRANSFORMS_0_vbeta_o_10 => 
        FOC_TRANSFORMS_0_vbeta_o_10, FOC_TRANSFORMS_0_vbeta_o_2
         => FOC_TRANSFORMS_0_vbeta_o_2, FOC_TRANSFORMS_0_iq_o_0
         => FOC_TRANSFORMS_0_iq_o_0, FOC_TRANSFORMS_0_iq_o_1 => 
        FOC_TRANSFORMS_0_iq_o_1, FOC_TRANSFORMS_0_iq_o_3 => 
        FOC_TRANSFORMS_0_iq_o_3, FOC_TRANSFORMS_0_iq_o_5 => 
        FOC_TRANSFORMS_0_iq_o_5, FOC_TRANSFORMS_0_iq_o_8 => 
        FOC_TRANSFORMS_0_iq_o_8, FOC_TRANSFORMS_0_iq_o_12 => 
        FOC_TRANSFORMS_0_iq_o_12, FOC_TRANSFORMS_0_iq_o_15 => 
        FOC_TRANSFORMS_0_iq_o_15, FOC_TRANSFORMS_0_iq_o_7 => 
        FOC_TRANSFORMS_0_iq_o_7, FOC_TRANSFORMS_0_iq_o_10 => 
        FOC_TRANSFORMS_0_iq_o_10, FOC_TRANSFORMS_0_iq_o_6 => 
        FOC_TRANSFORMS_0_iq_o_6, FOC_TRANSFORMS_0_iq_o_11 => 
        FOC_TRANSFORMS_0_iq_o_11, FOC_TRANSFORMS_0_iq_o_2 => 
        FOC_TRANSFORMS_0_iq_o_2, prdata_o_1_0_iv_0_0_0_1 => 
        prdata_o_1_0_iv_0_0_0_1, prdata_o_1_0_iv_0_0_0_4 => 
        prdata_o_1_0_iv_0_0_0_4, prdata_o_1_0_iv_0_0_0_0_d0 => 
        prdata_o_1_0_iv_0_0_0_0_d0, prdata_o_1_0_iv_0_0_0_2 => 
        prdata_o_1_0_iv_0_0_0_2, prdata_o_1_0_iv_0_0_0_7 => 
        prdata_o_1_0_iv_0_0_0_7, prdata_o_1_0_iv_0_0_0_5 => 
        prdata_o_1_0_iv_0_0_0_5, FOC_TRANSFORMS_0_id_o_0 => 
        FOC_TRANSFORMS_0_id_o_0, FOC_TRANSFORMS_0_id_o_5 => 
        FOC_TRANSFORMS_0_id_o_5, FOC_TRANSFORMS_0_id_o_8 => 
        FOC_TRANSFORMS_0_id_o_8, FOC_TRANSFORMS_0_id_o_9 => 
        FOC_TRANSFORMS_0_id_o_9, FOC_TRANSFORMS_0_id_o_7 => 
        FOC_TRANSFORMS_0_id_o_7, FOC_TRANSFORMS_0_id_o_10 => 
        FOC_TRANSFORMS_0_id_o_10, FOC_TRANSFORMS_0_id_o_12 => 
        FOC_TRANSFORMS_0_id_o_12, FOC_TRANSFORMS_0_id_o_15 => 
        FOC_TRANSFORMS_0_id_o_15, prdata_o_1_0_iv_0_3_0 => 
        prdata_o_1_0_iv_0_3_0, prdata_o_1_0_iv_0_3_3 => 
        prdata_o_1_0_iv_0_3_3, 
        adc_measurements_0_adc_result_ch1_o_0 => 
        adc_measurements_0_adc_result_ch1_o_0, 
        adc_measurements_0_adc_result_ch1_o_5 => 
        adc_measurements_0_adc_result_ch1_o_5, 
        adc_measurements_0_adc_result_ch1_o_8 => 
        adc_measurements_0_adc_result_ch1_o_8, 
        adc_measurements_0_adc_result_ch1_o_10 => 
        adc_measurements_0_adc_result_ch1_o_10, 
        adc_measurements_0_adc_result_ch1_o_1 => 
        adc_measurements_0_adc_result_ch1_o_1, 
        adc_measurements_0_adc_result_ch1_o_9 => 
        adc_measurements_0_adc_result_ch1_o_9, 
        adc_measurements_0_adc_result_ch1_o_7 => 
        adc_measurements_0_adc_result_ch1_o_7, 
        adc_interface_0_result_ch0_o_6 => 
        adc_interface_0_result_ch0_o_6, 
        adc_interface_0_result_ch0_o_11 => 
        adc_interface_0_result_ch0_o_11, 
        adc_interface_0_result_ch0_o_7 => 
        adc_interface_0_result_ch0_o_7, 
        adc_interface_0_result_ch0_o_0 => 
        adc_interface_0_result_ch0_o_0, 
        adc_interface_0_result_ch0_o_5 => 
        adc_interface_0_result_ch0_o_5, 
        adc_interface_0_result_ch0_o_8 => 
        adc_interface_0_result_ch0_o_8, 
        adc_interface_0_result_ch0_o_9 => 
        adc_interface_0_result_ch0_o_9, ADC_SCALING_0_ia_adc_o_0
         => ADC_SCALING_0_ia_adc_o_0, ADC_SCALING_0_ia_adc_o_7
         => ADC_SCALING_0_ia_adc_o_7, ADC_SCALING_0_ia_adc_o_10
         => ADC_SCALING_0_ia_adc_o_10, ADC_SCALING_0_ia_adc_o_2
         => ADC_SCALING_0_ia_adc_o_2, ADC_SCALING_0_ia_adc_o_5
         => ADC_SCALING_0_ia_adc_o_5, ADC_SCALING_0_ia_adc_o_8
         => ADC_SCALING_0_ia_adc_o_8, ADC_SCALING_0_ia_adc_o_9
         => ADC_SCALING_0_ia_adc_o_9, ADC_SCALING_0_ia_adc_o_12
         => ADC_SCALING_0_ia_adc_o_12, ADC_SCALING_0_ia_adc_o_15
         => ADC_SCALING_0_ia_adc_o_15, ADC_SCALING_0_ia_adc_o_4
         => ADC_SCALING_0_ia_adc_o_4, ADC_SCALING_0_ia_adc_o_1
         => ADC_SCALING_0_ia_adc_o_1, ADC_SCALING_0_ia_adc_o_6
         => ADC_SCALING_0_ia_adc_o_6, ADC_SCALING_0_ia_adc_o_11
         => ADC_SCALING_0_ia_adc_o_11, 
        prdata_o_1_0_iv_0_1_o2_0(17) => 
        prdata_o_1_0_iv_0_1_o2_0(17), prdata_o_1_iv_0_0_11(3) => 
        prdata_o_1_iv_0_0_11(3), prdata_o_1_2_0_0_5(3) => 
        prdata_o_1_2_0_0_5(3), ADC_SCALING_0_ib_adc_o_10 => 
        ADC_SCALING_0_ib_adc_o_10, ADC_SCALING_0_ib_adc_o_5 => 
        ADC_SCALING_0_ib_adc_o_5, ADC_SCALING_0_ib_adc_o_4 => 
        ADC_SCALING_0_ib_adc_o_4, ADC_SCALING_0_ib_adc_o_7 => 
        ADC_SCALING_0_ib_adc_o_7, ADC_SCALING_0_ib_adc_o_8 => 
        ADC_SCALING_0_ib_adc_o_8, ADC_SCALING_0_ib_adc_o_11 => 
        ADC_SCALING_0_ib_adc_o_11, ADC_SCALING_0_ib_adc_o_14 => 
        ADC_SCALING_0_ib_adc_o_14, ADC_SCALING_0_ib_adc_o_3 => 
        ADC_SCALING_0_ib_adc_o_3, ADC_SCALING_0_ib_adc_o_0 => 
        ADC_SCALING_0_ib_adc_o_0, prdata_o_1_iv_0_0_0_3_tz(1) => 
        prdata_o_1_iv_0_0_0_3_tz(1), prdata_o_1_0_1(16) => 
        prdata_o_1_0_1(16), prdata_o_1_0_2(16) => 
        prdata_o_1_0_2(16), prdata_o_1_0_0(16) => 
        prdata_o_1_0_0(16), prdata_o_1_3_0_0_2(11) => 
        prdata_o_1_3_0_0_2(11), prdata_o_1_3_0_0_3(11) => 
        prdata_o_1_3_0_0_3(11), prdata_o_1_3_0_0_0(11) => 
        prdata_o_1_3_0_0_0(11), prdata_o_1_8_2(6) => 
        prdata_o_1_8_2(6), prdata_o_1_8_3(6) => prdata_o_1_8_3(6), 
        prdata_o_1_8_0(6) => prdata_o_1_8_0(6), 
        prdata_o_1_iv_0_0_12_4_3(3) => 
        prdata_o_1_iv_0_0_12_4_3(3), prdata_o_1_iv_0_0_12_4_2(3)
         => prdata_o_1_iv_0_0_12_4_2(3), prdata_o_1_0_iv_0_5_1
         => prdata_o_1_0_iv_0_5_1, prdata_o_1_0_iv_0_5_4 => 
        prdata_o_1_0_iv_0_5_4, prdata_o_1_0_iv_0_5_2 => 
        prdata_o_1_0_iv_0_5_2, prdata_o_1_0_iv_0_5_7 => 
        prdata_o_1_0_iv_0_5_7, prdata_o_1_0_iv_0_5_5 => 
        prdata_o_1_0_iv_0_5_5, prdata_o_1_0_iv_0_5_0 => 
        prdata_o_1_0_iv_0_5_0, prdata_o_1_0_iv_0_5_12 => 
        prdata_o_1_0_iv_0_5_12, prdata_o_1_0_iv_0_6(16) => 
        prdata_o_1_0_iv_0_6(16), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14, USB_ULPI_DATA(7) => 
        USB_ULPI_DATA(7), USB_ULPI_DATA(6) => USB_ULPI_DATA(6), 
        USB_ULPI_DATA(5) => USB_ULPI_DATA(5), USB_ULPI_DATA(4)
         => USB_ULPI_DATA(4), USB_ULPI_DATA(3) => 
        USB_ULPI_DATA(3), USB_ULPI_DATA(2) => USB_ULPI_DATA(2), 
        USB_ULPI_DATA(1) => USB_ULPI_DATA(1), USB_ULPI_DATA(0)
         => USB_ULPI_DATA(0), MC_System_0_AMBA_SLAVE_1_PADDR(11)
         => MC_System_0_AMBA_SLAVE_1_PADDR(11), 
        MC_System_0_AMBA_SLAVE_1_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), 
        MC_System_0_AMBA_SLAVE_1_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), 
        MC_System_0_AMBA_SLAVE_1_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        MC_System_0_AMBA_SLAVE_1_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), 
        MC_System_0_AMBA_SLAVE_1_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), 
        MC_System_0_AMBA_SLAVE_1_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), 
        MC_System_0_AMBA_SLAVE_1_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), 
        MC_System_0_AMBA_SLAVE_1_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        MC_System_0_AMBA_SLAVE_1_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        MC_System_0_AMBA_SLAVE_1_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK => MC_System_0_FIC_0_CLK, 
        MC_System_0_FAB_CCC_GL1 => MC_System_0_FAB_CCC_GL1, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, 
        MC_System_0_AMBA_SLAVE_1_PSELx => 
        MC_System_0_AMBA_SLAVE_1_PSELx, N_1342 => N_1342, N_2598
         => N_2598, N_2644 => N_2644, N_1396 => N_1396, N_2631
         => N_2631, prdata_m2_e_1_1 => prdata_m2_e_1_1, N_1360
         => N_1360, N_1288 => N_1288, prdata_m1_0_a2_0 => 
        prdata_m1_0_a2_0, N_522 => N_522, N_527 => N_527, N_542
         => N_542, prdata_m4_e_0 => prdata_m4_e_0, 
        prdata_m1_0_a2_2_0 => prdata_m1_0_a2_2_0, N_509 => N_509, 
        N_529 => N_529, N_503 => N_503, prdata_m2_e_0 => 
        prdata_m2_e_0, N_508 => N_508, N_2652 => N_2652, N_768
         => N_768, N_1345 => N_1345, N_2647 => N_2647, N_2531 => 
        N_2531, N_513 => N_513, N_502 => N_502, N_534 => N_534, 
        N_500 => N_500, N_514 => N_514, N_506 => N_506, N_505 => 
        N_505, N_518 => N_518, N_2574 => N_2574, N_1346 => N_1346, 
        N_531 => N_531, N_2640 => N_2640, N_738 => N_738, N_533
         => N_533, N_507 => N_507, prdata_m1_e_0_1 => 
        prdata_m1_e_0_1, N_1398 => N_1398, N_1378 => N_1378, 
        N_2627 => N_2627, prdata_m2_0_a2_0 => prdata_m2_0_a2_0, 
        N_455 => N_455, N_495 => N_495, N_892 => N_892, N_771 => 
        N_771, N_773 => N_773, N_750 => N_750, N_2639 => N_2639, 
        N_775 => N_775, N_763 => N_763, N_2645 => N_2645, N_1351
         => N_1351, N_1169 => N_1169, N_1279 => N_1279, N_793 => 
        N_793, N_791 => N_791, N_782 => N_782, N_893 => N_893, 
        N_788 => N_788, N_772 => N_772, N_749 => N_749, N_774 => 
        N_774, N_762 => N_762, N_1347 => N_1347, N_1165 => N_1165, 
        N_1275 => N_1275, N_792 => N_792, N_878 => N_878, N_859
         => N_859, N_880 => N_880, N_870 => N_870, 
        prdata_m2_e_0_0 => prdata_m2_e_0_0, prdata_m1_e_11_0 => 
        prdata_m1_e_11_0, N_414 => N_414, N_516 => N_516, N_397
         => N_397, N_355 => N_355, N_198 => N_198, m20_i_2_tz => 
        m20_i_2_tz, m20_i_a2_0_1 => m20_i_a2_0_1, m20_m2_0_a2_1
         => m20_m2_0_a2_1, N_349 => N_349, m20_i_a2_5_0 => 
        m20_i_a2_5_0, N_517 => N_517, N_128 => N_128, N_528 => 
        N_528, N_524 => N_524, N_454 => N_454, N_494 => N_494, 
        N_894 => N_894, N_1326 => N_1326, N_2646 => N_2646, N_770
         => N_770, N_777 => N_777, N_883 => N_883, N_1333 => 
        N_1333, N_790 => N_790, N_895 => N_895, N_769 => N_769, 
        N_776 => N_776, N_832 => N_832, N_1329 => N_1329, N_789
         => N_789, N_876 => N_876, N_882 => N_882, prdata_m3_i_0
         => prdata_m3_i_0, N_260 => N_260, N_766 => N_766, N_739
         => N_739, N_891 => N_891, N_767 => N_767, N_875 => N_875, 
        N_396 => N_396, N_405 => N_405, N_354 => N_354, N_363 => 
        N_363, prdata_N_7_2 => prdata_N_7_2, m20_i_10_1 => 
        m20_i_10_1, m20_i_10_0 => m20_i_10_0, N_215 => N_215, 
        N_377 => N_377, N_2495 => N_2495, N_2498 => N_2498, 
        m20_i_11_5 => m20_i_11_5, N_122 => N_122, N_317 => N_317, 
        N_318 => N_318, N_319 => N_319, N_320 => N_320, N_321 => 
        N_321, N_315 => N_315, USB_ULPI_XCLK => USB_ULPI_XCLK, 
        USB_ULPI_STP => USB_ULPI_STP, USB_ULPI_NXT => 
        USB_ULPI_NXT, USB_ULPI_DIR => USB_ULPI_DIR, 
        MC_System_0_AMBA_SLAVE_1_PENABLE => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, 
        MC_System_0_AMBA_SLAVE_1_PWRITE => 
        MC_System_0_AMBA_SLAVE_1_PWRITE, GPIO_0_M2F_c => 
        GPIO_0_M2F_c);
    
    GND_Z : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity pi_scheduler_spi_0 is

    port( s_pi_sel_fast_1      : out   std_logic;
          s_pi_sel_i_0         : out   std_logic_vector(1 to 1);
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          s_init               : out   std_logic_vector(17 downto 0);
          s_output_y           : in    std_logic_vector(17 downto 0);
          s_acc_out            : in    std_logic_vector(43 downto 0);
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0);
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0);
          speed_pi_ref_input_i : in    std_logic_vector(16 downto 0);
          iq_pi_ref_input_i    : in    std_logic_vector(16 downto 0);
          speed_init_i         : in    std_logic_vector(17 downto 0);
          iq_init_i            : in    std_logic_vector(17 downto 0);
          id_pi_act_input_i    : in    std_logic_vector(16 downto 0);
          s_act_input          : out   std_logic_vector(16 downto 0);
          s_acc_in             : out   std_logic_vector(43 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          id_pi_done_o         : out   std_logic;
          s_done               : in    std_logic;
          iq_pi_done_o         : out   std_logic;
          s_start              : out   std_logic;
          s_pi_sel_1_rep1      : out   std_logic;
          s_pi_sel_0_rep1      : out   std_logic;
          s_pi_sel_0_rep2      : out   std_logic;
          speed_en_i           : in    std_logic;
          idq_en_i             : in    std_logic;
          s_en                 : out   std_logic;
          clear_buffer_i       : in    std_logic;
          speed_pi_start_i     : in    std_logic;
          iq_pi_start_i        : in    std_logic;
          N_1337               : out   std_logic;
          N_1336               : out   std_logic;
          N_1335               : out   std_logic;
          N_1334               : out   std_logic;
          N_1333               : out   std_logic;
          N_1332               : out   std_logic;
          N_1330               : out   std_logic;
          N_1329               : out   std_logic;
          N_1328               : out   std_logic;
          N_1327               : out   std_logic;
          N_1326               : out   std_logic;
          N_1325               : out   std_logic;
          N_1324               : out   std_logic;
          N_1323               : out   std_logic;
          N_1322               : out   std_logic;
          N_1320               : out   std_logic;
          un3_init_o           : out   std_logic;
          N_1423               : out   std_logic;
          N_1354               : out   std_logic;
          N_1353               : out   std_logic;
          N_1352               : out   std_logic;
          N_1351               : out   std_logic;
          N_1350               : out   std_logic;
          N_1349               : out   std_logic;
          N_1348               : out   std_logic;
          N_1347               : out   std_logic;
          N_1346               : out   std_logic;
          N_1345               : out   std_logic;
          N_1344               : out   std_logic;
          N_1343               : out   std_logic;
          N_1342               : out   std_logic;
          N_1341               : out   std_logic;
          N_1340               : out   std_logic;
          N_1339               : out   std_logic;
          N_1338               : out   std_logic;
          N_1331               : out   std_logic;
          N_1321               : out   std_logic;
          id_pi_start_i        : in    std_logic
        );

end pi_scheduler_spi_0;

architecture DEF_ARCH of pi_scheduler_spi_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \s_pi_sel_i_0\ : std_logic_vector(1 to 1);
    signal MSC_net_319, MSC_net_322, MSC_net_324, MSC_net_326, 
        MSC_net_327, MSC_net_328, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, MSC_net_350 : std_logic;
    signal s_speed_pi_acc_in : std_logic_vector(43 downto 0);
    signal s_speed_pi_acc_in_4 : std_logic_vector(43 downto 0);
    signal s_pi_sel : std_logic_vector(1 downto 0);
    signal s_pi_sel_dly : std_logic_vector(1 downto 0);
    signal s_iq_acc_in : std_logic_vector(43 downto 0);
    signal s_id_acc_in : std_logic_vector(43 downto 0);
    signal speed_pi_output_y_o_5 : std_logic_vector(17 downto 0);
    signal s_pi_sel_fast : std_logic_vector(0 to 0);
    signal MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, MSC_net_591, 
        MSC_net_592, MSC_net_593, MSC_net_594, MSC_net_595, 
        MSC_net_596, MSC_net_597, MSC_net_598, MSC_net_599, 
        MSC_net_600, MSC_net_601, MSC_net_602, MSC_net_603, 
        MSC_net_604, MSC_net_605, MSC_net_606, MSC_net_607, 
        MSC_net_608, MSC_net_609, MSC_net_610, MSC_net_611, 
        MSC_net_612, MSC_net_613, MSC_net_614, MSC_net_615, 
        MSC_net_616, MSC_net_617, MSC_net_618, MSC_net_619, 
        MSC_net_620, MSC_net_621, MSC_net_622, MSC_net_623, 
        MSC_net_624, MSC_net_625, MSC_net_626, MSC_net_627, 
        MSC_net_628, MSC_net_629, MSC_net_630, MSC_net_631, 
        MSC_net_632, MSC_net_633, MSC_net_634, MSC_net_635, 
        MSC_net_636, MSC_net_637, MSC_net_638, MSC_net_639, 
        MSC_net_640, MSC_net_641, MSC_net_642, MSC_net_643, 
        MSC_net_644, MSC_net_645, MSC_net_646, MSC_net_647, 
        MSC_net_648, MSC_net_649, MSC_net_650, MSC_net_651, 
        MSC_net_652 : std_logic;

begin 

    s_pi_sel_fast_1 <= MSC_net_319;
    s_pi_sel_i_0(1) <= \s_pi_sel_i_0\(1);
    id_pi_done_o <= MSC_net_322;
    iq_pi_done_o <= MSC_net_324;
    s_pi_sel_1_rep1 <= MSC_net_326;
    s_pi_sel_0_rep1 <= MSC_net_327;
    s_pi_sel_0_rep2 <= MSC_net_328;
    N_1337 <= MSC_net_335;
    N_1336 <= MSC_net_336;
    N_1335 <= MSC_net_337;
    N_1334 <= MSC_net_338;
    N_1333 <= MSC_net_339;
    N_1332 <= MSC_net_340;
    N_1330 <= MSC_net_341;
    N_1329 <= MSC_net_342;
    N_1328 <= MSC_net_343;
    N_1327 <= MSC_net_344;
    N_1326 <= MSC_net_345;
    N_1325 <= MSC_net_346;
    N_1324 <= MSC_net_347;
    N_1323 <= MSC_net_348;
    N_1322 <= MSC_net_349;
    N_1320 <= MSC_net_350;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
f1QUgbIu1MDNGAMNSlnL3UDfPuLJYbblieaRpnl4Q5B5NJ3czreBPcXGKa6nmGEk
Cn26Rsxl+UUYZcoAXkdH3ejkWwWvRcJ1QAXpitI8/ML9si5Rg2h0NcKX1umwKBQt
91Fd3ghh3hv9hEPsioS7Rbk7nnsBnbyXbur1xb8apac=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=133120)
`protect data_block
[encoded data, 131072 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_pi_spi_0 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_pi_spi_0;

architecture DEF_ARCH of mas_pi_spi_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_174, MSC_net_175, MSC_net_176 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
Qz3Q0cfxbgTLF9k8b0vsBT092E2/qlQzQz3EqxxpgA7Plr2bPctP47tvslme1PWB
pvWk8PyT3MPhMiJ+ISCMWeSKfQyZMpw+tBjiqrMbykdC9lOKr1plnUnj9N09pODA
BacfIm12/KO4wDZwnrfeNw3z5DuJz9xd7dRT0XXmwv4=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12005)
`protect data_block
[encoded data, 11776 characters]
nXlncNBPbZ132PTXXtgNhwHgJ6O1aJz4FU0DFEhgfAk=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity pi_controller_spi_0 is

    port( s_acc_in_0           : in    std_logic_vector(43 downto 0);
          s_acc_out            : out   std_logic_vector(43 downto 0);
          s_output_y           : out   std_logic_vector(17 downto 0);
          s_init               : in    std_logic_vector(17 downto 0);
          s_pi_sel_fast        : in    std_logic_vector(1 to 1);
          id_pi_act_input_i    : in    std_logic_vector(17 to 17);
          s_act_input          : in    std_logic_vector(16 downto 0);
          s_pi_sel_i_0         : in    std_logic_vector(1 to 1);
          iq_pi_ref_input_i    : in    std_logic_vector(17 to 17);
          speed_pi_ref_input_i : in    std_logic_vector(17 to 17);
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0);
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0);
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0);
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          s_done               : out   std_logic;
          s_en                 : in    std_logic;
          N_1338               : in    std_logic;
          N_1339               : in    std_logic;
          N_1340               : in    std_logic;
          N_1341               : in    std_logic;
          N_1342               : in    std_logic;
          N_1343               : in    std_logic;
          N_1344               : in    std_logic;
          N_1345               : in    std_logic;
          N_1346               : in    std_logic;
          N_1347               : in    std_logic;
          N_1348               : in    std_logic;
          N_1349               : in    std_logic;
          N_1350               : in    std_logic;
          N_1351               : in    std_logic;
          N_1352               : in    std_logic;
          N_1353               : in    std_logic;
          N_1423               : in    std_logic;
          s_pi_sel_1_rep1      : in    std_logic;
          N_1354               : in    std_logic;
          N_1320               : in    std_logic;
          N_1321               : in    std_logic;
          N_1322               : in    std_logic;
          N_1323               : in    std_logic;
          N_1324               : in    std_logic;
          N_1325               : in    std_logic;
          N_1326               : in    std_logic;
          N_1327               : in    std_logic;
          N_1328               : in    std_logic;
          N_1329               : in    std_logic;
          N_1330               : in    std_logic;
          N_1331               : in    std_logic;
          N_1332               : in    std_logic;
          N_1333               : in    std_logic;
          N_1334               : in    std_logic;
          N_1335               : in    std_logic;
          N_1337               : in    std_logic;
          N_1336               : in    std_logic;
          s_pi_sel_0_rep1      : in    std_logic;
          s_pi_sel_0_rep2      : in    std_logic;
          un3_init_o           : in    std_logic;
          s_start              : in    std_logic
        );

end pi_controller_spi_0;

architecture DEF_ARCH of pi_controller_spi_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component mas_pi_spi_0
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_inew_RNIKNMR_Y : std_logic_vector(16 to 16);
    signal s_piout_i : std_logic_vector(16 downto 0);
    signal s_piout : std_logic_vector(34 downto 1);
    signal s_acc_in : std_logic_vector(43 downto 0);
    signal s_inew : std_logic_vector(43 downto 0);
    signal s_product : std_logic_vector(43 downto 0);
    signal s_pout : std_logic_vector(43 downto 10);
    signal s_mult1_input : std_logic_vector(17 downto 0);
    signal s_mult1_input_6 : std_logic_vector(17 downto 0);
    signal s_add_cin : std_logic_vector(43 downto 0);
    signal s_add_cin_5 : std_logic_vector(43 downto 0);
    signal s_i_init_ds : std_logic_vector(17 downto 0);
    signal s_i_init_ds_2 : std_logic_vector(17 downto 1);
    signal s_state : std_logic_vector(4 downto 0);
    signal s_mult0_input : std_logic_vector(17 downto 0);
    signal s_error : std_logic_vector(17 downto 1);
    signal acc_out_o_3 : std_logic_vector(43 downto 0);
    signal output_y_o_5 : std_logic_vector(17 downto 1);
    signal s_state_ns : std_logic_vector(1 to 1);
    signal s_inew_RNIKNMR_S : std_logic_vector(16 to 16);
    signal s_pout_RNIBIDN1_Y : std_logic_vector(11 to 11);
    signal s_pout_RNI5G4J2_Y : std_logic_vector(12 to 12);
    signal s_pout_RNI2HRE3_Y : std_logic_vector(13 to 13);
    signal s_pout_RNIPCJA4_Y : std_logic_vector(14 to 14);
    signal s_pout_RNIJBB65_Y : std_logic_vector(15 to 15);
    signal s_pout_RNIGD326_Y : std_logic_vector(16 to 16);
    signal s_pout_RNIGIRT6_Y : std_logic_vector(17 to 17);
    signal s_pout_RNIJQJP7_Y : std_logic_vector(18 to 18);
    signal s_pout_RNIP5CL8_Y : std_logic_vector(19 to 19);
    signal s_pout_RNI040G9_Y : std_logic_vector(20 to 20);
    signal s_pout_RNIA5KAA_Y : std_logic_vector(21 to 21);
    signal s_pout_RNIN985B_Y : std_logic_vector(22 to 22);
    signal s_pout_RNI7HSVB_Y : std_logic_vector(23 to 23);
    signal s_pout_RNIHJHQC_Y : std_logic_vector(24 to 24);
    signal s_pout_RNIUO6LD_Y : std_logic_vector(25 to 25);
    signal s_pout_RNIE1SFE_Y : std_logic_vector(26 to 26);
    signal s_pout_RNI1DHAF_Y : std_logic_vector(27 to 27);
    signal s_pout_RNIMQ65G_Y : std_logic_vector(28 to 28);
    signal s_pout_RNIDASVG_Y : std_logic_vector(29 to 29);
    signal s_pout_RNITJIQH_Y : std_logic_vector(30 to 30);
    signal s_pout_RNIFV8LI_Y : std_logic_vector(31 to 31);
    signal s_pout_RNI3DVFJ_Y : std_logic_vector(32 to 32);
    signal s_pout_RNIPSLAK_Y : std_logic_vector(33 to 33);
    signal s_pout_RNI86D5L_Y : std_logic_vector(34 to 34);
    signal s_pout_RNIPH40M_Y : std_logic_vector(35 to 35);
    signal s_pout_RNICVRQM_Y : std_logic_vector(36 to 36);
    signal s_pout_RNI1FJLN_Y : std_logic_vector(37 to 37);
    signal s_pout_RNINVAGO_Y : std_logic_vector(38 to 38);
    signal s_pout_RNIEH2BP_Y : std_logic_vector(39 to 39);
    signal s_pout_RNITRQ5Q_Y : std_logic_vector(40 to 40);
    signal s_pout_RNID7J0R_Y : std_logic_vector(41 to 41);
    signal s_pout_RNIUJBRR_Y : std_logic_vector(42 to 42);
    signal s_pout_RNI2FSGT_FCO : std_logic_vector(43 to 43);
    signal s_pout_RNI2FSGT_Y : std_logic_vector(43 to 43);
    signal s_pout_RNIG14MS_Y : std_logic_vector(43 to 43);
    signal s_piout_0 : std_logic_vector(0 to 0);
    signal s_mult1_input_6_1_1 : std_logic_vector(17 downto 0);
    signal s_state_ns_i_0 : std_logic_vector(0 to 0);
    signal s_iout : std_logic_vector(42 downto 0);
    signal acc_out_o_3_b_A : std_logic_vector(43 to 43);
    signal MSC_net_842, MSC_net_843, MSC_net_844, MSC_net_845, 
        MSC_net_846, MSC_net_847, MSC_net_848, MSC_net_849, 
        MSC_net_850, MSC_net_851, MSC_net_852, MSC_net_853, 
        MSC_net_854, MSC_net_855, MSC_net_856, MSC_net_857, 
        MSC_net_858, MSC_net_859, MSC_net_860, MSC_net_861, 
        MSC_net_862, MSC_net_863, MSC_net_864, MSC_net_865, 
        MSC_net_866, MSC_net_867, MSC_net_868, MSC_net_869, 
        MSC_net_870, MSC_net_871, MSC_net_872, MSC_net_873, 
        MSC_net_874, MSC_net_875, MSC_net_876, MSC_net_877, 
        MSC_net_878, MSC_net_879, MSC_net_880, MSC_net_881, 
        MSC_net_882, MSC_net_883, MSC_net_884, MSC_net_885, 
        MSC_net_886, MSC_net_887, MSC_net_888, MSC_net_889, 
        MSC_net_890, MSC_net_891, MSC_net_892, MSC_net_893, 
        MSC_net_894, MSC_net_895, MSC_net_896, MSC_net_897, 
        MSC_net_898, MSC_net_899, MSC_net_900, MSC_net_901, 
        MSC_net_902, MSC_net_903, MSC_net_904, MSC_net_905, 
        MSC_net_906, MSC_net_907, MSC_net_908, MSC_net_909, 
        MSC_net_910, MSC_net_911, MSC_net_912, MSC_net_913, 
        MSC_net_914, MSC_net_915, MSC_net_916, MSC_net_917, 
        MSC_net_918, MSC_net_919, MSC_net_920, MSC_net_921, 
        MSC_net_922, MSC_net_923, MSC_net_924, MSC_net_925, 
        MSC_net_926, MSC_net_927, MSC_net_928, MSC_net_929, 
        MSC_net_930, MSC_net_931, MSC_net_932, MSC_net_933, 
        MSC_net_934, MSC_net_935, MSC_net_936, MSC_net_937, 
        MSC_net_938, MSC_net_939, MSC_net_940, MSC_net_941, 
        MSC_net_942, MSC_net_943, MSC_net_944, MSC_net_945, 
        MSC_net_946, MSC_net_947, MSC_net_948, MSC_net_949, 
        MSC_net_950, MSC_net_951, MSC_net_952, MSC_net_953, 
        MSC_net_954, MSC_net_955, MSC_net_956, MSC_net_957, 
        MSC_net_958, MSC_net_959, MSC_net_960, MSC_net_961, 
        MSC_net_962, MSC_net_963, MSC_net_964, MSC_net_965, 
        MSC_net_966, MSC_net_967, MSC_net_968, MSC_net_969, 
        MSC_net_970, MSC_net_971, MSC_net_972, MSC_net_973, 
        MSC_net_974, MSC_net_975, MSC_net_976, MSC_net_977, 
        MSC_net_978, MSC_net_979, MSC_net_980, MSC_net_981, 
        MSC_net_982, MSC_net_983, MSC_net_984, MSC_net_985, 
        MSC_net_986, MSC_net_987, MSC_net_988, MSC_net_989, 
        MSC_net_990, MSC_net_991, MSC_net_992, MSC_net_993, 
        MSC_net_994, MSC_net_995, MSC_net_996, MSC_net_997, 
        MSC_net_998, MSC_net_999, MSC_net_1000, MSC_net_1001, 
        MSC_net_1002, MSC_net_1003, MSC_net_1004, MSC_net_1005, 
        MSC_net_1006, MSC_net_1007, MSC_net_1008, MSC_net_1009, 
        MSC_net_1010, MSC_net_1011, MSC_net_1012, MSC_net_1013, 
        MSC_net_1014, MSC_net_1015, MSC_net_1016, MSC_net_1017, 
        MSC_net_1018, MSC_net_1019, MSC_net_1020, MSC_net_1021, 
        MSC_net_1022, MSC_net_1023, MSC_net_1024, MSC_net_1025, 
        MSC_net_1026, MSC_net_1027, MSC_net_1028, MSC_net_1029, 
        MSC_net_1030, MSC_net_1031, MSC_net_1032, MSC_net_1033, 
        MSC_net_1034, MSC_net_1035, MSC_net_1036, MSC_net_1037, 
        MSC_net_1038, MSC_net_1039, MSC_net_1040, MSC_net_1041, 
        MSC_net_1042, MSC_net_1043, MSC_net_1044, MSC_net_1045, 
        MSC_net_1046, MSC_net_1047, MSC_net_1048, MSC_net_1049, 
        MSC_net_1050, MSC_net_1051, MSC_net_1052, MSC_net_1053, 
        MSC_net_1054, MSC_net_1055, MSC_net_1056, MSC_net_1057, 
        MSC_net_1058, MSC_net_1059, MSC_net_1060, MSC_net_1061, 
        MSC_net_1062, MSC_net_1063, MSC_net_1064, MSC_net_1065, 
        MSC_net_1066, MSC_net_1067, MSC_net_1068, MSC_net_1069, 
        MSC_net_1070, MSC_net_1071, MSC_net_1072, MSC_net_1073, 
        MSC_net_1074, MSC_net_1075, MSC_net_1076, MSC_net_1077, 
        MSC_net_1078, MSC_net_1079, MSC_net_1080, MSC_net_1081, 
        MSC_net_1082, MSC_net_1083, MSC_net_1084, MSC_net_1085, 
        MSC_net_1086, MSC_net_1087, MSC_net_1088, MSC_net_1089, 
        MSC_net_1090, MSC_net_1091, MSC_net_1092, MSC_net_1093, 
        MSC_net_1094, MSC_net_1095, MSC_net_1096, MSC_net_1097, 
        MSC_net_1098, MSC_net_1099, MSC_net_1100, MSC_net_1101, 
        MSC_net_1102, MSC_net_1103, MSC_net_1104, MSC_net_1105, 
        MSC_net_1106, MSC_net_1107, MSC_net_1108, MSC_net_1109, 
        MSC_net_1110, MSC_net_1111, MSC_net_1112, MSC_net_1113, 
        MSC_net_1114, MSC_net_1115, MSC_net_1116, MSC_net_1117, 
        MSC_net_1118, MSC_net_1119, MSC_net_1120, MSC_net_1121, 
        MSC_net_1122, MSC_net_1123, MSC_net_1124, MSC_net_1125, 
        MSC_net_1126, MSC_net_1127, MSC_net_1128, MSC_net_1129, 
        MSC_net_1130, MSC_net_1131, MSC_net_1132, MSC_net_1133, 
        MSC_net_1134, MSC_net_1135, MSC_net_1136, MSC_net_1137, 
        MSC_net_1138, MSC_net_1139, MSC_net_1140, MSC_net_1141, 
        MSC_net_1142, MSC_net_1143, MSC_net_1144, MSC_net_1145, 
        MSC_net_1146, MSC_net_1147, MSC_net_1148, MSC_net_1149, 
        MSC_net_1150, MSC_net_1151, MSC_net_1152, MSC_net_1153, 
        MSC_net_1154, MSC_net_1155, MSC_net_1156, MSC_net_1157, 
        MSC_net_1158, MSC_net_1159, MSC_net_1160, MSC_net_1161, 
        MSC_net_1162, MSC_net_1163, MSC_net_1164, MSC_net_1165, 
        MSC_net_1166, MSC_net_1167, MSC_net_1168, MSC_net_1169, 
        MSC_net_1170, MSC_net_1171, MSC_net_1172, MSC_net_1173, 
        MSC_net_1174, MSC_net_1175, MSC_net_1176, MSC_net_1177, 
        MSC_net_1178, MSC_net_1179, MSC_net_1180, MSC_net_1181, 
        MSC_net_1182, MSC_net_1183, MSC_net_1184, MSC_net_1185, 
        MSC_net_1186, MSC_net_1187, MSC_net_1188, MSC_net_1189, 
        MSC_net_1190, MSC_net_1191, MSC_net_1192, MSC_net_1193, 
        MSC_net_1194, MSC_net_1195, MSC_net_1196, MSC_net_1197, 
        MSC_net_1198 : std_logic;

    for all : mas_pi_spi_0
	Use entity work.mas_pi_spi_0(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
TsBv0lZK+gIvJjUAdCJyl25kEpZ1t4eWxUVFBDklw8HNy/a2RfHzzZMhUvDgLNxE
wjLpppSt5ftBvTsCB/5N9eD1s9ZmloiLb1FGxKAprMTD5SzWpEKEgjNK1E4MHGlG
P5dalC264fw8Gpq1b9mIFdd4Pbpglx6tYO6Ysc25D5M=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=204165)
`protect data_block
[encoded data, 201024 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity SPEED_ID_IQ_PI_0 is

    port( reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          clear_buffer_i       : in    std_logic;
          speed_en_i           : in    std_logic;
          idq_en_i             : in    std_logic;
          speed_pi_start_i     : in    std_logic;
          id_pi_start_i        : in    std_logic;
          iq_pi_start_i        : in    std_logic;
          speed_init_i         : in    std_logic_vector(17 downto 0);
          id_init_i            : in    std_logic_vector(17 downto 0);
          iq_init_i            : in    std_logic_vector(17 downto 0);
          speed_pi_ref_input_i : in    std_logic_vector(17 downto 0);
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0);
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0);
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0);
          speed_pi_ymax_i      : in    std_logic_vector(17 downto 0);
          speed_pi_ymin_i      : in    std_logic_vector(17 downto 0);
          id_pi_ref_input_i    : in    std_logic_vector(17 downto 0);
          id_pi_act_input_i    : in    std_logic_vector(17 downto 0);
          id_pi_kp_i           : in    std_logic_vector(17 downto 0);
          id_pi_ki_i           : in    std_logic_vector(17 downto 0);
          idq_pi_ymax_i        : in    std_logic_vector(17 downto 0);
          idq_pi_ymin_i        : in    std_logic_vector(17 downto 0);
          iq_pi_ref_input_i    : in    std_logic_vector(17 downto 0);
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0);
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0);
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0);
          speed_pi_done_o      : out   std_logic;
          id_pi_done_o         : out   std_logic;
          iq_pi_done_o         : out   std_logic;
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0)
        );

end SPEED_ID_IQ_PI_0;

architecture DEF_ARCH of SPEED_ID_IQ_PI_0 is 

  component pi_scheduler_spi_0
    port( s_pi_sel_fast_1      : out   std_logic;
          s_pi_sel_i_0         : out   std_logic_vector(1 to 1);
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          s_init               : out   std_logic_vector(17 downto 0);
          s_output_y           : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_acc_out            : in    std_logic_vector(43 downto 0) := (others => 'U');
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ref_input_i : in    std_logic_vector(16 downto 0) := (others => 'U');
          iq_pi_ref_input_i    : in    std_logic_vector(16 downto 0) := (others => 'U');
          speed_init_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_init_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_act_input_i    : in    std_logic_vector(16 downto 0) := (others => 'U');
          s_act_input          : out   std_logic_vector(16 downto 0);
          s_acc_in             : out   std_logic_vector(43 downto 0);
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          id_pi_done_o         : out   std_logic;
          s_done               : in    std_logic := 'U';
          iq_pi_done_o         : out   std_logic;
          s_start              : out   std_logic;
          s_pi_sel_1_rep1      : out   std_logic;
          s_pi_sel_0_rep1      : out   std_logic;
          s_pi_sel_0_rep2      : out   std_logic;
          speed_en_i           : in    std_logic := 'U';
          idq_en_i             : in    std_logic := 'U';
          s_en                 : out   std_logic;
          clear_buffer_i       : in    std_logic := 'U';
          speed_pi_start_i     : in    std_logic := 'U';
          iq_pi_start_i        : in    std_logic := 'U';
          N_1337               : out   std_logic;
          N_1336               : out   std_logic;
          N_1335               : out   std_logic;
          N_1334               : out   std_logic;
          N_1333               : out   std_logic;
          N_1332               : out   std_logic;
          N_1330               : out   std_logic;
          N_1329               : out   std_logic;
          N_1328               : out   std_logic;
          N_1327               : out   std_logic;
          N_1326               : out   std_logic;
          N_1325               : out   std_logic;
          N_1324               : out   std_logic;
          N_1323               : out   std_logic;
          N_1322               : out   std_logic;
          N_1320               : out   std_logic;
          un3_init_o           : out   std_logic;
          N_1423               : out   std_logic;
          N_1354               : out   std_logic;
          N_1353               : out   std_logic;
          N_1352               : out   std_logic;
          N_1351               : out   std_logic;
          N_1350               : out   std_logic;
          N_1349               : out   std_logic;
          N_1348               : out   std_logic;
          N_1347               : out   std_logic;
          N_1346               : out   std_logic;
          N_1345               : out   std_logic;
          N_1344               : out   std_logic;
          N_1343               : out   std_logic;
          N_1342               : out   std_logic;
          N_1341               : out   std_logic;
          N_1340               : out   std_logic;
          N_1339               : out   std_logic;
          N_1338               : out   std_logic;
          N_1331               : out   std_logic;
          N_1321               : out   std_logic;
          id_pi_start_i        : in    std_logic := 'U'
        );
  end component;

  component pi_controller_spi_0
    port( s_acc_in_0           : in    std_logic_vector(43 downto 0) := (others => 'U');
          s_acc_out            : out   std_logic_vector(43 downto 0);
          s_output_y           : out   std_logic_vector(17 downto 0);
          s_init               : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_pi_sel_fast        : in    std_logic_vector(1 to 1) := (others => 'U');
          id_pi_act_input_i    : in    std_logic_vector(17 to 17) := (others => 'U');
          s_act_input          : in    std_logic_vector(16 downto 0) := (others => 'U');
          s_pi_sel_i_0         : in    std_logic_vector(1 to 1) := (others => 'U');
          iq_pi_ref_input_i    : in    std_logic_vector(17 to 17) := (others => 'U');
          speed_pi_ref_input_i : in    std_logic_vector(17 to 17) := (others => 'U');
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          s_done               : out   std_logic;
          s_en                 : in    std_logic := 'U';
          N_1338               : in    std_logic := 'U';
          N_1339               : in    std_logic := 'U';
          N_1340               : in    std_logic := 'U';
          N_1341               : in    std_logic := 'U';
          N_1342               : in    std_logic := 'U';
          N_1343               : in    std_logic := 'U';
          N_1344               : in    std_logic := 'U';
          N_1345               : in    std_logic := 'U';
          N_1346               : in    std_logic := 'U';
          N_1347               : in    std_logic := 'U';
          N_1348               : in    std_logic := 'U';
          N_1349               : in    std_logic := 'U';
          N_1350               : in    std_logic := 'U';
          N_1351               : in    std_logic := 'U';
          N_1352               : in    std_logic := 'U';
          N_1353               : in    std_logic := 'U';
          N_1423               : in    std_logic := 'U';
          s_pi_sel_1_rep1      : in    std_logic := 'U';
          N_1354               : in    std_logic := 'U';
          N_1320               : in    std_logic := 'U';
          N_1321               : in    std_logic := 'U';
          N_1322               : in    std_logic := 'U';
          N_1323               : in    std_logic := 'U';
          N_1324               : in    std_logic := 'U';
          N_1325               : in    std_logic := 'U';
          N_1326               : in    std_logic := 'U';
          N_1327               : in    std_logic := 'U';
          N_1328               : in    std_logic := 'U';
          N_1329               : in    std_logic := 'U';
          N_1330               : in    std_logic := 'U';
          N_1331               : in    std_logic := 'U';
          N_1332               : in    std_logic := 'U';
          N_1333               : in    std_logic := 'U';
          N_1334               : in    std_logic := 'U';
          N_1335               : in    std_logic := 'U';
          N_1337               : in    std_logic := 'U';
          N_1336               : in    std_logic := 'U';
          s_pi_sel_0_rep1      : in    std_logic := 'U';
          s_pi_sel_0_rep2      : in    std_logic := 'U';
          un3_init_o           : in    std_logic := 'U';
          s_start              : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_acc_out : std_logic_vector(43 downto 0);
    signal s_output_y : std_logic_vector(17 downto 0);
    signal s_init : std_logic_vector(17 downto 0);
    signal s_acc_in : std_logic_vector(43 downto 0);
    signal s_act_input : std_logic_vector(16 downto 0);
    signal \PI_SCHEDULER_INST.s_pi_sel_i_0\ : 
        std_logic_vector(1 to 1);
    signal \PI_SCHEDULER_INST.s_pi_sel_fast\ : 
        std_logic_vector(1 to 1);
    signal MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        \PI_SCHEDULER_INST.op_eq.un3_init_o\, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, 
        \PI_SCHEDULER_INST.s_pi_sel_1_rep1\, 
        \PI_SCHEDULER_INST.s_pi_sel_0_rep1\, 
        \PI_SCHEDULER_INST.s_pi_sel_0_rep2\ : std_logic;

    for all : pi_scheduler_spi_0
	Use entity work.pi_scheduler_spi_0(DEF_ARCH);
    for all : pi_controller_spi_0
	Use entity work.pi_controller_spi_0(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
Onk1RsUXgnOCbOwf9ZWxq4UbRRHya8fkchnVnRGnEgM4e7BMfmQ/8oNsud6Hdspz
fYtTKXo6auMLpG/TbeoPY/IlN8qTvF3VaZ7OTQrZWXq98R2IB2bF2kGAE81SBC++
mOOK6NsneLjdBGJgBjI2DLos3/9CV1APXDOvQwU+WZ4=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=35600)
`protect data_block
[encoded data, 35008 characters]
fXe1AUcD6F1rlQkRUK39W/qKt4k1pnDMHIe8KxtCvhk=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity SVM is

    port( reset_i   : in    std_logic;
          sys_clk_i : in    std_logic;
          start_i   : in    std_logic;
          va_i      : in    std_logic_vector(17 downto 0);
          vb_i      : in    std_logic_vector(17 downto 0);
          vc_i      : in    std_logic_vector(17 downto 0);
          va3h_o    : out   std_logic_vector(17 downto 0);
          vb3h_o    : out   std_logic_vector(17 downto 0);
          vc3h_o    : out   std_logic_vector(17 downto 0);
          done_o    : out   std_logic
        );

end SVM;

architecture DEF_ARCH of SVM is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal s_min_value : std_logic_vector(17 downto 1);
    signal s_max_value : std_logic_vector(17 downto 0);
    signal \SVM_FSM_PROC.s_max_value_3\ : 
        std_logic_vector(17 downto 0);
    signal \SVM_FSM_PROC.s_min_value_4\ : 
        std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(1 downto 0);
    signal s_state_ns : std_logic_vector(0 to 0);
    signal \SVM_FSM_PROC.vc3h_o_1\ : 
        std_logic_vector(17 downto 1);
    signal \SVM_FSM_PROC.va3h_o_2\ : 
        std_logic_vector(17 downto 1);
    signal \SVM_FSM_PROC.vb3h_o_1\ : 
        std_logic_vector(17 downto 1);
    signal \SVM_FSM_PROC.s_min_value_4_3_ns_1\ : 
        std_logic_vector(17 downto 0);
    signal \SVM_FSM_PROC.s_max_value_3_3_ns_1\ : 
        std_logic_vector(17 downto 0);
    signal MSC_net_273, MSC_net_274, MSC_net_275, MSC_net_276, 
        MSC_net_277, MSC_net_278, MSC_net_279, MSC_net_280, 
        MSC_net_281, MSC_net_282, MSC_net_283, MSC_net_284, 
        MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        MSC_net_305, MSC_net_306, MSC_net_307, MSC_net_308, 
        MSC_net_309, MSC_net_310, MSC_net_311, MSC_net_312, 
        MSC_net_313, MSC_net_314, MSC_net_315, MSC_net_316, 
        MSC_net_317, MSC_net_318, MSC_net_319, MSC_net_320, 
        MSC_net_321, MSC_net_322, MSC_net_323, MSC_net_324, 
        MSC_net_325, MSC_net_326, MSC_net_327, MSC_net_328, 
        MSC_net_329, MSC_net_330, MSC_net_331, MSC_net_332, 
        MSC_net_333, MSC_net_334, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, \SVM_FSM_PROC.vc3h_o_1_cry_0_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_1_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_2_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_3_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_4_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_5_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_6_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_7_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_8_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_9_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_10_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_11_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_12_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_13_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_14_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_15_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_16_Z\, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        \SVM_FSM_PROC.va3h_o_2_cry_0_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_1_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_2_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_3_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_4_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_5_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_6_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_7_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_8_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_9_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_10_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_11_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_12_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_13_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_14_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_15_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_16_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_0_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_1_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_2_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_3_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_4_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_5_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_6_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_7_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_8_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_9_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_10_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_11_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_12_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_13_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_14_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_15_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_16_Z\, MSC_net_418, 
        \SVM_FSM_PROC.vc3h_o_1_axb_0_i_0_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_axb_0_i_0_Z\, 
        \SVM_FSM_PROC.va3h_o_2_axb_0_i_0_Z\, MSC_net_422, 
        MSC_net_423, MSC_net_424, MSC_net_425, MSC_net_426, 
        MSC_net_427, MSC_net_428, MSC_net_429, MSC_net_430, 
        MSC_net_431, MSC_net_432, MSC_net_433, MSC_net_434, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, MSC_net_442, 
        MSC_net_443, MSC_net_444, MSC_net_445, MSC_net_446, 
        MSC_net_447, MSC_net_448, MSC_net_449, MSC_net_450, 
        MSC_net_451, MSC_net_452, MSC_net_453, MSC_net_454, 
        MSC_net_455, MSC_net_456, MSC_net_457, MSC_net_458, 
        MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, MSC_net_470, 
        MSC_net_471, MSC_net_472, MSC_net_473, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488, MSC_net_489, MSC_net_490, 
        MSC_net_491, MSC_net_492, MSC_net_493, MSC_net_494, 
        MSC_net_495, MSC_net_496, MSC_net_497, MSC_net_498, 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, MSC_net_518, 
        MSC_net_519, MSC_net_520, MSC_net_521, MSC_net_522, 
        MSC_net_523, MSC_net_524, MSC_net_525, MSC_net_526, 
        MSC_net_527, MSC_net_528, MSC_net_529, 
        \SVM_FSM_PROC.vc3h_o_1_cry_16_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_s_17_FCO\, 
        \SVM_FSM_PROC.vc3h_o_1_s_17_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_15_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_14_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_13_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_12_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_11_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_10_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_9_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_8_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_7_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_6_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_5_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_4_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_3_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_2_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_1_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_0_S\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_0_Y\, MSC_net_550, MSC_net_551, 
        MSC_net_552, MSC_net_553, MSC_net_554, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, 
        \SVM_FSM_PROC.va3h_o_2_cry_16_Y\, 
        \SVM_FSM_PROC.va3h_o_2_s_17_FCO\, 
        \SVM_FSM_PROC.va3h_o_2_s_17_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_15_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_14_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_13_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_12_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_11_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_10_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_9_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_8_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_7_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_6_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_5_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_4_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_3_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_2_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_1_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_0_S\, 
        \SVM_FSM_PROC.va3h_o_2_cry_0_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_16_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_s_17_FCO\, 
        \SVM_FSM_PROC.vb3h_o_1_s_17_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_15_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_14_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_13_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_12_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_11_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_10_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_9_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_8_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_7_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_6_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_5_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_4_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_3_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_2_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_1_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_0_S\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_0_Y\ : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
Q6LrB8TgkLUvz+LKRH9ogLnpZwn3nfEokykBdm9Vy4tfQ/ISP60uPXb3IR8BwRB9
xv2L0piGeSTaFwJvJNe1xA2VZYPkKejT1jsAoW3mBIG+lOLw/B4/gspYJvIq2VPy
z4EUqO5MvoAT/Fd5uOE5yvaT1KaV/v9CkL2ZPH7BqcU=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=108095)
`protect data_block
[encoded data, 106432 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity PWM3PH_0 is

    port( reset_i        : in    std_logic;
          sys_clk_i      : in    std_logic;
          en_pwm_i       : in    std_logic;
          en_dual_trig_i : in    std_logic;
          va_i           : in    std_logic_vector(17 downto 0);
          vb_i           : in    std_logic_vector(17 downto 0);
          vc_i           : in    std_logic_vector(17 downto 0);
          pwm_period_i   : in    std_logic_vector(17 downto 0);
          dead_time_i    : in    std_logic_vector(17 downto 0);
          delay_time_i   : in    std_logic_vector(17 downto 0);
          midmatch_o     : out   std_logic;
          PWM_AH_o       : out   std_logic;
          PWM_BH_o       : out   std_logic;
          PWM_CH_o       : out   std_logic;
          PWM_AL_o       : out   std_logic;
          PWM_BL_o       : out   std_logic;
          PWM_CL_o       : out   std_logic
        );

end PWM3PH_0;

architecture DEF_ARCH of PWM3PH_0 is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal MSC_net_116 : std_logic;
    signal s_pwm_counter : std_logic_vector(16 downto 0);
    signal s_delay_counter : std_logic_vector(17 downto 0);
    signal \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4\ : 
        std_logic_vector(17 downto 1);
    signal \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_0_data_tmp\
         : std_logic_vector(8 downto 0);
    signal s_pwm_counter_cry : std_logic_vector(16 downto 0);
    signal s_pwm_counter_s : std_logic_vector(17 downto 0);
    signal s_delay_counter_s : std_logic_vector(17 downto 0);
    signal s_delay_counter_cry : std_logic_vector(16 downto 1);
    signal s_pwm_counter_Z : std_logic_vector(17 to 17);
    signal s_delay_counter_cry_Y : std_logic_vector(16 downto 1);
    signal s_delay_counter_s_FCO : std_logic_vector(17 to 17);
    signal s_delay_counter_s_Y : std_logic_vector(17 to 17);
    signal s_pwm_counter_cry_Y : std_logic_vector(16 downto 0);
    signal s_pwm_counter_s_FCO : std_logic_vector(17 to 17);
    signal s_pwm_counter_s_Y : std_logic_vector(17 to 17);
    signal MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i\, 
        \PWM_OUTPUT_GEN_PROC.va_i\, \PWM_OUTPUT_GEN_PROC.vb_i\, 
        \PWM_OUTPUT_GEN_PROC.vc_i\, MSC_net_309, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2\, MSC_net_313, MSC_net_314, 
        MSC_net_315, MSC_net_316, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_16_Z\, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_5_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_7_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_13_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_15_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_16_Z\, 
        MSC_net_474, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_15_Z\, 
        MSC_net_481, MSC_net_482, MSC_net_483, MSC_net_484, 
        MSC_net_485, MSC_net_486, MSC_net_487, MSC_net_488, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_RNIIS8A5_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_RNIIS8A5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_RNIV2JH4_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_RNIV2JH4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_RNIP1IO3_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_RNIP1IO3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_RNIR4HV2_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_RNIR4HV2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_RNI5CG62_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_RNI5CG62_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_RNIJ44P1_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_RNIJ44P1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_RNI91OB1_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_RNI91OB1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_RNI72CU_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_RNI72CU_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_RNID70H_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_RNID70H_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_17_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_17_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_0_Y\, MSC_net_759, 
        MSC_net_760, MSC_net_761, MSC_net_762, MSC_net_763, 
        MSC_net_764, MSC_net_765, MSC_net_766, MSC_net_767, 
        MSC_net_768, MSC_net_769, MSC_net_770, MSC_net_771, 
        MSC_net_772, MSC_net_773, MSC_net_774, MSC_net_775, 
        MSC_net_776, MSC_net_777, MSC_net_778, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_16_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_FCO\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_15_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_13_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_11_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_9_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_7_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_Y\, 
        MSC_net_799, MSC_net_800, MSC_net_801, MSC_net_802
         : std_logic;

begin 

    PWM_AL_o <= MSC_net_116;
    PWM_BL_o <= MSC_net_116;
    PWM_CL_o <= MSC_net_116;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
ZQqDKZ/sK1qHvL+yQ8OkgWa/1CpFIccT6YsnIXAEnlEKJFeamRErl/CQrkEwoKy8
wu+L6NrTgNOnFjsmjy3rIYzTqgoGQrKXgsyX0WcC2QxzQEdKo9l+XA92dHlRbbp0
w3epQQj6rXAGL6qVih1jwmQjTI8zdtJfWy9RfmznPqE=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=132820)
`protect data_block
[encoded data, 130752 characters]
zFTXnpNF9wcp0ko8qt40YQ==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_olmng is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_olmng;

architecture DEF_ARCH of mas_olmng is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(12) <= \product_o\(0);
    product_o(11) <= \product_o\(0);
    product_o(10) <= \product_o\(0);
    product_o(9) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
HtXwV3IPsy8xYRHQz5VTAp7crNAXfi8q2LF1lueZZlg0uATVmDG9lyxU9TGO4rTi
B/Rvf55upCk8a8GQPMvX7uEC/i5wYaSWTuU9mtOSXTtOFXA8Be6A31Z9irPMKc5e
kflz/d9CHG09/ch2UhiTBcvuKpKjcbDJHchYgGBrYWg=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12375)
`protect data_block
[encoded data, 12160 characters]
YfUMO/f/APeltdDcIXq3zg==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity accumulator_olmng is

    port( s_theta_buff   : out   std_logic_vector(17 downto 0);
          theta_o        : in    std_logic_vector(17 downto 0);
          reset_i        : in    std_logic;
          sys_clk_i      : in    std_logic;
          clear_buffer_i : in    std_logic;
          s_olmng_done   : in    std_logic
        );

end accumulator_olmng;

architecture DEF_ARCH of accumulator_olmng is 

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal theta_scl_buff_o_3 : std_logic_vector(17 downto 0);
    signal MSC_net_58, MSC_net_59, MSC_net_60 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
VMo9V/q5BtGe60yftFb58J73phILNVeYQArOdlFCgWOEw6Okm94y3BUbvPfnkCis
/esiDL6254MeGrKE9mCXgV9grIsuFhpSXcDBXtciERIxZva8FyYdysYViRtapqXx
AtbfbV4HYQgY6qRJBNEFtuElivW3FYTy4qXoNJlq9fk=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=10985)
`protect data_block
[encoded data, 10816 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity OLMNG is

    port( reset_i            : in    std_logic;
          sys_clk_i          : in    std_logic;
          start_i            : in    std_logic;
          clear_buffer_i     : in    std_logic;
          direction_config_i : in    std_logic;
          cl_status_i        : in    std_logic;
          theta_factor_i     : in    std_logic_vector(17 downto 0);
          speed_ref_i        : in    std_logic_vector(17 downto 0);
          dv_i               : in    std_logic_vector(17 downto 0);
          theta_cl_i         : in    std_logic_vector(17 downto 0);
          iq_ref_in_i        : in    std_logic_vector(17 downto 0);
          done_o             : out   std_logic;
          theta_o            : out   std_logic_vector(17 downto 0);
          init_speedpi_o     : out   std_logic_vector(17 downto 0);
          init_iqpi_o        : out   std_logic_vector(17 downto 0)
        );

end OLMNG;

architecture DEF_ARCH of OLMNG is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_olmng
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component accumulator_olmng
    port( s_theta_buff   : out   std_logic_vector(17 downto 0);
          theta_o        : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i        : in    std_logic := 'U';
          sys_clk_i      : in    std_logic := 'U';
          clear_buffer_i : in    std_logic := 'U';
          s_olmng_done   : in    std_logic := 'U'
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \theta_o\ : std_logic_vector(17 downto 0);
    signal MSC_net_150 : std_logic;
    signal s_mult0_input : std_logic_vector(17 downto 0);
    signal s_mult1_input : std_logic_vector(17 downto 0);
    signal s_addc_input : std_logic_vector(30 downto 13);
    signal s_product : std_logic_vector(30 downto 13);
    signal s_theta_buff : std_logic_vector(17 downto 0);
    signal s_theta_ol : std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(1 downto 0);
    signal s_state_d : std_logic_vector(2 to 2);
    signal s_state_ns : std_logic_vector(0 to 0);
    signal iq_ref_in_i_RNI4RTI3_S : std_logic_vector(0 to 0);
    signal init_speedpi_o_4 : std_logic_vector(17 downto 1);
    signal iq_ref_in_i_RNITO8O01_Y : std_logic_vector(16 to 16);
    signal init_speedpi_o_RNO_FCO : std_logic_vector(17 to 17);
    signal init_speedpi_o_RNO_Y : std_logic_vector(17 to 17);
    signal iq_ref_in_i_RNIM0K4V_Y : std_logic_vector(15 to 15);
    signal iq_ref_in_i_RNIG9VGT_Y : std_logic_vector(14 to 14);
    signal iq_ref_in_i_RNIBJATR_Y : std_logic_vector(13 to 13);
    signal iq_ref_in_i_RNI7UL9Q_Y : std_logic_vector(12 to 12);
    signal iq_ref_in_i_RNI4A1MO_Y : std_logic_vector(11 to 11);
    signal iq_ref_in_i_RNI2NC2N_Y : std_logic_vector(10 to 10);
    signal iq_ref_in_i_RNI15OEL_Y : std_logic_vector(9 to 9);
    signal iq_ref_in_i_RNI8S6FJ_Y : std_logic_vector(8 to 8);
    signal iq_ref_in_i_RNIGKLFH_Y : std_logic_vector(7 to 7);
    signal iq_ref_in_i_RNIPD4GF_Y : std_logic_vector(6 to 6);
    signal iq_ref_in_i_RNI38JGD_Y : std_logic_vector(5 to 5);
    signal iq_ref_in_i_RNIE32HB_Y : std_logic_vector(4 to 4);
    signal iq_ref_in_i_RNIQVGH9_Y : std_logic_vector(3 to 3);
    signal iq_ref_in_i_RNI7TVH7_Y : std_logic_vector(2 to 2);
    signal iq_ref_in_i_RNILREI5_Y : std_logic_vector(1 to 1);
    signal iq_ref_in_i_RNI4RTI3_Y : std_logic_vector(0 to 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_344, MSC_net_345, MSC_net_346, MSC_net_347, 
        MSC_net_348, MSC_net_349, MSC_net_350, MSC_net_351, 
        MSC_net_352, MSC_net_353, MSC_net_354, MSC_net_355, 
        MSC_net_356, MSC_net_357, MSC_net_358, MSC_net_359, 
        MSC_net_360, MSC_net_361, MSC_net_362, MSC_net_363, 
        MSC_net_364, MSC_net_365, MSC_net_366, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        MSC_net_384, MSC_net_385, MSC_net_386, MSC_net_387, 
        MSC_net_388, MSC_net_389, MSC_net_390, MSC_net_391, 
        MSC_net_392, MSC_net_393, MSC_net_394, MSC_net_395, 
        MSC_net_396, MSC_net_397, MSC_net_398, MSC_net_399, 
        MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, MSC_net_406, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431
         : std_logic;

    for all : mas_olmng
	Use entity work.mas_olmng(DEF_ARCH);
    for all : accumulator_olmng
	Use entity work.accumulator_olmng(DEF_ARCH);
begin 

    done_o <= MSC_net_150;
    theta_o(17) <= \theta_o\(17);
    theta_o(16) <= \theta_o\(16);
    theta_o(15) <= \theta_o\(15);
    theta_o(14) <= \theta_o\(14);
    theta_o(13) <= \theta_o\(13);
    theta_o(12) <= \theta_o\(12);
    theta_o(11) <= \theta_o\(11);
    theta_o(10) <= \theta_o\(10);
    theta_o(9) <= \theta_o\(9);
    theta_o(8) <= \theta_o\(8);
    theta_o(7) <= \theta_o\(7);
    theta_o(6) <= \theta_o\(6);
    theta_o(5) <= \theta_o\(5);
    theta_o(4) <= \theta_o\(4);
    theta_o(3) <= \theta_o\(3);
    theta_o(2) <= \theta_o\(2);
    theta_o(1) <= \theta_o\(1);
    theta_o(0) <= \theta_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
LftufDom7peyeoNrj4tCqoVjR0QgPGy2WG+eUp6XZkhpFP8BgyYMMihBamFBylF3
c3/8jOizHuZYImmTtF7dD22+7JSPS0L4M4k3MT7YlSwiDCYIt+VAiUysRPpZhccg
lQoWyLdrwcf1dA2EAFLMek2OGjy8wyFlwpzvOByHq1c=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=67970)
`protect data_block
[encoded data, 66880 characters]
pgu1zU2HQLHpEhGV88PsnP0dd6+6g5kWL7tMylBXuQc=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity accumulator_rl is

    port( s_ref_val_buf : out   std_logic_vector(17 downto 0);
          s_ramp_out    : in    std_logic_vector(17 downto 0);
          reset_i       : in    std_logic;
          sys_clk_i     : in    std_logic;
          reset_rl_i    : in    std_logic;
          s_rl_done     : in    std_logic
        );

end accumulator_rl;

architecture DEF_ARCH of accumulator_rl is 

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal rl_out_prev_o_3 : std_logic_vector(17 downto 0);
    signal MSC_net_58, MSC_net_59, MSC_net_60 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
ZqMuvZJYDixLE5LQ/xfBJyhamKoavTAOHTt9uLhU553Dr8bepsldiQ/KdvQg9Sxb
3WnT+eAN8xUMyB7sHNZMsODxE7yJcsqXWmmLX6v1/enYDMsnNIDooKTEayGqBJFz
6Tipi8sRramafRTJjI1x3iRAjMYsRQ0kz0UEG94QO6k=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=10685)
`protect data_block
[encoded data, 10496 characters]
vmJPp1DAKvvshBW+q49fJA==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity RATE_LIMITER is

    port( reset_i      : in    std_logic;
          sys_clk_i    : in    std_logic;
          start_i      : in    std_logic;
          soft_stop_i  : in    std_logic;
          reset_rl_i   : in    std_logic;
          direction_i  : in    std_logic;
          slew_count_i : in    std_logic_vector(17 downto 0);
          rate_count_i : in    std_logic_vector(17 downto 0);
          rl_in_i      : in    std_logic_vector(17 downto 0);
          rl_out_o     : out   std_logic_vector(17 downto 0);
          rl_done_o    : out   std_logic
        );

end RATE_LIMITER;

architecture DEF_ARCH of RATE_LIMITER is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component accumulator_rl
    port( s_ref_val_buf : out   std_logic_vector(17 downto 0);
          s_ramp_out    : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i       : in    std_logic := 'U';
          sys_clk_i     : in    std_logic := 'U';
          reset_rl_i    : in    std_logic := 'U';
          s_rl_done     : in    std_logic := 'U'
        );
  end component;

    signal \rl_out_o\ : std_logic_vector(17 downto 0);
    signal MSC_net_78 : std_logic;
    signal s_ref_val_buf : std_logic_vector(17 downto 0);
    signal s_set_ref : std_logic_vector(17 downto 0);
    signal s_count : std_logic_vector(18 downto 0);
    signal s_ramp_present_state : std_logic_vector(1 downto 0);
    signal s_ramp_present_state_ns : std_logic_vector(1 to 1);
    signal s_ramp_out_7 : std_logic_vector(17 downto 0);
    signal un1_s_ramp_out : std_logic_vector(17 downto 0);
    signal s_set_ref_4 : std_logic_vector(17 downto 0);
    signal s_rl_in : std_logic_vector(17 downto 1);
    signal \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref\ : 
        std_logic_vector(18 to 18);
    signal s_count_cry : std_logic_vector(17 downto 0);
    signal s_count_s : std_logic_vector(18 downto 0);
    signal s_ramp_present_state_i_0 : std_logic_vector(0 to 0);
    signal rate_count_i_i : std_logic_vector(0 to 0);
    signal s_count_i : std_logic_vector(0 to 0);
    signal un1_s_ramp_out_RNIEUSTL_Y : std_logic_vector(1 to 1);
    signal s_ramp_out_7_RNO_FCO : std_logic_vector(17 to 17);
    signal s_ramp_out_7_RNO_Y : std_logic_vector(17 to 17);
    signal un1_s_ramp_out_RNI4Q2KK_Y : std_logic_vector(2 to 2);
    signal un1_s_ramp_out_RNIRM8AJ_Y : std_logic_vector(3 to 3);
    signal un1_s_ramp_out_RNIJKE0I_Y : std_logic_vector(4 to 4);
    signal un1_s_ramp_out_RNICJKMG_Y : std_logic_vector(5 to 5);
    signal un1_s_ramp_out_RNI6JQCF_Y : std_logic_vector(6 to 6);
    signal un1_s_ramp_out_RNI1K03E_Y : std_logic_vector(7 to 7);
    signal un1_s_ramp_out_RNITL6PC_Y : std_logic_vector(8 to 8);
    signal un1_s_ramp_out_RNI8289B_Y : std_logic_vector(9 to 9);
    signal un1_s_ramp_out_RNIKF9P9_Y : 
        std_logic_vector(10 to 10);
    signal un1_s_ramp_out_RNIQTAJ8_Y : 
        std_logic_vector(11 to 11);
    signal un1_s_ramp_out_RNI1DCD7_Y : 
        std_logic_vector(12 to 12);
    signal un1_s_ramp_out_RNI9TD76_Y : 
        std_logic_vector(13 to 13);
    signal un1_s_ramp_out_RNIIEF15_Y : 
        std_logic_vector(14 to 14);
    signal un1_s_ramp_out_RNIS0HR3_Y : 
        std_logic_vector(15 to 15);
    signal un1_s_ramp_out_RNI7KIL2_Y : 
        std_logic_vector(16 to 16);
    signal un1_s_ramp_out_RNIJ8KF1_Y : 
        std_logic_vector(17 to 17);
    signal s_count_RNIT51DM_Y : std_logic_vector(17 to 17);
    signal s_count_RNO_FCO : std_logic_vector(18 to 18);
    signal s_count_RNO_Y : std_logic_vector(18 to 18);
    signal s_count_RNIGI45L_Y : std_logic_vector(16 to 16);
    signal s_count_RNI408TJ_Y : std_logic_vector(15 to 15);
    signal s_count_RNIPEBLI_Y : std_logic_vector(14 to 14);
    signal s_count_RNIFUEDH_Y : std_logic_vector(13 to 13);
    signal s_count_RNI6FI5G_Y : std_logic_vector(12 to 12);
    signal s_count_RNIU0MTE_Y : std_logic_vector(11 to 11);
    signal s_count_RNINJPLD_Y : std_logic_vector(10 to 10);
    signal s_count_RNIH7TDC_Y : std_logic_vector(9 to 9);
    signal s_count_RNIJBK8B_Y : std_logic_vector(8 to 8);
    signal s_count_RNIMGB3A_Y : std_logic_vector(7 to 7);
    signal s_count_RNIQM2U8_Y : std_logic_vector(6 to 6);
    signal s_count_RNIVTPO7_Y : std_logic_vector(5 to 5);
    signal s_count_RNI56HJ6_Y : std_logic_vector(4 to 4);
    signal s_count_RNICF8E5_Y : std_logic_vector(3 to 3);
    signal s_count_RNIKPV84_Y : std_logic_vector(2 to 2);
    signal s_count_RNIT4N33_Y : std_logic_vector(1 to 1);
    signal s_count_RNI7HEU1_Y : std_logic_vector(0 to 0);
    signal \FSM_RATE_LIM_PROC.un1_s_count_1\, 
        \FSM_RATE_LIM_PROC.un1_s_count_2\, 
        \FSM_RATE_LIM_PROC.un1_s_count_3\, 
        \FSM_RATE_LIM_PROC.un1_s_count_4\, 
        \FSM_RATE_LIM_PROC.un1_s_count_5\, 
        \FSM_RATE_LIM_PROC.un1_s_count_6\, 
        \FSM_RATE_LIM_PROC.un1_s_count_7\, 
        \FSM_RATE_LIM_PROC.un1_s_count_8\, 
        \FSM_RATE_LIM_PROC.un1_s_count_9\, 
        \FSM_RATE_LIM_PROC.un1_s_count_10\, 
        \FSM_RATE_LIM_PROC.un1_s_count_11\, 
        \FSM_RATE_LIM_PROC.un1_s_count_12\, 
        \FSM_RATE_LIM_PROC.un1_s_count_13\, 
        \FSM_RATE_LIM_PROC.un1_s_count_14\, 
        \FSM_RATE_LIM_PROC.un1_s_count_15\, 
        \FSM_RATE_LIM_PROC.un1_s_count_16\, 
        \FSM_RATE_LIM_PROC.un1_s_count_17\, MSC_net_305, 
        MSC_net_306, MSC_net_307, 
        \FSM_RATE_LIM_PROC.s_ramp_out19\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref\, 
        \FSM_RATE_LIM_PROC.un1_s_count\, MSC_net_311, MSC_net_312, 
        MSC_net_313, MSC_net_314, MSC_net_315, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_0_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_1_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_2_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_3_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_4_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_5_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_6_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_7_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_8_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_9_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_10_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_11_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_12_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_13_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_14_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_15_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_16_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_17_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_0_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_1_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_2_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_3_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_4_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_5_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_6_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_7_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_8_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_9_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_10_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_11_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_12_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_13_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_14_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_15_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_16_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_17_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_Z\, MSC_net_370, 
        MSC_net_371, MSC_net_372, MSC_net_373, MSC_net_374, 
        MSC_net_375, MSC_net_376, MSC_net_377, MSC_net_378, 
        MSC_net_379, MSC_net_380, MSC_net_381, MSC_net_382, 
        MSC_net_383, MSC_net_384, MSC_net_385, MSC_net_386, 
        MSC_net_387, MSC_net_388, MSC_net_389, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_1\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_2\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_3\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_4\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_5\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_6\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_7\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_8\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_9\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_10\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_11\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_12\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_13\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_14\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_15\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_16\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_17\, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, MSC_net_433, MSC_net_434, MSC_net_435, 
        MSC_net_436, MSC_net_437, MSC_net_438, MSC_net_439, 
        MSC_net_440, MSC_net_441, MSC_net_442, MSC_net_443, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_1\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_2\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_3\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_4\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_5\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_6\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_7\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_8\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_9\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_10\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_11\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_12\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_13\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_14\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_15\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_16\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_17\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_0_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_1_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_2_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_3_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_4_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_5_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_6_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_7_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_8_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_9_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_10_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_11_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_12_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_13_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_14_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_15_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_16_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_17_Z\, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488, MSC_net_489, MSC_net_490, 
        MSC_net_491, MSC_net_492, MSC_net_493, MSC_net_494, 
        MSC_net_495, MSC_net_496, MSC_net_497, MSC_net_498, 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_18_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_18_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_17_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_17_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_16_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_16_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_15_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_15_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_14_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_14_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_13_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_13_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_12_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_12_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_11_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_11_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_10_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_10_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_9_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_9_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_8_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_8_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_7_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_7_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_6_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_6_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_5_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_5_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_4_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_4_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_3_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_3_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_2_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_2_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_1_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_1_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_0_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_0_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_18_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_18_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_17_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_17_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_16_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_16_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_15_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_15_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_14_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_14_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_13_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_13_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_12_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_12_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_11_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_11_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_10_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_10_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_9_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_9_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_8_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_8_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_7_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_7_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_6_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_6_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_5_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_5_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_4_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_4_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_3_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_3_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_2_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_2_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_1_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_1_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_0_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_0_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_18_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_18_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_Y\, MSC_net_632, 
        MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        MSC_net_641, MSC_net_642, MSC_net_643, MSC_net_644, 
        MSC_net_645, MSC_net_646, MSC_net_647, MSC_net_648, 
        MSC_net_649, MSC_net_650, MSC_net_651, MSC_net_652, 
        MSC_net_653, MSC_net_654, MSC_net_655, MSC_net_656, 
        MSC_net_657, MSC_net_658, MSC_net_659, MSC_net_660, 
        MSC_net_661, MSC_net_662, MSC_net_663, MSC_net_664, 
        MSC_net_665, MSC_net_666, MSC_net_667, MSC_net_668, 
        MSC_net_669, MSC_net_670, MSC_net_671, MSC_net_672, 
        MSC_net_673, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_17_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_s_18_FCO\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_s_18_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_16_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_15_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_14_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_13_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_12_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_11_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_10_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_9_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_8_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_7_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_6_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_5_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_4_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_3_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_2_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_1_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_0_S\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_0_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_18_RNI0UL9_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_18_RNI0UL9_Y\, 
        MSC_net_697, MSC_net_698, MSC_net_699, MSC_net_700, 
        MSC_net_701, MSC_net_702, MSC_net_703, MSC_net_704, 
        MSC_net_705, MSC_net_706, MSC_net_707, MSC_net_708, 
        MSC_net_709, MSC_net_710, MSC_net_711, MSC_net_712, 
        MSC_net_713, MSC_net_714, MSC_net_715, MSC_net_716, 
        MSC_net_717, MSC_net_718, MSC_net_719 : std_logic;

    for all : accumulator_rl
	Use entity work.accumulator_rl(DEF_ARCH);
begin 

    rl_out_o(17) <= \rl_out_o\(17);
    rl_out_o(16) <= \rl_out_o\(16);
    rl_out_o(15) <= \rl_out_o\(15);
    rl_out_o(14) <= \rl_out_o\(14);
    rl_out_o(13) <= \rl_out_o\(13);
    rl_out_o(12) <= \rl_out_o\(12);
    rl_out_o(11) <= \rl_out_o\(11);
    rl_out_o(10) <= \rl_out_o\(10);
    rl_out_o(9) <= \rl_out_o\(9);
    rl_out_o(8) <= \rl_out_o\(8);
    rl_out_o(7) <= \rl_out_o\(7);
    rl_out_o(6) <= \rl_out_o\(6);
    rl_out_o(5) <= \rl_out_o\(5);
    rl_out_o(4) <= \rl_out_o\(4);
    rl_out_o(3) <= \rl_out_o\(3);
    rl_out_o(2) <= \rl_out_o\(2);
    rl_out_o(1) <= \rl_out_o\(1);
    rl_out_o(0) <= \rl_out_o\(0);
    rl_done_o <= MSC_net_78;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
IMMyh17n4A5X0xN6PLiLcJxMitjB9LZJ1MRiNqtQUHpFftnUuPkfBzv6WgmCTcei
NpDazNy+PRny3ukD0YgD8nlIFH0Xu6ygPOATgb+Jbkp+Mp7KX/ZJ7bpUueU9P3ox
Xr5hadJ9Pdb6jFxV5QQb5afb3DyVp0yWefQ8qsuO2MM=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=120295)
`protect data_block
[encoded data, 118400 characters]
477n5sw3oL29safbuz6K18FPUChPf06fwZvGFsjE0n0=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_pll is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_pll;

architecture DEF_ARCH of mas_pll is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(12) <= \product_o\(0);
    product_o(11) <= \product_o\(0);
    product_o(10) <= \product_o\(0);
    product_o(9) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12375)
`protect data_block
[encoded data, 12160 characters]
XBBs3bC6kQ09Vm9fJnVqVQ==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity pll_theta_be is

    port( theta_o            : out   std_logic_vector(17 downto 0);
          theta_o_i_0        : out   std_logic_vector(17 downto 0);
          s_pll_theta_dly    : in    std_logic_vector(17 downto 0);
          s_pll_pi_out       : in    std_logic_vector(17 downto 0);
          pll_theta_factor_i : in    std_logic_vector(17 downto 0);
          reset_i            : in    std_logic;
          sys_clk_i          : in    std_logic;
          s_pll_theta_done_o : out   std_logic;
          s_pll_pi_done      : in    std_logic
        );

end pll_theta_be;

architecture DEF_ARCH of pll_theta_be is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component mas_pll
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \theta_o\ : std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(0 to 0);
    signal s_state_i_0 : std_logic_vector(0 to 0);
    signal s_addc_input : std_logic_vector(30 downto 13);
    signal s_product : std_logic_vector(30 downto 13);
    signal s_mult0_input : std_logic_vector(17 downto 0);
    signal s_mult1_input : std_logic_vector(17 downto 0);
    signal s_state_5 : std_logic_vector(0 to 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218 : std_logic;

    for all : mas_pll
	Use entity work.mas_pll(DEF_ARCH);
begin 

    theta_o(17) <= \theta_o\(17);
    theta_o(16) <= \theta_o\(16);
    theta_o(15) <= \theta_o\(15);
    theta_o(14) <= \theta_o\(14);
    theta_o(13) <= \theta_o\(13);
    theta_o(12) <= \theta_o\(12);
    theta_o(11) <= \theta_o\(11);
    theta_o(10) <= \theta_o\(10);
    theta_o(9) <= \theta_o\(9);
    theta_o(8) <= \theta_o\(8);
    theta_o(7) <= \theta_o\(7);
    theta_o(6) <= \theta_o\(6);
    theta_o(5) <= \theta_o\(5);
    theta_o(4) <= \theta_o\(4);
    theta_o(3) <= \theta_o\(3);
    theta_o(2) <= \theta_o\(2);
    theta_o(1) <= \theta_o\(1);
    theta_o(0) <= \theta_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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LwxdQ4oR2/UAs/W4cC0wl4pZWeX1RoCoXqK6Q9HP7Usik2LWFEtH1yBqiMeAoFrg
3VKJyGSDZ1y8lEfgQv+s/i7blRtbq1KMOJGnIojD41A=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=36575)
`protect data_block
[encoded data, 35968 characters]
YZgOi/GIGv6DjN6nSt31di91PcnHzV6v9GNBzENucJw=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity filter_be_0 is

    port( ebeta_filtered_o         : out   std_logic_vector(17 downto 0);
          s_ebeta_filter_out_scale : out   std_logic_vector(15 downto 0);
          s_e_beta_filter_out_prev : in    std_logic_vector(33 downto 0);
          ebeta_o                  : in    std_logic_vector(17 downto 0);
          ebeta_filter_factor_i    : in    std_logic_vector(3 downto 0);
          reset_i                  : in    std_logic;
          sys_clk_i                : in    std_logic;
          s_ebeta_filter_done      : out   std_logic;
          m3_2_03_0_0              : in    std_logic;
          m1_2_03_1_0              : in    std_logic;
          m8_2_03_3_0              : in    std_logic;
          s_ealpha_filter_done     : in    std_logic
        );

end filter_be_0;

architecture DEF_ARCH of filter_be_0 is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal s_filter_incr : std_logic_vector(32 downto 0);
    signal s_filter_incr_2 : std_logic_vector(33 downto 1);
    signal s_state : std_logic_vector(0 to 0);
    signal MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194, MSC_net_195, 
        MSC_net_196, MSC_net_197, MSC_net_198, MSC_net_199, 
        MSC_net_200, MSC_net_201, MSC_net_202, MSC_net_203, 
        MSC_net_204, MSC_net_205, MSC_net_206, MSC_net_207, 
        MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, MSC_net_213, MSC_net_214, MSC_net_215, 
        MSC_net_216, MSC_net_217, MSC_net_218, MSC_net_219, 
        MSC_net_220, MSC_net_221, MSC_net_222, MSC_net_223, 
        MSC_net_224, MSC_net_225, MSC_net_226, MSC_net_227, 
        MSC_net_228, MSC_net_229, MSC_net_230, MSC_net_231, 
        MSC_net_232, MSC_net_233, MSC_net_234, MSC_net_235, 
        MSC_net_236, MSC_net_237, MSC_net_238, MSC_net_239, 
        MSC_net_240, MSC_net_241, MSC_net_242, MSC_net_243, 
        MSC_net_244, MSC_net_245, MSC_net_246, MSC_net_247, 
        MSC_net_248, MSC_net_249, MSC_net_250, MSC_net_251, 
        MSC_net_252, MSC_net_253, MSC_net_254, MSC_net_255, 
        MSC_net_256, MSC_net_257, MSC_net_258, MSC_net_259, 
        MSC_net_260, MSC_net_261, MSC_net_262, MSC_net_263, 
        MSC_net_264, MSC_net_265, MSC_net_266, MSC_net_267, 
        MSC_net_268, MSC_net_269, MSC_net_270, MSC_net_271, 
        MSC_net_272, MSC_net_273, MSC_net_274, MSC_net_275, 
        MSC_net_276, MSC_net_277, MSC_net_278, MSC_net_279, 
        MSC_net_280, MSC_net_281, MSC_net_282, MSC_net_283, 
        MSC_net_284, MSC_net_285, MSC_net_286, MSC_net_287, 
        MSC_net_288, MSC_net_289, MSC_net_290, MSC_net_291, 
        MSC_net_292, MSC_net_293, MSC_net_294, MSC_net_295, 
        MSC_net_296, MSC_net_297, MSC_net_298, MSC_net_299, 
        MSC_net_300, MSC_net_301, MSC_net_302, MSC_net_303, 
        MSC_net_304, MSC_net_305, MSC_net_306, MSC_net_307, 
        MSC_net_308, MSC_net_309, MSC_net_310, MSC_net_311, 
        MSC_net_312, MSC_net_313, MSC_net_314, MSC_net_315, 
        MSC_net_316, MSC_net_317, MSC_net_318, MSC_net_319, 
        MSC_net_320, MSC_net_321, MSC_net_322, MSC_net_323, 
        MSC_net_324, MSC_net_325, MSC_net_326, MSC_net_327, 
        MSC_net_328, MSC_net_329, MSC_net_330, MSC_net_331, 
        MSC_net_332, MSC_net_333, MSC_net_334, MSC_net_335, 
        MSC_net_336, MSC_net_337, MSC_net_338, MSC_net_339, 
        MSC_net_340, MSC_net_341, MSC_net_342, MSC_net_343, 
        MSC_net_344, MSC_net_345, MSC_net_346, MSC_net_347, 
        MSC_net_348, MSC_net_349, MSC_net_350, MSC_net_351, 
        MSC_net_352, MSC_net_353, MSC_net_354, MSC_net_355, 
        MSC_net_356, MSC_net_357, MSC_net_358, MSC_net_359, 
        MSC_net_360, MSC_net_361, MSC_net_362, MSC_net_363, 
        MSC_net_364, MSC_net_365, MSC_net_366, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        MSC_net_384, MSC_net_385, MSC_net_386, MSC_net_387, 
        MSC_net_388, MSC_net_389, MSC_net_390, MSC_net_391, 
        MSC_net_392, MSC_net_393, MSC_net_394, MSC_net_395, 
        MSC_net_396, MSC_net_397, MSC_net_398, MSC_net_399, 
        MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, MSC_net_406, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, MSC_net_433, MSC_net_434, MSC_net_435, 
        MSC_net_436, MSC_net_437, MSC_net_438, MSC_net_439, 
        MSC_net_440, MSC_net_441, MSC_net_442, MSC_net_443, 
        MSC_net_444, MSC_net_445, MSC_net_446, MSC_net_447, 
        MSC_net_448, MSC_net_449, MSC_net_450, MSC_net_451, 
        MSC_net_452, MSC_net_453, MSC_net_454, MSC_net_455, 
        MSC_net_456, MSC_net_457, MSC_net_458, MSC_net_459, 
        MSC_net_460, MSC_net_461, MSC_net_462, MSC_net_463, 
        MSC_net_464, MSC_net_465 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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eL4qsNAQ4zwP8/agOcrZrDlLEPLwSArMPey/iwKMhtdyZtFpRyuktW2qBrQhgWjL
cpwJnG43e1xrzAdpZhWRoDtMzMe7mlHjl3VBypyy7fI=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=87620)
`protect data_block
[encoded data, 86272 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity filter_be is

    port( ealpha_filtered_o         : out   std_logic_vector(17 downto 0);
          s_ealpha_filter_out_scale : out   std_logic_vector(15 downto 0);
          s_e_alpha_filter_out_prev : in    std_logic_vector(33 downto 0);
          ealpha_o                  : in    std_logic_vector(17 downto 0);
          ebeta_filter_factor_i     : in    std_logic_vector(3 downto 0);
          reset_i                   : in    std_logic;
          sys_clk_i                 : in    std_logic;
          s_ealpha_filter_done      : out   std_logic;
          m3_2_03_0_0               : out   std_logic;
          m1_2_03_1_1               : out   std_logic;
          m8_2_03_3_0               : out   std_logic;
          s_flux_estimator_done     : in    std_logic
        );

end filter_be;

architecture DEF_ARCH of filter_be is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal MSC_net_93, MSC_net_94 : std_logic;
    signal s_filter_incr : std_logic_vector(32 downto 0);
    signal s_filter_incr_2 : std_logic_vector(33 downto 1);
    signal s_state : std_logic_vector(0 to 0);
    signal MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194, MSC_net_195, 
        MSC_net_196, MSC_net_197, MSC_net_198, MSC_net_199, 
        MSC_net_200, MSC_net_201, MSC_net_202, MSC_net_203, 
        MSC_net_204, MSC_net_205, MSC_net_206, MSC_net_207, 
        MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, MSC_net_213, MSC_net_214, MSC_net_215, 
        MSC_net_216, MSC_net_217, MSC_net_218, MSC_net_219, 
        MSC_net_220, MSC_net_221, MSC_net_222, MSC_net_223, 
        MSC_net_224, MSC_net_225, MSC_net_226, MSC_net_227, 
        MSC_net_228, MSC_net_229, MSC_net_230, MSC_net_231, 
        MSC_net_232, MSC_net_233, MSC_net_234, MSC_net_235, 
        MSC_net_236, MSC_net_237, MSC_net_238, MSC_net_239, 
        MSC_net_240, MSC_net_241, MSC_net_242, MSC_net_243, 
        MSC_net_244, MSC_net_245, MSC_net_246, MSC_net_247, 
        MSC_net_248, MSC_net_249, MSC_net_250, MSC_net_251, 
        MSC_net_252, MSC_net_253, MSC_net_254, MSC_net_255, 
        MSC_net_256, MSC_net_257, MSC_net_258, MSC_net_259, 
        MSC_net_260, MSC_net_261, MSC_net_262, MSC_net_263, 
        MSC_net_264, MSC_net_265, MSC_net_266, MSC_net_267, 
        MSC_net_268, MSC_net_269, MSC_net_270, MSC_net_271, 
        MSC_net_272, MSC_net_273, MSC_net_274, MSC_net_275, 
        MSC_net_276, MSC_net_277, MSC_net_278, MSC_net_279, 
        MSC_net_280, MSC_net_281, MSC_net_282, MSC_net_283, 
        MSC_net_284, MSC_net_285, MSC_net_286, MSC_net_287, 
        MSC_net_288, MSC_net_289, MSC_net_290, MSC_net_291, 
        MSC_net_292, MSC_net_293, MSC_net_294, MSC_net_295, 
        MSC_net_296, MSC_net_297, MSC_net_298, MSC_net_299, 
        MSC_net_300, MSC_net_301, MSC_net_302, MSC_net_303, 
        MSC_net_304, MSC_net_305, MSC_net_306, MSC_net_307, 
        MSC_net_308, MSC_net_309, MSC_net_310, MSC_net_311, 
        MSC_net_312, MSC_net_313, MSC_net_314, MSC_net_315, 
        MSC_net_316, MSC_net_317, MSC_net_318, MSC_net_319, 
        MSC_net_320, MSC_net_321, MSC_net_322, MSC_net_323, 
        MSC_net_324, MSC_net_325, MSC_net_326, MSC_net_327, 
        MSC_net_328, MSC_net_329, MSC_net_330, MSC_net_331, 
        MSC_net_332, MSC_net_333, MSC_net_334, MSC_net_335, 
        MSC_net_336, MSC_net_337, MSC_net_338, MSC_net_339, 
        MSC_net_340, MSC_net_341, MSC_net_342, MSC_net_343, 
        MSC_net_344, MSC_net_345, MSC_net_346, MSC_net_347, 
        MSC_net_348, MSC_net_349, MSC_net_350, MSC_net_351, 
        MSC_net_352, MSC_net_353, MSC_net_354, MSC_net_355, 
        MSC_net_356, MSC_net_357, MSC_net_358, MSC_net_359, 
        MSC_net_360, MSC_net_361, MSC_net_362, MSC_net_363, 
        MSC_net_364, MSC_net_365, MSC_net_366, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        MSC_net_384, MSC_net_385, MSC_net_386, MSC_net_387, 
        MSC_net_388, MSC_net_389, MSC_net_390, MSC_net_391, 
        MSC_net_392, MSC_net_393, MSC_net_394, MSC_net_395, 
        MSC_net_396, MSC_net_397, MSC_net_398, MSC_net_399, 
        MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, MSC_net_406, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, MSC_net_433, MSC_net_434, MSC_net_435, 
        MSC_net_436, MSC_net_437, MSC_net_438, MSC_net_439, 
        MSC_net_440, MSC_net_441, MSC_net_442, MSC_net_443, 
        MSC_net_444, MSC_net_445, MSC_net_446, MSC_net_447, 
        MSC_net_448, MSC_net_449, MSC_net_450, MSC_net_451, 
        MSC_net_452, MSC_net_453, MSC_net_454, MSC_net_455, 
        MSC_net_456, MSC_net_457, MSC_net_458, MSC_net_459, 
        MSC_net_460, MSC_net_461 : std_logic;

begin 

    m3_2_03_0_0 <= MSC_net_93;
    m1_2_03_1_1 <= MSC_net_94;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
Ni00v6VvAAwwSiVoaz3HitPcUYJ7ASJOAszCWMieQBlwNCuu8Qxk+V7cr1KPfu3h
mRAXPmU5Hqckwi01xtKUSlcI5GAEIBXMMnSGMx4mbIhQIfd29DV+UWTumTJ5n4pw
CquYkwj8rqg7QAEozZcFAjZNWmo0TacyISYzb24mAJ8=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=88270)
`protect data_block
[encoded data, 86912 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_bm_be is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_bm_be;

architecture DEF_ARCH of mas_bm_be is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_174, MSC_net_175, MSC_net_176 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
jCLFCy11vQra/YU+vZUOZmc133uvtfGJytXVEJ98KBYGfbKEoSL1BvyL97ltJ6GI
qtLdpmJ2Vrx/T6+xqpLFueGhwEJidre3EOPcoet1qPHkK1rWf+6DQvTKIAzzvYhM
8/HrcFrh9+MRePo7fmel4RXVVcyoD13lEo1HUcMkmJA=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12005)
`protect data_block
[encoded data, 11776 characters]
3upyBh/sl6CbpMLMavuJ4k88KDsPpuOZ/8ABZFMHN/w=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity bldc_model is

    port( ealpha_o              : out   std_logic_vector(17 downto 0);
          ebeta_o               : out   std_logic_vector(17 downto 0);
          v_alpha_i             : in    std_logic_vector(17 downto 0);
          v_beta_i              : in    std_logic_vector(17 downto 0);
          i_alpha_i             : in    std_logic_vector(17 downto 0);
          s_i_alpha_buf         : in    std_logic_vector(17 downto 0);
          i_beta_i              : in    std_logic_vector(17 downto 0);
          s_i_beta_buf          : in    std_logic_vector(17 downto 0);
          Rs_pu_i               : in    std_logic_vector(17 downto 0);
          Ls_by_Ts_pu_i         : in    std_logic_vector(17 downto 0);
          reset_i               : in    std_logic;
          sys_clk_i             : in    std_logic;
          s_flux_estimator_done : out   std_logic;
          start_i               : in    std_logic
        );

end bldc_model;

architecture DEF_ARCH of bldc_model is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_bm_be
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

    signal s_d_ialpha : std_logic_vector(17 downto 0);
    signal s_d_ialpha_2 : std_logic_vector(17 downto 1);
    signal s_state : std_logic_vector(6 downto 0);
    signal s_d_ibeta : std_logic_vector(17 downto 0);
    signal s_d_ibeta_2 : std_logic_vector(17 downto 1);
    signal s_ialpha_res : std_logic_vector(17 downto 0);
    signal s_mult_result : std_logic_vector(43 downto 0);
    signal s_ibeta_res : std_logic_vector(17 downto 0);
    signal s_mult0_input : std_logic_vector(17 downto 0);
    signal s_mult0_input_6 : std_logic_vector(17 downto 0);
    signal s_mult1_input : std_logic_vector(17 downto 0);
    signal s_mult1_input_4 : std_logic_vector(17 downto 0);
    signal s_addc_input : std_logic_vector(43 downto 0);
    signal s_addc_input_4 : std_logic_vector(43 downto 0);
    signal e_alpha_o_2 : std_logic_vector(17 downto 1);
    signal e_beta_o_2 : std_logic_vector(17 downto 1);
    signal s_state_ns : std_logic_vector(0 to 0);
    signal i_beta_i_m : std_logic_vector(11 downto 0);
    signal s_state_ns_0_a2_2 : std_logic_vector(0 to 0);
    signal s_mult0_input_6_iv_0 : std_logic_vector(11 downto 0);
    signal s_mult0_input_6_iv_0_0 : 
        std_logic_vector(17 downto 12);
    signal MSC_net_567, MSC_net_568, MSC_net_569, MSC_net_570, 
        MSC_net_571, MSC_net_572, MSC_net_573, MSC_net_574, 
        MSC_net_575, MSC_net_576, MSC_net_577, MSC_net_578, 
        MSC_net_579, MSC_net_580, MSC_net_581, MSC_net_582, 
        MSC_net_583, MSC_net_584, MSC_net_585, MSC_net_586, 
        MSC_net_587, MSC_net_588, MSC_net_589, MSC_net_590, 
        MSC_net_591, MSC_net_592, MSC_net_593, MSC_net_594, 
        MSC_net_595, MSC_net_596, MSC_net_597, MSC_net_598, 
        MSC_net_599, MSC_net_600, MSC_net_601, MSC_net_602, 
        MSC_net_603, MSC_net_604, MSC_net_605, MSC_net_606, 
        MSC_net_607, MSC_net_608, MSC_net_609, MSC_net_610, 
        MSC_net_611, MSC_net_612, MSC_net_613, MSC_net_614, 
        MSC_net_615, MSC_net_616, MSC_net_617, MSC_net_618, 
        MSC_net_619, MSC_net_620, MSC_net_621, MSC_net_622, 
        MSC_net_623, MSC_net_624, MSC_net_625, MSC_net_626, 
        MSC_net_627, MSC_net_628, MSC_net_629, MSC_net_630, 
        MSC_net_631, MSC_net_632, MSC_net_633, MSC_net_634, 
        MSC_net_635, MSC_net_636, MSC_net_637, MSC_net_638, 
        MSC_net_639, MSC_net_640, MSC_net_641, MSC_net_642, 
        MSC_net_643, MSC_net_644, MSC_net_645, MSC_net_646, 
        MSC_net_647, MSC_net_648, MSC_net_649, MSC_net_650, 
        MSC_net_651, MSC_net_652, MSC_net_653, MSC_net_654, 
        MSC_net_655, MSC_net_656, MSC_net_657, MSC_net_658, 
        MSC_net_659, MSC_net_660, MSC_net_661, MSC_net_662, 
        MSC_net_663, MSC_net_664, MSC_net_665, MSC_net_666, 
        MSC_net_667, MSC_net_668, MSC_net_669, MSC_net_670, 
        MSC_net_671, MSC_net_672, MSC_net_673, MSC_net_674, 
        MSC_net_675, MSC_net_676, MSC_net_677, MSC_net_678, 
        MSC_net_679, MSC_net_680, MSC_net_681, MSC_net_682, 
        MSC_net_683, MSC_net_684, MSC_net_685, MSC_net_686, 
        MSC_net_687, MSC_net_688, MSC_net_689, MSC_net_690, 
        MSC_net_691, MSC_net_692, MSC_net_693, MSC_net_694, 
        MSC_net_695, MSC_net_696, MSC_net_697, MSC_net_698, 
        MSC_net_699, MSC_net_700, MSC_net_701, MSC_net_702, 
        MSC_net_703, MSC_net_704, MSC_net_705, MSC_net_706, 
        MSC_net_707, MSC_net_708, MSC_net_709, MSC_net_710, 
        MSC_net_711, MSC_net_712, MSC_net_713, MSC_net_714, 
        MSC_net_715, MSC_net_716, MSC_net_717, MSC_net_718, 
        MSC_net_719, MSC_net_720, MSC_net_721, MSC_net_722, 
        MSC_net_723, MSC_net_724, MSC_net_725, MSC_net_726, 
        MSC_net_727, MSC_net_728, MSC_net_729, MSC_net_730, 
        MSC_net_731, MSC_net_732, MSC_net_733, MSC_net_734, 
        MSC_net_735, MSC_net_736, MSC_net_737, MSC_net_738, 
        MSC_net_739, MSC_net_740, MSC_net_741 : std_logic;

    for all : mas_bm_be
	Use entity work.mas_bm_be(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
LnLNbKVtaLa0oBgl9OTr+JvYodvEgz4HdXB6w3VOvRMHk+FD/fTP+QF8GE2JVx+k
vtcjJDzvFf6MKtaEtk+UcV4HVXfYPgI5jsd13qR6lUi6kSkLRpN2PtCtv9PoPf1F
N2n3lduF65LTpkBxrTB0HVwtjlZpSKf3E3wtAbp5xIU=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=136870)
`protect data_block
[encoded data, 134720 characters]
Xw8fs3YJ/Y8vlvwWX86WPUwsZwW3nIWa6R6c5dRkVcE=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_pi_be is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_pi_be;

architecture DEF_ARCH of mas_pi_be is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_174, MSC_net_175, MSC_net_176 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
FLftflkzJzGjcrDpXoMQlP3LbJlwkQRVDJgPUfWGuUTRcZGaAFKxz97OySdbR0bp
F7fiHmt9k8dBEaBMjColIvB8KrwHYX/+ZSwOVM/9b4fEYGVvpXKYxW+D76IVPhyz
rjibNgwbn7zT1IJyIFOK+PanGIEfNIUGC07Q63qxyu0=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12005)
`protect data_block
[encoded data, 11776 characters]
a2n11O+LtYhABKPAZcHIN+mmA5YCEAUvypTqimsCQI0=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity pi_controller_be is

    port( s_angle_pi_acc_out : out   std_logic_vector(43 downto 0);
          s_pll_pi_out       : out   std_logic_vector(17 downto 0);
          s_omega_pi_acc_in  : in    std_logic_vector(43 downto 0);
          s_flux_q           : in    std_logic_vector(17 downto 0);
          angle_pi_kp_i      : in    std_logic_vector(17 downto 0);
          angle_pi_ki_i      : in    std_logic_vector(17 downto 0);
          reset_i            : in    std_logic;
          sys_clk_i          : in    std_logic;
          s_pll_pi_done      : out   std_logic;
          angle_pi_en_i      : in    std_logic;
          s_cordic_done      : in    std_logic
        );

end pi_controller_be;

architecture DEF_ARCH of pi_controller_be is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_pi_be
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

    signal acc_out_o_3 : std_logic_vector(43 downto 0);
    signal s_state : std_logic_vector(4 downto 0);
    signal output_y_o_5_iv_i_0 : std_logic_vector(16 downto 0);
    signal s_piout : std_logic_vector(34 downto 1);
    signal s_acc_in : std_logic_vector(43 downto 0);
    signal s_inew : std_logic_vector(43 downto 0);
    signal s_product : std_logic_vector(43 downto 0);
    signal s_pout : std_logic_vector(43 downto 10);
    signal s_mult1_input : std_logic_vector(17 downto 0);
    signal s_mult1_input_6 : std_logic_vector(17 downto 0);
    signal s_add_cin : std_logic_vector(43 downto 0);
    signal s_add_cin_5 : std_logic_vector(43 downto 0);
    signal s_i_init_ds : std_logic_vector(17 downto 0);
    signal s_i_init_ds_2 : std_logic_vector(17 downto 1);
    signal s_mult0_input : std_logic_vector(17 downto 0);
    signal s_state_ns : std_logic_vector(1 to 1);
    signal s_inew_RNI8CQP_S : std_logic_vector(16 to 16);
    signal s_inew_RNI8CQP_Y : std_logic_vector(16 to 16);
    signal s_pout_RNIIQKJ1_Y : std_logic_vector(11 to 11);
    signal s_pout_RNIUAFD2_Y : std_logic_vector(12 to 12);
    signal s_pout_RNICT973_Y : std_logic_vector(13 to 13);
    signal s_pout_RNIJ9514_Y : std_logic_vector(14 to 14);
    signal s_pout_RNISN0R4_Y : std_logic_vector(15 to 15);
    signal s_pout_RNI78SK5_Y : std_logic_vector(16 to 16);
    signal s_pout_RNIKQNE6_Y : std_logic_vector(17 to 17);
    signal s_pout_RNI3FJ87_Y : std_logic_vector(18 to 18);
    signal s_pout_RNIK5F28_Y : std_logic_vector(19 to 19);
    signal s_pout_RNIULBS8_Y : std_logic_vector(20 to 20);
    signal s_pout_RNIA88M9_Y : std_logic_vector(21 to 21);
    signal s_pout_RNIOS4GA_Y : std_logic_vector(22 to 22);
    signal s_pout_RNI8J1AB_Y : std_logic_vector(23 to 23);
    signal s_pout_RNIH3V3C_Y : std_logic_vector(24 to 24);
    signal s_pout_RNISLSTC_Y : std_logic_vector(25 to 25);
    signal s_pout_RNI9AQND_Y : std_logic_vector(26 to 26);
    signal s_pout_RNIO0OHE_Y : std_logic_vector(27 to 27);
    signal s_pout_RNI9PLBF_Y : std_logic_vector(28 to 28);
    signal s_pout_RNISJJ5G_Y : std_logic_vector(29 to 29);
    signal s_pout_RNI88IVG_Y : std_logic_vector(30 to 30);
    signal s_pout_RNIMUGPH_Y : std_logic_vector(31 to 31);
    signal s_pout_RNI6NFJI_Y : std_logic_vector(32 to 32);
    signal s_pout_RNIOHEDJ_Y : std_logic_vector(33 to 33);
    signal s_pout_RNI36E7K_Y : std_logic_vector(34 to 34);
    signal s_pout_RNIGSD1L_Y : std_logic_vector(35 to 35);
    signal s_pout_RNIVKDRL_Y : std_logic_vector(36 to 36);
    signal s_pout_RNIGFDLM_Y : std_logic_vector(37 to 37);
    signal s_pout_RNI2BDFN_Y : std_logic_vector(38 to 38);
    signal s_pout_RNIL7D9O_Y : std_logic_vector(39 to 39);
    signal s_pout_RNI0TD3P_Y : std_logic_vector(40 to 40);
    signal s_pout_RNICJETP_Y : std_logic_vector(41 to 41);
    signal s_pout_RNIPAFNQ_Y : std_logic_vector(42 to 42);
    signal s_pout_RNILRGBS_FCO : std_logic_vector(43 to 43);
    signal s_pout_RNILRGBS_Y : std_logic_vector(43 to 43);
    signal s_pout_RNI73GHR_Y : std_logic_vector(43 to 43);
    signal s_state_ns_i_0 : std_logic_vector(0 to 0);
    signal s_iout : std_logic_vector(42 downto 16);
    signal acc_out_o_3_b_A : std_logic_vector(43 to 43);
    signal MSC_net_675, MSC_net_676, MSC_net_677, MSC_net_678, 
        MSC_net_679, MSC_net_680, MSC_net_681, MSC_net_682, 
        MSC_net_683, MSC_net_684, MSC_net_685, MSC_net_686, 
        MSC_net_687, MSC_net_688, MSC_net_689, MSC_net_690, 
        MSC_net_691, MSC_net_692, MSC_net_693, MSC_net_694, 
        MSC_net_695, MSC_net_696, MSC_net_697, MSC_net_698, 
        MSC_net_699, MSC_net_700, MSC_net_701, MSC_net_702, 
        MSC_net_703, MSC_net_704, MSC_net_705, MSC_net_706, 
        MSC_net_707, MSC_net_708, MSC_net_709, MSC_net_710, 
        MSC_net_711, MSC_net_712, MSC_net_713, MSC_net_714, 
        MSC_net_715, MSC_net_716, MSC_net_717, MSC_net_718, 
        MSC_net_719, MSC_net_720, MSC_net_721, MSC_net_722, 
        MSC_net_723, MSC_net_724, MSC_net_725, MSC_net_726, 
        MSC_net_727, MSC_net_728, MSC_net_729, MSC_net_730, 
        MSC_net_731, MSC_net_732, MSC_net_733, MSC_net_734, 
        MSC_net_735, MSC_net_736, MSC_net_737, MSC_net_738, 
        MSC_net_739, MSC_net_740, MSC_net_741, MSC_net_742, 
        MSC_net_743, MSC_net_744, MSC_net_745, MSC_net_746, 
        MSC_net_747, MSC_net_748, MSC_net_749, MSC_net_750, 
        MSC_net_751, MSC_net_752, MSC_net_753, MSC_net_754, 
        MSC_net_755, MSC_net_756, MSC_net_757, MSC_net_758, 
        MSC_net_759, MSC_net_760, MSC_net_761, MSC_net_762, 
        MSC_net_763, MSC_net_764, MSC_net_765, MSC_net_766, 
        MSC_net_767, MSC_net_768, MSC_net_769, MSC_net_770, 
        MSC_net_771, MSC_net_772, MSC_net_773, MSC_net_774, 
        MSC_net_775, MSC_net_776, MSC_net_777, MSC_net_778, 
        MSC_net_779, MSC_net_780, MSC_net_781, MSC_net_782, 
        MSC_net_783, MSC_net_784, MSC_net_785, MSC_net_786, 
        MSC_net_787, MSC_net_788, MSC_net_789, MSC_net_790, 
        MSC_net_791, MSC_net_792, MSC_net_793, MSC_net_794, 
        MSC_net_795, MSC_net_796, MSC_net_797 : std_logic;

    for all : mas_pi_be
	Use entity work.mas_pi_be(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
eHdMevubnbhy78YPhn8oTPr8qg2VT80lPH/sOsqoTtePF5XeLjRBJ8lWmotlHesj
fmC1Sh52hisGa1F3GmQ5y/c4lpDPNXOxlnY86SIralFuVa2O47o2xyaVEbNGRygx
T3uygEzDiKzBlwsIz/XyJSLkpReE4NRvnECue3APIP4=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=167920)
`protect data_block
[encoded data, 165312 characters]
hrsAQDmGK/GAyg35ax0mUg==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity filter_be_1 is

    port( speed_filtered_o         : out   std_logic_vector(17 downto 0);
          s_omega_filter_out_scale : out   std_logic_vector(15 downto 0);
          s_omega_filter_out_prev  : in    std_logic_vector(33 downto 0);
          s_pll_pi_out             : in    std_logic_vector(17 downto 0);
          omega_filter_factor_i    : in    std_logic_vector(3 downto 0);
          reset_i                  : in    std_logic;
          sys_clk_i                : in    std_logic;
          done_o                   : out   std_logic;
          s_pll_pi_done            : in    std_logic
        );

end filter_be_1;

architecture DEF_ARCH of filter_be_1 is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal s_filter_incr : std_logic_vector(32 downto 0);
    signal s_filter_incr_2 : std_logic_vector(33 downto 1);
    signal s_state : std_logic_vector(0 to 0);
    signal MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220, 
        MSC_net_221, MSC_net_222, MSC_net_223, MSC_net_224, 
        MSC_net_225, MSC_net_226, MSC_net_227, MSC_net_228, 
        MSC_net_229, MSC_net_230, MSC_net_231, MSC_net_232, 
        MSC_net_233, MSC_net_234, MSC_net_235, MSC_net_236, 
        MSC_net_237, MSC_net_238, MSC_net_239, MSC_net_240, 
        MSC_net_241, MSC_net_242, MSC_net_243, MSC_net_244, 
        MSC_net_245, MSC_net_246, MSC_net_247, MSC_net_248, 
        MSC_net_249, MSC_net_250, MSC_net_251, MSC_net_252, 
        MSC_net_253, MSC_net_254, MSC_net_255, MSC_net_256, 
        MSC_net_257, MSC_net_258, MSC_net_259, MSC_net_260, 
        MSC_net_261, MSC_net_262, MSC_net_263, MSC_net_264, 
        MSC_net_265, MSC_net_266, MSC_net_267, MSC_net_268, 
        MSC_net_269, MSC_net_270, MSC_net_271, MSC_net_272, 
        MSC_net_273, MSC_net_274, MSC_net_275, MSC_net_276, 
        MSC_net_277, MSC_net_278, MSC_net_279, MSC_net_280, 
        MSC_net_281, MSC_net_282, MSC_net_283, MSC_net_284, 
        MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        MSC_net_305, MSC_net_306, MSC_net_307, MSC_net_308, 
        MSC_net_309, MSC_net_310, MSC_net_311, MSC_net_312, 
        MSC_net_313, MSC_net_314, MSC_net_315, MSC_net_316, 
        MSC_net_317, MSC_net_318, MSC_net_319, MSC_net_320, 
        MSC_net_321, MSC_net_322, MSC_net_323, MSC_net_324, 
        MSC_net_325, MSC_net_326, MSC_net_327, MSC_net_328, 
        MSC_net_329, MSC_net_330, MSC_net_331, MSC_net_332, 
        MSC_net_333, MSC_net_334, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, MSC_net_350, MSC_net_351, MSC_net_352, 
        MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
J7N0FM/Mhz71u/KT77J3dYAoYqGSehtgN44SDUUE/RirP9RE1GFIwSHAQeyaZCHV
KNjw8YR27Z2+p3CjgpdQZ+GZoUb2lcjjVnb4sf5VNPi7CPPe4HT+a+Zhb6OX5QT3
2cBTS4obUX0iueSDl2kKcbj2cyTiDt9TIDsf2IXqcWo=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=87060)
`protect data_block
[encoded data, 85696 characters]
nZGUrxG+N39NuEvPELcQpQ==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity accumulator_be is

    port( speed_filtered_o          : in    std_logic_vector(17 downto 0);
          s_omega_filter_out_prev   : out   std_logic_vector(33 downto 0);
          s_omega_filter_out_scale  : in    std_logic_vector(15 downto 0);
          s_omega_pi_acc_in         : out   std_logic_vector(43 downto 0);
          s_angle_pi_acc_out        : in    std_logic_vector(43 downto 0);
          s_i_alpha_buf             : out   std_logic_vector(17 downto 0);
          i_alpha_i                 : in    std_logic_vector(17 downto 0);
          s_i_beta_buf              : out   std_logic_vector(17 downto 0);
          i_beta_i                  : in    std_logic_vector(17 downto 0);
          s_pll_theta_dly           : out   std_logic_vector(17 downto 0);
          theta_o                   : in    std_logic_vector(17 downto 0);
          ealpha_filtered_o         : in    std_logic_vector(17 downto 0);
          s_e_alpha_filter_out_prev : out   std_logic_vector(33 downto 0);
          s_ealpha_filter_out_scale : in    std_logic_vector(15 downto 0);
          ebeta_filtered_o          : in    std_logic_vector(17 downto 0);
          s_e_beta_filter_out_prev  : out   std_logic_vector(33 downto 0);
          s_ebeta_filter_out_scale  : in    std_logic_vector(15 downto 0);
          reset_i                   : in    std_logic;
          sys_clk_i                 : in    std_logic;
          done_o                    : in    std_logic;
          s_pll_pi_done             : in    std_logic;
          s_flux_estimator_done     : in    std_logic;
          s_pll_theta_done_o        : in    std_logic;
          s_ealpha_filter_done      : in    std_logic;
          s_ebeta_filter_done       : in    std_logic
        );

end accumulator_be;

architecture DEF_ARCH of accumulator_be is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal MSC_net_408, MSC_net_409 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
kB64CUoOqlGTnm5xFx2GLNkuSzOX9Shezc30EVL7QsQ1Wf06lUCXSVYifONkZtBY
RrHIFVmmkdd/Ezi15NfRAa0cRv/JI96G7yjQpfNoP3YBbZyeGDRx9VPu/YWi8UVo
nIRww/zqHcrcCwxMnWskINvLL8vJGilraKCwS3rAlWo=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=75530)
`protect data_block
[encoded data, 74368 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_rot_be is

    port( s_flux_q            : out   std_logic_vector(17 downto 0);
          theta_o_i_0         : in    std_logic_vector(17 downto 0);
          ebeta_filtered_o    : in    std_logic_vector(17 downto 0);
          ealpha_filtered_o   : in    std_logic_vector(17 downto 0);
          reset_i             : in    std_logic;
          sys_clk_i           : in    std_logic;
          s_cordic_done       : out   std_logic;
          s_ebeta_filter_done : in    std_logic
        );

end cordic_rot_be;

architecture DEF_ARCH of cordic_rot_be is 

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal y_o_3_1 : std_logic_vector(17 downto 0);
    signal s_index : std_logic_vector(3 downto 0);
    signal s_index_7 : std_logic_vector(0 to 0);
    signal s_index_7_iv_i_0 : std_logic_vector(3 downto 1);
    signal s_theta_c : std_logic_vector(17 downto 0);
    signal s_theta_c_9 : std_logic_vector(17 downto 0);
    signal un1_s_theta_c3_1_i_0 : std_logic_vector(0 to 0);
    signal s_xi_rot : std_logic_vector(16 downto 0);
    signal s_xi_rot_7 : std_logic_vector(17 downto 0);
    signal un1_s_theta_c3_i_0 : std_logic_vector(0 to 0);
    signal s_yi_rot : std_logic_vector(16 downto 0);
    signal s_yi_rot_7 : std_logic_vector(17 downto 0);
    signal s_theta_i : std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(0 to 0);
    signal un1_s_yout : std_logic_vector(17 downto 0);
    signal un1_s_xout : std_logic_vector(17 downto 1);
    signal un4_s_theta_c : std_logic_vector(14 downto 1);
    signal s_theta_i_RNI3LE1_FCO : std_logic_vector(17 to 17);
    signal s_theta_i_RNI3LE1_S : std_logic_vector(17 to 17);
    signal s_theta_i_RNI3LE1_Y : std_logic_vector(17 to 17);
    signal s_xi_rot_RNI8F14_Y : std_logic_vector(0 to 0);
    signal s_xi_rot_RNIEAK6_Y : std_logic_vector(1 to 1);
    signal s_xi_rot_RNIL679_Y : std_logic_vector(2 to 2);
    signal s_xi_rot_RNIT3QB_Y : std_logic_vector(3 to 3);
    signal s_xi_rot_RNI62DE_Y : std_logic_vector(4 to 4);
    signal s_xi_rot_RNIG10H_Y : std_logic_vector(5 to 5);
    signal s_xi_rot_RNIR1JJ_Y : std_logic_vector(6 to 6);
    signal s_xi_rot_RNI736M_Y : std_logic_vector(7 to 7);
    signal s_xi_rot_RNIK5PO_Y : std_logic_vector(8 to 8);
    signal s_xi_rot_RNI29CR_Y : std_logic_vector(9 to 9);
    signal s_xi_rot_RNIOR321_Y : std_logic_vector(10 to 10);
    signal s_xi_rot_RNIFFR81_Y : std_logic_vector(11 to 11);
    signal s_xi_rot_RNI74JF1_Y : std_logic_vector(12 to 12);
    signal s_xi_rot_RNI0QAM1_Y : std_logic_vector(13 to 13);
    signal s_xi_rot_RNIQG2T1_Y : std_logic_vector(14 to 14);
    signal s_xi_rot_RNIL8Q32_Y : std_logic_vector(15 to 15);
    signal y_o_3_1_3_RNO_FCO : std_logic_vector(17 to 17);
    signal y_o_3_1_3_RNO_Y : std_logic_vector(17 to 17);
    signal s_xi_rot_RNIH1IA2_Y : std_logic_vector(16 to 16);
    signal un4_s_theta_c_1 : std_logic_vector(1 to 1);
    signal un6_s_xout : std_logic_vector(16 downto 14);
    signal MSC_net_304, MSC_net_305, MSC_net_306, MSC_net_307, 
        MSC_net_308, MSC_net_309, MSC_net_310, MSC_net_311, 
        MSC_net_312, MSC_net_313, MSC_net_314, MSC_net_315, 
        MSC_net_316, MSC_net_317, MSC_net_318, MSC_net_319, 
        MSC_net_320, MSC_net_321, MSC_net_322, MSC_net_323, 
        MSC_net_324, MSC_net_325, MSC_net_326, MSC_net_327, 
        MSC_net_328, MSC_net_329, MSC_net_330, MSC_net_331, 
        MSC_net_332, MSC_net_333, MSC_net_334, MSC_net_335, 
        MSC_net_336, MSC_net_337, MSC_net_338, MSC_net_339, 
        MSC_net_340, MSC_net_341, MSC_net_342, MSC_net_343, 
        MSC_net_344, MSC_net_345, MSC_net_346, MSC_net_347, 
        MSC_net_348, MSC_net_349, MSC_net_350, MSC_net_351, 
        MSC_net_352, MSC_net_353, MSC_net_354, MSC_net_355, 
        MSC_net_356, MSC_net_357, MSC_net_358, MSC_net_359, 
        MSC_net_360, MSC_net_361, MSC_net_362, MSC_net_363, 
        MSC_net_364, MSC_net_365, MSC_net_366, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        MSC_net_384, MSC_net_385, MSC_net_386, MSC_net_387, 
        MSC_net_388, MSC_net_389, MSC_net_390, MSC_net_391, 
        MSC_net_392, MSC_net_393, MSC_net_394, MSC_net_395, 
        MSC_net_396, MSC_net_397, MSC_net_398, MSC_net_399, 
        MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, MSC_net_406, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, MSC_net_433, MSC_net_434, MSC_net_435, 
        MSC_net_436, MSC_net_437, MSC_net_438, MSC_net_439, 
        MSC_net_440, MSC_net_441, MSC_net_442, MSC_net_443, 
        MSC_net_444, MSC_net_445, MSC_net_446, MSC_net_447, 
        MSC_net_448, MSC_net_449, MSC_net_450, MSC_net_451, 
        MSC_net_452, MSC_net_453, MSC_net_454, MSC_net_455, 
        MSC_net_456, MSC_net_457, MSC_net_458, MSC_net_459, 
        MSC_net_460, MSC_net_461, MSC_net_462, MSC_net_463, 
        MSC_net_464, MSC_net_465, MSC_net_466, MSC_net_467, 
        MSC_net_468, MSC_net_469, MSC_net_470, MSC_net_471, 
        MSC_net_472, MSC_net_473, MSC_net_474, MSC_net_475, 
        MSC_net_476, MSC_net_477, MSC_net_478, MSC_net_479, 
        MSC_net_480, MSC_net_481, MSC_net_482, MSC_net_483, 
        MSC_net_484, MSC_net_485, MSC_net_486, MSC_net_487, 
        MSC_net_488, MSC_net_489, MSC_net_490, MSC_net_491, 
        MSC_net_492, MSC_net_493, MSC_net_494, MSC_net_495, 
        MSC_net_496, MSC_net_497, MSC_net_498, MSC_net_499, 
        MSC_net_500, MSC_net_501, MSC_net_502, MSC_net_503, 
        MSC_net_504, MSC_net_505, MSC_net_506, MSC_net_507, 
        MSC_net_508, MSC_net_509, MSC_net_510, MSC_net_511, 
        MSC_net_512, MSC_net_513, MSC_net_514, MSC_net_515, 
        MSC_net_516, MSC_net_517, MSC_net_518, MSC_net_519, 
        MSC_net_520, MSC_net_521, MSC_net_522, MSC_net_523, 
        MSC_net_524, MSC_net_525, MSC_net_526, MSC_net_527, 
        MSC_net_528, MSC_net_529, MSC_net_530, MSC_net_531, 
        MSC_net_532, MSC_net_533, MSC_net_534, MSC_net_535, 
        MSC_net_536, MSC_net_537, MSC_net_538, MSC_net_539, 
        MSC_net_540, MSC_net_541, MSC_net_542, MSC_net_543, 
        MSC_net_544, MSC_net_545, MSC_net_546, MSC_net_547, 
        MSC_net_548, MSC_net_549, MSC_net_550, MSC_net_551, 
        MSC_net_552, MSC_net_553, MSC_net_554, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, MSC_net_591, 
        MSC_net_592, MSC_net_593, MSC_net_594, MSC_net_595, 
        MSC_net_596, MSC_net_597, MSC_net_598, MSC_net_599, 
        MSC_net_600, MSC_net_601, MSC_net_602, MSC_net_603, 
        MSC_net_604, MSC_net_605, MSC_net_606, MSC_net_607, 
        MSC_net_608, MSC_net_609, MSC_net_610, MSC_net_611, 
        MSC_net_612, MSC_net_613, MSC_net_614, MSC_net_615, 
        MSC_net_616, MSC_net_617, MSC_net_618, MSC_net_619, 
        MSC_net_620, MSC_net_621, MSC_net_622, MSC_net_623, 
        MSC_net_624, MSC_net_625, MSC_net_626, MSC_net_627, 
        MSC_net_628, MSC_net_629, MSC_net_630, MSC_net_631, 
        MSC_net_632, MSC_net_633, MSC_net_634, MSC_net_635, 
        MSC_net_636, MSC_net_637, MSC_net_638, MSC_net_639, 
        MSC_net_640, MSC_net_641, MSC_net_642, MSC_net_643, 
        MSC_net_644, MSC_net_645, MSC_net_646, MSC_net_647, 
        MSC_net_648, MSC_net_649, MSC_net_650, MSC_net_651, 
        MSC_net_652, MSC_net_653, MSC_net_654, MSC_net_655, 
        MSC_net_656, MSC_net_657, MSC_net_658, MSC_net_659, 
        MSC_net_660, MSC_net_661, MSC_net_662, MSC_net_663, 
        MSC_net_664, MSC_net_665, MSC_net_666, MSC_net_667, 
        MSC_net_668, MSC_net_669, MSC_net_670, MSC_net_671, 
        MSC_net_672, MSC_net_673, MSC_net_674, MSC_net_675, 
        MSC_net_676, MSC_net_677, MSC_net_678, MSC_net_679, 
        MSC_net_680, MSC_net_681, MSC_net_682, MSC_net_683, 
        MSC_net_684, MSC_net_685, MSC_net_686, MSC_net_687, 
        MSC_net_688, MSC_net_689, MSC_net_690, MSC_net_691, 
        MSC_net_692, MSC_net_693, MSC_net_694, MSC_net_695, 
        MSC_net_696, MSC_net_697, MSC_net_698, MSC_net_699, 
        MSC_net_700, MSC_net_701, MSC_net_702, MSC_net_703, 
        MSC_net_704, MSC_net_705, MSC_net_706, MSC_net_707, 
        MSC_net_708, MSC_net_709, MSC_net_710, MSC_net_711, 
        MSC_net_712, MSC_net_713, MSC_net_714, MSC_net_715, 
        MSC_net_716, MSC_net_717, MSC_net_718, MSC_net_719, 
        MSC_net_720, MSC_net_721, MSC_net_722, MSC_net_723, 
        MSC_net_724, MSC_net_725, MSC_net_726, MSC_net_727, 
        MSC_net_728, MSC_net_729, MSC_net_730, MSC_net_731, 
        MSC_net_732, MSC_net_733, MSC_net_734, MSC_net_735, 
        MSC_net_736, MSC_net_737, MSC_net_738, MSC_net_739, 
        MSC_net_740, MSC_net_741, MSC_net_742, MSC_net_743
         : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
eWxnL51ebOOGjzPAwy0wyN8OcgUw1S85NBMJfXhZviYbyeLioIi7U3QVWv6c85vk
fTI0z0xVfW8xaxyj/U0hIDoj3xhIsPGcwAXbxfX4xheS1OSopg1itlxbgQRTy9e8
rpt9CkTocuqhdTckNj7rZsxToQyeNB5voB4LTQBIpNo=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=128375)
`protect data_block
[encoded data, 126400 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity BLDC_ESTIMATOR is

    port( reset_i                : in    std_logic;
          sys_clk_i              : in    std_logic;
          start_i                : in    std_logic;
          angle_pi_en_i          : in    std_logic;
          v_alpha_i              : in    std_logic_vector(17 downto 0);
          v_beta_i               : in    std_logic_vector(17 downto 0);
          i_alpha_i              : in    std_logic_vector(17 downto 0);
          i_beta_i               : in    std_logic_vector(17 downto 0);
          Ls_by_Ts_pu_i          : in    std_logic_vector(17 downto 0);
          Rs_pu_i                : in    std_logic_vector(17 downto 0);
          ealpha_filter_factor_i : in    std_logic_vector(3 downto 0);
          ebeta_filter_factor_i  : in    std_logic_vector(3 downto 0);
          pll_theta_factor_i     : in    std_logic_vector(17 downto 0);
          angle_pi_ki_i          : in    std_logic_vector(17 downto 0);
          angle_pi_kp_i          : in    std_logic_vector(17 downto 0);
          omega_filter_factor_i  : in    std_logic_vector(3 downto 0);
          done_o                 : out   std_logic;
          theta_o                : out   std_logic_vector(17 downto 0);
          ealpha_o               : out   std_logic_vector(17 downto 0);
          ebeta_o                : out   std_logic_vector(17 downto 0);
          ealpha_filtered_o      : out   std_logic_vector(17 downto 0);
          ebeta_filtered_o       : out   std_logic_vector(17 downto 0);
          pll_pi_out_o           : out   std_logic_vector(17 downto 0);
          speed_filtered_o       : out   std_logic_vector(17 downto 0)
        );

end BLDC_ESTIMATOR;

architecture DEF_ARCH of BLDC_ESTIMATOR is 

  component pll_theta_be
    port( theta_o            : out   std_logic_vector(17 downto 0);
          theta_o_i_0        : out   std_logic_vector(17 downto 0);
          s_pll_theta_dly    : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_pll_pi_out       : in    std_logic_vector(17 downto 0) := (others => 'U');
          pll_theta_factor_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i            : in    std_logic := 'U';
          sys_clk_i          : in    std_logic := 'U';
          s_pll_theta_done_o : out   std_logic;
          s_pll_pi_done      : in    std_logic := 'U'
        );
  end component;

  component filter_be_0
    port( ebeta_filtered_o         : out   std_logic_vector(17 downto 0);
          s_ebeta_filter_out_scale : out   std_logic_vector(15 downto 0);
          s_e_beta_filter_out_prev : in    std_logic_vector(33 downto 0) := (others => 'U');
          ebeta_o                  : in    std_logic_vector(17 downto 0) := (others => 'U');
          ebeta_filter_factor_i    : in    std_logic_vector(3 downto 0) := (others => 'U');
          reset_i                  : in    std_logic := 'U';
          sys_clk_i                : in    std_logic := 'U';
          s_ebeta_filter_done      : out   std_logic;
          m3_2_03_0_0              : in    std_logic := 'U';
          m1_2_03_1_0              : in    std_logic := 'U';
          m8_2_03_3_0              : in    std_logic := 'U';
          s_ealpha_filter_done     : in    std_logic := 'U'
        );
  end component;

  component filter_be
    port( ealpha_filtered_o         : out   std_logic_vector(17 downto 0);
          s_ealpha_filter_out_scale : out   std_logic_vector(15 downto 0);
          s_e_alpha_filter_out_prev : in    std_logic_vector(33 downto 0) := (others => 'U');
          ealpha_o                  : in    std_logic_vector(17 downto 0) := (others => 'U');
          ebeta_filter_factor_i     : in    std_logic_vector(3 downto 0) := (others => 'U');
          reset_i                   : in    std_logic := 'U';
          sys_clk_i                 : in    std_logic := 'U';
          s_ealpha_filter_done      : out   std_logic;
          m3_2_03_0_0               : out   std_logic;
          m1_2_03_1_1               : out   std_logic;
          m8_2_03_3_0               : out   std_logic;
          s_flux_estimator_done     : in    std_logic := 'U'
        );
  end component;

  component bldc_model
    port( ealpha_o              : out   std_logic_vector(17 downto 0);
          ebeta_o               : out   std_logic_vector(17 downto 0);
          v_alpha_i             : in    std_logic_vector(17 downto 0) := (others => 'U');
          v_beta_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          i_alpha_i             : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_i_alpha_buf         : in    std_logic_vector(17 downto 0) := (others => 'U');
          i_beta_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_i_beta_buf          : in    std_logic_vector(17 downto 0) := (others => 'U');
          Rs_pu_i               : in    std_logic_vector(17 downto 0) := (others => 'U');
          Ls_by_Ts_pu_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i               : in    std_logic := 'U';
          sys_clk_i             : in    std_logic := 'U';
          s_flux_estimator_done : out   std_logic;
          start_i               : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component pi_controller_be
    port( s_angle_pi_acc_out : out   std_logic_vector(43 downto 0);
          s_pll_pi_out       : out   std_logic_vector(17 downto 0);
          s_omega_pi_acc_in  : in    std_logic_vector(43 downto 0) := (others => 'U');
          s_flux_q           : in    std_logic_vector(17 downto 0) := (others => 'U');
          angle_pi_kp_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          angle_pi_ki_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i            : in    std_logic := 'U';
          sys_clk_i          : in    std_logic := 'U';
          s_pll_pi_done      : out   std_logic;
          angle_pi_en_i      : in    std_logic := 'U';
          s_cordic_done      : in    std_logic := 'U'
        );
  end component;

  component filter_be_1
    port( speed_filtered_o         : out   std_logic_vector(17 downto 0);
          s_omega_filter_out_scale : out   std_logic_vector(15 downto 0);
          s_omega_filter_out_prev  : in    std_logic_vector(33 downto 0) := (others => 'U');
          s_pll_pi_out             : in    std_logic_vector(17 downto 0) := (others => 'U');
          omega_filter_factor_i    : in    std_logic_vector(3 downto 0) := (others => 'U');
          reset_i                  : in    std_logic := 'U';
          sys_clk_i                : in    std_logic := 'U';
          done_o                   : out   std_logic;
          s_pll_pi_done            : in    std_logic := 'U'
        );
  end component;

  component accumulator_be
    port( speed_filtered_o          : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_omega_filter_out_prev   : out   std_logic_vector(33 downto 0);
          s_omega_filter_out_scale  : in    std_logic_vector(15 downto 0) := (others => 'U');
          s_omega_pi_acc_in         : out   std_logic_vector(43 downto 0);
          s_angle_pi_acc_out        : in    std_logic_vector(43 downto 0) := (others => 'U');
          s_i_alpha_buf             : out   std_logic_vector(17 downto 0);
          i_alpha_i                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_i_beta_buf              : out   std_logic_vector(17 downto 0);
          i_beta_i                  : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_pll_theta_dly           : out   std_logic_vector(17 downto 0);
          theta_o                   : in    std_logic_vector(17 downto 0) := (others => 'U');
          ealpha_filtered_o         : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_e_alpha_filter_out_prev : out   std_logic_vector(33 downto 0);
          s_ealpha_filter_out_scale : in    std_logic_vector(15 downto 0) := (others => 'U');
          ebeta_filtered_o          : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_e_beta_filter_out_prev  : out   std_logic_vector(33 downto 0);
          s_ebeta_filter_out_scale  : in    std_logic_vector(15 downto 0) := (others => 'U');
          reset_i                   : in    std_logic := 'U';
          sys_clk_i                 : in    std_logic := 'U';
          done_o                    : in    std_logic := 'U';
          s_pll_pi_done             : in    std_logic := 'U';
          s_flux_estimator_done     : in    std_logic := 'U';
          s_pll_theta_done_o        : in    std_logic := 'U';
          s_ealpha_filter_done      : in    std_logic := 'U';
          s_ebeta_filter_done       : in    std_logic := 'U'
        );
  end component;

  component cordic_rot_be
    port( s_flux_q            : out   std_logic_vector(17 downto 0);
          theta_o_i_0         : in    std_logic_vector(17 downto 0) := (others => 'U');
          ebeta_filtered_o    : in    std_logic_vector(17 downto 0) := (others => 'U');
          ealpha_filtered_o   : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i             : in    std_logic := 'U';
          sys_clk_i           : in    std_logic := 'U';
          s_cordic_done       : out   std_logic;
          s_ebeta_filter_done : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \theta_o\ : std_logic_vector(17 downto 0);
    signal \ealpha_o\ : std_logic_vector(17 downto 0);
    signal \ebeta_o\ : std_logic_vector(17 downto 0);
    signal \ealpha_filtered_o\ : std_logic_vector(17 downto 0);
    signal \ebeta_filtered_o\ : std_logic_vector(17 downto 0);
    signal \pll_pi_out_o\ : std_logic_vector(17 downto 0);
    signal \speed_filtered_o\ : std_logic_vector(17 downto 0);
    signal s_i_alpha_buf : std_logic_vector(17 downto 0);
    signal s_i_beta_buf : std_logic_vector(17 downto 0);
    signal s_e_alpha_filter_out_prev : 
        std_logic_vector(33 downto 0);
    signal s_ealpha_filter_out_scale : 
        std_logic_vector(15 downto 0);
    signal s_e_beta_filter_out_prev : 
        std_logic_vector(33 downto 0);
    signal s_ebeta_filter_out_scale : 
        std_logic_vector(15 downto 0);
    signal s_flux_q : std_logic_vector(17 downto 0);
    signal s_omega_pi_acc_in : std_logic_vector(43 downto 0);
    signal s_angle_pi_acc_out : std_logic_vector(43 downto 0);
    signal s_pll_theta_dly : std_logic_vector(17 downto 0);
    signal s_omega_filter_out_prev : 
        std_logic_vector(33 downto 0);
    signal s_omega_filter_out_scale : 
        std_logic_vector(15 downto 0);
    signal theta_o_i_0 : std_logic_vector(17 downto 0);
    signal MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        \EBETA_FILTER_INST.m3_2_03_0_0\, 
        \EBETA_FILTER_INST.m1_2_03_1_0\, 
        \EBETA_FILTER_INST.m8_2_03_3_0\ : std_logic;

    for all : pll_theta_be
	Use entity work.pll_theta_be(DEF_ARCH);
    for all : filter_be_0
	Use entity work.filter_be_0(DEF_ARCH);
    for all : filter_be
	Use entity work.filter_be(DEF_ARCH);
    for all : bldc_model
	Use entity work.bldc_model(DEF_ARCH);
    for all : pi_controller_be
	Use entity work.pi_controller_be(DEF_ARCH);
    for all : filter_be_1
	Use entity work.filter_be_1(DEF_ARCH);
    for all : accumulator_be
	Use entity work.accumulator_be(DEF_ARCH);
    for all : cordic_rot_be
	Use entity work.cordic_rot_be(DEF_ARCH);
begin 

    theta_o(17) <= \theta_o\(17);
    theta_o(16) <= \theta_o\(16);
    theta_o(15) <= \theta_o\(15);
    theta_o(14) <= \theta_o\(14);
    theta_o(13) <= \theta_o\(13);
    theta_o(12) <= \theta_o\(12);
    theta_o(11) <= \theta_o\(11);
    theta_o(10) <= \theta_o\(10);
    theta_o(9) <= \theta_o\(9);
    theta_o(8) <= \theta_o\(8);
    theta_o(7) <= \theta_o\(7);
    theta_o(6) <= \theta_o\(6);
    theta_o(5) <= \theta_o\(5);
    theta_o(4) <= \theta_o\(4);
    theta_o(3) <= \theta_o\(3);
    theta_o(2) <= \theta_o\(2);
    theta_o(1) <= \theta_o\(1);
    theta_o(0) <= \theta_o\(0);
    ealpha_o(17) <= \ealpha_o\(17);
    ealpha_o(16) <= \ealpha_o\(16);
    ealpha_o(15) <= \ealpha_o\(15);
    ealpha_o(14) <= \ealpha_o\(14);
    ealpha_o(13) <= \ealpha_o\(13);
    ealpha_o(12) <= \ealpha_o\(12);
    ealpha_o(11) <= \ealpha_o\(11);
    ealpha_o(10) <= \ealpha_o\(10);
    ealpha_o(9) <= \ealpha_o\(9);
    ealpha_o(8) <= \ealpha_o\(8);
    ealpha_o(7) <= \ealpha_o\(7);
    ealpha_o(6) <= \ealpha_o\(6);
    ealpha_o(5) <= \ealpha_o\(5);
    ealpha_o(4) <= \ealpha_o\(4);
    ealpha_o(3) <= \ealpha_o\(3);
    ealpha_o(2) <= \ealpha_o\(2);
    ealpha_o(1) <= \ealpha_o\(1);
    ealpha_o(0) <= \ealpha_o\(0);
    ebeta_o(17) <= \ebeta_o\(17);
    ebeta_o(16) <= \ebeta_o\(16);
    ebeta_o(15) <= \ebeta_o\(15);
    ebeta_o(14) <= \ebeta_o\(14);
    ebeta_o(13) <= \ebeta_o\(13);
    ebeta_o(12) <= \ebeta_o\(12);
    ebeta_o(11) <= \ebeta_o\(11);
    ebeta_o(10) <= \ebeta_o\(10);
    ebeta_o(9) <= \ebeta_o\(9);
    ebeta_o(8) <= \ebeta_o\(8);
    ebeta_o(7) <= \ebeta_o\(7);
    ebeta_o(6) <= \ebeta_o\(6);
    ebeta_o(5) <= \ebeta_o\(5);
    ebeta_o(4) <= \ebeta_o\(4);
    ebeta_o(3) <= \ebeta_o\(3);
    ebeta_o(2) <= \ebeta_o\(2);
    ebeta_o(1) <= \ebeta_o\(1);
    ebeta_o(0) <= \ebeta_o\(0);
    ealpha_filtered_o(17) <= \ealpha_filtered_o\(17);
    ealpha_filtered_o(16) <= \ealpha_filtered_o\(16);
    ealpha_filtered_o(15) <= \ealpha_filtered_o\(15);
    ealpha_filtered_o(14) <= \ealpha_filtered_o\(14);
    ealpha_filtered_o(13) <= \ealpha_filtered_o\(13);
    ealpha_filtered_o(12) <= \ealpha_filtered_o\(12);
    ealpha_filtered_o(11) <= \ealpha_filtered_o\(11);
    ealpha_filtered_o(10) <= \ealpha_filtered_o\(10);
    ealpha_filtered_o(9) <= \ealpha_filtered_o\(9);
    ealpha_filtered_o(8) <= \ealpha_filtered_o\(8);
    ealpha_filtered_o(7) <= \ealpha_filtered_o\(7);
    ealpha_filtered_o(6) <= \ealpha_filtered_o\(6);
    ealpha_filtered_o(5) <= \ealpha_filtered_o\(5);
    ealpha_filtered_o(4) <= \ealpha_filtered_o\(4);
    ealpha_filtered_o(3) <= \ealpha_filtered_o\(3);
    ealpha_filtered_o(2) <= \ealpha_filtered_o\(2);
    ealpha_filtered_o(1) <= \ealpha_filtered_o\(1);
    ealpha_filtered_o(0) <= \ealpha_filtered_o\(0);
    ebeta_filtered_o(17) <= \ebeta_filtered_o\(17);
    ebeta_filtered_o(16) <= \ebeta_filtered_o\(16);
    ebeta_filtered_o(15) <= \ebeta_filtered_o\(15);
    ebeta_filtered_o(14) <= \ebeta_filtered_o\(14);
    ebeta_filtered_o(13) <= \ebeta_filtered_o\(13);
    ebeta_filtered_o(12) <= \ebeta_filtered_o\(12);
    ebeta_filtered_o(11) <= \ebeta_filtered_o\(11);
    ebeta_filtered_o(10) <= \ebeta_filtered_o\(10);
    ebeta_filtered_o(9) <= \ebeta_filtered_o\(9);
    ebeta_filtered_o(8) <= \ebeta_filtered_o\(8);
    ebeta_filtered_o(7) <= \ebeta_filtered_o\(7);
    ebeta_filtered_o(6) <= \ebeta_filtered_o\(6);
    ebeta_filtered_o(5) <= \ebeta_filtered_o\(5);
    ebeta_filtered_o(4) <= \ebeta_filtered_o\(4);
    ebeta_filtered_o(3) <= \ebeta_filtered_o\(3);
    ebeta_filtered_o(2) <= \ebeta_filtered_o\(2);
    ebeta_filtered_o(1) <= \ebeta_filtered_o\(1);
    ebeta_filtered_o(0) <= \ebeta_filtered_o\(0);
    pll_pi_out_o(17) <= \pll_pi_out_o\(17);
    pll_pi_out_o(16) <= \pll_pi_out_o\(16);
    pll_pi_out_o(15) <= \pll_pi_out_o\(15);
    pll_pi_out_o(14) <= \pll_pi_out_o\(14);
    pll_pi_out_o(13) <= \pll_pi_out_o\(13);
    pll_pi_out_o(12) <= \pll_pi_out_o\(12);
    pll_pi_out_o(11) <= \pll_pi_out_o\(11);
    pll_pi_out_o(10) <= \pll_pi_out_o\(10);
    pll_pi_out_o(9) <= \pll_pi_out_o\(9);
    pll_pi_out_o(8) <= \pll_pi_out_o\(8);
    pll_pi_out_o(7) <= \pll_pi_out_o\(7);
    pll_pi_out_o(6) <= \pll_pi_out_o\(6);
    pll_pi_out_o(5) <= \pll_pi_out_o\(5);
    pll_pi_out_o(4) <= \pll_pi_out_o\(4);
    pll_pi_out_o(3) <= \pll_pi_out_o\(3);
    pll_pi_out_o(2) <= \pll_pi_out_o\(2);
    pll_pi_out_o(1) <= \pll_pi_out_o\(1);
    pll_pi_out_o(0) <= \pll_pi_out_o\(0);
    speed_filtered_o(17) <= \speed_filtered_o\(17);
    speed_filtered_o(16) <= \speed_filtered_o\(16);
    speed_filtered_o(15) <= \speed_filtered_o\(15);
    speed_filtered_o(14) <= \speed_filtered_o\(14);
    speed_filtered_o(13) <= \speed_filtered_o\(13);
    speed_filtered_o(12) <= \speed_filtered_o\(12);
    speed_filtered_o(11) <= \speed_filtered_o\(11);
    speed_filtered_o(10) <= \speed_filtered_o\(10);
    speed_filtered_o(9) <= \speed_filtered_o\(9);
    speed_filtered_o(8) <= \speed_filtered_o\(8);
    speed_filtered_o(7) <= \speed_filtered_o\(7);
    speed_filtered_o(6) <= \speed_filtered_o\(6);
    speed_filtered_o(5) <= \speed_filtered_o\(5);
    speed_filtered_o(4) <= \speed_filtered_o\(4);
    speed_filtered_o(3) <= \speed_filtered_o\(3);
    speed_filtered_o(2) <= \speed_filtered_o\(2);
    speed_filtered_o(1) <= \speed_filtered_o\(1);
    speed_filtered_o(0) <= \speed_filtered_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
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`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=89420)
`protect data_block
[encoded data, 88000 characters]
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`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity SEQ_CONTROLLER_0 is

    port( reset_i         : in    std_logic;
          sys_clk_i       : in    std_logic;
          fault_i         : in    std_logic;
          start_motor_i   : in    std_logic;
          stop_motor_i    : in    std_logic;
          fault_clear_i   : in    std_logic;
          speed_ref_i     : in    std_logic_vector(17 downto 0);
          speed_cl_i      : in    std_logic_vector(17 downto 0);
          vq_i            : in    std_logic_vector(17 downto 0);
          max_ar_i        : in    std_logic_vector(3 downto 0);
          calib_done_i    : in    std_logic;
          pwm_midmatch_i  : in    std_logic;
          foc_done_i      : in    std_logic;
          config_reg_i    : in    std_logic_vector(3 downto 0);
          adc_start_o     : out   std_logic;
          cl_status_o     : out   std_logic;
          en_idq_pi_o     : out   std_logic;
          en_pwm_o        : out   std_logic;
          motor_stopped_o : out   std_logic;
          reset_rl_o      : out   std_logic;
          soft_stop_o     : out   std_logic;
          sensor_reset_o  : out   std_logic;
          state_o         : out   std_logic_vector(3 downto 0)
        );

end SEQ_CONTROLLER_0;

architecture DEF_ARCH of SEQ_CONTROLLER_0 is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal MSC_net_82 : std_logic;
    signal s_state : std_logic_vector(8 downto 1);
    signal s_restart_count : std_logic_vector(3 downto 0);
    signal s_adctrig_count : std_logic_vector(12 downto 0);
    signal s_state_ns : std_logic_vector(6 downto 0);
    signal s_state_ns_0_0_0_a2 : std_logic_vector(0 to 0);
    signal inf_abs1 : std_logic_vector(17 downto 0);
    signal inf_abs0 : std_logic_vector(17 downto 0);
    signal s_state_ns_0_a3_0 : std_logic_vector(6 to 6);
    signal s_adctrig_count_cry : std_logic_vector(11 downto 0);
    signal s_adctrig_count_s : std_logic_vector(12 downto 0);
    signal s_sensor_calib_count : std_logic_vector(13 downto 0);
    signal s_sensor_calib_count_cry : 
        std_logic_vector(12 downto 0);
    signal s_sensor_calib_count_s : 
        std_logic_vector(13 downto 0);
    signal s_state_ns_i_i_a4_0_0_o2_6 : std_logic_vector(2 to 2);
    signal s_state_ns_i_i_a4_0_0_o2_7 : std_logic_vector(2 to 2);
    signal s_state_ns_i_i_a4_0_0_o2_8 : std_logic_vector(2 to 2);
    signal s_state_ns_i_i_a4_0_0_o2_9 : std_logic_vector(2 to 2);
    signal s_state_ns_0_a3_1_0 : std_logic_vector(6 to 6);
    signal s_state_ns_i_i_a2_4_a2_0_a3_0 : 
        std_logic_vector(1 to 1);
    signal s_state_ns_0_0_0_a3_2_0 : std_logic_vector(4 to 4);
    signal s_state_ns_i_3_0_i_0_a3_2 : std_logic_vector(7 to 7);
    signal s_state_ns_0_0_0_1 : std_logic_vector(0 to 0);
    signal s_state_ns_0_0 : std_logic_vector(6 to 6);
    signal s_state_ns_0_0_0_0 : std_logic_vector(4 downto 3);
    signal s_state_ns_0_0_0_2 : std_logic_vector(4 downto 3);
    signal s_state_ns_0_0_0_1_1 : std_logic_vector(0 to 0);
    signal s_state_fast : std_logic_vector(7 downto 1);
    signal s_sensor_calib_count_RNICLE93_Y : 
        std_logic_vector(12 to 12);
    signal s_sensor_calib_count_RNO_FCO : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNO_Y : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNI3PI33_Y : 
        std_logic_vector(11 to 11);
    signal s_sensor_calib_count_RNIRTMT2_Y : 
        std_logic_vector(10 to 10);
    signal s_sensor_calib_count_RNIK3RN2_Y : 
        std_logic_vector(9 to 9);
    signal s_sensor_calib_count_RNILCCG2_Y : 
        std_logic_vector(8 to 8);
    signal s_sensor_calib_count_RNINMT82_Y : 
        std_logic_vector(7 to 7);
    signal s_sensor_calib_count_RNIQ1F12_Y : 
        std_logic_vector(6 to 6);
    signal s_sensor_calib_count_RNIUD0Q1_Y : 
        std_logic_vector(5 to 5);
    signal s_sensor_calib_count_RNI3RHI1_Y : 
        std_logic_vector(4 to 4);
    signal s_sensor_calib_count_RNI993B1_Y : 
        std_logic_vector(3 to 3);
    signal s_sensor_calib_count_RNIGOK31_Y : 
        std_logic_vector(2 to 2);
    signal s_sensor_calib_count_RNIO86S_Y : 
        std_logic_vector(1 to 1);
    signal s_sensor_calib_count_RNI1QNK_Y : 
        std_logic_vector(0 to 0);
    signal s_sensor_calib_count_RNIBC9D_S : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNIBC9D_Y : 
        std_logic_vector(13 to 13);
    signal s_adctrig_count_cry_Y : std_logic_vector(11 downto 0);
    signal s_adctrig_count_s_FCO : std_logic_vector(12 to 12);
    signal s_adctrig_count_s_Y : std_logic_vector(12 to 12);
    signal s_adctrig_count_cry_cy_S : std_logic_vector(0 to 0);
    signal s_adctrig_count_cry_cy_Y : std_logic_vector(0 to 0);
    signal MSC_net_274, MSC_net_275, MSC_net_276, MSC_net_277, 
        MSC_net_278, MSC_net_279, \ADC_START_PROC.adc_start_o_3\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs\, 
        \EN_SPEED_PI_PROC.un110_s_state\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs\, 
        \EN_SPEED_PI_PROC.un111_s_state\, MSC_net_285, 
        MSC_net_286, MSC_net_287, MSC_net_288, MSC_net_289, 
        MSC_net_290, MSC_net_291, MSC_net_292, MSC_net_293, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_0_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_1_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_2_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_3_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_4_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_5_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_6_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_7_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_8_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_9_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_10_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_11_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_12_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_13_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_14_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_15_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_16_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_0_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_1_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_2_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_3_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_4_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_5_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_6_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_7_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_8_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_9_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_10_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_11_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_12_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_13_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_14_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_15_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_16_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_0_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_1_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_2_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_3_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_4_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_5_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_6_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_7_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_8_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_9_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_10_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_11_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_12_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_13_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_14\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_15\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_16\, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        \ADC_START_PROC.op_eq.un98_s_state_Z\, MSC_net_350, 
        MSC_net_351, MSC_net_352, MSC_net_353, MSC_net_354, 
        MSC_net_355, MSC_net_356, MSC_net_357, MSC_net_358, 
        MSC_net_359, MSC_net_360, MSC_net_361, MSC_net_362, 
        MSC_net_363, MSC_net_364, MSC_net_365, MSC_net_366, 
        MSC_net_367, MSC_net_368, MSC_net_369, MSC_net_370, 
        MSC_net_371, MSC_net_372, MSC_net_373, MSC_net_374, 
        MSC_net_375, MSC_net_376, MSC_net_377, MSC_net_378, 
        MSC_net_379, MSC_net_380, MSC_net_381, MSC_net_382, 
        MSC_net_383, MSC_net_384, MSC_net_385, MSC_net_386, 
        MSC_net_387, MSC_net_388, MSC_net_389, MSC_net_390, 
        MSC_net_391, MSC_net_392, MSC_net_393, MSC_net_394, 
        MSC_net_395, MSC_net_396, MSC_net_397, MSC_net_398, 
        MSC_net_399, MSC_net_400, MSC_net_401, MSC_net_402, 
        MSC_net_403, \ADC_START_PROC.adc_start_o_3_iv_0_a3_0_0\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un8_fault_i_NE_0_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un8_fault_i_NE_1_Z\, 
        \ADC_START_PROC.op_eq.un98_s_state_7_Z\, 
        \ADC_START_PROC.op_eq.un98_s_state_8_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_9_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_10_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_11_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_12_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_14_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_15_Z\, 
        MSC_net_415, MSC_net_416, MSC_net_417, MSC_net_418, 
        MSC_net_419, MSC_net_420, MSC_net_421, MSC_net_422, 
        MSC_net_423, MSC_net_424, MSC_net_425, MSC_net_426, 
        MSC_net_427, MSC_net_428, 
        \ADC_START_PROC.op_eq.un98_s_state_1_Z\, MSC_net_430, 
        MSC_net_431, MSC_net_432, MSC_net_433, MSC_net_434, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, MSC_net_442, 
        MSC_net_443, MSC_net_444, MSC_net_445, MSC_net_446, 
        MSC_net_447, MSC_net_448, MSC_net_449, MSC_net_450, 
        MSC_net_451, MSC_net_452, MSC_net_453, MSC_net_454, 
        MSC_net_455, MSC_net_456, MSC_net_457, MSC_net_458, 
        MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, MSC_net_470, 
        MSC_net_471, MSC_net_472, MSC_net_473, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        MSC_net_479, MSC_net_480, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_17_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_17_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_16_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_16_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_15_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_15_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_14_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_14_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_13_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_13_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_12_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_12_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_11_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_11_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_10_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_10_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_9_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_9_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_8_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_8_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_7_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_7_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_6_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_6_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_5_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_5_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_4_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_4_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_3_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_3_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_2_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_2_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_1_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_1_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_0_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_0_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_17_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_17_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_16_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_16_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_15_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_15_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_14_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_14_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_13_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_13_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_12_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_12_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_11_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_11_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_10_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_10_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_9_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_9_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_8_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_8_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_7_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_7_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_6_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_6_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_5_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_5_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_4_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_4_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_3_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_3_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_2_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_2_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_1_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_1_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_0_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_0_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_13_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_13_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_12_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_12_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_11_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_11_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_10_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_10_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_9_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_9_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_8_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_8_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_7_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_7_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_6_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_6_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_5_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_5_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_4_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_4_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_3_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_3_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_2_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_2_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_1_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_1_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_0_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_0_Y\
         : std_logic;

begin 

    sensor_reset_o <= MSC_net_82;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
dhQCQBiKuJsPnghi/3Yb6chrhgJp5AGtP1csCh3XSkb6fV9s5j+ksf99tsOYD8VB
aDjS8N2f8YHa07mTVcowteCge9sIDUWjOaK3NC04YiM8qB2CCUL7/h88BmP+LxvR
K2P/IbFUrveZEITU+4vJhd5uMh6u2lzLjDmPf67uHAc=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=103395)
`protect data_block
[encoded data, 101760 characters]
9WprCd+j+QQ0SSXlahWsLttmi9ojFJLb5bvwQWuVhMc=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_rot_foc_0 is

    port( s_xo          : out   std_logic_vector(17 downto 0);
          s_yo          : out   std_logic_vector(17 downto 0);
          s_yi_0        : in    std_logic;
          s_yi_1        : in    std_logic;
          s_yi_2        : in    std_logic;
          s_yi_3        : in    std_logic;
          s_yi_4        : in    std_logic;
          s_yi_5        : in    std_logic;
          s_yi_6        : in    std_logic;
          s_yi_7        : in    std_logic;
          s_yi_8        : in    std_logic;
          s_yi_10       : in    std_logic;
          s_yi_11       : in    std_logic;
          s_yi_12       : in    std_logic;
          s_yi_13       : in    std_logic;
          s_yi_14       : in    std_logic;
          s_yi_15       : in    std_logic;
          s_yi_16       : in    std_logic;
          s_xi          : in    std_logic_vector(16 downto 0);
          ibeta_i       : in    std_logic_vector(10 to 10);
          vq_i          : in    std_logic_vector(10 to 10);
          reset_i       : in    std_logic;
          sys_clk_i     : in    std_logic;
          N_605         : in    std_logic;
          N_606         : in    std_logic;
          N_607         : in    std_logic;
          N_608         : in    std_logic;
          N_609         : in    std_logic;
          N_592         : in    std_logic;
          N_593         : in    std_logic;
          N_594         : in    std_logic;
          N_595         : in    std_logic;
          N_596         : in    std_logic;
          N_597         : in    std_logic;
          N_598         : in    std_logic;
          N_599         : in    std_logic;
          N_600         : in    std_logic;
          N_601         : in    std_logic;
          N_602         : in    std_logic;
          N_603         : in    std_logic;
          N_604         : in    std_logic;
          s_cordic_done : out   std_logic;
          start_ipark_i : in    std_logic;
          start_park_i  : in    std_logic;
          s_start       : in    std_logic
        );

end cordic_rot_foc_0;

architecture DEF_ARCH of cordic_rot_foc_0 is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal x_o_5 : std_logic_vector(17 downto 0);
    signal s_index : std_logic_vector(3 downto 0);
    signal s_index_7 : std_logic_vector(0 to 0);
    signal s_index_7_iv_i_0 : std_logic_vector(3 downto 1);
    signal y_o_3_1 : std_logic_vector(17 downto 0);
    signal s_theta_c : std_logic_vector(17 downto 0);
    signal s_theta_c_9 : std_logic_vector(17 downto 0);
    signal un1_s_theta_c3_1_i_0 : std_logic_vector(0 to 0);
    signal s_xi_rot : std_logic_vector(17 downto 0);
    signal s_xi_rot_7 : std_logic_vector(17 downto 0);
    signal un1_s_theta_c3_i_0 : std_logic_vector(0 to 0);
    signal s_yi_rot : std_logic_vector(16 downto 1);
    signal s_yi_rot_7 : std_logic_vector(17 downto 0);
    signal s_theta_i : std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(0 to 0);
    signal un1_s_yout : std_logic_vector(17 downto 1);
    signal s_yi_rot_7_bm : std_logic_vector(9 to 9);
    signal un1_s_xout : std_logic_vector(17 downto 0);
    signal un4_s_theta_c : std_logic_vector(14 downto 12);
    signal y_o_3 : std_logic_vector(17 downto 1);
    signal s_theta_i_RNI0KP4_FCO : std_logic_vector(17 to 17);
    signal s_theta_i_RNI0KP4_S : std_logic_vector(17 to 17);
    signal s_theta_i_RNI0KP4_Y : std_logic_vector(17 to 17);
    signal s_xi_rot_RNIVHRG_Y : std_logic_vector(0 to 0);
    signal s_xi_rot_RNIVGTS_Y : std_logic_vector(1 to 1);
    signal s_xi_rot_RNI0HV81_Y : std_logic_vector(2 to 2);
    signal s_xi_rot_RNI2I1L1_Y : std_logic_vector(3 to 3);
    signal s_xi_rot_RNI5K312_Y : std_logic_vector(4 to 4);
    signal s_xi_rot_RNI9N5D2_Y : std_logic_vector(5 to 5);
    signal s_xi_rot_RNIER7P2_Y : std_logic_vector(6 to 6);
    signal s_xi_rot_RNIK0A53_Y : std_logic_vector(7 to 7);
    signal s_xi_rot_RNIR6CH3_Y : std_logic_vector(8 to 8);
    signal s_xi_rot_RNI3EET3_Y : std_logic_vector(9 to 9);
    signal s_xi_rot_RNIJ1QH4_Y : std_logic_vector(10 to 10);
    signal s_xi_rot_RNI4M565_Y : std_logic_vector(11 to 11);
    signal s_xi_rot_RNIMBHQ5_Y : std_logic_vector(12 to 12);
    signal s_xi_rot_RNI92TE6_Y : std_logic_vector(13 to 13);
    signal s_xi_rot_RNITP837_Y : std_logic_vector(14 to 14);
    signal s_xi_rot_RNIIIKN7_Y : std_logic_vector(15 to 15);
    signal s_xi_rot_RNIV6C09_FCO : std_logic_vector(17 to 17);
    signal s_xi_rot_RNIV6C09_Y : std_logic_vector(17 to 17);
    signal s_xi_rot_RNI8C0C8_Y : std_logic_vector(16 to 16);
    signal un4_s_theta_c_1 : std_logic_vector(1 to 1);
    signal MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, MSC_net_350, MSC_net_351, MSC_net_352, 
        MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459, MSC_net_460, 
        MSC_net_461, MSC_net_462, MSC_net_463, MSC_net_464, 
        MSC_net_465, MSC_net_466, MSC_net_467, MSC_net_468, 
        MSC_net_469, MSC_net_470, MSC_net_471, MSC_net_472, 
        MSC_net_473, MSC_net_474, MSC_net_475, MSC_net_476, 
        MSC_net_477, MSC_net_478, MSC_net_479, MSC_net_480, 
        MSC_net_481, MSC_net_482, MSC_net_483, MSC_net_484, 
        MSC_net_485, MSC_net_486, MSC_net_487, MSC_net_488, 
        MSC_net_489, MSC_net_490, MSC_net_491, MSC_net_492, 
        MSC_net_493, MSC_net_494, MSC_net_495, MSC_net_496, 
        MSC_net_497, MSC_net_498, MSC_net_499, MSC_net_500, 
        MSC_net_501, MSC_net_502, MSC_net_503, MSC_net_504, 
        MSC_net_505, MSC_net_506, MSC_net_507, MSC_net_508, 
        MSC_net_509, MSC_net_510, MSC_net_511, MSC_net_512, 
        MSC_net_513, MSC_net_514, MSC_net_515, MSC_net_516, 
        MSC_net_517, MSC_net_518, MSC_net_519, MSC_net_520, 
        MSC_net_521, MSC_net_522, MSC_net_523, MSC_net_524, 
        MSC_net_525, MSC_net_526, MSC_net_527, MSC_net_528, 
        MSC_net_529, MSC_net_530, MSC_net_531, MSC_net_532, 
        MSC_net_533, MSC_net_534, MSC_net_535, MSC_net_536, 
        MSC_net_537, MSC_net_538, MSC_net_539, MSC_net_540, 
        MSC_net_541, MSC_net_542, MSC_net_543, MSC_net_544, 
        MSC_net_545, MSC_net_546, MSC_net_547, MSC_net_548, 
        MSC_net_549, MSC_net_550, MSC_net_551, MSC_net_552, 
        MSC_net_553, MSC_net_554, MSC_net_555, MSC_net_556, 
        MSC_net_557, MSC_net_558, MSC_net_559, MSC_net_560, 
        MSC_net_561, MSC_net_562, MSC_net_563, MSC_net_564, 
        MSC_net_565, MSC_net_566, MSC_net_567, MSC_net_568, 
        MSC_net_569, MSC_net_570, MSC_net_571, MSC_net_572, 
        MSC_net_573, MSC_net_574, MSC_net_575, MSC_net_576, 
        MSC_net_577, MSC_net_578, MSC_net_579, MSC_net_580, 
        MSC_net_581, MSC_net_582, MSC_net_583, MSC_net_584, 
        MSC_net_585, MSC_net_586, MSC_net_587, MSC_net_588, 
        MSC_net_589, MSC_net_590, MSC_net_591, MSC_net_592, 
        MSC_net_593, MSC_net_594, MSC_net_595, MSC_net_596, 
        MSC_net_597, MSC_net_598, MSC_net_599, MSC_net_600, 
        MSC_net_601, MSC_net_602, MSC_net_603, MSC_net_604, 
        MSC_net_605, MSC_net_606, MSC_net_607, MSC_net_608, 
        MSC_net_609, MSC_net_610, MSC_net_611, MSC_net_612, 
        MSC_net_613, MSC_net_614, MSC_net_615, MSC_net_616, 
        MSC_net_617, MSC_net_618, MSC_net_619, MSC_net_620, 
        MSC_net_621, MSC_net_622, MSC_net_623, MSC_net_624, 
        MSC_net_625, MSC_net_626, MSC_net_627, MSC_net_628, 
        MSC_net_629, MSC_net_630, MSC_net_631, MSC_net_632, 
        MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        MSC_net_641, MSC_net_642, MSC_net_643, MSC_net_644, 
        MSC_net_645, MSC_net_646, MSC_net_647, MSC_net_648, 
        MSC_net_649, MSC_net_650, MSC_net_651, MSC_net_652, 
        MSC_net_653, MSC_net_654, MSC_net_655, MSC_net_656, 
        MSC_net_657, MSC_net_658, MSC_net_659, MSC_net_660, 
        MSC_net_661, MSC_net_662, MSC_net_663, MSC_net_664, 
        MSC_net_665, MSC_net_666, MSC_net_667, MSC_net_668, 
        MSC_net_669, MSC_net_670, MSC_net_671, MSC_net_672, 
        MSC_net_673, MSC_net_674, MSC_net_675, MSC_net_676, 
        MSC_net_677, MSC_net_678, MSC_net_679, MSC_net_680, 
        MSC_net_681, MSC_net_682, MSC_net_683, MSC_net_684, 
        MSC_net_685, MSC_net_686, MSC_net_687, MSC_net_688, 
        MSC_net_689, MSC_net_690, MSC_net_691, MSC_net_692, 
        MSC_net_693, MSC_net_694, MSC_net_695, MSC_net_696, 
        MSC_net_697, MSC_net_698, MSC_net_699, MSC_net_700, 
        MSC_net_701, MSC_net_702, MSC_net_703, MSC_net_704, 
        MSC_net_705, MSC_net_706, MSC_net_707, MSC_net_708, 
        MSC_net_709, MSC_net_710, MSC_net_711, MSC_net_712, 
        MSC_net_713, MSC_net_714, MSC_net_715, MSC_net_716, 
        MSC_net_717, MSC_net_718, MSC_net_719, MSC_net_720, 
        MSC_net_721, MSC_net_722, MSC_net_723, MSC_net_724, 
        MSC_net_725, MSC_net_726, MSC_net_727, MSC_net_728, 
        MSC_net_729, MSC_net_730, MSC_net_731, MSC_net_732, 
        MSC_net_733, MSC_net_734, MSC_net_735, MSC_net_736, 
        MSC_net_737, MSC_net_738, MSC_net_739, MSC_net_740, 
        MSC_net_741, MSC_net_742, MSC_net_743, MSC_net_744, 
        MSC_net_745, MSC_net_746, MSC_net_747, MSC_net_748, 
        MSC_net_749, MSC_net_750, MSC_net_751, MSC_net_752, 
        MSC_net_753, MSC_net_754, MSC_net_755, MSC_net_756, 
        MSC_net_757, MSC_net_758, MSC_net_759, MSC_net_760, 
        MSC_net_761, MSC_net_762, MSC_net_763, MSC_net_764, 
        MSC_net_765, MSC_net_766, MSC_net_767, MSC_net_768, 
        MSC_net_769, MSC_net_770 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
op83BnEIuds/YKzWtvrgovoQycu69ofZSFp5HdeInPCXOJYK9ZJldtZ/JGhWbwPt
PoybvV6drsA9By1cPY/L7eckee1RcFp2qx0QuppeO44fPjvcFi20E9wmGYOhtLIS
eQGjhKOhZmqPe1aQnZwU/a7QfaSSAbiYrpZiaM05wsw=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=141920)
`protect data_block
[encoded data, 139712 characters]
lO/jQguxsH1rt7s8tel9zA==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_scale_0 is

    port( s_xo_scale           : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9);
          s_yo_scale           : out   std_logic_vector(17 downto 0);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0);
          s_yo                 : in    std_logic_vector(17 downto 0);
          s_xo                 : in    std_logic_vector(17 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          s_done_o             : out   std_logic;
          s_mas_en_from_cordic : out   std_logic;
          s_mas_done_to_cordic : in    std_logic;
          s_mas_done_from_mas  : in    std_logic;
          s_cordic_done        : in    std_logic
        );

end cordic_scale_0;

architecture DEF_ARCH of cordic_scale_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal s_state : std_logic_vector(1 downto 0);
    signal MSC_net_119, MSC_net_120, MSC_net_121, MSC_net_122, 
        MSC_net_123, MSC_net_124, MSC_net_125, MSC_net_126, 
        MSC_net_127, MSC_net_128, MSC_net_129, MSC_net_130, 
        MSC_net_131, MSC_net_132, MSC_net_133, MSC_net_134, 
        MSC_net_135, MSC_net_136, MSC_net_137, MSC_net_138, 
        MSC_net_139, MSC_net_140, MSC_net_141, MSC_net_142, 
        MSC_net_143, MSC_net_144, MSC_net_145, MSC_net_146, 
        MSC_net_147 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
SR8RUO0zo6KGuTQqzJYXKM8YmwwqfwJk7GHfVbPUTFDtyDiO5jzIlTA5ntRKP/IR
LKH11NE93xblnJ9TV10lkoqquClzjP2JYm4G4QxhQlTBkeOQab+CbowiXR7sqDQX
qeb8DHcGBAnC2gMZ6gwNfZUH+BB7QOU1w2RJ+U53kBU=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=25850)
`protect data_block
[encoded data, 25408 characters]
GZ5qw9VfenAX+jEn9UHYalqZDWCaBB+adNzVC63NTEg=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_scheduler_foc_0 is

    port( id_o                 : out   std_logic_vector(17 downto 0);
          iq_o                 : out   std_logic_vector(17 downto 0);
          valpha_o             : out   std_logic_vector(17 downto 0);
          vbeta_o              : out   std_logic_vector(17 downto 0);
          ialpha_i             : in    std_logic_vector(17 downto 1);
          vd_i                 : in    std_logic_vector(17 downto 1);
          theta_i              : in    std_logic_vector(17 downto 0);
          ibeta_i              : in    std_logic_vector(17 downto 1);
          vq_i                 : in    std_logic_vector(17 downto 1);
          s_product_from_mas   : in    std_logic_vector(26 downto 9);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          start_park_i_i_0     : in    std_logic;
          ipark_done_o         : out   std_logic;
          park_done_o          : out   std_logic;
          start_park_i         : in    std_logic;
          start_ipark_i        : in    std_logic;
          s_mas_en_from_cordic : out   std_logic;
          s_mas_done_to_cordic : in    std_logic;
          s_mas_done_from_mas  : in    std_logic
        );

end cordic_scheduler_foc_0;

architecture DEF_ARCH of cordic_scheduler_foc_0 is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component cordic_rot_foc_0
    port( s_xo          : out   std_logic_vector(17 downto 0);
          s_yo          : out   std_logic_vector(17 downto 0);
          s_yi_0        : in    std_logic := 'U';
          s_yi_1        : in    std_logic := 'U';
          s_yi_2        : in    std_logic := 'U';
          s_yi_3        : in    std_logic := 'U';
          s_yi_4        : in    std_logic := 'U';
          s_yi_5        : in    std_logic := 'U';
          s_yi_6        : in    std_logic := 'U';
          s_yi_7        : in    std_logic := 'U';
          s_yi_8        : in    std_logic := 'U';
          s_yi_10       : in    std_logic := 'U';
          s_yi_11       : in    std_logic := 'U';
          s_yi_12       : in    std_logic := 'U';
          s_yi_13       : in    std_logic := 'U';
          s_yi_14       : in    std_logic := 'U';
          s_yi_15       : in    std_logic := 'U';
          s_yi_16       : in    std_logic := 'U';
          s_xi          : in    std_logic_vector(16 downto 0) := (others => 'U');
          ibeta_i       : in    std_logic_vector(10 to 10) := (others => 'U');
          vq_i          : in    std_logic_vector(10 to 10) := (others => 'U');
          reset_i       : in    std_logic := 'U';
          sys_clk_i     : in    std_logic := 'U';
          N_605         : in    std_logic := 'U';
          N_606         : in    std_logic := 'U';
          N_607         : in    std_logic := 'U';
          N_608         : in    std_logic := 'U';
          N_609         : in    std_logic := 'U';
          N_592         : in    std_logic := 'U';
          N_593         : in    std_logic := 'U';
          N_594         : in    std_logic := 'U';
          N_595         : in    std_logic := 'U';
          N_596         : in    std_logic := 'U';
          N_597         : in    std_logic := 'U';
          N_598         : in    std_logic := 'U';
          N_599         : in    std_logic := 'U';
          N_600         : in    std_logic := 'U';
          N_601         : in    std_logic := 'U';
          N_602         : in    std_logic := 'U';
          N_603         : in    std_logic := 'U';
          N_604         : in    std_logic := 'U';
          s_cordic_done : out   std_logic;
          start_ipark_i : in    std_logic := 'U';
          start_park_i  : in    std_logic := 'U';
          s_start       : in    std_logic := 'U'
        );
  end component;

  component cordic_scale_0
    port( s_xo_scale           : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9) := (others => 'U');
          s_yo_scale           : out   std_logic_vector(17 downto 0);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0) := (others => 'U');
          s_yo                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_xo                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          s_done_o             : out   std_logic;
          s_mas_en_from_cordic : out   std_logic;
          s_mas_done_to_cordic : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U';
          s_cordic_done        : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal s_xo_scale : std_logic_vector(17 downto 0);
    signal s_yo_scale : std_logic_vector(17 downto 0);
    signal s_xi : std_logic_vector(16 downto 0);
    signal s_yi : std_logic_vector(16 downto 0);
    signal s_xo : std_logic_vector(17 downto 0);
    signal s_yo : std_logic_vector(17 downto 0);
    signal MSC_net_312, MSC_net_313, MSC_net_314, MSC_net_315, 
        MSC_net_316, MSC_net_317, MSC_net_318, MSC_net_319, 
        MSC_net_320, MSC_net_321, MSC_net_322, MSC_net_323, 
        MSC_net_324, MSC_net_325, MSC_net_326, MSC_net_327, 
        MSC_net_328, MSC_net_329, MSC_net_330, MSC_net_331, 
        MSC_net_332, MSC_net_333, MSC_net_334, MSC_net_335, 
        MSC_net_336, MSC_net_337 : std_logic;

    for all : cordic_rot_foc_0
	Use entity work.cordic_rot_foc_0(DEF_ARCH);
    for all : cordic_scale_0
	Use entity work.cordic_scale_0(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
DLzhD6pK3RWf3jtHSAasZVvMQ3WQR5ms4KkrsKyZqYSTuVEXye8FRMRGWJS6v7My
HqeDmNn1+LVYF1+F48RhOItcWG6zl6/J6A7kqORn6y9vXA9+7fl2OSE0dQhN0d+Z
ilCA8iF3MQpQrTIO1ve+k687KtezWXFAU6kbOuQVCPg=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=46410)
`protect data_block
[encoded data, 45696 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity clarke_foc_0 is

    port( ibeta_o              : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9);
          ialpha_o             : out   std_logic_vector(17 downto 0);
          ia_i                 : in    std_logic_vector(17 downto 0);
          s_mul_a_from_clarke  : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke  : out   std_logic_vector(1 to 1);
          ib_i                 : in    std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0);
          s_mul_b_from_iclarke : in    std_logic_vector(2 to 2);
          s_mul_b_to_mas_0     : out   std_logic;
          s_mul_b_to_mas_7     : out   std_logic;
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          clarke_done_o        : out   std_logic;
          s_mas_en_from_clarke : out   std_logic;
          start_clarke_i       : in    std_logic;
          s_mas_done_from_mas  : in    std_logic
        );

end clarke_foc_0;

architecture DEF_ARCH of clarke_foc_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \s_mul_b_from_clarke\ : std_logic_vector(1 to 1);
    signal s_state : std_logic_vector(0 to 0);
    signal MSC_net_121, MSC_net_122, MSC_net_123, MSC_net_124, 
        MSC_net_125, MSC_net_126, MSC_net_127, MSC_net_128, 
        MSC_net_129, MSC_net_130, MSC_net_131, MSC_net_132, 
        MSC_net_133, MSC_net_134, MSC_net_135, MSC_net_136, 
        MSC_net_137, MSC_net_138, MSC_net_139, MSC_net_140, 
        MSC_net_141, MSC_net_142, MSC_net_143, MSC_net_144, 
        MSC_net_145, MSC_net_146, MSC_net_147, MSC_net_148, 
        MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180
         : std_logic;

begin 

    s_mul_b_from_clarke(1) <= \s_mul_b_from_clarke\(1);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
RpBVQU/oR1O2cahVYqVCPJW7vzK+MoKKFRdcP3YsiMAlDNBdwedntgoYVEjQ1Vy9
BjgmXWsD1/k/Byop/cZwgbkIAQNxNhesNggOXCHVlOlnatox5a0yixkBw2DGjH76
FJJH7hFz4ii7iKi+D2/HdYEvkBZEG9LD7hT2WAFk3B8=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=27170)
`protect data_block
[encoded data, 26752 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity inverse_clarke_foc_0 is

    port( s_product_from_mas    : in    std_logic_vector(28 downto 11);
          s_mul_a_from_iclarke  : out   std_logic_vector(17 downto 0);
          vbeta_i               : in    std_logic_vector(17 downto 0);
          va_o                  : out   std_logic_vector(17 downto 0);
          valpha_i              : in    std_logic_vector(17 downto 0);
          s_mul_b_from_iclarke  : out   std_logic_vector(2 to 2);
          vb_o                  : out   std_logic_vector(17 downto 1);
          vc_o                  : out   std_logic_vector(17 downto 0);
          s_mas_sel             : in    std_logic_vector(1 downto 0);
          reset_i               : in    std_logic;
          sys_clk_i             : in    std_logic;
          iclarke_done_o        : out   std_logic;
          s_mas_en_from_iclarke : out   std_logic;
          vb_output_o_axb_0_i_0 : out   std_logic;
          start_iclarke_i       : in    std_logic;
          s_mas_done_from_mas   : in    std_logic
        );

end inverse_clarke_foc_0;

architecture DEF_ARCH of inverse_clarke_foc_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \va_o\ : std_logic_vector(17 downto 0);
    signal \vc_o\ : std_logic_vector(17 downto 0);
    signal s_vc : std_logic_vector(17 downto 1);
    signal s_state : std_logic_vector(0 to 0);
    signal MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220, 
        MSC_net_221, MSC_net_222, MSC_net_223, MSC_net_224, 
        MSC_net_225, MSC_net_226, MSC_net_227, MSC_net_228, 
        MSC_net_229, MSC_net_230, MSC_net_231, MSC_net_232
         : std_logic;

begin 

    \vc_o\(17 downto 1) <= (OTHERS => 'U'); 
    va_o(17) <= \va_o\(17);
    va_o(16) <= \va_o\(16);
    va_o(15) <= \va_o\(15);
    va_o(14) <= \va_o\(14);
    va_o(13) <= \va_o\(13);
    va_o(12) <= \va_o\(12);
    va_o(11) <= \va_o\(11);
    va_o(10) <= \va_o\(10);
    va_o(9) <= \va_o\(9);
    va_o(8) <= \va_o\(8);
    va_o(7) <= \va_o\(7);
    va_o(6) <= \va_o\(6);
    va_o(5) <= \va_o\(5);
    va_o(4) <= \va_o\(4);
    va_o(3) <= \va_o\(3);
    va_o(2) <= \va_o\(2);
    va_o(1) <= \va_o\(1);
    va_o(0) <= \va_o\(0);
    vc_o(0) <= \vc_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
kY5bUCZ+xRhIqx3isB7WKi/RONX7GrasGpxlxgnQ4sjoaMy24M5qlnEVce68k0Kw
rW8Wf8Fp0QoBFNMg60ZlS1AqvJLADVKIg2WI9ejMpNj1jgx4Qf36FcTowGv6PX+S
QMdz4+6IrNVN/k3CKQccrrTCswQTx3dyox3As0DjuAI=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=33000)
`protect data_block
[encoded data, 32448 characters]
t62Sj/Ut67Dgca+YtikkIQZFk5TnS9B+a2NOEf9Toyk=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_scheduler_foc_0 is

    port( s_mas_sel             : out   std_logic_vector(1 downto 0);
          s_mul_a_from_cordic   : in    std_logic_vector(17 downto 0);
          s_mul_a_from_clarke   : in    std_logic_vector(17 downto 0);
          va_o                  : in    std_logic_vector(17 downto 0);
          s_add_c_to_mas_0      : out   std_logic;
          s_add_c_to_mas_1      : out   std_logic;
          s_add_c_to_mas_2      : out   std_logic;
          s_add_c_to_mas_3      : out   std_logic;
          s_add_c_to_mas_4      : out   std_logic;
          s_add_c_to_mas_5      : out   std_logic;
          s_add_c_to_mas_6      : out   std_logic;
          s_add_c_to_mas_7      : out   std_logic;
          s_add_c_to_mas_8      : out   std_logic;
          s_add_c_to_mas_9      : out   std_logic;
          s_add_c_to_mas_10     : out   std_logic;
          s_add_c_to_mas_11     : out   std_logic;
          s_add_c_to_mas_12     : out   std_logic;
          s_add_c_to_mas_13     : out   std_logic;
          s_add_c_to_mas_14     : out   std_logic;
          s_add_c_to_mas_15     : out   std_logic;
          s_add_c_to_mas_16     : out   std_logic;
          s_add_c_to_mas_33     : out   std_logic;
          s_mul_b_from_iclarke  : in    std_logic_vector(2 to 2);
          s_mul_a_from_iclarke  : in    std_logic_vector(17 downto 0);
          s_mul_a_to_mas        : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke   : in    std_logic_vector(1 to 1);
          s_mul_b_to_mas_0      : out   std_logic;
          s_mul_b_to_mas_4      : out   std_logic;
          start_park_i          : in    std_logic;
          start_park_i_i_0      : out   std_logic;
          reset_i               : in    std_logic;
          sys_clk_i             : in    std_logic;
          start_clarke_i        : in    std_logic;
          start_iclarke_i       : in    std_logic;
          start_ipark_i         : in    std_logic;
          s_mas_en_from_cordic  : in    std_logic;
          s_mas_en_from_clarke  : in    std_logic;
          s_mas_done_from_mas   : in    std_logic;
          s_mas_done_to_cordic  : out   std_logic;
          s_mas_en_from_iclarke : in    std_logic;
          s_mas_en_to_mas       : out   std_logic
        );

end mas_scheduler_foc_0;

architecture DEF_ARCH of mas_scheduler_foc_0 is 

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \s_mas_sel\ : std_logic_vector(1 downto 0);
    signal MSC_net_112, MSC_net_127, MSC_net_128, MSC_net_129, 
        MSC_net_130, MSC_net_131, MSC_net_132, MSC_net_133, 
        MSC_net_134, MSC_net_135, MSC_net_136, MSC_net_137, 
        MSC_net_138, MSC_net_139, MSC_net_140, MSC_net_141, 
        MSC_net_142, MSC_net_143, MSC_net_144, MSC_net_145, 
        MSC_net_146, MSC_net_147, MSC_net_148, MSC_net_149, 
        MSC_net_150 : std_logic;

begin 

    s_mas_sel(1) <= \s_mas_sel\(1);
    s_mas_sel(0) <= \s_mas_sel\(0);
    s_mul_b_to_mas_0 <= MSC_net_112;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
ELLOVerurhsx8GKEhKYB3PFeOQTjEZ7a5CVnDPeOX59sqz8HVW3UohCvGLrZKIzp
3VaR+xLxeo+qFpS4GVG8GCxDX1H8Shh0Hfm0T2SiIowA7uuN3uznBA75OOBqgFh7
HG9pjQVgvLedNuKDARK02Oz5/fRodVjICO+TGlaU6l8=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=17920)
`protect data_block
[encoded data, 17600 characters]
9VhSLD5rGzjBnaW/UFrN3BVCxs0l9Ja7ZS3gxCE+NNA=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_foc_0 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_foc_0;

architecture DEF_ARCH of mas_foc_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_151, MSC_net_152, MSC_net_153, MSC_net_154, 
        MSC_net_155, MSC_net_156, MSC_net_157, MSC_net_158, 
        MSC_net_159, MSC_net_160, MSC_net_161, MSC_net_162, 
        MSC_net_163, MSC_net_164, MSC_net_165, MSC_net_166, 
        MSC_net_167, MSC_net_168, MSC_net_169, MSC_net_170, 
        MSC_net_171, MSC_net_172, MSC_net_173, MSC_net_174, 
        MSC_net_175, MSC_net_176 : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(30) <= \product_o\(0);
    product_o(29) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
Bv+xo7nSBocHfiYlsNY7aPcBpleB4MXkG+zlPRm+qjiQrIrAf5NsbD1DVavV/zNl
Vm9RdpsdP2FORXTwATbUewbp11bpFSh3eGeVvEwNT8X5on6zcWaz1aZTZDHGpwMF
ZD34DK3ySdCaL6r5Uo4dfU/qjwcuW0b5wOIJm8TYrjs=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12330)
`protect data_block
[encoded data, 12096 characters]
PIyDhXtYv/MjpkBUp++Im2lxtqw0BaR6pV/G0dPAKcg=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity FOC_TRANSFORMS_0 is

    port( reset_i         : in    std_logic;
          sys_clk_i       : in    std_logic;
          start_clarke_i  : in    std_logic;
          start_park_i    : in    std_logic;
          start_ipark_i   : in    std_logic;
          start_iclarke_i : in    std_logic;
          ia_i            : in    std_logic_vector(17 downto 0);
          ib_i            : in    std_logic_vector(17 downto 0);
          ialpha_i        : in    std_logic_vector(17 downto 0);
          ibeta_i         : in    std_logic_vector(17 downto 0);
          vd_i            : in    std_logic_vector(17 downto 0);
          vq_i            : in    std_logic_vector(17 downto 0);
          valpha_i        : in    std_logic_vector(17 downto 0);
          vbeta_i         : in    std_logic_vector(17 downto 0);
          theta_i         : in    std_logic_vector(17 downto 0);
          clarke_done_o   : out   std_logic;
          park_done_o     : out   std_logic;
          ipark_done_o    : out   std_logic;
          iclarke_done_o  : out   std_logic;
          ialpha_o        : out   std_logic_vector(17 downto 0);
          ibeta_o         : out   std_logic_vector(17 downto 0);
          id_o            : out   std_logic_vector(17 downto 0);
          iq_o            : out   std_logic_vector(17 downto 0);
          valpha_o        : out   std_logic_vector(17 downto 0);
          vbeta_o         : out   std_logic_vector(17 downto 0);
          va_o            : out   std_logic_vector(17 downto 0);
          vb_o            : out   std_logic_vector(17 downto 0);
          vc_o            : out   std_logic_vector(17 downto 0)
        );

end FOC_TRANSFORMS_0;

architecture DEF_ARCH of FOC_TRANSFORMS_0 is 

  component cordic_scheduler_foc_0
    port( id_o                 : out   std_logic_vector(17 downto 0);
          iq_o                 : out   std_logic_vector(17 downto 0);
          valpha_o             : out   std_logic_vector(17 downto 0);
          vbeta_o              : out   std_logic_vector(17 downto 0);
          ialpha_i             : in    std_logic_vector(17 downto 1) := (others => 'U');
          vd_i                 : in    std_logic_vector(17 downto 1) := (others => 'U');
          theta_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          ibeta_i              : in    std_logic_vector(17 downto 1) := (others => 'U');
          vq_i                 : in    std_logic_vector(17 downto 1) := (others => 'U');
          s_product_from_mas   : in    std_logic_vector(26 downto 9) := (others => 'U');
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          start_park_i_i_0     : in    std_logic := 'U';
          ipark_done_o         : out   std_logic;
          park_done_o          : out   std_logic;
          start_park_i         : in    std_logic := 'U';
          start_ipark_i        : in    std_logic := 'U';
          s_mas_en_from_cordic : out   std_logic;
          s_mas_done_to_cordic : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U'
        );
  end component;

  component clarke_foc_0
    port( ibeta_o              : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9) := (others => 'U');
          ialpha_o             : out   std_logic_vector(17 downto 0);
          ia_i                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_a_from_clarke  : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke  : out   std_logic_vector(1 to 1);
          ib_i                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mas_sel            : in    std_logic_vector(1 downto 0) := (others => 'U');
          s_mul_b_from_iclarke : in    std_logic_vector(2 to 2) := (others => 'U');
          s_mul_b_to_mas_0     : out   std_logic;
          s_mul_b_to_mas_7     : out   std_logic;
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          clarke_done_o        : out   std_logic;
          s_mas_en_from_clarke : out   std_logic;
          start_clarke_i       : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U'
        );
  end component;

  component inverse_clarke_foc_0
    port( s_product_from_mas    : in    std_logic_vector(28 downto 11) := (others => 'U');
          s_mul_a_from_iclarke  : out   std_logic_vector(17 downto 0);
          vbeta_i               : in    std_logic_vector(17 downto 0) := (others => 'U');
          va_o                  : out   std_logic_vector(17 downto 0);
          valpha_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_b_from_iclarke  : out   std_logic_vector(2 to 2);
          vb_o                  : out   std_logic_vector(17 downto 1);
          vc_o                  : out   std_logic_vector(17 downto 0);
          s_mas_sel             : in    std_logic_vector(1 downto 0) := (others => 'U');
          reset_i               : in    std_logic := 'U';
          sys_clk_i             : in    std_logic := 'U';
          iclarke_done_o        : out   std_logic;
          s_mas_en_from_iclarke : out   std_logic;
          vb_output_o_axb_0_i_0 : out   std_logic;
          start_iclarke_i       : in    std_logic := 'U';
          s_mas_done_from_mas   : in    std_logic := 'U'
        );
  end component;

  component mas_scheduler_foc_0
    port( s_mas_sel             : out   std_logic_vector(1 downto 0);
          s_mul_a_from_cordic   : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_a_from_clarke   : in    std_logic_vector(17 downto 0) := (others => 'U');
          va_o                  : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_add_c_to_mas_0      : out   std_logic;
          s_add_c_to_mas_1      : out   std_logic;
          s_add_c_to_mas_2      : out   std_logic;
          s_add_c_to_mas_3      : out   std_logic;
          s_add_c_to_mas_4      : out   std_logic;
          s_add_c_to_mas_5      : out   std_logic;
          s_add_c_to_mas_6      : out   std_logic;
          s_add_c_to_mas_7      : out   std_logic;
          s_add_c_to_mas_8      : out   std_logic;
          s_add_c_to_mas_9      : out   std_logic;
          s_add_c_to_mas_10     : out   std_logic;
          s_add_c_to_mas_11     : out   std_logic;
          s_add_c_to_mas_12     : out   std_logic;
          s_add_c_to_mas_13     : out   std_logic;
          s_add_c_to_mas_14     : out   std_logic;
          s_add_c_to_mas_15     : out   std_logic;
          s_add_c_to_mas_16     : out   std_logic;
          s_add_c_to_mas_33     : out   std_logic;
          s_mul_b_from_iclarke  : in    std_logic_vector(2 to 2) := (others => 'U');
          s_mul_a_from_iclarke  : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_a_to_mas        : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke   : in    std_logic_vector(1 to 1) := (others => 'U');
          s_mul_b_to_mas_0      : out   std_logic;
          s_mul_b_to_mas_4      : out   std_logic;
          start_park_i          : in    std_logic := 'U';
          start_park_i_i_0      : out   std_logic;
          reset_i               : in    std_logic := 'U';
          sys_clk_i             : in    std_logic := 'U';
          start_clarke_i        : in    std_logic := 'U';
          start_iclarke_i       : in    std_logic := 'U';
          start_ipark_i         : in    std_logic := 'U';
          s_mas_en_from_cordic  : in    std_logic := 'U';
          s_mas_en_from_clarke  : in    std_logic := 'U';
          s_mas_done_from_mas   : in    std_logic := 'U';
          s_mas_done_to_cordic  : out   std_logic;
          s_mas_en_from_iclarke : in    std_logic := 'U';
          s_mas_en_to_mas       : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_foc_0
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \va_o\ : std_logic_vector(17 downto 0);
    signal s_mul_a_from_clarke : std_logic_vector(17 downto 0);
    signal s_mul_b_from_clarke : std_logic_vector(1 to 1);
    signal s_mul_a_from_cordic : std_logic_vector(17 downto 0);
    signal s_mul_a_from_iclarke : std_logic_vector(17 downto 0);
    signal s_mul_b_from_iclarke : std_logic_vector(2 to 2);
    signal s_mul_a_to_mas : std_logic_vector(17 downto 0);
    signal s_mul_b_to_mas : std_logic_vector(9 downto 0);
    signal s_add_c_to_mas : std_logic_vector(43 downto 10);
    signal s_product_from_mas : std_logic_vector(28 downto 9);
    signal \MAS_SCHEDULER_INST.s_mas_sel\ : 
        std_logic_vector(1 downto 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_518, MSC_net_519, MSC_net_520, MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526 : std_logic;

    for all : cordic_scheduler_foc_0
	Use entity work.cordic_scheduler_foc_0(DEF_ARCH);
    for all : clarke_foc_0
	Use entity work.clarke_foc_0(DEF_ARCH);
    for all : inverse_clarke_foc_0
	Use entity work.inverse_clarke_foc_0(DEF_ARCH);
    for all : mas_scheduler_foc_0
	Use entity work.mas_scheduler_foc_0(DEF_ARCH);
    for all : mas_foc_0
	Use entity work.mas_foc_0(DEF_ARCH);
begin 

    va_o(17) <= \va_o\(17);
    va_o(16) <= \va_o\(16);
    va_o(15) <= \va_o\(15);
    va_o(14) <= \va_o\(14);
    va_o(13) <= \va_o\(13);
    va_o(12) <= \va_o\(12);
    va_o(11) <= \va_o\(11);
    va_o(10) <= \va_o\(10);
    va_o(9) <= \va_o\(9);
    va_o(8) <= \va_o\(8);
    va_o(7) <= \va_o\(7);
    va_o(6) <= \va_o\(6);
    va_o(5) <= \va_o\(5);
    va_o(4) <= \va_o\(4);
    va_o(3) <= \va_o\(3);
    va_o(2) <= \va_o\(2);
    va_o(1) <= \va_o\(1);
    va_o(0) <= \va_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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iiZnOeR02M0luF0CkuFk1akeJuVtAono2qphNmofQ+k=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=39065)
`protect data_block
[encoded data, 38464 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity adc_interface_0 is

    port( apb3_if_0_adc_control_reg_val_o     : in    std_logic_vector(5 downto 0);
          adc_interface_0_result_ch0_o        : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch1_o        : out   std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch2_o : out   std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch3_o : out   std_logic_vector(11 downto 0);
          apb3_if_0_adc_channel_ch2_o         : in    std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch0_o         : in    std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch1_o         : in    std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch3_o         : in    std_logic_vector(15 downto 0);
          MC_System_0_FIC_0_LOCK              : in    std_logic;
          MC_System_0_FIC_0_CLK               : in    std_logic;
          SEQ_CONTROLLER_1_adc_start_o        : in    std_logic;
          A0_ADC_SDI_I_c                      : in    std_logic;
          A0_ADC_SDO_O_c                      : out   std_logic;
          A0_ADC_CS_O_c                       : out   std_logic;
          A0_ADC_SCK_O_c                      : out   std_logic;
          adc_interface_0_results_rdy_o       : out   std_logic
        );

end adc_interface_0;

architecture DEF_ARCH of adc_interface_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \A0_ADC_CS_O_c\, \A0_ADC_SCK_O_c\ : std_logic;
    signal s_r_sck_count : std_logic_vector(4 downto 0);
    signal s_channel_cnt : std_logic_vector(2 downto 0);
    signal s_channel_cnt_5 : std_logic_vector(2 downto 0);
    signal s_r_adc_chnls_4_samp : std_logic_vector(2 downto 0);
    signal s_r_sck_sel : std_logic_vector(2 downto 0);
    signal s_r_adc_data : std_logic_vector(15 downto 0);
    signal s_r_adc_data_4 : std_logic_vector(12 downto 0);
    signal s_sdo : std_logic_vector(15 downto 0);
    signal s_sdo_14 : std_logic_vector(15 downto 0);
    signal present_state : std_logic_vector(4 downto 0);
    signal next_state : std_logic_vector(4 to 4);
    signal present_state_ns : std_logic_vector(3 downto 1);
    signal next_state_i_0 : std_logic_vector(4 to 4);
    signal s_r_sck_max_count : std_logic_vector(3 to 3);
    signal s_r_clock_count : std_logic_vector(7 downto 0);
    signal s_r_clock_count_s : std_logic_vector(7 downto 0);
    signal s_r_clock_count_cry : std_logic_vector(6 downto 0);
    signal s_r_clock_count_cry_Y_0 : 
        std_logic_vector(6 downto 0);
    signal s_r_clock_count_s_FCO_0 : std_logic_vector(7 to 7);
    signal s_r_clock_count_s_Y_0 : std_logic_vector(7 to 7);
    signal s_sdo_14_bm : std_logic_vector(15 downto 0);
    signal s_sdo_14_am : std_logic_vector(15 downto 0);
    signal present_state_ns_a3_1 : std_logic_vector(1 to 1);
    signal s_sdo_14_m0 : std_logic_vector(15 downto 1);
    signal \VCC\, N_2129_i_0, s_r_sck_counte, \GND\, N_2128_i_0, 
        N_2127_i_0, N_36, N_2130_i_0, s_r_sck_count_0_sqmuxa_Z, 
        N_2133_i_0, N_2132_i_0, N_2131_i_0, result_ch1_o_1_sqmuxa, 
        result_ch0_o_0_sqmuxa, result_ch2_o_1_sqmuxa, 
        result_ch3_o_1_sqmuxa, s_sdo_1_sqmuxa_3_i_0, 
        s_start_sig_ext_Z, un13_s_r_adc_results_ready, 
        s_adc_sdi_Z, N_154_i_0, N_173_i_0, s_r_sck_enable_Z, 
        adc_sdo_dly_Z, s_slave_select_2, s_r_sck_Z, s_r_sck_10, 
        s_r_adc_results_ready_1_sqmuxa_1, 
        s_r_clock_count_s_80_FCO, s_r_clock_count_s_80_S, 
        s_r_clock_count_s_80_Y, s_channel_cnt_0_sqmuxa_Z, 
        un13_s_r_sck, s_r_sck_10_7_am_1_1, s_r_sck_10_7_am_0, 
        s_r_sck_10_7_bm_1_1, s_r_sck_10_7_bm_0, s_sdo_14_sm2, 
        s_sdo_0_sqmuxa_1_1_Z, un1_s_r_sck, 
        result_ch3_o_1_sqmuxa_0_a2_3_Z, 
        result_ch3_o_1_sqmuxa_0_a2_2_Z, 
        un10_s_start_sig_ext_0_a3_1, N_2135, N_188, 
        un1_s_sdo_2_sqmuxa_tz_Z, s_sdo_14_m0s2, s_sdo_3_sqmuxa_Z, 
        N_42, CO1, un1_s_sdo_1_sqmuxa_1_Z, un22_s_r_sck, 
        s_r_adc_results_ready_0_sqmuxa_1, CO0, N_120, N_119, 
        N_118, N_117, N_116 : std_logic;

begin 

    A0_ADC_CS_O_c <= \A0_ADC_CS_O_c\;
    A0_ADC_SCK_O_c <= \A0_ADC_SCK_O_c\;

    s_r_sck : SLE
      port map(D => s_r_sck_10, CLK => MC_System_0_FIC_0_CLK, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => s_r_sck_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[7]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(7), B => s_sdo_14_am(7), C => 
        s_sdo_14_sm2, Y => s_sdo_14(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[14]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(14), B => 
        apb3_if_0_adc_channel_ch3_o(14), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(14));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[14]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(14), B => 
        s_sdo(13), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(14));
    
    s_r_sck_enable : SLE
      port map(D => next_state_i_0(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_enable_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[8]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(8), B => s_sdo_14_am(8), C => 
        s_sdo_14_sm2, Y => s_sdo_14(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[12]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(12), B => 
        apb3_if_0_adc_channel_ch3_o(12), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(12));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[1]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(0), Y => 
        s_r_adc_data_4(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[0]\ : CFG4
      generic map(INIT => x"B830")

      port map(A => \A0_ADC_CS_O_c\, B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(0), D => 
        apb3_if_0_adc_channel_ch0_o(0), Y => s_sdo_14_bm(0));
    
    \s_r_adc_data[13]\ : SLE
      port map(D => N_2133_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => s_r_sck_count_0_sqmuxa_Z, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_data(13));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[15]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(15), B => s_sdo_14_am(15), C => 
        s_sdo_14_sm2, Y => s_sdo_14(15));
    
    s_r_clock_count_s_80 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \VCC\, B => s_r_sck_enable_Z, C => \GND\, D
         => \GND\, FCI => \VCC\, S => s_r_clock_count_s_80_S, Y
         => s_r_clock_count_s_80_Y, FCO => 
        s_r_clock_count_s_80_FCO);
    
    \s_r_adc_data[4]\ : SLE
      port map(D => s_r_adc_data_4(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(4));
    
    s_slave_select : SLE
      port map(D => s_slave_select_2, CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => \A0_ADC_CS_O_c\);
    
    \s_r_adc_chnls_4_samp[0]\ : SLE
      port map(D => apb3_if_0_adc_control_reg_val_o(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(0));
    
    \s_r_clock_count[4]\ : SLE
      port map(D => s_r_clock_count_s(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(4));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[1]\ : CFG4
      generic map(INIT => x"1444")

      port map(A => present_state(4), B => s_channel_cnt(1), C
         => s_channel_cnt_0_sqmuxa_Z, D => s_channel_cnt(0), Y
         => s_channel_cnt_5(1));
    
    \s_r_clock_count_cry[1]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(1), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(0), S => s_r_clock_count_s(1), Y => 
        s_r_clock_count_cry_Y_0(1), FCO => s_r_clock_count_cry(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[10]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(10), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(10), Y => s_sdo_14_bm(10));
    
    \SCK_GEN_PROC.s_r_sck_10_7_bm_1_1\ : CFG4
      generic map(INIT => x"3437")

      port map(A => s_r_clock_count(5), B => s_r_sck_sel(2), C
         => s_r_sck_sel(1), D => s_r_clock_count(1), Y => 
        s_r_sck_10_7_bm_1_1);
    
    \s_sdo[2]\ : SLE
      port map(D => s_sdo_14(2), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(2));
    
    s_sdo_1_sqmuxa_3_i : CFG2
      generic map(INIT => x"E")

      port map(A => un1_s_r_sck, B => \A0_ADC_CS_O_c\, Y => 
        s_sdo_1_sqmuxa_3_i_0);
    
    \s_r_clock_count_cry[4]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(4), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(3), S => s_r_clock_count_s(4), Y => 
        s_r_clock_count_cry_Y_0(4), FCO => s_r_clock_count_cry(4));
    
    s_r_sck_count_n3_i_o3 : CFG3
      generic map(INIT => x"7F")

      port map(A => s_r_sck_count(2), B => s_r_sck_count(1), C
         => s_r_sck_count(0), Y => N_2135);
    
    \result_ch0_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(4));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[12]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(11), Y => 
        s_r_adc_data_4(12));
    
    \s_r_clock_count_cry[0]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(0), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_s_80_FCO, S => s_r_clock_count_s(0), Y
         => s_r_clock_count_cry_Y_0(0), FCO => 
        s_r_clock_count_cry(0));
    
    \result_ch1_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[9]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(9), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(9), Y => s_sdo_14_bm(9));
    
    \SS_GEN_PROC.s_slave_select_2\ : CFG4
      generic map(INIT => x"5755")

      port map(A => s_start_sig_ext_Z, B => s_r_sck_count(1), C
         => s_r_sck_count(0), D => un10_s_start_sig_ext_0_a3_1, Y
         => s_slave_select_2);
    
    \s_sdo[5]\ : SLE
      port map(D => s_sdo_14(5), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[5]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(5), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(5), Y => s_sdo_14_bm(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[7]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(7), B => 
        apb3_if_0_adc_channel_ch3_o(7), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(7));
    
    \result_ch3_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(0));
    
    \s_r_sck_count[0]\ : SLE
      port map(D => N_36, CLK => MC_System_0_FIC_0_CLK, EN => 
        s_r_sck_counte, ALn => MC_System_0_FIC_0_LOCK, ADn => 
        \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(0));
    
    \s_sdo[0]\ : SLE
      port map(D => s_sdo_14(0), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(0));
    
    \s_r_adc_data_RNO[13]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(12), Y => 
        N_2133_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[5]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(5), B => s_sdo(4), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(5));
    
    s_start_sig_ext : SLE
      port map(D => SEQ_CONTROLLER_1_adc_start_o, CLK => 
        MC_System_0_FIC_0_CLK, EN => un13_s_r_adc_results_ready, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_start_sig_ext_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[15]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(15), B => 
        s_sdo(14), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(15));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[3]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(2), Y => 
        s_r_adc_data_4(3));
    
    \result_ch2_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[2]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(2), B => s_sdo_14_am(2), C => 
        s_sdo_14_sm2, Y => s_sdo_14(2));
    
    \s_r_adc_data[6]\ : SLE
      port map(D => s_r_adc_data_4(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(6));
    
    \result_ch1_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[6]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(6), B => s_sdo_14_am(6), C => 
        s_sdo_14_sm2, Y => s_sdo_14(6));
    
    s_adc_sdi : SLE
      port map(D => A0_ADC_SDI_I_c, CLK => MC_System_0_FIC_0_CLK, 
        EN => N_154_i_0, ALn => MC_System_0_FIC_0_LOCK, ADn => 
        \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_adc_sdi_Z);
    
    \result_ch1_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(4));
    
    \START_SIG_PROC.un13_s_r_adc_results_ready_0\ : CFG2
      generic map(INIT => x"E")

      port map(A => s_r_adc_results_ready_1_sqmuxa_1, B => 
        SEQ_CONTROLLER_1_adc_start_o, Y => 
        un13_s_r_adc_results_ready);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[9]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(9), B => s_sdo_14_am(9), C => 
        s_sdo_14_sm2, Y => s_sdo_14(9));
    
    s_r_adc_results_ready_0_sqmuxa_1_0_a3 : CFG3
      generic map(INIT => x"80")

      port map(A => un22_s_r_sck, B => present_state(0), C => 
        un1_s_r_sck, Y => s_r_adc_results_ready_0_sqmuxa_1);
    
    s_adc_sdi_RNO : CFG2
      generic map(INIT => x"8")

      port map(A => un1_s_r_sck, B => present_state(1), Y => 
        N_154_i_0);
    
    \s_sdo[1]\ : SLE
      port map(D => s_sdo_14(1), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(1));
    
    \present_state[2]\ : SLE
      port map(D => present_state_ns(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => present_state(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[4]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(4), B => 
        apb3_if_0_adc_channel_ch3_o(4), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(4));
    
    result_ch3_o_1_sqmuxa_0_a3 : CFG3
      generic map(INIT => x"80")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => N_42, Y => result_ch3_o_1_sqmuxa);
    
    \s_r_clock_count[5]\ : SLE
      port map(D => s_r_clock_count_s(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(5));
    
    \result_ch3_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(3));
    
    \s_r_clock_count[2]\ : SLE
      port map(D => s_r_clock_count_s(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[6]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(6), B => s_sdo(5), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[15]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(15), B => 
        apb3_if_0_adc_channel_ch3_o(15), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(15));
    
    \s_sdo[15]\ : SLE
      port map(D => s_sdo_14(15), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(15));
    
    \s_sdo[12]\ : SLE
      port map(D => s_sdo_14(12), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(12));
    
    \s_r_clock_count[3]\ : SLE
      port map(D => s_r_clock_count_s(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(3));
    
    \s_r_adc_data[14]\ : SLE
      port map(D => N_2132_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => s_r_sck_count_0_sqmuxa_Z, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_data(14));
    
    results_rdy_o : SLE
      port map(D => s_r_adc_results_ready_1_sqmuxa_1, CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_results_rdy_o);
    
    \result_ch2_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(2));
    
    \s_r_sck_count[4]\ : SLE
      port map(D => N_2127_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => s_r_sck_counte, ALn => MC_System_0_FIC_0_LOCK, ADn
         => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(4));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[12]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(12), B => s_sdo_14_am(12), C => 
        s_sdo_14_sm2, Y => s_sdo_14(12));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[10]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(10), B => 
        s_sdo(9), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(10));
    
    \result_ch1_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(10));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[13]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(13), B => 
        s_sdo(12), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(13));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[8]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(8), B => 
        apb3_if_0_adc_channel_ch3_o(8), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(8));
    
    \s_r_adc_data[7]\ : SLE
      port map(D => s_r_adc_data_4(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(7));
    
    \result_ch0_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(2));
    
    result_ch2_o_1_sqmuxa_0_a3 : CFG3
      generic map(INIT => x"20")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => N_42, Y => result_ch2_o_1_sqmuxa);
    
    \s_channel_cnt[0]\ : SLE
      port map(D => s_channel_cnt_5(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(0));
    
    \result_ch1_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(5));
    
    \s_sdo[11]\ : SLE
      port map(D => s_sdo_14(11), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(11));
    
    result_ch3_o_1_sqmuxa_0_a2_2 : CFG4
      generic map(INIT => x"0401")

      port map(A => s_r_adc_data(15), B => s_r_sck_max_count(3), 
        C => s_r_adc_data(14), D => s_r_sck_count(4), Y => 
        result_ch3_o_1_sqmuxa_0_a2_2_Z);
    
    \s_r_sck_sel[0]\ : SLE
      port map(D => apb3_if_0_adc_control_reg_val_o(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(0));
    
    s_r_sck_count_n0_i_a3 : CFG2
      generic map(INIT => x"2")

      port map(A => present_state(1), B => s_r_sck_count(0), Y
         => N_36);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0s2\ : CFG4
      generic map(INIT => x"555D")

      port map(A => \A0_ADC_CS_O_c\, B => s_sdo_0_sqmuxa_1_1_Z, C
         => s_r_adc_chnls_4_samp(2), D => s_channel_cnt(0), Y => 
        s_sdo_14_m0s2);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[12]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(12), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(12), Y => s_sdo_14_bm(12));
    
    \s_r_sck_count_RNO[4]\ : CFG4
      generic map(INIT => x"A060")

      port map(A => s_r_sck_count(4), B => s_r_sck_count(3), C
         => present_state(1), D => N_2135, Y => N_2127_i_0);
    
    \s_r_adc_data[15]\ : SLE
      port map(D => N_2131_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => s_r_sck_count_0_sqmuxa_Z, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_data(15));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[13]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(13), B => 
        apb3_if_0_adc_channel_ch3_o(13), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(13));
    
    \present_state_ns_i_m4[2]\ : CFG3
      generic map(INIT => x"A4")

      port map(A => present_state(3), B => present_state(2), C
         => un1_s_r_sck, Y => present_state_ns(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[7]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(7), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(7), Y => s_sdo_14_bm(7));
    
    result_ch3_o_1_sqmuxa_0_a2_3 : CFG3
      generic map(INIT => x"18")

      port map(A => s_r_sck_max_count(3), B => s_r_sck_count(1), 
        C => s_r_sck_count(0), Y => 
        result_ch3_o_1_sqmuxa_0_a2_3_Z);
    
    \next_state_0[4]\ : CFG3
      generic map(INIT => x"DC")

      port map(A => SEQ_CONTROLLER_1_adc_start_o, B => 
        s_r_adc_results_ready_1_sqmuxa_1, C => present_state(4), 
        Y => next_state(4));
    
    \s_r_adc_data[5]\ : SLE
      port map(D => s_r_adc_data_4(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(5));
    
    \s_r_adc_data[11]\ : SLE
      port map(D => s_r_adc_data_4(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(11));
    
    \s_r_adc_chnls_4_samp[1]\ : SLE
      port map(D => apb3_if_0_adc_control_reg_val_o(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(1));
    
    \s_sdo[9]\ : SLE
      port map(D => s_sdo_14(9), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(9));
    
    \result_ch0_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[11]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(11), B => 
        s_sdo(10), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(11));
    
    \s_r_sck_max_count[3]\ : SLE
      port map(D => \VCC\, CLK => MC_System_0_FIC_0_CLK, EN => 
        \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn
         => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_max_count(3));
    
    GND_Z : GND
      port map(Y => \GND\);
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[4]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(3), Y => 
        s_r_adc_data_4(4));
    
    \s_sdo[4]\ : SLE
      port map(D => s_sdo_14(4), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(4));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[2]\ : CFG4
      generic map(INIT => x"006A")

      port map(A => s_channel_cnt(2), B => s_channel_cnt(1), C
         => CO0, D => present_state(4), Y => s_channel_cnt_5(2));
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[2]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(2), B => 
        apb3_if_0_adc_channel_ch3_o(2), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(2));
    
    s_channel_cnt_0_sqmuxa : CFG4
      generic map(INIT => x"0800")

      port map(A => present_state(0), B => s_r_sck_Z, C => 
        \A0_ADC_SCK_O_c\, D => un22_s_r_sck, Y => 
        s_channel_cnt_0_sqmuxa_Z);
    
    \s_r_sck_sel[2]\ : SLE
      port map(D => apb3_if_0_adc_control_reg_val_o(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(2));
    
    \s_r_adc_data[10]\ : SLE
      port map(D => s_r_adc_data_4(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(10));
    
    \result_ch0_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(8));
    
    \result_ch2_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[5]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(5), B => s_sdo_14_am(5), C => 
        s_sdo_14_sm2, Y => s_sdo_14(5));
    
    \result_ch2_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(10));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[10]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(9), Y => 
        s_r_adc_data_4(10));
    
    \present_state_ns_o4_RNIN9SS[3]\ : CFG4
      generic map(INIT => x"7555")

      port map(A => present_state(1), B => s_r_sck_Z, C => 
        un13_s_r_sck, D => \A0_ADC_SCK_O_c\, Y => s_r_sck_counte);
    
    \result_ch3_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(4));
    
    \result_ch0_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(9));
    
    \result_ch3_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[6]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(6), B => 
        apb3_if_0_adc_channel_ch3_o(6), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(6));
    
    sdo_o : SLE
      port map(D => adc_sdo_dly_Z, CLK => MC_System_0_FIC_0_CLK, 
        EN => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        A0_ADC_SDO_O_c);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[4]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(4), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(4), Y => s_sdo_14_bm(4));
    
    \s_r_clock_count_s[7]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(7), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(6), S => s_r_clock_count_s(7), Y => 
        s_r_clock_count_s_Y_0(7), FCO => 
        s_r_clock_count_s_FCO_0(7));
    
    \result_ch1_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(11));
    
    \result_ch0_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(5));
    
    \result_ch0_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[11]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(11), B => 
        apb3_if_0_adc_channel_ch3_o(11), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(11));
    
    \present_state_ns[3]\ : CFG4
      generic map(INIT => x"EACC")

      port map(A => present_state(2), B => present_state(1), C
         => un13_s_r_sck, D => un1_s_r_sck, Y => 
        present_state_ns(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[13]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(13), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(13), Y => s_sdo_14_bm(13));
    
    \s_r_adc_data[8]\ : SLE
      port map(D => s_r_adc_data_4(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(8));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[0]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_adc_sdi_Z, Y => 
        s_r_adc_data_4(0));
    
    \s_r_clock_count[6]\ : SLE
      port map(D => s_r_clock_count_s(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(6));
    
    result_ch3_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"1000")

      port map(A => s_r_sck_count(3), B => s_r_sck_count(2), C
         => result_ch3_o_1_sqmuxa_0_a2_3_Z, D => 
        result_ch3_o_1_sqmuxa_0_a2_2_Z, Y => N_42);
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[2]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(1), Y => 
        s_r_adc_data_4(2));
    
    \present_state[0]\ : SLE
      port map(D => N_173_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        present_state(0));
    
    result_ch1_o_1_sqmuxa_0_a3 : CFG3
      generic map(INIT => x"40")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => N_42, Y => result_ch1_o_1_sqmuxa);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[7]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(7), B => s_sdo(6), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(7));
    
    \result_ch3_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(1));
    
    \result_ch2_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(6));
    
    \s_r_sck_count[3]\ : SLE
      port map(D => N_2128_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => s_r_sck_counte, ALn => MC_System_0_FIC_0_LOCK, ADn
         => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(3));
    
    \s_r_sck_count[1]\ : SLE
      port map(D => N_2130_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => s_r_sck_counte, ALn => MC_System_0_FIC_0_LOCK, ADn
         => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(1));
    
    \present_state[3]\ : SLE
      port map(D => present_state_ns(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => present_state(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[14]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(14), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(14), Y => s_sdo_14_bm(14));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[7]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(6), Y => 
        s_r_adc_data_4(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[8]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(8), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(8), Y => s_sdo_14_bm(8));
    
    \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO1\ : CFG4
      generic map(INIT => x"1075")

      port map(A => s_r_adc_chnls_4_samp(1), B => 
        s_channel_cnt(0), C => s_r_adc_chnls_4_samp(0), D => 
        s_channel_cnt(1), Y => CO1);
    
    \s_r_clock_count_cry[6]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(6), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(5), S => s_r_clock_count_s(6), Y => 
        s_r_clock_count_cry_Y_0(6), FCO => s_r_clock_count_cry(6));
    
    \s_channel_cnt[2]\ : SLE
      port map(D => s_channel_cnt_5(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(2));
    
    \s_sdo[6]\ : SLE
      port map(D => s_sdo_14(6), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(6));
    
    \result_ch0_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(3));
    
    s_sdo_0_sqmuxa_1_1 : CFG2
      generic map(INIT => x"1")

      port map(A => s_channel_cnt(2), B => s_channel_cnt(1), Y
         => s_sdo_0_sqmuxa_1_1_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[11]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(11), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(11), Y => s_sdo_14_bm(11));
    
    \result_ch0_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(7));
    
    \s_r_adc_data_RNO[15]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(14), Y => 
        N_2131_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[1]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(1), B => s_sdo_14_am(1), C => 
        s_sdo_14_sm2, Y => s_sdo_14(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[1]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(1), B => 
        apb3_if_0_adc_channel_ch3_o(1), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(1));
    
    \result_ch0_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[3]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(3), B => 
        apb3_if_0_adc_channel_ch3_o(3), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(3));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[9]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(8), Y => 
        s_r_adc_data_4(9));
    
    \result_ch3_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(10));
    
    result_ch0_o_0_sqmuxa_0_a3 : CFG3
      generic map(INIT => x"10")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => N_42, Y => result_ch0_o_0_sqmuxa);
    
    \present_state[1]\ : SLE
      port map(D => present_state_ns(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => present_state(1));
    
    \next_state_0_a3_0[4]\ : CFG3
      generic map(INIT => x"40")

      port map(A => un22_s_r_sck, B => present_state(0), C => 
        un1_s_r_sck, Y => s_r_adc_results_ready_1_sqmuxa_1);
    
    \result_ch3_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(5));
    
    \present_state_ns[1]\ : CFG4
      generic map(INIT => x"FFF4")

      port map(A => un1_s_r_sck, B => present_state(3), C => 
        s_r_adc_results_ready_0_sqmuxa_1, D => N_188, Y => 
        present_state_ns(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[2]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(2), B => s_sdo(1), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[0]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(0), B => s_sdo_14_am(0), C => 
        s_sdo_14_sm2, Y => s_sdo_14(0));
    
    s_sdo_3_sqmuxa : CFG4
      generic map(INIT => x"0400")

      port map(A => s_r_adc_chnls_4_samp(2), B => 
        s_r_adc_chnls_4_samp(0), C => s_channel_cnt(2), D => 
        s_r_adc_chnls_4_samp(1), Y => s_sdo_3_sqmuxa_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[10]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(10), B => s_sdo_14_am(10), C => 
        s_sdo_14_sm2, Y => s_sdo_14(10));
    
    \result_ch2_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(4));
    
    \SCK_GEN_PROC.s_r_sck_10_7_ns\ : CFG3
      generic map(INIT => x"E2")

      port map(A => s_r_sck_10_7_am_0, B => s_r_sck_sel(0), C => 
        s_r_sck_10_7_bm_0, Y => s_r_sck_10);
    
    \result_ch2_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(11));
    
    \s_r_sck_count_RNO[3]\ : CFG3
      generic map(INIT => x"84")

      port map(A => s_r_sck_count(3), B => present_state(1), C
         => N_2135, Y => N_2128_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[4]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(4), B => s_sdo(3), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(4));
    
    \s_r_clock_count_cry[5]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(5), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(4), S => s_r_clock_count_s(5), Y => 
        s_r_clock_count_cry_Y_0(5), FCO => s_r_clock_count_cry(5));
    
    \s_r_sck_count_RNO[2]\ : CFG4
      generic map(INIT => x"6A00")

      port map(A => s_r_sck_count(2), B => s_r_sck_count(1), C
         => s_r_sck_count(0), D => present_state(1), Y => 
        N_2129_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[12]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(12), B => 
        s_sdo(11), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(12));
    
    \s_sdo[13]\ : SLE
      port map(D => s_sdo_14(13), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(13));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[2]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(2), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(2), Y => s_sdo_14_bm(2));
    
    \result_ch2_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(0));
    
    \present_state_ns_a3[1]\ : CFG4
      generic map(INIT => x"0008")

      port map(A => SEQ_CONTROLLER_1_adc_start_o, B => 
        present_state_ns_a3_1(1), C => present_state(3), D => 
        present_state(2), Y => N_188);
    
    \s_sdo[7]\ : SLE
      port map(D => s_sdo_14(7), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[14]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(14), B => s_sdo_14_am(14), C => 
        s_sdo_14_sm2, Y => s_sdo_14(14));
    
    \result_ch3_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(2));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[11]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(10), Y => 
        s_r_adc_data_4(11));
    
    \result_ch3_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(7));
    
    \result_ch1_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(1));
    
    \present_state_ns_a3_1[1]\ : CFG2
      generic map(INIT => x"1")

      port map(A => present_state(1), B => present_state(0), Y
         => present_state_ns_a3_1(1));
    
    \SCK_GEN_PROC.s_r_sck_10_7_am_1_1\ : CFG4
      generic map(INIT => x"3437")

      port map(A => s_r_clock_count(4), B => s_r_sck_sel(2), C
         => s_r_sck_sel(1), D => s_r_clock_count(0), Y => 
        s_r_sck_10_7_am_1_1);
    
    \result_ch1_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(9));
    
    \SS_GEN_PROC.un10_s_start_sig_ext_0_a3_1\ : CFG3
      generic map(INIT => x"01")

      port map(A => s_r_sck_count(4), B => s_r_sck_count(3), C
         => s_r_sck_count(2), Y => un10_s_start_sig_ext_0_a3_1);
    
    \present_state_RNO[0]\ : CFG4
      generic map(INIT => x"04AC")

      port map(A => present_state(1), B => present_state(0), C
         => un1_s_r_sck, D => un13_s_r_sck, Y => N_173_i_0);
    
    \result_ch3_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(9));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[6]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(6), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(6), Y => s_sdo_14_bm(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[0]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(0), B => 
        apb3_if_0_adc_channel_ch3_o(0), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(0));
    
    \present_state[4]\ : SLE
      port map(D => next_state(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \GND\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        present_state(4));
    
    \result_ch0_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(10));
    
    \s_r_adc_data[2]\ : SLE
      port map(D => s_r_adc_data_4(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(2));
    
    un1_s_sdo_2_sqmuxa_tz : CFG2
      generic map(INIT => x"2")

      port map(A => s_r_adc_chnls_4_samp(1), B => 
        s_r_adc_chnls_4_samp(2), Y => un1_s_sdo_2_sqmuxa_tz_Z);
    
    \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO2\ : CFG4
      generic map(INIT => x"6F06")

      port map(A => s_r_adc_chnls_4_samp(2), B => 
        s_r_adc_chnls_4_samp(1), C => s_channel_cnt(2), D => CO1, 
        Y => un22_s_r_sck);
    
    \s_r_clock_count_cry[2]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(2), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(1), S => s_r_clock_count_s(2), Y => 
        s_r_clock_count_cry_Y_0(2), FCO => s_r_clock_count_cry(2));
    
    \s_r_adc_data[12]\ : SLE
      port map(D => s_r_adc_data_4(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(12));
    
    \s_r_adc_data[1]\ : SLE
      port map(D => s_r_adc_data_4(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(1));
    
    \SCK_GEN_PROC.s_r_sck_10_7_am\ : CFG4
      generic map(INIT => x"B931")

      port map(A => s_r_sck_sel(1), B => s_r_sck_10_7_am_1_1, C
         => s_r_clock_count(6), D => s_r_clock_count(2), Y => 
        s_r_sck_10_7_am_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[9]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(9), B => s_sdo(8), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(9));
    
    \s_sdo[10]\ : SLE
      port map(D => s_sdo_14(10), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(10));
    
    un1_s_sdo_1_sqmuxa_1 : CFG4
      generic map(INIT => x"3200")

      port map(A => s_r_adc_chnls_4_samp(0), B => 
        s_r_adc_chnls_4_samp(2), C => s_r_adc_chnls_4_samp(1), D
         => s_sdo_0_sqmuxa_1_1_Z, Y => un1_s_sdo_1_sqmuxa_1_Z);
    
    \result_ch2_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(8));
    
    \ADC_FSM_NS_PROC.un1_s_r_sck\ : CFG2
      generic map(INIT => x"2")

      port map(A => \A0_ADC_SCK_O_c\, B => s_r_sck_Z, Y => 
        un1_s_r_sck);
    
    \s_r_clock_count_cry[3]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(3), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(2), S => s_r_clock_count_s(3), Y => 
        s_r_clock_count_cry_Y_0(3), FCO => s_r_clock_count_cry(3));
    
    \result_ch3_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(11));
    
    \DATA_TRANSMIT_PROC.s_sdo_14s2\ : CFG4
      generic map(INIT => x"F1F0")

      port map(A => s_channel_cnt(0), B => s_channel_cnt(2), C
         => s_sdo_14_m0s2, D => un1_s_sdo_2_sqmuxa_tz_Z, Y => 
        s_sdo_14_sm2);
    
    \s_r_sck_count_RNO[1]\ : CFG3
      generic map(INIT => x"60")

      port map(A => s_r_sck_count(1), B => s_r_sck_count(0), C
         => present_state(1), Y => N_2130_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[3]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(3), B => s_sdo(2), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(3));
    
    \s_r_adc_chnls_4_samp[2]\ : SLE
      port map(D => apb3_if_0_adc_control_reg_val_o(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(2));
    
    \s_sdo[8]\ : SLE
      port map(D => s_sdo_14(8), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(8));
    
    \result_ch1_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(3));
    
    \next_state_0_i[4]\ : CFG3
      generic map(INIT => x"23")

      port map(A => SEQ_CONTROLLER_1_adc_start_o, B => 
        s_r_adc_results_ready_1_sqmuxa_1, C => present_state(4), 
        Y => next_state_i_0(4));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[0]\ : CFG3
      generic map(INIT => x"14")

      port map(A => present_state(4), B => s_channel_cnt(0), C
         => s_channel_cnt_0_sqmuxa_Z, Y => s_channel_cnt_5(0));
    
    \result_ch2_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(9));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[1]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(1), B => s_sdo(0), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(1));
    
    \result_ch1_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(7));
    
    \present_state_ns_o4[3]\ : CFG4
      generic map(INIT => x"5557")

      port map(A => s_r_sck_count(4), B => s_r_sck_count(3), C
         => s_r_sck_count(2), D => s_r_sck_count(1), Y => 
        un13_s_r_sck);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[9]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(9), B => 
        apb3_if_0_adc_channel_ch3_o(9), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(9));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[1]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(1), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(1), Y => s_sdo_14_bm(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[5]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(5), B => 
        apb3_if_0_adc_channel_ch3_o(5), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(5));
    
    \s_r_adc_data[3]\ : SLE
      port map(D => s_r_adc_data_4(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[3]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(3), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(3), Y => s_sdo_14_bm(3));
    
    \SCK_GEN_PROC.s_r_sck_10_7_bm\ : CFG4
      generic map(INIT => x"B931")

      port map(A => s_r_sck_sel(1), B => s_r_sck_10_7_bm_1_1, C
         => s_r_clock_count(7), D => s_r_clock_count(3), Y => 
        s_r_sck_10_7_bm_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[3]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(3), B => s_sdo_14_am(3), C => 
        s_sdo_14_sm2, Y => s_sdo_14(3));
    
    \s_sdo[14]\ : SLE
      port map(D => s_sdo_14(14), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(14));
    
    \result_ch2_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(7));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[6]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(5), Y => 
        s_r_adc_data_4(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[11]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(11), B => s_sdo_14_am(11), C => 
        s_sdo_14_sm2, Y => s_sdo_14(11));
    
    \result_ch1_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(0));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[5]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(4), Y => 
        s_r_adc_data_4(5));
    
    \s_r_sck_sel[1]\ : SLE
      port map(D => apb3_if_0_adc_control_reg_val_o(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(1));
    
    \s_r_adc_data[0]\ : SLE
      port map(D => s_r_adc_data_4(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(0));
    
    \result_ch3_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[10]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_if_0_adc_channel_ch1_o(10), B => 
        apb3_if_0_adc_channel_ch3_o(10), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(10));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5_RNO[2]\ : CFG2
      generic map(INIT => x"8")

      port map(A => s_channel_cnt_0_sqmuxa_Z, B => 
        s_channel_cnt(0), Y => CO0);
    
    s_r_sck_count_0_sqmuxa : CFG4
      generic map(INIT => x"4000")

      port map(A => s_r_sck_Z, B => present_state(1), C => 
        \A0_ADC_SCK_O_c\, D => un13_s_r_sck, Y => 
        s_r_sck_count_0_sqmuxa_Z);
    
    \s_r_clock_count[1]\ : SLE
      port map(D => s_r_clock_count_s(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(1));
    
    \s_r_clock_count[0]\ : SLE
      port map(D => s_r_clock_count_s(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[15]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(15), B => s_sdo_14_m0s2, C => 
        apb3_if_0_adc_channel_ch2_o(15), Y => s_sdo_14_bm(15));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[13]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(13), B => s_sdo_14_am(13), C => 
        s_sdo_14_sm2, Y => s_sdo_14(13));
    
    adc_sdo_dly : SLE
      port map(D => s_sdo(15), CLK => MC_System_0_FIC_0_CLK, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        adc_sdo_dly_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[4]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(4), B => s_sdo_14_am(4), C => 
        s_sdo_14_sm2, Y => s_sdo_14(4));
    
    \s_sdo[3]\ : SLE
      port map(D => s_sdo_14(3), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(3));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[8]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(7), Y => 
        s_r_adc_data_4(8));
    
    \s_r_adc_data_RNO[14]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(13), Y => 
        N_2132_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[8]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_0_adc_channel_ch0_o(8), B => s_sdo(7), 
        C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(8));
    
    \s_r_sck_count[2]\ : SLE
      port map(D => N_2129_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => s_r_sck_counte, ALn => MC_System_0_FIC_0_LOCK, ADn
         => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(2));
    
    \result_ch2_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch2_o(1));
    
    \s_r_adc_data[9]\ : SLE
      port map(D => s_r_adc_data_4(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(9));
    
    \result_ch1_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(2));
    
    \s_channel_cnt[1]\ : SLE
      port map(D => s_channel_cnt_5(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(1));
    
    \result_ch0_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(11));
    
    \s_r_clock_count[7]\ : SLE
      port map(D => s_r_clock_count_s(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(7));
    
    sck_o : SLE
      port map(D => s_r_sck_Z, CLK => MC_System_0_FIC_0_CLK, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        \A0_ADC_SCK_O_c\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_pwm_scl_0 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_pwm_scl_0;

architecture DEF_ARCH of mas_pwm_scl_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(15) <= \product_o\(0);
    product_o(14) <= \product_o\(0);
    product_o(13) <= \product_o\(0);
    product_o(12) <= \product_o\(0);
    product_o(11) <= \product_o\(0);
    product_o(10) <= \product_o\(0);
    product_o(9) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
BQBqjEq7/B45xXsyaAJfu1Q/7qeLQJ2omOEnayY45Bp2jMKBbASvFwaoKfgRbnJk
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P4/Hvl/EcGdTGUeW2Oi8nxTkhxoUt4SNi9/myQFi4QI=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12375)
`protect data_block
[encoded data, 12160 characters]
1+JB98jLDvhyhnftyarEyQ==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity PWM_SCALING_0 is

    port( reset_i      : in    std_logic;
          sys_clk_i    : in    std_logic;
          start_i      : in    std_logic;
          va_i         : in    std_logic_vector(17 downto 0);
          vb_i         : in    std_logic_vector(17 downto 0);
          vc_i         : in    std_logic_vector(17 downto 0);
          pwm_period_i : in    std_logic_vector(17 downto 0);
          pwm_gain_i   : in    std_logic_vector(17 downto 0);
          Va_o         : out   std_logic_vector(17 downto 0);
          Vb_o         : out   std_logic_vector(17 downto 0);
          Vc_o         : out   std_logic_vector(17 downto 0);
          done_o       : out   std_logic
        );

end PWM_SCALING_0;

architecture DEF_ARCH of PWM_SCALING_0 is 

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component mas_pwm_scl_0
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal s_mult_in0 : std_logic_vector(17 downto 0);
    signal s_product : std_logic_vector(33 downto 16);
    signal s_state : std_logic_vector(4 downto 0);
    signal s_state_ns : std_logic_vector(1 to 1);
    signal \MUL_INP_GEN_PROC.s_mult_in0_4\ : 
        std_logic_vector(17 downto 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_252, MSC_net_253, MSC_net_254, MSC_net_255, 
        MSC_net_256, MSC_net_257, MSC_net_258, MSC_net_259, 
        MSC_net_260, MSC_net_261, MSC_net_262, MSC_net_263, 
        MSC_net_264, MSC_net_265, MSC_net_266, MSC_net_267, 
        MSC_net_268, MSC_net_269, MSC_net_270, MSC_net_271, 
        MSC_net_272, MSC_net_273, MSC_net_274, MSC_net_275, 
        MSC_net_276, MSC_net_277, MSC_net_278, MSC_net_279, 
        MSC_net_280, MSC_net_281, MSC_net_282, MSC_net_283, 
        MSC_net_284, MSC_net_285, MSC_net_286, MSC_net_287
         : std_logic;

    for all : mas_pwm_scl_0
	Use entity work.mas_pwm_scl_0(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
LVpHbLpFdX6XStoZVSh60rNlsaqD/Pu3gqHI9j6S1iGejVUKp8Do0V/m7yrtTrhC
ZQC1/nhOOG41mm78ahHxmgJCjPpzYxsZO1WdRowjLbzC7YjC2iwtyUqHe64anV/o
XaEX8M1RBn7kRtQ7ERT+XEqvVjGI3G9K/v3oxpVx9zY=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=43835)
`protect data_block
[encoded data, 43136 characters]
aDRYB4H0JLcQmdSOIPzOOg==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_adc_scl_0 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_adc_scl_0;

architecture DEF_ARCH of mas_adc_scl_0 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal product_o_ONC : std_logic_vector(43 downto 36);
    signal MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(30) <= \product_o\(0);
    product_o(29) <= \product_o\(0);
    product_o(28) <= \product_o\(0);
    product_o(27) <= \product_o\(0);
    product_o(26) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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CFxvHPAU8Hi3Q9c30fk0ZDA/37huHHi2aVqg/t3lqgQ=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12525)
`protect data_block
[encoded data, 12288 characters]
vRAeaAygdDLgNtiEM8IBxplJO+w/Tdw8/iNi8+kRmv0=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity ADC_SCALING_0 is

    port( reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          adc_results_rdy_i    : in    std_logic;
          adc_scale_val_i      : in    std_logic_vector(17 downto 0);
          adc_result_ch0_i     : in    std_logic_vector(11 downto 0);
          adc_result_ch1_i     : in    std_logic_vector(11 downto 0);
          fault_threshold_i    : in    std_logic_vector(17 downto 0);
          done_o               : out   std_logic;
          calib_done_o         : out   std_logic;
          over_current_fault_o : out   std_logic;
          ia_adc_o             : out   std_logic_vector(17 downto 0);
          ib_adc_o             : out   std_logic_vector(17 downto 0)
        );

end ADC_SCALING_0;

architecture DEF_ARCH of ADC_SCALING_0 is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_adc_scl_0
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

    signal \ia_adc_o\ : std_logic_vector(17 downto 0);
    signal \ib_adc_o\ : std_logic_vector(17 downto 0);
    signal MSC_net_100 : std_logic;
    signal s_mult0_in : std_logic_vector(17 downto 0);
    signal s_product : std_logic_vector(25 downto 8);
    signal s_adc_ch1_offset : std_logic_vector(30 downto 0);
    signal s_adc_ch0_offset : std_logic_vector(30 downto 0);
    signal s_state : std_logic_vector(1 downto 0);
    signal s_state_ns : std_logic_vector(1 downto 0);
    signal inf_abs1 : std_logic_vector(17 downto 0);
    signal inf_abs0 : std_logic_vector(17 downto 0);
    signal s_calib_cnt : std_logic_vector(13 downto 0);
    signal s_calib_cnt_cry : std_logic_vector(12 downto 0);
    signal s_calib_cnt_s : std_logic_vector(13 downto 0);
    signal un1_s_mult0_in_0 : std_logic_vector(16 downto 6);
    signal s_calib_cnt_cry_Y : std_logic_vector(12 downto 0);
    signal s_calib_cnt_s_FCO : std_logic_vector(13 to 13);
    signal s_calib_cnt_s_Y : std_logic_vector(13 to 13);
    signal s_calib_cnt_cry_cy_S : std_logic_vector(0 to 0);
    signal s_calib_cnt_cry_cy_Y : std_logic_vector(0 to 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1\, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o2\, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Z\, 
        MSC_net_476, MSC_net_477, MSC_net_478, MSC_net_479, 
        MSC_net_480, MSC_net_481, MSC_net_482, MSC_net_483, 
        MSC_net_484, MSC_net_485, MSC_net_486, MSC_net_487, 
        MSC_net_488, MSC_net_489, MSC_net_490, MSC_net_491, 
        MSC_net_492, MSC_net_493, MSC_net_494, MSC_net_495, 
        MSC_net_496, MSC_net_497, MSC_net_498, MSC_net_499, 
        MSC_net_500, MSC_net_501, MSC_net_502, MSC_net_503, 
        MSC_net_504, MSC_net_505, MSC_net_506, MSC_net_507, 
        MSC_net_508, MSC_net_509, MSC_net_510, MSC_net_511, 
        MSC_net_512, MSC_net_513, MSC_net_514, MSC_net_515, 
        MSC_net_516, MSC_net_517, MSC_net_518, MSC_net_519, 
        MSC_net_520, MSC_net_521, MSC_net_522, MSC_net_523, 
        MSC_net_524, MSC_net_525, MSC_net_526, MSC_net_527, 
        MSC_net_528, MSC_net_529, MSC_net_530, MSC_net_531, 
        MSC_net_532, MSC_net_533, MSC_net_534, MSC_net_535, 
        MSC_net_536, MSC_net_537, MSC_net_538, MSC_net_539, 
        MSC_net_540, MSC_net_541, MSC_net_542, MSC_net_543, 
        MSC_net_544, MSC_net_545, MSC_net_546, MSC_net_547, 
        MSC_net_548, MSC_net_549, MSC_net_550, MSC_net_551, 
        MSC_net_552, MSC_net_553, MSC_net_554, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, MSC_net_591, 
        MSC_net_592, MSC_net_593, MSC_net_594, MSC_net_595, 
        MSC_net_596, MSC_net_597, MSC_net_598, MSC_net_599, 
        MSC_net_600, MSC_net_601, MSC_net_602, MSC_net_603, 
        MSC_net_604, MSC_net_605, MSC_net_606, MSC_net_607, 
        MSC_net_608, MSC_net_609, MSC_net_610, MSC_net_611, 
        MSC_net_612, MSC_net_613, MSC_net_614, MSC_net_615, 
        MSC_net_616, MSC_net_617, MSC_net_618, MSC_net_619, 
        MSC_net_620, MSC_net_621, MSC_net_622, MSC_net_623, 
        MSC_net_624, MSC_net_625, MSC_net_626, MSC_net_627, 
        MSC_net_628, MSC_net_629, MSC_net_630, MSC_net_631, 
        MSC_net_632, MSC_net_633, MSC_net_634, MSC_net_635, 
        MSC_net_636, MSC_net_637, MSC_net_638, MSC_net_639, 
        MSC_net_640, MSC_net_641, MSC_net_642, MSC_net_643, 
        MSC_net_644, MSC_net_645, MSC_net_646, MSC_net_647, 
        MSC_net_648, MSC_net_649, MSC_net_650, MSC_net_651, 
        MSC_net_652, MSC_net_653, MSC_net_654, MSC_net_655, 
        MSC_net_656, MSC_net_657, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_17_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_17_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_17_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_17_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Y\, 
        MSC_net_730, MSC_net_731, MSC_net_732, MSC_net_733, 
        MSC_net_734, MSC_net_735, MSC_net_736, MSC_net_737, 
        MSC_net_738, MSC_net_739, MSC_net_740, MSC_net_741, 
        MSC_net_742, MSC_net_743, MSC_net_744, MSC_net_745, 
        MSC_net_746, MSC_net_747, MSC_net_748, MSC_net_749, 
        MSC_net_750, MSC_net_751, MSC_net_752, MSC_net_753, 
        MSC_net_754, MSC_net_755, MSC_net_756, MSC_net_757, 
        MSC_net_758, MSC_net_759, MSC_net_760, MSC_net_761, 
        MSC_net_762, MSC_net_763, MSC_net_764, MSC_net_765, 
        MSC_net_766, MSC_net_767, MSC_net_768, MSC_net_769, 
        MSC_net_770, MSC_net_771, MSC_net_772, MSC_net_773, 
        MSC_net_774, MSC_net_775, MSC_net_776, MSC_net_777, 
        MSC_net_778, MSC_net_779, MSC_net_780, MSC_net_781, 
        MSC_net_782, MSC_net_783, MSC_net_784, MSC_net_785, 
        MSC_net_786, MSC_net_787, MSC_net_788, MSC_net_789, 
        MSC_net_790, MSC_net_791, MSC_net_792, MSC_net_793, 
        MSC_net_794, MSC_net_795, MSC_net_796, MSC_net_797, 
        MSC_net_798, MSC_net_799, MSC_net_800, MSC_net_801, 
        MSC_net_802, MSC_net_803, MSC_net_804, MSC_net_805, 
        MSC_net_806, MSC_net_807, MSC_net_808, MSC_net_809, 
        MSC_net_810, MSC_net_811, MSC_net_812, MSC_net_813, 
        MSC_net_814, MSC_net_815, MSC_net_816 : std_logic;

    for all : mas_adc_scl_0
	Use entity work.mas_adc_scl_0(DEF_ARCH);
begin 

    calib_done_o <= MSC_net_100;
    ia_adc_o(17) <= \ia_adc_o\(17);
    ia_adc_o(16) <= \ia_adc_o\(16);
    ia_adc_o(15) <= \ia_adc_o\(15);
    ia_adc_o(14) <= \ia_adc_o\(14);
    ia_adc_o(13) <= \ia_adc_o\(13);
    ia_adc_o(12) <= \ia_adc_o\(12);
    ia_adc_o(11) <= \ia_adc_o\(11);
    ia_adc_o(10) <= \ia_adc_o\(10);
    ia_adc_o(9) <= \ia_adc_o\(9);
    ia_adc_o(8) <= \ia_adc_o\(8);
    ia_adc_o(7) <= \ia_adc_o\(7);
    ia_adc_o(6) <= \ia_adc_o\(6);
    ia_adc_o(5) <= \ia_adc_o\(5);
    ia_adc_o(4) <= \ia_adc_o\(4);
    ia_adc_o(3) <= \ia_adc_o\(3);
    ia_adc_o(2) <= \ia_adc_o\(2);
    ia_adc_o(1) <= \ia_adc_o\(1);
    ia_adc_o(0) <= \ia_adc_o\(0);
    ib_adc_o(17) <= \ib_adc_o\(17);
    ib_adc_o(16) <= \ib_adc_o\(16);
    ib_adc_o(15) <= \ib_adc_o\(15);
    ib_adc_o(14) <= \ib_adc_o\(14);
    ib_adc_o(13) <= \ib_adc_o\(13);
    ib_adc_o(12) <= \ib_adc_o\(12);
    ib_adc_o(11) <= \ib_adc_o\(11);
    ib_adc_o(10) <= \ib_adc_o\(10);
    ib_adc_o(9) <= \ib_adc_o\(9);
    ib_adc_o(8) <= \ib_adc_o\(8);
    ib_adc_o(7) <= \ib_adc_o\(7);
    ib_adc_o(6) <= \ib_adc_o\(6);
    ib_adc_o(5) <= \ib_adc_o\(5);
    ib_adc_o(4) <= \ib_adc_o\(4);
    ib_adc_o(3) <= \ib_adc_o\(3);
    ib_adc_o(2) <= \ib_adc_o\(2);
    ib_adc_o(1) <= \ib_adc_o\(1);
    ib_adc_o(0) <= \ib_adc_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
jWLs4bDOTLdKJ2SCgqJyUzseGFYSL3cMeUvBF9oIMgq1Nlaxlg6wKYu/x3u9A7zZ
zSXLYEFrYPQVTUiYUhbKNNtT7NUcmhZC8WJ6guNaq5LB92B1k/YNTXfvJjc9Vhio
B5XdvjmivY0CjoIH4f39PmHZyymGP2RXORKNWXlTnfw=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=141355)
`protect data_block
[encoded data, 139136 characters]
z8aeEHcZVAv2IWyeib1f+4m6+laRM+Bg+HjkOA0BMPc=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity apb3_if is

    port( apb3_if_0_idq_pi_ki_o_0             : out   std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_1_PWDATA     : in    std_logic_vector(17 downto 0);
          apb3_if_0_idq_pi_kp_o               : out   std_logic_vector(17 downto 0);
          apb3_if_0_olmng_dv_o                : out   std_logic_vector(17 downto 0);
          apb3_if_0_olmng_iq_ref_in_o         : out   std_logic_vector(17 downto 0);
          apb3_if_0_olmng_theta_factor_o      : out   std_logic_vector(17 downto 0);
          apb3_if_0_pwm_dead_time_val_o       : out   std_logic_vector(17 downto 0);
          apb3_if_0_pwm_delay_time_val_o      : out   std_logic_vector(17 downto 0);
          apb3_if_0_pwm_gain_val_o            : out   std_logic_vector(17 downto 1);
          apb3_if_0_pwm_period_val_o          : out   std_logic_vector(17 downto 0);
          apb3_if_0_rate_limit_rate_cnt_o     : out   std_logic_vector(17 downto 0);
          apb3_if_0_rate_limit_ref_in_o       : out   std_logic_vector(17 downto 0);
          apb3_if_0_rate_limit_slew_cnt_o     : out   std_logic_vector(17 downto 0);
          apb3_if_0_seq_cntl_cl_omega_o       : out   std_logic_vector(17 downto 0);
          apb3_if_0_speed_pi_ki_o             : out   std_logic_vector(17 downto 0);
          apb3_if_0_filter_factor_bemf_o      : out   std_logic_vector(3 downto 0);
          apb3_if_0_auto_restart_no_o         : out   std_logic_vector(3 downto 0);
          apb3_if_0_speed_pi_kp_o             : out   std_logic_vector(17 downto 0);
          apb3_if_0_adc_control_reg_val_o     : out   std_logic_vector(5 downto 0);
          apb3_if_0_seq_cntl_config_o         : out   std_logic_vector(3 downto 0);
          apb3_if_0_filter_factor_omega_o     : out   std_logic_vector(3 downto 0);
          apb3_if_0_adc_channel_ch0_o         : out   std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch1_o         : out   std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch2_o         : out   std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch3_o         : out   std_logic_vector(15 downto 0);
          apb3_if_0_Ls_by_Ts_pu_o             : out   std_logic_vector(17 downto 0);
          apb3_if_0_Rs_pu_o                   : out   std_logic_vector(17 downto 0);
          apb3_if_0_adc_oc_thresh_o           : out   std_logic_vector(17 downto 0);
          apb3_if_0_adc_scale_val_o           : out   std_logic_vector(17 downto 0);
          apb3_if_0_angle_ki_o                : out   std_logic_vector(17 downto 0);
          apb3_if_0_angle_kp_o                : out   std_logic_vector(17 downto 0);
          prdata_o_1_2_0_a2_17_0              : out   std_logic_vector(1 to 1);
          prdata_o_1_2_0_a2_11_0              : out   std_logic_vector(1 to 1);
          adc_interface_0_result_ch1_o        : in    std_logic_vector(11 downto 0);
          adc_interface_0_result_ch0_o        : in    std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch3_o : in    std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch2_o : in    std_logic_vector(11 downto 0);
          RATE_LIMITER_0_rl_out_o             : in    std_logic_vector(17 downto 0);
          BLDC_ESTIMATOR_1_ealpha_o           : in    std_logic_vector(17 downto 0);
          BLDC_ESTIMATOR_1_theta_o            : in    std_logic_vector(17 downto 0);
          OLMNG_1_theta_o                     : in    std_logic_vector(17 downto 0);
          ADC_SCALING_1_ib_adc_o              : in    std_logic_vector(17 downto 0);
          ADC_SCALING_1_ia_adc_o              : in    std_logic_vector(17 downto 0);
          FOC_TRANSFORMS_0_iq_o               : in    std_logic_vector(17 downto 0);
          FOC_TRANSFORMS_0_id_o               : in    std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_1_PADDR      : in    std_logic_vector(11 downto 0);
          prdata_o_1_2_0_a2_12_0              : out   std_logic_vector(1 to 1);
          SPEED_ID_IQ_PI_1_iq_pi_output_o     : in    std_logic_vector(17 downto 0);
          net_189                             : in    std_logic_vector(17 downto 0);
          BLDC_ESTIMATOR_1_ealpha_filtered_o  : in    std_logic_vector(17 downto 0);
          SPEED_ID_IQ_PI_1_id_pi_output_o     : in    std_logic_vector(17 downto 0);
          BLDC_ESTIMATOR_1_ebeta_filtered_o   : in    std_logic_vector(17 downto 0);
          BLDC_ESTIMATOR_1_ebeta_o            : in    std_logic_vector(17 downto 0);
          BLDC_ESTIMATOR_0_speed_filtered_o   : in    std_logic_vector(17 downto 0);
          FOC_TRANSFORMS_0_valpha_o           : in    std_logic_vector(17 downto 0);
          SEQ_CONTROLLER_1_state_o_0          : in    std_logic;
          SEQ_CONTROLLER_1_state_o_2          : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o            : in    std_logic_vector(17 downto 0);
          BLDC_ESTIMATOR_1_pll_pi_out_o       : in    std_logic_vector(17 downto 0);
          FOC_TRANSFORMS_0_ibeta_o            : in    std_logic_vector(17 downto 0);
          FOC_TRANSFORMS_0_ialpha_o           : in    std_logic_vector(17 downto 0);
          prdata_o_1_2_0_0_1                  : out   std_logic_vector(2 to 2);
          prdata_o_1_0_1                      : out   std_logic_vector(16 to 16);
          prdata_o_1_0_0_4                    : out   std_logic;
          prdata_o_1_2_0_0_5                  : out   std_logic_vector(3 to 3);
          prdata_o_1_2_0_0_2                  : out   std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_0                  : out   std_logic_vector(2 to 2);
          prdata_o_1_3_0_0_3                  : out   std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_2                  : out   std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_0                  : out   std_logic_vector(11 to 11);
          prdata_o_1_8_3                      : out   std_logic_vector(6 to 6);
          prdata_o_1_8_2                      : out   std_logic_vector(6 to 6);
          prdata_o_1_8_0                      : out   std_logic_vector(6 to 6);
          prdata_o_1_0_2                      : out   std_logic_vector(16 to 16);
          prdata_o_1_2_0_0_4_2                : out   std_logic_vector(3 to 3);
          MC_System_0_AMBA_SLAVE_0_PRDATA_12  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_13  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_15  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_14  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_0   : out   std_logic;
          MC_System_0_FIC_0_LOCK              : in    std_logic;
          MC_System_0_FIC_0_CLK               : in    std_logic;
          apb3_if_0_stop_motor_o              : out   std_logic;
          apb3_if_0_start_motor_o             : out   std_logic;
          apb3_if_0_fault_clr_o               : out   std_logic;
          apb3_if_0_direction_config_o        : out   std_logic;
          N_2627                              : out   std_logic;
          N_2574                              : out   std_logic;
          prdata_m2_e_1_1                     : out   std_logic;
          N_2645                              : out   std_logic;
          N_739                               : out   std_logic;
          N_766                               : out   std_logic;
          N_768                               : out   std_logic;
          N_769                               : out   std_logic;
          N_1345                              : out   std_logic;
          N_767                               : out   std_logic;
          N_875                               : out   std_logic;
          N_770                               : out   std_logic;
          N_771                               : out   std_logic;
          N_772                               : out   std_logic;
          N_876                               : out   std_logic;
          N_773                               : out   std_logic;
          N_1333                              : out   std_logic;
          N_1347                              : out   std_logic;
          N_1351                              : out   std_logic;
          N_1326                              : out   std_logic;
          N_1346                              : out   std_logic;
          N_878                               : out   std_logic;
          N_789                               : out   std_logic;
          N_791                               : out   std_logic;
          N_1329                              : out   std_logic;
          N_1342                              : out   std_logic;
          N_790                               : out   std_logic;
          N_891                               : out   std_logic;
          N_1360                              : out   std_logic;
          N_1378                              : out   std_logic;
          N_1396                              : out   std_logic;
          N_774                               : out   std_logic;
          N_775                               : out   std_logic;
          N_776                               : out   std_logic;
          N_777                               : out   std_logic;
          N_792                               : out   std_logic;
          N_793                               : out   std_logic;
          N_832                               : out   std_logic;
          N_880                               : out   std_logic;
          N_882                               : out   std_logic;
          N_883                               : out   std_logic;
          N_892                               : out   std_logic;
          N_893                               : out   std_logic;
          N_894                               : out   std_logic;
          N_895                               : out   std_logic;
          N_738                               : out   std_logic;
          N_502                               : out   std_logic;
          N_240                               : out   std_logic;
          N_549                               : out   std_logic;
          N_870                               : out   std_logic;
          N_859                               : out   std_logic;
          N_788                               : out   std_logic;
          N_782                               : out   std_logic;
          N_763                               : out   std_logic;
          N_762                               : out   std_logic;
          N_750                               : out   std_logic;
          N_749                               : out   std_logic;
          N_1288                              : out   std_logic;
          N_1279                              : out   std_logic;
          N_1275                              : out   std_logic;
          N_1169                              : out   std_logic;
          N_1165                              : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE     : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PENABLE    : in    std_logic;
          prdata_m1_e_0_1                     : out   std_logic;
          N_2631                              : out   std_logic;
          N_1398                              : out   std_logic;
          N_519                               : in    std_logic;
          N_540                               : in    std_logic;
          N_2644                              : out   std_logic;
          N_2639                              : out   std_logic;
          N_2647                              : out   std_logic;
          N_2640                              : out   std_logic;
          N_2598                              : out   std_logic;
          N_2646                              : out   std_logic;
          N_2652                              : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx      : in    std_logic;
          N_2495                              : out   std_logic;
          N_2498                              : out   std_logic;
          N_2531                              : out   std_logic;
          N_542                               : in    std_logic;
          N_544                               : in    std_logic
        );

end apb3_if;

architecture DEF_ARCH of apb3_if is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \prdata_o_1_2_0_a2_17_0\ : std_logic_vector(1 to 1);
    signal \prdata_o_1_2_0_a2_11_0\ : std_logic_vector(1 to 1);
    signal \prdata_o_1_2_0_a2_12_0\ : std_logic_vector(1 to 1);
    signal \N_2627\, \N_2645\, \N_502\, \N_240\, \N_549\, 
        \prdata_m1_e_0_1\, \N_2644\, \N_2639\, \N_2647\, \N_2640\, 
        \N_2646\, \N_2652\ : std_logic;
    signal prdata_o_1_2_0_a2_10_1_1 : std_logic_vector(1 to 1);
    signal prdata_o_1_2_0_a2_11_0_1 : std_logic_vector(1 to 1);
    signal prdata_o_1_15_i_m2_i_m2_1_1 : 
        std_logic_vector(14 downto 1);
    signal prdata_o_1_13_i_m2_i_m2_i_m2_1_1 : 
        std_logic_vector(10 downto 8);
    signal prdata_o_1_13_i_m2_i_m2_1_1 : 
        std_logic_vector(11 downto 1);
    signal prdata_o_1_14_i_m2_i_m2_1_1 : 
        std_logic_vector(14 downto 5);
    signal prdata_o_1_15_i_m2_1_1 : 
        std_logic_vector(17 downto 2);
    signal prdata_o_1_14_i_m2_1_1 : 
        std_logic_vector(17 downto 1);
    signal prdata_o_1_13_i_m2_1_1 : std_logic_vector(6 to 6);
    signal prdata_o_1_16_i_m2_am : 
        std_logic_vector(17 downto 12);
    signal prdata_o_1_16_i_m2_bm : 
        std_logic_vector(17 downto 12);
    signal prdata_o_1_17_i_m2_am : std_logic_vector(17 downto 6);
    signal prdata_o_1_17_i_m2_bm : std_logic_vector(17 downto 6);
    signal prdata_o_1_0_0_RNO_1 : std_logic_vector(16 to 16);
    signal prdata_o_1_0_0_RNO_2 : std_logic_vector(16 to 16);
    signal prdata_o_1_16_i_m2_i_m2_am : 
        std_logic_vector(13 downto 2);
    signal prdata_o_1_16_i_m2_i_m2_bm : 
        std_logic_vector(13 downto 2);
    signal prdata_o_1_17_i_m2_i_m2_am : 
        std_logic_vector(13 downto 2);
    signal prdata_o_1_17_i_m2_i_m2_bm : 
        std_logic_vector(13 downto 2);
    signal prdata_o_1_16_i_m2_i_m2_i_m2_am : 
        std_logic_vector(10 downto 1);
    signal prdata_o_1_16_i_m2_i_m2_i_m2_bm : 
        std_logic_vector(10 downto 1);
    signal prdata_o_1_17_i_m2_i_m2_i_m2_am : 
        std_logic_vector(10 downto 1);
    signal prdata_o_1_17_i_m2_i_m2_i_m2_bm : 
        std_logic_vector(10 downto 1);
    signal prdata_o_1_0_a2_4_0 : std_logic_vector(17 to 17);
    signal prdata_o_1_2_0_a2_6_0 : std_logic_vector(2 to 2);
    signal prdata_o_1_0_0_0 : std_logic_vector(13 to 13);
    signal prdata_o_1_0_0 : std_logic_vector(12 to 12);
    signal prdata_o_1_0_0_3 : std_logic_vector(13 to 13);
    signal prdata_o_1_0_3 : std_logic_vector(12 to 12);
    signal \VCC\, idq_pi_ki_o_1_sqmuxa, \GND\, 
        idq_pi_kp_o_1_sqmuxa, olmng_dv_o_1_sqmuxa, 
        olmng_iq_ref_in_o_1_sqmuxa, olmng_theta_factor_o_1_sqmuxa, 
        pwm_dead_time_val_o_1_sqmuxa, 
        pwm_delay_time_val_o_1_sqmuxa, pwm_gain_val_o_1_sqmuxa, 
        pwm_period_val_o_1_sqmuxa, rate_limit_rate_cnt_o_1_sqmuxa, 
        rate_limit_ref_in_o_1_sqmuxa, 
        rate_limit_slew_cnt_o_1_sqmuxa, 
        seq_cntl_cl_omega_o_1_sqmuxa, speed_pi_ki_o_1_sqmuxa, 
        speed_pi_kp_o_1_sqmuxa, filter_factor_omega_o_1_sqmuxa, 
        filter_factor_bemf_o_1_sqmuxa, auto_restart_no_o_1_sqmuxa, 
        adc_channel_ch0_o_1_sqmuxa, 
        adc_control_reg_val_o_1_sqmuxa, 
        seq_cntl_config_o_1_sqmuxa, adc_channel_ch1_o_1_sqmuxa, 
        adc_channel_ch2_o_1_sqmuxa, adc_channel_ch3_o_1_sqmuxa, 
        Ls_by_Ts_pu_o_0_sqmuxa, Rs_pu_o_1_sqmuxa, 
        adc_oc_thresh_o_1_sqmuxa, adc_scale_val_o_1_sqmuxa, 
        angle_ki_o_1_sqmuxa, angle_kp_o_1_sqmuxa, 
        stop_motor_o_1_sqmuxa, start_motor_o_1_sqmuxa, 
        fault_clr_o_1_sqmuxa, direction_config_o_1_sqmuxa, 
        prdata_m2_e_1_N_2L1_Z, prdata_m2_e_1_N_3L3_Z, 
        prdata_o_1_2_0_a2_10_N_2L1_Z, 
        prdata_o_1_2_0_a2_10_N_3L3_Z, N_853, N_874, N_1327, 
        N_1355, N_877, N_1337, N_1328, N_849, N_879, 
        m88_i_m2_1_2_Z, N_2152, N_851, N_852, N_1359, 
        m85_i_m2_i_m2_1_2_Z, N_824, N_1319, N_1331, N_1341, 
        m76_i_m2_i_m2_1_2_Z, N_827, N_802, N_1349, N_850, 
        m79_i_m2_i_m2_1_2_Z, N_826, m82_i_m2_i_m2_1_2_Z, N_825, 
        N_1373, N_1391, N_65_0, N_1385, N_1395, N_57, N_144, 
        N_141, N_803, N_804, N_805, m73_i_m2_i_m2_am_Z, 
        m73_i_m2_i_m2_bm_Z, N_828, m70_i_m2_i_m2_am_Z, 
        m70_i_m2_i_m2_bm_Z, N_829, m67_i_m2_i_m2_am_Z, 
        m67_i_m2_i_m2_bm_Z, N_830, m61_i_m2_i_m2_am_Z, 
        m61_i_m2_i_m2_bm_Z, N_831, m58_i_m2_i_m2_am_Z, 
        m58_i_m2_i_m2_bm_Z, m55_i_m2_i_m2_am_Z, 
        m55_i_m2_i_m2_bm_Z, N_833, m52_i_m2_i_m2_am_Z, 
        m52_i_m2_i_m2_bm_Z, N_834, N_854, N_881, N_1238, N_910, 
        N_2636, N_2262, N_858, N_819, N_807, N_795, N_1287, 
        N_1177, direction_config_o_1_sqmuxa_0_a2_0_a2_3_2_Z, 
        N_2622, N_2663, 
        filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2_Z, 
        N_2628, N_2648, N_1400, m40_i_0_a2_6_0, N_2655, N_2548, 
        N_2551, N_2554, N_2557, N_2561, N_2564, N_2567, N_2570, 
        N_2608, N_2611, N_2614, N_2617, m40_i_0_3, m40_i_0_1, 
        m26_0_0_0, m19_0_0_0, N_2649, N_2650, m40_i_0_2, 
        m40_i_0_0, m26_0_0_3, m19_0_0_3, N_1094 : std_logic;

begin 

    prdata_o_1_2_0_a2_17_0(1) <= \prdata_o_1_2_0_a2_17_0\(1);
    prdata_o_1_2_0_a2_11_0(1) <= \prdata_o_1_2_0_a2_11_0\(1);
    prdata_o_1_2_0_a2_12_0(1) <= \prdata_o_1_2_0_a2_12_0\(1);
    N_2627 <= \N_2627\;
    N_2645 <= \N_2645\;
    N_502 <= \N_502\;
    N_240 <= \N_240\;
    N_549 <= \N_549\;
    prdata_m1_e_0_1 <= \prdata_m1_e_0_1\;
    N_2644 <= \N_2644\;
    N_2639 <= \N_2639\;
    N_2647 <= \N_2647\;
    N_2640 <= \N_2640\;
    N_2646 <= \N_2646\;
    N_2652 <= \N_2652\;

    \prdata_o_1_2_0_a2_7[1]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(8), B => 
        N_2636, C => \prdata_m1_e_0_1\, D => \N_2627\, Y => 
        \N_2639\);
    
    \prdata_o_1_3_0_0_0_cZ[11]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_144, B => N_849, C => \N_2640\, D => 
        \N_2652\, Y => prdata_o_1_3_0_0_0(11));
    
    \idq_pi_ki_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(6));
    
    \rate_limit_rate_cnt_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(16));
    
    \adc_channel_ch2_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(14));
    
    \prdata_o_1_2_0_0_0_RNO[2]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(2), B => 
        adc_interface_0_result_ch0_o(2), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_1_1(2), Y => N_802);
    
    \adc_oc_thresh_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(13));
    
    \rate_limit_slew_cnt_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(8));
    
    adc_channel_ch3_o_1_sqmuxa_0_a2_0_a2_0_a2 : CFG4
      generic map(INIT => x"0080")

      port map(A => N_2628, B => N_2649, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => N_2262, Y => 
        adc_channel_ch3_o_1_sqmuxa);
    
    \olmng_theta_factor_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(4));
    
    \adc_channel_ch3_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(15));
    
    \prdata_o_1_17_i_m2_i_m2_ns[9]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_am(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_bm(9), Y => N_777);
    
    \prdata_o_1_16_i_m2_i_m2_am[5]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(5), Y => 
        prdata_o_1_16_i_m2_i_m2_am(5));
    
    \prdata_o_1_8_3_RNO_0[6]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(6), B => 
        FOC_TRANSFORMS_0_id_o(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(6));
    
    \speed_pi_kp_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(3));
    
    m67_i_m2_i_m2_ns : CFG3
      generic map(INIT => x"E2")

      port map(A => m67_i_m2_i_m2_am_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        m67_i_m2_i_m2_bm_Z, Y => N_830);
    
    \idq_pi_kp_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(14));
    
    \speed_pi_ki_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(3));
    
    \prdata_o_1_17_i_m2_i_m2_bm[9]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(9), Y => 
        prdata_o_1_17_i_m2_i_m2_bm(9));
    
    \olmng_iq_ref_in_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(11));
    
    \prdata_o_1_14_i_m2_i_m2_1_1[5]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(5), B => 
        FOC_TRANSFORMS_0_id_o(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_i_m2_1_1(5));
    
    \prdata_o_1_16_i_m2_i_m2_ns[4]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(4), Y => N_792);
    
    \prdata_o_1_3_0_2_RNO_0[11]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(11), B => 
        OLMNG_1_theta_o(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_i_m2_1_1(11));
    
    \idq_pi_kp_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(12));
    
    \prdata_o_1_17_i_m2_ns[12]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_am(12), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_bm(12), Y => N_1391);
    
    \prdata_o_1_16_i_m2_i_m2_bm[2]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(2), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(2));
    
    \adc_channel_ch0_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(3));
    
    \angle_ki_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(14));
    
    \adc_channel_ch0_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(15));
    
    \angle_ki_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(7));
    
    \speed_pi_ki_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(6));
    
    m82_i_m2_i_m2 : CFG4
      generic map(INIT => x"F305")

      port map(A => ADC_SCALING_1_ib_adc_o(15), B => 
        ADC_SCALING_1_ia_adc_o(15), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        m82_i_m2_i_m2_1_2_Z, Y => N_825);
    
    m52_i_m2_i_m2_ns : CFG3
      generic map(INIT => x"E2")

      port map(A => m52_i_m2_i_m2_am_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        m52_i_m2_i_m2_bm_Z, Y => N_834);
    
    \pwm_period_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(10));
    
    \rate_limit_ref_in_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(7));
    
    \prdata_o_1_15_i_m2_i_m2_1_1[9]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(9), B => 
        OLMNG_1_theta_o(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_i_m2_1_1(9));
    
    \pwm_period_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(6));
    
    \prdata_o_1_8_0_RNO[6]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(6), B => 
        adc_interface_0_result_ch0_o(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_1_1(6), Y => N_1319);
    
    \prdata_o_1_2_0_a2_6_0[2]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_519, B => \N_502\, C => 
        SEQ_CONTROLLER_1_state_o_2, D => N_540, Y => 
        prdata_o_1_2_0_a2_6_0(2));
    
    \idq_pi_kp_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(13));
    
    \Ls_by_Ts_pu_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(12));
    
    \Ls_by_Ts_pu_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(16));
    
    \prdata_o_1_16_i_m2_i_m2_ns[13]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(13), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(13), Y => N_854);
    
    \rate_limit_rate_cnt_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(17));
    
    \adc_channel_ch2_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(9));
    
    \pwm_delay_time_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(1));
    
    \idq_pi_ki_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(15));
    
    \speed_pi_kp_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(15));
    
    \prdata_o_1_17_i_m2_i_m2_i_m2_ns[1]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_i_m2_am(1), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_i_m2_bm(1), Y => N_894);
    
    \prdata_o_1_0_3_RNO_0[12]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(12), B => 
        FOC_TRANSFORMS_0_id_o(12), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(12));
    
    \idq_pi_kp_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(9));
    
    \prdata_o_1_16_i_m2_i_m2_ns[11]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(11), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(11), Y => N_144);
    
    \idq_pi_kp_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(8));
    
    \pwm_dead_time_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(9));
    
    \prdata_o_1_17_i_m2_bm[17]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(17), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(17), Y
         => prdata_o_1_17_i_m2_bm(17));
    
    \olmng_iq_ref_in_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(0));
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_0_a2_4_a2_2_RNIDUNE3 : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_2_0_a2_17_0\(1), B => 
        prdata_m2_e_1_N_2L1_Z, C => \N_2627\, D => 
        prdata_m2_e_1_N_3L3_Z, Y => N_2574);
    
    \angle_kp_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(4));
    
    \prdata_o_1_2_0_a2_10_1[1]\ : CFG4
      generic map(INIT => x"0012")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(8), B => 
        prdata_o_1_2_0_a2_10_1_1(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => prdata_m2_e_1_1);
    
    \rate_limit_slew_cnt_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(5));
    
    \prdata_o_1_0_0_RNO_0[12]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(12), B => 
        OLMNG_1_theta_o(12), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_1_1(12));
    
    \prdata_o_1_2_0_a2_2[2]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(2), B => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(2), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => \N_2645\, Y => 
        N_2531);
    
    direction_config_o_1_sqmuxa_0_a2_0_a2_0 : CFG4
      generic map(INIT => x"1000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), C => 
        direction_config_o_1_sqmuxa_0_a2_0_a2_3_2_Z, D => 
        MC_System_0_AMBA_SLAVE_0_PSELx, Y => N_2649);
    
    \Rs_pu_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(5));
    
    direction_config_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => direction_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_direction_config_o);
    
    \idq_pi_kp_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(11));
    
    \adc_channel_ch3_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(13));
    
    \Ls_by_Ts_pu_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(11));
    
    adc_oc_thresh_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => N_544, 
        C => N_2628, D => N_2650, Y => adc_oc_thresh_o_1_sqmuxa);
    
    \pwm_delay_time_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(13));
    
    \olmng_dv_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(6));
    
    \angle_kp_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(2));
    
    \angle_ki_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(13));
    
    \speed_pi_ki_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(15));
    
    \adc_control_reg_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_control_reg_val_o(3));
    
    \adc_channel_ch1_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(7));
    
    \prdata_o_1_2_0_a2_10_1_1[1]\ : CFG2
      generic map(INIT => x"7")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => 
        prdata_o_1_2_0_a2_10_1_1(1));
    
    adc_channel_ch2_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_2636, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => N_2649, D => 
        N_2628, Y => adc_channel_ch2_o_1_sqmuxa);
    
    \filter_factor_omega_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        filter_factor_omega_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_filter_factor_omega_o(3));
    
    \adc_channel_ch0_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(13));
    
    \pwm_gain_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(8));
    
    \prdata_o_1_2_0_0_4_2_RNO[3]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(3), B => 
        adc_interface_0_result_ch0_o(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_1_1(3), Y => N_874);
    
    \rate_limit_rate_cnt_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(11));
    
    \pwm_gain_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(17));
    
    \pwm_delay_time_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(7));
    
    \prdata_o_1_2_0_a2_20[1]\ : CFG2
      generic map(INIT => x"2")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_2636);
    
    \seq_cntl_cl_omega_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(0));
    
    \prdata_o_1_3_i_m2_i_m2[3]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(3), Y => N_910);
    
    \adc_scale_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(5));
    
    seq_cntl_cl_omega_o_1_sqmuxa_0_a2_0_a2_0_a2 : CFG4
      generic map(INIT => x"0800")

      port map(A => N_2648, B => N_2650, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => N_2636, Y => 
        seq_cntl_cl_omega_o_1_sqmuxa);
    
    \rate_limit_rate_cnt_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(8));
    
    \adc_channel_ch2_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(5));
    
    \prdata_o_1_4_i_m2_i_m2[5]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(5), Y => N_749);
    
    \rate_limit_slew_cnt_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(17));
    
    \olmng_theta_factor_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(16));
    
    \speed_pi_kp_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(17));
    
    \prdata_o_1_17_i_m2_i_m2_am[2]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(2), Y => 
        prdata_o_1_17_i_m2_i_m2_am(2));
    
    \prdata_o_1_16_i_m2_am[17]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(17), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(17), Y => 
        prdata_o_1_16_i_m2_am(17));
    
    \pwm_period_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(15));
    
    \pwm_delay_time_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(8));
    
    \prdata_o_1_0_a2_4[17]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_0_a2_4_0(17), B => N_2636, C => 
        \N_2627\, D => \prdata_m1_e_0_1\, Y => N_2598);
    
    \adc_oc_thresh_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(2));
    
    \adc_channel_ch3_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(7));
    
    \Rs_pu_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(0));
    
    \adc_channel_ch3_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(5));
    
    \filter_factor_omega_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        filter_factor_omega_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_filter_factor_omega_o(1));
    
    \pwm_delay_time_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(11));
    
    \prdata_o_1_2_0_0_o2[1]\ : CFG4
      generic map(INIT => x"5808")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => N_1398);
    
    \prdata_o_1_2_0_a2_9_RNIMKPQ7[1]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => \N_2644\, B => N_877, C => N_2551, D => 
        m26_0_0_0, Y => m26_0_0_3);
    
    \seq_cntl_cl_omega_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(10));
    
    \pwm_delay_time_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(10));
    
    \pwm_delay_time_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(15));
    
    \speed_pi_ki_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(7));
    
    \prdata_o_1_2_0_a2_7_RNI856F3[1]\ : CFG4
      generic map(INIT => x"7530")

      port map(A => N_824, B => N_807, C => \N_2639\, D => 
        \N_2644\, Y => m40_i_0_1);
    
    \angle_ki_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(6));
    
    \pwm_gain_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(2));
    
    \adc_oc_thresh_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(12));
    
    \rate_limit_ref_in_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(9));
    
    \angle_ki_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(12));
    
    \olmng_iq_ref_in_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(10));
    
    \speed_pi_kp_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(10));
    
    \rate_limit_rate_cnt_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(3));
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \olmng_iq_ref_in_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(6));
    
    m79_i_m2_i_m2 : CFG4
      generic map(INIT => x"F053")

      port map(A => RATE_LIMITER_0_rl_out_o(0), B => 
        BLDC_ESTIMATOR_1_ealpha_o(0), C => m79_i_m2_i_m2_1_2_Z, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_826);
    
    \prdata_o_1_17_i_m2_bm[12]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(12), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(12), Y
         => prdata_o_1_17_i_m2_bm(12));
    
    \Rs_pu_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(12));
    
    \idq_pi_ki_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(14));
    
    \prdata_o_1_3_0_0_3_RNO[11]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(11), B => 
        ADC_SCALING_1_ia_adc_o(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_i_m2_1_1(11), Y => N_850);
    
    \prdata_o_1_2_0_0_0_cZ[2]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => prdata_o_1_2_0_a2_6_0(2), B => N_802, C => 
        \N_2652\, D => N_542, Y => prdata_o_1_2_0_0_0(2));
    
    \speed_pi_ki_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(17));
    
    \pwm_gain_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(15));
    
    \prdata_o_1_2_0_a2_12_RNIJ90N3[1]\ : CFG4
      generic map(INIT => x"7350")

      port map(A => N_819, B => N_826, C => \N_2645\, D => 
        \N_2647\, Y => m40_i_0_3);
    
    angle_kp_o_1_sqmuxa_0_a2_1_a2 : CFG4
      generic map(INIT => x"0800")

      port map(A => 
        filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2_Z, B
         => N_2649, C => MC_System_0_AMBA_SLAVE_1_PADDR(2), D => 
        N_2636, Y => angle_kp_o_1_sqmuxa);
    
    \seq_cntl_cl_omega_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(7));
    
    \filter_factor_bemf_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        filter_factor_bemf_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_filter_factor_bemf_o(1));
    
    \idq_pi_ki_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(12));
    
    \prdata_o_1_16_i_m2_i_m2_am[2]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(2), Y => 
        prdata_o_1_16_i_m2_i_m2_am(2));
    
    \Rs_pu_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(4));
    
    \pwm_dead_time_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(5));
    
    \prdata_o_1_8_0_RNO_0[6]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(6), B => 
        adc_measurements_0_adc_result_ch2_o(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_1_1(6));
    
    speed_pi_kp_o_1_sqmuxa_0_a2_2_a2_0_a2 : CFG4
      generic map(INIT => x"0200")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => N_2262, D => 
        N_2655, Y => speed_pi_kp_o_1_sqmuxa);
    
    \prdata_o_1_0[12]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => N_1391, B => \N_2646\, C => N_2614, D => 
        prdata_o_1_0_3(12), Y => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12);
    
    \rate_limit_rate_cnt_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(7));
    
    \prdata_o_1_16_i_m2_i_m2_ns[2]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(2), Y => N_803);
    
    \Rs_pu_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(14));
    
    \olmng_dv_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(2));
    
    \prdata_o_1_2_0_a2_8[1]\ : CFG4
      generic map(INIT => x"E000")

      port map(A => N_2663, B => N_2622, C => \prdata_m1_e_0_1\, 
        D => \N_2627\, Y => \N_2640\);
    
    rate_limit_ref_in_o_1_sqmuxa_0_a2_1_a2_0_a2_1 : CFG4
      generic map(INIT => x"8000")

      port map(A => direction_config_o_1_sqmuxa_0_a2_0_a2_3_2_Z, 
        B => MC_System_0_AMBA_SLAVE_1_PADDR(6), C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, D => N_2628, Y => N_2655);
    
    \prdata_o_1_16_i_m2_i_m2_ns[5]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(5), Y => N_774);
    
    m61_i_m2_i_m2_ns : CFG3
      generic map(INIT => x"E2")

      port map(A => m61_i_m2_i_m2_am_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        m61_i_m2_i_m2_bm_Z, Y => N_831);
    
    \idq_pi_ki_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(13));
    
    \rate_limit_rate_cnt_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(0));
    
    \olmng_dv_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(16));
    
    \prdata_o_1_16_i_m2_i_m2_bm[9]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(9), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(9));
    
    \rate_limit_ref_in_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(15));
    
    \prdata_o_1_10_i_m2[16]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(16), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        FOC_TRANSFORMS_0_vbeta_o(16), Y => N_1287);
    
    \rate_limit_ref_in_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(5));
    
    \pwm_delay_time_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(12));
    
    \seq_cntl_cl_omega_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(12));
    
    \rate_limit_rate_cnt_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(13));
    
    \rate_limit_ref_in_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(4));
    
    \speed_pi_ki_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(10));
    
    \idq_pi_ki_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(9));
    
    \prdata_o_1_10_i_m2_i_m2[7]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        FOC_TRANSFORMS_0_vbeta_o(7), Y => N_870);
    
    pwm_period_val_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        \N_549\, C => N_2628, D => N_2650, Y => 
        pwm_period_val_o_1_sqmuxa);
    
    \Ls_by_Ts_pu_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(9));
    
    \angle_kp_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(17));
    
    \adc_scale_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(4));
    
    m70_i_m2_i_m2_ns : CFG3
      generic map(INIT => x"E2")

      port map(A => m70_i_m2_i_m2_am_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        m70_i_m2_i_m2_bm_Z, Y => N_829);
    
    \adc_channel_ch0_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(2));
    
    \pwm_period_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(7));
    
    \prdata_o_1_17_i_m2_bm[16]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(16), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(16), Y
         => prdata_o_1_17_i_m2_bm(16));
    
    \prdata_o_1_0_a2_4[12]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_ibeta_o(12), B => 
        FOC_TRANSFORMS_0_ialpha_o(12), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => \N_2639\, Y => 
        N_2617);
    
    \olmng_theta_factor_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(6));
    
    \prdata_o_1_2_0_a2_17_0_cZ[1]\ : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), Y => 
        \prdata_o_1_2_0_a2_17_0\(1));
    
    \Ls_by_Ts_pu_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(1));
    
    \adc_channel_ch2_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(0));
    
    \rate_limit_ref_in_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(8));
    
    \rate_limit_ref_in_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(13));
    
    \filter_factor_omega_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        filter_factor_omega_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_filter_factor_omega_o(2));
    
    \prdata_o_1_17_i_m2_i_m2_i_m2_bm[10]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(10), Y
         => prdata_o_1_17_i_m2_i_m2_i_m2_bm(10));
    
    \idq_pi_ki_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(5));
    
    \seq_cntl_cl_omega_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(5));
    
    \pwm_dead_time_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(8));
    
    \rate_limit_ref_in_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(16));
    
    \adc_channel_ch3_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(4));
    
    \prdata_o_1_13_i_m2_i_m2[1]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(1), B => 
        adc_interface_0_result_ch0_o(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_1_1(1), Y => N_766);
    
    \olmng_dv_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(5));
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_0_a2_4_a2_2_0_RNIJMHU : CFG4
      generic map(INIT => x"8000")

      port map(A => N_519, B => \N_502\, C => 
        SEQ_CONTROLLER_1_state_o_0, D => N_540, Y => 
        m40_i_0_a2_6_0);
    
    \prdata_o_1_3_0_0_RNO_0[11]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(11), B
         => adc_measurements_0_adc_result_ch2_o(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_1_1(11));
    
    \adc_oc_thresh_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(7));
    
    \olmng_iq_ref_in_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(3));
    
    \Ls_by_Ts_pu_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(2));
    
    \rate_limit_slew_cnt_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(7));
    
    filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2 : CFG4
      generic map(INIT => x"0400")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), D => \N_240\, Y => 
        filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2_Z);
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_0_a2_4_a2_2_0 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), Y => \N_502\);
    
    \prdata_o_1_2_0_a2_15[1]\ : CFG3
      generic map(INIT => x"08")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_2622);
    
    \adc_channel_ch2_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(12));
    
    \auto_restart_no_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => auto_restart_no_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_auto_restart_no_o(2));
    
    \prdata_o_1_10_i_m2_i_m2[9]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        FOC_TRANSFORMS_0_vbeta_o(9), Y => N_763);
    
    fault_clr_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => fault_clr_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_fault_clr_o);
    
    m67_i_m2_i_m2_bm : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(15), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(15), Y => m67_i_m2_i_m2_bm_Z);
    
    m88_i_m2_1_2 : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(0), B => 
        adc_measurements_0_adc_result_ch2_o(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => m88_i_m2_1_2_Z);
    
    \prdata_o_1_17_i_m2_ns[6]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_am(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_bm(6), Y => N_1385);
    
    m61_i_m2_i_m2_am : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0), Y => 
        m61_i_m2_i_m2_am_Z);
    
    \Rs_pu_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(2));
    
    m76_i_m2_i_m2 : CFG4
      generic map(INIT => x"F053")

      port map(A => RATE_LIMITER_0_rl_out_o(15), B => 
        BLDC_ESTIMATOR_1_ealpha_o(15), C => m76_i_m2_i_m2_1_2_Z, 
        D => MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_827);
    
    \idq_pi_ki_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(11));
    
    \pwm_dead_time_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(2));
    
    \adc_channel_ch2_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(11));
    
    \adc_channel_ch2_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(7));
    
    \rate_limit_slew_cnt_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(3));
    
    \prdata_o_1_8_2_RNO[6]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(6), B => 
        BLDC_ESTIMATOR_1_ealpha_o(6), C => 
        prdata_o_1_15_i_m2_1_1(6), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_1349);
    
    \adc_channel_ch1_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(14));
    
    \rate_limit_slew_cnt_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(0));
    
    filter_factor_bemf_o_1_sqmuxa_0_a2_0_a2_2_a2 : CFG4
      generic map(INIT => x"0080")

      port map(A => 
        filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2_Z, B
         => N_2649, C => MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        N_2262, Y => filter_factor_bemf_o_1_sqmuxa);
    
    \adc_channel_ch3_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(8));
    
    \rate_limit_slew_cnt_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(16));
    
    olmng_dv_o_1_sqmuxa_0_a2_0_a2_2_a2 : CFG4
      generic map(INIT => x"0008")

      port map(A => N_2648, B => N_2650, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => N_2262, Y => 
        olmng_dv_o_1_sqmuxa);
    
    \pwm_dead_time_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(1));
    
    \prdata_o_1_0_0_3_RNO[13]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(13), B => 
        ADC_SCALING_1_ia_adc_o(13), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_i_m2_1_1(13), Y => N_851);
    
    \seq_cntl_cl_omega_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(11));
    
    \prdata_o_1_2_0_a2_17[1]\ : CFG4
      generic map(INIT => x"0800")

      port map(A => \prdata_o_1_2_0_a2_17_0\(1), B => \N_502\, C
         => MC_System_0_AMBA_SLAVE_1_PADDR(6), D => \N_240\, Y
         => N_2631);
    
    \Ls_by_Ts_pu_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(8));
    
    \prdata_o_1_0_1_RNO[16]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(16), B => 
        ADC_SCALING_1_ia_adc_o(16), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(16), Y => N_1341);
    
    \prdata_o_1_17_i_m2_am[6]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(6), Y => 
        prdata_o_1_17_i_m2_am(6));
    
    \adc_channel_ch3_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(3));
    
    \adc_scale_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(1));
    
    \prdata_o_1_2_0_a2_9[1]\ : CFG4
      generic map(INIT => x"1000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => \N_2627\, D => 
        \prdata_m1_e_0_1\, Y => \N_2644\);
    
    \prdata_o_1_14_i_m2[4]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(4), B => 
        ADC_SCALING_1_ia_adc_o(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(4), Y => N_1329);
    
    m58_i_m2_i_m2_ns : CFG3
      generic map(INIT => x"E2")

      port map(A => m58_i_m2_i_m2_am_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        m58_i_m2_i_m2_bm_Z, Y => N_832);
    
    \pwm_gain_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(14));
    
    \angle_kp_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(8));
    
    seq_cntl_config_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        \N_549\, C => N_2648, D => N_2649, Y => 
        seq_cntl_config_o_1_sqmuxa);
    
    m52_i_m2_i_m2_bm : CFG3
      generic map(INIT => x"47")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(15), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(15), Y
         => m52_i_m2_i_m2_bm_Z);
    
    \prdata_o_1_17_i_m2_i_m2_ns[11]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_am(11), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_bm(11), Y => N_141);
    
    \Ls_by_Ts_pu_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(0));
    
    \pwm_delay_time_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(4));
    
    \prdata_o_1_17_i_m2_i_m2_bm[8]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(8), Y => 
        prdata_o_1_17_i_m2_i_m2_bm(8));
    
    \adc_control_reg_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_control_reg_val_o(4));
    
    \speed_pi_kp_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(6));
    
    adc_channel_ch0_o_1_sqmuxa_0_a2_0_a2_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => N_544, 
        C => N_2628, D => N_2649, Y => adc_channel_ch0_o_1_sqmuxa);
    
    \prdata_o_1_16_i_m2_i_m2_bm[4]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(4), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(4));
    
    m85_i_m2_i_m2 : CFG4
      generic map(INIT => x"F305")

      port map(A => ADC_SCALING_1_ib_adc_o(0), B => 
        ADC_SCALING_1_ia_adc_o(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        m85_i_m2_i_m2_1_2_Z, Y => N_824);
    
    \angle_ki_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(16));
    
    pwm_delay_time_val_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        \N_549\, C => N_2628, D => N_2650, Y => 
        pwm_delay_time_val_o_1_sqmuxa);
    
    \pwm_gain_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(11));
    
    \prdata_o_1_0_0_RNO_3[16]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(16), B => 
        OLMNG_1_theta_o(16), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_1_1(16));
    
    m79_i_m2_i_m2_1_2 : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(0), B => 
        OLMNG_1_theta_o(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        m79_i_m2_i_m2_1_2_Z);
    
    \angle_ki_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(11));
    
    \rate_limit_ref_in_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(17));
    
    \adc_scale_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(13));
    
    \prdata_o_1_17_i_m2_i_m2_am[9]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(9), Y => 
        prdata_o_1_17_i_m2_i_m2_am(9));
    
    \rate_limit_slew_cnt_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(6));
    
    \rate_limit_slew_cnt_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(15));
    
    \seq_cntl_cl_omega_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(8));
    
    \prdata_o_1_2_0_0_1_RNO[2]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(2), B => 
        ADC_SCALING_1_ia_adc_o(2), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(2), Y => N_1327);
    
    \adc_oc_thresh_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(4));
    
    \prdata_o_1_4_i_m2_i_m2[2]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(2), Y => N_795);
    
    \prdata_o_1_15_i_m2_i_m2_1_1[14]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(14), B => 
        OLMNG_1_theta_o(14), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_i_m2_1_1(14));
    
    \rate_limit_ref_in_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(1));
    
    \prdata_o_1_14_i_m2_1_1[1]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(1), B => 
        FOC_TRANSFORMS_0_id_o(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(1));
    
    \prdata_o_1_16_i_m2_i_m2_i_m2_bm[10]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(10), Y => 
        prdata_o_1_16_i_m2_i_m2_i_m2_bm(10));
    
    \adc_channel_ch2_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(6));
    
    rate_limit_rate_cnt_o_1_sqmuxa_0_a2_1_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(5), B => 
        N_2663, C => N_2655, Y => rate_limit_rate_cnt_o_1_sqmuxa);
    
    \adc_channel_ch1_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(6));
    
    \prdata_o_1_0_0_3[13]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => \N_2644\, B => N_851, C => N_2570, D => 
        prdata_o_1_0_0_0(13), Y => prdata_o_1_0_0_3(13));
    
    \prdata_o_1_2_0_a2_5[1]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_ibeta_o(1), B => 
        FOC_TRANSFORMS_0_ialpha_o(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => \N_2639\, Y => 
        N_2498);
    
    \prdata_o_1_17_i_m2_i_m2_bm[3]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(3), Y => 
        prdata_o_1_17_i_m2_i_m2_bm(3));
    
    \adc_channel_ch0_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(7));
    
    \rate_limit_ref_in_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(11));
    
    idq_pi_ki_o_1_sqmuxa_0_a2_0_a2_1_a2 : CFG4
      generic map(INIT => x"0800")

      port map(A => N_544, B => N_2655, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => 
        idq_pi_ki_o_1_sqmuxa);
    
    \rate_limit_rate_cnt_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(10));
    
    \speed_pi_ki_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(4));
    
    \Ls_by_Ts_pu_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(5));
    
    \prdata_o_1_16_i_m2_am[12]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(12), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(12), Y => 
        prdata_o_1_16_i_m2_am(12));
    
    \Rs_pu_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(1));
    
    \auto_restart_no_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => auto_restart_no_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_auto_restart_no_o(1));
    
    \adc_channel_ch2_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(1));
    
    \prdata_o_1_0_1_cZ[16]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_1341, B => N_1177, C => \N_2639\, D => 
        \N_2644\, Y => prdata_o_1_0_1(16));
    
    \prdata_o_1_15_i_m2_i_m2_1_1[1]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(1), B => 
        OLMNG_1_theta_o(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_i_m2_1_1(1));
    
    \adc_scale_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(16));
    
    \prdata_o_1_17_i_m2_i_m2_i_m2_am[1]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(1), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1), Y => 
        prdata_o_1_17_i_m2_i_m2_i_m2_am(1));
    
    \idq_pi_kp_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(1));
    
    speed_pi_kp_o_1_sqmuxa_0_a2_2_a2_0_o2 : CFG2
      generic map(INIT => x"E")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => N_2262);
    
    stop_motor_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => stop_motor_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_stop_motor_o);
    
    \rate_limit_ref_in_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(2));
    
    \adc_channel_ch0_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(8));
    
    \prdata_o_1_15_i_m2_1_1[17]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(17), B => 
        OLMNG_1_theta_o(17), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_1_1(17));
    
    m55_i_m2_i_m2_bm : CFG3
      generic map(INIT => x"47")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(14), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(14), Y
         => m55_i_m2_i_m2_bm_Z);
    
    \adc_channel_ch1_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(3));
    
    \olmng_iq_ref_in_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(8));
    
    \seq_cntl_config_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_config_o(3));
    
    \prdata_o_1_2_0_a2_12[1]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        \prdata_o_1_2_0_a2_17_0\(1), C => 
        \prdata_o_1_2_0_a2_12_0\(1), D => \N_2627\, Y => \N_2647\);
    
    angle_ki_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => 
        filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2_Z, B
         => N_2649, C => MC_System_0_AMBA_SLAVE_1_PADDR(2), D => 
        N_2636, Y => angle_ki_o_1_sqmuxa);
    
    \pwm_delay_time_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(17));
    
    \adc_oc_thresh_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(1));
    
    \adc_channel_ch2_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(2));
    
    \seq_cntl_cl_omega_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(16));
    
    \prdata_o_1_16_i_m2_i_m2_am[9]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(9), Y => 
        prdata_o_1_16_i_m2_i_m2_am(9));
    
    prdata_m2_e_1_N_2L1 : CFG4
      generic map(INIT => x"0008")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => 
        prdata_m2_e_1_N_2L1_Z);
    
    \adc_oc_thresh_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(5));
    
    \prdata_o_1_0_2_cZ[16]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_1287, B => N_1395, C => \N_2645\, D => 
        \N_2646\, Y => prdata_o_1_0_2(16));
    
    adc_control_reg_val_o_1_sqmuxa_0_a2_3_a2 : CFG4
      generic map(INIT => x"0008")

      port map(A => N_2628, B => N_2649, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => N_2262, Y => 
        adc_control_reg_val_o_1_sqmuxa);
    
    \adc_channel_ch1_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(8));
    
    \adc_channel_ch0_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(5));
    
    \Rs_pu_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(17));
    
    \prdata_o_1_16_i_m2_i_m2_ns[8]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(8), Y => N_793);
    
    \prdata_o_1_17_i_m2_i_m2_ns[2]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_am(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_bm(2), Y => N_804);
    
    rate_limit_rate_cnt_o_1_sqmuxa_0_a2_1_a2_0 : CFG3
      generic map(INIT => x"08")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => N_2663);
    
    \olmng_theta_factor_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(10));
    
    \prdata_o_1_15_i_m2_i_m2[14]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(14), B => 
        BLDC_ESTIMATOR_1_ealpha_o(14), C => 
        prdata_o_1_15_i_m2_i_m2_1_1(14), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_879);
    
    \prdata_o_1_13_i_m2_i_m2[4]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(4), B => 
        adc_interface_0_result_ch0_o(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_1_1(4), Y => N_789);
    
    \angle_ki_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(15));
    
    \prdata_o_1_17_i_m2_i_m2_ns[5]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_am(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_bm(5), Y => N_776);
    
    \olmng_theta_factor_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(15));
    
    \olmng_dv_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(8));
    
    \idq_pi_ki_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(1));
    
    \pwm_dead_time_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(4));
    
    \angle_ki_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(5));
    
    \adc_scale_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(14));
    
    \prdata_o_1_14_i_m2_i_m2[7]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(7), B => 
        ADC_SCALING_1_ia_adc_o(7), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_i_m2_1_1(7), Y => N_876);
    
    \prdata_o_1_13_i_m2_i_m2[9]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(9), B => 
        adc_interface_0_result_ch0_o(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_1_1(9), Y => N_768);
    
    \adc_control_reg_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_control_reg_val_o(5));
    
    \adc_scale_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(0));
    
    \Ls_by_Ts_pu_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(15));
    
    \angle_kp_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(5));
    
    \pwm_period_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(17));
    
    \Ls_by_Ts_pu_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(13));
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_0_a2_4_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => N_2636, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => N_2649, D => 
        N_2628, Y => adc_channel_ch1_o_1_sqmuxa);
    
    \olmng_iq_ref_in_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(9));
    
    \prdata_o_1_15_i_m2_i_m2_1_1[5]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(5), B => 
        OLMNG_1_theta_o(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_i_m2_1_1(5));
    
    \prdata_o_1_2_0_a2_11[1]\ : CFG4
      generic map(INIT => x"2000")

      port map(A => \prdata_o_1_2_0_a2_17_0\(1), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), C => 
        \prdata_o_1_2_0_a2_11_0\(1), D => \N_2627\, Y => \N_2646\);
    
    \angle_ki_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(10));
    
    \speed_pi_ki_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(9));
    
    \Rs_pu_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(10));
    
    \idq_pi_ki_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(3));
    
    \adc_oc_thresh_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(0));
    
    \pwm_dead_time_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(0));
    
    \adc_scale_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(11));
    
    \prdata_o_1_2_0_0_5_cZ[3]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_1328, B => N_858, C => \N_2639\, D => 
        \N_2644\, Y => prdata_o_1_2_0_0_5(3));
    
    \olmng_iq_ref_in_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(13));
    
    \prdata_o_1_3_0_0_3_cZ[11]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => N_2561, B => N_2564, C => N_850, D => 
        \N_2644\, Y => prdata_o_1_3_0_0_3(11));
    
    \prdata_o_1_2_0_a2_12_0_cZ[1]\ : CFG4
      generic map(INIT => x"0110")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => 
        \prdata_o_1_2_0_a2_12_0\(1));
    
    \prdata_o_1_2_0_a2_8_RNI4RHQ4[1]\ : CFG4
      generic map(INIT => x"7530")

      port map(A => N_828, B => N_831, C => \N_2646\, D => 
        \N_2640\, Y => m40_i_0_2);
    
    \Ls_by_Ts_pu_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(3));
    
    m61_i_m2_i_m2_bm : CFG3
      generic map(INIT => x"47")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(0), Y => 
        m61_i_m2_i_m2_bm_Z);
    
    \prdata_o_1_14_i_m2_i_m2_1_1[10]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(10), B => 
        FOC_TRANSFORMS_0_id_o(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_i_m2_1_1(10));
    
    \prdata_o_1_2_0_1_RNO_0[2]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(2), B => 
        FOC_TRANSFORMS_0_id_o(2), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(2));
    
    \prdata_o_1_15_i_m2[3]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(3), B => 
        BLDC_ESTIMATOR_1_ealpha_o(3), C => 
        prdata_o_1_15_i_m2_1_1(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_1346);
    
    \prdata_o_1_10_i_m2[17]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(17), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        FOC_TRANSFORMS_0_vbeta_o(17), Y => N_1288);
    
    \idq_pi_kp_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(6));
    
    \olmng_theta_factor_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(11));
    
    \pwm_dead_time_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(10));
    
    \olmng_theta_factor_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(7));
    
    \idq_pi_kp_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(7));
    
    \prdata_o_1_2_0_0_2_cZ[2]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_803, B => N_804, C => \N_2646\, D => 
        \N_2640\, Y => prdata_o_1_2_0_0_2(2));
    
    \pwm_dead_time_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(13));
    
    \prdata_o_1_8_2_cZ[6]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_1385, B => N_1349, C => \N_2647\, D => 
        \N_2646\, Y => prdata_o_1_8_2(6));
    
    \adc_channel_ch1_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(4));
    
    Ls_by_Ts_pu_o_0_sqmuxa_0_a2_0_a2_1_a2 : CFG4
      generic map(INIT => x"0008")

      port map(A => 
        filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2_Z, B
         => N_2649, C => MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        N_2262, Y => Ls_by_Ts_pu_o_0_sqmuxa);
    
    seq_cntl_cl_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_3 : CFG4
      generic map(INIT => x"2000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), C => 
        direction_config_o_1_sqmuxa_0_a2_0_a2_3_2_Z, D => 
        MC_System_0_AMBA_SLAVE_0_PSELx, Y => N_2650);
    
    speed_pi_ki_o_1_sqmuxa_0_a2_2_a2 : CFG4
      generic map(INIT => x"0008")

      port map(A => \N_549\, B => N_2655, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => 
        speed_pi_ki_o_1_sqmuxa);
    
    \olmng_dv_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(4));
    
    \prdata_o_1_2_0_0_5_RNO[3]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(3), B => 
        ADC_SCALING_1_ia_adc_o(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(3), Y => N_1328);
    
    \adc_channel_ch1_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(5));
    
    \prdata_o_1_0_0[13]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => N_805, B => \N_2646\, C => N_2567, D => 
        prdata_o_1_0_0_3(13), Y => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13);
    
    \seq_cntl_cl_omega_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(2));
    
    \prdata_o_1_15_i_m2[8]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(8), B => 
        BLDC_ESTIMATOR_1_ealpha_o(8), C => 
        prdata_o_1_15_i_m2_1_1(8), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_1351);
    
    \prdata_o_1_2_0_a2_12_RNIGDST3[1]\ : CFG4
      generic map(INIT => x"BA30")

      port map(A => N_879, B => N_829, C => \N_2640\, D => 
        \N_2647\, Y => m26_0_0_0);
    
    \adc_oc_thresh_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(15));
    
    \prdata_o_1_2_0_0_4_2_cZ[3]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_874, B => N_881, C => \N_2652\, D => 
        \N_2646\, Y => prdata_o_1_2_0_0_4_2(3));
    
    \prdata_o_1_16_i_m2_i_m2_am[11]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(11), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(11), Y => 
        prdata_o_1_16_i_m2_i_m2_am(11));
    
    \idq_pi_ki_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(7));
    
    \seq_cntl_config_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_config_o(1));
    
    \pwm_gain_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(16));
    
    \olmng_iq_ref_in_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(16));
    
    \pwm_delay_time_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(6));
    
    \prdata_o_1_2_0_a2_7_RNIO5I81[1]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_ibeta_o(14), B => 
        FOC_TRANSFORMS_0_ialpha_o(14), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => \N_2639\, Y => 
        N_2551);
    
    direction_config_o_1_sqmuxa_0_a2_0_a2_3_2 : CFG4
      generic map(INIT => x"0200")

      port map(A => MC_System_0_AMBA_SLAVE_1_PWRITE, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), D => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, Y => 
        direction_config_o_1_sqmuxa_0_a2_0_a2_3_2_Z);
    
    \prdata_o_1_16_i_m2_i_m2_i_m2_am[1]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(1), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(1), Y => 
        prdata_o_1_16_i_m2_i_m2_i_m2_am(1));
    
    \prdata_o_1_16_i_m2_i_m2_am[4]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(4), Y => 
        prdata_o_1_16_i_m2_i_m2_am(4));
    
    \olmng_iq_ref_in_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(5));
    
    \prdata_o_1_2_0_a2_12_RNIH4JBF[1]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => m40_i_0_3, B => m40_i_0_1, C => m40_i_0_0, D
         => m40_i_0_2, Y => MC_System_0_AMBA_SLAVE_0_PRDATA_0);
    
    \angle_kp_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(14));
    
    \prdata_o_1_4_i_m2_i_m2[3]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(3), Y => N_858);
    
    \speed_pi_kp_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(9));
    
    \speed_pi_ki_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(0));
    
    \prdata_o_1_16_i_m2_i_m2_bm[6]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(6), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(6));
    
    \idq_pi_kp_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(16));
    
    \olmng_dv_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(9));
    
    \prdata_o_1_17_i_m2_am[17]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(17), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(17), Y => 
        prdata_o_1_17_i_m2_am(17));
    
    \speed_pi_kp_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(8));
    
    \seq_cntl_cl_omega_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(3));
    
    \olmng_iq_ref_in_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(17));
    
    \idq_pi_kp_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(17));
    
    \speed_pi_ki_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(1));
    
    \adc_channel_ch3_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(14));
    
    \Rs_pu_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(8));
    
    \rate_limit_rate_cnt_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(4));
    
    fault_clr_o_1_sqmuxa_0_a2_1_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_2650, B => N_2663, C => N_2648, Y => 
        fault_clr_o_1_sqmuxa);
    
    \prdata_o_1_16_i_m2_i_m2_bm[8]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(8), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(8));
    
    \prdata_o_1_13_i_m2_i_m2_i_m2[8]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(8), B => 
        adc_interface_0_result_ch0_o(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_i_m2_1_1(8), Y => N_739);
    
    \pwm_period_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(1));
    
    \prdata_o_1_10_i_m2[8]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        FOC_TRANSFORMS_0_vbeta_o(8), Y => N_1279);
    
    \pwm_dead_time_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(6));
    
    m58_i_m2_i_m2_am : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(4), Y => 
        m58_i_m2_i_m2_am_Z);
    
    \seq_cntl_cl_omega_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(15));
    
    \adc_channel_ch1_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(12));
    
    \seq_cntl_cl_omega_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(13));
    
    \Ls_by_Ts_pu_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(4));
    
    \prdata_o_1_0_0[12]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_1373, B => N_1355, C => \N_2647\, D => 
        \N_2640\, Y => prdata_o_1_0_0(12));
    
    \angle_ki_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(0));
    
    \adc_channel_ch0_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(14));
    
    \prdata_o_1_3_0_0_0_RNO[11]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(11), B => 
        adc_interface_0_result_ch0_o(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_1_1(11), Y => N_849);
    
    \adc_channel_ch2_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(10));
    
    rate_limit_slew_cnt_o_1_sqmuxa_0_a2_1_a2 : CFG4
      generic map(INIT => x"0800")

      port map(A => \N_549\, B => N_2655, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => 
        rate_limit_slew_cnt_o_1_sqmuxa);
    
    \pwm_gain_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(1));
    
    \prdata_o_1_3_0_0_2_cZ[11]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_852, B => N_141, C => \N_2646\, D => 
        \N_2647\, Y => prdata_o_1_3_0_0_2(11));
    
    \adc_channel_ch1_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(11));
    
    \prdata_o_1_17_i_m2_bm[6]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(6), Y => 
        prdata_o_1_17_i_m2_bm(6));
    
    \Ls_by_Ts_pu_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(17));
    
    \idq_pi_kp_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(5));
    
    \prdata_o_1_3_0_3_RNO_0[11]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(11), B => 
        FOC_TRANSFORMS_0_id_o(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_i_m2_1_1(11));
    
    \pwm_gain_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(7));
    
    m70_i_m2_i_m2_bm : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(14), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(14), Y => m70_i_m2_i_m2_bm_Z);
    
    \adc_channel_ch0_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(1));
    
    \prdata_o_1_14_i_m2_i_m2[14]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(14), B => 
        ADC_SCALING_1_ia_adc_o(14), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_i_m2_1_1(14), Y => N_877);
    
    \prdata_o_1_14_i_m2_1_1[8]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(8), B => 
        FOC_TRANSFORMS_0_id_o(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(8));
    
    \olmng_iq_ref_in_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(15));
    
    \speed_pi_ki_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(2));
    
    \rate_limit_rate_cnt_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(14));
    
    \prdata_o_1_0_0_RNO[16]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(16), B => 
        BLDC_ESTIMATOR_1_ealpha_o(16), C => 
        prdata_o_1_15_i_m2_1_1(16), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_1359);
    
    filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => \N_549\, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => N_2649, D => 
        filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2_Z, Y
         => filter_factor_omega_o_1_sqmuxa);
    
    \filter_factor_bemf_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        filter_factor_bemf_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_filter_factor_bemf_o(2));
    
    \angle_ki_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(3));
    
    \prdata_o_1_3_0_a2_5[11]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_ibeta_o(11), B => 
        FOC_TRANSFORMS_0_ialpha_o(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => \N_2639\, Y => 
        N_2564);
    
    \adc_channel_ch2_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(8));
    
    \prdata_o_1_8_2_RNO_0[6]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(6), B => 
        OLMNG_1_theta_o(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_1_1(6));
    
    \adc_scale_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(17));
    
    \angle_kp_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(13));
    
    \speed_pi_kp_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(7));
    
    \pwm_gain_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(9));
    
    \olmng_theta_factor_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(0));
    
    m52_i_m2_i_m2_am : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(15), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(15), Y => 
        m52_i_m2_i_m2_am_Z);
    
    \idq_pi_kp_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(3));
    
    \pwm_gain_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(3));
    
    \prdata_o_1_16_i_m2_i_m2_bm[11]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(11), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(11), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(11));
    
    \pwm_dead_time_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(15));
    
    \adc_control_reg_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_control_reg_val_o(1));
    
    \adc_oc_thresh_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(9));
    
    \prdata_o_1_17_i_m2_i_m2_ns[8]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_am(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_bm(8), Y => N_883);
    
    \prdata_o_1_3_i_m2_i_m2_RNIB3MU[3]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => N_1238, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => N_910, Y => N_738);
    
    \adc_control_reg_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_control_reg_val_o(2));
    
    \rate_limit_slew_cnt_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(13));
    
    \adc_scale_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(7));
    
    \rate_limit_rate_cnt_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(5));
    
    \adc_channel_ch2_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(15));
    
    \Rs_pu_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(11));
    
    \prdata_o_1_13_i_m2_i_m2_1_1[7]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(7), B => 
        adc_measurements_0_adc_result_ch2_o(7), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_1_1(7));
    
    \rate_limit_rate_cnt_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(6));
    
    \prdata_o_1_16_i_m2_i_m2_i_m2_ns[1]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_i_m2_am(1), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_i_m2_bm(1), Y => N_892);
    
    \angle_kp_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(0));
    
    \idq_pi_kp_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(10));
    
    \pwm_period_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(16));
    
    \prdata_o_1_2_0_a2_12_RNIOLST3[1]\ : CFG4
      generic map(INIT => x"7530")

      port map(A => N_830, B => N_827, C => \N_2647\, D => 
        \N_2640\, Y => m19_0_0_0);
    
    \olmng_dv_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(12));
    
    \angle_ki_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(9));
    
    \prdata_o_1_0_0_a2_1[13]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(13), B => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(13), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => \N_2645\, Y => 
        N_2567);
    
    \prdata_o_1_0_0_a2_4[13]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_ibeta_o(13), B => 
        FOC_TRANSFORMS_0_ialpha_o(13), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => \N_2639\, Y => 
        N_2570);
    
    filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_3_0 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), Y => \N_240\);
    
    \olmng_theta_factor_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(8));
    
    \pwm_delay_time_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(0));
    
    \pwm_gain_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(4));
    
    \olmng_theta_factor_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(12));
    
    \pwm_dead_time_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(7));
    
    \olmng_iq_ref_in_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(1));
    
    m55_i_m2_i_m2_am : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(14), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(14), Y => 
        m55_i_m2_i_m2_am_Z);
    
    \prdata_o_1_15_i_m2_i_m2[5]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(5), B => 
        BLDC_ESTIMATOR_1_ealpha_o(5), C => 
        prdata_o_1_15_i_m2_i_m2_1_1(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_772);
    
    \Rs_pu_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(6));
    
    \prdata_o_1_17_i_m2_i_m2_am[8]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(8), Y => 
        prdata_o_1_17_i_m2_i_m2_am(8));
    
    \adc_channel_ch3_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(0));
    
    \seq_cntl_cl_omega_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(17));
    
    \pwm_delay_time_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(2));
    
    \angle_kp_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(12));
    
    \prdata_o_1_17_i_m2_i_m2_am[11]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(11), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(11), Y => 
        prdata_o_1_17_i_m2_i_m2_am(11));
    
    \pwm_dead_time_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(14));
    
    \prdata_o_1_2_0_a2_11_0_cZ[1]\ : CFG4
      generic map(INIT => x"4408")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(8), B => 
        prdata_o_1_2_0_a2_11_0_1(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => 
        \prdata_o_1_2_0_a2_11_0\(1));
    
    \prdata_o_1_13_i_m2_i_m2_1_1[9]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(9), B => 
        adc_measurements_0_adc_result_ch2_o(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_1_1(9));
    
    start_motor_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => start_motor_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_start_motor_o);
    
    \filter_factor_bemf_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        filter_factor_bemf_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_filter_factor_bemf_o(3));
    
    \olmng_theta_factor_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(14));
    
    \rate_limit_rate_cnt_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(2));
    
    \olmng_theta_factor_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(1));
    
    idq_pi_kp_o_1_sqmuxa_0_a2_0_a2_1_a2 : CFG4
      generic map(INIT => x"0400")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => N_2262, D => 
        N_2655, Y => idq_pi_kp_o_1_sqmuxa);
    
    \prdata_o_1_17_i_m2_i_m2_am[3]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(3), Y => 
        prdata_o_1_17_i_m2_i_m2_am(3));
    
    \filter_factor_bemf_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        filter_factor_bemf_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_filter_factor_bemf_o(0));
    
    \speed_pi_kp_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(14));
    
    \prdata_o_1_16_i_m2_i_m2_am[6]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(6), Y => 
        prdata_o_1_16_i_m2_i_m2_am(6));
    
    \idq_pi_ki_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(4));
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_0_a2_4_a2_1 : CFG4
      generic map(INIT => x"0100")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), D => \N_240\, Y => 
        N_2628);
    
    \idq_pi_ki_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(16));
    
    \prdata_o_1_14_i_m2_1_1[4]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(4), B => 
        FOC_TRANSFORMS_0_id_o(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(4));
    
    \olmng_iq_ref_in_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(2));
    
    \prdata_o_1_8_i_m2[3]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(3), Y => N_1238);
    
    \idq_pi_ki_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(17));
    
    \pwm_period_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(4));
    
    \prdata_o_1_16_i_m2_i_m2_ns[7]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(7), Y => N_880);
    
    Rs_pu_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => N_544, B => MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        C => N_2649, D => 
        filter_factor_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_1_2_Z, Y
         => Rs_pu_o_1_sqmuxa);
    
    \prdata_o_1_17_i_m2_i_m2_bm[11]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(11), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(11), Y
         => prdata_o_1_17_i_m2_i_m2_bm(11));
    
    \olmng_dv_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(15));
    
    \pwm_gain_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(12));
    
    \rate_limit_rate_cnt_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(1));
    
    \adc_scale_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(6));
    
    \prdata_o_1_16_i_m2_i_m2_am[8]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(8), Y => 
        prdata_o_1_16_i_m2_i_m2_am(8));
    
    \adc_scale_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(9));
    
    \prdata_o_1_17_i_m2_i_m2_bm[7]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(7), Y => 
        prdata_o_1_17_i_m2_i_m2_bm(7));
    
    \prdata_o_1_16_i_m2_i_m2_ns[6]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(6), Y => N_57);
    
    \adc_channel_ch2_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(13));
    
    \rate_limit_slew_cnt_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(12));
    
    m88_i_m2 : CFG4
      generic map(INIT => x"3F50")

      port map(A => adc_interface_0_result_ch1_o(0), B => 
        adc_interface_0_result_ch0_o(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => m88_i_m2_1_2_Z, Y
         => N_2152);
    
    \Ls_by_Ts_pu_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(6));
    
    \Rs_pu_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(9));
    
    \prdata_o_1_0_0_RNO_2[16]\ : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(16), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(16), Y => 
        prdata_o_1_0_0_RNO_2(16));
    
    m76_i_m2_i_m2_1_2 : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(15), B => 
        OLMNG_1_theta_o(15), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        m76_i_m2_i_m2_1_2_Z);
    
    \prdata_o_1_8_3_cZ[6]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => N_2608, B => N_2611, C => N_1331, D => 
        \N_2644\, Y => prdata_o_1_8_3(6));
    
    \rate_limit_ref_in_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(12));
    
    \prdata_o_1_2_0_a2_2[1]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(1), B => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => \N_2645\, Y => 
        N_2495);
    
    \adc_channel_ch3_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(1));
    
    \rate_limit_slew_cnt_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(10));
    
    \seq_cntl_cl_omega_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(14));
    
    \angle_kp_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(1));
    
    \pwm_dead_time_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(11));
    
    \speed_pi_kp_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(1));
    
    \prdata_o_1_16_i_m2_i_m2_bm[13]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(13), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(13), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(13));
    
    m142_i_m2_i_m2 : CFG3
      generic map(INIT => x"1D")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(0), Y => N_807);
    
    \prdata_o_1_13_i_m2_i_m2[7]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(7), B => 
        adc_interface_0_result_ch0_o(7), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_1_1(7), Y => N_875);
    
    \adc_oc_thresh_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(16));
    
    \prdata_o_1_17_i_m2_i_m2_bm[13]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(13), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(13), Y
         => prdata_o_1_17_i_m2_i_m2_bm(13));
    
    \speed_pi_ki_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(14));
    
    \prdata_o_1_17_i_m2_am[12]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(12), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(12), Y => 
        prdata_o_1_17_i_m2_am(12));
    
    \speed_pi_kp_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(12));
    
    \auto_restart_no_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => auto_restart_no_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_auto_restart_no_o(0));
    
    \seq_cntl_config_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_config_o(2));
    
    \pwm_delay_time_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(5));
    
    \seq_cntl_cl_omega_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(4));
    
    \prdata_o_1_15_i_m2_i_m2[1]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(1), B => 
        BLDC_ESTIMATOR_1_ealpha_o(1), C => 
        prdata_o_1_15_i_m2_i_m2_1_1(1), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_771);
    
    \olmng_dv_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(13));
    
    \adc_channel_ch1_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(1));
    
    \rate_limit_rate_cnt_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(15));
    
    \olmng_theta_factor_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(13));
    
    \prdata_o_1_13_i_m2_i_m2_i_m2[10]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(10), B => 
        adc_interface_0_result_ch0_o(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_i_m2_1_1(10), Y => N_891);
    
    \angle_kp_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(6));
    
    stop_motor_o_1_sqmuxa_0_a2_4_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_2648, B => N_2650, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => N_2636, Y => 
        stop_motor_o_1_sqmuxa);
    
    \idq_pi_ki_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(8));
    
    \prdata_o_1_17_i_m2_i_m2_bm[5]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(5), Y => 
        prdata_o_1_17_i_m2_i_m2_bm(5));
    
    \adc_channel_ch0_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(4));
    
    m70_i_m2_i_m2_am : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(14), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(14), Y => m70_i_m2_i_m2_am_Z);
    
    \prdata_o_1_17_i_m2_i_m2_ns[3]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_am(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_bm(3), Y => N_881);
    
    \olmng_theta_factor_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(17));
    
    \prdata_o_1_0_0_0_RNO[13]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(13), B => 
        BLDC_ESTIMATOR_1_ealpha_o(13), C => 
        prdata_o_1_15_i_m2_i_m2_1_1(13), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_853);
    
    \prdata_o_1_16_i_m2_ns[17]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_am(17), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_bm(17), Y => N_1378);
    
    \olmng_theta_factor_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(5));
    
    \idq_pi_kp_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(4));
    
    \prdata_o_1_13_i_m2_i_m2_i_m2_1_1[8]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(8), B => 
        adc_measurements_0_adc_result_ch2_o(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_i_m2_1_1(8));
    
    \adc_channel_ch2_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(4));
    
    \adc_channel_ch3_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(12));
    
    \prdata_o_1_0_a2_1[12]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(12), B => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(12), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => \N_2645\, Y => 
        N_2614);
    
    \prdata_o_1_8_a2_2[6]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(6), B => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => \N_2645\, Y => 
        N_2608);
    
    \speed_pi_ki_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(12));
    
    \pwm_gain_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(10));
    
    \prdata_o_1_15_i_m2_1_1[3]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(3), B => 
        OLMNG_1_theta_o(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_1_1(3));
    
    \prdata_o_1_17_i_m2_i_m2_i_m2_bm[1]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(1), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(1), Y => 
        prdata_o_1_17_i_m2_i_m2_i_m2_bm(1));
    
    \prdata_o_1_8_3_RNO[6]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(6), B => 
        ADC_SCALING_1_ia_adc_o(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(6), Y => N_1331);
    
    \speed_pi_kp_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(13));
    
    \idq_pi_ki_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(10));
    
    \adc_scale_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(8));
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_0_a2_4_a2_2 : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), Y => \N_2627\);
    
    \olmng_iq_ref_in_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(4));
    
    m85_i_m2_i_m2_1_2 : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(0), B => 
        FOC_TRANSFORMS_0_id_o(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        m85_i_m2_i_m2_1_2_Z);
    
    \adc_channel_ch0_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(0));
    
    \adc_channel_ch0_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(6));
    
    \adc_channel_ch3_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(11));
    
    \rate_limit_ref_in_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(0));
    
    \prdata_o_1_17_i_m2_am[16]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(16), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(16), Y => 
        prdata_o_1_17_i_m2_am(16));
    
    \angle_kp_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(16));
    
    \seq_cntl_cl_omega_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(9));
    
    \prdata_o_1_3_0_a2_2[11]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(11), B => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => \N_2645\, Y => 
        N_2561);
    
    \olmng_dv_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(0));
    
    \adc_channel_ch0_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(12));
    
    \angle_kp_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(11));
    
    m103_i_m2_i_m2 : CFG3
      generic map(INIT => x"35")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(0), B => 
        FOC_TRANSFORMS_0_vbeta_o(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => N_819);
    
    \adc_channel_ch2_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch2_o(3));
    
    \pwm_dead_time_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(16));
    
    \prdata_o_1_17_i_m2_ns[17]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_am(17), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_bm(17), Y => N_1396);
    
    \prdata_o_1_17_i_m2_i_m2_i_m2_ns[10]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_i_m2_am(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_i_m2_bm(10), Y => N_895);
    
    \adc_channel_ch0_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(11));
    
    m58_i_m2_i_m2_bm : CFG3
      generic map(INIT => x"47")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(4), Y => 
        m58_i_m2_i_m2_bm_Z);
    
    \prdata_o_1_17_i_m2_i_m2_i_m2_am[10]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(10), Y => 
        prdata_o_1_17_i_m2_i_m2_i_m2_am(10));
    
    \auto_restart_no_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => auto_restart_no_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_auto_restart_no_o(3));
    
    \adc_channel_ch1_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(10));
    
    \prdata_o_1_15_i_m2_i_m2[10]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(10), B => 
        BLDC_ESTIMATOR_1_ealpha_o(10), C => 
        prdata_o_1_15_i_m2_i_m2_1_1(10), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_791);
    
    \prdata_o_1_16_i_m2_bm[17]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(17), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(17), Y => 
        prdata_o_1_16_i_m2_bm(17));
    
    \prdata_o_1_2_0_a2_11_RNINIR6B[1]\ : CFG4
      generic map(INIT => x"FFF4")

      port map(A => N_834, B => \N_2646\, C => N_2554, D => 
        m19_0_0_3, Y => MC_System_0_AMBA_SLAVE_0_PRDATA_15);
    
    \seq_cntl_cl_omega_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(1));
    
    \prdata_o_1_2_0_a2_7_RNIQ7I81[1]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_ibeta_o(15), B => 
        FOC_TRANSFORMS_0_ialpha_o(15), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => \N_2639\, Y => 
        N_2557);
    
    \prdata_o_1_2_0_5_RNO_0[3]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(3), B => 
        FOC_TRANSFORMS_0_id_o(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(3));
    
    \rate_limit_slew_cnt_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(9));
    
    \prdata_o_1_17_i_m2_i_m2_ns[13]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_am(13), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_bm(13), Y => N_805);
    
    \olmng_dv_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(7));
    
    \prdata_o_1_4_i_m2_i_m2[7]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(7), Y => N_859);
    
    \prdata_o_1_0_0_RNO[12]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(12), B => 
        BLDC_ESTIMATOR_1_ealpha_o(12), C => 
        prdata_o_1_15_i_m2_1_1(12), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_1355);
    
    \adc_channel_ch3_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(2));
    
    \idq_pi_ki_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(2));
    
    \Ls_by_Ts_pu_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(7));
    
    \adc_scale_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(2));
    
    GND_Z : GND
      port map(Y => \GND\);
    
    m82_i_m2_i_m2_1_2 : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(15), B => 
        FOC_TRANSFORMS_0_id_o(15), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        m82_i_m2_i_m2_1_2_Z);
    
    rate_limit_ref_in_o_1_sqmuxa_0_a2_1_a2_0_a2 : CFG4
      generic map(INIT => x"0800")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => N_2262, D => 
        N_2655, Y => rate_limit_ref_in_o_1_sqmuxa);
    
    \adc_scale_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(3));
    
    \speed_pi_ki_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(13));
    
    prdata_m2_e_1_N_3L3 : CFG4
      generic map(INIT => x"0CA0")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(3), B => 
        FOC_TRANSFORMS_0_vbeta_o(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        prdata_m2_e_1_N_3L3_Z);
    
    \adc_channel_ch1_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(0));
    
    seq_cntl_config_o_1_sqmuxa_0_a2_0_a2_0 : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => \N_549\);
    
    \seq_cntl_cl_omega_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_cl_omega_o(6));
    
    \speed_pi_kp_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(16));
    
    \prdata_o_1_4_i_m2[4]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(4), Y => N_1165);
    
    \prdata_o_1_0_3_RNO[12]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(12), B => 
        ADC_SCALING_1_ia_adc_o(12), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(12), Y => N_1337);
    
    \prdata_o_1_15_i_m2[4]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(4), B => 
        BLDC_ESTIMATOR_1_ealpha_o(4), C => 
        prdata_o_1_15_i_m2_1_1(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_1347);
    
    \olmng_dv_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(10));
    
    \adc_oc_thresh_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(3));
    
    \adc_oc_thresh_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(14));
    
    \olmng_iq_ref_in_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(14));
    
    \angle_kp_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(9));
    
    \idq_pi_ki_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_idq_pi_ki_o_0(0));
    
    \pwm_gain_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(6));
    
    \rate_limit_slew_cnt_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(2));
    
    \prdata_o_1_10_i_m2_i_m2[10]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        FOC_TRANSFORMS_0_vbeta_o(10), Y => N_788);
    
    \pwm_dead_time_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(3));
    
    \Rs_pu_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(7));
    
    \rate_limit_slew_cnt_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(1));
    
    \pwm_gain_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(5));
    
    olmng_theta_factor_o_1_sqmuxa_0_a2_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_2649, B => N_2663, C => N_2648, Y => 
        olmng_theta_factor_o_1_sqmuxa);
    
    \olmng_theta_factor_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(9));
    
    \speed_pi_ki_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(5));
    
    \rate_limit_ref_in_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(10));
    
    pwm_dead_time_val_o_1_sqmuxa_0_a2_1_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_2650, B => N_2663, C => N_2628, Y => 
        pwm_dead_time_val_o_1_sqmuxa);
    
    \prdata_o_1_2_0_a2_13_RNIIQQA3[1]\ : CFG4
      generic map(INIT => x"BA30")

      port map(A => m40_i_0_a2_6_0, B => N_2152, C => \N_2652\, D
         => N_542, Y => m40_i_0_0);
    
    \olmng_theta_factor_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(3));
    
    \prdata_o_1_15_i_m2[2]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(2), B => 
        BLDC_ESTIMATOR_1_ealpha_o(2), C => 
        prdata_o_1_15_i_m2_1_1(2), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_1345);
    
    \prdata_o_1_17_i_m2_i_m2_ns[7]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_i_m2_am(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_i_m2_bm(7), Y => N_882);
    
    \prdata_o_1_0_0_RNO_0[16]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_0_0_RNO_1(16), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_0_0_RNO_2(16), Y => N_65_0);
    
    \angle_kp_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(15));
    
    \prdata_o_1_13_i_m2_i_m2_i_m2_1_1[10]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(10), B
         => adc_measurements_0_adc_result_ch2_o(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_i_m2_1_1(10));
    
    \prdata_o_1_0_1_RNO_0[16]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(16), B => 
        FOC_TRANSFORMS_0_id_o(16), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(16));
    
    \prdata_o_1_0_0_RNO_0[13]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(13), B => 
        OLMNG_1_theta_o(13), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_i_m2_1_1(13));
    
    \angle_ki_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(17));
    
    \prdata_o_1_2_0_0_1_cZ[2]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_1327, B => N_795, C => \N_2639\, D => 
        \N_2644\, Y => prdata_o_1_2_0_0_1(2));
    
    \idq_pi_kp_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(0));
    
    direction_config_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"0080")

      port map(A => N_2648, B => N_2649, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => N_2262, Y => 
        direction_config_o_1_sqmuxa);
    
    \adc_channel_ch1_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(15));
    
    \Rs_pu_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(3));
    
    \pwm_period_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(3));
    
    \prdata_o_1_3_0_0_2_RNO[11]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(11), B => 
        BLDC_ESTIMATOR_1_ealpha_o(11), C => 
        prdata_o_1_15_i_m2_i_m2_1_1(11), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_852);
    
    \speed_pi_kp_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(5));
    
    \prdata_o_1_14_i_m2_i_m2[5]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(5), B => 
        ADC_SCALING_1_ia_adc_o(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_i_m2_1_1(5), Y => N_769);
    
    \speed_pi_ki_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(8));
    
    \prdata_o_1_10_i_m2[4]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        FOC_TRANSFORMS_0_vbeta_o(4), Y => N_1275);
    
    \olmng_dv_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(11));
    
    \pwm_delay_time_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(3));
    
    \prdata_o_1_14_i_m2_1_1[17]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(17), B => 
        FOC_TRANSFORMS_0_id_o(17), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_1_1(17));
    
    \speed_pi_ki_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(16));
    
    \prdata_o_1_16_i_m2_i_m2_bm[7]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(7), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(7));
    
    \prdata_o_1_14_i_m2_i_m2_1_1[7]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(7), B => 
        FOC_TRANSFORMS_0_id_o(7), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_i_m2_1_1(7));
    
    \angle_kp_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(10));
    
    \pwm_delay_time_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(14));
    
    \adc_oc_thresh_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(11));
    
    \prdata_o_1_16_i_m2_i_m2_i_m2_bm[1]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(1), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(1), Y => 
        prdata_o_1_16_i_m2_i_m2_i_m2_bm(1));
    
    \pwm_period_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(8));
    
    \prdata_o_1_15_i_m2_i_m2_1_1[10]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(10), B => 
        OLMNG_1_theta_o(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_i_m2_1_1(10));
    
    \idq_pi_kp_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(2));
    
    \prdata_o_1_2_0_a2_10_RNITK111[1]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(14), B => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(14), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => \N_2645\, Y => 
        N_2548);
    
    \prdata_o_1_13_i_m2_i_m2_1_1[1]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(1), B => 
        adc_measurements_0_adc_result_ch2_o(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_1_1(1));
    
    \olmng_dv_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(17));
    
    \adc_oc_thresh_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(8));
    
    \prdata_o_1_16_i_m2_i_m2_i_m2_am[10]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(10), Y => 
        prdata_o_1_16_i_m2_i_m2_i_m2_am(10));
    
    \Rs_pu_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(15));
    
    \pwm_period_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(12));
    
    \prdata_o_1_2_0_0_RNO_0[2]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(2), B => 
        adc_measurements_0_adc_result_ch2_o(2), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_1_1(2));
    
    \pwm_dead_time_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(12));
    
    \prdata_o_1_14_i_m2_i_m2_1_1[9]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(9), B => 
        FOC_TRANSFORMS_0_id_o(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_i_m2_1_1(9));
    
    \pwm_period_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(2));
    
    \rate_limit_slew_cnt_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(4));
    
    \adc_channel_ch1_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(9));
    
    \angle_kp_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(7));
    
    \prdata_o_1_16_i_m2_i_m2_ns[9]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_am(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_bm(9), Y => N_775);
    
    \prdata_o_1_16_i_m2_i_m2_i_m2_ns[10]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_i_m2_i_m2_am(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_i_m2_i_m2_bm(10), Y => N_893);
    
    \adc_oc_thresh_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(17));
    
    \rate_limit_rate_cnt_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(9));
    
    \seq_cntl_config_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_seq_cntl_config_o(0));
    
    \prdata_o_1_2_0_4_2_RNO_0[3]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(3), B => 
        adc_measurements_0_adc_result_ch2_o(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_1_1(3));
    
    \angle_ki_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(1));
    
    pwm_gain_val_o_1_sqmuxa_0_a2_1_a2_1_a2 : CFG4
      generic map(INIT => x"0100")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => N_2262, D => 
        N_2655, Y => pwm_gain_val_o_1_sqmuxa);
    
    \prdata_o_1_4_i_m2[8]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(8), Y => N_1169);
    
    \prdata_o_1_16_i_m2_bm[12]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(12), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(12), Y => 
        prdata_o_1_16_i_m2_bm(12));
    
    prdata_m1_e_0_1_c : CFG4
      generic map(INIT => x"0004")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => \prdata_m1_e_0_1\);
    
    \prdata_o_1_17_i_m2_i_m2_bm[2]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => net_189(2), Y => 
        prdata_o_1_17_i_m2_i_m2_bm(2));
    
    \pwm_period_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(13));
    
    \adc_control_reg_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_control_reg_val_o(0));
    
    \Ls_by_Ts_pu_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(14));
    
    \speed_pi_kp_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(11));
    
    \adc_oc_thresh_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(10));
    
    \prdata_o_1_16_i_m2_i_m2_bm[5]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(5), Y => 
        prdata_o_1_16_i_m2_i_m2_bm(5));
    
    \prdata_o_1_2_0_a2_13[1]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), C => N_2628, D => 
        N_1400, Y => \N_2652\);
    
    seq_cntl_cl_omega_o_1_sqmuxa_0_a2_0_a2_0_a2_2 : CFG4
      generic map(INIT => x"0200")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), D => \N_240\, Y => 
        N_2648);
    
    \prdata_o_1_0_3[12]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => \N_2644\, B => N_1337, C => N_2617, D => 
        prdata_o_1_0_0(12), Y => prdata_o_1_0_3(12));
    
    olmng_iq_ref_in_o_1_sqmuxa_0_a2_3_a2_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => N_544, 
        C => N_2648, D => N_2650, Y => olmng_iq_ref_in_o_1_sqmuxa);
    
    \olmng_iq_ref_in_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(12));
    
    \prdata_o_1_8_0_cZ[6]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_57, B => N_1319, C => \N_2640\, D => 
        \N_2652\, Y => prdata_o_1_8_0(6));
    
    m67_i_m2_i_m2_am : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(15), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(15), Y => m67_i_m2_i_m2_am_Z);
    
    \prdata_o_1_15_i_m2_1_1[8]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(8), B => 
        OLMNG_1_theta_o(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_1_1(8));
    
    m73_i_m2_i_m2_ns : CFG3
      generic map(INIT => x"E2")

      port map(A => m73_i_m2_i_m2_am_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        m73_i_m2_i_m2_bm_Z, Y => N_828);
    
    \prdata_o_1_14_i_m2_i_m2[10]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(10), B => 
        ADC_SCALING_1_ia_adc_o(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_i_m2_1_1(10), Y => N_790);
    
    \prdata_o_1_2_0_o2_1[1]\ : CFG4
      generic map(INIT => x"0810")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => N_1400);
    
    \prdata_o_1_2_0_a2_9_RNI43QQ7[1]\ : CFG4
      generic map(INIT => x"FFF2")

      port map(A => \N_2644\, B => N_825, C => N_2557, D => 
        m19_0_0_0, Y => m19_0_0_3);
    
    \adc_channel_ch1_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(13));
    
    adc_scale_val_o_1_sqmuxa_0_a2_1_a2_1_a2 : CFG4
      generic map(INIT => x"0008")

      port map(A => N_2628, B => N_2650, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => N_2262, Y => 
        adc_scale_val_o_1_sqmuxa);
    
    \adc_oc_thresh_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_oc_thresh_o(6));
    
    \prdata_o_1_14_i_m2[17]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(17), B => 
        ADC_SCALING_1_ia_adc_o(17), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(17), Y => N_1342);
    
    \pwm_period_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(11));
    
    \speed_pi_kp_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(4));
    
    \angle_ki_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(8));
    
    \prdata_o_1_0_0[16]\ : CFG4
      generic map(INIT => x"BA30")

      port map(A => N_1359, B => N_65_0, C => \N_2640\, D => 
        \N_2647\, Y => prdata_o_1_0_0_4);
    
    \prdata_o_1_0_0_RNO_1[16]\ : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(16), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(16), Y => 
        prdata_o_1_0_0_RNO_1(16));
    
    \rate_limit_ref_in_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(3));
    
    \adc_channel_ch0_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(9));
    
    \speed_pi_kp_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(2));
    
    start_motor_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        \N_549\, C => N_2648, D => N_2649, Y => 
        start_motor_o_1_sqmuxa);
    
    \rate_limit_slew_cnt_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(14));
    
    \prdata_o_1_0_0_RNO_1[13]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(13), B => 
        FOC_TRANSFORMS_0_id_o(13), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_i_m2_1_1(13));
    
    \adc_scale_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(10));
    
    \pwm_dead_time_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_dead_time_val_o(17));
    
    prdata_o_1_2_0_a2_10_N_2L1 : CFG4
      generic map(INIT => x"0008")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => 
        prdata_o_1_2_0_a2_10_N_2L1_Z);
    
    \speed_pi_ki_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_ki_o(11));
    
    \prdata_o_1_2_0_a2_11_0_1[1]\ : CFG3
      generic map(INIT => x"54")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_2_0_a2_11_0_1(1));
    
    \rate_limit_slew_cnt_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_slew_cnt_o(11));
    
    \olmng_dv_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(1));
    
    \prdata_o_1_17_i_m2_i_m2_am[13]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(13), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(13), Y => 
        prdata_o_1_17_i_m2_i_m2_am(13));
    
    \prdata_o_1_4_i_m2_i_m2[9]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(9), Y => N_750);
    
    \idq_pi_kp_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_0_idq_pi_kp_o(15));
    
    \angle_ki_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(4));
    
    \prdata_o_1_13_i_m2_i_m2[5]\ : CFG4
      generic map(INIT => x"C0AF")

      port map(A => adc_interface_0_result_ch1_o(5), B => 
        adc_interface_0_result_ch0_o(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        prdata_o_1_13_i_m2_i_m2_1_1(5), Y => N_767);
    
    \prdata_o_1_14_i_m2_i_m2_1_1[14]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => FOC_TRANSFORMS_0_iq_o(14), B => 
        FOC_TRANSFORMS_0_id_o(14), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_14_i_m2_i_m2_1_1(14));
    
    \olmng_dv_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(14));
    
    \prdata_o_1_17_i_m2_i_m2_am[7]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(7), Y => 
        prdata_o_1_17_i_m2_i_m2_am(7));
    
    \rate_limit_ref_in_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(6));
    
    \pwm_delay_time_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(16));
    
    \prdata_o_1_4_i_m2_i_m2[10]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(10), Y => N_782);
    
    \speed_pi_kp_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_speed_pi_kp_o(0));
    
    \angle_kp_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_kp_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_kp_o(3));
    
    \prdata_o_1_2_0_a2_10_RNIVM111[1]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(15), B => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(15), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => \N_2645\, Y => 
        N_2554);
    
    \angle_ki_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => angle_ki_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_angle_ki_o(2));
    
    \prdata_o_1_15_i_m2_i_m2[9]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(9), B => 
        BLDC_ESTIMATOR_1_ealpha_o(9), C => 
        prdata_o_1_15_i_m2_i_m2_1_1(9), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_773);
    
    m73_i_m2_i_m2_bm : CFG3
      generic map(INIT => x"47")

      port map(A => BLDC_ESTIMATOR_1_ebeta_filtered_o(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        BLDC_ESTIMATOR_1_ebeta_o(0), Y => m73_i_m2_i_m2_bm_Z);
    
    auto_restart_no_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        \N_549\, C => N_2648, D => N_2650, Y => 
        auto_restart_no_o_1_sqmuxa);
    
    \prdata_o_1_2_0_a2_10[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_2_0_a2_17_0\(1), B => \N_2627\, C
         => prdata_o_1_2_0_a2_10_N_2L1_Z, D => 
        prdata_o_1_2_0_a2_10_N_3L3_Z, Y => \N_2645\);
    
    \prdata_o_1_8_a2_5[6]\ : CFG4
      generic map(INIT => x"AC00")

      port map(A => FOC_TRANSFORMS_0_ibeta_o(6), B => 
        FOC_TRANSFORMS_0_ialpha_o(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => \N_2639\, Y => 
        N_2611);
    
    \prdata_o_1_16_i_m2_i_m2_am[13]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(13), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(13), Y => 
        prdata_o_1_16_i_m2_i_m2_am(13));
    
    \prdata_o_1_17_i_m2_ns[16]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_17_i_m2_am(16), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_17_i_m2_bm(16), Y => N_1395);
    
    \pwm_period_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(14));
    
    \filter_factor_omega_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        filter_factor_omega_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_filter_factor_omega_o(0));
    
    \pwm_delay_time_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_delay_time_val_o(9));
    
    \adc_scale_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(12));
    
    \prdata_o_1_14_i_m2[1]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(1), B => 
        ADC_SCALING_1_ia_adc_o(1), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(1), Y => N_1326);
    
    \prdata_o_1_15_i_m2_i_m2_1_1[7]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(7), B => 
        OLMNG_1_theta_o(7), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_i_m2_1_1(7));
    
    \olmng_theta_factor_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_theta_factor_o(2));
    
    \prdata_o_1_4_i_m2[16]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(16), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        FOC_TRANSFORMS_0_ibeta_o(16), Y => N_1177);
    
    \pwm_period_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(9));
    
    \pwm_period_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(5));
    
    \prdata_o_1_14_i_m2[8]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(8), B => 
        ADC_SCALING_1_ia_adc_o(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_1_1(8), Y => N_1333);
    
    \prdata_o_1_14_i_m2_i_m2[9]\ : CFG4
      generic map(INIT => x"0CFA")

      port map(A => ADC_SCALING_1_ib_adc_o(9), B => 
        ADC_SCALING_1_ia_adc_o(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        prdata_o_1_14_i_m2_i_m2_1_1(9), Y => N_770);
    
    \adc_channel_ch3_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(10));
    
    \prdata_o_1_15_i_m2_1_1[2]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(2), B => 
        OLMNG_1_theta_o(2), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_1_1(2));
    
    \prdata_o_1_2_0_a2_11_RNI3UQ6B[1]\ : CFG4
      generic map(INIT => x"FFF4")

      port map(A => N_833, B => \N_2646\, C => N_2548, D => 
        m26_0_0_3, Y => MC_System_0_AMBA_SLAVE_0_PRDATA_14);
    
    \rate_limit_ref_in_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_ref_in_o(14));
    
    \prdata_o_1_17_i_m2_i_m2_am[5]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_1_ealpha_filtered_o(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(5), Y => 
        prdata_o_1_17_i_m2_i_m2_am(5));
    
    \prdata_o_1_16_i_m2_i_m2_am[7]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(7), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        FOC_TRANSFORMS_0_valpha_o(7), Y => 
        prdata_o_1_16_i_m2_i_m2_am(7));
    
    \Ls_by_Ts_pu_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => Ls_by_Ts_pu_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_Ls_by_Ts_pu_o(10));
    
    \Rs_pu_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(13));
    
    \adc_channel_ch3_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(9));
    
    m55_i_m2_i_m2_ns : CFG3
      generic map(INIT => x"E2")

      port map(A => m55_i_m2_i_m2_am_Z, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        m55_i_m2_i_m2_bm_Z, Y => N_833);
    
    \adc_scale_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_scale_val_o(15));
    
    \adc_channel_ch0_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch0_o(10));
    
    \prdata_o_1_13_i_m2_i_m2_1_1[5]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(5), B => 
        adc_measurements_0_adc_result_ch2_o(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_1_1(5));
    
    \olmng_iq_ref_in_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_olmng_iq_ref_in_o(7));
    
    \Rs_pu_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => Rs_pu_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_Rs_pu_o(16));
    
    \prdata_o_1_0_0_0[13]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_854, B => N_853, C => \N_2647\, D => 
        \N_2640\, Y => prdata_o_1_0_0_0(13));
    
    \prdata_o_1_15_i_m2_1_1[4]\ : CFG4
      generic map(INIT => x"503F")

      port map(A => BLDC_ESTIMATOR_1_theta_o(4), B => 
        OLMNG_1_theta_o(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_15_i_m2_1_1(4));
    
    prdata_o_1_2_0_a2_10_N_3L3 : CFG2
      generic map(INIT => x"6")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        prdata_o_1_2_0_a2_10_N_3L3_Z);
    
    \adc_channel_ch3_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch3_o(6));
    
    m73_i_m2_i_m2_am : CFG3
      generic map(INIT => x"53")

      port map(A => BLDC_ESTIMATOR_0_speed_filtered_o(0), B => 
        FOC_TRANSFORMS_0_valpha_o(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        m73_i_m2_i_m2_am_Z);
    
    \prdata_o_1_10_i_m2_i_m2[5]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => BLDC_ESTIMATOR_1_pll_pi_out_o(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), C => 
        FOC_TRANSFORMS_0_vbeta_o(5), Y => N_762);
    
    \prdata_o_1_13_i_m2_i_m2_1_1[4]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => adc_measurements_0_adc_result_ch3_o(4), B => 
        adc_measurements_0_adc_result_ch2_o(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_13_i_m2_i_m2_1_1(4));
    
    \pwm_period_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_period_val_o(0));
    
    \prdata_o_1_0_a2_4_0[17]\ : CFG4
      generic map(INIT => x"0C0A")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(17), B => 
        FOC_TRANSFORMS_0_ibeta_o(17), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_a2_4_0(17));
    
    \pwm_gain_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_pwm_gain_val_o(13));
    
    \prdata_o_1_15_i_m2_i_m2[7]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(7), B => 
        BLDC_ESTIMATOR_1_ealpha_o(7), C => 
        prdata_o_1_15_i_m2_i_m2_1_1(7), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_878);
    
    \prdata_o_1_15_i_m2[17]\ : CFG4
      generic map(INIT => x"0FAC")

      port map(A => RATE_LIMITER_0_rl_out_o(17), B => 
        BLDC_ESTIMATOR_1_ealpha_o(17), C => 
        prdata_o_1_15_i_m2_1_1(17), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_1360);
    
    \prdata_o_1_16_i_m2_ns[12]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => prdata_o_1_16_i_m2_am(12), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => 
        prdata_o_1_16_i_m2_bm(12), Y => N_1373);
    
    \adc_channel_ch1_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_0_adc_channel_ch1_o(2));
    
    \olmng_dv_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_if_0_olmng_dv_o(3));
    
    \rate_limit_rate_cnt_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_0_rate_limit_rate_cnt_o(12));
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity Bldc_Axis is

    port( SEQ_CONTROLLER_1_state_o_1         : out   std_logic;
          SEQ_CONTROLLER_1_state_o_3         : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWDATA    : in    std_logic_vector(17 downto 0);
          prdata_o_1_2_0_a2_17_0             : out   std_logic_vector(1 to 1);
          prdata_o_1_2_0_a2_11_0             : out   std_logic_vector(1 to 1);
          MC_System_0_AMBA_SLAVE_1_PADDR     : in    std_logic_vector(11 downto 0);
          prdata_o_1_2_0_a2_12_0             : out   std_logic_vector(1 to 1);
          prdata_o_1_2_0_0_1                 : out   std_logic_vector(2 to 2);
          prdata_o_1_0_1                     : out   std_logic_vector(16 to 16);
          prdata_o_1_0_0                     : out   std_logic_vector(16 to 16);
          prdata_o_1_2_0_0_5                 : out   std_logic_vector(3 to 3);
          prdata_o_1_2_0_0_2                 : out   std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_0                 : out   std_logic_vector(2 to 2);
          prdata_o_1_3_0_0_3                 : out   std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_2                 : out   std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_0                 : out   std_logic_vector(11 to 11);
          prdata_o_1_8_3                     : out   std_logic_vector(6 to 6);
          prdata_o_1_8_2                     : out   std_logic_vector(6 to 6);
          prdata_o_1_8_0                     : out   std_logic_vector(6 to 6);
          prdata_o_1_0_2                     : out   std_logic_vector(16 to 16);
          prdata_o_1_2_0_0_4_2               : out   std_logic_vector(3 to 3);
          MC_System_0_AMBA_SLAVE_0_PRDATA_12 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_13 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_15 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_14 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_0  : out   std_logic;
          MC_System_0_FIC_0_LOCK             : in    std_logic;
          MC_System_0_FIC_0_CLK              : in    std_logic;
          A0_PWM_VL_O_c                      : out   std_logic;
          A0_PWM_UH_O_c                      : out   std_logic;
          A0_PWM_VH_O_c                      : out   std_logic;
          A0_PWM_WH_O_c                      : out   std_logic;
          A0_ADC_SDI_I_c                     : in    std_logic;
          A0_ADC_SDO_O_c                     : out   std_logic;
          A0_ADC_CS_O_c                      : out   std_logic;
          A0_ADC_SCK_O_c                     : out   std_logic;
          N_2627                             : out   std_logic;
          N_2574                             : out   std_logic;
          prdata_m2_e_1_1                    : out   std_logic;
          N_2645                             : out   std_logic;
          N_739                              : out   std_logic;
          N_766                              : out   std_logic;
          N_768                              : out   std_logic;
          N_769                              : out   std_logic;
          N_1345                             : out   std_logic;
          N_767                              : out   std_logic;
          N_875                              : out   std_logic;
          N_770                              : out   std_logic;
          N_771                              : out   std_logic;
          N_772                              : out   std_logic;
          N_876                              : out   std_logic;
          N_773                              : out   std_logic;
          N_1333                             : out   std_logic;
          N_1347                             : out   std_logic;
          N_1351                             : out   std_logic;
          N_1326                             : out   std_logic;
          N_1346                             : out   std_logic;
          N_878                              : out   std_logic;
          N_789                              : out   std_logic;
          N_791                              : out   std_logic;
          N_1329                             : out   std_logic;
          N_1342                             : out   std_logic;
          N_790                              : out   std_logic;
          N_891                              : out   std_logic;
          N_1360                             : out   std_logic;
          N_1378                             : out   std_logic;
          N_1396                             : out   std_logic;
          N_774                              : out   std_logic;
          N_775                              : out   std_logic;
          N_776                              : out   std_logic;
          N_777                              : out   std_logic;
          N_792                              : out   std_logic;
          N_793                              : out   std_logic;
          N_832                              : out   std_logic;
          N_880                              : out   std_logic;
          N_882                              : out   std_logic;
          N_883                              : out   std_logic;
          N_892                              : out   std_logic;
          N_893                              : out   std_logic;
          N_894                              : out   std_logic;
          N_895                              : out   std_logic;
          N_738                              : out   std_logic;
          N_502                              : out   std_logic;
          N_240                              : out   std_logic;
          N_549                              : out   std_logic;
          N_870                              : out   std_logic;
          N_859                              : out   std_logic;
          N_788                              : out   std_logic;
          N_782                              : out   std_logic;
          N_763                              : out   std_logic;
          N_762                              : out   std_logic;
          N_750                              : out   std_logic;
          N_749                              : out   std_logic;
          N_1288                             : out   std_logic;
          N_1279                             : out   std_logic;
          N_1275                             : out   std_logic;
          N_1169                             : out   std_logic;
          N_1165                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE    : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PENABLE   : in    std_logic;
          prdata_m1_e_0_1                    : out   std_logic;
          N_2631                             : out   std_logic;
          N_1398                             : out   std_logic;
          N_519                              : in    std_logic;
          N_540                              : in    std_logic;
          N_2644                             : out   std_logic;
          N_2639                             : out   std_logic;
          N_2647                             : out   std_logic;
          N_2640                             : out   std_logic;
          N_2598                             : out   std_logic;
          N_2646                             : out   std_logic;
          N_2652                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx     : in    std_logic;
          N_2495                             : out   std_logic;
          N_2498                             : out   std_logic;
          N_2531                             : out   std_logic;
          N_542                              : in    std_logic;
          N_544                              : in    std_logic
        );

end Bldc_Axis;

architecture DEF_ARCH of Bldc_Axis is 

  component SPEED_ID_IQ_PI_0
    port( reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          clear_buffer_i       : in    std_logic := 'U';
          speed_en_i           : in    std_logic := 'U';
          idq_en_i             : in    std_logic := 'U';
          speed_pi_start_i     : in    std_logic := 'U';
          id_pi_start_i        : in    std_logic := 'U';
          iq_pi_start_i        : in    std_logic := 'U';
          speed_init_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_init_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_init_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ref_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ymax_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ymin_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_ref_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_act_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_kp_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_ki_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          idq_pi_ymax_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          idq_pi_ymin_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_ref_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_done_o      : out   std_logic;
          id_pi_done_o         : out   std_logic;
          iq_pi_done_o         : out   std_logic;
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0)
        );
  end component;

  component SVM
    port( reset_i   : in    std_logic := 'U';
          sys_clk_i : in    std_logic := 'U';
          start_i   : in    std_logic := 'U';
          va_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          vb_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          vc_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          va3h_o    : out   std_logic_vector(17 downto 0);
          vb3h_o    : out   std_logic_vector(17 downto 0);
          vc3h_o    : out   std_logic_vector(17 downto 0);
          done_o    : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component PWM3PH_0
    port( reset_i        : in    std_logic := 'U';
          sys_clk_i      : in    std_logic := 'U';
          en_pwm_i       : in    std_logic := 'U';
          en_dual_trig_i : in    std_logic := 'U';
          va_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          vb_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          vc_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_period_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          dead_time_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          delay_time_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          midmatch_o     : out   std_logic;
          PWM_AH_o       : out   std_logic;
          PWM_BH_o       : out   std_logic;
          PWM_CH_o       : out   std_logic;
          PWM_AL_o       : out   std_logic;
          PWM_BL_o       : out   std_logic;
          PWM_CL_o       : out   std_logic
        );
  end component;

  component OLMNG
    port( reset_i            : in    std_logic := 'U';
          sys_clk_i          : in    std_logic := 'U';
          start_i            : in    std_logic := 'U';
          clear_buffer_i     : in    std_logic := 'U';
          direction_config_i : in    std_logic := 'U';
          cl_status_i        : in    std_logic := 'U';
          theta_factor_i     : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_ref_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          dv_i               : in    std_logic_vector(17 downto 0) := (others => 'U');
          theta_cl_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_ref_in_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          done_o             : out   std_logic;
          theta_o            : out   std_logic_vector(17 downto 0);
          init_speedpi_o     : out   std_logic_vector(17 downto 0);
          init_iqpi_o        : out   std_logic_vector(17 downto 0)
        );
  end component;

  component RATE_LIMITER
    port( reset_i      : in    std_logic := 'U';
          sys_clk_i    : in    std_logic := 'U';
          start_i      : in    std_logic := 'U';
          soft_stop_i  : in    std_logic := 'U';
          reset_rl_i   : in    std_logic := 'U';
          direction_i  : in    std_logic := 'U';
          slew_count_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          rate_count_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          rl_in_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          rl_out_o     : out   std_logic_vector(17 downto 0);
          rl_done_o    : out   std_logic
        );
  end component;

  component BLDC_ESTIMATOR
    port( reset_i                : in    std_logic := 'U';
          sys_clk_i              : in    std_logic := 'U';
          start_i                : in    std_logic := 'U';
          angle_pi_en_i          : in    std_logic := 'U';
          v_alpha_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          v_beta_i               : in    std_logic_vector(17 downto 0) := (others => 'U');
          i_alpha_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          i_beta_i               : in    std_logic_vector(17 downto 0) := (others => 'U');
          Ls_by_Ts_pu_i          : in    std_logic_vector(17 downto 0) := (others => 'U');
          Rs_pu_i                : in    std_logic_vector(17 downto 0) := (others => 'U');
          ealpha_filter_factor_i : in    std_logic_vector(3 downto 0) := (others => 'U');
          ebeta_filter_factor_i  : in    std_logic_vector(3 downto 0) := (others => 'U');
          pll_theta_factor_i     : in    std_logic_vector(17 downto 0) := (others => 'U');
          angle_pi_ki_i          : in    std_logic_vector(17 downto 0) := (others => 'U');
          angle_pi_kp_i          : in    std_logic_vector(17 downto 0) := (others => 'U');
          omega_filter_factor_i  : in    std_logic_vector(3 downto 0) := (others => 'U');
          done_o                 : out   std_logic;
          theta_o                : out   std_logic_vector(17 downto 0);
          ealpha_o               : out   std_logic_vector(17 downto 0);
          ebeta_o                : out   std_logic_vector(17 downto 0);
          ealpha_filtered_o      : out   std_logic_vector(17 downto 0);
          ebeta_filtered_o       : out   std_logic_vector(17 downto 0);
          pll_pi_out_o           : out   std_logic_vector(17 downto 0);
          speed_filtered_o       : out   std_logic_vector(17 downto 0)
        );
  end component;

  component SEQ_CONTROLLER_0
    port( reset_i         : in    std_logic := 'U';
          sys_clk_i       : in    std_logic := 'U';
          fault_i         : in    std_logic := 'U';
          start_motor_i   : in    std_logic := 'U';
          stop_motor_i    : in    std_logic := 'U';
          fault_clear_i   : in    std_logic := 'U';
          speed_ref_i     : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_cl_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          vq_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          max_ar_i        : in    std_logic_vector(3 downto 0) := (others => 'U');
          calib_done_i    : in    std_logic := 'U';
          pwm_midmatch_i  : in    std_logic := 'U';
          foc_done_i      : in    std_logic := 'U';
          config_reg_i    : in    std_logic_vector(3 downto 0) := (others => 'U');
          adc_start_o     : out   std_logic;
          cl_status_o     : out   std_logic;
          en_idq_pi_o     : out   std_logic;
          en_pwm_o        : out   std_logic;
          motor_stopped_o : out   std_logic;
          reset_rl_o      : out   std_logic;
          soft_stop_o     : out   std_logic;
          sensor_reset_o  : out   std_logic;
          state_o         : out   std_logic_vector(3 downto 0)
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component FOC_TRANSFORMS_0
    port( reset_i         : in    std_logic := 'U';
          sys_clk_i       : in    std_logic := 'U';
          start_clarke_i  : in    std_logic := 'U';
          start_park_i    : in    std_logic := 'U';
          start_ipark_i   : in    std_logic := 'U';
          start_iclarke_i : in    std_logic := 'U';
          ia_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          ib_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          ialpha_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          ibeta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vd_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          vq_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          valpha_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          vbeta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          theta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          clarke_done_o   : out   std_logic;
          park_done_o     : out   std_logic;
          ipark_done_o    : out   std_logic;
          iclarke_done_o  : out   std_logic;
          ialpha_o        : out   std_logic_vector(17 downto 0);
          ibeta_o         : out   std_logic_vector(17 downto 0);
          id_o            : out   std_logic_vector(17 downto 0);
          iq_o            : out   std_logic_vector(17 downto 0);
          valpha_o        : out   std_logic_vector(17 downto 0);
          vbeta_o         : out   std_logic_vector(17 downto 0);
          va_o            : out   std_logic_vector(17 downto 0);
          vb_o            : out   std_logic_vector(17 downto 0);
          vc_o            : out   std_logic_vector(17 downto 0)
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component adc_interface_0
    port( apb3_if_0_adc_control_reg_val_o     : in    std_logic_vector(5 downto 0) := (others => 'U');
          adc_interface_0_result_ch0_o        : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch1_o        : out   std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch2_o : out   std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch3_o : out   std_logic_vector(11 downto 0);
          apb3_if_0_adc_channel_ch2_o         : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_if_0_adc_channel_ch0_o         : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_if_0_adc_channel_ch1_o         : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_if_0_adc_channel_ch3_o         : in    std_logic_vector(15 downto 0) := (others => 'U');
          MC_System_0_FIC_0_LOCK              : in    std_logic := 'U';
          MC_System_0_FIC_0_CLK               : in    std_logic := 'U';
          SEQ_CONTROLLER_1_adc_start_o        : in    std_logic := 'U';
          A0_ADC_SDI_I_c                      : in    std_logic := 'U';
          A0_ADC_SDO_O_c                      : out   std_logic;
          A0_ADC_CS_O_c                       : out   std_logic;
          A0_ADC_SCK_O_c                      : out   std_logic;
          adc_interface_0_results_rdy_o       : out   std_logic
        );
  end component;

  component PWM_SCALING_0
    port( reset_i      : in    std_logic := 'U';
          sys_clk_i    : in    std_logic := 'U';
          start_i      : in    std_logic := 'U';
          va_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vb_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vc_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_period_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_gain_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          Va_o         : out   std_logic_vector(17 downto 0);
          Vb_o         : out   std_logic_vector(17 downto 0);
          Vc_o         : out   std_logic_vector(17 downto 0);
          done_o       : out   std_logic
        );
  end component;

  component ADC_SCALING_0
    port( reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          adc_results_rdy_i    : in    std_logic := 'U';
          adc_scale_val_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          adc_result_ch0_i     : in    std_logic_vector(11 downto 0) := (others => 'U');
          adc_result_ch1_i     : in    std_logic_vector(11 downto 0) := (others => 'U');
          fault_threshold_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          done_o               : out   std_logic;
          calib_done_o         : out   std_logic;
          over_current_fault_o : out   std_logic;
          ia_adc_o             : out   std_logic_vector(17 downto 0);
          ib_adc_o             : out   std_logic_vector(17 downto 0)
        );
  end component;

  component apb3_if
    port( apb3_if_0_idq_pi_ki_o_0             : out   std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_1_PWDATA     : in    std_logic_vector(17 downto 0) := (others => 'U');
          apb3_if_0_idq_pi_kp_o               : out   std_logic_vector(17 downto 0);
          apb3_if_0_olmng_dv_o                : out   std_logic_vector(17 downto 0);
          apb3_if_0_olmng_iq_ref_in_o         : out   std_logic_vector(17 downto 0);
          apb3_if_0_olmng_theta_factor_o      : out   std_logic_vector(17 downto 0);
          apb3_if_0_pwm_dead_time_val_o       : out   std_logic_vector(17 downto 0);
          apb3_if_0_pwm_delay_time_val_o      : out   std_logic_vector(17 downto 0);
          apb3_if_0_pwm_gain_val_o            : out   std_logic_vector(17 downto 1);
          apb3_if_0_pwm_period_val_o          : out   std_logic_vector(17 downto 0);
          apb3_if_0_rate_limit_rate_cnt_o     : out   std_logic_vector(17 downto 0);
          apb3_if_0_rate_limit_ref_in_o       : out   std_logic_vector(17 downto 0);
          apb3_if_0_rate_limit_slew_cnt_o     : out   std_logic_vector(17 downto 0);
          apb3_if_0_seq_cntl_cl_omega_o       : out   std_logic_vector(17 downto 0);
          apb3_if_0_speed_pi_ki_o             : out   std_logic_vector(17 downto 0);
          apb3_if_0_filter_factor_bemf_o      : out   std_logic_vector(3 downto 0);
          apb3_if_0_auto_restart_no_o         : out   std_logic_vector(3 downto 0);
          apb3_if_0_speed_pi_kp_o             : out   std_logic_vector(17 downto 0);
          apb3_if_0_adc_control_reg_val_o     : out   std_logic_vector(5 downto 0);
          apb3_if_0_seq_cntl_config_o         : out   std_logic_vector(3 downto 0);
          apb3_if_0_filter_factor_omega_o     : out   std_logic_vector(3 downto 0);
          apb3_if_0_adc_channel_ch0_o         : out   std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch1_o         : out   std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch2_o         : out   std_logic_vector(15 downto 0);
          apb3_if_0_adc_channel_ch3_o         : out   std_logic_vector(15 downto 0);
          apb3_if_0_Ls_by_Ts_pu_o             : out   std_logic_vector(17 downto 0);
          apb3_if_0_Rs_pu_o                   : out   std_logic_vector(17 downto 0);
          apb3_if_0_adc_oc_thresh_o           : out   std_logic_vector(17 downto 0);
          apb3_if_0_adc_scale_val_o           : out   std_logic_vector(17 downto 0);
          apb3_if_0_angle_ki_o                : out   std_logic_vector(17 downto 0);
          apb3_if_0_angle_kp_o                : out   std_logic_vector(17 downto 0);
          prdata_o_1_2_0_a2_17_0              : out   std_logic_vector(1 to 1);
          prdata_o_1_2_0_a2_11_0              : out   std_logic_vector(1 to 1);
          adc_interface_0_result_ch1_o        : in    std_logic_vector(11 downto 0) := (others => 'U');
          adc_interface_0_result_ch0_o        : in    std_logic_vector(11 downto 0) := (others => 'U');
          adc_measurements_0_adc_result_ch3_o : in    std_logic_vector(11 downto 0) := (others => 'U');
          adc_measurements_0_adc_result_ch2_o : in    std_logic_vector(11 downto 0) := (others => 'U');
          RATE_LIMITER_0_rl_out_o             : in    std_logic_vector(17 downto 0) := (others => 'U');
          BLDC_ESTIMATOR_1_ealpha_o           : in    std_logic_vector(17 downto 0) := (others => 'U');
          BLDC_ESTIMATOR_1_theta_o            : in    std_logic_vector(17 downto 0) := (others => 'U');
          OLMNG_1_theta_o                     : in    std_logic_vector(17 downto 0) := (others => 'U');
          ADC_SCALING_1_ib_adc_o              : in    std_logic_vector(17 downto 0) := (others => 'U');
          ADC_SCALING_1_ia_adc_o              : in    std_logic_vector(17 downto 0) := (others => 'U');
          FOC_TRANSFORMS_0_iq_o               : in    std_logic_vector(17 downto 0) := (others => 'U');
          FOC_TRANSFORMS_0_id_o               : in    std_logic_vector(17 downto 0) := (others => 'U');
          MC_System_0_AMBA_SLAVE_1_PADDR      : in    std_logic_vector(11 downto 0) := (others => 'U');
          prdata_o_1_2_0_a2_12_0              : out   std_logic_vector(1 to 1);
          SPEED_ID_IQ_PI_1_iq_pi_output_o     : in    std_logic_vector(17 downto 0) := (others => 'U');
          net_189                             : in    std_logic_vector(17 downto 0) := (others => 'U');
          BLDC_ESTIMATOR_1_ealpha_filtered_o  : in    std_logic_vector(17 downto 0) := (others => 'U');
          SPEED_ID_IQ_PI_1_id_pi_output_o     : in    std_logic_vector(17 downto 0) := (others => 'U');
          BLDC_ESTIMATOR_1_ebeta_filtered_o   : in    std_logic_vector(17 downto 0) := (others => 'U');
          BLDC_ESTIMATOR_1_ebeta_o            : in    std_logic_vector(17 downto 0) := (others => 'U');
          BLDC_ESTIMATOR_0_speed_filtered_o   : in    std_logic_vector(17 downto 0) := (others => 'U');
          FOC_TRANSFORMS_0_valpha_o           : in    std_logic_vector(17 downto 0) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_0          : in    std_logic := 'U';
          SEQ_CONTROLLER_1_state_o_2          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o            : in    std_logic_vector(17 downto 0) := (others => 'U');
          BLDC_ESTIMATOR_1_pll_pi_out_o       : in    std_logic_vector(17 downto 0) := (others => 'U');
          FOC_TRANSFORMS_0_ibeta_o            : in    std_logic_vector(17 downto 0) := (others => 'U');
          FOC_TRANSFORMS_0_ialpha_o           : in    std_logic_vector(17 downto 0) := (others => 'U');
          prdata_o_1_2_0_0_1                  : out   std_logic_vector(2 to 2);
          prdata_o_1_0_1                      : out   std_logic_vector(16 to 16);
          prdata_o_1_0_0_4                    : out   std_logic;
          prdata_o_1_2_0_0_5                  : out   std_logic_vector(3 to 3);
          prdata_o_1_2_0_0_2                  : out   std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_0                  : out   std_logic_vector(2 to 2);
          prdata_o_1_3_0_0_3                  : out   std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_2                  : out   std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_0                  : out   std_logic_vector(11 to 11);
          prdata_o_1_8_3                      : out   std_logic_vector(6 to 6);
          prdata_o_1_8_2                      : out   std_logic_vector(6 to 6);
          prdata_o_1_8_0                      : out   std_logic_vector(6 to 6);
          prdata_o_1_0_2                      : out   std_logic_vector(16 to 16);
          prdata_o_1_2_0_0_4_2                : out   std_logic_vector(3 to 3);
          MC_System_0_AMBA_SLAVE_0_PRDATA_12  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_13  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_15  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_14  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_0   : out   std_logic;
          MC_System_0_FIC_0_LOCK              : in    std_logic := 'U';
          MC_System_0_FIC_0_CLK               : in    std_logic := 'U';
          apb3_if_0_stop_motor_o              : out   std_logic;
          apb3_if_0_start_motor_o             : out   std_logic;
          apb3_if_0_fault_clr_o               : out   std_logic;
          apb3_if_0_direction_config_o        : out   std_logic;
          N_2627                              : out   std_logic;
          N_2574                              : out   std_logic;
          prdata_m2_e_1_1                     : out   std_logic;
          N_2645                              : out   std_logic;
          N_739                               : out   std_logic;
          N_766                               : out   std_logic;
          N_768                               : out   std_logic;
          N_769                               : out   std_logic;
          N_1345                              : out   std_logic;
          N_767                               : out   std_logic;
          N_875                               : out   std_logic;
          N_770                               : out   std_logic;
          N_771                               : out   std_logic;
          N_772                               : out   std_logic;
          N_876                               : out   std_logic;
          N_773                               : out   std_logic;
          N_1333                              : out   std_logic;
          N_1347                              : out   std_logic;
          N_1351                              : out   std_logic;
          N_1326                              : out   std_logic;
          N_1346                              : out   std_logic;
          N_878                               : out   std_logic;
          N_789                               : out   std_logic;
          N_791                               : out   std_logic;
          N_1329                              : out   std_logic;
          N_1342                              : out   std_logic;
          N_790                               : out   std_logic;
          N_891                               : out   std_logic;
          N_1360                              : out   std_logic;
          N_1378                              : out   std_logic;
          N_1396                              : out   std_logic;
          N_774                               : out   std_logic;
          N_775                               : out   std_logic;
          N_776                               : out   std_logic;
          N_777                               : out   std_logic;
          N_792                               : out   std_logic;
          N_793                               : out   std_logic;
          N_832                               : out   std_logic;
          N_880                               : out   std_logic;
          N_882                               : out   std_logic;
          N_883                               : out   std_logic;
          N_892                               : out   std_logic;
          N_893                               : out   std_logic;
          N_894                               : out   std_logic;
          N_895                               : out   std_logic;
          N_738                               : out   std_logic;
          N_502                               : out   std_logic;
          N_240                               : out   std_logic;
          N_549                               : out   std_logic;
          N_870                               : out   std_logic;
          N_859                               : out   std_logic;
          N_788                               : out   std_logic;
          N_782                               : out   std_logic;
          N_763                               : out   std_logic;
          N_762                               : out   std_logic;
          N_750                               : out   std_logic;
          N_749                               : out   std_logic;
          N_1288                              : out   std_logic;
          N_1279                              : out   std_logic;
          N_1275                              : out   std_logic;
          N_1169                              : out   std_logic;
          N_1165                              : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PENABLE    : in    std_logic := 'U';
          prdata_m1_e_0_1                     : out   std_logic;
          N_2631                              : out   std_logic;
          N_1398                              : out   std_logic;
          N_519                               : in    std_logic := 'U';
          N_540                               : in    std_logic := 'U';
          N_2644                              : out   std_logic;
          N_2639                              : out   std_logic;
          N_2647                              : out   std_logic;
          N_2640                              : out   std_logic;
          N_2598                              : out   std_logic;
          N_2646                              : out   std_logic;
          N_2652                              : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx      : in    std_logic := 'U';
          N_2495                              : out   std_logic;
          N_2498                              : out   std_logic;
          N_2531                              : out   std_logic;
          N_542                               : in    std_logic := 'U';
          N_544                               : in    std_logic := 'U'
        );
  end component;

    signal \A0_PWM_VL_O_c\ : std_logic;
    signal FOC_TRANSFORMS_0_va_o : std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_vb_o : std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_vc_o : std_logic_vector(17 downto 0);
    signal SVM_0_va3h_o : std_logic_vector(17 downto 0);
    signal SVM_0_vb3h_o : std_logic_vector(17 downto 0);
    signal SVM_0_vc3h_o : std_logic_vector(17 downto 0);
    signal OLMNG_0_init_speedpi_o : 
        std_logic_vector(17 downto 0);
    signal OLMNG_0_init_iqpi_o : std_logic_vector(17 downto 0);
    signal RATE_LIMITER_0_rl_out_o : 
        std_logic_vector(17 downto 0);
    signal BLDC_ESTIMATOR_0_speed_filtered_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_speed_pi_kp_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_speed_pi_ki_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_id_o : std_logic_vector(17 downto 0);
    signal apb3_if_0_idq_pi_kp_o : std_logic_vector(17 downto 0);
    signal apb3_if_0_idq_pi_ki_o_0 : 
        std_logic_vector(17 downto 0);
    signal net_189 : std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_iq_o : std_logic_vector(17 downto 0);
    signal SPEED_ID_IQ_PI_1_id_pi_output_o : 
        std_logic_vector(17 downto 0);
    signal SPEED_ID_IQ_PI_1_iq_pi_output_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_seq_cntl_cl_omega_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_auto_restart_no_o : 
        std_logic_vector(3 downto 0);
    signal apb3_if_0_seq_cntl_config_o : 
        std_logic_vector(3 downto 0);
    signal SEQ_CONTROLLER_1_state_o : 
        std_logic_vector(2 downto 0);
    signal apb3_if_0_rate_limit_slew_cnt_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_rate_limit_rate_cnt_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_rate_limit_ref_in_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_pwm_period_val_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_pwm_gain_val_o : 
        std_logic_vector(17 downto 1);
    signal PWM_SCALING_0_Va_o : std_logic_vector(17 downto 0);
    signal PWM_SCALING_0_Vb_o : std_logic_vector(17 downto 0);
    signal PWM_SCALING_0_Vc_o : std_logic_vector(17 downto 0);
    signal apb3_if_0_pwm_dead_time_val_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_pwm_delay_time_val_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_olmng_theta_factor_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_olmng_dv_o : std_logic_vector(17 downto 0);
    signal BLDC_ESTIMATOR_1_theta_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_olmng_iq_ref_in_o : 
        std_logic_vector(17 downto 0);
    signal OLMNG_1_theta_o : std_logic_vector(17 downto 0);
    signal ADC_SCALING_1_ia_adc_o : 
        std_logic_vector(17 downto 0);
    signal ADC_SCALING_1_ib_adc_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_ialpha_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_ibeta_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_valpha_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_vbeta_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_Ls_by_Ts_pu_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_Rs_pu_o : std_logic_vector(17 downto 0);
    signal apb3_if_0_filter_factor_bemf_o : 
        std_logic_vector(3 downto 0);
    signal apb3_if_0_angle_ki_o : std_logic_vector(17 downto 0);
    signal apb3_if_0_angle_kp_o : std_logic_vector(17 downto 0);
    signal apb3_if_0_filter_factor_omega_o : 
        std_logic_vector(3 downto 0);
    signal BLDC_ESTIMATOR_1_ealpha_o : 
        std_logic_vector(17 downto 0);
    signal BLDC_ESTIMATOR_1_ebeta_o : 
        std_logic_vector(17 downto 0);
    signal BLDC_ESTIMATOR_1_ealpha_filtered_o : 
        std_logic_vector(17 downto 0);
    signal BLDC_ESTIMATOR_1_ebeta_filtered_o : 
        std_logic_vector(17 downto 0);
    signal BLDC_ESTIMATOR_1_pll_pi_out_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_adc_scale_val_o : 
        std_logic_vector(17 downto 0);
    signal adc_interface_0_result_ch0_o : 
        std_logic_vector(11 downto 0);
    signal adc_interface_0_result_ch1_o : 
        std_logic_vector(11 downto 0);
    signal apb3_if_0_adc_oc_thresh_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_0_adc_control_reg_val_o : 
        std_logic_vector(5 downto 0);
    signal adc_measurements_0_adc_result_ch2_o : 
        std_logic_vector(11 downto 0);
    signal adc_measurements_0_adc_result_ch3_o : 
        std_logic_vector(11 downto 0);
    signal apb3_if_0_adc_channel_ch2_o : 
        std_logic_vector(15 downto 0);
    signal apb3_if_0_adc_channel_ch0_o : 
        std_logic_vector(15 downto 0);
    signal apb3_if_0_adc_channel_ch1_o : 
        std_logic_vector(15 downto 0);
    signal apb3_if_0_adc_channel_ch3_o : 
        std_logic_vector(15 downto 0);
    signal SEQ_CONTROLLER_0_reset_rl_o, 
        SEQ_CONTROLLER_0_reset_rl_o_i_0, 
        FOC_TRANSFORMS_0_iclarke_done_o, SVM_0_done_o, 
        SEQ_CONTROLLER_0_motor_stopped_o, 
        SEQ_CONTROLLER_0_cl_status_o, 
        SEQ_CONTROLLER_0_en_idq_pi_o, RATE_LIMITER_0_rl_done_o, 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, 
        FOC_TRANSFORMS_0_park_done_o, \GND\, \VCC\, 
        speed_pi_done_o_0, SPEED_ID_IQ_PI_1_id_pi_done_o, 
        ADC_SCALING_1_over_current_fault_o, 
        apb3_if_0_start_motor_o, apb3_if_0_stop_motor_o, 
        apb3_if_0_fault_clr_o, ADC_SCALING_1_calib_done_o, 
        PWM3PH_1_midmatch_o, PWM_SCALING_1_done_o, 
        SEQ_CONTROLLER_1_adc_start_o, 
        SEQ_CONTROLLER_0_soft_stop_o, sensor_reset_o_0, 
        ADC_SCALING_0_done_o, apb3_if_0_direction_config_o, 
        PWM_AL_o, PWM_BL_o, PWM_CL_o_0, done_o, 
        FOC_TRANSFORMS_1_clarke_done_o_0, 
        FOC_TRANSFORMS_0_ipark_done_o, done_o_0, 
        adc_interface_0_results_rdy_o : std_logic;

    for all : SPEED_ID_IQ_PI_0
	Use entity work.SPEED_ID_IQ_PI_0(DEF_ARCH);
    for all : SVM
	Use entity work.SVM(DEF_ARCH);
    for all : PWM3PH_0
	Use entity work.PWM3PH_0(DEF_ARCH);
    for all : OLMNG
	Use entity work.OLMNG(DEF_ARCH);
    for all : RATE_LIMITER
	Use entity work.RATE_LIMITER(DEF_ARCH);
    for all : BLDC_ESTIMATOR
	Use entity work.BLDC_ESTIMATOR(DEF_ARCH);
    for all : SEQ_CONTROLLER_0
	Use entity work.SEQ_CONTROLLER_0(DEF_ARCH);
    for all : FOC_TRANSFORMS_0
	Use entity work.FOC_TRANSFORMS_0(DEF_ARCH);
    for all : adc_interface_0
	Use entity work.adc_interface_0(DEF_ARCH);
    for all : PWM_SCALING_0
	Use entity work.PWM_SCALING_0(DEF_ARCH);
    for all : ADC_SCALING_0
	Use entity work.ADC_SCALING_0(DEF_ARCH);
    for all : apb3_if
	Use entity work.apb3_if(DEF_ARCH);
begin 

    A0_PWM_VL_O_c <= \A0_PWM_VL_O_c\;

    MSC_i_17 : SPEED_ID_IQ_PI_0
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, clear_buffer_i => 
        SEQ_CONTROLLER_0_motor_stopped_o, speed_en_i => 
        SEQ_CONTROLLER_0_cl_status_o, idq_en_i => 
        SEQ_CONTROLLER_0_en_idq_pi_o, speed_pi_start_i => 
        RATE_LIMITER_0_rl_done_o, id_pi_start_i => 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, iq_pi_start_i => 
        FOC_TRANSFORMS_0_park_done_o, speed_init_i(17) => 
        OLMNG_0_init_speedpi_o(17), speed_init_i(16) => 
        OLMNG_0_init_speedpi_o(16), speed_init_i(15) => 
        OLMNG_0_init_speedpi_o(15), speed_init_i(14) => 
        OLMNG_0_init_speedpi_o(14), speed_init_i(13) => 
        OLMNG_0_init_speedpi_o(13), speed_init_i(12) => 
        OLMNG_0_init_speedpi_o(12), speed_init_i(11) => 
        OLMNG_0_init_speedpi_o(11), speed_init_i(10) => 
        OLMNG_0_init_speedpi_o(10), speed_init_i(9) => 
        OLMNG_0_init_speedpi_o(9), speed_init_i(8) => 
        OLMNG_0_init_speedpi_o(8), speed_init_i(7) => 
        OLMNG_0_init_speedpi_o(7), speed_init_i(6) => 
        OLMNG_0_init_speedpi_o(6), speed_init_i(5) => 
        OLMNG_0_init_speedpi_o(5), speed_init_i(4) => 
        OLMNG_0_init_speedpi_o(4), speed_init_i(3) => 
        OLMNG_0_init_speedpi_o(3), speed_init_i(2) => 
        OLMNG_0_init_speedpi_o(2), speed_init_i(1) => 
        OLMNG_0_init_speedpi_o(1), speed_init_i(0) => 
        OLMNG_0_init_speedpi_o(0), id_init_i(17) => \GND\, 
        id_init_i(16) => \GND\, id_init_i(15) => \GND\, 
        id_init_i(14) => \GND\, id_init_i(13) => \GND\, 
        id_init_i(12) => \GND\, id_init_i(11) => \GND\, 
        id_init_i(10) => \GND\, id_init_i(9) => \GND\, 
        id_init_i(8) => \GND\, id_init_i(7) => \GND\, 
        id_init_i(6) => \GND\, id_init_i(5) => \GND\, 
        id_init_i(4) => \GND\, id_init_i(3) => \GND\, 
        id_init_i(2) => \GND\, id_init_i(1) => \GND\, 
        id_init_i(0) => \GND\, iq_init_i(17) => 
        OLMNG_0_init_iqpi_o(17), iq_init_i(16) => 
        OLMNG_0_init_iqpi_o(16), iq_init_i(15) => 
        OLMNG_0_init_iqpi_o(15), iq_init_i(14) => 
        OLMNG_0_init_iqpi_o(14), iq_init_i(13) => 
        OLMNG_0_init_iqpi_o(13), iq_init_i(12) => 
        OLMNG_0_init_iqpi_o(12), iq_init_i(11) => 
        OLMNG_0_init_iqpi_o(11), iq_init_i(10) => 
        OLMNG_0_init_iqpi_o(10), iq_init_i(9) => 
        OLMNG_0_init_iqpi_o(9), iq_init_i(8) => 
        OLMNG_0_init_iqpi_o(8), iq_init_i(7) => 
        OLMNG_0_init_iqpi_o(7), iq_init_i(6) => 
        OLMNG_0_init_iqpi_o(6), iq_init_i(5) => 
        OLMNG_0_init_iqpi_o(5), iq_init_i(4) => 
        OLMNG_0_init_iqpi_o(4), iq_init_i(3) => 
        OLMNG_0_init_iqpi_o(3), iq_init_i(2) => 
        OLMNG_0_init_iqpi_o(2), iq_init_i(1) => 
        OLMNG_0_init_iqpi_o(1), iq_init_i(0) => 
        OLMNG_0_init_iqpi_o(0), speed_pi_ref_input_i(17) => 
        RATE_LIMITER_0_rl_out_o(17), speed_pi_ref_input_i(16) => 
        RATE_LIMITER_0_rl_out_o(16), speed_pi_ref_input_i(15) => 
        RATE_LIMITER_0_rl_out_o(15), speed_pi_ref_input_i(14) => 
        RATE_LIMITER_0_rl_out_o(14), speed_pi_ref_input_i(13) => 
        RATE_LIMITER_0_rl_out_o(13), speed_pi_ref_input_i(12) => 
        RATE_LIMITER_0_rl_out_o(12), speed_pi_ref_input_i(11) => 
        RATE_LIMITER_0_rl_out_o(11), speed_pi_ref_input_i(10) => 
        RATE_LIMITER_0_rl_out_o(10), speed_pi_ref_input_i(9) => 
        RATE_LIMITER_0_rl_out_o(9), speed_pi_ref_input_i(8) => 
        RATE_LIMITER_0_rl_out_o(8), speed_pi_ref_input_i(7) => 
        RATE_LIMITER_0_rl_out_o(7), speed_pi_ref_input_i(6) => 
        RATE_LIMITER_0_rl_out_o(6), speed_pi_ref_input_i(5) => 
        RATE_LIMITER_0_rl_out_o(5), speed_pi_ref_input_i(4) => 
        RATE_LIMITER_0_rl_out_o(4), speed_pi_ref_input_i(3) => 
        RATE_LIMITER_0_rl_out_o(3), speed_pi_ref_input_i(2) => 
        RATE_LIMITER_0_rl_out_o(2), speed_pi_ref_input_i(1) => 
        RATE_LIMITER_0_rl_out_o(1), speed_pi_ref_input_i(0) => 
        RATE_LIMITER_0_rl_out_o(0), speed_pi_act_input_i(17) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(17), 
        speed_pi_act_input_i(16) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(16), 
        speed_pi_act_input_i(15) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(15), 
        speed_pi_act_input_i(14) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(14), 
        speed_pi_act_input_i(13) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(13), 
        speed_pi_act_input_i(12) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(12), 
        speed_pi_act_input_i(11) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(11), 
        speed_pi_act_input_i(10) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(10), 
        speed_pi_act_input_i(9) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(9), 
        speed_pi_act_input_i(8) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(8), 
        speed_pi_act_input_i(7) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(7), 
        speed_pi_act_input_i(6) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(6), 
        speed_pi_act_input_i(5) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(5), 
        speed_pi_act_input_i(4) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(4), 
        speed_pi_act_input_i(3) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(3), 
        speed_pi_act_input_i(2) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(2), 
        speed_pi_act_input_i(1) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(1), 
        speed_pi_act_input_i(0) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(0), speed_pi_kp_i(17)
         => apb3_if_0_speed_pi_kp_o(17), speed_pi_kp_i(16) => 
        apb3_if_0_speed_pi_kp_o(16), speed_pi_kp_i(15) => 
        apb3_if_0_speed_pi_kp_o(15), speed_pi_kp_i(14) => 
        apb3_if_0_speed_pi_kp_o(14), speed_pi_kp_i(13) => 
        apb3_if_0_speed_pi_kp_o(13), speed_pi_kp_i(12) => 
        apb3_if_0_speed_pi_kp_o(12), speed_pi_kp_i(11) => 
        apb3_if_0_speed_pi_kp_o(11), speed_pi_kp_i(10) => 
        apb3_if_0_speed_pi_kp_o(10), speed_pi_kp_i(9) => 
        apb3_if_0_speed_pi_kp_o(9), speed_pi_kp_i(8) => 
        apb3_if_0_speed_pi_kp_o(8), speed_pi_kp_i(7) => 
        apb3_if_0_speed_pi_kp_o(7), speed_pi_kp_i(6) => 
        apb3_if_0_speed_pi_kp_o(6), speed_pi_kp_i(5) => 
        apb3_if_0_speed_pi_kp_o(5), speed_pi_kp_i(4) => 
        apb3_if_0_speed_pi_kp_o(4), speed_pi_kp_i(3) => 
        apb3_if_0_speed_pi_kp_o(3), speed_pi_kp_i(2) => 
        apb3_if_0_speed_pi_kp_o(2), speed_pi_kp_i(1) => 
        apb3_if_0_speed_pi_kp_o(1), speed_pi_kp_i(0) => 
        apb3_if_0_speed_pi_kp_o(0), speed_pi_ki_i(17) => 
        apb3_if_0_speed_pi_ki_o(17), speed_pi_ki_i(16) => 
        apb3_if_0_speed_pi_ki_o(16), speed_pi_ki_i(15) => 
        apb3_if_0_speed_pi_ki_o(15), speed_pi_ki_i(14) => 
        apb3_if_0_speed_pi_ki_o(14), speed_pi_ki_i(13) => 
        apb3_if_0_speed_pi_ki_o(13), speed_pi_ki_i(12) => 
        apb3_if_0_speed_pi_ki_o(12), speed_pi_ki_i(11) => 
        apb3_if_0_speed_pi_ki_o(11), speed_pi_ki_i(10) => 
        apb3_if_0_speed_pi_ki_o(10), speed_pi_ki_i(9) => 
        apb3_if_0_speed_pi_ki_o(9), speed_pi_ki_i(8) => 
        apb3_if_0_speed_pi_ki_o(8), speed_pi_ki_i(7) => 
        apb3_if_0_speed_pi_ki_o(7), speed_pi_ki_i(6) => 
        apb3_if_0_speed_pi_ki_o(6), speed_pi_ki_i(5) => 
        apb3_if_0_speed_pi_ki_o(5), speed_pi_ki_i(4) => 
        apb3_if_0_speed_pi_ki_o(4), speed_pi_ki_i(3) => 
        apb3_if_0_speed_pi_ki_o(3), speed_pi_ki_i(2) => 
        apb3_if_0_speed_pi_ki_o(2), speed_pi_ki_i(1) => 
        apb3_if_0_speed_pi_ki_o(1), speed_pi_ki_i(0) => 
        apb3_if_0_speed_pi_ki_o(0), speed_pi_ymax_i(17) => \GND\, 
        speed_pi_ymax_i(16) => \VCC\, speed_pi_ymax_i(15) => 
        \VCC\, speed_pi_ymax_i(14) => \VCC\, speed_pi_ymax_i(13)
         => \VCC\, speed_pi_ymax_i(12) => \VCC\, 
        speed_pi_ymax_i(11) => \VCC\, speed_pi_ymax_i(10) => 
        \VCC\, speed_pi_ymax_i(9) => \VCC\, speed_pi_ymax_i(8)
         => \VCC\, speed_pi_ymax_i(7) => \VCC\, 
        speed_pi_ymax_i(6) => \VCC\, speed_pi_ymax_i(5) => \VCC\, 
        speed_pi_ymax_i(4) => \VCC\, speed_pi_ymax_i(3) => \VCC\, 
        speed_pi_ymax_i(2) => \VCC\, speed_pi_ymax_i(1) => \VCC\, 
        speed_pi_ymax_i(0) => \VCC\, speed_pi_ymin_i(17) => \VCC\, 
        speed_pi_ymin_i(16) => \GND\, speed_pi_ymin_i(15) => 
        \GND\, speed_pi_ymin_i(14) => \GND\, speed_pi_ymin_i(13)
         => \GND\, speed_pi_ymin_i(12) => \GND\, 
        speed_pi_ymin_i(11) => \GND\, speed_pi_ymin_i(10) => 
        \GND\, speed_pi_ymin_i(9) => \GND\, speed_pi_ymin_i(8)
         => \GND\, speed_pi_ymin_i(7) => \GND\, 
        speed_pi_ymin_i(6) => \GND\, speed_pi_ymin_i(5) => \GND\, 
        speed_pi_ymin_i(4) => \GND\, speed_pi_ymin_i(3) => \GND\, 
        speed_pi_ymin_i(2) => \GND\, speed_pi_ymin_i(1) => \GND\, 
        speed_pi_ymin_i(0) => \VCC\, id_pi_ref_input_i(17) => 
        \GND\, id_pi_ref_input_i(16) => \GND\, 
        id_pi_ref_input_i(15) => \GND\, id_pi_ref_input_i(14) => 
        \GND\, id_pi_ref_input_i(13) => \GND\, 
        id_pi_ref_input_i(12) => \GND\, id_pi_ref_input_i(11) => 
        \GND\, id_pi_ref_input_i(10) => \GND\, 
        id_pi_ref_input_i(9) => \GND\, id_pi_ref_input_i(8) => 
        \GND\, id_pi_ref_input_i(7) => \GND\, 
        id_pi_ref_input_i(6) => \GND\, id_pi_ref_input_i(5) => 
        \GND\, id_pi_ref_input_i(4) => \GND\, 
        id_pi_ref_input_i(3) => \GND\, id_pi_ref_input_i(2) => 
        \GND\, id_pi_ref_input_i(1) => \GND\, 
        id_pi_ref_input_i(0) => \GND\, id_pi_act_input_i(17) => 
        FOC_TRANSFORMS_0_id_o(17), id_pi_act_input_i(16) => 
        FOC_TRANSFORMS_0_id_o(16), id_pi_act_input_i(15) => 
        FOC_TRANSFORMS_0_id_o(15), id_pi_act_input_i(14) => 
        FOC_TRANSFORMS_0_id_o(14), id_pi_act_input_i(13) => 
        FOC_TRANSFORMS_0_id_o(13), id_pi_act_input_i(12) => 
        FOC_TRANSFORMS_0_id_o(12), id_pi_act_input_i(11) => 
        FOC_TRANSFORMS_0_id_o(11), id_pi_act_input_i(10) => 
        FOC_TRANSFORMS_0_id_o(10), id_pi_act_input_i(9) => 
        FOC_TRANSFORMS_0_id_o(9), id_pi_act_input_i(8) => 
        FOC_TRANSFORMS_0_id_o(8), id_pi_act_input_i(7) => 
        FOC_TRANSFORMS_0_id_o(7), id_pi_act_input_i(6) => 
        FOC_TRANSFORMS_0_id_o(6), id_pi_act_input_i(5) => 
        FOC_TRANSFORMS_0_id_o(5), id_pi_act_input_i(4) => 
        FOC_TRANSFORMS_0_id_o(4), id_pi_act_input_i(3) => 
        FOC_TRANSFORMS_0_id_o(3), id_pi_act_input_i(2) => 
        FOC_TRANSFORMS_0_id_o(2), id_pi_act_input_i(1) => 
        FOC_TRANSFORMS_0_id_o(1), id_pi_act_input_i(0) => 
        FOC_TRANSFORMS_0_id_o(0), id_pi_kp_i(17) => 
        apb3_if_0_idq_pi_kp_o(17), id_pi_kp_i(16) => 
        apb3_if_0_idq_pi_kp_o(16), id_pi_kp_i(15) => 
        apb3_if_0_idq_pi_kp_o(15), id_pi_kp_i(14) => 
        apb3_if_0_idq_pi_kp_o(14), id_pi_kp_i(13) => 
        apb3_if_0_idq_pi_kp_o(13), id_pi_kp_i(12) => 
        apb3_if_0_idq_pi_kp_o(12), id_pi_kp_i(11) => 
        apb3_if_0_idq_pi_kp_o(11), id_pi_kp_i(10) => 
        apb3_if_0_idq_pi_kp_o(10), id_pi_kp_i(9) => 
        apb3_if_0_idq_pi_kp_o(9), id_pi_kp_i(8) => 
        apb3_if_0_idq_pi_kp_o(8), id_pi_kp_i(7) => 
        apb3_if_0_idq_pi_kp_o(7), id_pi_kp_i(6) => 
        apb3_if_0_idq_pi_kp_o(6), id_pi_kp_i(5) => 
        apb3_if_0_idq_pi_kp_o(5), id_pi_kp_i(4) => 
        apb3_if_0_idq_pi_kp_o(4), id_pi_kp_i(3) => 
        apb3_if_0_idq_pi_kp_o(3), id_pi_kp_i(2) => 
        apb3_if_0_idq_pi_kp_o(2), id_pi_kp_i(1) => 
        apb3_if_0_idq_pi_kp_o(1), id_pi_kp_i(0) => 
        apb3_if_0_idq_pi_kp_o(0), id_pi_ki_i(17) => 
        apb3_if_0_idq_pi_ki_o_0(17), id_pi_ki_i(16) => 
        apb3_if_0_idq_pi_ki_o_0(16), id_pi_ki_i(15) => 
        apb3_if_0_idq_pi_ki_o_0(15), id_pi_ki_i(14) => 
        apb3_if_0_idq_pi_ki_o_0(14), id_pi_ki_i(13) => 
        apb3_if_0_idq_pi_ki_o_0(13), id_pi_ki_i(12) => 
        apb3_if_0_idq_pi_ki_o_0(12), id_pi_ki_i(11) => 
        apb3_if_0_idq_pi_ki_o_0(11), id_pi_ki_i(10) => 
        apb3_if_0_idq_pi_ki_o_0(10), id_pi_ki_i(9) => 
        apb3_if_0_idq_pi_ki_o_0(9), id_pi_ki_i(8) => 
        apb3_if_0_idq_pi_ki_o_0(8), id_pi_ki_i(7) => 
        apb3_if_0_idq_pi_ki_o_0(7), id_pi_ki_i(6) => 
        apb3_if_0_idq_pi_ki_o_0(6), id_pi_ki_i(5) => 
        apb3_if_0_idq_pi_ki_o_0(5), id_pi_ki_i(4) => 
        apb3_if_0_idq_pi_ki_o_0(4), id_pi_ki_i(3) => 
        apb3_if_0_idq_pi_ki_o_0(3), id_pi_ki_i(2) => 
        apb3_if_0_idq_pi_ki_o_0(2), id_pi_ki_i(1) => 
        apb3_if_0_idq_pi_ki_o_0(1), id_pi_ki_i(0) => 
        apb3_if_0_idq_pi_ki_o_0(0), idq_pi_ymax_i(17) => \GND\, 
        idq_pi_ymax_i(16) => \VCC\, idq_pi_ymax_i(15) => \GND\, 
        idq_pi_ymax_i(14) => \GND\, idq_pi_ymax_i(13) => \GND\, 
        idq_pi_ymax_i(12) => \GND\, idq_pi_ymax_i(11) => \GND\, 
        idq_pi_ymax_i(10) => \GND\, idq_pi_ymax_i(9) => \GND\, 
        idq_pi_ymax_i(8) => \GND\, idq_pi_ymax_i(7) => \GND\, 
        idq_pi_ymax_i(6) => \GND\, idq_pi_ymax_i(5) => \GND\, 
        idq_pi_ymax_i(4) => \GND\, idq_pi_ymax_i(3) => \GND\, 
        idq_pi_ymax_i(2) => \GND\, idq_pi_ymax_i(1) => \GND\, 
        idq_pi_ymax_i(0) => \GND\, idq_pi_ymin_i(17) => \VCC\, 
        idq_pi_ymin_i(16) => \VCC\, idq_pi_ymin_i(15) => \GND\, 
        idq_pi_ymin_i(14) => \GND\, idq_pi_ymin_i(13) => \GND\, 
        idq_pi_ymin_i(12) => \GND\, idq_pi_ymin_i(11) => \GND\, 
        idq_pi_ymin_i(10) => \GND\, idq_pi_ymin_i(9) => \GND\, 
        idq_pi_ymin_i(8) => \GND\, idq_pi_ymin_i(7) => \GND\, 
        idq_pi_ymin_i(6) => \GND\, idq_pi_ymin_i(5) => \GND\, 
        idq_pi_ymin_i(4) => \GND\, idq_pi_ymin_i(3) => \GND\, 
        idq_pi_ymin_i(2) => \GND\, idq_pi_ymin_i(1) => \GND\, 
        idq_pi_ymin_i(0) => \GND\, iq_pi_ref_input_i(17) => 
        net_189(17), iq_pi_ref_input_i(16) => net_189(16), 
        iq_pi_ref_input_i(15) => net_189(15), 
        iq_pi_ref_input_i(14) => net_189(14), 
        iq_pi_ref_input_i(13) => net_189(13), 
        iq_pi_ref_input_i(12) => net_189(12), 
        iq_pi_ref_input_i(11) => net_189(11), 
        iq_pi_ref_input_i(10) => net_189(10), 
        iq_pi_ref_input_i(9) => net_189(9), iq_pi_ref_input_i(8)
         => net_189(8), iq_pi_ref_input_i(7) => net_189(7), 
        iq_pi_ref_input_i(6) => net_189(6), iq_pi_ref_input_i(5)
         => net_189(5), iq_pi_ref_input_i(4) => net_189(4), 
        iq_pi_ref_input_i(3) => net_189(3), iq_pi_ref_input_i(2)
         => net_189(2), iq_pi_ref_input_i(1) => net_189(1), 
        iq_pi_ref_input_i(0) => net_189(0), iq_pi_act_input_i(17)
         => FOC_TRANSFORMS_0_iq_o(17), iq_pi_act_input_i(16) => 
        FOC_TRANSFORMS_0_iq_o(16), iq_pi_act_input_i(15) => 
        FOC_TRANSFORMS_0_iq_o(15), iq_pi_act_input_i(14) => 
        FOC_TRANSFORMS_0_iq_o(14), iq_pi_act_input_i(13) => 
        FOC_TRANSFORMS_0_iq_o(13), iq_pi_act_input_i(12) => 
        FOC_TRANSFORMS_0_iq_o(12), iq_pi_act_input_i(11) => 
        FOC_TRANSFORMS_0_iq_o(11), iq_pi_act_input_i(10) => 
        FOC_TRANSFORMS_0_iq_o(10), iq_pi_act_input_i(9) => 
        FOC_TRANSFORMS_0_iq_o(9), iq_pi_act_input_i(8) => 
        FOC_TRANSFORMS_0_iq_o(8), iq_pi_act_input_i(7) => 
        FOC_TRANSFORMS_0_iq_o(7), iq_pi_act_input_i(6) => 
        FOC_TRANSFORMS_0_iq_o(6), iq_pi_act_input_i(5) => 
        FOC_TRANSFORMS_0_iq_o(5), iq_pi_act_input_i(4) => 
        FOC_TRANSFORMS_0_iq_o(4), iq_pi_act_input_i(3) => 
        FOC_TRANSFORMS_0_iq_o(3), iq_pi_act_input_i(2) => 
        FOC_TRANSFORMS_0_iq_o(2), iq_pi_act_input_i(1) => 
        FOC_TRANSFORMS_0_iq_o(1), iq_pi_act_input_i(0) => 
        FOC_TRANSFORMS_0_iq_o(0), iq_pi_kp_i(17) => \GND\, 
        iq_pi_kp_i(16) => \GND\, iq_pi_kp_i(15) => \GND\, 
        iq_pi_kp_i(14) => \GND\, iq_pi_kp_i(13) => \GND\, 
        iq_pi_kp_i(12) => \GND\, iq_pi_kp_i(11) => \GND\, 
        iq_pi_kp_i(10) => \GND\, iq_pi_kp_i(9) => \GND\, 
        iq_pi_kp_i(8) => \GND\, iq_pi_kp_i(7) => \GND\, 
        iq_pi_kp_i(6) => \GND\, iq_pi_kp_i(5) => \GND\, 
        iq_pi_kp_i(4) => \GND\, iq_pi_kp_i(3) => \GND\, 
        iq_pi_kp_i(2) => \GND\, iq_pi_kp_i(1) => \GND\, 
        iq_pi_kp_i(0) => \GND\, iq_pi_ki_i(17) => \GND\, 
        iq_pi_ki_i(16) => \GND\, iq_pi_ki_i(15) => \GND\, 
        iq_pi_ki_i(14) => \GND\, iq_pi_ki_i(13) => \GND\, 
        iq_pi_ki_i(12) => \GND\, iq_pi_ki_i(11) => \GND\, 
        iq_pi_ki_i(10) => \GND\, iq_pi_ki_i(9) => \GND\, 
        iq_pi_ki_i(8) => \GND\, iq_pi_ki_i(7) => \GND\, 
        iq_pi_ki_i(6) => \GND\, iq_pi_ki_i(5) => \GND\, 
        iq_pi_ki_i(4) => \GND\, iq_pi_ki_i(3) => \GND\, 
        iq_pi_ki_i(2) => \GND\, iq_pi_ki_i(1) => \GND\, 
        iq_pi_ki_i(0) => \GND\, speed_pi_done_o => 
        speed_pi_done_o_0, id_pi_done_o => 
        SPEED_ID_IQ_PI_1_id_pi_done_o, iq_pi_done_o => 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, speed_pi_output_o(17) => 
        net_189(17), speed_pi_output_o(16) => net_189(16), 
        speed_pi_output_o(15) => net_189(15), 
        speed_pi_output_o(14) => net_189(14), 
        speed_pi_output_o(13) => net_189(13), 
        speed_pi_output_o(12) => net_189(12), 
        speed_pi_output_o(11) => net_189(11), 
        speed_pi_output_o(10) => net_189(10), 
        speed_pi_output_o(9) => net_189(9), speed_pi_output_o(8)
         => net_189(8), speed_pi_output_o(7) => net_189(7), 
        speed_pi_output_o(6) => net_189(6), speed_pi_output_o(5)
         => net_189(5), speed_pi_output_o(4) => net_189(4), 
        speed_pi_output_o(3) => net_189(3), speed_pi_output_o(2)
         => net_189(2), speed_pi_output_o(1) => net_189(1), 
        speed_pi_output_o(0) => net_189(0), id_pi_output_o(17)
         => SPEED_ID_IQ_PI_1_id_pi_output_o(17), 
        id_pi_output_o(16) => SPEED_ID_IQ_PI_1_id_pi_output_o(16), 
        id_pi_output_o(15) => SPEED_ID_IQ_PI_1_id_pi_output_o(15), 
        id_pi_output_o(14) => SPEED_ID_IQ_PI_1_id_pi_output_o(14), 
        id_pi_output_o(13) => SPEED_ID_IQ_PI_1_id_pi_output_o(13), 
        id_pi_output_o(12) => SPEED_ID_IQ_PI_1_id_pi_output_o(12), 
        id_pi_output_o(11) => SPEED_ID_IQ_PI_1_id_pi_output_o(11), 
        id_pi_output_o(10) => SPEED_ID_IQ_PI_1_id_pi_output_o(10), 
        id_pi_output_o(9) => SPEED_ID_IQ_PI_1_id_pi_output_o(9), 
        id_pi_output_o(8) => SPEED_ID_IQ_PI_1_id_pi_output_o(8), 
        id_pi_output_o(7) => SPEED_ID_IQ_PI_1_id_pi_output_o(7), 
        id_pi_output_o(6) => SPEED_ID_IQ_PI_1_id_pi_output_o(6), 
        id_pi_output_o(5) => SPEED_ID_IQ_PI_1_id_pi_output_o(5), 
        id_pi_output_o(4) => SPEED_ID_IQ_PI_1_id_pi_output_o(4), 
        id_pi_output_o(3) => SPEED_ID_IQ_PI_1_id_pi_output_o(3), 
        id_pi_output_o(2) => SPEED_ID_IQ_PI_1_id_pi_output_o(2), 
        id_pi_output_o(1) => SPEED_ID_IQ_PI_1_id_pi_output_o(1), 
        id_pi_output_o(0) => SPEED_ID_IQ_PI_1_id_pi_output_o(0), 
        iq_pi_output_o(17) => SPEED_ID_IQ_PI_1_iq_pi_output_o(17), 
        iq_pi_output_o(16) => SPEED_ID_IQ_PI_1_iq_pi_output_o(16), 
        iq_pi_output_o(15) => SPEED_ID_IQ_PI_1_iq_pi_output_o(15), 
        iq_pi_output_o(14) => SPEED_ID_IQ_PI_1_iq_pi_output_o(14), 
        iq_pi_output_o(13) => SPEED_ID_IQ_PI_1_iq_pi_output_o(13), 
        iq_pi_output_o(12) => SPEED_ID_IQ_PI_1_iq_pi_output_o(12), 
        iq_pi_output_o(11) => SPEED_ID_IQ_PI_1_iq_pi_output_o(11), 
        iq_pi_output_o(10) => SPEED_ID_IQ_PI_1_iq_pi_output_o(10), 
        iq_pi_output_o(9) => SPEED_ID_IQ_PI_1_iq_pi_output_o(9), 
        iq_pi_output_o(8) => SPEED_ID_IQ_PI_1_iq_pi_output_o(8), 
        iq_pi_output_o(7) => SPEED_ID_IQ_PI_1_iq_pi_output_o(7), 
        iq_pi_output_o(6) => SPEED_ID_IQ_PI_1_iq_pi_output_o(6), 
        iq_pi_output_o(5) => SPEED_ID_IQ_PI_1_iq_pi_output_o(5), 
        iq_pi_output_o(4) => SPEED_ID_IQ_PI_1_iq_pi_output_o(4), 
        iq_pi_output_o(3) => SPEED_ID_IQ_PI_1_iq_pi_output_o(3), 
        iq_pi_output_o(2) => SPEED_ID_IQ_PI_1_iq_pi_output_o(2), 
        iq_pi_output_o(1) => SPEED_ID_IQ_PI_1_iq_pi_output_o(1), 
        iq_pi_output_o(0) => SPEED_ID_IQ_PI_1_iq_pi_output_o(0));
    
    MSC_i_0 : SVM
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => 
        FOC_TRANSFORMS_0_iclarke_done_o, va_i(17) => 
        FOC_TRANSFORMS_0_va_o(17), va_i(16) => 
        FOC_TRANSFORMS_0_va_o(16), va_i(15) => 
        FOC_TRANSFORMS_0_va_o(15), va_i(14) => 
        FOC_TRANSFORMS_0_va_o(14), va_i(13) => 
        FOC_TRANSFORMS_0_va_o(13), va_i(12) => 
        FOC_TRANSFORMS_0_va_o(12), va_i(11) => 
        FOC_TRANSFORMS_0_va_o(11), va_i(10) => 
        FOC_TRANSFORMS_0_va_o(10), va_i(9) => 
        FOC_TRANSFORMS_0_va_o(9), va_i(8) => 
        FOC_TRANSFORMS_0_va_o(8), va_i(7) => 
        FOC_TRANSFORMS_0_va_o(7), va_i(6) => 
        FOC_TRANSFORMS_0_va_o(6), va_i(5) => 
        FOC_TRANSFORMS_0_va_o(5), va_i(4) => 
        FOC_TRANSFORMS_0_va_o(4), va_i(3) => 
        FOC_TRANSFORMS_0_va_o(3), va_i(2) => 
        FOC_TRANSFORMS_0_va_o(2), va_i(1) => 
        FOC_TRANSFORMS_0_va_o(1), va_i(0) => 
        FOC_TRANSFORMS_0_va_o(0), vb_i(17) => 
        FOC_TRANSFORMS_0_vb_o(17), vb_i(16) => 
        FOC_TRANSFORMS_0_vb_o(16), vb_i(15) => 
        FOC_TRANSFORMS_0_vb_o(15), vb_i(14) => 
        FOC_TRANSFORMS_0_vb_o(14), vb_i(13) => 
        FOC_TRANSFORMS_0_vb_o(13), vb_i(12) => 
        FOC_TRANSFORMS_0_vb_o(12), vb_i(11) => 
        FOC_TRANSFORMS_0_vb_o(11), vb_i(10) => 
        FOC_TRANSFORMS_0_vb_o(10), vb_i(9) => 
        FOC_TRANSFORMS_0_vb_o(9), vb_i(8) => 
        FOC_TRANSFORMS_0_vb_o(8), vb_i(7) => 
        FOC_TRANSFORMS_0_vb_o(7), vb_i(6) => 
        FOC_TRANSFORMS_0_vb_o(6), vb_i(5) => 
        FOC_TRANSFORMS_0_vb_o(5), vb_i(4) => 
        FOC_TRANSFORMS_0_vb_o(4), vb_i(3) => 
        FOC_TRANSFORMS_0_vb_o(3), vb_i(2) => 
        FOC_TRANSFORMS_0_vb_o(2), vb_i(1) => 
        FOC_TRANSFORMS_0_vb_o(1), vb_i(0) => 
        FOC_TRANSFORMS_0_vb_o(0), vc_i(17) => 
        FOC_TRANSFORMS_0_vc_o(17), vc_i(16) => 
        FOC_TRANSFORMS_0_vc_o(16), vc_i(15) => 
        FOC_TRANSFORMS_0_vc_o(15), vc_i(14) => 
        FOC_TRANSFORMS_0_vc_o(14), vc_i(13) => 
        FOC_TRANSFORMS_0_vc_o(13), vc_i(12) => 
        FOC_TRANSFORMS_0_vc_o(12), vc_i(11) => 
        FOC_TRANSFORMS_0_vc_o(11), vc_i(10) => 
        FOC_TRANSFORMS_0_vc_o(10), vc_i(9) => 
        FOC_TRANSFORMS_0_vc_o(9), vc_i(8) => 
        FOC_TRANSFORMS_0_vc_o(8), vc_i(7) => 
        FOC_TRANSFORMS_0_vc_o(7), vc_i(6) => 
        FOC_TRANSFORMS_0_vc_o(6), vc_i(5) => 
        FOC_TRANSFORMS_0_vc_o(5), vc_i(4) => 
        FOC_TRANSFORMS_0_vc_o(4), vc_i(3) => 
        FOC_TRANSFORMS_0_vc_o(3), vc_i(2) => 
        FOC_TRANSFORMS_0_vc_o(2), vc_i(1) => 
        FOC_TRANSFORMS_0_vc_o(1), vc_i(0) => 
        FOC_TRANSFORMS_0_vc_o(0), va3h_o(17) => SVM_0_va3h_o(17), 
        va3h_o(16) => SVM_0_va3h_o(16), va3h_o(15) => 
        SVM_0_va3h_o(15), va3h_o(14) => SVM_0_va3h_o(14), 
        va3h_o(13) => SVM_0_va3h_o(13), va3h_o(12) => 
        SVM_0_va3h_o(12), va3h_o(11) => SVM_0_va3h_o(11), 
        va3h_o(10) => SVM_0_va3h_o(10), va3h_o(9) => 
        SVM_0_va3h_o(9), va3h_o(8) => SVM_0_va3h_o(8), va3h_o(7)
         => SVM_0_va3h_o(7), va3h_o(6) => SVM_0_va3h_o(6), 
        va3h_o(5) => SVM_0_va3h_o(5), va3h_o(4) => 
        SVM_0_va3h_o(4), va3h_o(3) => SVM_0_va3h_o(3), va3h_o(2)
         => SVM_0_va3h_o(2), va3h_o(1) => SVM_0_va3h_o(1), 
        va3h_o(0) => SVM_0_va3h_o(0), vb3h_o(17) => 
        SVM_0_vb3h_o(17), vb3h_o(16) => SVM_0_vb3h_o(16), 
        vb3h_o(15) => SVM_0_vb3h_o(15), vb3h_o(14) => 
        SVM_0_vb3h_o(14), vb3h_o(13) => SVM_0_vb3h_o(13), 
        vb3h_o(12) => SVM_0_vb3h_o(12), vb3h_o(11) => 
        SVM_0_vb3h_o(11), vb3h_o(10) => SVM_0_vb3h_o(10), 
        vb3h_o(9) => SVM_0_vb3h_o(9), vb3h_o(8) => 
        SVM_0_vb3h_o(8), vb3h_o(7) => SVM_0_vb3h_o(7), vb3h_o(6)
         => SVM_0_vb3h_o(6), vb3h_o(5) => SVM_0_vb3h_o(5), 
        vb3h_o(4) => SVM_0_vb3h_o(4), vb3h_o(3) => 
        SVM_0_vb3h_o(3), vb3h_o(2) => SVM_0_vb3h_o(2), vb3h_o(1)
         => SVM_0_vb3h_o(1), vb3h_o(0) => SVM_0_vb3h_o(0), 
        vc3h_o(17) => SVM_0_vc3h_o(17), vc3h_o(16) => 
        SVM_0_vc3h_o(16), vc3h_o(15) => SVM_0_vc3h_o(15), 
        vc3h_o(14) => SVM_0_vc3h_o(14), vc3h_o(13) => 
        SVM_0_vc3h_o(13), vc3h_o(12) => SVM_0_vc3h_o(12), 
        vc3h_o(11) => SVM_0_vc3h_o(11), vc3h_o(10) => 
        SVM_0_vc3h_o(10), vc3h_o(9) => SVM_0_vc3h_o(9), vc3h_o(8)
         => SVM_0_vc3h_o(8), vc3h_o(7) => SVM_0_vc3h_o(7), 
        vc3h_o(6) => SVM_0_vc3h_o(6), vc3h_o(5) => 
        SVM_0_vc3h_o(5), vc3h_o(4) => SVM_0_vc3h_o(4), vc3h_o(3)
         => SVM_0_vc3h_o(3), vc3h_o(2) => SVM_0_vc3h_o(2), 
        vc3h_o(1) => SVM_0_vc3h_o(1), vc3h_o(0) => 
        SVM_0_vc3h_o(0), done_o => SVM_0_done_o);
    
    GND_Z : GND
      port map(Y => \GND\);
    
    MSC_i_35 : PWM3PH_0
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, en_pwm_i => \A0_PWM_VL_O_c\, 
        en_dual_trig_i => \GND\, va_i(17) => 
        PWM_SCALING_0_Va_o(17), va_i(16) => 
        PWM_SCALING_0_Va_o(16), va_i(15) => 
        PWM_SCALING_0_Va_o(15), va_i(14) => 
        PWM_SCALING_0_Va_o(14), va_i(13) => 
        PWM_SCALING_0_Va_o(13), va_i(12) => 
        PWM_SCALING_0_Va_o(12), va_i(11) => 
        PWM_SCALING_0_Va_o(11), va_i(10) => 
        PWM_SCALING_0_Va_o(10), va_i(9) => PWM_SCALING_0_Va_o(9), 
        va_i(8) => PWM_SCALING_0_Va_o(8), va_i(7) => 
        PWM_SCALING_0_Va_o(7), va_i(6) => PWM_SCALING_0_Va_o(6), 
        va_i(5) => PWM_SCALING_0_Va_o(5), va_i(4) => 
        PWM_SCALING_0_Va_o(4), va_i(3) => PWM_SCALING_0_Va_o(3), 
        va_i(2) => PWM_SCALING_0_Va_o(2), va_i(1) => 
        PWM_SCALING_0_Va_o(1), va_i(0) => PWM_SCALING_0_Va_o(0), 
        vb_i(17) => PWM_SCALING_0_Vb_o(17), vb_i(16) => 
        PWM_SCALING_0_Vb_o(16), vb_i(15) => 
        PWM_SCALING_0_Vb_o(15), vb_i(14) => 
        PWM_SCALING_0_Vb_o(14), vb_i(13) => 
        PWM_SCALING_0_Vb_o(13), vb_i(12) => 
        PWM_SCALING_0_Vb_o(12), vb_i(11) => 
        PWM_SCALING_0_Vb_o(11), vb_i(10) => 
        PWM_SCALING_0_Vb_o(10), vb_i(9) => PWM_SCALING_0_Vb_o(9), 
        vb_i(8) => PWM_SCALING_0_Vb_o(8), vb_i(7) => 
        PWM_SCALING_0_Vb_o(7), vb_i(6) => PWM_SCALING_0_Vb_o(6), 
        vb_i(5) => PWM_SCALING_0_Vb_o(5), vb_i(4) => 
        PWM_SCALING_0_Vb_o(4), vb_i(3) => PWM_SCALING_0_Vb_o(3), 
        vb_i(2) => PWM_SCALING_0_Vb_o(2), vb_i(1) => 
        PWM_SCALING_0_Vb_o(1), vb_i(0) => PWM_SCALING_0_Vb_o(0), 
        vc_i(17) => PWM_SCALING_0_Vc_o(17), vc_i(16) => 
        PWM_SCALING_0_Vc_o(16), vc_i(15) => 
        PWM_SCALING_0_Vc_o(15), vc_i(14) => 
        PWM_SCALING_0_Vc_o(14), vc_i(13) => 
        PWM_SCALING_0_Vc_o(13), vc_i(12) => 
        PWM_SCALING_0_Vc_o(12), vc_i(11) => 
        PWM_SCALING_0_Vc_o(11), vc_i(10) => 
        PWM_SCALING_0_Vc_o(10), vc_i(9) => PWM_SCALING_0_Vc_o(9), 
        vc_i(8) => PWM_SCALING_0_Vc_o(8), vc_i(7) => 
        PWM_SCALING_0_Vc_o(7), vc_i(6) => PWM_SCALING_0_Vc_o(6), 
        vc_i(5) => PWM_SCALING_0_Vc_o(5), vc_i(4) => 
        PWM_SCALING_0_Vc_o(4), vc_i(3) => PWM_SCALING_0_Vc_o(3), 
        vc_i(2) => PWM_SCALING_0_Vc_o(2), vc_i(1) => 
        PWM_SCALING_0_Vc_o(1), vc_i(0) => PWM_SCALING_0_Vc_o(0), 
        pwm_period_i(17) => apb3_if_0_pwm_period_val_o(17), 
        pwm_period_i(16) => apb3_if_0_pwm_period_val_o(16), 
        pwm_period_i(15) => apb3_if_0_pwm_period_val_o(15), 
        pwm_period_i(14) => apb3_if_0_pwm_period_val_o(14), 
        pwm_period_i(13) => apb3_if_0_pwm_period_val_o(13), 
        pwm_period_i(12) => apb3_if_0_pwm_period_val_o(12), 
        pwm_period_i(11) => apb3_if_0_pwm_period_val_o(11), 
        pwm_period_i(10) => apb3_if_0_pwm_period_val_o(10), 
        pwm_period_i(9) => apb3_if_0_pwm_period_val_o(9), 
        pwm_period_i(8) => apb3_if_0_pwm_period_val_o(8), 
        pwm_period_i(7) => apb3_if_0_pwm_period_val_o(7), 
        pwm_period_i(6) => apb3_if_0_pwm_period_val_o(6), 
        pwm_period_i(5) => apb3_if_0_pwm_period_val_o(5), 
        pwm_period_i(4) => apb3_if_0_pwm_period_val_o(4), 
        pwm_period_i(3) => apb3_if_0_pwm_period_val_o(3), 
        pwm_period_i(2) => apb3_if_0_pwm_period_val_o(2), 
        pwm_period_i(1) => apb3_if_0_pwm_period_val_o(1), 
        pwm_period_i(0) => apb3_if_0_pwm_period_val_o(0), 
        dead_time_i(17) => apb3_if_0_pwm_dead_time_val_o(17), 
        dead_time_i(16) => apb3_if_0_pwm_dead_time_val_o(16), 
        dead_time_i(15) => apb3_if_0_pwm_dead_time_val_o(15), 
        dead_time_i(14) => apb3_if_0_pwm_dead_time_val_o(14), 
        dead_time_i(13) => apb3_if_0_pwm_dead_time_val_o(13), 
        dead_time_i(12) => apb3_if_0_pwm_dead_time_val_o(12), 
        dead_time_i(11) => apb3_if_0_pwm_dead_time_val_o(11), 
        dead_time_i(10) => apb3_if_0_pwm_dead_time_val_o(10), 
        dead_time_i(9) => apb3_if_0_pwm_dead_time_val_o(9), 
        dead_time_i(8) => apb3_if_0_pwm_dead_time_val_o(8), 
        dead_time_i(7) => apb3_if_0_pwm_dead_time_val_o(7), 
        dead_time_i(6) => apb3_if_0_pwm_dead_time_val_o(6), 
        dead_time_i(5) => apb3_if_0_pwm_dead_time_val_o(5), 
        dead_time_i(4) => apb3_if_0_pwm_dead_time_val_o(4), 
        dead_time_i(3) => apb3_if_0_pwm_dead_time_val_o(3), 
        dead_time_i(2) => apb3_if_0_pwm_dead_time_val_o(2), 
        dead_time_i(1) => apb3_if_0_pwm_dead_time_val_o(1), 
        dead_time_i(0) => apb3_if_0_pwm_dead_time_val_o(0), 
        delay_time_i(17) => apb3_if_0_pwm_delay_time_val_o(17), 
        delay_time_i(16) => apb3_if_0_pwm_delay_time_val_o(16), 
        delay_time_i(15) => apb3_if_0_pwm_delay_time_val_o(15), 
        delay_time_i(14) => apb3_if_0_pwm_delay_time_val_o(14), 
        delay_time_i(13) => apb3_if_0_pwm_delay_time_val_o(13), 
        delay_time_i(12) => apb3_if_0_pwm_delay_time_val_o(12), 
        delay_time_i(11) => apb3_if_0_pwm_delay_time_val_o(11), 
        delay_time_i(10) => apb3_if_0_pwm_delay_time_val_o(10), 
        delay_time_i(9) => apb3_if_0_pwm_delay_time_val_o(9), 
        delay_time_i(8) => apb3_if_0_pwm_delay_time_val_o(8), 
        delay_time_i(7) => apb3_if_0_pwm_delay_time_val_o(7), 
        delay_time_i(6) => apb3_if_0_pwm_delay_time_val_o(6), 
        delay_time_i(5) => apb3_if_0_pwm_delay_time_val_o(5), 
        delay_time_i(4) => apb3_if_0_pwm_delay_time_val_o(4), 
        delay_time_i(3) => apb3_if_0_pwm_delay_time_val_o(3), 
        delay_time_i(2) => apb3_if_0_pwm_delay_time_val_o(2), 
        delay_time_i(1) => apb3_if_0_pwm_delay_time_val_o(1), 
        delay_time_i(0) => apb3_if_0_pwm_delay_time_val_o(0), 
        midmatch_o => PWM3PH_1_midmatch_o, PWM_AH_o => 
        A0_PWM_UH_O_c, PWM_BH_o => A0_PWM_VH_O_c, PWM_CH_o => 
        A0_PWM_WH_O_c, PWM_AL_o => PWM_AL_o, PWM_BL_o => PWM_BL_o, 
        PWM_CL_o => PWM_CL_o_0);
    
    MSC_i_12 : OLMNG
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => 
        RATE_LIMITER_0_rl_done_o, clear_buffer_i => 
        SEQ_CONTROLLER_0_motor_stopped_o, direction_config_i => 
        apb3_if_0_direction_config_o, cl_status_i => 
        SEQ_CONTROLLER_0_cl_status_o, theta_factor_i(17) => 
        apb3_if_0_olmng_theta_factor_o(17), theta_factor_i(16)
         => apb3_if_0_olmng_theta_factor_o(16), 
        theta_factor_i(15) => apb3_if_0_olmng_theta_factor_o(15), 
        theta_factor_i(14) => apb3_if_0_olmng_theta_factor_o(14), 
        theta_factor_i(13) => apb3_if_0_olmng_theta_factor_o(13), 
        theta_factor_i(12) => apb3_if_0_olmng_theta_factor_o(12), 
        theta_factor_i(11) => apb3_if_0_olmng_theta_factor_o(11), 
        theta_factor_i(10) => apb3_if_0_olmng_theta_factor_o(10), 
        theta_factor_i(9) => apb3_if_0_olmng_theta_factor_o(9), 
        theta_factor_i(8) => apb3_if_0_olmng_theta_factor_o(8), 
        theta_factor_i(7) => apb3_if_0_olmng_theta_factor_o(7), 
        theta_factor_i(6) => apb3_if_0_olmng_theta_factor_o(6), 
        theta_factor_i(5) => apb3_if_0_olmng_theta_factor_o(5), 
        theta_factor_i(4) => apb3_if_0_olmng_theta_factor_o(4), 
        theta_factor_i(3) => apb3_if_0_olmng_theta_factor_o(3), 
        theta_factor_i(2) => apb3_if_0_olmng_theta_factor_o(2), 
        theta_factor_i(1) => apb3_if_0_olmng_theta_factor_o(1), 
        theta_factor_i(0) => apb3_if_0_olmng_theta_factor_o(0), 
        speed_ref_i(17) => RATE_LIMITER_0_rl_out_o(17), 
        speed_ref_i(16) => RATE_LIMITER_0_rl_out_o(16), 
        speed_ref_i(15) => RATE_LIMITER_0_rl_out_o(15), 
        speed_ref_i(14) => RATE_LIMITER_0_rl_out_o(14), 
        speed_ref_i(13) => RATE_LIMITER_0_rl_out_o(13), 
        speed_ref_i(12) => RATE_LIMITER_0_rl_out_o(12), 
        speed_ref_i(11) => RATE_LIMITER_0_rl_out_o(11), 
        speed_ref_i(10) => RATE_LIMITER_0_rl_out_o(10), 
        speed_ref_i(9) => RATE_LIMITER_0_rl_out_o(9), 
        speed_ref_i(8) => RATE_LIMITER_0_rl_out_o(8), 
        speed_ref_i(7) => RATE_LIMITER_0_rl_out_o(7), 
        speed_ref_i(6) => RATE_LIMITER_0_rl_out_o(6), 
        speed_ref_i(5) => RATE_LIMITER_0_rl_out_o(5), 
        speed_ref_i(4) => RATE_LIMITER_0_rl_out_o(4), 
        speed_ref_i(3) => RATE_LIMITER_0_rl_out_o(3), 
        speed_ref_i(2) => RATE_LIMITER_0_rl_out_o(2), 
        speed_ref_i(1) => RATE_LIMITER_0_rl_out_o(1), 
        speed_ref_i(0) => RATE_LIMITER_0_rl_out_o(0), dv_i(17)
         => apb3_if_0_olmng_dv_o(17), dv_i(16) => 
        apb3_if_0_olmng_dv_o(16), dv_i(15) => 
        apb3_if_0_olmng_dv_o(15), dv_i(14) => 
        apb3_if_0_olmng_dv_o(14), dv_i(13) => 
        apb3_if_0_olmng_dv_o(13), dv_i(12) => 
        apb3_if_0_olmng_dv_o(12), dv_i(11) => 
        apb3_if_0_olmng_dv_o(11), dv_i(10) => 
        apb3_if_0_olmng_dv_o(10), dv_i(9) => 
        apb3_if_0_olmng_dv_o(9), dv_i(8) => 
        apb3_if_0_olmng_dv_o(8), dv_i(7) => 
        apb3_if_0_olmng_dv_o(7), dv_i(6) => 
        apb3_if_0_olmng_dv_o(6), dv_i(5) => 
        apb3_if_0_olmng_dv_o(5), dv_i(4) => 
        apb3_if_0_olmng_dv_o(4), dv_i(3) => 
        apb3_if_0_olmng_dv_o(3), dv_i(2) => 
        apb3_if_0_olmng_dv_o(2), dv_i(1) => 
        apb3_if_0_olmng_dv_o(1), dv_i(0) => 
        apb3_if_0_olmng_dv_o(0), theta_cl_i(17) => 
        BLDC_ESTIMATOR_1_theta_o(17), theta_cl_i(16) => 
        BLDC_ESTIMATOR_1_theta_o(16), theta_cl_i(15) => 
        BLDC_ESTIMATOR_1_theta_o(15), theta_cl_i(14) => 
        BLDC_ESTIMATOR_1_theta_o(14), theta_cl_i(13) => 
        BLDC_ESTIMATOR_1_theta_o(13), theta_cl_i(12) => 
        BLDC_ESTIMATOR_1_theta_o(12), theta_cl_i(11) => 
        BLDC_ESTIMATOR_1_theta_o(11), theta_cl_i(10) => 
        BLDC_ESTIMATOR_1_theta_o(10), theta_cl_i(9) => 
        BLDC_ESTIMATOR_1_theta_o(9), theta_cl_i(8) => 
        BLDC_ESTIMATOR_1_theta_o(8), theta_cl_i(7) => 
        BLDC_ESTIMATOR_1_theta_o(7), theta_cl_i(6) => 
        BLDC_ESTIMATOR_1_theta_o(6), theta_cl_i(5) => 
        BLDC_ESTIMATOR_1_theta_o(5), theta_cl_i(4) => 
        BLDC_ESTIMATOR_1_theta_o(4), theta_cl_i(3) => 
        BLDC_ESTIMATOR_1_theta_o(3), theta_cl_i(2) => 
        BLDC_ESTIMATOR_1_theta_o(2), theta_cl_i(1) => 
        BLDC_ESTIMATOR_1_theta_o(1), theta_cl_i(0) => 
        BLDC_ESTIMATOR_1_theta_o(0), iq_ref_in_i(17) => 
        apb3_if_0_olmng_iq_ref_in_o(17), iq_ref_in_i(16) => 
        apb3_if_0_olmng_iq_ref_in_o(16), iq_ref_in_i(15) => 
        apb3_if_0_olmng_iq_ref_in_o(15), iq_ref_in_i(14) => 
        apb3_if_0_olmng_iq_ref_in_o(14), iq_ref_in_i(13) => 
        apb3_if_0_olmng_iq_ref_in_o(13), iq_ref_in_i(12) => 
        apb3_if_0_olmng_iq_ref_in_o(12), iq_ref_in_i(11) => 
        apb3_if_0_olmng_iq_ref_in_o(11), iq_ref_in_i(10) => 
        apb3_if_0_olmng_iq_ref_in_o(10), iq_ref_in_i(9) => 
        apb3_if_0_olmng_iq_ref_in_o(9), iq_ref_in_i(8) => 
        apb3_if_0_olmng_iq_ref_in_o(8), iq_ref_in_i(7) => 
        apb3_if_0_olmng_iq_ref_in_o(7), iq_ref_in_i(6) => 
        apb3_if_0_olmng_iq_ref_in_o(6), iq_ref_in_i(5) => 
        apb3_if_0_olmng_iq_ref_in_o(5), iq_ref_in_i(4) => 
        apb3_if_0_olmng_iq_ref_in_o(4), iq_ref_in_i(3) => 
        apb3_if_0_olmng_iq_ref_in_o(3), iq_ref_in_i(2) => 
        apb3_if_0_olmng_iq_ref_in_o(2), iq_ref_in_i(1) => 
        apb3_if_0_olmng_iq_ref_in_o(1), iq_ref_in_i(0) => 
        apb3_if_0_olmng_iq_ref_in_o(0), done_o => done_o, 
        theta_o(17) => OLMNG_1_theta_o(17), theta_o(16) => 
        OLMNG_1_theta_o(16), theta_o(15) => OLMNG_1_theta_o(15), 
        theta_o(14) => OLMNG_1_theta_o(14), theta_o(13) => 
        OLMNG_1_theta_o(13), theta_o(12) => OLMNG_1_theta_o(12), 
        theta_o(11) => OLMNG_1_theta_o(11), theta_o(10) => 
        OLMNG_1_theta_o(10), theta_o(9) => OLMNG_1_theta_o(9), 
        theta_o(8) => OLMNG_1_theta_o(8), theta_o(7) => 
        OLMNG_1_theta_o(7), theta_o(6) => OLMNG_1_theta_o(6), 
        theta_o(5) => OLMNG_1_theta_o(5), theta_o(4) => 
        OLMNG_1_theta_o(4), theta_o(3) => OLMNG_1_theta_o(3), 
        theta_o(2) => OLMNG_1_theta_o(2), theta_o(1) => 
        OLMNG_1_theta_o(1), theta_o(0) => OLMNG_1_theta_o(0), 
        init_speedpi_o(17) => OLMNG_0_init_speedpi_o(17), 
        init_speedpi_o(16) => OLMNG_0_init_speedpi_o(16), 
        init_speedpi_o(15) => OLMNG_0_init_speedpi_o(15), 
        init_speedpi_o(14) => OLMNG_0_init_speedpi_o(14), 
        init_speedpi_o(13) => OLMNG_0_init_speedpi_o(13), 
        init_speedpi_o(12) => OLMNG_0_init_speedpi_o(12), 
        init_speedpi_o(11) => OLMNG_0_init_speedpi_o(11), 
        init_speedpi_o(10) => OLMNG_0_init_speedpi_o(10), 
        init_speedpi_o(9) => OLMNG_0_init_speedpi_o(9), 
        init_speedpi_o(8) => OLMNG_0_init_speedpi_o(8), 
        init_speedpi_o(7) => OLMNG_0_init_speedpi_o(7), 
        init_speedpi_o(6) => OLMNG_0_init_speedpi_o(6), 
        init_speedpi_o(5) => OLMNG_0_init_speedpi_o(5), 
        init_speedpi_o(4) => OLMNG_0_init_speedpi_o(4), 
        init_speedpi_o(3) => OLMNG_0_init_speedpi_o(3), 
        init_speedpi_o(2) => OLMNG_0_init_speedpi_o(2), 
        init_speedpi_o(1) => OLMNG_0_init_speedpi_o(1), 
        init_speedpi_o(0) => OLMNG_0_init_speedpi_o(0), 
        init_iqpi_o(17) => OLMNG_0_init_iqpi_o(17), 
        init_iqpi_o(16) => OLMNG_0_init_iqpi_o(16), 
        init_iqpi_o(15) => OLMNG_0_init_iqpi_o(15), 
        init_iqpi_o(14) => OLMNG_0_init_iqpi_o(14), 
        init_iqpi_o(13) => OLMNG_0_init_iqpi_o(13), 
        init_iqpi_o(12) => OLMNG_0_init_iqpi_o(12), 
        init_iqpi_o(11) => OLMNG_0_init_iqpi_o(11), 
        init_iqpi_o(10) => OLMNG_0_init_iqpi_o(10), 
        init_iqpi_o(9) => OLMNG_0_init_iqpi_o(9), init_iqpi_o(8)
         => OLMNG_0_init_iqpi_o(8), init_iqpi_o(7) => 
        OLMNG_0_init_iqpi_o(7), init_iqpi_o(6) => 
        OLMNG_0_init_iqpi_o(6), init_iqpi_o(5) => 
        OLMNG_0_init_iqpi_o(5), init_iqpi_o(4) => 
        OLMNG_0_init_iqpi_o(4), init_iqpi_o(3) => 
        OLMNG_0_init_iqpi_o(3), init_iqpi_o(2) => 
        OLMNG_0_init_iqpi_o(2), init_iqpi_o(1) => 
        OLMNG_0_init_iqpi_o(1), init_iqpi_o(0) => 
        OLMNG_0_init_iqpi_o(0));
    
    MSC_i_9 : RATE_LIMITER
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => ADC_SCALING_0_done_o, 
        soft_stop_i => SEQ_CONTROLLER_0_soft_stop_o, reset_rl_i
         => SEQ_CONTROLLER_0_reset_rl_o, direction_i => 
        apb3_if_0_direction_config_o, slew_count_i(17) => 
        apb3_if_0_rate_limit_slew_cnt_o(17), slew_count_i(16) => 
        apb3_if_0_rate_limit_slew_cnt_o(16), slew_count_i(15) => 
        apb3_if_0_rate_limit_slew_cnt_o(15), slew_count_i(14) => 
        apb3_if_0_rate_limit_slew_cnt_o(14), slew_count_i(13) => 
        apb3_if_0_rate_limit_slew_cnt_o(13), slew_count_i(12) => 
        apb3_if_0_rate_limit_slew_cnt_o(12), slew_count_i(11) => 
        apb3_if_0_rate_limit_slew_cnt_o(11), slew_count_i(10) => 
        apb3_if_0_rate_limit_slew_cnt_o(10), slew_count_i(9) => 
        apb3_if_0_rate_limit_slew_cnt_o(9), slew_count_i(8) => 
        apb3_if_0_rate_limit_slew_cnt_o(8), slew_count_i(7) => 
        apb3_if_0_rate_limit_slew_cnt_o(7), slew_count_i(6) => 
        apb3_if_0_rate_limit_slew_cnt_o(6), slew_count_i(5) => 
        apb3_if_0_rate_limit_slew_cnt_o(5), slew_count_i(4) => 
        apb3_if_0_rate_limit_slew_cnt_o(4), slew_count_i(3) => 
        apb3_if_0_rate_limit_slew_cnt_o(3), slew_count_i(2) => 
        apb3_if_0_rate_limit_slew_cnt_o(2), slew_count_i(1) => 
        apb3_if_0_rate_limit_slew_cnt_o(1), slew_count_i(0) => 
        apb3_if_0_rate_limit_slew_cnt_o(0), rate_count_i(17) => 
        apb3_if_0_rate_limit_rate_cnt_o(17), rate_count_i(16) => 
        apb3_if_0_rate_limit_rate_cnt_o(16), rate_count_i(15) => 
        apb3_if_0_rate_limit_rate_cnt_o(15), rate_count_i(14) => 
        apb3_if_0_rate_limit_rate_cnt_o(14), rate_count_i(13) => 
        apb3_if_0_rate_limit_rate_cnt_o(13), rate_count_i(12) => 
        apb3_if_0_rate_limit_rate_cnt_o(12), rate_count_i(11) => 
        apb3_if_0_rate_limit_rate_cnt_o(11), rate_count_i(10) => 
        apb3_if_0_rate_limit_rate_cnt_o(10), rate_count_i(9) => 
        apb3_if_0_rate_limit_rate_cnt_o(9), rate_count_i(8) => 
        apb3_if_0_rate_limit_rate_cnt_o(8), rate_count_i(7) => 
        apb3_if_0_rate_limit_rate_cnt_o(7), rate_count_i(6) => 
        apb3_if_0_rate_limit_rate_cnt_o(6), rate_count_i(5) => 
        apb3_if_0_rate_limit_rate_cnt_o(5), rate_count_i(4) => 
        apb3_if_0_rate_limit_rate_cnt_o(4), rate_count_i(3) => 
        apb3_if_0_rate_limit_rate_cnt_o(3), rate_count_i(2) => 
        apb3_if_0_rate_limit_rate_cnt_o(2), rate_count_i(1) => 
        apb3_if_0_rate_limit_rate_cnt_o(1), rate_count_i(0) => 
        apb3_if_0_rate_limit_rate_cnt_o(0), rl_in_i(17) => 
        apb3_if_0_rate_limit_ref_in_o(17), rl_in_i(16) => 
        apb3_if_0_rate_limit_ref_in_o(16), rl_in_i(15) => 
        apb3_if_0_rate_limit_ref_in_o(15), rl_in_i(14) => 
        apb3_if_0_rate_limit_ref_in_o(14), rl_in_i(13) => 
        apb3_if_0_rate_limit_ref_in_o(13), rl_in_i(12) => 
        apb3_if_0_rate_limit_ref_in_o(12), rl_in_i(11) => 
        apb3_if_0_rate_limit_ref_in_o(11), rl_in_i(10) => 
        apb3_if_0_rate_limit_ref_in_o(10), rl_in_i(9) => 
        apb3_if_0_rate_limit_ref_in_o(9), rl_in_i(8) => 
        apb3_if_0_rate_limit_ref_in_o(8), rl_in_i(7) => 
        apb3_if_0_rate_limit_ref_in_o(7), rl_in_i(6) => 
        apb3_if_0_rate_limit_ref_in_o(6), rl_in_i(5) => 
        apb3_if_0_rate_limit_ref_in_o(5), rl_in_i(4) => 
        apb3_if_0_rate_limit_ref_in_o(4), rl_in_i(3) => 
        apb3_if_0_rate_limit_ref_in_o(3), rl_in_i(2) => 
        apb3_if_0_rate_limit_ref_in_o(2), rl_in_i(1) => 
        apb3_if_0_rate_limit_ref_in_o(1), rl_in_i(0) => 
        apb3_if_0_rate_limit_ref_in_o(0), rl_out_o(17) => 
        RATE_LIMITER_0_rl_out_o(17), rl_out_o(16) => 
        RATE_LIMITER_0_rl_out_o(16), rl_out_o(15) => 
        RATE_LIMITER_0_rl_out_o(15), rl_out_o(14) => 
        RATE_LIMITER_0_rl_out_o(14), rl_out_o(13) => 
        RATE_LIMITER_0_rl_out_o(13), rl_out_o(12) => 
        RATE_LIMITER_0_rl_out_o(12), rl_out_o(11) => 
        RATE_LIMITER_0_rl_out_o(11), rl_out_o(10) => 
        RATE_LIMITER_0_rl_out_o(10), rl_out_o(9) => 
        RATE_LIMITER_0_rl_out_o(9), rl_out_o(8) => 
        RATE_LIMITER_0_rl_out_o(8), rl_out_o(7) => 
        RATE_LIMITER_0_rl_out_o(7), rl_out_o(6) => 
        RATE_LIMITER_0_rl_out_o(6), rl_out_o(5) => 
        RATE_LIMITER_0_rl_out_o(5), rl_out_o(4) => 
        RATE_LIMITER_0_rl_out_o(4), rl_out_o(3) => 
        RATE_LIMITER_0_rl_out_o(3), rl_out_o(2) => 
        RATE_LIMITER_0_rl_out_o(2), rl_out_o(1) => 
        RATE_LIMITER_0_rl_out_o(1), rl_out_o(0) => 
        RATE_LIMITER_0_rl_out_o(0), rl_done_o => 
        RATE_LIMITER_0_rl_done_o);
    
    MSC_i_21 : BLDC_ESTIMATOR
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => 
        FOC_TRANSFORMS_0_ipark_done_o, angle_pi_en_i => 
        SEQ_CONTROLLER_0_reset_rl_o_i_0, v_alpha_i(17) => 
        FOC_TRANSFORMS_0_valpha_o(17), v_alpha_i(16) => 
        FOC_TRANSFORMS_0_valpha_o(16), v_alpha_i(15) => 
        FOC_TRANSFORMS_0_valpha_o(15), v_alpha_i(14) => 
        FOC_TRANSFORMS_0_valpha_o(14), v_alpha_i(13) => 
        FOC_TRANSFORMS_0_valpha_o(13), v_alpha_i(12) => 
        FOC_TRANSFORMS_0_valpha_o(12), v_alpha_i(11) => 
        FOC_TRANSFORMS_0_valpha_o(11), v_alpha_i(10) => 
        FOC_TRANSFORMS_0_valpha_o(10), v_alpha_i(9) => 
        FOC_TRANSFORMS_0_valpha_o(9), v_alpha_i(8) => 
        FOC_TRANSFORMS_0_valpha_o(8), v_alpha_i(7) => 
        FOC_TRANSFORMS_0_valpha_o(7), v_alpha_i(6) => 
        FOC_TRANSFORMS_0_valpha_o(6), v_alpha_i(5) => 
        FOC_TRANSFORMS_0_valpha_o(5), v_alpha_i(4) => 
        FOC_TRANSFORMS_0_valpha_o(4), v_alpha_i(3) => 
        FOC_TRANSFORMS_0_valpha_o(3), v_alpha_i(2) => 
        FOC_TRANSFORMS_0_valpha_o(2), v_alpha_i(1) => 
        FOC_TRANSFORMS_0_valpha_o(1), v_alpha_i(0) => 
        FOC_TRANSFORMS_0_valpha_o(0), v_beta_i(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), v_beta_i(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), v_beta_i(15) => 
        FOC_TRANSFORMS_0_vbeta_o(15), v_beta_i(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), v_beta_i(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), v_beta_i(12) => 
        FOC_TRANSFORMS_0_vbeta_o(12), v_beta_i(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), v_beta_i(10) => 
        FOC_TRANSFORMS_0_vbeta_o(10), v_beta_i(9) => 
        FOC_TRANSFORMS_0_vbeta_o(9), v_beta_i(8) => 
        FOC_TRANSFORMS_0_vbeta_o(8), v_beta_i(7) => 
        FOC_TRANSFORMS_0_vbeta_o(7), v_beta_i(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), v_beta_i(5) => 
        FOC_TRANSFORMS_0_vbeta_o(5), v_beta_i(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), v_beta_i(3) => 
        FOC_TRANSFORMS_0_vbeta_o(3), v_beta_i(2) => 
        FOC_TRANSFORMS_0_vbeta_o(2), v_beta_i(1) => 
        FOC_TRANSFORMS_0_vbeta_o(1), v_beta_i(0) => 
        FOC_TRANSFORMS_0_vbeta_o(0), i_alpha_i(17) => 
        FOC_TRANSFORMS_0_ialpha_o(17), i_alpha_i(16) => 
        FOC_TRANSFORMS_0_ialpha_o(16), i_alpha_i(15) => 
        FOC_TRANSFORMS_0_ialpha_o(15), i_alpha_i(14) => 
        FOC_TRANSFORMS_0_ialpha_o(14), i_alpha_i(13) => 
        FOC_TRANSFORMS_0_ialpha_o(13), i_alpha_i(12) => 
        FOC_TRANSFORMS_0_ialpha_o(12), i_alpha_i(11) => 
        FOC_TRANSFORMS_0_ialpha_o(11), i_alpha_i(10) => 
        FOC_TRANSFORMS_0_ialpha_o(10), i_alpha_i(9) => 
        FOC_TRANSFORMS_0_ialpha_o(9), i_alpha_i(8) => 
        FOC_TRANSFORMS_0_ialpha_o(8), i_alpha_i(7) => 
        FOC_TRANSFORMS_0_ialpha_o(7), i_alpha_i(6) => 
        FOC_TRANSFORMS_0_ialpha_o(6), i_alpha_i(5) => 
        FOC_TRANSFORMS_0_ialpha_o(5), i_alpha_i(4) => 
        FOC_TRANSFORMS_0_ialpha_o(4), i_alpha_i(3) => 
        FOC_TRANSFORMS_0_ialpha_o(3), i_alpha_i(2) => 
        FOC_TRANSFORMS_0_ialpha_o(2), i_alpha_i(1) => 
        FOC_TRANSFORMS_0_ialpha_o(1), i_alpha_i(0) => 
        FOC_TRANSFORMS_0_ialpha_o(0), i_beta_i(17) => 
        FOC_TRANSFORMS_0_ibeta_o(17), i_beta_i(16) => 
        FOC_TRANSFORMS_0_ibeta_o(16), i_beta_i(15) => 
        FOC_TRANSFORMS_0_ibeta_o(15), i_beta_i(14) => 
        FOC_TRANSFORMS_0_ibeta_o(14), i_beta_i(13) => 
        FOC_TRANSFORMS_0_ibeta_o(13), i_beta_i(12) => 
        FOC_TRANSFORMS_0_ibeta_o(12), i_beta_i(11) => 
        FOC_TRANSFORMS_0_ibeta_o(11), i_beta_i(10) => 
        FOC_TRANSFORMS_0_ibeta_o(10), i_beta_i(9) => 
        FOC_TRANSFORMS_0_ibeta_o(9), i_beta_i(8) => 
        FOC_TRANSFORMS_0_ibeta_o(8), i_beta_i(7) => 
        FOC_TRANSFORMS_0_ibeta_o(7), i_beta_i(6) => 
        FOC_TRANSFORMS_0_ibeta_o(6), i_beta_i(5) => 
        FOC_TRANSFORMS_0_ibeta_o(5), i_beta_i(4) => 
        FOC_TRANSFORMS_0_ibeta_o(4), i_beta_i(3) => 
        FOC_TRANSFORMS_0_ibeta_o(3), i_beta_i(2) => 
        FOC_TRANSFORMS_0_ibeta_o(2), i_beta_i(1) => 
        FOC_TRANSFORMS_0_ibeta_o(1), i_beta_i(0) => 
        FOC_TRANSFORMS_0_ibeta_o(0), Ls_by_Ts_pu_i(17) => 
        apb3_if_0_Ls_by_Ts_pu_o(17), Ls_by_Ts_pu_i(16) => 
        apb3_if_0_Ls_by_Ts_pu_o(16), Ls_by_Ts_pu_i(15) => 
        apb3_if_0_Ls_by_Ts_pu_o(15), Ls_by_Ts_pu_i(14) => 
        apb3_if_0_Ls_by_Ts_pu_o(14), Ls_by_Ts_pu_i(13) => 
        apb3_if_0_Ls_by_Ts_pu_o(13), Ls_by_Ts_pu_i(12) => 
        apb3_if_0_Ls_by_Ts_pu_o(12), Ls_by_Ts_pu_i(11) => 
        apb3_if_0_Ls_by_Ts_pu_o(11), Ls_by_Ts_pu_i(10) => 
        apb3_if_0_Ls_by_Ts_pu_o(10), Ls_by_Ts_pu_i(9) => 
        apb3_if_0_Ls_by_Ts_pu_o(9), Ls_by_Ts_pu_i(8) => 
        apb3_if_0_Ls_by_Ts_pu_o(8), Ls_by_Ts_pu_i(7) => 
        apb3_if_0_Ls_by_Ts_pu_o(7), Ls_by_Ts_pu_i(6) => 
        apb3_if_0_Ls_by_Ts_pu_o(6), Ls_by_Ts_pu_i(5) => 
        apb3_if_0_Ls_by_Ts_pu_o(5), Ls_by_Ts_pu_i(4) => 
        apb3_if_0_Ls_by_Ts_pu_o(4), Ls_by_Ts_pu_i(3) => 
        apb3_if_0_Ls_by_Ts_pu_o(3), Ls_by_Ts_pu_i(2) => 
        apb3_if_0_Ls_by_Ts_pu_o(2), Ls_by_Ts_pu_i(1) => 
        apb3_if_0_Ls_by_Ts_pu_o(1), Ls_by_Ts_pu_i(0) => 
        apb3_if_0_Ls_by_Ts_pu_o(0), Rs_pu_i(17) => 
        apb3_if_0_Rs_pu_o(17), Rs_pu_i(16) => 
        apb3_if_0_Rs_pu_o(16), Rs_pu_i(15) => 
        apb3_if_0_Rs_pu_o(15), Rs_pu_i(14) => 
        apb3_if_0_Rs_pu_o(14), Rs_pu_i(13) => 
        apb3_if_0_Rs_pu_o(13), Rs_pu_i(12) => 
        apb3_if_0_Rs_pu_o(12), Rs_pu_i(11) => 
        apb3_if_0_Rs_pu_o(11), Rs_pu_i(10) => 
        apb3_if_0_Rs_pu_o(10), Rs_pu_i(9) => apb3_if_0_Rs_pu_o(9), 
        Rs_pu_i(8) => apb3_if_0_Rs_pu_o(8), Rs_pu_i(7) => 
        apb3_if_0_Rs_pu_o(7), Rs_pu_i(6) => apb3_if_0_Rs_pu_o(6), 
        Rs_pu_i(5) => apb3_if_0_Rs_pu_o(5), Rs_pu_i(4) => 
        apb3_if_0_Rs_pu_o(4), Rs_pu_i(3) => apb3_if_0_Rs_pu_o(3), 
        Rs_pu_i(2) => apb3_if_0_Rs_pu_o(2), Rs_pu_i(1) => 
        apb3_if_0_Rs_pu_o(1), Rs_pu_i(0) => apb3_if_0_Rs_pu_o(0), 
        ealpha_filter_factor_i(3) => 
        apb3_if_0_filter_factor_bemf_o(3), 
        ealpha_filter_factor_i(2) => 
        apb3_if_0_filter_factor_bemf_o(2), 
        ealpha_filter_factor_i(1) => 
        apb3_if_0_filter_factor_bemf_o(1), 
        ealpha_filter_factor_i(0) => 
        apb3_if_0_filter_factor_bemf_o(0), 
        ebeta_filter_factor_i(3) => \GND\, 
        ebeta_filter_factor_i(2) => \GND\, 
        ebeta_filter_factor_i(1) => \GND\, 
        ebeta_filter_factor_i(0) => \GND\, pll_theta_factor_i(17)
         => apb3_if_0_olmng_theta_factor_o(17), 
        pll_theta_factor_i(16) => 
        apb3_if_0_olmng_theta_factor_o(16), 
        pll_theta_factor_i(15) => 
        apb3_if_0_olmng_theta_factor_o(15), 
        pll_theta_factor_i(14) => 
        apb3_if_0_olmng_theta_factor_o(14), 
        pll_theta_factor_i(13) => 
        apb3_if_0_olmng_theta_factor_o(13), 
        pll_theta_factor_i(12) => 
        apb3_if_0_olmng_theta_factor_o(12), 
        pll_theta_factor_i(11) => 
        apb3_if_0_olmng_theta_factor_o(11), 
        pll_theta_factor_i(10) => 
        apb3_if_0_olmng_theta_factor_o(10), pll_theta_factor_i(9)
         => apb3_if_0_olmng_theta_factor_o(9), 
        pll_theta_factor_i(8) => 
        apb3_if_0_olmng_theta_factor_o(8), pll_theta_factor_i(7)
         => apb3_if_0_olmng_theta_factor_o(7), 
        pll_theta_factor_i(6) => 
        apb3_if_0_olmng_theta_factor_o(6), pll_theta_factor_i(5)
         => apb3_if_0_olmng_theta_factor_o(5), 
        pll_theta_factor_i(4) => 
        apb3_if_0_olmng_theta_factor_o(4), pll_theta_factor_i(3)
         => apb3_if_0_olmng_theta_factor_o(3), 
        pll_theta_factor_i(2) => 
        apb3_if_0_olmng_theta_factor_o(2), pll_theta_factor_i(1)
         => apb3_if_0_olmng_theta_factor_o(1), 
        pll_theta_factor_i(0) => 
        apb3_if_0_olmng_theta_factor_o(0), angle_pi_ki_i(17) => 
        apb3_if_0_angle_ki_o(17), angle_pi_ki_i(16) => 
        apb3_if_0_angle_ki_o(16), angle_pi_ki_i(15) => 
        apb3_if_0_angle_ki_o(15), angle_pi_ki_i(14) => 
        apb3_if_0_angle_ki_o(14), angle_pi_ki_i(13) => 
        apb3_if_0_angle_ki_o(13), angle_pi_ki_i(12) => 
        apb3_if_0_angle_ki_o(12), angle_pi_ki_i(11) => 
        apb3_if_0_angle_ki_o(11), angle_pi_ki_i(10) => 
        apb3_if_0_angle_ki_o(10), angle_pi_ki_i(9) => 
        apb3_if_0_angle_ki_o(9), angle_pi_ki_i(8) => 
        apb3_if_0_angle_ki_o(8), angle_pi_ki_i(7) => 
        apb3_if_0_angle_ki_o(7), angle_pi_ki_i(6) => 
        apb3_if_0_angle_ki_o(6), angle_pi_ki_i(5) => 
        apb3_if_0_angle_ki_o(5), angle_pi_ki_i(4) => 
        apb3_if_0_angle_ki_o(4), angle_pi_ki_i(3) => 
        apb3_if_0_angle_ki_o(3), angle_pi_ki_i(2) => 
        apb3_if_0_angle_ki_o(2), angle_pi_ki_i(1) => 
        apb3_if_0_angle_ki_o(1), angle_pi_ki_i(0) => 
        apb3_if_0_angle_ki_o(0), angle_pi_kp_i(17) => 
        apb3_if_0_angle_kp_o(17), angle_pi_kp_i(16) => 
        apb3_if_0_angle_kp_o(16), angle_pi_kp_i(15) => 
        apb3_if_0_angle_kp_o(15), angle_pi_kp_i(14) => 
        apb3_if_0_angle_kp_o(14), angle_pi_kp_i(13) => 
        apb3_if_0_angle_kp_o(13), angle_pi_kp_i(12) => 
        apb3_if_0_angle_kp_o(12), angle_pi_kp_i(11) => 
        apb3_if_0_angle_kp_o(11), angle_pi_kp_i(10) => 
        apb3_if_0_angle_kp_o(10), angle_pi_kp_i(9) => 
        apb3_if_0_angle_kp_o(9), angle_pi_kp_i(8) => 
        apb3_if_0_angle_kp_o(8), angle_pi_kp_i(7) => 
        apb3_if_0_angle_kp_o(7), angle_pi_kp_i(6) => 
        apb3_if_0_angle_kp_o(6), angle_pi_kp_i(5) => 
        apb3_if_0_angle_kp_o(5), angle_pi_kp_i(4) => 
        apb3_if_0_angle_kp_o(4), angle_pi_kp_i(3) => 
        apb3_if_0_angle_kp_o(3), angle_pi_kp_i(2) => 
        apb3_if_0_angle_kp_o(2), angle_pi_kp_i(1) => 
        apb3_if_0_angle_kp_o(1), angle_pi_kp_i(0) => 
        apb3_if_0_angle_kp_o(0), omega_filter_factor_i(3) => 
        apb3_if_0_filter_factor_omega_o(3), 
        omega_filter_factor_i(2) => 
        apb3_if_0_filter_factor_omega_o(2), 
        omega_filter_factor_i(1) => 
        apb3_if_0_filter_factor_omega_o(1), 
        omega_filter_factor_i(0) => 
        apb3_if_0_filter_factor_omega_o(0), done_o => done_o_0, 
        theta_o(17) => BLDC_ESTIMATOR_1_theta_o(17), theta_o(16)
         => BLDC_ESTIMATOR_1_theta_o(16), theta_o(15) => 
        BLDC_ESTIMATOR_1_theta_o(15), theta_o(14) => 
        BLDC_ESTIMATOR_1_theta_o(14), theta_o(13) => 
        BLDC_ESTIMATOR_1_theta_o(13), theta_o(12) => 
        BLDC_ESTIMATOR_1_theta_o(12), theta_o(11) => 
        BLDC_ESTIMATOR_1_theta_o(11), theta_o(10) => 
        BLDC_ESTIMATOR_1_theta_o(10), theta_o(9) => 
        BLDC_ESTIMATOR_1_theta_o(9), theta_o(8) => 
        BLDC_ESTIMATOR_1_theta_o(8), theta_o(7) => 
        BLDC_ESTIMATOR_1_theta_o(7), theta_o(6) => 
        BLDC_ESTIMATOR_1_theta_o(6), theta_o(5) => 
        BLDC_ESTIMATOR_1_theta_o(5), theta_o(4) => 
        BLDC_ESTIMATOR_1_theta_o(4), theta_o(3) => 
        BLDC_ESTIMATOR_1_theta_o(3), theta_o(2) => 
        BLDC_ESTIMATOR_1_theta_o(2), theta_o(1) => 
        BLDC_ESTIMATOR_1_theta_o(1), theta_o(0) => 
        BLDC_ESTIMATOR_1_theta_o(0), ealpha_o(17) => 
        BLDC_ESTIMATOR_1_ealpha_o(17), ealpha_o(16) => 
        BLDC_ESTIMATOR_1_ealpha_o(16), ealpha_o(15) => 
        BLDC_ESTIMATOR_1_ealpha_o(15), ealpha_o(14) => 
        BLDC_ESTIMATOR_1_ealpha_o(14), ealpha_o(13) => 
        BLDC_ESTIMATOR_1_ealpha_o(13), ealpha_o(12) => 
        BLDC_ESTIMATOR_1_ealpha_o(12), ealpha_o(11) => 
        BLDC_ESTIMATOR_1_ealpha_o(11), ealpha_o(10) => 
        BLDC_ESTIMATOR_1_ealpha_o(10), ealpha_o(9) => 
        BLDC_ESTIMATOR_1_ealpha_o(9), ealpha_o(8) => 
        BLDC_ESTIMATOR_1_ealpha_o(8), ealpha_o(7) => 
        BLDC_ESTIMATOR_1_ealpha_o(7), ealpha_o(6) => 
        BLDC_ESTIMATOR_1_ealpha_o(6), ealpha_o(5) => 
        BLDC_ESTIMATOR_1_ealpha_o(5), ealpha_o(4) => 
        BLDC_ESTIMATOR_1_ealpha_o(4), ealpha_o(3) => 
        BLDC_ESTIMATOR_1_ealpha_o(3), ealpha_o(2) => 
        BLDC_ESTIMATOR_1_ealpha_o(2), ealpha_o(1) => 
        BLDC_ESTIMATOR_1_ealpha_o(1), ealpha_o(0) => 
        BLDC_ESTIMATOR_1_ealpha_o(0), ebeta_o(17) => 
        BLDC_ESTIMATOR_1_ebeta_o(17), ebeta_o(16) => 
        BLDC_ESTIMATOR_1_ebeta_o(16), ebeta_o(15) => 
        BLDC_ESTIMATOR_1_ebeta_o(15), ebeta_o(14) => 
        BLDC_ESTIMATOR_1_ebeta_o(14), ebeta_o(13) => 
        BLDC_ESTIMATOR_1_ebeta_o(13), ebeta_o(12) => 
        BLDC_ESTIMATOR_1_ebeta_o(12), ebeta_o(11) => 
        BLDC_ESTIMATOR_1_ebeta_o(11), ebeta_o(10) => 
        BLDC_ESTIMATOR_1_ebeta_o(10), ebeta_o(9) => 
        BLDC_ESTIMATOR_1_ebeta_o(9), ebeta_o(8) => 
        BLDC_ESTIMATOR_1_ebeta_o(8), ebeta_o(7) => 
        BLDC_ESTIMATOR_1_ebeta_o(7), ebeta_o(6) => 
        BLDC_ESTIMATOR_1_ebeta_o(6), ebeta_o(5) => 
        BLDC_ESTIMATOR_1_ebeta_o(5), ebeta_o(4) => 
        BLDC_ESTIMATOR_1_ebeta_o(4), ebeta_o(3) => 
        BLDC_ESTIMATOR_1_ebeta_o(3), ebeta_o(2) => 
        BLDC_ESTIMATOR_1_ebeta_o(2), ebeta_o(1) => 
        BLDC_ESTIMATOR_1_ebeta_o(1), ebeta_o(0) => 
        BLDC_ESTIMATOR_1_ebeta_o(0), ealpha_filtered_o(17) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(17), 
        ealpha_filtered_o(16) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(16), 
        ealpha_filtered_o(15) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(15), 
        ealpha_filtered_o(14) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(14), 
        ealpha_filtered_o(13) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(13), 
        ealpha_filtered_o(12) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(12), 
        ealpha_filtered_o(11) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(11), 
        ealpha_filtered_o(10) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(10), 
        ealpha_filtered_o(9) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(9), 
        ealpha_filtered_o(8) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(8), 
        ealpha_filtered_o(7) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(7), 
        ealpha_filtered_o(6) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(6), 
        ealpha_filtered_o(5) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(5), 
        ealpha_filtered_o(4) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(4), 
        ealpha_filtered_o(3) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(3), 
        ealpha_filtered_o(2) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(2), 
        ealpha_filtered_o(1) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(1), 
        ealpha_filtered_o(0) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(0), 
        ebeta_filtered_o(17) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(17), 
        ebeta_filtered_o(16) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(16), 
        ebeta_filtered_o(15) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(15), 
        ebeta_filtered_o(14) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(14), 
        ebeta_filtered_o(13) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(13), 
        ebeta_filtered_o(12) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(12), 
        ebeta_filtered_o(11) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(11), 
        ebeta_filtered_o(10) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(10), 
        ebeta_filtered_o(9) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(9), ebeta_filtered_o(8)
         => BLDC_ESTIMATOR_1_ebeta_filtered_o(8), 
        ebeta_filtered_o(7) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(7), ebeta_filtered_o(6)
         => BLDC_ESTIMATOR_1_ebeta_filtered_o(6), 
        ebeta_filtered_o(5) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(5), ebeta_filtered_o(4)
         => BLDC_ESTIMATOR_1_ebeta_filtered_o(4), 
        ebeta_filtered_o(3) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(3), ebeta_filtered_o(2)
         => BLDC_ESTIMATOR_1_ebeta_filtered_o(2), 
        ebeta_filtered_o(1) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(1), ebeta_filtered_o(0)
         => BLDC_ESTIMATOR_1_ebeta_filtered_o(0), 
        pll_pi_out_o(17) => BLDC_ESTIMATOR_1_pll_pi_out_o(17), 
        pll_pi_out_o(16) => BLDC_ESTIMATOR_1_pll_pi_out_o(16), 
        pll_pi_out_o(15) => BLDC_ESTIMATOR_1_pll_pi_out_o(15), 
        pll_pi_out_o(14) => BLDC_ESTIMATOR_1_pll_pi_out_o(14), 
        pll_pi_out_o(13) => BLDC_ESTIMATOR_1_pll_pi_out_o(13), 
        pll_pi_out_o(12) => BLDC_ESTIMATOR_1_pll_pi_out_o(12), 
        pll_pi_out_o(11) => BLDC_ESTIMATOR_1_pll_pi_out_o(11), 
        pll_pi_out_o(10) => BLDC_ESTIMATOR_1_pll_pi_out_o(10), 
        pll_pi_out_o(9) => BLDC_ESTIMATOR_1_pll_pi_out_o(9), 
        pll_pi_out_o(8) => BLDC_ESTIMATOR_1_pll_pi_out_o(8), 
        pll_pi_out_o(7) => BLDC_ESTIMATOR_1_pll_pi_out_o(7), 
        pll_pi_out_o(6) => BLDC_ESTIMATOR_1_pll_pi_out_o(6), 
        pll_pi_out_o(5) => BLDC_ESTIMATOR_1_pll_pi_out_o(5), 
        pll_pi_out_o(4) => BLDC_ESTIMATOR_1_pll_pi_out_o(4), 
        pll_pi_out_o(3) => BLDC_ESTIMATOR_1_pll_pi_out_o(3), 
        pll_pi_out_o(2) => BLDC_ESTIMATOR_1_pll_pi_out_o(2), 
        pll_pi_out_o(1) => BLDC_ESTIMATOR_1_pll_pi_out_o(1), 
        pll_pi_out_o(0) => BLDC_ESTIMATOR_1_pll_pi_out_o(0), 
        speed_filtered_o(17) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(17), 
        speed_filtered_o(16) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(16), 
        speed_filtered_o(15) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(15), 
        speed_filtered_o(14) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(14), 
        speed_filtered_o(13) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(13), 
        speed_filtered_o(12) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(12), 
        speed_filtered_o(11) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(11), 
        speed_filtered_o(10) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(10), 
        speed_filtered_o(9) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(9), speed_filtered_o(8)
         => BLDC_ESTIMATOR_0_speed_filtered_o(8), 
        speed_filtered_o(7) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(7), speed_filtered_o(6)
         => BLDC_ESTIMATOR_0_speed_filtered_o(6), 
        speed_filtered_o(5) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(5), speed_filtered_o(4)
         => BLDC_ESTIMATOR_0_speed_filtered_o(4), 
        speed_filtered_o(3) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(3), speed_filtered_o(2)
         => BLDC_ESTIMATOR_0_speed_filtered_o(2), 
        speed_filtered_o(1) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(1), speed_filtered_o(0)
         => BLDC_ESTIMATOR_0_speed_filtered_o(0));
    
    MSC_i_11 : SEQ_CONTROLLER_0
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, fault_i => 
        ADC_SCALING_1_over_current_fault_o, start_motor_i => 
        apb3_if_0_start_motor_o, stop_motor_i => 
        apb3_if_0_stop_motor_o, fault_clear_i => 
        apb3_if_0_fault_clr_o, speed_ref_i(17) => 
        RATE_LIMITER_0_rl_out_o(17), speed_ref_i(16) => 
        RATE_LIMITER_0_rl_out_o(16), speed_ref_i(15) => 
        RATE_LIMITER_0_rl_out_o(15), speed_ref_i(14) => 
        RATE_LIMITER_0_rl_out_o(14), speed_ref_i(13) => 
        RATE_LIMITER_0_rl_out_o(13), speed_ref_i(12) => 
        RATE_LIMITER_0_rl_out_o(12), speed_ref_i(11) => 
        RATE_LIMITER_0_rl_out_o(11), speed_ref_i(10) => 
        RATE_LIMITER_0_rl_out_o(10), speed_ref_i(9) => 
        RATE_LIMITER_0_rl_out_o(9), speed_ref_i(8) => 
        RATE_LIMITER_0_rl_out_o(8), speed_ref_i(7) => 
        RATE_LIMITER_0_rl_out_o(7), speed_ref_i(6) => 
        RATE_LIMITER_0_rl_out_o(6), speed_ref_i(5) => 
        RATE_LIMITER_0_rl_out_o(5), speed_ref_i(4) => 
        RATE_LIMITER_0_rl_out_o(4), speed_ref_i(3) => 
        RATE_LIMITER_0_rl_out_o(3), speed_ref_i(2) => 
        RATE_LIMITER_0_rl_out_o(2), speed_ref_i(1) => 
        RATE_LIMITER_0_rl_out_o(1), speed_ref_i(0) => 
        RATE_LIMITER_0_rl_out_o(0), speed_cl_i(17) => 
        apb3_if_0_seq_cntl_cl_omega_o(17), speed_cl_i(16) => 
        apb3_if_0_seq_cntl_cl_omega_o(16), speed_cl_i(15) => 
        apb3_if_0_seq_cntl_cl_omega_o(15), speed_cl_i(14) => 
        apb3_if_0_seq_cntl_cl_omega_o(14), speed_cl_i(13) => 
        apb3_if_0_seq_cntl_cl_omega_o(13), speed_cl_i(12) => 
        apb3_if_0_seq_cntl_cl_omega_o(12), speed_cl_i(11) => 
        apb3_if_0_seq_cntl_cl_omega_o(11), speed_cl_i(10) => 
        apb3_if_0_seq_cntl_cl_omega_o(10), speed_cl_i(9) => 
        apb3_if_0_seq_cntl_cl_omega_o(9), speed_cl_i(8) => 
        apb3_if_0_seq_cntl_cl_omega_o(8), speed_cl_i(7) => 
        apb3_if_0_seq_cntl_cl_omega_o(7), speed_cl_i(6) => 
        apb3_if_0_seq_cntl_cl_omega_o(6), speed_cl_i(5) => 
        apb3_if_0_seq_cntl_cl_omega_o(5), speed_cl_i(4) => 
        apb3_if_0_seq_cntl_cl_omega_o(4), speed_cl_i(3) => 
        apb3_if_0_seq_cntl_cl_omega_o(3), speed_cl_i(2) => 
        apb3_if_0_seq_cntl_cl_omega_o(2), speed_cl_i(1) => 
        apb3_if_0_seq_cntl_cl_omega_o(1), speed_cl_i(0) => 
        apb3_if_0_seq_cntl_cl_omega_o(0), vq_i(17) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(17), vq_i(16) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(16), vq_i(15) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(15), vq_i(14) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(14), vq_i(13) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(13), vq_i(12) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(12), vq_i(11) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(11), vq_i(10) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(10), vq_i(9) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(9), vq_i(8) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(8), vq_i(7) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(7), vq_i(6) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(6), vq_i(5) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(5), vq_i(4) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(4), vq_i(3) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(3), vq_i(2) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(2), vq_i(1) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1), vq_i(0) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0), max_ar_i(3) => 
        apb3_if_0_auto_restart_no_o(3), max_ar_i(2) => 
        apb3_if_0_auto_restart_no_o(2), max_ar_i(1) => 
        apb3_if_0_auto_restart_no_o(1), max_ar_i(0) => 
        apb3_if_0_auto_restart_no_o(0), calib_done_i => 
        ADC_SCALING_1_calib_done_o, pwm_midmatch_i => 
        PWM3PH_1_midmatch_o, foc_done_i => PWM_SCALING_1_done_o, 
        config_reg_i(3) => apb3_if_0_seq_cntl_config_o(3), 
        config_reg_i(2) => apb3_if_0_seq_cntl_config_o(2), 
        config_reg_i(1) => apb3_if_0_seq_cntl_config_o(1), 
        config_reg_i(0) => apb3_if_0_seq_cntl_config_o(0), 
        adc_start_o => SEQ_CONTROLLER_1_adc_start_o, cl_status_o
         => SEQ_CONTROLLER_0_cl_status_o, en_idq_pi_o => 
        SEQ_CONTROLLER_0_en_idq_pi_o, en_pwm_o => \A0_PWM_VL_O_c\, 
        motor_stopped_o => SEQ_CONTROLLER_0_motor_stopped_o, 
        reset_rl_o => SEQ_CONTROLLER_0_reset_rl_o, soft_stop_o
         => SEQ_CONTROLLER_0_soft_stop_o, sensor_reset_o => 
        sensor_reset_o_0, state_o(3) => 
        SEQ_CONTROLLER_1_state_o_3, state_o(2) => 
        SEQ_CONTROLLER_1_state_o(2), state_o(1) => 
        SEQ_CONTROLLER_1_state_o_1, state_o(0) => 
        SEQ_CONTROLLER_1_state_o(0));
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MSC_i_1 : FOC_TRANSFORMS_0
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_clarke_i => 
        ADC_SCALING_0_done_o, start_park_i => 
        FOC_TRANSFORMS_1_clarke_done_o_0, start_ipark_i => 
        SPEED_ID_IQ_PI_1_id_pi_done_o, start_iclarke_i => 
        FOC_TRANSFORMS_0_ipark_done_o, ia_i(17) => 
        ADC_SCALING_1_ia_adc_o(17), ia_i(16) => 
        ADC_SCALING_1_ia_adc_o(16), ia_i(15) => 
        ADC_SCALING_1_ia_adc_o(15), ia_i(14) => 
        ADC_SCALING_1_ia_adc_o(14), ia_i(13) => 
        ADC_SCALING_1_ia_adc_o(13), ia_i(12) => 
        ADC_SCALING_1_ia_adc_o(12), ia_i(11) => 
        ADC_SCALING_1_ia_adc_o(11), ia_i(10) => 
        ADC_SCALING_1_ia_adc_o(10), ia_i(9) => 
        ADC_SCALING_1_ia_adc_o(9), ia_i(8) => 
        ADC_SCALING_1_ia_adc_o(8), ia_i(7) => 
        ADC_SCALING_1_ia_adc_o(7), ia_i(6) => 
        ADC_SCALING_1_ia_adc_o(6), ia_i(5) => 
        ADC_SCALING_1_ia_adc_o(5), ia_i(4) => 
        ADC_SCALING_1_ia_adc_o(4), ia_i(3) => 
        ADC_SCALING_1_ia_adc_o(3), ia_i(2) => 
        ADC_SCALING_1_ia_adc_o(2), ia_i(1) => 
        ADC_SCALING_1_ia_adc_o(1), ia_i(0) => 
        ADC_SCALING_1_ia_adc_o(0), ib_i(17) => 
        ADC_SCALING_1_ib_adc_o(17), ib_i(16) => 
        ADC_SCALING_1_ib_adc_o(16), ib_i(15) => 
        ADC_SCALING_1_ib_adc_o(15), ib_i(14) => 
        ADC_SCALING_1_ib_adc_o(14), ib_i(13) => 
        ADC_SCALING_1_ib_adc_o(13), ib_i(12) => 
        ADC_SCALING_1_ib_adc_o(12), ib_i(11) => 
        ADC_SCALING_1_ib_adc_o(11), ib_i(10) => 
        ADC_SCALING_1_ib_adc_o(10), ib_i(9) => 
        ADC_SCALING_1_ib_adc_o(9), ib_i(8) => 
        ADC_SCALING_1_ib_adc_o(8), ib_i(7) => 
        ADC_SCALING_1_ib_adc_o(7), ib_i(6) => 
        ADC_SCALING_1_ib_adc_o(6), ib_i(5) => 
        ADC_SCALING_1_ib_adc_o(5), ib_i(4) => 
        ADC_SCALING_1_ib_adc_o(4), ib_i(3) => 
        ADC_SCALING_1_ib_adc_o(3), ib_i(2) => 
        ADC_SCALING_1_ib_adc_o(2), ib_i(1) => 
        ADC_SCALING_1_ib_adc_o(1), ib_i(0) => 
        ADC_SCALING_1_ib_adc_o(0), ialpha_i(17) => 
        FOC_TRANSFORMS_0_ialpha_o(17), ialpha_i(16) => 
        FOC_TRANSFORMS_0_ialpha_o(16), ialpha_i(15) => 
        FOC_TRANSFORMS_0_ialpha_o(15), ialpha_i(14) => 
        FOC_TRANSFORMS_0_ialpha_o(14), ialpha_i(13) => 
        FOC_TRANSFORMS_0_ialpha_o(13), ialpha_i(12) => 
        FOC_TRANSFORMS_0_ialpha_o(12), ialpha_i(11) => 
        FOC_TRANSFORMS_0_ialpha_o(11), ialpha_i(10) => 
        FOC_TRANSFORMS_0_ialpha_o(10), ialpha_i(9) => 
        FOC_TRANSFORMS_0_ialpha_o(9), ialpha_i(8) => 
        FOC_TRANSFORMS_0_ialpha_o(8), ialpha_i(7) => 
        FOC_TRANSFORMS_0_ialpha_o(7), ialpha_i(6) => 
        FOC_TRANSFORMS_0_ialpha_o(6), ialpha_i(5) => 
        FOC_TRANSFORMS_0_ialpha_o(5), ialpha_i(4) => 
        FOC_TRANSFORMS_0_ialpha_o(4), ialpha_i(3) => 
        FOC_TRANSFORMS_0_ialpha_o(3), ialpha_i(2) => 
        FOC_TRANSFORMS_0_ialpha_o(2), ialpha_i(1) => 
        FOC_TRANSFORMS_0_ialpha_o(1), ialpha_i(0) => \GND\, 
        ibeta_i(17) => FOC_TRANSFORMS_0_ibeta_o(17), ibeta_i(16)
         => FOC_TRANSFORMS_0_ibeta_o(16), ibeta_i(15) => 
        FOC_TRANSFORMS_0_ibeta_o(15), ibeta_i(14) => 
        FOC_TRANSFORMS_0_ibeta_o(14), ibeta_i(13) => 
        FOC_TRANSFORMS_0_ibeta_o(13), ibeta_i(12) => 
        FOC_TRANSFORMS_0_ibeta_o(12), ibeta_i(11) => 
        FOC_TRANSFORMS_0_ibeta_o(11), ibeta_i(10) => 
        FOC_TRANSFORMS_0_ibeta_o(10), ibeta_i(9) => 
        FOC_TRANSFORMS_0_ibeta_o(9), ibeta_i(8) => 
        FOC_TRANSFORMS_0_ibeta_o(8), ibeta_i(7) => 
        FOC_TRANSFORMS_0_ibeta_o(7), ibeta_i(6) => 
        FOC_TRANSFORMS_0_ibeta_o(6), ibeta_i(5) => 
        FOC_TRANSFORMS_0_ibeta_o(5), ibeta_i(4) => 
        FOC_TRANSFORMS_0_ibeta_o(4), ibeta_i(3) => 
        FOC_TRANSFORMS_0_ibeta_o(3), ibeta_i(2) => 
        FOC_TRANSFORMS_0_ibeta_o(2), ibeta_i(1) => 
        FOC_TRANSFORMS_0_ibeta_o(1), ibeta_i(0) => \GND\, 
        vd_i(17) => SPEED_ID_IQ_PI_1_id_pi_output_o(17), vd_i(16)
         => SPEED_ID_IQ_PI_1_id_pi_output_o(16), vd_i(15) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(15), vd_i(14) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(14), vd_i(13) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(13), vd_i(12) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(12), vd_i(11) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(11), vd_i(10) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(10), vd_i(9) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(9), vd_i(8) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(8), vd_i(7) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(7), vd_i(6) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(6), vd_i(5) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(5), vd_i(4) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(4), vd_i(3) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(3), vd_i(2) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(2), vd_i(1) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1), vd_i(0) => \GND\, 
        vq_i(17) => SPEED_ID_IQ_PI_1_iq_pi_output_o(17), vq_i(16)
         => SPEED_ID_IQ_PI_1_iq_pi_output_o(16), vq_i(15) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(15), vq_i(14) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(14), vq_i(13) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(13), vq_i(12) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(12), vq_i(11) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(11), vq_i(10) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(10), vq_i(9) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(9), vq_i(8) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(8), vq_i(7) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(7), vq_i(6) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(6), vq_i(5) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(5), vq_i(4) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(4), vq_i(3) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(3), vq_i(2) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(2), vq_i(1) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1), vq_i(0) => \GND\, 
        valpha_i(17) => FOC_TRANSFORMS_0_valpha_o(17), 
        valpha_i(16) => FOC_TRANSFORMS_0_valpha_o(16), 
        valpha_i(15) => FOC_TRANSFORMS_0_valpha_o(15), 
        valpha_i(14) => FOC_TRANSFORMS_0_valpha_o(14), 
        valpha_i(13) => FOC_TRANSFORMS_0_valpha_o(13), 
        valpha_i(12) => FOC_TRANSFORMS_0_valpha_o(12), 
        valpha_i(11) => FOC_TRANSFORMS_0_valpha_o(11), 
        valpha_i(10) => FOC_TRANSFORMS_0_valpha_o(10), 
        valpha_i(9) => FOC_TRANSFORMS_0_valpha_o(9), valpha_i(8)
         => FOC_TRANSFORMS_0_valpha_o(8), valpha_i(7) => 
        FOC_TRANSFORMS_0_valpha_o(7), valpha_i(6) => 
        FOC_TRANSFORMS_0_valpha_o(6), valpha_i(5) => 
        FOC_TRANSFORMS_0_valpha_o(5), valpha_i(4) => 
        FOC_TRANSFORMS_0_valpha_o(4), valpha_i(3) => 
        FOC_TRANSFORMS_0_valpha_o(3), valpha_i(2) => 
        FOC_TRANSFORMS_0_valpha_o(2), valpha_i(1) => 
        FOC_TRANSFORMS_0_valpha_o(1), valpha_i(0) => 
        FOC_TRANSFORMS_0_valpha_o(0), vbeta_i(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), vbeta_i(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), vbeta_i(15) => 
        FOC_TRANSFORMS_0_vbeta_o(15), vbeta_i(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), vbeta_i(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), vbeta_i(12) => 
        FOC_TRANSFORMS_0_vbeta_o(12), vbeta_i(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), vbeta_i(10) => 
        FOC_TRANSFORMS_0_vbeta_o(10), vbeta_i(9) => 
        FOC_TRANSFORMS_0_vbeta_o(9), vbeta_i(8) => 
        FOC_TRANSFORMS_0_vbeta_o(8), vbeta_i(7) => 
        FOC_TRANSFORMS_0_vbeta_o(7), vbeta_i(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), vbeta_i(5) => 
        FOC_TRANSFORMS_0_vbeta_o(5), vbeta_i(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), vbeta_i(3) => 
        FOC_TRANSFORMS_0_vbeta_o(3), vbeta_i(2) => 
        FOC_TRANSFORMS_0_vbeta_o(2), vbeta_i(1) => 
        FOC_TRANSFORMS_0_vbeta_o(1), vbeta_i(0) => 
        FOC_TRANSFORMS_0_vbeta_o(0), theta_i(17) => 
        OLMNG_1_theta_o(17), theta_i(16) => OLMNG_1_theta_o(16), 
        theta_i(15) => OLMNG_1_theta_o(15), theta_i(14) => 
        OLMNG_1_theta_o(14), theta_i(13) => OLMNG_1_theta_o(13), 
        theta_i(12) => OLMNG_1_theta_o(12), theta_i(11) => 
        OLMNG_1_theta_o(11), theta_i(10) => OLMNG_1_theta_o(10), 
        theta_i(9) => OLMNG_1_theta_o(9), theta_i(8) => 
        OLMNG_1_theta_o(8), theta_i(7) => OLMNG_1_theta_o(7), 
        theta_i(6) => OLMNG_1_theta_o(6), theta_i(5) => 
        OLMNG_1_theta_o(5), theta_i(4) => OLMNG_1_theta_o(4), 
        theta_i(3) => OLMNG_1_theta_o(3), theta_i(2) => 
        OLMNG_1_theta_o(2), theta_i(1) => OLMNG_1_theta_o(1), 
        theta_i(0) => OLMNG_1_theta_o(0), clarke_done_o => 
        FOC_TRANSFORMS_1_clarke_done_o_0, park_done_o => 
        FOC_TRANSFORMS_0_park_done_o, ipark_done_o => 
        FOC_TRANSFORMS_0_ipark_done_o, iclarke_done_o => 
        FOC_TRANSFORMS_0_iclarke_done_o, ialpha_o(17) => 
        FOC_TRANSFORMS_0_ialpha_o(17), ialpha_o(16) => 
        FOC_TRANSFORMS_0_ialpha_o(16), ialpha_o(15) => 
        FOC_TRANSFORMS_0_ialpha_o(15), ialpha_o(14) => 
        FOC_TRANSFORMS_0_ialpha_o(14), ialpha_o(13) => 
        FOC_TRANSFORMS_0_ialpha_o(13), ialpha_o(12) => 
        FOC_TRANSFORMS_0_ialpha_o(12), ialpha_o(11) => 
        FOC_TRANSFORMS_0_ialpha_o(11), ialpha_o(10) => 
        FOC_TRANSFORMS_0_ialpha_o(10), ialpha_o(9) => 
        FOC_TRANSFORMS_0_ialpha_o(9), ialpha_o(8) => 
        FOC_TRANSFORMS_0_ialpha_o(8), ialpha_o(7) => 
        FOC_TRANSFORMS_0_ialpha_o(7), ialpha_o(6) => 
        FOC_TRANSFORMS_0_ialpha_o(6), ialpha_o(5) => 
        FOC_TRANSFORMS_0_ialpha_o(5), ialpha_o(4) => 
        FOC_TRANSFORMS_0_ialpha_o(4), ialpha_o(3) => 
        FOC_TRANSFORMS_0_ialpha_o(3), ialpha_o(2) => 
        FOC_TRANSFORMS_0_ialpha_o(2), ialpha_o(1) => 
        FOC_TRANSFORMS_0_ialpha_o(1), ialpha_o(0) => 
        FOC_TRANSFORMS_0_ialpha_o(0), ibeta_o(17) => 
        FOC_TRANSFORMS_0_ibeta_o(17), ibeta_o(16) => 
        FOC_TRANSFORMS_0_ibeta_o(16), ibeta_o(15) => 
        FOC_TRANSFORMS_0_ibeta_o(15), ibeta_o(14) => 
        FOC_TRANSFORMS_0_ibeta_o(14), ibeta_o(13) => 
        FOC_TRANSFORMS_0_ibeta_o(13), ibeta_o(12) => 
        FOC_TRANSFORMS_0_ibeta_o(12), ibeta_o(11) => 
        FOC_TRANSFORMS_0_ibeta_o(11), ibeta_o(10) => 
        FOC_TRANSFORMS_0_ibeta_o(10), ibeta_o(9) => 
        FOC_TRANSFORMS_0_ibeta_o(9), ibeta_o(8) => 
        FOC_TRANSFORMS_0_ibeta_o(8), ibeta_o(7) => 
        FOC_TRANSFORMS_0_ibeta_o(7), ibeta_o(6) => 
        FOC_TRANSFORMS_0_ibeta_o(6), ibeta_o(5) => 
        FOC_TRANSFORMS_0_ibeta_o(5), ibeta_o(4) => 
        FOC_TRANSFORMS_0_ibeta_o(4), ibeta_o(3) => 
        FOC_TRANSFORMS_0_ibeta_o(3), ibeta_o(2) => 
        FOC_TRANSFORMS_0_ibeta_o(2), ibeta_o(1) => 
        FOC_TRANSFORMS_0_ibeta_o(1), ibeta_o(0) => 
        FOC_TRANSFORMS_0_ibeta_o(0), id_o(17) => 
        FOC_TRANSFORMS_0_id_o(17), id_o(16) => 
        FOC_TRANSFORMS_0_id_o(16), id_o(15) => 
        FOC_TRANSFORMS_0_id_o(15), id_o(14) => 
        FOC_TRANSFORMS_0_id_o(14), id_o(13) => 
        FOC_TRANSFORMS_0_id_o(13), id_o(12) => 
        FOC_TRANSFORMS_0_id_o(12), id_o(11) => 
        FOC_TRANSFORMS_0_id_o(11), id_o(10) => 
        FOC_TRANSFORMS_0_id_o(10), id_o(9) => 
        FOC_TRANSFORMS_0_id_o(9), id_o(8) => 
        FOC_TRANSFORMS_0_id_o(8), id_o(7) => 
        FOC_TRANSFORMS_0_id_o(7), id_o(6) => 
        FOC_TRANSFORMS_0_id_o(6), id_o(5) => 
        FOC_TRANSFORMS_0_id_o(5), id_o(4) => 
        FOC_TRANSFORMS_0_id_o(4), id_o(3) => 
        FOC_TRANSFORMS_0_id_o(3), id_o(2) => 
        FOC_TRANSFORMS_0_id_o(2), id_o(1) => 
        FOC_TRANSFORMS_0_id_o(1), id_o(0) => 
        FOC_TRANSFORMS_0_id_o(0), iq_o(17) => 
        FOC_TRANSFORMS_0_iq_o(17), iq_o(16) => 
        FOC_TRANSFORMS_0_iq_o(16), iq_o(15) => 
        FOC_TRANSFORMS_0_iq_o(15), iq_o(14) => 
        FOC_TRANSFORMS_0_iq_o(14), iq_o(13) => 
        FOC_TRANSFORMS_0_iq_o(13), iq_o(12) => 
        FOC_TRANSFORMS_0_iq_o(12), iq_o(11) => 
        FOC_TRANSFORMS_0_iq_o(11), iq_o(10) => 
        FOC_TRANSFORMS_0_iq_o(10), iq_o(9) => 
        FOC_TRANSFORMS_0_iq_o(9), iq_o(8) => 
        FOC_TRANSFORMS_0_iq_o(8), iq_o(7) => 
        FOC_TRANSFORMS_0_iq_o(7), iq_o(6) => 
        FOC_TRANSFORMS_0_iq_o(6), iq_o(5) => 
        FOC_TRANSFORMS_0_iq_o(5), iq_o(4) => 
        FOC_TRANSFORMS_0_iq_o(4), iq_o(3) => 
        FOC_TRANSFORMS_0_iq_o(3), iq_o(2) => 
        FOC_TRANSFORMS_0_iq_o(2), iq_o(1) => 
        FOC_TRANSFORMS_0_iq_o(1), iq_o(0) => 
        FOC_TRANSFORMS_0_iq_o(0), valpha_o(17) => 
        FOC_TRANSFORMS_0_valpha_o(17), valpha_o(16) => 
        FOC_TRANSFORMS_0_valpha_o(16), valpha_o(15) => 
        FOC_TRANSFORMS_0_valpha_o(15), valpha_o(14) => 
        FOC_TRANSFORMS_0_valpha_o(14), valpha_o(13) => 
        FOC_TRANSFORMS_0_valpha_o(13), valpha_o(12) => 
        FOC_TRANSFORMS_0_valpha_o(12), valpha_o(11) => 
        FOC_TRANSFORMS_0_valpha_o(11), valpha_o(10) => 
        FOC_TRANSFORMS_0_valpha_o(10), valpha_o(9) => 
        FOC_TRANSFORMS_0_valpha_o(9), valpha_o(8) => 
        FOC_TRANSFORMS_0_valpha_o(8), valpha_o(7) => 
        FOC_TRANSFORMS_0_valpha_o(7), valpha_o(6) => 
        FOC_TRANSFORMS_0_valpha_o(6), valpha_o(5) => 
        FOC_TRANSFORMS_0_valpha_o(5), valpha_o(4) => 
        FOC_TRANSFORMS_0_valpha_o(4), valpha_o(3) => 
        FOC_TRANSFORMS_0_valpha_o(3), valpha_o(2) => 
        FOC_TRANSFORMS_0_valpha_o(2), valpha_o(1) => 
        FOC_TRANSFORMS_0_valpha_o(1), valpha_o(0) => 
        FOC_TRANSFORMS_0_valpha_o(0), vbeta_o(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), vbeta_o(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), vbeta_o(15) => 
        FOC_TRANSFORMS_0_vbeta_o(15), vbeta_o(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), vbeta_o(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), vbeta_o(12) => 
        FOC_TRANSFORMS_0_vbeta_o(12), vbeta_o(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), vbeta_o(10) => 
        FOC_TRANSFORMS_0_vbeta_o(10), vbeta_o(9) => 
        FOC_TRANSFORMS_0_vbeta_o(9), vbeta_o(8) => 
        FOC_TRANSFORMS_0_vbeta_o(8), vbeta_o(7) => 
        FOC_TRANSFORMS_0_vbeta_o(7), vbeta_o(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), vbeta_o(5) => 
        FOC_TRANSFORMS_0_vbeta_o(5), vbeta_o(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), vbeta_o(3) => 
        FOC_TRANSFORMS_0_vbeta_o(3), vbeta_o(2) => 
        FOC_TRANSFORMS_0_vbeta_o(2), vbeta_o(1) => 
        FOC_TRANSFORMS_0_vbeta_o(1), vbeta_o(0) => 
        FOC_TRANSFORMS_0_vbeta_o(0), va_o(17) => 
        FOC_TRANSFORMS_0_va_o(17), va_o(16) => 
        FOC_TRANSFORMS_0_va_o(16), va_o(15) => 
        FOC_TRANSFORMS_0_va_o(15), va_o(14) => 
        FOC_TRANSFORMS_0_va_o(14), va_o(13) => 
        FOC_TRANSFORMS_0_va_o(13), va_o(12) => 
        FOC_TRANSFORMS_0_va_o(12), va_o(11) => 
        FOC_TRANSFORMS_0_va_o(11), va_o(10) => 
        FOC_TRANSFORMS_0_va_o(10), va_o(9) => 
        FOC_TRANSFORMS_0_va_o(9), va_o(8) => 
        FOC_TRANSFORMS_0_va_o(8), va_o(7) => 
        FOC_TRANSFORMS_0_va_o(7), va_o(6) => 
        FOC_TRANSFORMS_0_va_o(6), va_o(5) => 
        FOC_TRANSFORMS_0_va_o(5), va_o(4) => 
        FOC_TRANSFORMS_0_va_o(4), va_o(3) => 
        FOC_TRANSFORMS_0_va_o(3), va_o(2) => 
        FOC_TRANSFORMS_0_va_o(2), va_o(1) => 
        FOC_TRANSFORMS_0_va_o(1), va_o(0) => 
        FOC_TRANSFORMS_0_va_o(0), vb_o(17) => 
        FOC_TRANSFORMS_0_vb_o(17), vb_o(16) => 
        FOC_TRANSFORMS_0_vb_o(16), vb_o(15) => 
        FOC_TRANSFORMS_0_vb_o(15), vb_o(14) => 
        FOC_TRANSFORMS_0_vb_o(14), vb_o(13) => 
        FOC_TRANSFORMS_0_vb_o(13), vb_o(12) => 
        FOC_TRANSFORMS_0_vb_o(12), vb_o(11) => 
        FOC_TRANSFORMS_0_vb_o(11), vb_o(10) => 
        FOC_TRANSFORMS_0_vb_o(10), vb_o(9) => 
        FOC_TRANSFORMS_0_vb_o(9), vb_o(8) => 
        FOC_TRANSFORMS_0_vb_o(8), vb_o(7) => 
        FOC_TRANSFORMS_0_vb_o(7), vb_o(6) => 
        FOC_TRANSFORMS_0_vb_o(6), vb_o(5) => 
        FOC_TRANSFORMS_0_vb_o(5), vb_o(4) => 
        FOC_TRANSFORMS_0_vb_o(4), vb_o(3) => 
        FOC_TRANSFORMS_0_vb_o(3), vb_o(2) => 
        FOC_TRANSFORMS_0_vb_o(2), vb_o(1) => 
        FOC_TRANSFORMS_0_vb_o(1), vb_o(0) => 
        FOC_TRANSFORMS_0_vb_o(0), vc_o(17) => 
        FOC_TRANSFORMS_0_vc_o(17), vc_o(16) => 
        FOC_TRANSFORMS_0_vc_o(16), vc_o(15) => 
        FOC_TRANSFORMS_0_vc_o(15), vc_o(14) => 
        FOC_TRANSFORMS_0_vc_o(14), vc_o(13) => 
        FOC_TRANSFORMS_0_vc_o(13), vc_o(12) => 
        FOC_TRANSFORMS_0_vc_o(12), vc_o(11) => 
        FOC_TRANSFORMS_0_vc_o(11), vc_o(10) => 
        FOC_TRANSFORMS_0_vc_o(10), vc_o(9) => 
        FOC_TRANSFORMS_0_vc_o(9), vc_o(8) => 
        FOC_TRANSFORMS_0_vc_o(8), vc_o(7) => 
        FOC_TRANSFORMS_0_vc_o(7), vc_o(6) => 
        FOC_TRANSFORMS_0_vc_o(6), vc_o(5) => 
        FOC_TRANSFORMS_0_vc_o(5), vc_o(4) => 
        FOC_TRANSFORMS_0_vc_o(4), vc_o(3) => 
        FOC_TRANSFORMS_0_vc_o(3), vc_o(2) => 
        FOC_TRANSFORMS_0_vc_o(2), vc_o(1) => 
        FOC_TRANSFORMS_0_vc_o(1), vc_o(0) => 
        FOC_TRANSFORMS_0_vc_o(0));
    
    SEQ_CONTROLLER_0_reset_rl_o_RNIEI29 : CFG1
      generic map(INIT => "01")

      port map(A => SEQ_CONTROLLER_0_reset_rl_o, Y => 
        SEQ_CONTROLLER_0_reset_rl_o_i_0);
    
    \adc_interface_0\ : adc_interface_0
      port map(apb3_if_0_adc_control_reg_val_o(5) => 
        apb3_if_0_adc_control_reg_val_o(5), 
        apb3_if_0_adc_control_reg_val_o(4) => 
        apb3_if_0_adc_control_reg_val_o(4), 
        apb3_if_0_adc_control_reg_val_o(3) => 
        apb3_if_0_adc_control_reg_val_o(3), 
        apb3_if_0_adc_control_reg_val_o(2) => 
        apb3_if_0_adc_control_reg_val_o(2), 
        apb3_if_0_adc_control_reg_val_o(1) => 
        apb3_if_0_adc_control_reg_val_o(1), 
        apb3_if_0_adc_control_reg_val_o(0) => 
        apb3_if_0_adc_control_reg_val_o(0), 
        adc_interface_0_result_ch0_o(11) => 
        adc_interface_0_result_ch0_o(11), 
        adc_interface_0_result_ch0_o(10) => 
        adc_interface_0_result_ch0_o(10), 
        adc_interface_0_result_ch0_o(9) => 
        adc_interface_0_result_ch0_o(9), 
        adc_interface_0_result_ch0_o(8) => 
        adc_interface_0_result_ch0_o(8), 
        adc_interface_0_result_ch0_o(7) => 
        adc_interface_0_result_ch0_o(7), 
        adc_interface_0_result_ch0_o(6) => 
        adc_interface_0_result_ch0_o(6), 
        adc_interface_0_result_ch0_o(5) => 
        adc_interface_0_result_ch0_o(5), 
        adc_interface_0_result_ch0_o(4) => 
        adc_interface_0_result_ch0_o(4), 
        adc_interface_0_result_ch0_o(3) => 
        adc_interface_0_result_ch0_o(3), 
        adc_interface_0_result_ch0_o(2) => 
        adc_interface_0_result_ch0_o(2), 
        adc_interface_0_result_ch0_o(1) => 
        adc_interface_0_result_ch0_o(1), 
        adc_interface_0_result_ch0_o(0) => 
        adc_interface_0_result_ch0_o(0), 
        adc_interface_0_result_ch1_o(11) => 
        adc_interface_0_result_ch1_o(11), 
        adc_interface_0_result_ch1_o(10) => 
        adc_interface_0_result_ch1_o(10), 
        adc_interface_0_result_ch1_o(9) => 
        adc_interface_0_result_ch1_o(9), 
        adc_interface_0_result_ch1_o(8) => 
        adc_interface_0_result_ch1_o(8), 
        adc_interface_0_result_ch1_o(7) => 
        adc_interface_0_result_ch1_o(7), 
        adc_interface_0_result_ch1_o(6) => 
        adc_interface_0_result_ch1_o(6), 
        adc_interface_0_result_ch1_o(5) => 
        adc_interface_0_result_ch1_o(5), 
        adc_interface_0_result_ch1_o(4) => 
        adc_interface_0_result_ch1_o(4), 
        adc_interface_0_result_ch1_o(3) => 
        adc_interface_0_result_ch1_o(3), 
        adc_interface_0_result_ch1_o(2) => 
        adc_interface_0_result_ch1_o(2), 
        adc_interface_0_result_ch1_o(1) => 
        adc_interface_0_result_ch1_o(1), 
        adc_interface_0_result_ch1_o(0) => 
        adc_interface_0_result_ch1_o(0), 
        adc_measurements_0_adc_result_ch2_o(11) => 
        adc_measurements_0_adc_result_ch2_o(11), 
        adc_measurements_0_adc_result_ch2_o(10) => 
        adc_measurements_0_adc_result_ch2_o(10), 
        adc_measurements_0_adc_result_ch2_o(9) => 
        adc_measurements_0_adc_result_ch2_o(9), 
        adc_measurements_0_adc_result_ch2_o(8) => 
        adc_measurements_0_adc_result_ch2_o(8), 
        adc_measurements_0_adc_result_ch2_o(7) => 
        adc_measurements_0_adc_result_ch2_o(7), 
        adc_measurements_0_adc_result_ch2_o(6) => 
        adc_measurements_0_adc_result_ch2_o(6), 
        adc_measurements_0_adc_result_ch2_o(5) => 
        adc_measurements_0_adc_result_ch2_o(5), 
        adc_measurements_0_adc_result_ch2_o(4) => 
        adc_measurements_0_adc_result_ch2_o(4), 
        adc_measurements_0_adc_result_ch2_o(3) => 
        adc_measurements_0_adc_result_ch2_o(3), 
        adc_measurements_0_adc_result_ch2_o(2) => 
        adc_measurements_0_adc_result_ch2_o(2), 
        adc_measurements_0_adc_result_ch2_o(1) => 
        adc_measurements_0_adc_result_ch2_o(1), 
        adc_measurements_0_adc_result_ch2_o(0) => 
        adc_measurements_0_adc_result_ch2_o(0), 
        adc_measurements_0_adc_result_ch3_o(11) => 
        adc_measurements_0_adc_result_ch3_o(11), 
        adc_measurements_0_adc_result_ch3_o(10) => 
        adc_measurements_0_adc_result_ch3_o(10), 
        adc_measurements_0_adc_result_ch3_o(9) => 
        adc_measurements_0_adc_result_ch3_o(9), 
        adc_measurements_0_adc_result_ch3_o(8) => 
        adc_measurements_0_adc_result_ch3_o(8), 
        adc_measurements_0_adc_result_ch3_o(7) => 
        adc_measurements_0_adc_result_ch3_o(7), 
        adc_measurements_0_adc_result_ch3_o(6) => 
        adc_measurements_0_adc_result_ch3_o(6), 
        adc_measurements_0_adc_result_ch3_o(5) => 
        adc_measurements_0_adc_result_ch3_o(5), 
        adc_measurements_0_adc_result_ch3_o(4) => 
        adc_measurements_0_adc_result_ch3_o(4), 
        adc_measurements_0_adc_result_ch3_o(3) => 
        adc_measurements_0_adc_result_ch3_o(3), 
        adc_measurements_0_adc_result_ch3_o(2) => 
        adc_measurements_0_adc_result_ch3_o(2), 
        adc_measurements_0_adc_result_ch3_o(1) => 
        adc_measurements_0_adc_result_ch3_o(1), 
        adc_measurements_0_adc_result_ch3_o(0) => 
        adc_measurements_0_adc_result_ch3_o(0), 
        apb3_if_0_adc_channel_ch2_o(15) => 
        apb3_if_0_adc_channel_ch2_o(15), 
        apb3_if_0_adc_channel_ch2_o(14) => 
        apb3_if_0_adc_channel_ch2_o(14), 
        apb3_if_0_adc_channel_ch2_o(13) => 
        apb3_if_0_adc_channel_ch2_o(13), 
        apb3_if_0_adc_channel_ch2_o(12) => 
        apb3_if_0_adc_channel_ch2_o(12), 
        apb3_if_0_adc_channel_ch2_o(11) => 
        apb3_if_0_adc_channel_ch2_o(11), 
        apb3_if_0_adc_channel_ch2_o(10) => 
        apb3_if_0_adc_channel_ch2_o(10), 
        apb3_if_0_adc_channel_ch2_o(9) => 
        apb3_if_0_adc_channel_ch2_o(9), 
        apb3_if_0_adc_channel_ch2_o(8) => 
        apb3_if_0_adc_channel_ch2_o(8), 
        apb3_if_0_adc_channel_ch2_o(7) => 
        apb3_if_0_adc_channel_ch2_o(7), 
        apb3_if_0_adc_channel_ch2_o(6) => 
        apb3_if_0_adc_channel_ch2_o(6), 
        apb3_if_0_adc_channel_ch2_o(5) => 
        apb3_if_0_adc_channel_ch2_o(5), 
        apb3_if_0_adc_channel_ch2_o(4) => 
        apb3_if_0_adc_channel_ch2_o(4), 
        apb3_if_0_adc_channel_ch2_o(3) => 
        apb3_if_0_adc_channel_ch2_o(3), 
        apb3_if_0_adc_channel_ch2_o(2) => 
        apb3_if_0_adc_channel_ch2_o(2), 
        apb3_if_0_adc_channel_ch2_o(1) => 
        apb3_if_0_adc_channel_ch2_o(1), 
        apb3_if_0_adc_channel_ch2_o(0) => 
        apb3_if_0_adc_channel_ch2_o(0), 
        apb3_if_0_adc_channel_ch0_o(15) => 
        apb3_if_0_adc_channel_ch0_o(15), 
        apb3_if_0_adc_channel_ch0_o(14) => 
        apb3_if_0_adc_channel_ch0_o(14), 
        apb3_if_0_adc_channel_ch0_o(13) => 
        apb3_if_0_adc_channel_ch0_o(13), 
        apb3_if_0_adc_channel_ch0_o(12) => 
        apb3_if_0_adc_channel_ch0_o(12), 
        apb3_if_0_adc_channel_ch0_o(11) => 
        apb3_if_0_adc_channel_ch0_o(11), 
        apb3_if_0_adc_channel_ch0_o(10) => 
        apb3_if_0_adc_channel_ch0_o(10), 
        apb3_if_0_adc_channel_ch0_o(9) => 
        apb3_if_0_adc_channel_ch0_o(9), 
        apb3_if_0_adc_channel_ch0_o(8) => 
        apb3_if_0_adc_channel_ch0_o(8), 
        apb3_if_0_adc_channel_ch0_o(7) => 
        apb3_if_0_adc_channel_ch0_o(7), 
        apb3_if_0_adc_channel_ch0_o(6) => 
        apb3_if_0_adc_channel_ch0_o(6), 
        apb3_if_0_adc_channel_ch0_o(5) => 
        apb3_if_0_adc_channel_ch0_o(5), 
        apb3_if_0_adc_channel_ch0_o(4) => 
        apb3_if_0_adc_channel_ch0_o(4), 
        apb3_if_0_adc_channel_ch0_o(3) => 
        apb3_if_0_adc_channel_ch0_o(3), 
        apb3_if_0_adc_channel_ch0_o(2) => 
        apb3_if_0_adc_channel_ch0_o(2), 
        apb3_if_0_adc_channel_ch0_o(1) => 
        apb3_if_0_adc_channel_ch0_o(1), 
        apb3_if_0_adc_channel_ch0_o(0) => 
        apb3_if_0_adc_channel_ch0_o(0), 
        apb3_if_0_adc_channel_ch1_o(15) => 
        apb3_if_0_adc_channel_ch1_o(15), 
        apb3_if_0_adc_channel_ch1_o(14) => 
        apb3_if_0_adc_channel_ch1_o(14), 
        apb3_if_0_adc_channel_ch1_o(13) => 
        apb3_if_0_adc_channel_ch1_o(13), 
        apb3_if_0_adc_channel_ch1_o(12) => 
        apb3_if_0_adc_channel_ch1_o(12), 
        apb3_if_0_adc_channel_ch1_o(11) => 
        apb3_if_0_adc_channel_ch1_o(11), 
        apb3_if_0_adc_channel_ch1_o(10) => 
        apb3_if_0_adc_channel_ch1_o(10), 
        apb3_if_0_adc_channel_ch1_o(9) => 
        apb3_if_0_adc_channel_ch1_o(9), 
        apb3_if_0_adc_channel_ch1_o(8) => 
        apb3_if_0_adc_channel_ch1_o(8), 
        apb3_if_0_adc_channel_ch1_o(7) => 
        apb3_if_0_adc_channel_ch1_o(7), 
        apb3_if_0_adc_channel_ch1_o(6) => 
        apb3_if_0_adc_channel_ch1_o(6), 
        apb3_if_0_adc_channel_ch1_o(5) => 
        apb3_if_0_adc_channel_ch1_o(5), 
        apb3_if_0_adc_channel_ch1_o(4) => 
        apb3_if_0_adc_channel_ch1_o(4), 
        apb3_if_0_adc_channel_ch1_o(3) => 
        apb3_if_0_adc_channel_ch1_o(3), 
        apb3_if_0_adc_channel_ch1_o(2) => 
        apb3_if_0_adc_channel_ch1_o(2), 
        apb3_if_0_adc_channel_ch1_o(1) => 
        apb3_if_0_adc_channel_ch1_o(1), 
        apb3_if_0_adc_channel_ch1_o(0) => 
        apb3_if_0_adc_channel_ch1_o(0), 
        apb3_if_0_adc_channel_ch3_o(15) => 
        apb3_if_0_adc_channel_ch3_o(15), 
        apb3_if_0_adc_channel_ch3_o(14) => 
        apb3_if_0_adc_channel_ch3_o(14), 
        apb3_if_0_adc_channel_ch3_o(13) => 
        apb3_if_0_adc_channel_ch3_o(13), 
        apb3_if_0_adc_channel_ch3_o(12) => 
        apb3_if_0_adc_channel_ch3_o(12), 
        apb3_if_0_adc_channel_ch3_o(11) => 
        apb3_if_0_adc_channel_ch3_o(11), 
        apb3_if_0_adc_channel_ch3_o(10) => 
        apb3_if_0_adc_channel_ch3_o(10), 
        apb3_if_0_adc_channel_ch3_o(9) => 
        apb3_if_0_adc_channel_ch3_o(9), 
        apb3_if_0_adc_channel_ch3_o(8) => 
        apb3_if_0_adc_channel_ch3_o(8), 
        apb3_if_0_adc_channel_ch3_o(7) => 
        apb3_if_0_adc_channel_ch3_o(7), 
        apb3_if_0_adc_channel_ch3_o(6) => 
        apb3_if_0_adc_channel_ch3_o(6), 
        apb3_if_0_adc_channel_ch3_o(5) => 
        apb3_if_0_adc_channel_ch3_o(5), 
        apb3_if_0_adc_channel_ch3_o(4) => 
        apb3_if_0_adc_channel_ch3_o(4), 
        apb3_if_0_adc_channel_ch3_o(3) => 
        apb3_if_0_adc_channel_ch3_o(3), 
        apb3_if_0_adc_channel_ch3_o(2) => 
        apb3_if_0_adc_channel_ch3_o(2), 
        apb3_if_0_adc_channel_ch3_o(1) => 
        apb3_if_0_adc_channel_ch3_o(1), 
        apb3_if_0_adc_channel_ch3_o(0) => 
        apb3_if_0_adc_channel_ch3_o(0), MC_System_0_FIC_0_LOCK
         => MC_System_0_FIC_0_LOCK, MC_System_0_FIC_0_CLK => 
        MC_System_0_FIC_0_CLK, SEQ_CONTROLLER_1_adc_start_o => 
        SEQ_CONTROLLER_1_adc_start_o, A0_ADC_SDI_I_c => 
        A0_ADC_SDI_I_c, A0_ADC_SDO_O_c => A0_ADC_SDO_O_c, 
        A0_ADC_CS_O_c => A0_ADC_CS_O_c, A0_ADC_SCK_O_c => 
        A0_ADC_SCK_O_c, adc_interface_0_results_rdy_o => 
        adc_interface_0_results_rdy_o);
    
    MSC_i_33 : PWM_SCALING_0
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => SVM_0_done_o, va_i(17)
         => SVM_0_va3h_o(17), va_i(16) => SVM_0_va3h_o(16), 
        va_i(15) => SVM_0_va3h_o(15), va_i(14) => 
        SVM_0_va3h_o(14), va_i(13) => SVM_0_va3h_o(13), va_i(12)
         => SVM_0_va3h_o(12), va_i(11) => SVM_0_va3h_o(11), 
        va_i(10) => SVM_0_va3h_o(10), va_i(9) => SVM_0_va3h_o(9), 
        va_i(8) => SVM_0_va3h_o(8), va_i(7) => SVM_0_va3h_o(7), 
        va_i(6) => SVM_0_va3h_o(6), va_i(5) => SVM_0_va3h_o(5), 
        va_i(4) => SVM_0_va3h_o(4), va_i(3) => SVM_0_va3h_o(3), 
        va_i(2) => SVM_0_va3h_o(2), va_i(1) => SVM_0_va3h_o(1), 
        va_i(0) => SVM_0_va3h_o(0), vb_i(17) => SVM_0_vb3h_o(17), 
        vb_i(16) => SVM_0_vb3h_o(16), vb_i(15) => 
        SVM_0_vb3h_o(15), vb_i(14) => SVM_0_vb3h_o(14), vb_i(13)
         => SVM_0_vb3h_o(13), vb_i(12) => SVM_0_vb3h_o(12), 
        vb_i(11) => SVM_0_vb3h_o(11), vb_i(10) => 
        SVM_0_vb3h_o(10), vb_i(9) => SVM_0_vb3h_o(9), vb_i(8) => 
        SVM_0_vb3h_o(8), vb_i(7) => SVM_0_vb3h_o(7), vb_i(6) => 
        SVM_0_vb3h_o(6), vb_i(5) => SVM_0_vb3h_o(5), vb_i(4) => 
        SVM_0_vb3h_o(4), vb_i(3) => SVM_0_vb3h_o(3), vb_i(2) => 
        SVM_0_vb3h_o(2), vb_i(1) => SVM_0_vb3h_o(1), vb_i(0) => 
        SVM_0_vb3h_o(0), vc_i(17) => SVM_0_vc3h_o(17), vc_i(16)
         => SVM_0_vc3h_o(16), vc_i(15) => SVM_0_vc3h_o(15), 
        vc_i(14) => SVM_0_vc3h_o(14), vc_i(13) => 
        SVM_0_vc3h_o(13), vc_i(12) => SVM_0_vc3h_o(12), vc_i(11)
         => SVM_0_vc3h_o(11), vc_i(10) => SVM_0_vc3h_o(10), 
        vc_i(9) => SVM_0_vc3h_o(9), vc_i(8) => SVM_0_vc3h_o(8), 
        vc_i(7) => SVM_0_vc3h_o(7), vc_i(6) => SVM_0_vc3h_o(6), 
        vc_i(5) => SVM_0_vc3h_o(5), vc_i(4) => SVM_0_vc3h_o(4), 
        vc_i(3) => SVM_0_vc3h_o(3), vc_i(2) => SVM_0_vc3h_o(2), 
        vc_i(1) => SVM_0_vc3h_o(1), vc_i(0) => SVM_0_vc3h_o(0), 
        pwm_period_i(17) => apb3_if_0_pwm_period_val_o(17), 
        pwm_period_i(16) => apb3_if_0_pwm_period_val_o(16), 
        pwm_period_i(15) => apb3_if_0_pwm_period_val_o(15), 
        pwm_period_i(14) => apb3_if_0_pwm_period_val_o(14), 
        pwm_period_i(13) => apb3_if_0_pwm_period_val_o(13), 
        pwm_period_i(12) => apb3_if_0_pwm_period_val_o(12), 
        pwm_period_i(11) => apb3_if_0_pwm_period_val_o(11), 
        pwm_period_i(10) => apb3_if_0_pwm_period_val_o(10), 
        pwm_period_i(9) => apb3_if_0_pwm_period_val_o(9), 
        pwm_period_i(8) => apb3_if_0_pwm_period_val_o(8), 
        pwm_period_i(7) => apb3_if_0_pwm_period_val_o(7), 
        pwm_period_i(6) => apb3_if_0_pwm_period_val_o(6), 
        pwm_period_i(5) => apb3_if_0_pwm_period_val_o(5), 
        pwm_period_i(4) => apb3_if_0_pwm_period_val_o(4), 
        pwm_period_i(3) => apb3_if_0_pwm_period_val_o(3), 
        pwm_period_i(2) => apb3_if_0_pwm_period_val_o(2), 
        pwm_period_i(1) => apb3_if_0_pwm_period_val_o(1), 
        pwm_period_i(0) => apb3_if_0_pwm_period_val_o(0), 
        pwm_gain_i(17) => apb3_if_0_pwm_gain_val_o(17), 
        pwm_gain_i(16) => apb3_if_0_pwm_gain_val_o(16), 
        pwm_gain_i(15) => apb3_if_0_pwm_gain_val_o(15), 
        pwm_gain_i(14) => apb3_if_0_pwm_gain_val_o(14), 
        pwm_gain_i(13) => apb3_if_0_pwm_gain_val_o(13), 
        pwm_gain_i(12) => apb3_if_0_pwm_gain_val_o(12), 
        pwm_gain_i(11) => apb3_if_0_pwm_gain_val_o(11), 
        pwm_gain_i(10) => apb3_if_0_pwm_gain_val_o(10), 
        pwm_gain_i(9) => apb3_if_0_pwm_gain_val_o(9), 
        pwm_gain_i(8) => apb3_if_0_pwm_gain_val_o(8), 
        pwm_gain_i(7) => apb3_if_0_pwm_gain_val_o(7), 
        pwm_gain_i(6) => apb3_if_0_pwm_gain_val_o(6), 
        pwm_gain_i(5) => apb3_if_0_pwm_gain_val_o(5), 
        pwm_gain_i(4) => apb3_if_0_pwm_gain_val_o(4), 
        pwm_gain_i(3) => apb3_if_0_pwm_gain_val_o(3), 
        pwm_gain_i(2) => apb3_if_0_pwm_gain_val_o(2), 
        pwm_gain_i(1) => apb3_if_0_pwm_gain_val_o(1), 
        pwm_gain_i(0) => \GND\, Va_o(17) => 
        PWM_SCALING_0_Va_o(17), Va_o(16) => 
        PWM_SCALING_0_Va_o(16), Va_o(15) => 
        PWM_SCALING_0_Va_o(15), Va_o(14) => 
        PWM_SCALING_0_Va_o(14), Va_o(13) => 
        PWM_SCALING_0_Va_o(13), Va_o(12) => 
        PWM_SCALING_0_Va_o(12), Va_o(11) => 
        PWM_SCALING_0_Va_o(11), Va_o(10) => 
        PWM_SCALING_0_Va_o(10), Va_o(9) => PWM_SCALING_0_Va_o(9), 
        Va_o(8) => PWM_SCALING_0_Va_o(8), Va_o(7) => 
        PWM_SCALING_0_Va_o(7), Va_o(6) => PWM_SCALING_0_Va_o(6), 
        Va_o(5) => PWM_SCALING_0_Va_o(5), Va_o(4) => 
        PWM_SCALING_0_Va_o(4), Va_o(3) => PWM_SCALING_0_Va_o(3), 
        Va_o(2) => PWM_SCALING_0_Va_o(2), Va_o(1) => 
        PWM_SCALING_0_Va_o(1), Va_o(0) => PWM_SCALING_0_Va_o(0), 
        Vb_o(17) => PWM_SCALING_0_Vb_o(17), Vb_o(16) => 
        PWM_SCALING_0_Vb_o(16), Vb_o(15) => 
        PWM_SCALING_0_Vb_o(15), Vb_o(14) => 
        PWM_SCALING_0_Vb_o(14), Vb_o(13) => 
        PWM_SCALING_0_Vb_o(13), Vb_o(12) => 
        PWM_SCALING_0_Vb_o(12), Vb_o(11) => 
        PWM_SCALING_0_Vb_o(11), Vb_o(10) => 
        PWM_SCALING_0_Vb_o(10), Vb_o(9) => PWM_SCALING_0_Vb_o(9), 
        Vb_o(8) => PWM_SCALING_0_Vb_o(8), Vb_o(7) => 
        PWM_SCALING_0_Vb_o(7), Vb_o(6) => PWM_SCALING_0_Vb_o(6), 
        Vb_o(5) => PWM_SCALING_0_Vb_o(5), Vb_o(4) => 
        PWM_SCALING_0_Vb_o(4), Vb_o(3) => PWM_SCALING_0_Vb_o(3), 
        Vb_o(2) => PWM_SCALING_0_Vb_o(2), Vb_o(1) => 
        PWM_SCALING_0_Vb_o(1), Vb_o(0) => PWM_SCALING_0_Vb_o(0), 
        Vc_o(17) => PWM_SCALING_0_Vc_o(17), Vc_o(16) => 
        PWM_SCALING_0_Vc_o(16), Vc_o(15) => 
        PWM_SCALING_0_Vc_o(15), Vc_o(14) => 
        PWM_SCALING_0_Vc_o(14), Vc_o(13) => 
        PWM_SCALING_0_Vc_o(13), Vc_o(12) => 
        PWM_SCALING_0_Vc_o(12), Vc_o(11) => 
        PWM_SCALING_0_Vc_o(11), Vc_o(10) => 
        PWM_SCALING_0_Vc_o(10), Vc_o(9) => PWM_SCALING_0_Vc_o(9), 
        Vc_o(8) => PWM_SCALING_0_Vc_o(8), Vc_o(7) => 
        PWM_SCALING_0_Vc_o(7), Vc_o(6) => PWM_SCALING_0_Vc_o(6), 
        Vc_o(5) => PWM_SCALING_0_Vc_o(5), Vc_o(4) => 
        PWM_SCALING_0_Vc_o(4), Vc_o(3) => PWM_SCALING_0_Vc_o(3), 
        Vc_o(2) => PWM_SCALING_0_Vc_o(2), Vc_o(1) => 
        PWM_SCALING_0_Vc_o(1), Vc_o(0) => PWM_SCALING_0_Vc_o(0), 
        done_o => PWM_SCALING_1_done_o);
    
    MSC_i_15 : ADC_SCALING_0
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, adc_results_rdy_i => 
        adc_interface_0_results_rdy_o, adc_scale_val_i(17) => 
        apb3_if_0_adc_scale_val_o(17), adc_scale_val_i(16) => 
        apb3_if_0_adc_scale_val_o(16), adc_scale_val_i(15) => 
        apb3_if_0_adc_scale_val_o(15), adc_scale_val_i(14) => 
        apb3_if_0_adc_scale_val_o(14), adc_scale_val_i(13) => 
        apb3_if_0_adc_scale_val_o(13), adc_scale_val_i(12) => 
        apb3_if_0_adc_scale_val_o(12), adc_scale_val_i(11) => 
        apb3_if_0_adc_scale_val_o(11), adc_scale_val_i(10) => 
        apb3_if_0_adc_scale_val_o(10), adc_scale_val_i(9) => 
        apb3_if_0_adc_scale_val_o(9), adc_scale_val_i(8) => 
        apb3_if_0_adc_scale_val_o(8), adc_scale_val_i(7) => 
        apb3_if_0_adc_scale_val_o(7), adc_scale_val_i(6) => 
        apb3_if_0_adc_scale_val_o(6), adc_scale_val_i(5) => 
        apb3_if_0_adc_scale_val_o(5), adc_scale_val_i(4) => 
        apb3_if_0_adc_scale_val_o(4), adc_scale_val_i(3) => 
        apb3_if_0_adc_scale_val_o(3), adc_scale_val_i(2) => 
        apb3_if_0_adc_scale_val_o(2), adc_scale_val_i(1) => 
        apb3_if_0_adc_scale_val_o(1), adc_scale_val_i(0) => 
        apb3_if_0_adc_scale_val_o(0), adc_result_ch0_i(11) => 
        adc_interface_0_result_ch0_o(11), adc_result_ch0_i(10)
         => adc_interface_0_result_ch0_o(10), adc_result_ch0_i(9)
         => adc_interface_0_result_ch0_o(9), adc_result_ch0_i(8)
         => adc_interface_0_result_ch0_o(8), adc_result_ch0_i(7)
         => adc_interface_0_result_ch0_o(7), adc_result_ch0_i(6)
         => adc_interface_0_result_ch0_o(6), adc_result_ch0_i(5)
         => adc_interface_0_result_ch0_o(5), adc_result_ch0_i(4)
         => adc_interface_0_result_ch0_o(4), adc_result_ch0_i(3)
         => adc_interface_0_result_ch0_o(3), adc_result_ch0_i(2)
         => adc_interface_0_result_ch0_o(2), adc_result_ch0_i(1)
         => adc_interface_0_result_ch0_o(1), adc_result_ch0_i(0)
         => adc_interface_0_result_ch0_o(0), adc_result_ch1_i(11)
         => adc_interface_0_result_ch1_o(11), 
        adc_result_ch1_i(10) => adc_interface_0_result_ch1_o(10), 
        adc_result_ch1_i(9) => adc_interface_0_result_ch1_o(9), 
        adc_result_ch1_i(8) => adc_interface_0_result_ch1_o(8), 
        adc_result_ch1_i(7) => adc_interface_0_result_ch1_o(7), 
        adc_result_ch1_i(6) => adc_interface_0_result_ch1_o(6), 
        adc_result_ch1_i(5) => adc_interface_0_result_ch1_o(5), 
        adc_result_ch1_i(4) => adc_interface_0_result_ch1_o(4), 
        adc_result_ch1_i(3) => adc_interface_0_result_ch1_o(3), 
        adc_result_ch1_i(2) => adc_interface_0_result_ch1_o(2), 
        adc_result_ch1_i(1) => adc_interface_0_result_ch1_o(1), 
        adc_result_ch1_i(0) => adc_interface_0_result_ch1_o(0), 
        fault_threshold_i(17) => apb3_if_0_adc_oc_thresh_o(17), 
        fault_threshold_i(16) => apb3_if_0_adc_oc_thresh_o(16), 
        fault_threshold_i(15) => apb3_if_0_adc_oc_thresh_o(15), 
        fault_threshold_i(14) => apb3_if_0_adc_oc_thresh_o(14), 
        fault_threshold_i(13) => apb3_if_0_adc_oc_thresh_o(13), 
        fault_threshold_i(12) => apb3_if_0_adc_oc_thresh_o(12), 
        fault_threshold_i(11) => apb3_if_0_adc_oc_thresh_o(11), 
        fault_threshold_i(10) => apb3_if_0_adc_oc_thresh_o(10), 
        fault_threshold_i(9) => apb3_if_0_adc_oc_thresh_o(9), 
        fault_threshold_i(8) => apb3_if_0_adc_oc_thresh_o(8), 
        fault_threshold_i(7) => apb3_if_0_adc_oc_thresh_o(7), 
        fault_threshold_i(6) => apb3_if_0_adc_oc_thresh_o(6), 
        fault_threshold_i(5) => apb3_if_0_adc_oc_thresh_o(5), 
        fault_threshold_i(4) => apb3_if_0_adc_oc_thresh_o(4), 
        fault_threshold_i(3) => apb3_if_0_adc_oc_thresh_o(3), 
        fault_threshold_i(2) => apb3_if_0_adc_oc_thresh_o(2), 
        fault_threshold_i(1) => apb3_if_0_adc_oc_thresh_o(1), 
        fault_threshold_i(0) => apb3_if_0_adc_oc_thresh_o(0), 
        done_o => ADC_SCALING_0_done_o, calib_done_o => 
        ADC_SCALING_1_calib_done_o, over_current_fault_o => 
        ADC_SCALING_1_over_current_fault_o, ia_adc_o(17) => 
        ADC_SCALING_1_ia_adc_o(17), ia_adc_o(16) => 
        ADC_SCALING_1_ia_adc_o(16), ia_adc_o(15) => 
        ADC_SCALING_1_ia_adc_o(15), ia_adc_o(14) => 
        ADC_SCALING_1_ia_adc_o(14), ia_adc_o(13) => 
        ADC_SCALING_1_ia_adc_o(13), ia_adc_o(12) => 
        ADC_SCALING_1_ia_adc_o(12), ia_adc_o(11) => 
        ADC_SCALING_1_ia_adc_o(11), ia_adc_o(10) => 
        ADC_SCALING_1_ia_adc_o(10), ia_adc_o(9) => 
        ADC_SCALING_1_ia_adc_o(9), ia_adc_o(8) => 
        ADC_SCALING_1_ia_adc_o(8), ia_adc_o(7) => 
        ADC_SCALING_1_ia_adc_o(7), ia_adc_o(6) => 
        ADC_SCALING_1_ia_adc_o(6), ia_adc_o(5) => 
        ADC_SCALING_1_ia_adc_o(5), ia_adc_o(4) => 
        ADC_SCALING_1_ia_adc_o(4), ia_adc_o(3) => 
        ADC_SCALING_1_ia_adc_o(3), ia_adc_o(2) => 
        ADC_SCALING_1_ia_adc_o(2), ia_adc_o(1) => 
        ADC_SCALING_1_ia_adc_o(1), ia_adc_o(0) => 
        ADC_SCALING_1_ia_adc_o(0), ib_adc_o(17) => 
        ADC_SCALING_1_ib_adc_o(17), ib_adc_o(16) => 
        ADC_SCALING_1_ib_adc_o(16), ib_adc_o(15) => 
        ADC_SCALING_1_ib_adc_o(15), ib_adc_o(14) => 
        ADC_SCALING_1_ib_adc_o(14), ib_adc_o(13) => 
        ADC_SCALING_1_ib_adc_o(13), ib_adc_o(12) => 
        ADC_SCALING_1_ib_adc_o(12), ib_adc_o(11) => 
        ADC_SCALING_1_ib_adc_o(11), ib_adc_o(10) => 
        ADC_SCALING_1_ib_adc_o(10), ib_adc_o(9) => 
        ADC_SCALING_1_ib_adc_o(9), ib_adc_o(8) => 
        ADC_SCALING_1_ib_adc_o(8), ib_adc_o(7) => 
        ADC_SCALING_1_ib_adc_o(7), ib_adc_o(6) => 
        ADC_SCALING_1_ib_adc_o(6), ib_adc_o(5) => 
        ADC_SCALING_1_ib_adc_o(5), ib_adc_o(4) => 
        ADC_SCALING_1_ib_adc_o(4), ib_adc_o(3) => 
        ADC_SCALING_1_ib_adc_o(3), ib_adc_o(2) => 
        ADC_SCALING_1_ib_adc_o(2), ib_adc_o(1) => 
        ADC_SCALING_1_ib_adc_o(1), ib_adc_o(0) => 
        ADC_SCALING_1_ib_adc_o(0));
    
    apb3_if_0 : apb3_if
      port map(apb3_if_0_idq_pi_ki_o_0(17) => 
        apb3_if_0_idq_pi_ki_o_0(17), apb3_if_0_idq_pi_ki_o_0(16)
         => apb3_if_0_idq_pi_ki_o_0(16), 
        apb3_if_0_idq_pi_ki_o_0(15) => 
        apb3_if_0_idq_pi_ki_o_0(15), apb3_if_0_idq_pi_ki_o_0(14)
         => apb3_if_0_idq_pi_ki_o_0(14), 
        apb3_if_0_idq_pi_ki_o_0(13) => 
        apb3_if_0_idq_pi_ki_o_0(13), apb3_if_0_idq_pi_ki_o_0(12)
         => apb3_if_0_idq_pi_ki_o_0(12), 
        apb3_if_0_idq_pi_ki_o_0(11) => 
        apb3_if_0_idq_pi_ki_o_0(11), apb3_if_0_idq_pi_ki_o_0(10)
         => apb3_if_0_idq_pi_ki_o_0(10), 
        apb3_if_0_idq_pi_ki_o_0(9) => apb3_if_0_idq_pi_ki_o_0(9), 
        apb3_if_0_idq_pi_ki_o_0(8) => apb3_if_0_idq_pi_ki_o_0(8), 
        apb3_if_0_idq_pi_ki_o_0(7) => apb3_if_0_idq_pi_ki_o_0(7), 
        apb3_if_0_idq_pi_ki_o_0(6) => apb3_if_0_idq_pi_ki_o_0(6), 
        apb3_if_0_idq_pi_ki_o_0(5) => apb3_if_0_idq_pi_ki_o_0(5), 
        apb3_if_0_idq_pi_ki_o_0(4) => apb3_if_0_idq_pi_ki_o_0(4), 
        apb3_if_0_idq_pi_ki_o_0(3) => apb3_if_0_idq_pi_ki_o_0(3), 
        apb3_if_0_idq_pi_ki_o_0(2) => apb3_if_0_idq_pi_ki_o_0(2), 
        apb3_if_0_idq_pi_ki_o_0(1) => apb3_if_0_idq_pi_ki_o_0(1), 
        apb3_if_0_idq_pi_ki_o_0(0) => apb3_if_0_idq_pi_ki_o_0(0), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0), 
        apb3_if_0_idq_pi_kp_o(17) => apb3_if_0_idq_pi_kp_o(17), 
        apb3_if_0_idq_pi_kp_o(16) => apb3_if_0_idq_pi_kp_o(16), 
        apb3_if_0_idq_pi_kp_o(15) => apb3_if_0_idq_pi_kp_o(15), 
        apb3_if_0_idq_pi_kp_o(14) => apb3_if_0_idq_pi_kp_o(14), 
        apb3_if_0_idq_pi_kp_o(13) => apb3_if_0_idq_pi_kp_o(13), 
        apb3_if_0_idq_pi_kp_o(12) => apb3_if_0_idq_pi_kp_o(12), 
        apb3_if_0_idq_pi_kp_o(11) => apb3_if_0_idq_pi_kp_o(11), 
        apb3_if_0_idq_pi_kp_o(10) => apb3_if_0_idq_pi_kp_o(10), 
        apb3_if_0_idq_pi_kp_o(9) => apb3_if_0_idq_pi_kp_o(9), 
        apb3_if_0_idq_pi_kp_o(8) => apb3_if_0_idq_pi_kp_o(8), 
        apb3_if_0_idq_pi_kp_o(7) => apb3_if_0_idq_pi_kp_o(7), 
        apb3_if_0_idq_pi_kp_o(6) => apb3_if_0_idq_pi_kp_o(6), 
        apb3_if_0_idq_pi_kp_o(5) => apb3_if_0_idq_pi_kp_o(5), 
        apb3_if_0_idq_pi_kp_o(4) => apb3_if_0_idq_pi_kp_o(4), 
        apb3_if_0_idq_pi_kp_o(3) => apb3_if_0_idq_pi_kp_o(3), 
        apb3_if_0_idq_pi_kp_o(2) => apb3_if_0_idq_pi_kp_o(2), 
        apb3_if_0_idq_pi_kp_o(1) => apb3_if_0_idq_pi_kp_o(1), 
        apb3_if_0_idq_pi_kp_o(0) => apb3_if_0_idq_pi_kp_o(0), 
        apb3_if_0_olmng_dv_o(17) => apb3_if_0_olmng_dv_o(17), 
        apb3_if_0_olmng_dv_o(16) => apb3_if_0_olmng_dv_o(16), 
        apb3_if_0_olmng_dv_o(15) => apb3_if_0_olmng_dv_o(15), 
        apb3_if_0_olmng_dv_o(14) => apb3_if_0_olmng_dv_o(14), 
        apb3_if_0_olmng_dv_o(13) => apb3_if_0_olmng_dv_o(13), 
        apb3_if_0_olmng_dv_o(12) => apb3_if_0_olmng_dv_o(12), 
        apb3_if_0_olmng_dv_o(11) => apb3_if_0_olmng_dv_o(11), 
        apb3_if_0_olmng_dv_o(10) => apb3_if_0_olmng_dv_o(10), 
        apb3_if_0_olmng_dv_o(9) => apb3_if_0_olmng_dv_o(9), 
        apb3_if_0_olmng_dv_o(8) => apb3_if_0_olmng_dv_o(8), 
        apb3_if_0_olmng_dv_o(7) => apb3_if_0_olmng_dv_o(7), 
        apb3_if_0_olmng_dv_o(6) => apb3_if_0_olmng_dv_o(6), 
        apb3_if_0_olmng_dv_o(5) => apb3_if_0_olmng_dv_o(5), 
        apb3_if_0_olmng_dv_o(4) => apb3_if_0_olmng_dv_o(4), 
        apb3_if_0_olmng_dv_o(3) => apb3_if_0_olmng_dv_o(3), 
        apb3_if_0_olmng_dv_o(2) => apb3_if_0_olmng_dv_o(2), 
        apb3_if_0_olmng_dv_o(1) => apb3_if_0_olmng_dv_o(1), 
        apb3_if_0_olmng_dv_o(0) => apb3_if_0_olmng_dv_o(0), 
        apb3_if_0_olmng_iq_ref_in_o(17) => 
        apb3_if_0_olmng_iq_ref_in_o(17), 
        apb3_if_0_olmng_iq_ref_in_o(16) => 
        apb3_if_0_olmng_iq_ref_in_o(16), 
        apb3_if_0_olmng_iq_ref_in_o(15) => 
        apb3_if_0_olmng_iq_ref_in_o(15), 
        apb3_if_0_olmng_iq_ref_in_o(14) => 
        apb3_if_0_olmng_iq_ref_in_o(14), 
        apb3_if_0_olmng_iq_ref_in_o(13) => 
        apb3_if_0_olmng_iq_ref_in_o(13), 
        apb3_if_0_olmng_iq_ref_in_o(12) => 
        apb3_if_0_olmng_iq_ref_in_o(12), 
        apb3_if_0_olmng_iq_ref_in_o(11) => 
        apb3_if_0_olmng_iq_ref_in_o(11), 
        apb3_if_0_olmng_iq_ref_in_o(10) => 
        apb3_if_0_olmng_iq_ref_in_o(10), 
        apb3_if_0_olmng_iq_ref_in_o(9) => 
        apb3_if_0_olmng_iq_ref_in_o(9), 
        apb3_if_0_olmng_iq_ref_in_o(8) => 
        apb3_if_0_olmng_iq_ref_in_o(8), 
        apb3_if_0_olmng_iq_ref_in_o(7) => 
        apb3_if_0_olmng_iq_ref_in_o(7), 
        apb3_if_0_olmng_iq_ref_in_o(6) => 
        apb3_if_0_olmng_iq_ref_in_o(6), 
        apb3_if_0_olmng_iq_ref_in_o(5) => 
        apb3_if_0_olmng_iq_ref_in_o(5), 
        apb3_if_0_olmng_iq_ref_in_o(4) => 
        apb3_if_0_olmng_iq_ref_in_o(4), 
        apb3_if_0_olmng_iq_ref_in_o(3) => 
        apb3_if_0_olmng_iq_ref_in_o(3), 
        apb3_if_0_olmng_iq_ref_in_o(2) => 
        apb3_if_0_olmng_iq_ref_in_o(2), 
        apb3_if_0_olmng_iq_ref_in_o(1) => 
        apb3_if_0_olmng_iq_ref_in_o(1), 
        apb3_if_0_olmng_iq_ref_in_o(0) => 
        apb3_if_0_olmng_iq_ref_in_o(0), 
        apb3_if_0_olmng_theta_factor_o(17) => 
        apb3_if_0_olmng_theta_factor_o(17), 
        apb3_if_0_olmng_theta_factor_o(16) => 
        apb3_if_0_olmng_theta_factor_o(16), 
        apb3_if_0_olmng_theta_factor_o(15) => 
        apb3_if_0_olmng_theta_factor_o(15), 
        apb3_if_0_olmng_theta_factor_o(14) => 
        apb3_if_0_olmng_theta_factor_o(14), 
        apb3_if_0_olmng_theta_factor_o(13) => 
        apb3_if_0_olmng_theta_factor_o(13), 
        apb3_if_0_olmng_theta_factor_o(12) => 
        apb3_if_0_olmng_theta_factor_o(12), 
        apb3_if_0_olmng_theta_factor_o(11) => 
        apb3_if_0_olmng_theta_factor_o(11), 
        apb3_if_0_olmng_theta_factor_o(10) => 
        apb3_if_0_olmng_theta_factor_o(10), 
        apb3_if_0_olmng_theta_factor_o(9) => 
        apb3_if_0_olmng_theta_factor_o(9), 
        apb3_if_0_olmng_theta_factor_o(8) => 
        apb3_if_0_olmng_theta_factor_o(8), 
        apb3_if_0_olmng_theta_factor_o(7) => 
        apb3_if_0_olmng_theta_factor_o(7), 
        apb3_if_0_olmng_theta_factor_o(6) => 
        apb3_if_0_olmng_theta_factor_o(6), 
        apb3_if_0_olmng_theta_factor_o(5) => 
        apb3_if_0_olmng_theta_factor_o(5), 
        apb3_if_0_olmng_theta_factor_o(4) => 
        apb3_if_0_olmng_theta_factor_o(4), 
        apb3_if_0_olmng_theta_factor_o(3) => 
        apb3_if_0_olmng_theta_factor_o(3), 
        apb3_if_0_olmng_theta_factor_o(2) => 
        apb3_if_0_olmng_theta_factor_o(2), 
        apb3_if_0_olmng_theta_factor_o(1) => 
        apb3_if_0_olmng_theta_factor_o(1), 
        apb3_if_0_olmng_theta_factor_o(0) => 
        apb3_if_0_olmng_theta_factor_o(0), 
        apb3_if_0_pwm_dead_time_val_o(17) => 
        apb3_if_0_pwm_dead_time_val_o(17), 
        apb3_if_0_pwm_dead_time_val_o(16) => 
        apb3_if_0_pwm_dead_time_val_o(16), 
        apb3_if_0_pwm_dead_time_val_o(15) => 
        apb3_if_0_pwm_dead_time_val_o(15), 
        apb3_if_0_pwm_dead_time_val_o(14) => 
        apb3_if_0_pwm_dead_time_val_o(14), 
        apb3_if_0_pwm_dead_time_val_o(13) => 
        apb3_if_0_pwm_dead_time_val_o(13), 
        apb3_if_0_pwm_dead_time_val_o(12) => 
        apb3_if_0_pwm_dead_time_val_o(12), 
        apb3_if_0_pwm_dead_time_val_o(11) => 
        apb3_if_0_pwm_dead_time_val_o(11), 
        apb3_if_0_pwm_dead_time_val_o(10) => 
        apb3_if_0_pwm_dead_time_val_o(10), 
        apb3_if_0_pwm_dead_time_val_o(9) => 
        apb3_if_0_pwm_dead_time_val_o(9), 
        apb3_if_0_pwm_dead_time_val_o(8) => 
        apb3_if_0_pwm_dead_time_val_o(8), 
        apb3_if_0_pwm_dead_time_val_o(7) => 
        apb3_if_0_pwm_dead_time_val_o(7), 
        apb3_if_0_pwm_dead_time_val_o(6) => 
        apb3_if_0_pwm_dead_time_val_o(6), 
        apb3_if_0_pwm_dead_time_val_o(5) => 
        apb3_if_0_pwm_dead_time_val_o(5), 
        apb3_if_0_pwm_dead_time_val_o(4) => 
        apb3_if_0_pwm_dead_time_val_o(4), 
        apb3_if_0_pwm_dead_time_val_o(3) => 
        apb3_if_0_pwm_dead_time_val_o(3), 
        apb3_if_0_pwm_dead_time_val_o(2) => 
        apb3_if_0_pwm_dead_time_val_o(2), 
        apb3_if_0_pwm_dead_time_val_o(1) => 
        apb3_if_0_pwm_dead_time_val_o(1), 
        apb3_if_0_pwm_dead_time_val_o(0) => 
        apb3_if_0_pwm_dead_time_val_o(0), 
        apb3_if_0_pwm_delay_time_val_o(17) => 
        apb3_if_0_pwm_delay_time_val_o(17), 
        apb3_if_0_pwm_delay_time_val_o(16) => 
        apb3_if_0_pwm_delay_time_val_o(16), 
        apb3_if_0_pwm_delay_time_val_o(15) => 
        apb3_if_0_pwm_delay_time_val_o(15), 
        apb3_if_0_pwm_delay_time_val_o(14) => 
        apb3_if_0_pwm_delay_time_val_o(14), 
        apb3_if_0_pwm_delay_time_val_o(13) => 
        apb3_if_0_pwm_delay_time_val_o(13), 
        apb3_if_0_pwm_delay_time_val_o(12) => 
        apb3_if_0_pwm_delay_time_val_o(12), 
        apb3_if_0_pwm_delay_time_val_o(11) => 
        apb3_if_0_pwm_delay_time_val_o(11), 
        apb3_if_0_pwm_delay_time_val_o(10) => 
        apb3_if_0_pwm_delay_time_val_o(10), 
        apb3_if_0_pwm_delay_time_val_o(9) => 
        apb3_if_0_pwm_delay_time_val_o(9), 
        apb3_if_0_pwm_delay_time_val_o(8) => 
        apb3_if_0_pwm_delay_time_val_o(8), 
        apb3_if_0_pwm_delay_time_val_o(7) => 
        apb3_if_0_pwm_delay_time_val_o(7), 
        apb3_if_0_pwm_delay_time_val_o(6) => 
        apb3_if_0_pwm_delay_time_val_o(6), 
        apb3_if_0_pwm_delay_time_val_o(5) => 
        apb3_if_0_pwm_delay_time_val_o(5), 
        apb3_if_0_pwm_delay_time_val_o(4) => 
        apb3_if_0_pwm_delay_time_val_o(4), 
        apb3_if_0_pwm_delay_time_val_o(3) => 
        apb3_if_0_pwm_delay_time_val_o(3), 
        apb3_if_0_pwm_delay_time_val_o(2) => 
        apb3_if_0_pwm_delay_time_val_o(2), 
        apb3_if_0_pwm_delay_time_val_o(1) => 
        apb3_if_0_pwm_delay_time_val_o(1), 
        apb3_if_0_pwm_delay_time_val_o(0) => 
        apb3_if_0_pwm_delay_time_val_o(0), 
        apb3_if_0_pwm_gain_val_o(17) => 
        apb3_if_0_pwm_gain_val_o(17), 
        apb3_if_0_pwm_gain_val_o(16) => 
        apb3_if_0_pwm_gain_val_o(16), 
        apb3_if_0_pwm_gain_val_o(15) => 
        apb3_if_0_pwm_gain_val_o(15), 
        apb3_if_0_pwm_gain_val_o(14) => 
        apb3_if_0_pwm_gain_val_o(14), 
        apb3_if_0_pwm_gain_val_o(13) => 
        apb3_if_0_pwm_gain_val_o(13), 
        apb3_if_0_pwm_gain_val_o(12) => 
        apb3_if_0_pwm_gain_val_o(12), 
        apb3_if_0_pwm_gain_val_o(11) => 
        apb3_if_0_pwm_gain_val_o(11), 
        apb3_if_0_pwm_gain_val_o(10) => 
        apb3_if_0_pwm_gain_val_o(10), apb3_if_0_pwm_gain_val_o(9)
         => apb3_if_0_pwm_gain_val_o(9), 
        apb3_if_0_pwm_gain_val_o(8) => 
        apb3_if_0_pwm_gain_val_o(8), apb3_if_0_pwm_gain_val_o(7)
         => apb3_if_0_pwm_gain_val_o(7), 
        apb3_if_0_pwm_gain_val_o(6) => 
        apb3_if_0_pwm_gain_val_o(6), apb3_if_0_pwm_gain_val_o(5)
         => apb3_if_0_pwm_gain_val_o(5), 
        apb3_if_0_pwm_gain_val_o(4) => 
        apb3_if_0_pwm_gain_val_o(4), apb3_if_0_pwm_gain_val_o(3)
         => apb3_if_0_pwm_gain_val_o(3), 
        apb3_if_0_pwm_gain_val_o(2) => 
        apb3_if_0_pwm_gain_val_o(2), apb3_if_0_pwm_gain_val_o(1)
         => apb3_if_0_pwm_gain_val_o(1), 
        apb3_if_0_pwm_period_val_o(17) => 
        apb3_if_0_pwm_period_val_o(17), 
        apb3_if_0_pwm_period_val_o(16) => 
        apb3_if_0_pwm_period_val_o(16), 
        apb3_if_0_pwm_period_val_o(15) => 
        apb3_if_0_pwm_period_val_o(15), 
        apb3_if_0_pwm_period_val_o(14) => 
        apb3_if_0_pwm_period_val_o(14), 
        apb3_if_0_pwm_period_val_o(13) => 
        apb3_if_0_pwm_period_val_o(13), 
        apb3_if_0_pwm_period_val_o(12) => 
        apb3_if_0_pwm_period_val_o(12), 
        apb3_if_0_pwm_period_val_o(11) => 
        apb3_if_0_pwm_period_val_o(11), 
        apb3_if_0_pwm_period_val_o(10) => 
        apb3_if_0_pwm_period_val_o(10), 
        apb3_if_0_pwm_period_val_o(9) => 
        apb3_if_0_pwm_period_val_o(9), 
        apb3_if_0_pwm_period_val_o(8) => 
        apb3_if_0_pwm_period_val_o(8), 
        apb3_if_0_pwm_period_val_o(7) => 
        apb3_if_0_pwm_period_val_o(7), 
        apb3_if_0_pwm_period_val_o(6) => 
        apb3_if_0_pwm_period_val_o(6), 
        apb3_if_0_pwm_period_val_o(5) => 
        apb3_if_0_pwm_period_val_o(5), 
        apb3_if_0_pwm_period_val_o(4) => 
        apb3_if_0_pwm_period_val_o(4), 
        apb3_if_0_pwm_period_val_o(3) => 
        apb3_if_0_pwm_period_val_o(3), 
        apb3_if_0_pwm_period_val_o(2) => 
        apb3_if_0_pwm_period_val_o(2), 
        apb3_if_0_pwm_period_val_o(1) => 
        apb3_if_0_pwm_period_val_o(1), 
        apb3_if_0_pwm_period_val_o(0) => 
        apb3_if_0_pwm_period_val_o(0), 
        apb3_if_0_rate_limit_rate_cnt_o(17) => 
        apb3_if_0_rate_limit_rate_cnt_o(17), 
        apb3_if_0_rate_limit_rate_cnt_o(16) => 
        apb3_if_0_rate_limit_rate_cnt_o(16), 
        apb3_if_0_rate_limit_rate_cnt_o(15) => 
        apb3_if_0_rate_limit_rate_cnt_o(15), 
        apb3_if_0_rate_limit_rate_cnt_o(14) => 
        apb3_if_0_rate_limit_rate_cnt_o(14), 
        apb3_if_0_rate_limit_rate_cnt_o(13) => 
        apb3_if_0_rate_limit_rate_cnt_o(13), 
        apb3_if_0_rate_limit_rate_cnt_o(12) => 
        apb3_if_0_rate_limit_rate_cnt_o(12), 
        apb3_if_0_rate_limit_rate_cnt_o(11) => 
        apb3_if_0_rate_limit_rate_cnt_o(11), 
        apb3_if_0_rate_limit_rate_cnt_o(10) => 
        apb3_if_0_rate_limit_rate_cnt_o(10), 
        apb3_if_0_rate_limit_rate_cnt_o(9) => 
        apb3_if_0_rate_limit_rate_cnt_o(9), 
        apb3_if_0_rate_limit_rate_cnt_o(8) => 
        apb3_if_0_rate_limit_rate_cnt_o(8), 
        apb3_if_0_rate_limit_rate_cnt_o(7) => 
        apb3_if_0_rate_limit_rate_cnt_o(7), 
        apb3_if_0_rate_limit_rate_cnt_o(6) => 
        apb3_if_0_rate_limit_rate_cnt_o(6), 
        apb3_if_0_rate_limit_rate_cnt_o(5) => 
        apb3_if_0_rate_limit_rate_cnt_o(5), 
        apb3_if_0_rate_limit_rate_cnt_o(4) => 
        apb3_if_0_rate_limit_rate_cnt_o(4), 
        apb3_if_0_rate_limit_rate_cnt_o(3) => 
        apb3_if_0_rate_limit_rate_cnt_o(3), 
        apb3_if_0_rate_limit_rate_cnt_o(2) => 
        apb3_if_0_rate_limit_rate_cnt_o(2), 
        apb3_if_0_rate_limit_rate_cnt_o(1) => 
        apb3_if_0_rate_limit_rate_cnt_o(1), 
        apb3_if_0_rate_limit_rate_cnt_o(0) => 
        apb3_if_0_rate_limit_rate_cnt_o(0), 
        apb3_if_0_rate_limit_ref_in_o(17) => 
        apb3_if_0_rate_limit_ref_in_o(17), 
        apb3_if_0_rate_limit_ref_in_o(16) => 
        apb3_if_0_rate_limit_ref_in_o(16), 
        apb3_if_0_rate_limit_ref_in_o(15) => 
        apb3_if_0_rate_limit_ref_in_o(15), 
        apb3_if_0_rate_limit_ref_in_o(14) => 
        apb3_if_0_rate_limit_ref_in_o(14), 
        apb3_if_0_rate_limit_ref_in_o(13) => 
        apb3_if_0_rate_limit_ref_in_o(13), 
        apb3_if_0_rate_limit_ref_in_o(12) => 
        apb3_if_0_rate_limit_ref_in_o(12), 
        apb3_if_0_rate_limit_ref_in_o(11) => 
        apb3_if_0_rate_limit_ref_in_o(11), 
        apb3_if_0_rate_limit_ref_in_o(10) => 
        apb3_if_0_rate_limit_ref_in_o(10), 
        apb3_if_0_rate_limit_ref_in_o(9) => 
        apb3_if_0_rate_limit_ref_in_o(9), 
        apb3_if_0_rate_limit_ref_in_o(8) => 
        apb3_if_0_rate_limit_ref_in_o(8), 
        apb3_if_0_rate_limit_ref_in_o(7) => 
        apb3_if_0_rate_limit_ref_in_o(7), 
        apb3_if_0_rate_limit_ref_in_o(6) => 
        apb3_if_0_rate_limit_ref_in_o(6), 
        apb3_if_0_rate_limit_ref_in_o(5) => 
        apb3_if_0_rate_limit_ref_in_o(5), 
        apb3_if_0_rate_limit_ref_in_o(4) => 
        apb3_if_0_rate_limit_ref_in_o(4), 
        apb3_if_0_rate_limit_ref_in_o(3) => 
        apb3_if_0_rate_limit_ref_in_o(3), 
        apb3_if_0_rate_limit_ref_in_o(2) => 
        apb3_if_0_rate_limit_ref_in_o(2), 
        apb3_if_0_rate_limit_ref_in_o(1) => 
        apb3_if_0_rate_limit_ref_in_o(1), 
        apb3_if_0_rate_limit_ref_in_o(0) => 
        apb3_if_0_rate_limit_ref_in_o(0), 
        apb3_if_0_rate_limit_slew_cnt_o(17) => 
        apb3_if_0_rate_limit_slew_cnt_o(17), 
        apb3_if_0_rate_limit_slew_cnt_o(16) => 
        apb3_if_0_rate_limit_slew_cnt_o(16), 
        apb3_if_0_rate_limit_slew_cnt_o(15) => 
        apb3_if_0_rate_limit_slew_cnt_o(15), 
        apb3_if_0_rate_limit_slew_cnt_o(14) => 
        apb3_if_0_rate_limit_slew_cnt_o(14), 
        apb3_if_0_rate_limit_slew_cnt_o(13) => 
        apb3_if_0_rate_limit_slew_cnt_o(13), 
        apb3_if_0_rate_limit_slew_cnt_o(12) => 
        apb3_if_0_rate_limit_slew_cnt_o(12), 
        apb3_if_0_rate_limit_slew_cnt_o(11) => 
        apb3_if_0_rate_limit_slew_cnt_o(11), 
        apb3_if_0_rate_limit_slew_cnt_o(10) => 
        apb3_if_0_rate_limit_slew_cnt_o(10), 
        apb3_if_0_rate_limit_slew_cnt_o(9) => 
        apb3_if_0_rate_limit_slew_cnt_o(9), 
        apb3_if_0_rate_limit_slew_cnt_o(8) => 
        apb3_if_0_rate_limit_slew_cnt_o(8), 
        apb3_if_0_rate_limit_slew_cnt_o(7) => 
        apb3_if_0_rate_limit_slew_cnt_o(7), 
        apb3_if_0_rate_limit_slew_cnt_o(6) => 
        apb3_if_0_rate_limit_slew_cnt_o(6), 
        apb3_if_0_rate_limit_slew_cnt_o(5) => 
        apb3_if_0_rate_limit_slew_cnt_o(5), 
        apb3_if_0_rate_limit_slew_cnt_o(4) => 
        apb3_if_0_rate_limit_slew_cnt_o(4), 
        apb3_if_0_rate_limit_slew_cnt_o(3) => 
        apb3_if_0_rate_limit_slew_cnt_o(3), 
        apb3_if_0_rate_limit_slew_cnt_o(2) => 
        apb3_if_0_rate_limit_slew_cnt_o(2), 
        apb3_if_0_rate_limit_slew_cnt_o(1) => 
        apb3_if_0_rate_limit_slew_cnt_o(1), 
        apb3_if_0_rate_limit_slew_cnt_o(0) => 
        apb3_if_0_rate_limit_slew_cnt_o(0), 
        apb3_if_0_seq_cntl_cl_omega_o(17) => 
        apb3_if_0_seq_cntl_cl_omega_o(17), 
        apb3_if_0_seq_cntl_cl_omega_o(16) => 
        apb3_if_0_seq_cntl_cl_omega_o(16), 
        apb3_if_0_seq_cntl_cl_omega_o(15) => 
        apb3_if_0_seq_cntl_cl_omega_o(15), 
        apb3_if_0_seq_cntl_cl_omega_o(14) => 
        apb3_if_0_seq_cntl_cl_omega_o(14), 
        apb3_if_0_seq_cntl_cl_omega_o(13) => 
        apb3_if_0_seq_cntl_cl_omega_o(13), 
        apb3_if_0_seq_cntl_cl_omega_o(12) => 
        apb3_if_0_seq_cntl_cl_omega_o(12), 
        apb3_if_0_seq_cntl_cl_omega_o(11) => 
        apb3_if_0_seq_cntl_cl_omega_o(11), 
        apb3_if_0_seq_cntl_cl_omega_o(10) => 
        apb3_if_0_seq_cntl_cl_omega_o(10), 
        apb3_if_0_seq_cntl_cl_omega_o(9) => 
        apb3_if_0_seq_cntl_cl_omega_o(9), 
        apb3_if_0_seq_cntl_cl_omega_o(8) => 
        apb3_if_0_seq_cntl_cl_omega_o(8), 
        apb3_if_0_seq_cntl_cl_omega_o(7) => 
        apb3_if_0_seq_cntl_cl_omega_o(7), 
        apb3_if_0_seq_cntl_cl_omega_o(6) => 
        apb3_if_0_seq_cntl_cl_omega_o(6), 
        apb3_if_0_seq_cntl_cl_omega_o(5) => 
        apb3_if_0_seq_cntl_cl_omega_o(5), 
        apb3_if_0_seq_cntl_cl_omega_o(4) => 
        apb3_if_0_seq_cntl_cl_omega_o(4), 
        apb3_if_0_seq_cntl_cl_omega_o(3) => 
        apb3_if_0_seq_cntl_cl_omega_o(3), 
        apb3_if_0_seq_cntl_cl_omega_o(2) => 
        apb3_if_0_seq_cntl_cl_omega_o(2), 
        apb3_if_0_seq_cntl_cl_omega_o(1) => 
        apb3_if_0_seq_cntl_cl_omega_o(1), 
        apb3_if_0_seq_cntl_cl_omega_o(0) => 
        apb3_if_0_seq_cntl_cl_omega_o(0), 
        apb3_if_0_speed_pi_ki_o(17) => 
        apb3_if_0_speed_pi_ki_o(17), apb3_if_0_speed_pi_ki_o(16)
         => apb3_if_0_speed_pi_ki_o(16), 
        apb3_if_0_speed_pi_ki_o(15) => 
        apb3_if_0_speed_pi_ki_o(15), apb3_if_0_speed_pi_ki_o(14)
         => apb3_if_0_speed_pi_ki_o(14), 
        apb3_if_0_speed_pi_ki_o(13) => 
        apb3_if_0_speed_pi_ki_o(13), apb3_if_0_speed_pi_ki_o(12)
         => apb3_if_0_speed_pi_ki_o(12), 
        apb3_if_0_speed_pi_ki_o(11) => 
        apb3_if_0_speed_pi_ki_o(11), apb3_if_0_speed_pi_ki_o(10)
         => apb3_if_0_speed_pi_ki_o(10), 
        apb3_if_0_speed_pi_ki_o(9) => apb3_if_0_speed_pi_ki_o(9), 
        apb3_if_0_speed_pi_ki_o(8) => apb3_if_0_speed_pi_ki_o(8), 
        apb3_if_0_speed_pi_ki_o(7) => apb3_if_0_speed_pi_ki_o(7), 
        apb3_if_0_speed_pi_ki_o(6) => apb3_if_0_speed_pi_ki_o(6), 
        apb3_if_0_speed_pi_ki_o(5) => apb3_if_0_speed_pi_ki_o(5), 
        apb3_if_0_speed_pi_ki_o(4) => apb3_if_0_speed_pi_ki_o(4), 
        apb3_if_0_speed_pi_ki_o(3) => apb3_if_0_speed_pi_ki_o(3), 
        apb3_if_0_speed_pi_ki_o(2) => apb3_if_0_speed_pi_ki_o(2), 
        apb3_if_0_speed_pi_ki_o(1) => apb3_if_0_speed_pi_ki_o(1), 
        apb3_if_0_speed_pi_ki_o(0) => apb3_if_0_speed_pi_ki_o(0), 
        apb3_if_0_filter_factor_bemf_o(3) => 
        apb3_if_0_filter_factor_bemf_o(3), 
        apb3_if_0_filter_factor_bemf_o(2) => 
        apb3_if_0_filter_factor_bemf_o(2), 
        apb3_if_0_filter_factor_bemf_o(1) => 
        apb3_if_0_filter_factor_bemf_o(1), 
        apb3_if_0_filter_factor_bemf_o(0) => 
        apb3_if_0_filter_factor_bemf_o(0), 
        apb3_if_0_auto_restart_no_o(3) => 
        apb3_if_0_auto_restart_no_o(3), 
        apb3_if_0_auto_restart_no_o(2) => 
        apb3_if_0_auto_restart_no_o(2), 
        apb3_if_0_auto_restart_no_o(1) => 
        apb3_if_0_auto_restart_no_o(1), 
        apb3_if_0_auto_restart_no_o(0) => 
        apb3_if_0_auto_restart_no_o(0), 
        apb3_if_0_speed_pi_kp_o(17) => 
        apb3_if_0_speed_pi_kp_o(17), apb3_if_0_speed_pi_kp_o(16)
         => apb3_if_0_speed_pi_kp_o(16), 
        apb3_if_0_speed_pi_kp_o(15) => 
        apb3_if_0_speed_pi_kp_o(15), apb3_if_0_speed_pi_kp_o(14)
         => apb3_if_0_speed_pi_kp_o(14), 
        apb3_if_0_speed_pi_kp_o(13) => 
        apb3_if_0_speed_pi_kp_o(13), apb3_if_0_speed_pi_kp_o(12)
         => apb3_if_0_speed_pi_kp_o(12), 
        apb3_if_0_speed_pi_kp_o(11) => 
        apb3_if_0_speed_pi_kp_o(11), apb3_if_0_speed_pi_kp_o(10)
         => apb3_if_0_speed_pi_kp_o(10), 
        apb3_if_0_speed_pi_kp_o(9) => apb3_if_0_speed_pi_kp_o(9), 
        apb3_if_0_speed_pi_kp_o(8) => apb3_if_0_speed_pi_kp_o(8), 
        apb3_if_0_speed_pi_kp_o(7) => apb3_if_0_speed_pi_kp_o(7), 
        apb3_if_0_speed_pi_kp_o(6) => apb3_if_0_speed_pi_kp_o(6), 
        apb3_if_0_speed_pi_kp_o(5) => apb3_if_0_speed_pi_kp_o(5), 
        apb3_if_0_speed_pi_kp_o(4) => apb3_if_0_speed_pi_kp_o(4), 
        apb3_if_0_speed_pi_kp_o(3) => apb3_if_0_speed_pi_kp_o(3), 
        apb3_if_0_speed_pi_kp_o(2) => apb3_if_0_speed_pi_kp_o(2), 
        apb3_if_0_speed_pi_kp_o(1) => apb3_if_0_speed_pi_kp_o(1), 
        apb3_if_0_speed_pi_kp_o(0) => apb3_if_0_speed_pi_kp_o(0), 
        apb3_if_0_adc_control_reg_val_o(5) => 
        apb3_if_0_adc_control_reg_val_o(5), 
        apb3_if_0_adc_control_reg_val_o(4) => 
        apb3_if_0_adc_control_reg_val_o(4), 
        apb3_if_0_adc_control_reg_val_o(3) => 
        apb3_if_0_adc_control_reg_val_o(3), 
        apb3_if_0_adc_control_reg_val_o(2) => 
        apb3_if_0_adc_control_reg_val_o(2), 
        apb3_if_0_adc_control_reg_val_o(1) => 
        apb3_if_0_adc_control_reg_val_o(1), 
        apb3_if_0_adc_control_reg_val_o(0) => 
        apb3_if_0_adc_control_reg_val_o(0), 
        apb3_if_0_seq_cntl_config_o(3) => 
        apb3_if_0_seq_cntl_config_o(3), 
        apb3_if_0_seq_cntl_config_o(2) => 
        apb3_if_0_seq_cntl_config_o(2), 
        apb3_if_0_seq_cntl_config_o(1) => 
        apb3_if_0_seq_cntl_config_o(1), 
        apb3_if_0_seq_cntl_config_o(0) => 
        apb3_if_0_seq_cntl_config_o(0), 
        apb3_if_0_filter_factor_omega_o(3) => 
        apb3_if_0_filter_factor_omega_o(3), 
        apb3_if_0_filter_factor_omega_o(2) => 
        apb3_if_0_filter_factor_omega_o(2), 
        apb3_if_0_filter_factor_omega_o(1) => 
        apb3_if_0_filter_factor_omega_o(1), 
        apb3_if_0_filter_factor_omega_o(0) => 
        apb3_if_0_filter_factor_omega_o(0), 
        apb3_if_0_adc_channel_ch0_o(15) => 
        apb3_if_0_adc_channel_ch0_o(15), 
        apb3_if_0_adc_channel_ch0_o(14) => 
        apb3_if_0_adc_channel_ch0_o(14), 
        apb3_if_0_adc_channel_ch0_o(13) => 
        apb3_if_0_adc_channel_ch0_o(13), 
        apb3_if_0_adc_channel_ch0_o(12) => 
        apb3_if_0_adc_channel_ch0_o(12), 
        apb3_if_0_adc_channel_ch0_o(11) => 
        apb3_if_0_adc_channel_ch0_o(11), 
        apb3_if_0_adc_channel_ch0_o(10) => 
        apb3_if_0_adc_channel_ch0_o(10), 
        apb3_if_0_adc_channel_ch0_o(9) => 
        apb3_if_0_adc_channel_ch0_o(9), 
        apb3_if_0_adc_channel_ch0_o(8) => 
        apb3_if_0_adc_channel_ch0_o(8), 
        apb3_if_0_adc_channel_ch0_o(7) => 
        apb3_if_0_adc_channel_ch0_o(7), 
        apb3_if_0_adc_channel_ch0_o(6) => 
        apb3_if_0_adc_channel_ch0_o(6), 
        apb3_if_0_adc_channel_ch0_o(5) => 
        apb3_if_0_adc_channel_ch0_o(5), 
        apb3_if_0_adc_channel_ch0_o(4) => 
        apb3_if_0_adc_channel_ch0_o(4), 
        apb3_if_0_adc_channel_ch0_o(3) => 
        apb3_if_0_adc_channel_ch0_o(3), 
        apb3_if_0_adc_channel_ch0_o(2) => 
        apb3_if_0_adc_channel_ch0_o(2), 
        apb3_if_0_adc_channel_ch0_o(1) => 
        apb3_if_0_adc_channel_ch0_o(1), 
        apb3_if_0_adc_channel_ch0_o(0) => 
        apb3_if_0_adc_channel_ch0_o(0), 
        apb3_if_0_adc_channel_ch1_o(15) => 
        apb3_if_0_adc_channel_ch1_o(15), 
        apb3_if_0_adc_channel_ch1_o(14) => 
        apb3_if_0_adc_channel_ch1_o(14), 
        apb3_if_0_adc_channel_ch1_o(13) => 
        apb3_if_0_adc_channel_ch1_o(13), 
        apb3_if_0_adc_channel_ch1_o(12) => 
        apb3_if_0_adc_channel_ch1_o(12), 
        apb3_if_0_adc_channel_ch1_o(11) => 
        apb3_if_0_adc_channel_ch1_o(11), 
        apb3_if_0_adc_channel_ch1_o(10) => 
        apb3_if_0_adc_channel_ch1_o(10), 
        apb3_if_0_adc_channel_ch1_o(9) => 
        apb3_if_0_adc_channel_ch1_o(9), 
        apb3_if_0_adc_channel_ch1_o(8) => 
        apb3_if_0_adc_channel_ch1_o(8), 
        apb3_if_0_adc_channel_ch1_o(7) => 
        apb3_if_0_adc_channel_ch1_o(7), 
        apb3_if_0_adc_channel_ch1_o(6) => 
        apb3_if_0_adc_channel_ch1_o(6), 
        apb3_if_0_adc_channel_ch1_o(5) => 
        apb3_if_0_adc_channel_ch1_o(5), 
        apb3_if_0_adc_channel_ch1_o(4) => 
        apb3_if_0_adc_channel_ch1_o(4), 
        apb3_if_0_adc_channel_ch1_o(3) => 
        apb3_if_0_adc_channel_ch1_o(3), 
        apb3_if_0_adc_channel_ch1_o(2) => 
        apb3_if_0_adc_channel_ch1_o(2), 
        apb3_if_0_adc_channel_ch1_o(1) => 
        apb3_if_0_adc_channel_ch1_o(1), 
        apb3_if_0_adc_channel_ch1_o(0) => 
        apb3_if_0_adc_channel_ch1_o(0), 
        apb3_if_0_adc_channel_ch2_o(15) => 
        apb3_if_0_adc_channel_ch2_o(15), 
        apb3_if_0_adc_channel_ch2_o(14) => 
        apb3_if_0_adc_channel_ch2_o(14), 
        apb3_if_0_adc_channel_ch2_o(13) => 
        apb3_if_0_adc_channel_ch2_o(13), 
        apb3_if_0_adc_channel_ch2_o(12) => 
        apb3_if_0_adc_channel_ch2_o(12), 
        apb3_if_0_adc_channel_ch2_o(11) => 
        apb3_if_0_adc_channel_ch2_o(11), 
        apb3_if_0_adc_channel_ch2_o(10) => 
        apb3_if_0_adc_channel_ch2_o(10), 
        apb3_if_0_adc_channel_ch2_o(9) => 
        apb3_if_0_adc_channel_ch2_o(9), 
        apb3_if_0_adc_channel_ch2_o(8) => 
        apb3_if_0_adc_channel_ch2_o(8), 
        apb3_if_0_adc_channel_ch2_o(7) => 
        apb3_if_0_adc_channel_ch2_o(7), 
        apb3_if_0_adc_channel_ch2_o(6) => 
        apb3_if_0_adc_channel_ch2_o(6), 
        apb3_if_0_adc_channel_ch2_o(5) => 
        apb3_if_0_adc_channel_ch2_o(5), 
        apb3_if_0_adc_channel_ch2_o(4) => 
        apb3_if_0_adc_channel_ch2_o(4), 
        apb3_if_0_adc_channel_ch2_o(3) => 
        apb3_if_0_adc_channel_ch2_o(3), 
        apb3_if_0_adc_channel_ch2_o(2) => 
        apb3_if_0_adc_channel_ch2_o(2), 
        apb3_if_0_adc_channel_ch2_o(1) => 
        apb3_if_0_adc_channel_ch2_o(1), 
        apb3_if_0_adc_channel_ch2_o(0) => 
        apb3_if_0_adc_channel_ch2_o(0), 
        apb3_if_0_adc_channel_ch3_o(15) => 
        apb3_if_0_adc_channel_ch3_o(15), 
        apb3_if_0_adc_channel_ch3_o(14) => 
        apb3_if_0_adc_channel_ch3_o(14), 
        apb3_if_0_adc_channel_ch3_o(13) => 
        apb3_if_0_adc_channel_ch3_o(13), 
        apb3_if_0_adc_channel_ch3_o(12) => 
        apb3_if_0_adc_channel_ch3_o(12), 
        apb3_if_0_adc_channel_ch3_o(11) => 
        apb3_if_0_adc_channel_ch3_o(11), 
        apb3_if_0_adc_channel_ch3_o(10) => 
        apb3_if_0_adc_channel_ch3_o(10), 
        apb3_if_0_adc_channel_ch3_o(9) => 
        apb3_if_0_adc_channel_ch3_o(9), 
        apb3_if_0_adc_channel_ch3_o(8) => 
        apb3_if_0_adc_channel_ch3_o(8), 
        apb3_if_0_adc_channel_ch3_o(7) => 
        apb3_if_0_adc_channel_ch3_o(7), 
        apb3_if_0_adc_channel_ch3_o(6) => 
        apb3_if_0_adc_channel_ch3_o(6), 
        apb3_if_0_adc_channel_ch3_o(5) => 
        apb3_if_0_adc_channel_ch3_o(5), 
        apb3_if_0_adc_channel_ch3_o(4) => 
        apb3_if_0_adc_channel_ch3_o(4), 
        apb3_if_0_adc_channel_ch3_o(3) => 
        apb3_if_0_adc_channel_ch3_o(3), 
        apb3_if_0_adc_channel_ch3_o(2) => 
        apb3_if_0_adc_channel_ch3_o(2), 
        apb3_if_0_adc_channel_ch3_o(1) => 
        apb3_if_0_adc_channel_ch3_o(1), 
        apb3_if_0_adc_channel_ch3_o(0) => 
        apb3_if_0_adc_channel_ch3_o(0), 
        apb3_if_0_Ls_by_Ts_pu_o(17) => 
        apb3_if_0_Ls_by_Ts_pu_o(17), apb3_if_0_Ls_by_Ts_pu_o(16)
         => apb3_if_0_Ls_by_Ts_pu_o(16), 
        apb3_if_0_Ls_by_Ts_pu_o(15) => 
        apb3_if_0_Ls_by_Ts_pu_o(15), apb3_if_0_Ls_by_Ts_pu_o(14)
         => apb3_if_0_Ls_by_Ts_pu_o(14), 
        apb3_if_0_Ls_by_Ts_pu_o(13) => 
        apb3_if_0_Ls_by_Ts_pu_o(13), apb3_if_0_Ls_by_Ts_pu_o(12)
         => apb3_if_0_Ls_by_Ts_pu_o(12), 
        apb3_if_0_Ls_by_Ts_pu_o(11) => 
        apb3_if_0_Ls_by_Ts_pu_o(11), apb3_if_0_Ls_by_Ts_pu_o(10)
         => apb3_if_0_Ls_by_Ts_pu_o(10), 
        apb3_if_0_Ls_by_Ts_pu_o(9) => apb3_if_0_Ls_by_Ts_pu_o(9), 
        apb3_if_0_Ls_by_Ts_pu_o(8) => apb3_if_0_Ls_by_Ts_pu_o(8), 
        apb3_if_0_Ls_by_Ts_pu_o(7) => apb3_if_0_Ls_by_Ts_pu_o(7), 
        apb3_if_0_Ls_by_Ts_pu_o(6) => apb3_if_0_Ls_by_Ts_pu_o(6), 
        apb3_if_0_Ls_by_Ts_pu_o(5) => apb3_if_0_Ls_by_Ts_pu_o(5), 
        apb3_if_0_Ls_by_Ts_pu_o(4) => apb3_if_0_Ls_by_Ts_pu_o(4), 
        apb3_if_0_Ls_by_Ts_pu_o(3) => apb3_if_0_Ls_by_Ts_pu_o(3), 
        apb3_if_0_Ls_by_Ts_pu_o(2) => apb3_if_0_Ls_by_Ts_pu_o(2), 
        apb3_if_0_Ls_by_Ts_pu_o(1) => apb3_if_0_Ls_by_Ts_pu_o(1), 
        apb3_if_0_Ls_by_Ts_pu_o(0) => apb3_if_0_Ls_by_Ts_pu_o(0), 
        apb3_if_0_Rs_pu_o(17) => apb3_if_0_Rs_pu_o(17), 
        apb3_if_0_Rs_pu_o(16) => apb3_if_0_Rs_pu_o(16), 
        apb3_if_0_Rs_pu_o(15) => apb3_if_0_Rs_pu_o(15), 
        apb3_if_0_Rs_pu_o(14) => apb3_if_0_Rs_pu_o(14), 
        apb3_if_0_Rs_pu_o(13) => apb3_if_0_Rs_pu_o(13), 
        apb3_if_0_Rs_pu_o(12) => apb3_if_0_Rs_pu_o(12), 
        apb3_if_0_Rs_pu_o(11) => apb3_if_0_Rs_pu_o(11), 
        apb3_if_0_Rs_pu_o(10) => apb3_if_0_Rs_pu_o(10), 
        apb3_if_0_Rs_pu_o(9) => apb3_if_0_Rs_pu_o(9), 
        apb3_if_0_Rs_pu_o(8) => apb3_if_0_Rs_pu_o(8), 
        apb3_if_0_Rs_pu_o(7) => apb3_if_0_Rs_pu_o(7), 
        apb3_if_0_Rs_pu_o(6) => apb3_if_0_Rs_pu_o(6), 
        apb3_if_0_Rs_pu_o(5) => apb3_if_0_Rs_pu_o(5), 
        apb3_if_0_Rs_pu_o(4) => apb3_if_0_Rs_pu_o(4), 
        apb3_if_0_Rs_pu_o(3) => apb3_if_0_Rs_pu_o(3), 
        apb3_if_0_Rs_pu_o(2) => apb3_if_0_Rs_pu_o(2), 
        apb3_if_0_Rs_pu_o(1) => apb3_if_0_Rs_pu_o(1), 
        apb3_if_0_Rs_pu_o(0) => apb3_if_0_Rs_pu_o(0), 
        apb3_if_0_adc_oc_thresh_o(17) => 
        apb3_if_0_adc_oc_thresh_o(17), 
        apb3_if_0_adc_oc_thresh_o(16) => 
        apb3_if_0_adc_oc_thresh_o(16), 
        apb3_if_0_adc_oc_thresh_o(15) => 
        apb3_if_0_adc_oc_thresh_o(15), 
        apb3_if_0_adc_oc_thresh_o(14) => 
        apb3_if_0_adc_oc_thresh_o(14), 
        apb3_if_0_adc_oc_thresh_o(13) => 
        apb3_if_0_adc_oc_thresh_o(13), 
        apb3_if_0_adc_oc_thresh_o(12) => 
        apb3_if_0_adc_oc_thresh_o(12), 
        apb3_if_0_adc_oc_thresh_o(11) => 
        apb3_if_0_adc_oc_thresh_o(11), 
        apb3_if_0_adc_oc_thresh_o(10) => 
        apb3_if_0_adc_oc_thresh_o(10), 
        apb3_if_0_adc_oc_thresh_o(9) => 
        apb3_if_0_adc_oc_thresh_o(9), 
        apb3_if_0_adc_oc_thresh_o(8) => 
        apb3_if_0_adc_oc_thresh_o(8), 
        apb3_if_0_adc_oc_thresh_o(7) => 
        apb3_if_0_adc_oc_thresh_o(7), 
        apb3_if_0_adc_oc_thresh_o(6) => 
        apb3_if_0_adc_oc_thresh_o(6), 
        apb3_if_0_adc_oc_thresh_o(5) => 
        apb3_if_0_adc_oc_thresh_o(5), 
        apb3_if_0_adc_oc_thresh_o(4) => 
        apb3_if_0_adc_oc_thresh_o(4), 
        apb3_if_0_adc_oc_thresh_o(3) => 
        apb3_if_0_adc_oc_thresh_o(3), 
        apb3_if_0_adc_oc_thresh_o(2) => 
        apb3_if_0_adc_oc_thresh_o(2), 
        apb3_if_0_adc_oc_thresh_o(1) => 
        apb3_if_0_adc_oc_thresh_o(1), 
        apb3_if_0_adc_oc_thresh_o(0) => 
        apb3_if_0_adc_oc_thresh_o(0), 
        apb3_if_0_adc_scale_val_o(17) => 
        apb3_if_0_adc_scale_val_o(17), 
        apb3_if_0_adc_scale_val_o(16) => 
        apb3_if_0_adc_scale_val_o(16), 
        apb3_if_0_adc_scale_val_o(15) => 
        apb3_if_0_adc_scale_val_o(15), 
        apb3_if_0_adc_scale_val_o(14) => 
        apb3_if_0_adc_scale_val_o(14), 
        apb3_if_0_adc_scale_val_o(13) => 
        apb3_if_0_adc_scale_val_o(13), 
        apb3_if_0_adc_scale_val_o(12) => 
        apb3_if_0_adc_scale_val_o(12), 
        apb3_if_0_adc_scale_val_o(11) => 
        apb3_if_0_adc_scale_val_o(11), 
        apb3_if_0_adc_scale_val_o(10) => 
        apb3_if_0_adc_scale_val_o(10), 
        apb3_if_0_adc_scale_val_o(9) => 
        apb3_if_0_adc_scale_val_o(9), 
        apb3_if_0_adc_scale_val_o(8) => 
        apb3_if_0_adc_scale_val_o(8), 
        apb3_if_0_adc_scale_val_o(7) => 
        apb3_if_0_adc_scale_val_o(7), 
        apb3_if_0_adc_scale_val_o(6) => 
        apb3_if_0_adc_scale_val_o(6), 
        apb3_if_0_adc_scale_val_o(5) => 
        apb3_if_0_adc_scale_val_o(5), 
        apb3_if_0_adc_scale_val_o(4) => 
        apb3_if_0_adc_scale_val_o(4), 
        apb3_if_0_adc_scale_val_o(3) => 
        apb3_if_0_adc_scale_val_o(3), 
        apb3_if_0_adc_scale_val_o(2) => 
        apb3_if_0_adc_scale_val_o(2), 
        apb3_if_0_adc_scale_val_o(1) => 
        apb3_if_0_adc_scale_val_o(1), 
        apb3_if_0_adc_scale_val_o(0) => 
        apb3_if_0_adc_scale_val_o(0), apb3_if_0_angle_ki_o(17)
         => apb3_if_0_angle_ki_o(17), apb3_if_0_angle_ki_o(16)
         => apb3_if_0_angle_ki_o(16), apb3_if_0_angle_ki_o(15)
         => apb3_if_0_angle_ki_o(15), apb3_if_0_angle_ki_o(14)
         => apb3_if_0_angle_ki_o(14), apb3_if_0_angle_ki_o(13)
         => apb3_if_0_angle_ki_o(13), apb3_if_0_angle_ki_o(12)
         => apb3_if_0_angle_ki_o(12), apb3_if_0_angle_ki_o(11)
         => apb3_if_0_angle_ki_o(11), apb3_if_0_angle_ki_o(10)
         => apb3_if_0_angle_ki_o(10), apb3_if_0_angle_ki_o(9) => 
        apb3_if_0_angle_ki_o(9), apb3_if_0_angle_ki_o(8) => 
        apb3_if_0_angle_ki_o(8), apb3_if_0_angle_ki_o(7) => 
        apb3_if_0_angle_ki_o(7), apb3_if_0_angle_ki_o(6) => 
        apb3_if_0_angle_ki_o(6), apb3_if_0_angle_ki_o(5) => 
        apb3_if_0_angle_ki_o(5), apb3_if_0_angle_ki_o(4) => 
        apb3_if_0_angle_ki_o(4), apb3_if_0_angle_ki_o(3) => 
        apb3_if_0_angle_ki_o(3), apb3_if_0_angle_ki_o(2) => 
        apb3_if_0_angle_ki_o(2), apb3_if_0_angle_ki_o(1) => 
        apb3_if_0_angle_ki_o(1), apb3_if_0_angle_ki_o(0) => 
        apb3_if_0_angle_ki_o(0), apb3_if_0_angle_kp_o(17) => 
        apb3_if_0_angle_kp_o(17), apb3_if_0_angle_kp_o(16) => 
        apb3_if_0_angle_kp_o(16), apb3_if_0_angle_kp_o(15) => 
        apb3_if_0_angle_kp_o(15), apb3_if_0_angle_kp_o(14) => 
        apb3_if_0_angle_kp_o(14), apb3_if_0_angle_kp_o(13) => 
        apb3_if_0_angle_kp_o(13), apb3_if_0_angle_kp_o(12) => 
        apb3_if_0_angle_kp_o(12), apb3_if_0_angle_kp_o(11) => 
        apb3_if_0_angle_kp_o(11), apb3_if_0_angle_kp_o(10) => 
        apb3_if_0_angle_kp_o(10), apb3_if_0_angle_kp_o(9) => 
        apb3_if_0_angle_kp_o(9), apb3_if_0_angle_kp_o(8) => 
        apb3_if_0_angle_kp_o(8), apb3_if_0_angle_kp_o(7) => 
        apb3_if_0_angle_kp_o(7), apb3_if_0_angle_kp_o(6) => 
        apb3_if_0_angle_kp_o(6), apb3_if_0_angle_kp_o(5) => 
        apb3_if_0_angle_kp_o(5), apb3_if_0_angle_kp_o(4) => 
        apb3_if_0_angle_kp_o(4), apb3_if_0_angle_kp_o(3) => 
        apb3_if_0_angle_kp_o(3), apb3_if_0_angle_kp_o(2) => 
        apb3_if_0_angle_kp_o(2), apb3_if_0_angle_kp_o(1) => 
        apb3_if_0_angle_kp_o(1), apb3_if_0_angle_kp_o(0) => 
        apb3_if_0_angle_kp_o(0), prdata_o_1_2_0_a2_17_0(1) => 
        prdata_o_1_2_0_a2_17_0(1), prdata_o_1_2_0_a2_11_0(1) => 
        prdata_o_1_2_0_a2_11_0(1), 
        adc_interface_0_result_ch1_o(11) => 
        adc_interface_0_result_ch1_o(11), 
        adc_interface_0_result_ch1_o(10) => 
        adc_interface_0_result_ch1_o(10), 
        adc_interface_0_result_ch1_o(9) => 
        adc_interface_0_result_ch1_o(9), 
        adc_interface_0_result_ch1_o(8) => 
        adc_interface_0_result_ch1_o(8), 
        adc_interface_0_result_ch1_o(7) => 
        adc_interface_0_result_ch1_o(7), 
        adc_interface_0_result_ch1_o(6) => 
        adc_interface_0_result_ch1_o(6), 
        adc_interface_0_result_ch1_o(5) => 
        adc_interface_0_result_ch1_o(5), 
        adc_interface_0_result_ch1_o(4) => 
        adc_interface_0_result_ch1_o(4), 
        adc_interface_0_result_ch1_o(3) => 
        adc_interface_0_result_ch1_o(3), 
        adc_interface_0_result_ch1_o(2) => 
        adc_interface_0_result_ch1_o(2), 
        adc_interface_0_result_ch1_o(1) => 
        adc_interface_0_result_ch1_o(1), 
        adc_interface_0_result_ch1_o(0) => 
        adc_interface_0_result_ch1_o(0), 
        adc_interface_0_result_ch0_o(11) => 
        adc_interface_0_result_ch0_o(11), 
        adc_interface_0_result_ch0_o(10) => 
        adc_interface_0_result_ch0_o(10), 
        adc_interface_0_result_ch0_o(9) => 
        adc_interface_0_result_ch0_o(9), 
        adc_interface_0_result_ch0_o(8) => 
        adc_interface_0_result_ch0_o(8), 
        adc_interface_0_result_ch0_o(7) => 
        adc_interface_0_result_ch0_o(7), 
        adc_interface_0_result_ch0_o(6) => 
        adc_interface_0_result_ch0_o(6), 
        adc_interface_0_result_ch0_o(5) => 
        adc_interface_0_result_ch0_o(5), 
        adc_interface_0_result_ch0_o(4) => 
        adc_interface_0_result_ch0_o(4), 
        adc_interface_0_result_ch0_o(3) => 
        adc_interface_0_result_ch0_o(3), 
        adc_interface_0_result_ch0_o(2) => 
        adc_interface_0_result_ch0_o(2), 
        adc_interface_0_result_ch0_o(1) => 
        adc_interface_0_result_ch0_o(1), 
        adc_interface_0_result_ch0_o(0) => 
        adc_interface_0_result_ch0_o(0), 
        adc_measurements_0_adc_result_ch3_o(11) => 
        adc_measurements_0_adc_result_ch3_o(11), 
        adc_measurements_0_adc_result_ch3_o(10) => 
        adc_measurements_0_adc_result_ch3_o(10), 
        adc_measurements_0_adc_result_ch3_o(9) => 
        adc_measurements_0_adc_result_ch3_o(9), 
        adc_measurements_0_adc_result_ch3_o(8) => 
        adc_measurements_0_adc_result_ch3_o(8), 
        adc_measurements_0_adc_result_ch3_o(7) => 
        adc_measurements_0_adc_result_ch3_o(7), 
        adc_measurements_0_adc_result_ch3_o(6) => 
        adc_measurements_0_adc_result_ch3_o(6), 
        adc_measurements_0_adc_result_ch3_o(5) => 
        adc_measurements_0_adc_result_ch3_o(5), 
        adc_measurements_0_adc_result_ch3_o(4) => 
        adc_measurements_0_adc_result_ch3_o(4), 
        adc_measurements_0_adc_result_ch3_o(3) => 
        adc_measurements_0_adc_result_ch3_o(3), 
        adc_measurements_0_adc_result_ch3_o(2) => 
        adc_measurements_0_adc_result_ch3_o(2), 
        adc_measurements_0_adc_result_ch3_o(1) => 
        adc_measurements_0_adc_result_ch3_o(1), 
        adc_measurements_0_adc_result_ch3_o(0) => 
        adc_measurements_0_adc_result_ch3_o(0), 
        adc_measurements_0_adc_result_ch2_o(11) => 
        adc_measurements_0_adc_result_ch2_o(11), 
        adc_measurements_0_adc_result_ch2_o(10) => 
        adc_measurements_0_adc_result_ch2_o(10), 
        adc_measurements_0_adc_result_ch2_o(9) => 
        adc_measurements_0_adc_result_ch2_o(9), 
        adc_measurements_0_adc_result_ch2_o(8) => 
        adc_measurements_0_adc_result_ch2_o(8), 
        adc_measurements_0_adc_result_ch2_o(7) => 
        adc_measurements_0_adc_result_ch2_o(7), 
        adc_measurements_0_adc_result_ch2_o(6) => 
        adc_measurements_0_adc_result_ch2_o(6), 
        adc_measurements_0_adc_result_ch2_o(5) => 
        adc_measurements_0_adc_result_ch2_o(5), 
        adc_measurements_0_adc_result_ch2_o(4) => 
        adc_measurements_0_adc_result_ch2_o(4), 
        adc_measurements_0_adc_result_ch2_o(3) => 
        adc_measurements_0_adc_result_ch2_o(3), 
        adc_measurements_0_adc_result_ch2_o(2) => 
        adc_measurements_0_adc_result_ch2_o(2), 
        adc_measurements_0_adc_result_ch2_o(1) => 
        adc_measurements_0_adc_result_ch2_o(1), 
        adc_measurements_0_adc_result_ch2_o(0) => 
        adc_measurements_0_adc_result_ch2_o(0), 
        RATE_LIMITER_0_rl_out_o(17) => 
        RATE_LIMITER_0_rl_out_o(17), RATE_LIMITER_0_rl_out_o(16)
         => RATE_LIMITER_0_rl_out_o(16), 
        RATE_LIMITER_0_rl_out_o(15) => 
        RATE_LIMITER_0_rl_out_o(15), RATE_LIMITER_0_rl_out_o(14)
         => RATE_LIMITER_0_rl_out_o(14), 
        RATE_LIMITER_0_rl_out_o(13) => 
        RATE_LIMITER_0_rl_out_o(13), RATE_LIMITER_0_rl_out_o(12)
         => RATE_LIMITER_0_rl_out_o(12), 
        RATE_LIMITER_0_rl_out_o(11) => 
        RATE_LIMITER_0_rl_out_o(11), RATE_LIMITER_0_rl_out_o(10)
         => RATE_LIMITER_0_rl_out_o(10), 
        RATE_LIMITER_0_rl_out_o(9) => RATE_LIMITER_0_rl_out_o(9), 
        RATE_LIMITER_0_rl_out_o(8) => RATE_LIMITER_0_rl_out_o(8), 
        RATE_LIMITER_0_rl_out_o(7) => RATE_LIMITER_0_rl_out_o(7), 
        RATE_LIMITER_0_rl_out_o(6) => RATE_LIMITER_0_rl_out_o(6), 
        RATE_LIMITER_0_rl_out_o(5) => RATE_LIMITER_0_rl_out_o(5), 
        RATE_LIMITER_0_rl_out_o(4) => RATE_LIMITER_0_rl_out_o(4), 
        RATE_LIMITER_0_rl_out_o(3) => RATE_LIMITER_0_rl_out_o(3), 
        RATE_LIMITER_0_rl_out_o(2) => RATE_LIMITER_0_rl_out_o(2), 
        RATE_LIMITER_0_rl_out_o(1) => RATE_LIMITER_0_rl_out_o(1), 
        RATE_LIMITER_0_rl_out_o(0) => RATE_LIMITER_0_rl_out_o(0), 
        BLDC_ESTIMATOR_1_ealpha_o(17) => 
        BLDC_ESTIMATOR_1_ealpha_o(17), 
        BLDC_ESTIMATOR_1_ealpha_o(16) => 
        BLDC_ESTIMATOR_1_ealpha_o(16), 
        BLDC_ESTIMATOR_1_ealpha_o(15) => 
        BLDC_ESTIMATOR_1_ealpha_o(15), 
        BLDC_ESTIMATOR_1_ealpha_o(14) => 
        BLDC_ESTIMATOR_1_ealpha_o(14), 
        BLDC_ESTIMATOR_1_ealpha_o(13) => 
        BLDC_ESTIMATOR_1_ealpha_o(13), 
        BLDC_ESTIMATOR_1_ealpha_o(12) => 
        BLDC_ESTIMATOR_1_ealpha_o(12), 
        BLDC_ESTIMATOR_1_ealpha_o(11) => 
        BLDC_ESTIMATOR_1_ealpha_o(11), 
        BLDC_ESTIMATOR_1_ealpha_o(10) => 
        BLDC_ESTIMATOR_1_ealpha_o(10), 
        BLDC_ESTIMATOR_1_ealpha_o(9) => 
        BLDC_ESTIMATOR_1_ealpha_o(9), 
        BLDC_ESTIMATOR_1_ealpha_o(8) => 
        BLDC_ESTIMATOR_1_ealpha_o(8), 
        BLDC_ESTIMATOR_1_ealpha_o(7) => 
        BLDC_ESTIMATOR_1_ealpha_o(7), 
        BLDC_ESTIMATOR_1_ealpha_o(6) => 
        BLDC_ESTIMATOR_1_ealpha_o(6), 
        BLDC_ESTIMATOR_1_ealpha_o(5) => 
        BLDC_ESTIMATOR_1_ealpha_o(5), 
        BLDC_ESTIMATOR_1_ealpha_o(4) => 
        BLDC_ESTIMATOR_1_ealpha_o(4), 
        BLDC_ESTIMATOR_1_ealpha_o(3) => 
        BLDC_ESTIMATOR_1_ealpha_o(3), 
        BLDC_ESTIMATOR_1_ealpha_o(2) => 
        BLDC_ESTIMATOR_1_ealpha_o(2), 
        BLDC_ESTIMATOR_1_ealpha_o(1) => 
        BLDC_ESTIMATOR_1_ealpha_o(1), 
        BLDC_ESTIMATOR_1_ealpha_o(0) => 
        BLDC_ESTIMATOR_1_ealpha_o(0), 
        BLDC_ESTIMATOR_1_theta_o(17) => 
        BLDC_ESTIMATOR_1_theta_o(17), 
        BLDC_ESTIMATOR_1_theta_o(16) => 
        BLDC_ESTIMATOR_1_theta_o(16), 
        BLDC_ESTIMATOR_1_theta_o(15) => 
        BLDC_ESTIMATOR_1_theta_o(15), 
        BLDC_ESTIMATOR_1_theta_o(14) => 
        BLDC_ESTIMATOR_1_theta_o(14), 
        BLDC_ESTIMATOR_1_theta_o(13) => 
        BLDC_ESTIMATOR_1_theta_o(13), 
        BLDC_ESTIMATOR_1_theta_o(12) => 
        BLDC_ESTIMATOR_1_theta_o(12), 
        BLDC_ESTIMATOR_1_theta_o(11) => 
        BLDC_ESTIMATOR_1_theta_o(11), 
        BLDC_ESTIMATOR_1_theta_o(10) => 
        BLDC_ESTIMATOR_1_theta_o(10), BLDC_ESTIMATOR_1_theta_o(9)
         => BLDC_ESTIMATOR_1_theta_o(9), 
        BLDC_ESTIMATOR_1_theta_o(8) => 
        BLDC_ESTIMATOR_1_theta_o(8), BLDC_ESTIMATOR_1_theta_o(7)
         => BLDC_ESTIMATOR_1_theta_o(7), 
        BLDC_ESTIMATOR_1_theta_o(6) => 
        BLDC_ESTIMATOR_1_theta_o(6), BLDC_ESTIMATOR_1_theta_o(5)
         => BLDC_ESTIMATOR_1_theta_o(5), 
        BLDC_ESTIMATOR_1_theta_o(4) => 
        BLDC_ESTIMATOR_1_theta_o(4), BLDC_ESTIMATOR_1_theta_o(3)
         => BLDC_ESTIMATOR_1_theta_o(3), 
        BLDC_ESTIMATOR_1_theta_o(2) => 
        BLDC_ESTIMATOR_1_theta_o(2), BLDC_ESTIMATOR_1_theta_o(1)
         => BLDC_ESTIMATOR_1_theta_o(1), 
        BLDC_ESTIMATOR_1_theta_o(0) => 
        BLDC_ESTIMATOR_1_theta_o(0), OLMNG_1_theta_o(17) => 
        OLMNG_1_theta_o(17), OLMNG_1_theta_o(16) => 
        OLMNG_1_theta_o(16), OLMNG_1_theta_o(15) => 
        OLMNG_1_theta_o(15), OLMNG_1_theta_o(14) => 
        OLMNG_1_theta_o(14), OLMNG_1_theta_o(13) => 
        OLMNG_1_theta_o(13), OLMNG_1_theta_o(12) => 
        OLMNG_1_theta_o(12), OLMNG_1_theta_o(11) => 
        OLMNG_1_theta_o(11), OLMNG_1_theta_o(10) => 
        OLMNG_1_theta_o(10), OLMNG_1_theta_o(9) => 
        OLMNG_1_theta_o(9), OLMNG_1_theta_o(8) => 
        OLMNG_1_theta_o(8), OLMNG_1_theta_o(7) => 
        OLMNG_1_theta_o(7), OLMNG_1_theta_o(6) => 
        OLMNG_1_theta_o(6), OLMNG_1_theta_o(5) => 
        OLMNG_1_theta_o(5), OLMNG_1_theta_o(4) => 
        OLMNG_1_theta_o(4), OLMNG_1_theta_o(3) => 
        OLMNG_1_theta_o(3), OLMNG_1_theta_o(2) => 
        OLMNG_1_theta_o(2), OLMNG_1_theta_o(1) => 
        OLMNG_1_theta_o(1), OLMNG_1_theta_o(0) => 
        OLMNG_1_theta_o(0), ADC_SCALING_1_ib_adc_o(17) => 
        ADC_SCALING_1_ib_adc_o(17), ADC_SCALING_1_ib_adc_o(16)
         => ADC_SCALING_1_ib_adc_o(16), 
        ADC_SCALING_1_ib_adc_o(15) => ADC_SCALING_1_ib_adc_o(15), 
        ADC_SCALING_1_ib_adc_o(14) => ADC_SCALING_1_ib_adc_o(14), 
        ADC_SCALING_1_ib_adc_o(13) => ADC_SCALING_1_ib_adc_o(13), 
        ADC_SCALING_1_ib_adc_o(12) => ADC_SCALING_1_ib_adc_o(12), 
        ADC_SCALING_1_ib_adc_o(11) => ADC_SCALING_1_ib_adc_o(11), 
        ADC_SCALING_1_ib_adc_o(10) => ADC_SCALING_1_ib_adc_o(10), 
        ADC_SCALING_1_ib_adc_o(9) => ADC_SCALING_1_ib_adc_o(9), 
        ADC_SCALING_1_ib_adc_o(8) => ADC_SCALING_1_ib_adc_o(8), 
        ADC_SCALING_1_ib_adc_o(7) => ADC_SCALING_1_ib_adc_o(7), 
        ADC_SCALING_1_ib_adc_o(6) => ADC_SCALING_1_ib_adc_o(6), 
        ADC_SCALING_1_ib_adc_o(5) => ADC_SCALING_1_ib_adc_o(5), 
        ADC_SCALING_1_ib_adc_o(4) => ADC_SCALING_1_ib_adc_o(4), 
        ADC_SCALING_1_ib_adc_o(3) => ADC_SCALING_1_ib_adc_o(3), 
        ADC_SCALING_1_ib_adc_o(2) => ADC_SCALING_1_ib_adc_o(2), 
        ADC_SCALING_1_ib_adc_o(1) => ADC_SCALING_1_ib_adc_o(1), 
        ADC_SCALING_1_ib_adc_o(0) => ADC_SCALING_1_ib_adc_o(0), 
        ADC_SCALING_1_ia_adc_o(17) => ADC_SCALING_1_ia_adc_o(17), 
        ADC_SCALING_1_ia_adc_o(16) => ADC_SCALING_1_ia_adc_o(16), 
        ADC_SCALING_1_ia_adc_o(15) => ADC_SCALING_1_ia_adc_o(15), 
        ADC_SCALING_1_ia_adc_o(14) => ADC_SCALING_1_ia_adc_o(14), 
        ADC_SCALING_1_ia_adc_o(13) => ADC_SCALING_1_ia_adc_o(13), 
        ADC_SCALING_1_ia_adc_o(12) => ADC_SCALING_1_ia_adc_o(12), 
        ADC_SCALING_1_ia_adc_o(11) => ADC_SCALING_1_ia_adc_o(11), 
        ADC_SCALING_1_ia_adc_o(10) => ADC_SCALING_1_ia_adc_o(10), 
        ADC_SCALING_1_ia_adc_o(9) => ADC_SCALING_1_ia_adc_o(9), 
        ADC_SCALING_1_ia_adc_o(8) => ADC_SCALING_1_ia_adc_o(8), 
        ADC_SCALING_1_ia_adc_o(7) => ADC_SCALING_1_ia_adc_o(7), 
        ADC_SCALING_1_ia_adc_o(6) => ADC_SCALING_1_ia_adc_o(6), 
        ADC_SCALING_1_ia_adc_o(5) => ADC_SCALING_1_ia_adc_o(5), 
        ADC_SCALING_1_ia_adc_o(4) => ADC_SCALING_1_ia_adc_o(4), 
        ADC_SCALING_1_ia_adc_o(3) => ADC_SCALING_1_ia_adc_o(3), 
        ADC_SCALING_1_ia_adc_o(2) => ADC_SCALING_1_ia_adc_o(2), 
        ADC_SCALING_1_ia_adc_o(1) => ADC_SCALING_1_ia_adc_o(1), 
        ADC_SCALING_1_ia_adc_o(0) => ADC_SCALING_1_ia_adc_o(0), 
        FOC_TRANSFORMS_0_iq_o(17) => FOC_TRANSFORMS_0_iq_o(17), 
        FOC_TRANSFORMS_0_iq_o(16) => FOC_TRANSFORMS_0_iq_o(16), 
        FOC_TRANSFORMS_0_iq_o(15) => FOC_TRANSFORMS_0_iq_o(15), 
        FOC_TRANSFORMS_0_iq_o(14) => FOC_TRANSFORMS_0_iq_o(14), 
        FOC_TRANSFORMS_0_iq_o(13) => FOC_TRANSFORMS_0_iq_o(13), 
        FOC_TRANSFORMS_0_iq_o(12) => FOC_TRANSFORMS_0_iq_o(12), 
        FOC_TRANSFORMS_0_iq_o(11) => FOC_TRANSFORMS_0_iq_o(11), 
        FOC_TRANSFORMS_0_iq_o(10) => FOC_TRANSFORMS_0_iq_o(10), 
        FOC_TRANSFORMS_0_iq_o(9) => FOC_TRANSFORMS_0_iq_o(9), 
        FOC_TRANSFORMS_0_iq_o(8) => FOC_TRANSFORMS_0_iq_o(8), 
        FOC_TRANSFORMS_0_iq_o(7) => FOC_TRANSFORMS_0_iq_o(7), 
        FOC_TRANSFORMS_0_iq_o(6) => FOC_TRANSFORMS_0_iq_o(6), 
        FOC_TRANSFORMS_0_iq_o(5) => FOC_TRANSFORMS_0_iq_o(5), 
        FOC_TRANSFORMS_0_iq_o(4) => FOC_TRANSFORMS_0_iq_o(4), 
        FOC_TRANSFORMS_0_iq_o(3) => FOC_TRANSFORMS_0_iq_o(3), 
        FOC_TRANSFORMS_0_iq_o(2) => FOC_TRANSFORMS_0_iq_o(2), 
        FOC_TRANSFORMS_0_iq_o(1) => FOC_TRANSFORMS_0_iq_o(1), 
        FOC_TRANSFORMS_0_iq_o(0) => FOC_TRANSFORMS_0_iq_o(0), 
        FOC_TRANSFORMS_0_id_o(17) => FOC_TRANSFORMS_0_id_o(17), 
        FOC_TRANSFORMS_0_id_o(16) => FOC_TRANSFORMS_0_id_o(16), 
        FOC_TRANSFORMS_0_id_o(15) => FOC_TRANSFORMS_0_id_o(15), 
        FOC_TRANSFORMS_0_id_o(14) => FOC_TRANSFORMS_0_id_o(14), 
        FOC_TRANSFORMS_0_id_o(13) => FOC_TRANSFORMS_0_id_o(13), 
        FOC_TRANSFORMS_0_id_o(12) => FOC_TRANSFORMS_0_id_o(12), 
        FOC_TRANSFORMS_0_id_o(11) => FOC_TRANSFORMS_0_id_o(11), 
        FOC_TRANSFORMS_0_id_o(10) => FOC_TRANSFORMS_0_id_o(10), 
        FOC_TRANSFORMS_0_id_o(9) => FOC_TRANSFORMS_0_id_o(9), 
        FOC_TRANSFORMS_0_id_o(8) => FOC_TRANSFORMS_0_id_o(8), 
        FOC_TRANSFORMS_0_id_o(7) => FOC_TRANSFORMS_0_id_o(7), 
        FOC_TRANSFORMS_0_id_o(6) => FOC_TRANSFORMS_0_id_o(6), 
        FOC_TRANSFORMS_0_id_o(5) => FOC_TRANSFORMS_0_id_o(5), 
        FOC_TRANSFORMS_0_id_o(4) => FOC_TRANSFORMS_0_id_o(4), 
        FOC_TRANSFORMS_0_id_o(3) => FOC_TRANSFORMS_0_id_o(3), 
        FOC_TRANSFORMS_0_id_o(2) => FOC_TRANSFORMS_0_id_o(2), 
        FOC_TRANSFORMS_0_id_o(1) => FOC_TRANSFORMS_0_id_o(1), 
        FOC_TRANSFORMS_0_id_o(0) => FOC_TRANSFORMS_0_id_o(0), 
        MC_System_0_AMBA_SLAVE_1_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), 
        MC_System_0_AMBA_SLAVE_1_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), 
        MC_System_0_AMBA_SLAVE_1_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), 
        MC_System_0_AMBA_SLAVE_1_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        MC_System_0_AMBA_SLAVE_1_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), 
        MC_System_0_AMBA_SLAVE_1_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), 
        MC_System_0_AMBA_SLAVE_1_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), 
        MC_System_0_AMBA_SLAVE_1_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), 
        MC_System_0_AMBA_SLAVE_1_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        MC_System_0_AMBA_SLAVE_1_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        MC_System_0_AMBA_SLAVE_1_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        prdata_o_1_2_0_a2_12_0(1) => prdata_o_1_2_0_a2_12_0(1), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(17) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(17), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(16) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(16), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(15) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(15), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(14) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(14), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(13) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(13), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(12) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(12), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(11) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(11), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(10) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(10), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(9) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(9), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(8) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(8), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(7) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(7), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(6) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(6), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(5) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(5), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(4) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(4), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(3) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(3), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(2) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(2), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0), net_189(17) => 
        net_189(17), net_189(16) => net_189(16), net_189(15) => 
        net_189(15), net_189(14) => net_189(14), net_189(13) => 
        net_189(13), net_189(12) => net_189(12), net_189(11) => 
        net_189(11), net_189(10) => net_189(10), net_189(9) => 
        net_189(9), net_189(8) => net_189(8), net_189(7) => 
        net_189(7), net_189(6) => net_189(6), net_189(5) => 
        net_189(5), net_189(4) => net_189(4), net_189(3) => 
        net_189(3), net_189(2) => net_189(2), net_189(1) => 
        net_189(1), net_189(0) => net_189(0), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(17) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(17), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(16) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(16), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(15) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(15), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(14) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(14), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(13) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(13), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(12) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(12), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(11) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(11), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(10) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(10), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(9) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(9), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(8) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(8), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(7) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(7), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(6) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(6), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(5) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(5), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(4) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(4), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(3) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(3), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(2) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(2), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(1) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(1), 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(0) => 
        BLDC_ESTIMATOR_1_ealpha_filtered_o(0), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(17) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(17), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(16) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(16), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(15) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(15), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(14) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(14), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(13) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(13), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(12) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(12), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(11) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(11), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(10) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(10), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(9) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(9), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(8) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(8), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(7) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(7), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(6) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(6), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(5) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(5), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(4) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(4), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(3) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(3), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(2) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(2), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(17) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(17), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(16) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(16), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(15) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(15), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(14) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(14), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(13) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(13), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(12) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(12), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(11) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(11), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(10) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(10), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(9) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(9), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(8) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(8), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(7) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(7), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(6) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(6), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(5) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(5), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(4) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(4), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(3) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(3), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(2) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(2), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(1) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(1), 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(0) => 
        BLDC_ESTIMATOR_1_ebeta_filtered_o(0), 
        BLDC_ESTIMATOR_1_ebeta_o(17) => 
        BLDC_ESTIMATOR_1_ebeta_o(17), 
        BLDC_ESTIMATOR_1_ebeta_o(16) => 
        BLDC_ESTIMATOR_1_ebeta_o(16), 
        BLDC_ESTIMATOR_1_ebeta_o(15) => 
        BLDC_ESTIMATOR_1_ebeta_o(15), 
        BLDC_ESTIMATOR_1_ebeta_o(14) => 
        BLDC_ESTIMATOR_1_ebeta_o(14), 
        BLDC_ESTIMATOR_1_ebeta_o(13) => 
        BLDC_ESTIMATOR_1_ebeta_o(13), 
        BLDC_ESTIMATOR_1_ebeta_o(12) => 
        BLDC_ESTIMATOR_1_ebeta_o(12), 
        BLDC_ESTIMATOR_1_ebeta_o(11) => 
        BLDC_ESTIMATOR_1_ebeta_o(11), 
        BLDC_ESTIMATOR_1_ebeta_o(10) => 
        BLDC_ESTIMATOR_1_ebeta_o(10), BLDC_ESTIMATOR_1_ebeta_o(9)
         => BLDC_ESTIMATOR_1_ebeta_o(9), 
        BLDC_ESTIMATOR_1_ebeta_o(8) => 
        BLDC_ESTIMATOR_1_ebeta_o(8), BLDC_ESTIMATOR_1_ebeta_o(7)
         => BLDC_ESTIMATOR_1_ebeta_o(7), 
        BLDC_ESTIMATOR_1_ebeta_o(6) => 
        BLDC_ESTIMATOR_1_ebeta_o(6), BLDC_ESTIMATOR_1_ebeta_o(5)
         => BLDC_ESTIMATOR_1_ebeta_o(5), 
        BLDC_ESTIMATOR_1_ebeta_o(4) => 
        BLDC_ESTIMATOR_1_ebeta_o(4), BLDC_ESTIMATOR_1_ebeta_o(3)
         => BLDC_ESTIMATOR_1_ebeta_o(3), 
        BLDC_ESTIMATOR_1_ebeta_o(2) => 
        BLDC_ESTIMATOR_1_ebeta_o(2), BLDC_ESTIMATOR_1_ebeta_o(1)
         => BLDC_ESTIMATOR_1_ebeta_o(1), 
        BLDC_ESTIMATOR_1_ebeta_o(0) => 
        BLDC_ESTIMATOR_1_ebeta_o(0), 
        BLDC_ESTIMATOR_0_speed_filtered_o(17) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(17), 
        BLDC_ESTIMATOR_0_speed_filtered_o(16) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(16), 
        BLDC_ESTIMATOR_0_speed_filtered_o(15) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(15), 
        BLDC_ESTIMATOR_0_speed_filtered_o(14) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(14), 
        BLDC_ESTIMATOR_0_speed_filtered_o(13) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(13), 
        BLDC_ESTIMATOR_0_speed_filtered_o(12) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(12), 
        BLDC_ESTIMATOR_0_speed_filtered_o(11) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(11), 
        BLDC_ESTIMATOR_0_speed_filtered_o(10) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(10), 
        BLDC_ESTIMATOR_0_speed_filtered_o(9) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(9), 
        BLDC_ESTIMATOR_0_speed_filtered_o(8) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(8), 
        BLDC_ESTIMATOR_0_speed_filtered_o(7) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(7), 
        BLDC_ESTIMATOR_0_speed_filtered_o(6) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(6), 
        BLDC_ESTIMATOR_0_speed_filtered_o(5) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(5), 
        BLDC_ESTIMATOR_0_speed_filtered_o(4) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(4), 
        BLDC_ESTIMATOR_0_speed_filtered_o(3) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(3), 
        BLDC_ESTIMATOR_0_speed_filtered_o(2) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(2), 
        BLDC_ESTIMATOR_0_speed_filtered_o(1) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(1), 
        BLDC_ESTIMATOR_0_speed_filtered_o(0) => 
        BLDC_ESTIMATOR_0_speed_filtered_o(0), 
        FOC_TRANSFORMS_0_valpha_o(17) => 
        FOC_TRANSFORMS_0_valpha_o(17), 
        FOC_TRANSFORMS_0_valpha_o(16) => 
        FOC_TRANSFORMS_0_valpha_o(16), 
        FOC_TRANSFORMS_0_valpha_o(15) => 
        FOC_TRANSFORMS_0_valpha_o(15), 
        FOC_TRANSFORMS_0_valpha_o(14) => 
        FOC_TRANSFORMS_0_valpha_o(14), 
        FOC_TRANSFORMS_0_valpha_o(13) => 
        FOC_TRANSFORMS_0_valpha_o(13), 
        FOC_TRANSFORMS_0_valpha_o(12) => 
        FOC_TRANSFORMS_0_valpha_o(12), 
        FOC_TRANSFORMS_0_valpha_o(11) => 
        FOC_TRANSFORMS_0_valpha_o(11), 
        FOC_TRANSFORMS_0_valpha_o(10) => 
        FOC_TRANSFORMS_0_valpha_o(10), 
        FOC_TRANSFORMS_0_valpha_o(9) => 
        FOC_TRANSFORMS_0_valpha_o(9), 
        FOC_TRANSFORMS_0_valpha_o(8) => 
        FOC_TRANSFORMS_0_valpha_o(8), 
        FOC_TRANSFORMS_0_valpha_o(7) => 
        FOC_TRANSFORMS_0_valpha_o(7), 
        FOC_TRANSFORMS_0_valpha_o(6) => 
        FOC_TRANSFORMS_0_valpha_o(6), 
        FOC_TRANSFORMS_0_valpha_o(5) => 
        FOC_TRANSFORMS_0_valpha_o(5), 
        FOC_TRANSFORMS_0_valpha_o(4) => 
        FOC_TRANSFORMS_0_valpha_o(4), 
        FOC_TRANSFORMS_0_valpha_o(3) => 
        FOC_TRANSFORMS_0_valpha_o(3), 
        FOC_TRANSFORMS_0_valpha_o(2) => 
        FOC_TRANSFORMS_0_valpha_o(2), 
        FOC_TRANSFORMS_0_valpha_o(1) => 
        FOC_TRANSFORMS_0_valpha_o(1), 
        FOC_TRANSFORMS_0_valpha_o(0) => 
        FOC_TRANSFORMS_0_valpha_o(0), SEQ_CONTROLLER_1_state_o_0
         => SEQ_CONTROLLER_1_state_o(0), 
        SEQ_CONTROLLER_1_state_o_2 => SEQ_CONTROLLER_1_state_o(2), 
        FOC_TRANSFORMS_0_vbeta_o(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), 
        FOC_TRANSFORMS_0_vbeta_o(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), 
        FOC_TRANSFORMS_0_vbeta_o(15) => 
        FOC_TRANSFORMS_0_vbeta_o(15), 
        FOC_TRANSFORMS_0_vbeta_o(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), 
        FOC_TRANSFORMS_0_vbeta_o(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), 
        FOC_TRANSFORMS_0_vbeta_o(12) => 
        FOC_TRANSFORMS_0_vbeta_o(12), 
        FOC_TRANSFORMS_0_vbeta_o(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), 
        FOC_TRANSFORMS_0_vbeta_o(10) => 
        FOC_TRANSFORMS_0_vbeta_o(10), FOC_TRANSFORMS_0_vbeta_o(9)
         => FOC_TRANSFORMS_0_vbeta_o(9), 
        FOC_TRANSFORMS_0_vbeta_o(8) => 
        FOC_TRANSFORMS_0_vbeta_o(8), FOC_TRANSFORMS_0_vbeta_o(7)
         => FOC_TRANSFORMS_0_vbeta_o(7), 
        FOC_TRANSFORMS_0_vbeta_o(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), FOC_TRANSFORMS_0_vbeta_o(5)
         => FOC_TRANSFORMS_0_vbeta_o(5), 
        FOC_TRANSFORMS_0_vbeta_o(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), FOC_TRANSFORMS_0_vbeta_o(3)
         => FOC_TRANSFORMS_0_vbeta_o(3), 
        FOC_TRANSFORMS_0_vbeta_o(2) => 
        FOC_TRANSFORMS_0_vbeta_o(2), FOC_TRANSFORMS_0_vbeta_o(1)
         => FOC_TRANSFORMS_0_vbeta_o(1), 
        FOC_TRANSFORMS_0_vbeta_o(0) => 
        FOC_TRANSFORMS_0_vbeta_o(0), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(17) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(17), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(16) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(16), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(15) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(15), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(14) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(14), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(13) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(13), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(12) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(12), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(11) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(11), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(10) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(10), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(9) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(9), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(8) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(8), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(7) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(7), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(6) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(6), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(5) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(5), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(4) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(4), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(3) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(3), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(2) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(2), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(1) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(1), 
        BLDC_ESTIMATOR_1_pll_pi_out_o(0) => 
        BLDC_ESTIMATOR_1_pll_pi_out_o(0), 
        FOC_TRANSFORMS_0_ibeta_o(17) => 
        FOC_TRANSFORMS_0_ibeta_o(17), 
        FOC_TRANSFORMS_0_ibeta_o(16) => 
        FOC_TRANSFORMS_0_ibeta_o(16), 
        FOC_TRANSFORMS_0_ibeta_o(15) => 
        FOC_TRANSFORMS_0_ibeta_o(15), 
        FOC_TRANSFORMS_0_ibeta_o(14) => 
        FOC_TRANSFORMS_0_ibeta_o(14), 
        FOC_TRANSFORMS_0_ibeta_o(13) => 
        FOC_TRANSFORMS_0_ibeta_o(13), 
        FOC_TRANSFORMS_0_ibeta_o(12) => 
        FOC_TRANSFORMS_0_ibeta_o(12), 
        FOC_TRANSFORMS_0_ibeta_o(11) => 
        FOC_TRANSFORMS_0_ibeta_o(11), 
        FOC_TRANSFORMS_0_ibeta_o(10) => 
        FOC_TRANSFORMS_0_ibeta_o(10), FOC_TRANSFORMS_0_ibeta_o(9)
         => FOC_TRANSFORMS_0_ibeta_o(9), 
        FOC_TRANSFORMS_0_ibeta_o(8) => 
        FOC_TRANSFORMS_0_ibeta_o(8), FOC_TRANSFORMS_0_ibeta_o(7)
         => FOC_TRANSFORMS_0_ibeta_o(7), 
        FOC_TRANSFORMS_0_ibeta_o(6) => 
        FOC_TRANSFORMS_0_ibeta_o(6), FOC_TRANSFORMS_0_ibeta_o(5)
         => FOC_TRANSFORMS_0_ibeta_o(5), 
        FOC_TRANSFORMS_0_ibeta_o(4) => 
        FOC_TRANSFORMS_0_ibeta_o(4), FOC_TRANSFORMS_0_ibeta_o(3)
         => FOC_TRANSFORMS_0_ibeta_o(3), 
        FOC_TRANSFORMS_0_ibeta_o(2) => 
        FOC_TRANSFORMS_0_ibeta_o(2), FOC_TRANSFORMS_0_ibeta_o(1)
         => FOC_TRANSFORMS_0_ibeta_o(1), 
        FOC_TRANSFORMS_0_ibeta_o(0) => 
        FOC_TRANSFORMS_0_ibeta_o(0), 
        FOC_TRANSFORMS_0_ialpha_o(17) => 
        FOC_TRANSFORMS_0_ialpha_o(17), 
        FOC_TRANSFORMS_0_ialpha_o(16) => 
        FOC_TRANSFORMS_0_ialpha_o(16), 
        FOC_TRANSFORMS_0_ialpha_o(15) => 
        FOC_TRANSFORMS_0_ialpha_o(15), 
        FOC_TRANSFORMS_0_ialpha_o(14) => 
        FOC_TRANSFORMS_0_ialpha_o(14), 
        FOC_TRANSFORMS_0_ialpha_o(13) => 
        FOC_TRANSFORMS_0_ialpha_o(13), 
        FOC_TRANSFORMS_0_ialpha_o(12) => 
        FOC_TRANSFORMS_0_ialpha_o(12), 
        FOC_TRANSFORMS_0_ialpha_o(11) => 
        FOC_TRANSFORMS_0_ialpha_o(11), 
        FOC_TRANSFORMS_0_ialpha_o(10) => 
        FOC_TRANSFORMS_0_ialpha_o(10), 
        FOC_TRANSFORMS_0_ialpha_o(9) => 
        FOC_TRANSFORMS_0_ialpha_o(9), 
        FOC_TRANSFORMS_0_ialpha_o(8) => 
        FOC_TRANSFORMS_0_ialpha_o(8), 
        FOC_TRANSFORMS_0_ialpha_o(7) => 
        FOC_TRANSFORMS_0_ialpha_o(7), 
        FOC_TRANSFORMS_0_ialpha_o(6) => 
        FOC_TRANSFORMS_0_ialpha_o(6), 
        FOC_TRANSFORMS_0_ialpha_o(5) => 
        FOC_TRANSFORMS_0_ialpha_o(5), 
        FOC_TRANSFORMS_0_ialpha_o(4) => 
        FOC_TRANSFORMS_0_ialpha_o(4), 
        FOC_TRANSFORMS_0_ialpha_o(3) => 
        FOC_TRANSFORMS_0_ialpha_o(3), 
        FOC_TRANSFORMS_0_ialpha_o(2) => 
        FOC_TRANSFORMS_0_ialpha_o(2), 
        FOC_TRANSFORMS_0_ialpha_o(1) => 
        FOC_TRANSFORMS_0_ialpha_o(1), 
        FOC_TRANSFORMS_0_ialpha_o(0) => 
        FOC_TRANSFORMS_0_ialpha_o(0), prdata_o_1_2_0_0_1(2) => 
        prdata_o_1_2_0_0_1(2), prdata_o_1_0_1(16) => 
        prdata_o_1_0_1(16), prdata_o_1_0_0_4 => 
        prdata_o_1_0_0(16), prdata_o_1_2_0_0_5(3) => 
        prdata_o_1_2_0_0_5(3), prdata_o_1_2_0_0_2(2) => 
        prdata_o_1_2_0_0_2(2), prdata_o_1_2_0_0_0(2) => 
        prdata_o_1_2_0_0_0(2), prdata_o_1_3_0_0_3(11) => 
        prdata_o_1_3_0_0_3(11), prdata_o_1_3_0_0_2(11) => 
        prdata_o_1_3_0_0_2(11), prdata_o_1_3_0_0_0(11) => 
        prdata_o_1_3_0_0_0(11), prdata_o_1_8_3(6) => 
        prdata_o_1_8_3(6), prdata_o_1_8_2(6) => prdata_o_1_8_2(6), 
        prdata_o_1_8_0(6) => prdata_o_1_8_0(6), 
        prdata_o_1_0_2(16) => prdata_o_1_0_2(16), 
        prdata_o_1_2_0_0_4_2(3) => prdata_o_1_2_0_0_4_2(3), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14, 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0, MC_System_0_FIC_0_LOCK
         => MC_System_0_FIC_0_LOCK, MC_System_0_FIC_0_CLK => 
        MC_System_0_FIC_0_CLK, apb3_if_0_stop_motor_o => 
        apb3_if_0_stop_motor_o, apb3_if_0_start_motor_o => 
        apb3_if_0_start_motor_o, apb3_if_0_fault_clr_o => 
        apb3_if_0_fault_clr_o, apb3_if_0_direction_config_o => 
        apb3_if_0_direction_config_o, N_2627 => N_2627, N_2574
         => N_2574, prdata_m2_e_1_1 => prdata_m2_e_1_1, N_2645
         => N_2645, N_739 => N_739, N_766 => N_766, N_768 => 
        N_768, N_769 => N_769, N_1345 => N_1345, N_767 => N_767, 
        N_875 => N_875, N_770 => N_770, N_771 => N_771, N_772 => 
        N_772, N_876 => N_876, N_773 => N_773, N_1333 => N_1333, 
        N_1347 => N_1347, N_1351 => N_1351, N_1326 => N_1326, 
        N_1346 => N_1346, N_878 => N_878, N_789 => N_789, N_791
         => N_791, N_1329 => N_1329, N_1342 => N_1342, N_790 => 
        N_790, N_891 => N_891, N_1360 => N_1360, N_1378 => N_1378, 
        N_1396 => N_1396, N_774 => N_774, N_775 => N_775, N_776
         => N_776, N_777 => N_777, N_792 => N_792, N_793 => N_793, 
        N_832 => N_832, N_880 => N_880, N_882 => N_882, N_883 => 
        N_883, N_892 => N_892, N_893 => N_893, N_894 => N_894, 
        N_895 => N_895, N_738 => N_738, N_502 => N_502, N_240 => 
        N_240, N_549 => N_549, N_870 => N_870, N_859 => N_859, 
        N_788 => N_788, N_782 => N_782, N_763 => N_763, N_762 => 
        N_762, N_750 => N_750, N_749 => N_749, N_1288 => N_1288, 
        N_1279 => N_1279, N_1275 => N_1275, N_1169 => N_1169, 
        N_1165 => N_1165, MC_System_0_AMBA_SLAVE_1_PWRITE => 
        MC_System_0_AMBA_SLAVE_1_PWRITE, 
        MC_System_0_AMBA_SLAVE_1_PENABLE => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, prdata_m1_e_0_1 => 
        prdata_m1_e_0_1, N_2631 => N_2631, N_1398 => N_1398, 
        N_519 => N_519, N_540 => N_540, N_2644 => N_2644, N_2639
         => N_2639, N_2647 => N_2647, N_2640 => N_2640, N_2598
         => N_2598, N_2646 => N_2646, N_2652 => N_2652, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, N_2495 => N_2495, N_2498
         => N_2498, N_2531 => N_2531, N_542 => N_542, N_544 => 
        N_544);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity apb3_if_st is

    port( apb3_if_st_0_adc_oc_thresh_o           : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_adc_scale_val_o           : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_id_ref_val_o              : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_idq_pi_ki_o               : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_idq_pi_kp_o               : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_pwm_dead_time_val_o       : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_pwm_delay_time_val_o      : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_pwm_period_val_o          : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_sqmng_dv_o                : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_theta_gen_rate_limit_o    : out   std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_1_PWDATA        : in    std_logic_vector(23 downto 0);
          apb3_if_st_0_theta_gen_slew_count_o    : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_theta_gen_cmd_step_no_o_0 : out   std_logic_vector(23 downto 0);
          apb3_if_st_0_adc_control_reg_val_o     : out   std_logic_vector(5 downto 0);
          apb3_if_st_0_seq_cntl_config_o         : out   std_logic_vector(2 downto 1);
          apb3_if_st_0_adc_channel_ch0_o         : out   std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch1_o         : out   std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch2_o         : out   std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch3_o         : out   std_logic_vector(15 downto 0);
          prdata_o_1_0_iv_0_12_4                 : out   std_logic_vector(8 to 8);
          prdata_o_1_2_0_a2_17_0                 : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI      : out   std_logic_vector(0 to 0);
          prdata_o_1_iv_0_0_a2_45_0              : out   std_logic_vector(0 to 0);
          prdata_o_1_0_iv_0_1_0                  : out   std_logic;
          prdata_o_1_iv_0_0_4_2_1_0              : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_4_2               : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_5_0               : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_a2_26_0              : out   std_logic_vector(1 to 1);
          MC_System_0_AMBA_SLAVE_1_PADDR         : in    std_logic_vector(11 downto 0);
          prdata_o_1_iv_0_0_a2_24_0              : out   std_logic_vector(1 to 1);
          FOC_TRANSFORMS_0_vbeta_o_16            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_15            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_10            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_12            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_5             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_0             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_13            : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_8             : in    std_logic;
          FOC_TRANSFORMS_0_vbeta_o_3             : in    std_logic;
          prdata_o_1_0_iv_0_a2_6_2_2             : out   std_logic;
          prdata_o_1_0_iv_0_a2_6_2_5             : out   std_logic;
          prdata_o_1_0_iv_0_a2_6_2_7             : out   std_logic;
          prdata_o_1_0_iv_0_a2_20_0              : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_a2_19_0              : out   std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_a2_14_1              : out   std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_0_0_0                : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_0_0_7                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_1                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_5                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_4                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_0_d0             : out   std_logic;
          prdata_o_1_0_iv_0_0_0_2                : out   std_logic;
          prdata_o_1_0_iv_0_1_1                  : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_12_1                 : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_0_2_tz_tz            : out   std_logic_vector(0 to 0);
          prdata_o_1_0_iv_0_3_0                  : out   std_logic;
          prdata_o_1_0_iv_0_3_3                  : out   std_logic;
          adc_measurements_0_adc_result_ch3_o_2  : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_11 : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_5  : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_9  : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_8  : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_4  : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_10 : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_6  : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_0  : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_7  : in    std_logic;
          adc_measurements_0_adc_result_ch3_o_3  : in    std_logic;
          SEQ_CONTROLLER_1_state_o_0_3           : in    std_logic;
          SEQ_CONTROLLER_1_state_o_0_0           : in    std_logic;
          SEQ_CONTROLLER_1_state_o_0_2           : in    std_logic;
          SPEED_ID_IQ_PI_1_id_pi_output_o        : in    std_logic_vector(17 downto 2);
          SPEED_ID_IQ_PI_1_iq_pi_output_o        : in    std_logic_vector(17 downto 2);
          prdata_o_1_0_iv_0_1_6_tz               : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_2_tz_0               : out   std_logic;
          prdata_o_1_0_iv_0_2_tz_4               : out   std_logic;
          prdata_o_1_0_iv_0_2_tz_1               : out   std_logic;
          prdata_o_1_iv_0_0_0_3_tz               : out   std_logic_vector(1 to 1);
          STEPPER_THETA_0_theta_output_o         : in    std_logic_vector(17 downto 0);
          FOC_TRANSFORMS_1_valpha_o_16           : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_0            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_2            : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_11           : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_14           : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_15           : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_13           : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_12           : in    std_logic;
          FOC_TRANSFORMS_1_valpha_o_1            : in    std_logic;
          prdata_o_1_0_iv_0_1_o2_0               : out   std_logic_vector(17 to 17);
          adc_interface_0_result_ch2_o           : in    std_logic_vector(11 downto 0);
          prdata_o_1_0_iv_0_0_0_d0               : out   std_logic;
          adc_interface_0_result_ch0_o_3         : in    std_logic;
          adc_interface_0_result_ch0_o_1         : in    std_logic;
          adc_interface_0_result_ch0_o_9         : in    std_logic;
          adc_interface_0_result_ch0_o_2         : in    std_logic;
          adc_interface_0_result_ch0_o_0         : in    std_logic;
          STEPPER_THETA_1_step_count_o_7         : in    std_logic;
          STEPPER_THETA_1_step_count_o_0         : in    std_logic;
          STEPPER_THETA_1_step_count_o_4         : in    std_logic;
          STEPPER_THETA_1_step_count_o_2         : in    std_logic;
          STEPPER_THETA_1_step_count_o_10        : in    std_logic;
          STEPPER_THETA_1_step_count_o_8         : in    std_logic;
          STEPPER_THETA_1_step_count_o_5         : in    std_logic;
          STEPPER_THETA_1_step_count_o_3         : in    std_logic;
          STEPPER_THETA_1_step_count_o_1         : in    std_logic;
          STEPPER_THETA_1_step_count_o_13        : in    std_logic;
          STEPPER_THETA_1_step_count_o_16        : in    std_logic;
          STEPPER_THETA_1_step_count_o_14        : in    std_logic;
          STEPPER_THETA_1_step_count_o_17        : in    std_logic;
          STEPPER_THETA_1_step_count_o_22        : in    std_logic;
          STEPPER_THETA_1_step_count_o_21        : in    std_logic;
          STEPPER_THETA_1_step_count_o_20        : in    std_logic;
          STEPPER_THETA_1_step_count_o_19        : in    std_logic;
          STEPPER_THETA_1_step_count_o_18        : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_2  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_1  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_0  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_9  : in    std_logic;
          adc_measurements_0_adc_result_ch1_o_4  : in    std_logic;
          prdata_o_1_iv_0_0_11                   : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_5_5                  : out   std_logic;
          prdata_o_1_0_iv_0_5_7                  : out   std_logic;
          prdata_o_1_0_iv_0_5_2                  : out   std_logic;
          prdata_o_1_0_iv_0_5_0                  : out   std_logic;
          prdata_o_1_0_iv_0_5_4                  : out   std_logic;
          prdata_o_1_0_iv_0_5_1                  : out   std_logic;
          prdata_o_1_0_iv_0_5_12                 : out   std_logic;
          ADC_SCALING_0_ib_adc_o_13              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_17              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_2               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_10              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_7               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_3               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_0               : in    std_logic;
          ADC_SCALING_0_ib_adc_o_16              : in    std_logic;
          ADC_SCALING_0_ib_adc_o_14              : in    std_logic;
          prdata_o_1_iv_0_0_12_4_3               : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_6_3                  : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_13               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_5                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_0                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_9                : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_12               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_10               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_16               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_2                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_0                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_10               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_3                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_5                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_15               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_13               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_1                : in    std_logic;
          FOC_TRANSFORMS_0_id_o_12               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_0               : in    std_logic;
          ADC_SCALING_0_ia_adc_o_10              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_14              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_13              : in    std_logic;
          ADC_SCALING_0_ia_adc_o_11              : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PRDATA        : out   std_logic_vector(14 downto 13);
          MC_System_0_FIC_0_LOCK                 : in    std_logic;
          MC_System_0_FAB_CCC_GL1                : in    std_logic;
          apb3_if_st_0_theta_gen_mode_o          : out   std_logic;
          apb3_if_st_0_stop_motor_o              : out   std_logic;
          apb3_if_st_0_start_motor_o             : out   std_logic;
          N_503                                  : out   std_logic;
          N_500                                  : out   std_logic;
          N_505                                  : out   std_logic;
          N_240                                  : in    std_logic;
          N_514                                  : out   std_logic;
          N_507                                  : out   std_logic;
          N_509                                  : out   std_logic;
          N_506                                  : out   std_logic;
          N_522                                  : out   std_logic;
          N_542                                  : out   std_logic;
          N_516                                  : out   std_logic;
          N_502                                  : in    std_logic;
          prdata_m2_e_0                          : out   std_logic;
          N_519                                  : out   std_logic;
          N_540                                  : out   std_logic;
          N_544                                  : out   std_logic;
          N_517                                  : out   std_logic;
          N_128                                  : out   std_logic;
          m20_m2_0_a2_1                          : out   std_logic;
          prdata_m1_e_11_0                       : out   std_logic;
          prdata_m1_0_a2_2_0                     : out   std_logic;
          N_513                                  : out   std_logic;
          prdata_m3_i_0                          : out   std_logic;
          prdata_m2_0_a2_0                       : out   std_logic;
          prdata_m2_e_0_0                        : out   std_logic;
          m20_i_a2_5_0                           : out   std_logic;
          prdata_m1_0_a2_0                       : out   std_logic;
          m20_i_a2_0_1                           : out   std_logic;
          prdata_m4_e_0                          : out   std_logic;
          N_518                                  : out   std_logic;
          N_533                                  : out   std_logic;
          N_397                                  : out   std_logic;
          N_355                                  : out   std_logic;
          N_531                                  : out   std_logic;
          N_527                                  : out   std_logic;
          N_529                                  : out   std_logic;
          N_508                                  : out   std_logic;
          m20_i_2_tz                             : out   std_logic;
          N_494                                  : out   std_logic;
          N_454                                  : out   std_logic;
          N_414                                  : out   std_logic;
          N_198                                  : out   std_logic;
          m20_i_11_5                             : out   std_logic;
          prdata_N_7_2                           : out   std_logic;
          N_349                                  : out   std_logic;
          N_534                                  : out   std_logic;
          N_260                                  : out   std_logic;
          N_363                                  : out   std_logic;
          N_377                                  : out   std_logic;
          N_405                                  : out   std_logic;
          N_455                                  : out   std_logic;
          N_495                                  : out   std_logic;
          N_524                                  : out   std_logic;
          N_528                                  : out   std_logic;
          m20_i_10_1                             : out   std_logic;
          m20_i_10_0                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE        : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx         : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PENABLE       : in    std_logic;
          N_215                                  : out   std_logic;
          N_315                                  : out   std_logic;
          N_317                                  : out   std_logic;
          N_318                                  : out   std_logic;
          N_319                                  : out   std_logic;
          N_320                                  : out   std_logic;
          N_321                                  : out   std_logic;
          N_354                                  : out   std_logic;
          N_396                                  : out   std_logic;
          N_122                                  : out   std_logic;
          N_549                                  : in    std_logic
        );

end apb3_if_st;

architecture DEF_ARCH of apb3_if_st is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \prdata_o_1_0_iv_0_12_4\ : std_logic_vector(8 to 8);
    signal \prdata_o_1_iv_0_0_a2_45_0\ : 
        std_logic_vector(0 to 0);
    signal \prdata_o_1_iv_0_0_4_2_1_0\ : 
        std_logic_vector(3 to 3);
    signal \prdata_o_1_iv_0_0_a2_26_0\ : 
        std_logic_vector(1 to 1);
    signal \prdata_o_1_iv_0_0_a2_24_0\ : 
        std_logic_vector(1 to 1);
    signal \prdata_o_1_0_iv_0_1_o2_0\ : 
        std_logic_vector(17 to 17);
    signal \N_503\, \N_500\, \N_505\, \N_514\, \N_507\, \N_509\, 
        \N_506\, \N_522\, \N_542\, \N_516\, \prdata_m2_e_0\, 
        \N_519\, \N_540\, \N_544\, \N_517\, \prdata_m1_e_11_0\, 
        \prdata_m1_0_a2_2_0\, \N_513\, \N_518\, \N_531\, \N_527\, 
        \N_529\, \N_508\, \prdata_N_7_2\, \N_524\, \N_528\
         : std_logic;
    signal prdata_o_1_iv_0_0_a2_49_1 : std_logic_vector(0 to 0);
    signal prdata_o_1_0_iv_0_12_4_sx : std_logic_vector(4 to 4);
    signal prdata_o_1_0_iv_0_1_sx : std_logic_vector(7 to 7);
    signal prdata_o_1_iv_0_0_4_2_1_1 : std_logic_vector(3 to 3);
    signal prdata_o_1_iv_0_0_12_5_0_1 : std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_2_1_1 : std_logic_vector(13 to 13);
    signal prdata_o_1_0_iv_0_2_1 : std_logic_vector(13 to 13);
    signal prdata_o_1_0_iv_0_2 : std_logic_vector(16 downto 13);
    signal prdata_o_1_0_iv_0_m2_i_m3_1_1 : 
        std_logic_vector(18 to 18);
    signal prdata_o_1_0_iv_0_8_0 : 
        std_logic_vector(16 downto 12);
    signal prdata_o_1_0_iv_0_12_0 : 
        std_logic_vector(11 downto 4);
    signal prdata_o_1_iv_0_0_a2_24_1 : std_logic_vector(1 to 1);
    signal prdata_o_1_0_iv_0_a2_2_0 : std_logic_vector(17 to 17);
    signal prdata_o_1_0_iv_0_a2_6_2 : std_logic_vector(4 to 4);
    signal prdata_o_1_iv_0_0_8_tz : std_logic_vector(3 to 3);
    signal prdata_o_1_iv_0_0_2_tz : std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_0_tz : 
        std_logic_vector(16 downto 13);
    signal prdata_o_1_0_iv_0_1 : std_logic_vector(16 downto 13);
    signal prdata_o_1_0_iv_0_5 : std_logic_vector(14 downto 13);
    signal prdata_o_1_0_iv_0_6_a2 : std_logic_vector(14 to 14);
    signal prdata_o_1_0_iv_0_0 : std_logic_vector(14 to 14);
    signal prdata_o_1_0_iv_0_4 : std_logic_vector(14 to 14);
    signal prdata_o_1_0_iv_0_6 : std_logic_vector(13 to 13);
    signal \VCC\, adc_oc_thresh_o_1_sqmuxa, \GND\, 
        adc_scale_val_o_1_sqmuxa, id_ref_val_o_1_sqmuxa, 
        idq_pi_ki_o_1_sqmuxa, idq_pi_kp_o_0_sqmuxa, 
        pwm_dead_time_val_o_1_sqmuxa, 
        pwm_delay_time_val_o_1_sqmuxa, pwm_period_val_o_1_sqmuxa, 
        sqmng_dv_o_1_sqmuxa, theta_gen_rate_limit_o_1_sqmuxa, 
        theta_gen_slew_count_o_1_sqmuxa, 
        theta_gen_cmd_step_no_o_1_sqmuxa, 
        adc_channel_ch0_o_1_sqmuxa, 
        adc_control_reg_val_o_1_sqmuxa, 
        seq_cntl_config_o_1_sqmuxa, adc_channel_ch1_o_1_sqmuxa, 
        adc_channel_ch2_o_1_sqmuxa, adc_channel_ch3_o_1_sqmuxa, 
        theta_gen_mode_o_1_sqmuxa, stop_motor_o_1_sqmuxa, 
        start_motor_o_1_sqmuxa, prdata_N_7_5, 
        prdata_o_1_iv_0_0_12_4_2_N_3L4_Z, 
        prdata_o_1_iv_0_0_4_2_N_5L8_1_0, N_130, 
        prdata_m2_0_a2_11_0, prdata_m2_0_a2_13_0_Z, 
        prdata_m2_0_a2_9_0, prdata_m2_0_a2_15_0_Z, N_550, N_510, 
        prdata_N_7_4, prdata_N_8_3, N_123, m20_i_11_0_Z, 
        prdata_m2_0_a2_17_1, prdata_m2_0_a2_19_0_Z, 
        prdata_m5_e_0_4_1_Z, prdata_m5_e_3, prdata_m5_e_0_3, 
        N_521, prdata_m4_0, m20_i_a2_7_0_Z, prdata_m2_0_a2_9_2_Z, 
        prdata_m2_0_a2_17_2, 
        id_ref_val_o_1_sqmuxa_0_a2_6_a2_2_2_Z, 
        prdata_o_1_0_iv_0_a2_3_out_1, prdata_o_1_0_iv_0_a2_out_5, 
        prdata_m4_0_1, prdata_m4_1, prdata_N_8_4, N_480, N_278, 
        N_268, N_554, N_487, prdata_N_7_6, 
        idq_pi_kp_o_0_sqmuxa_0_a2_0_a2_4_0_Z, N_525, 
        idq_pi_ki_o_1_sqmuxa_4, N_547, N_571, N_538, N_11, N_10
         : std_logic;

begin 

    prdata_o_1_0_iv_0_12_4(8) <= \prdata_o_1_0_iv_0_12_4\(8);
    prdata_o_1_iv_0_0_a2_45_0(0) <= 
        \prdata_o_1_iv_0_0_a2_45_0\(0);
    prdata_o_1_iv_0_0_4_2_1_0(3) <= 
        \prdata_o_1_iv_0_0_4_2_1_0\(3);
    prdata_o_1_iv_0_0_a2_26_0(1) <= 
        \prdata_o_1_iv_0_0_a2_26_0\(1);
    prdata_o_1_iv_0_0_a2_24_0(1) <= 
        \prdata_o_1_iv_0_0_a2_24_0\(1);
    prdata_o_1_0_iv_0_1_o2_0(17) <= 
        \prdata_o_1_0_iv_0_1_o2_0\(17);
    N_503 <= \N_503\;
    N_500 <= \N_500\;
    N_505 <= \N_505\;
    N_514 <= \N_514\;
    N_507 <= \N_507\;
    N_509 <= \N_509\;
    N_506 <= \N_506\;
    N_522 <= \N_522\;
    N_542 <= \N_542\;
    N_516 <= \N_516\;
    prdata_m2_e_0 <= \prdata_m2_e_0\;
    N_519 <= \N_519\;
    N_540 <= \N_540\;
    N_544 <= \N_544\;
    N_517 <= \N_517\;
    prdata_m1_e_11_0 <= \prdata_m1_e_11_0\;
    prdata_m1_0_a2_2_0 <= \prdata_m1_0_a2_2_0\;
    N_513 <= \N_513\;
    N_518 <= \N_518\;
    N_531 <= \N_531\;
    N_527 <= \N_527\;
    N_529 <= \N_529\;
    N_508 <= \N_508\;
    prdata_N_7_2 <= \prdata_N_7_2\;
    N_524 <= \N_524\;
    N_528 <= \N_528\;

    \idq_pi_kp_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(11));
    
    prdata_m3_i_m3_0 : CFG3
      generic map(INIT => x"AC")

      port map(A => ADC_SCALING_0_ib_adc_o_17, B => 
        ADC_SCALING_0_ia_adc_o_14, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => prdata_N_8_3);
    
    \pwm_dead_time_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(6));
    
    \adc_channel_ch1_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(3));
    
    \adc_scale_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(12));
    
    \theta_gen_rate_limit_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(14));
    
    \prdata_o_1_0_iv_0_a2_4[15]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \N_529\, B => FOC_TRANSFORMS_1_valpha_o_14, Y
         => N_495);
    
    \idq_pi_ki_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(8));
    
    \theta_gen_cmd_step_no_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(9));
    
    \pwm_delay_time_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(0));
    
    \pwm_dead_time_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(8));
    
    \prdata_o_1_0_iv_0_2_tz[4]\ : CFG4
      generic map(INIT => x"F4F0")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        STEPPER_THETA_1_step_count_o_4, C => 
        prdata_o_1_0_iv_0_a2_6_2(4), D => \N_507\, Y => 
        prdata_o_1_0_iv_0_2_tz_0);
    
    \idq_pi_kp_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(6));
    
    \prdata_o_1_0_iv_0[14]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => ADC_SCALING_0_ia_adc_o_11, B => \N_524\, C
         => prdata_o_1_0_iv_0_4(14), D => prdata_o_1_0_iv_0_5(14), 
        Y => MC_System_0_AMBA_SLAVE_1_PRDATA(14));
    
    prdata_m2_0_a2_0_0 : CFG4
      generic map(INIT => x"C480")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        \prdata_m2_e_0\, C => FOC_TRANSFORMS_0_vbeta_o_8, D => 
        FOC_TRANSFORMS_0_iq_o_5, Y => prdata_m2_0_a2_0);
    
    \theta_gen_rate_limit_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(11));
    
    id_ref_val_o_1_sqmuxa_0_a2_6_a2_1 : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => \N_540\);
    
    m20_i_11_0 : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(2), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(2), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => m20_i_11_0_Z);
    
    \adc_oc_thresh_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(17));
    
    \adc_channel_ch0_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(12));
    
    prdata_m1_e_11_0_c : CFG3
      generic map(INIT => x"40")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        \prdata_m1_e_11_0\);
    
    \pwm_dead_time_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(16));
    
    \prdata_o_1_0_iv_0_0_0[4]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch2_o(4), B => 
        adc_measurements_0_adc_result_ch3_o_4, C => \N_507\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_0_0_d0);
    
    \theta_gen_slew_count_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(5));
    
    \theta_gen_rate_limit_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(1));
    
    \prdata_o_1_iv_0_0_a2_26_0_RNI6AIO1[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_26_0\(1), B => \N_503\, 
        C => m20_i_11_0_Z, D => \N_516\, Y => m20_i_11_5);
    
    \adc_oc_thresh_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(9));
    
    \adc_channel_ch1_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(8));
    
    \id_ref_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(0));
    
    \pwm_period_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(4));
    
    \prdata_o_1_0_iv_0_1_sx_RNO[7]\ : CFG3
      generic map(INIT => x"CA")

      port map(A => STEPPER_THETA_1_step_count_o_7, B => 
        STEPPER_THETA_0_theta_output_o(7), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => prdata_N_7_5);
    
    \prdata_o_1_iv_0_0_a2_49_0_RNIGNRI_cZ[0]\ : CFG3
      generic map(INIT => x"08")

      port map(A => prdata_o_1_2_0_a2_17_0(1), B => \N_500\, C
         => MC_System_0_AMBA_SLAVE_1_PADDR(6), Y => 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0));
    
    \pwm_period_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(9));
    
    \adc_oc_thresh_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(5));
    
    \adc_scale_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(11));
    
    \theta_gen_cmd_step_no_o[21]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(21), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(21));
    
    \prdata_o_1_iv_0_0_a2_24_RNI6D8H3[1]\ : CFG4
      generic map(INIT => x"CC80")

      port map(A => \prdata_m1_0_a2_2_0\, B => \N_508\, C => 
        adc_measurements_0_adc_result_ch1_o_0, D => 
        m20_i_a2_7_0_Z, Y => m20_i_10_0);
    
    \id_ref_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(2));
    
    \pwm_delay_time_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(1));
    
    \prdata_o_1_0_iv_0_12_0[8]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(8), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_12_0(8));
    
    \adc_scale_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(10));
    
    \prdata_o_1_iv_0_m2_i_m2_i_m3[1]\ : CFG3
      generic map(INIT => x"CA")

      port map(A => FOC_TRANSFORMS_1_valpha_o_0, B => 
        FOC_TRANSFORMS_0_vbeta_o_0, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => N_128);
    
    prdata_m2_0_a2_15_0 : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        FOC_TRANSFORMS_0_vbeta_o_5, Y => prdata_m2_0_a2_15_0_Z);
    
    \id_ref_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(14));
    
    \theta_gen_slew_count_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(1));
    
    \prdata_o_1_0_iv_0_8_0[12]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(12), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(12), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_8_0(12));
    
    \id_ref_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(5));
    
    \pwm_delay_time_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(4));
    
    \prdata_o_1_0_iv_0_8[12]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_26_0\(1), B => \N_503\, 
        C => prdata_o_1_0_iv_0_8_0(12), D => \N_516\, Y => 
        prdata_o_1_0_iv_0_3_0);
    
    \theta_gen_cmd_step_no_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(6));
    
    \idq_pi_kp_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(0));
    
    \adc_channel_ch1_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(15));
    
    \theta_gen_rate_limit_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(13));
    
    \adc_channel_ch3_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(13));
    
    \adc_channel_ch0_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(8));
    
    \theta_gen_cmd_step_no_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(12));
    
    \prdata_o_1_0_iv_0_2_1[13]\ : CFG3
      generic map(INIT => x"02")

      port map(A => N_240, B => MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        C => prdata_o_1_0_iv_0_2_1_1(13), Y => 
        prdata_o_1_0_iv_0_2_1(13));
    
    \prdata_o_1_iv_0_0_a2_45_0_cZ[0]\ : CFG3
      generic map(INIT => x"40")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), Y => 
        \prdata_o_1_iv_0_0_a2_45_0\(0));
    
    \prdata_o_1_0_iv_0_4[16]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => ADC_SCALING_0_ib_adc_o_16, B => 
        ADC_SCALING_0_ia_adc_o_13, C => \N_528\, D => \N_524\, Y
         => prdata_o_1_0_iv_0_5_12);
    
    \prdata_o_1_iv_0_0_a2[3]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => adc_measurements_0_adc_result_ch3_o_3, B => 
        N_521, C => \N_513\, D => \N_503\, Y => N_268);
    
    \adc_scale_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(0));
    
    \adc_channel_ch3_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(10));
    
    \pwm_dead_time_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(15));
    
    \pwm_dead_time_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(11));
    
    idq_pi_kp_o_0_sqmuxa_0_a2_0_a2_4_0 : CFG4
      generic map(INIT => x"0080")

      port map(A => MC_System_0_AMBA_SLAVE_1_PWRITE, B => 
        MC_System_0_AMBA_SLAVE_1_PSELx, C => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), Y => 
        idq_pi_kp_o_0_sqmuxa_0_a2_0_a2_4_0_Z);
    
    \pwm_delay_time_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(14));
    
    pwm_dead_time_val_o_1_sqmuxa_0_a2_0_a2_0 : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => N_510);
    
    \prdata_o_1_0_iv_0_RNO_0[16]\ : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        FOC_TRANSFORMS_0_vbeta_o_15, Y => prdata_m2_0_a2_11_0);
    
    \prdata_o_1_0_iv_0_1_RNO[13]\ : CFG2
      generic map(INIT => x"8")

      port map(A => N_502, B => prdata_m4_0, Y => prdata_m4_1);
    
    \theta_gen_cmd_step_no_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(2));
    
    id_ref_val_o_1_sqmuxa_0_a2_6_a2_2_2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_240, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        id_ref_val_o_1_sqmuxa_0_a2_6_a2_2_2_Z);
    
    id_ref_val_o_1_sqmuxa_0_a2_6_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_547, B => \N_540\, C => \N_505\, Y => 
        id_ref_val_o_1_sqmuxa);
    
    \adc_channel_ch3_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(6));
    
    \prdata_o_1_0_iv_0_RNO_0[13]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_24_0\(1), B => N_502, C
         => prdata_m2_0_a2_9_0, D => \N_517\, Y => 
        prdata_m2_0_a2_9_2_Z);
    
    \prdata_o_1_0_iv_0_0_0[9]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch2_o(9), B => 
        adc_measurements_0_adc_result_ch3_o_9, C => \N_507\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_0_5);
    
    \prdata_o_1_0_iv_0_0_0[11]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch2_o(11), B => 
        adc_measurements_0_adc_result_ch3_o_11, C => \N_507\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_0_7);
    
    \adc_channel_ch0_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(3));
    
    prdata_o_1_iv_0_0_12_4_2_N_4L6 : CFG2
      generic map(INIT => x"7")

      port map(A => \N_509\, B => ADC_SCALING_0_ia_adc_o_0, Y => 
        prdata_o_1_iv_0_0_4_2_N_5L8_1_0);
    
    \theta_gen_cmd_step_no_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(5));
    
    \prdata_o_1_0_iv_0_RNO_2[13]\ : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        FOC_TRANSFORMS_0_vbeta_o_12, Y => prdata_m2_0_a2_9_0);
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_3_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_550, B => N_538, C => \N_517\, Y => 
        adc_channel_ch1_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_o2_0_RNO_0[17]\ : CFG4
      generic map(INIT => x"05F3")

      port map(A => FOC_TRANSFORMS_0_iq_o_13, B => 
        FOC_TRANSFORMS_0_id_o_16, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_m2_i_m3_1_1(18));
    
    \prdata_o_1_0_iv_0_12[4]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_240, B => prdata_o_1_0_iv_0_12_0(4), C => 
        \prdata_o_1_0_iv_0_12_4\(8), D => \N_516\, Y => 
        prdata_o_1_0_iv_0_5_0);
    
    theta_gen_mode_o_1_sqmuxa_0_a2_2_a2_2_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_547, B => \N_544\, C => \N_517\, Y => 
        theta_gen_mode_o_1_sqmuxa);
    
    \idq_pi_kp_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(3));
    
    \idq_pi_ki_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(6));
    
    stop_motor_o_1_sqmuxa_0_a2_0_a2_0 : CFG3
      generic map(INIT => x"08")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => \N_516\);
    
    \prdata_o_1_0_iv_0_1_a2[22]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_45_0\(0), B => \N_503\, 
        C => STEPPER_THETA_1_step_count_o_22, D => \N_509\, Y => 
        N_317);
    
    \prdata_o_1_0_iv_0_a2_20_0_cZ[10]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        adc_interface_0_result_ch0_o_9, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_a2_20_0(10));
    
    \prdata_o_1_0_iv_0_2_1_1[13]\ : CFG3
      generic map(INIT => x"53")

      port map(A => ADC_SCALING_0_ib_adc_o_13, B => 
        ADC_SCALING_0_ia_adc_o_10, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_2_1_1(13));
    
    \prdata_o_1_0_iv_0_1[7]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => \N_505\, B => prdata_o_1_2_0_a2_17_0(1), C
         => \prdata_o_1_iv_0_0_a2_45_0\(0), D => 
        prdata_o_1_0_iv_0_1_sx(7), Y => prdata_o_1_0_iv_0_1_0);
    
    \prdata_o_1_0_iv_0_5[16]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => \N_514\, B => prdata_o_1_0_iv_0_0_tz(16), C
         => prdata_o_1_0_iv_0_2(16), D => prdata_o_1_0_iv_0_1(16), 
        Y => prdata_o_1_0_iv_0_6_3);
    
    \idq_pi_ki_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(3));
    
    \theta_gen_rate_limit_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(16));
    
    \idq_pi_ki_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(0));
    
    \prdata_o_1_0_iv_0_1[16]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => \N_529\, B => \N_518\, C => 
        FOC_TRANSFORMS_1_valpha_o_15, D => 
        prdata_o_1_0_iv_0_8_0(16), Y => prdata_o_1_0_iv_0_1(16));
    
    \prdata_o_1_0_iv_0_1_o2[17]\ : CFG4
      generic map(INIT => x"FDDD")

      port map(A => \prdata_N_7_2\, B => 
        \prdata_o_1_0_iv_0_1_o2_0\(17), C => 
        prdata_o_1_0_iv_0_a2_2_0(17), D => \N_514\, Y => N_122);
    
    \adc_channel_ch3_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(15));
    
    theta_gen_rate_limit_o_1_sqmuxa_0_a2_0_a2_0 : CFG4
      generic map(INIT => x"0002")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => \N_513\);
    
    \pwm_delay_time_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(7));
    
    \adc_channel_ch0_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(4));
    
    \prdata_o_1_0_iv_0_1_a2[20]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_45_0\(0), B => \N_503\, 
        C => STEPPER_THETA_1_step_count_o_20, D => \N_509\, Y => 
        N_319);
    
    \pwm_period_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(14));
    
    \prdata_o_1_0_iv_0_2[13]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_507\, B => prdata_o_1_2_0_a2_17_0(1), C
         => \prdata_o_1_iv_0_0_a2_26_0\(1), D => 
        prdata_o_1_0_iv_0_2_1(13), Y => prdata_o_1_0_iv_0_2(13));
    
    prdata_m1_0_a2_2_0_c : CFG3
      generic map(INIT => x"80")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        \prdata_m1_0_a2_2_0\);
    
    \pwm_dead_time_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(7));
    
    \prdata_o_1_iv_0_0_a2_21[1]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \N_527\, B => FOC_TRANSFORMS_0_id_o_0, Y => 
        N_260);
    
    \adc_channel_ch3_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(8));
    
    \theta_gen_rate_limit_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(15));
    
    \theta_gen_cmd_step_no_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(13));
    
    \prdata_o_1_0_iv_0_a2_6_2[6]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        STEPPER_THETA_0_theta_output_o(6), C => \N_505\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_a2_6_2_2);
    
    \adc_oc_thresh_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(12));
    
    idq_pi_ki_o_1_sqmuxa_0_a2_3_a2_3 : CFG2
      generic map(INIT => x"2")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => \N_544\);
    
    \pwm_dead_time_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(9));
    
    \pwm_dead_time_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(1));
    
    \prdata_o_1_iv_0_0_a2_24_1_RNI87P11[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a2_24_1(1), B => \N_503\, C
         => prdata_m2_0_a2_13_0_Z, D => \N_517\, Y => N_355);
    
    \prdata_o_1_0_iv_0_RNO_1[14]\ : CFG4
      generic map(INIT => x"0800")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        FOC_TRANSFORMS_0_vbeta_o_13, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_m2_0_a2_17_1);
    
    \adc_oc_thresh_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(10));
    
    adc_control_reg_val_o_1_sqmuxa_0_a2_0_a2 : CFG2
      generic map(INIT => x"8")

      port map(A => \N_509\, B => N_538, Y => 
        adc_control_reg_val_o_1_sqmuxa);
    
    \theta_gen_slew_count_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(10));
    
    \prdata_o_1_iv_0_0_a2_24_1_RNIS5ME1[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a2_24_1(1), B => \N_503\, C
         => prdata_m2_0_a2_15_0_Z, D => \N_517\, Y => N_397);
    
    \prdata_o_1_0_iv_0_12[9]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => SPEED_ID_IQ_PI_1_id_pi_output_o(9), B => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(9), C => \N_518\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_5_5);
    
    \theta_gen_slew_count_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(2));
    
    id_ref_val_o_1_sqmuxa_0_a2_6_a2_0 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => \N_505\);
    
    \adc_channel_ch1_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(12));
    
    \theta_gen_slew_count_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(3));
    
    \prdata_o_1_0_iv_0_1_o2_0_cZ[17]\ : CFG4
      generic map(INIT => x"FF40")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(5), B => N_130, 
        C => \N_508\, D => N_554, Y => 
        \prdata_o_1_0_iv_0_1_o2_0\(17));
    
    \adc_channel_ch0_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(2));
    
    \theta_gen_rate_limit_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(7));
    
    \theta_gen_rate_limit_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(12));
    
    pwm_dead_time_val_o_1_sqmuxa_0_a2_0_a2_0_RNIQOAJ1 : CFG4
      generic map(INIT => x"3F5F")

      port map(A => adc_interface_0_result_ch0_o_3, B => 
        adc_measurements_0_adc_result_ch1_o_2, C => N_510, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => prdata_m3_i_0);
    
    \adc_channel_ch0_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(6));
    
    prdata_m1_0_a2_5_1 : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), Y => prdata_m5_e_3);
    
    \prdata_o_1_iv_0_0_a2_49_1[0]\ : CFG2
      generic map(INIT => x"2")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(11), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), Y => 
        prdata_o_1_iv_0_0_a2_49_1(0));
    
    \prdata_o_1_0_iv_0_1_1_cZ[10]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => SPEED_ID_IQ_PI_1_id_pi_output_o(10), B => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(10), C => N_240, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_1_1(10));
    
    \adc_scale_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(13));
    
    \adc_oc_thresh_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(16));
    
    \prdata_o_1_0_iv_0_a2_10[11]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \N_527\, B => FOC_TRANSFORMS_0_id_o_10, Y => 
        N_363);
    
    \idq_pi_kp_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(4));
    
    \theta_gen_cmd_step_no_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(1));
    
    \prdata_o_1_0_iv_0_a2_10[4]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \N_527\, B => FOC_TRANSFORMS_0_id_o_3, Y => 
        N_377);
    
    \theta_gen_slew_count_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(11));
    
    \theta_gen_slew_count_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(0));
    
    \prdata_o_1_0_iv_0_0_RNO[14]\ : CFG4
      generic map(INIT => x"0010")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), C => prdata_N_7_4, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(10), Y => 
        prdata_m4_0_1);
    
    \theta_gen_slew_count_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(15));
    
    \adc_oc_thresh_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(8));
    
    \sqmng_dv_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(15));
    
    adc_channel_ch2_o_1_sqmuxa_0_a2_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => \N_544\, B => N_538, C => \N_517\, Y => 
        adc_channel_ch2_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_a2_3[12]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_45_0\(0), B => \N_503\, 
        C => STEPPER_THETA_0_theta_output_o(12), D => \N_513\, Y
         => N_454);
    
    \sqmng_dv_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(8));
    
    \prdata_o_1_iv_0_0_a2_45_0_RNIFGUS[0]\ : CFG4
      generic map(INIT => x"0800")

      port map(A => prdata_o_1_2_0_a2_17_0(1), B => 
        \prdata_o_1_iv_0_0_a2_45_0\(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), D => N_240, Y => 
        \N_514\);
    
    \prdata_o_1_iv_0_0_12_4_2_cZ[3]\ : CFG4
      generic map(INIT => x"ECCC")

      port map(A => \N_542\, B => prdata_o_1_iv_0_0_4_2_1_1(3), C
         => SEQ_CONTROLLER_1_state_o_0_3, D => 
        \prdata_o_1_iv_0_0_4_2_1_0\(3), Y => 
        prdata_o_1_iv_0_0_12_4_2(3));
    
    \prdata_o_1_0_iv_0_8[15]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => SPEED_ID_IQ_PI_1_id_pi_output_o(15), B => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(15), C => \N_518\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_3_3);
    
    \adc_channel_ch2_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(3));
    
    \theta_gen_slew_count_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(14));
    
    \adc_oc_thresh_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(1));
    
    \prdata_o_1_iv_0_0_a2_5[3]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_513\, B => ADC_SCALING_0_ib_adc_o_3, C => 
        \N_503\, D => \prdata_o_1_iv_0_0_a2_26_0\(1), Y => N_278);
    
    \prdata_o_1_iv_0_0_a2_24_1[1]\ : CFG4
      generic map(INIT => x"0002")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), Y => 
        prdata_o_1_iv_0_0_a2_24_1(1));
    
    prdata_o_1_iv_0_0_12_4_2_N_5L8 : CFG4
      generic map(INIT => x"7530")

      port map(A => prdata_o_1_iv_0_0_12_4_2_N_3L4_Z, B => 
        prdata_o_1_iv_0_0_4_2_N_5L8_1_0, C => \N_506\, D => 
        \N_522\, Y => prdata_o_1_iv_0_0_4_2_1_1(3));
    
    \sqmng_dv_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(1));
    
    \pwm_dead_time_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(2));
    
    \theta_gen_rate_limit_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(8));
    
    \theta_gen_cmd_step_no_o[19]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(19), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(19));
    
    \pwm_delay_time_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(3));
    
    \adc_channel_ch1_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(1));
    
    \theta_gen_cmd_step_no_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(10));
    
    \adc_control_reg_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_control_reg_val_o(3));
    
    seq_cntl_config_o_1_sqmuxa_0_a2_1_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_571, B => N_549, C => \N_517\, Y => 
        seq_cntl_config_o_1_sqmuxa);
    
    \id_ref_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(13));
    
    \adc_channel_ch2_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(11));
    
    pwm_period_val_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"0080")

      port map(A => N_549, B => N_538, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        pwm_period_val_o_1_sqmuxa);
    
    \id_ref_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(4));
    
    \adc_scale_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(8));
    
    \adc_channel_ch2_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(6));
    
    \adc_channel_ch0_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(1));
    
    \prdata_o_1_0_iv_0_12[11]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_26_0\(1), B => \N_503\, 
        C => prdata_o_1_0_iv_0_12_0(11), D => \N_516\, Y => 
        prdata_o_1_0_iv_0_5_7);
    
    \prdata_o_1_iv_0_0_RNO_0[3]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch0_o_2, B => 
        adc_measurements_0_adc_result_ch1_o_1, C => N_510, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => prdata_N_8_4);
    
    \prdata_o_1_0_iv_0_4[14]\ : CFG4
      generic map(INIT => x"FF80")

      port map(A => ADC_SCALING_0_ib_adc_o_14, B => \N_513\, C
         => \N_506\, D => prdata_o_1_0_iv_0_2(14), Y => 
        prdata_o_1_0_iv_0_5(14));
    
    \adc_oc_thresh_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(2));
    
    \pwm_dead_time_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(10));
    
    \adc_channel_ch1_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(7));
    
    \adc_channel_ch3_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(12));
    
    \pwm_period_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(13));
    
    \adc_oc_thresh_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(6));
    
    \adc_channel_ch3_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(9));
    
    \theta_gen_cmd_step_no_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(7));
    
    sqmng_dv_o_1_sqmuxa_0_a2_2_a2_4 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), Y => \N_519\);
    
    \id_ref_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(11));
    
    \adc_channel_ch1_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(9));
    
    \prdata_o_1_iv_0_0_a2_26_0_RNIE02U1[1]\ : CFG4
      generic map(INIT => x"7FFF")

      port map(A => \prdata_o_1_iv_0_0_a2_26_0\(1), B => \N_503\, 
        C => prdata_N_8_3, D => \N_507\, Y => \prdata_N_7_2\);
    
    \adc_channel_ch0_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(11));
    
    \prdata_o_1_iv_0_0_a2_26_0_cZ[1]\ : CFG3
      generic map(INIT => x"01")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), Y => 
        \prdata_o_1_iv_0_0_a2_26_0\(1));
    
    \adc_channel_ch2_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(8));
    
    theta_gen_slew_count_o_1_sqmuxa_0_a2_0_a2 : CFG2
      generic map(INIT => x"8")

      port map(A => \N_509\, B => N_547, Y => 
        theta_gen_slew_count_o_1_sqmuxa);
    
    stop_motor_o_1_sqmuxa_0_a2_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_571, B => \N_516\, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        stop_motor_o_1_sqmuxa);
    
    \adc_channel_ch3_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(4));
    
    \adc_oc_thresh_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(15));
    
    \prdata_o_1_iv_0_0_a2_20[0]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_513\, B => ADC_SCALING_0_ib_adc_o_0, C => 
        \N_503\, D => \prdata_o_1_iv_0_0_a2_26_0\(1), Y => N_198);
    
    \prdata_o_1_0_iv_0_6_a2[14]\ : CFG4
      generic map(INIT => x"F800")

      port map(A => STEPPER_THETA_1_step_count_o_14, B => \N_509\, 
        C => prdata_o_1_0_iv_0_a2_3_out_1, D => \N_514\, Y => 
        prdata_o_1_0_iv_0_6_a2(14));
    
    \theta_gen_rate_limit_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(17));
    
    \adc_scale_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(1));
    
    \prdata_o_1_0_iv_0_a2_19_0_cZ[10]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        \N_505\, C => ADC_SCALING_0_ib_adc_o_10, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => 
        prdata_o_1_0_iv_0_a2_19_0(10));
    
    id_ref_val_o_1_sqmuxa_0_a2_6_a2_0_RNILK041 : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        adc_interface_0_result_ch2_o(2), C => \N_505\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => m20_i_a2_0_1);
    
    \adc_channel_ch2_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(4));
    
    \pwm_delay_time_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(6));
    
    \id_ref_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(1));
    
    prdata_m2_0_a2_19_0 : CFG3
      generic map(INIT => x"20")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        prdata_m2_0_a2_19_0_Z);
    
    \adc_channel_ch0_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(7));
    
    GND_Z : GND
      port map(Y => \GND\);
    
    \pwm_delay_time_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(2));
    
    \prdata_o_1_iv_0_0_12_4_3_cZ[3]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => prdata_o_1_iv_0_0_2_tz(3), B => \N_514\, C
         => N_278, D => N_268, Y => prdata_o_1_iv_0_0_12_4_3(3));
    
    \pwm_dead_time_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(14));
    
    \prdata_o_1_0_iv_0_2_tz[5]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => STEPPER_THETA_1_step_count_o_5, B => 
        STEPPER_THETA_0_theta_output_o(5), C => \N_513\, D => 
        \N_509\, Y => prdata_o_1_0_iv_0_2_tz_1);
    
    \prdata_o_1_iv_0_0_a2_49_0_RNI57U01[0]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        prdata_o_1_2_0_a2_17_0(1), C => N_502, D => \N_500\, Y
         => \N_522\);
    
    \prdata_o_1_iv_0_0_12_5_0_cZ[3]\ : CFG4
      generic map(INIT => x"0008")

      port map(A => \N_516\, B => N_502, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), D => 
        prdata_o_1_iv_0_0_12_5_0_1(3), Y => 
        prdata_o_1_iv_0_0_12_5_0(3));
    
    \prdata_o_1_iv_0_0_a2_49[0]\ : CFG4
      generic map(INIT => x"0010")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), C => 
        prdata_o_1_iv_0_0_a2_49_1(0), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => \N_503\);
    
    \theta_gen_cmd_step_no_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(15));
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \prdata_o_1_0_iv_0_a2_4[12]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \N_529\, B => FOC_TRANSFORMS_1_valpha_o_11, Y
         => N_455);
    
    \theta_gen_cmd_step_no_o[22]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(22), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(22));
    
    \theta_gen_cmd_step_no_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(0));
    
    \prdata_o_1_iv_0_0_11_cZ[3]\ : CFG4
      generic map(INIT => x"5D55")

      port map(A => prdata_N_7_6, B => \N_508\, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => 
        prdata_o_1_iv_0_0_8_tz(3), Y => prdata_o_1_iv_0_0_11(3));
    
    \idq_pi_ki_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(17));
    
    \adc_scale_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(15));
    
    \adc_channel_ch2_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(14));
    
    \theta_gen_slew_count_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(8));
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_3_a2_0 : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => \N_517\);
    
    \theta_gen_slew_count_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(12));
    
    \pwm_delay_time_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(8));
    
    \theta_gen_cmd_step_no_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(14));
    
    start_motor_o_1_sqmuxa_0_a2_0_a2_1 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_525, B => N_502, C => \N_500\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), Y => N_571);
    
    \theta_gen_rate_limit_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(4));
    
    \id_ref_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(17));
    
    \adc_channel_ch0_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(0));
    
    \adc_channel_ch1_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(4));
    
    start_motor_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => start_motor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_start_motor_o);
    
    \prdata_o_1_0_iv_0_a2_6_2[4]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        STEPPER_THETA_0_theta_output_o(4), C => \N_505\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_a2_6_2(4));
    
    \id_ref_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(6));
    
    \adc_scale_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(16));
    
    \adc_oc_thresh_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(0));
    
    \pwm_period_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(6));
    
    theta_gen_mode_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => theta_gen_mode_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_mode_o);
    
    \prdata_o_1_0_iv_0_a2_2_0[17]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        STEPPER_THETA_0_theta_output_o(17), C => \N_505\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_a2_2_0(17));
    
    \prdata_o_1_0_iv_0_a2_10[6]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \N_527\, B => FOC_TRANSFORMS_0_id_o_5, Y => 
        N_405);
    
    \pwm_dead_time_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(12));
    
    id_ref_val_o_1_sqmuxa_0_a2_6_a2_2 : CFG3
      generic map(INIT => x"08")

      port map(A => id_ref_val_o_1_sqmuxa_0_a2_6_a2_2_2_Z, B => 
        N_525, C => MC_System_0_AMBA_SLAVE_1_PADDR(7), Y => N_547);
    
    \pwm_period_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(0));
    
    \prdata_o_1_0_iv_0_RNO_1[13]\ : CFG4
      generic map(INIT => x"0C0A")

      port map(A => SPEED_ID_IQ_PI_1_id_pi_output_o(13), B => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(13), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => prdata_m4_0);
    
    \adc_scale_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(4));
    
    \adc_channel_ch0_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(14));
    
    \prdata_o_1_iv_0_0_0_2_tz_tz_cZ[0]\ : CFG4
      generic map(INIT => x"0C0A")

      port map(A => STEPPER_THETA_1_step_count_o_0, B => 
        STEPPER_THETA_0_theta_output_o(0), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_iv_0_0_0_2_tz_tz(0));
    
    prdata_m2_0_a2_13_0 : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        FOC_TRANSFORMS_0_vbeta_o_10, Y => prdata_m2_0_a2_13_0_Z);
    
    \idq_pi_kp_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(17));
    
    \sqmng_dv_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(6));
    
    \idq_pi_ki_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(1));
    
    \prdata_o_1_0_iv_0_a2_1[6]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a2_24_1(1), B => \N_503\, C
         => adc_measurements_0_adc_result_ch1_o_4, D => 
        \prdata_m1_0_a2_2_0\, Y => N_396);
    
    \seq_cntl_config_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_seq_cntl_config_o(1));
    
    \prdata_o_1_0_iv_0_a2_6_2[11]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        STEPPER_THETA_0_theta_output_o(11), C => \N_505\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_a2_6_2_7);
    
    \prdata_o_1_0_iv_0_1_a2[17]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_45_0\(0), B => \N_503\, 
        C => STEPPER_THETA_1_step_count_o_17, D => \N_509\, Y => 
        N_315);
    
    sqmng_dv_o_1_sqmuxa_0_a2_2_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_544\, B => \N_542\, C => N_525, D => N_502, 
        Y => sqmng_dv_o_1_sqmuxa);
    
    \adc_channel_ch0_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(5));
    
    \pwm_period_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(15));
    
    \adc_channel_ch1_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(2));
    
    sqmng_dv_o_1_sqmuxa_0_a2_2_a2_2 : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_519\, B => MC_System_0_AMBA_SLAVE_1_PWRITE, 
        C => MC_System_0_AMBA_SLAVE_1_PSELx, D => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, Y => N_525);
    
    \idq_pi_ki_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(15));
    
    \pwm_delay_time_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(13));
    
    \seq_cntl_config_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_seq_cntl_config_o(2));
    
    \prdata_o_1_iv_0_0_12_5_0_1[3]\ : CFG3
      generic map(INIT => x"53")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(3), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(3), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_iv_0_0_12_5_0_1(3));
    
    \theta_gen_rate_limit_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(9));
    
    \pwm_delay_time_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(15));
    
    \prdata_o_1_0_iv_0_1_6_tz_cZ[10]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => STEPPER_THETA_1_step_count_o_10, B => 
        STEPPER_THETA_0_theta_output_o(10), C => \N_513\, D => 
        \N_509\, Y => prdata_o_1_0_iv_0_1_6_tz(10));
    
    \idq_pi_kp_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(8));
    
    \prdata_o_1_0_iv_0_0[7]\ : CFG4
      generic map(INIT => x"F800")

      port map(A => adc_interface_0_result_ch2_o(7), B => \N_509\, 
        C => prdata_o_1_0_iv_0_a2_out_5, D => \N_522\, Y => 
        prdata_o_1_0_iv_0_0_0_d0);
    
    \pwm_period_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(17));
    
    theta_gen_slew_count_o_1_sqmuxa_0_a2_0_a2_1_RNIGF6N1 : CFG4
      generic map(INIT => x"A0C0")

      port map(A => STEPPER_THETA_0_theta_output_o(2), B => 
        STEPPER_THETA_1_step_count_o_2, C => \N_507\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => m20_i_2_tz);
    
    \adc_channel_ch3_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(2));
    
    \prdata_o_1_0_iv_0_2[16]\ : CFG4
      generic map(INIT => x"FEFA")

      port map(A => N_480, B => FOC_TRANSFORMS_0_iq_o_12, C => 
        N_487, D => \N_531\, Y => prdata_o_1_0_iv_0_2(16));
    
    \prdata_o_1_iv_0_0_a2_26[1]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        prdata_o_1_2_0_a2_17_0(1), C => N_502, D => \N_500\, Y
         => \N_506\);
    
    \theta_gen_cmd_step_no_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(3));
    
    \prdata_o_1_0_iv_0[13]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => prdata_o_1_0_iv_0_0_tz(13), B => \N_514\, C
         => prdata_o_1_0_iv_0_6(13), D => prdata_o_1_0_iv_0_5(13), 
        Y => MC_System_0_AMBA_SLAVE_1_PRDATA(13));
    
    \adc_control_reg_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_control_reg_val_o(0));
    
    \prdata_o_1_0_iv_0_12[8]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_240, B => prdata_o_1_0_iv_0_12_0(8), C => 
        \prdata_o_1_0_iv_0_12_4\(8), D => \N_516\, Y => 
        prdata_o_1_0_iv_0_5_4);
    
    pwm_delay_time_val_o_1_sqmuxa_0_a2_5_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_549, B => N_538, C => N_510, Y => 
        pwm_delay_time_val_o_1_sqmuxa);
    
    \theta_gen_cmd_step_no_o[23]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(23), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(23));
    
    \theta_gen_slew_count_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(9));
    
    \adc_control_reg_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_control_reg_val_o(5));
    
    \prdata_o_1_iv_0_0_a2_24_0_RNID97R7[1]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => FOC_TRANSFORMS_1_valpha_o_1, B => 
        FOC_TRANSFORMS_0_id_o_1, C => \N_529\, D => \N_527\, Y
         => m20_i_10_1);
    
    \pwm_dead_time_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(5));
    
    \prdata_o_1_0_iv_0_1_a2[19]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_45_0\(0), B => \N_503\, 
        C => STEPPER_THETA_1_step_count_o_19, D => \N_509\, Y => 
        N_320);
    
    \adc_channel_ch2_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(1));
    
    \adc_channel_ch1_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(11));
    
    \theta_gen_rate_limit_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(6));
    
    \pwm_delay_time_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(10));
    
    \adc_control_reg_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_control_reg_val_o(1));
    
    \pwm_period_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(10));
    
    \idq_pi_kp_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(15));
    
    \idq_pi_ki_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(14));
    
    \id_ref_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(10));
    
    \adc_channel_ch2_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(2));
    
    \prdata_o_1_0_iv_0_a2_s[7]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        adc_measurements_0_adc_result_ch3_o_7, C => \N_505\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_a2_out_5);
    
    \prdata_o_1_0_iv_0_0_tz[16]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => STEPPER_THETA_1_step_count_o_16, B => 
        STEPPER_THETA_0_theta_output_o(16), C => \N_513\, D => 
        \N_509\, Y => prdata_o_1_0_iv_0_0_tz(16));
    
    \idq_pi_ki_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(13));
    
    \pwm_dead_time_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(17));
    
    \adc_scale_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(3));
    
    \prdata_o_1_iv_0_0_a2_24[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_502, B => \N_500\, C => 
        \prdata_o_1_iv_0_0_a2_24_0\(1), D => 
        prdata_o_1_2_0_a2_17_0(1), Y => \N_508\);
    
    prdata_o_1_iv_0_0_12_4_2_N_3L4 : CFG3
      generic map(INIT => x"F7")

      port map(A => \N_507\, B => adc_interface_0_result_ch2_o(3), 
        C => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_iv_0_0_12_4_2_N_3L4_Z);
    
    \prdata_o_1_0_iv_0_12_0[4]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(4), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_12_0(4));
    
    \pwm_period_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(3));
    
    \theta_gen_slew_count_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(16));
    
    \sqmng_dv_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(14));
    
    \adc_channel_ch2_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(9));
    
    \prdata_o_1_0_iv_0_a2_6_2[9]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        STEPPER_THETA_0_theta_output_o(9), C => \N_505\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_a2_6_2_5);
    
    \theta_gen_slew_count_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(17));
    
    pwm_dead_time_val_o_1_sqmuxa_0_a2_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => \N_540\, B => N_538, C => N_510, Y => 
        pwm_dead_time_val_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_0_a2_25[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_516\, B => prdata_o_1_2_0_a2_17_0(1), C
         => \N_500\, D => \prdata_o_1_iv_0_0_a2_26_0\(1), Y => 
        \N_518\);
    
    \adc_scale_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(5));
    
    \theta_gen_slew_count_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(7));
    
    \prdata_o_1_0_iv_0_1_a2[21]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_45_0\(0), B => \N_503\, 
        C => STEPPER_THETA_1_step_count_o_21, D => \N_509\, Y => 
        N_318);
    
    \prdata_o_1_iv_0_0_a2_24_1_RNIH6VK1_0[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_2_0_a2_17_0(1), B => 
        \prdata_m1_e_11_0\, C => prdata_o_1_iv_0_0_a2_24_1(1), D
         => \N_500\, Y => N_534);
    
    \idq_pi_kp_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(14));
    
    sqmng_dv_o_1_sqmuxa_0_a2_2_a2_4_RNI19781 : CFG4
      generic map(INIT => x"8000")

      port map(A => SEQ_CONTROLLER_1_state_o_0_0, B => \N_540\, C
         => \N_519\, D => N_502, Y => prdata_m4_e_0);
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_3_a2_1 : CFG4
      generic map(INIT => x"0080")

      port map(A => N_525, B => N_502, C => \N_500\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), Y => N_538);
    
    \sqmng_dv_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(5));
    
    \prdata_o_1_iv_0_0_a2_24_0_cZ[1]\ : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => 
        \prdata_o_1_iv_0_0_a2_24_0\(1));
    
    m20_i_a2_7_0 : CFG4
      generic map(INIT => x"0080")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        adc_interface_0_result_ch0_o_1, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => m20_i_a2_7_0_Z);
    
    \adc_scale_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(2));
    
    \idq_pi_kp_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(13));
    
    \adc_channel_ch3_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(5));
    
    \adc_channel_ch3_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(1));
    
    \adc_channel_ch3_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(7));
    
    \sqmng_dv_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(13));
    
    \prdata_o_1_0_iv_0_m2_i_m2_i_m3[17]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(17), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(17), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => N_123);
    
    \prdata_o_1_0_iv_0_0_0[5]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch2_o(5), B => 
        adc_measurements_0_adc_result_ch3_o_5, C => \N_507\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_0_1);
    
    \pwm_period_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(12));
    
    \prdata_o_1_iv_0_0_a2_19[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a2_24_1(1), B => \N_503\, C
         => adc_interface_0_result_ch0_o_0, D => 
        \prdata_m1_e_11_0\, Y => N_215);
    
    \adc_oc_thresh_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(14));
    
    \pwm_delay_time_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(11));
    
    \prdata_o_1_iv_0_0_8_tz[3]\ : CFG4
      generic map(INIT => x"0C0A")

      port map(A => FOC_TRANSFORMS_0_id_o_2, B => 
        FOC_TRANSFORMS_1_valpha_o_2, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        prdata_o_1_iv_0_0_8_tz(3));
    
    \prdata_o_1_0_iv_0_12_0[5]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(5), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_12_0(5));
    
    \theta_gen_cmd_step_no_o[20]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(20), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(20));
    
    theta_gen_slew_count_o_1_sqmuxa_0_a2_0_a2_0 : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => \N_509\);
    
    \adc_channel_ch2_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(7));
    
    \theta_gen_cmd_step_no_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(11));
    
    \prdata_o_1_0_iv_0_a2_3_s[14]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        STEPPER_THETA_0_theta_output_o(14), C => \N_505\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_a2_3_out_1);
    
    \id_ref_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(3));
    
    theta_gen_cmd_step_no_o_1_sqmuxa_0_a2_1_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_550, B => N_547, C => \N_517\, Y => 
        theta_gen_cmd_step_no_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_0[14]\ : CFG4
      generic map(INIT => x"F080")

      port map(A => \N_516\, B => prdata_m4_0_1, C => \N_503\, D
         => prdata_m2_0_a2_17_2, Y => prdata_o_1_0_iv_0_0(14));
    
    \adc_control_reg_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_control_reg_val_o(2));
    
    \adc_channel_ch3_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(0));
    
    \prdata_o_1_iv_0_0_11_RNO[3]\ : CFG4
      generic map(INIT => x"7FFF")

      port map(A => \N_500\, B => prdata_o_1_2_0_a2_17_0(1), C
         => prdata_N_8_4, D => prdata_o_1_iv_0_0_a2_24_1(1), Y
         => prdata_N_7_6);
    
    prdata_m2_e_0_c : CFG4
      generic map(INIT => x"C480")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        \prdata_m2_e_0\, C => FOC_TRANSFORMS_0_vbeta_o_3, D => 
        FOC_TRANSFORMS_0_iq_o_0, Y => prdata_m2_e_0_0);
    
    \idq_pi_ki_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(16));
    
    \adc_channel_ch3_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(11));
    
    \theta_gen_rate_limit_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(10));
    
    \theta_gen_cmd_step_no_o[18]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(18), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(18));
    
    \adc_oc_thresh_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(13));
    
    \adc_channel_ch0_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(9));
    
    \prdata_o_1_0_iv_0_2_tz[8]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => STEPPER_THETA_1_step_count_o_8, B => 
        STEPPER_THETA_0_theta_output_o(8), C => \N_513\, D => 
        \N_509\, Y => prdata_o_1_0_iv_0_2_tz_4);
    
    \adc_channel_ch2_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(13));
    
    adc_channel_ch1_o_1_sqmuxa_0_a2_3_a2_2 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => N_550);
    
    \prdata_o_1_0_iv_0_12_0[11]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(11), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(11), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_12_0(11));
    
    \adc_channel_ch2_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(10));
    
    \adc_channel_ch1_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(14));
    
    \idq_pi_kp_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(7));
    
    \idq_pi_ki_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(4));
    
    \theta_gen_rate_limit_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(0));
    
    \theta_gen_rate_limit_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(3));
    
    \prdata_o_1_0_iv_0_12_1_cZ[7]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => SPEED_ID_IQ_PI_1_id_pi_output_o(7), B => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(7), C => N_240, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_12_1(7));
    
    \prdata_o_1_0_iv_0_4[13]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => FOC_TRANSFORMS_0_iq_o_9, B => 
        FOC_TRANSFORMS_1_valpha_o_12, C => \N_531\, D => \N_529\, 
        Y => prdata_o_1_0_iv_0_5(13));
    
    \prdata_o_1_0_iv_0_12[5]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_240, B => prdata_o_1_0_iv_0_12_0(5), C => 
        \prdata_o_1_0_iv_0_12_4\(8), D => \N_516\, Y => 
        prdata_o_1_0_iv_0_5_1);
    
    \idq_pi_kp_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(5));
    
    adc_oc_thresh_o_1_sqmuxa_0_a2_1_a2 : CFG4
      generic map(INIT => x"0080")

      port map(A => \N_544\, B => N_538, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        adc_oc_thresh_o_1_sqmuxa);
    
    \pwm_period_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(2));
    
    \adc_scale_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(17));
    
    \theta_gen_slew_count_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(6));
    
    \pwm_period_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(7));
    
    \prdata_o_1_0_iv_0_a2_5[7]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_513\, B => ADC_SCALING_0_ib_adc_o_7, C => 
        \N_503\, D => \prdata_o_1_iv_0_0_a2_26_0\(1), Y => N_414);
    
    adc_channel_ch3_o_1_sqmuxa_0_a2_2_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => \N_540\, B => N_538, C => \N_505\, Y => 
        adc_channel_ch3_o_1_sqmuxa);
    
    \idq_pi_kp_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(16));
    
    \adc_channel_ch0_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(13));
    
    \idq_pi_kp_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(9));
    
    stop_motor_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => stop_motor_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_if_st_0_stop_motor_o);
    
    idq_pi_ki_o_1_sqmuxa_0_a2_3_a2 : CFG4
      generic map(INIT => x"0080")

      port map(A => idq_pi_ki_o_1_sqmuxa_4, B => \N_544\, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        idq_pi_ki_o_1_sqmuxa);
    
    \adc_oc_thresh_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(7));
    
    \adc_channel_ch2_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(5));
    
    \theta_gen_rate_limit_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(5));
    
    \adc_oc_thresh_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(4));
    
    \pwm_delay_time_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(16));
    
    \idq_pi_ki_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(12));
    
    \adc_channel_ch0_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(10));
    
    \pwm_period_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(5));
    
    \sqmng_dv_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(3));
    
    \pwm_period_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(11));
    
    \theta_gen_slew_count_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(13));
    
    \pwm_dead_time_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(3));
    
    m20_m2_0_a2_1_c : CFG4
      generic map(INIT => x"0400")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(9), B => 
        adc_measurements_0_adc_result_ch3_o_2, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), Y => m20_m2_0_a2_1);
    
    \theta_gen_cmd_step_no_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(16));
    
    \pwm_delay_time_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(17));
    
    \pwm_dead_time_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(4));
    
    \id_ref_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(12));
    
    \id_ref_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(8));
    
    \adc_channel_ch1_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(6));
    
    \sqmng_dv_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(10));
    
    \pwm_period_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(1));
    
    \idq_pi_ki_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(2));
    
    \idq_pi_ki_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(9));
    
    \adc_oc_thresh_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(11));
    
    \prdata_o_1_iv_0_0_a2_43_1[0]\ : CFG4
      generic map(INIT => x"1000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(10), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), C => \N_519\, D => 
        \N_540\, Y => \prdata_o_1_iv_0_0_4_2_1_0\(3));
    
    \adc_channel_ch3_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(3));
    
    \theta_gen_slew_count_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_slew_count_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_slew_count_o(4));
    
    \sqmng_dv_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(9));
    
    \id_ref_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(9));
    
    \sqmng_dv_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(4));
    
    \prdata_o_1_0_iv_0_5[13]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => \N_527\, B => FOC_TRANSFORMS_0_id_o_12, C => 
        prdata_o_1_0_iv_0_1(13), D => prdata_o_1_0_iv_0_2(13), Y
         => prdata_o_1_0_iv_0_6(13));
    
    \adc_channel_ch2_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(15));
    
    \prdata_o_1_0_iv_0_2[14]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => FOC_TRANSFORMS_1_valpha_o_13, B => 
        FOC_TRANSFORMS_0_id_o_13, C => \N_529\, D => \N_527\, Y
         => prdata_o_1_0_iv_0_2(14));
    
    \pwm_delay_time_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(5));
    
    \idq_pi_kp_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(12));
    
    \sqmng_dv_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(11));
    
    \prdata_o_1_iv_0_0_a2_24_0_RNII6MN3_0[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_m5_e_0_4_1_Z, B => 
        \prdata_o_1_iv_0_0_a2_24_0\(1), C => prdata_m5_e_0_3, D
         => prdata_o_1_2_0_a2_17_0(1), Y => \N_529\);
    
    \prdata_o_1_0_iv_0_1_o2_0_RNO[17]\ : CFG4
      generic map(INIT => x"B391")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        prdata_o_1_0_iv_0_m2_i_m3_1_1(18), C => 
        FOC_TRANSFORMS_1_valpha_o_16, D => 
        FOC_TRANSFORMS_0_vbeta_o_16, Y => N_130);
    
    \prdata_o_1_0_iv_0_1[13]\ : CFG4
      generic map(INIT => x"CC80")

      port map(A => \N_516\, B => \N_503\, C => prdata_m4_1, D
         => prdata_m2_0_a2_9_2_Z, Y => prdata_o_1_0_iv_0_1(13));
    
    theta_gen_rate_limit_o_1_sqmuxa_0_a2_0_a2 : CFG2
      generic map(INIT => x"8")

      port map(A => \N_513\, B => N_547, Y => 
        theta_gen_rate_limit_o_1_sqmuxa);
    
    \adc_channel_ch3_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch3_o(14));
    
    \prdata_o_1_0_iv_0_2_RNO[16]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a2_24_1(1), B => \N_503\, C
         => prdata_m2_0_a2_11_0, D => \N_517\, Y => N_480);
    
    \id_ref_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(15));
    
    theta_gen_slew_count_o_1_sqmuxa_0_a2_0_a2_1_RNINDGD1 : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch2_o(0), B => 
        adc_measurements_0_adc_result_ch3_o_0, C => \N_507\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_m1_0_a2_0);
    
    sqmng_dv_o_1_sqmuxa_0_a2_2_a2_1 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), C => \N_500\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), Y => \N_542\);
    
    \pwm_period_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(8));
    
    \prdata_o_1_iv_0_0_2_tz[3]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => STEPPER_THETA_1_step_count_o_3, B => 
        STEPPER_THETA_0_theta_output_o(3), C => \N_513\, D => 
        \N_509\, Y => prdata_o_1_iv_0_0_2_tz(3));
    
    \prdata_o_1_iv_0_0_a2_43_1_RNIIULP[0]\ : CFG3
      generic map(INIT => x"80")

      port map(A => \prdata_o_1_iv_0_0_4_2_1_0\(3), B => \N_542\, 
        C => SEQ_CONTROLLER_1_state_o_0_2, Y => N_349);
    
    \prdata_o_1_0_iv_0_8_0[16]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(16), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(16), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_8_0(16));
    
    \adc_control_reg_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_control_reg_val_o(4));
    
    \prdata_o_1_iv_0_0_a2_14_1_cZ[1]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(4), B => 
        adc_interface_0_result_ch2_o(1), C => \N_505\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_iv_0_0_a2_14_1(1));
    
    \prdata_o_1_0_iv_0_RNO_0[14]\ : CFG3
      generic map(INIT => x"80")

      port map(A => \prdata_o_1_iv_0_0_a2_24_0\(1), B => N_502, C
         => prdata_m2_0_a2_17_1, Y => prdata_m2_0_a2_17_2);
    
    \prdata_o_1_0_iv_0_a2_3[15]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_45_0\(0), B => \N_503\, 
        C => STEPPER_THETA_0_theta_output_o(15), D => \N_513\, Y
         => N_494);
    
    \prdata_o_1_0_iv_0_0_tz[13]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => STEPPER_THETA_1_step_count_o_13, B => 
        STEPPER_THETA_0_theta_output_o(13), C => \N_513\, D => 
        \N_509\, Y => prdata_o_1_0_iv_0_0_tz(13));
    
    prdata_m5_e_0_4_1 : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_m5_e_0_4_1_Z);
    
    adc_scale_val_o_1_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"0080")

      port map(A => N_550, B => N_538, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        adc_scale_val_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_12_4_sx[4]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(9), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), Y => 
        prdata_o_1_0_iv_0_12_4_sx(4));
    
    \idq_pi_ki_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(7));
    
    \adc_channel_ch2_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(0));
    
    \id_ref_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(7));
    
    \adc_channel_ch0_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(15), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch0_o(15));
    
    \prdata_o_1_0_iv_0_RNO_2[14]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(14), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(14), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => prdata_N_7_4);
    
    \prdata_o_1_0_iv_0_12[6]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_26_0\(1), B => \N_503\, 
        C => prdata_o_1_0_iv_0_12_0(6), D => \N_516\, Y => 
        prdata_o_1_0_iv_0_5_2);
    
    \pwm_delay_time_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(9));
    
    \adc_oc_thresh_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_oc_thresh_o(3));
    
    \adc_channel_ch1_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(5));
    
    \pwm_delay_time_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_delay_time_val_o(12));
    
    \prdata_o_1_0_iv_0_3[14]\ : CFG4
      generic map(INIT => x"FEFA")

      port map(A => prdata_o_1_0_iv_0_0(14), B => 
        FOC_TRANSFORMS_0_iq_o_10, C => prdata_o_1_0_iv_0_6_a2(14), 
        D => \N_531\, Y => prdata_o_1_0_iv_0_4(14));
    
    \prdata_o_1_0_iv_0_1_a2[18]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a2_45_0\(0), B => \N_503\, 
        C => STEPPER_THETA_1_step_count_o_18, D => \N_509\, Y => 
        N_321);
    
    \prdata_o_1_0_iv_0_a2_1[11]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a2_24_1(1), B => \N_503\, C
         => adc_measurements_0_adc_result_ch1_o_9, D => 
        \prdata_m1_0_a2_2_0\, Y => N_354);
    
    \idq_pi_ki_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(10));
    
    \sqmng_dv_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(17));
    
    \prdata_o_1_iv_0_0_a2_24_1_RNIH6VK1[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_2_0_a2_17_0(1), B => 
        prdata_m2_0_a2_19_0_Z, C => prdata_o_1_iv_0_0_a2_24_1(1), 
        D => \N_500\, Y => N_533);
    
    \prdata_o_1_0_iv_0_a2_4[17]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_516\, B => N_123, C => \N_503\, D => 
        \prdata_o_1_iv_0_0_a2_26_0\(1), Y => N_554);
    
    \prdata_o_1_iv_0_0_a2_49_0[0]\ : CFG3
      generic map(INIT => x"01")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), Y => \N_500\);
    
    \prdata_o_1_0_iv_0_0_0_0_cZ[10]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch2_o(10), B => 
        adc_measurements_0_adc_result_ch3_o_10, C => \N_507\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_0_0(10));
    
    \id_ref_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => id_ref_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_id_ref_val_o(16));
    
    \adc_scale_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(6));
    
    adc_channel_ch0_o_1_sqmuxa_0_a2_0_a2 : CFG2
      generic map(INIT => x"8")

      port map(A => \N_513\, B => N_538, Y => 
        adc_channel_ch0_o_1_sqmuxa);
    
    \pwm_dead_time_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(13));
    
    \sqmng_dv_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(16));
    
    \pwm_period_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(16), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_period_val_o(16));
    
    \prdata_o_1_0_iv_0_0_0[8]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch2_o(8), B => 
        adc_measurements_0_adc_result_ch3_o_8, C => \N_507\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_0_4);
    
    \idq_pi_kp_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(2));
    
    \idq_pi_kp_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(1));
    
    \prdata_o_1_iv_0_0_a2_34[0]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \N_513\, B => prdata_o_1_2_0_a2_17_0(1), C
         => \N_500\, D => \prdata_o_1_iv_0_0_a2_26_0\(1), Y => 
        \N_528\);
    
    \theta_gen_cmd_step_no_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(8));
    
    \sqmng_dv_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(0));
    
    idq_pi_kp_o_0_sqmuxa_0_a2_0_a2_4 : CFG4
      generic map(INIT => x"0080")

      port map(A => idq_pi_kp_o_0_sqmuxa_0_a2_0_a2_4_0_Z, B => 
        N_521, C => \N_500\, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), Y => 
        idq_pi_ki_o_1_sqmuxa_4);
    
    \adc_scale_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(14), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(14));
    
    \prdata_o_1_0_iv_0_a2_6[16]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \N_527\, B => FOC_TRANSFORMS_0_id_o_15, Y => 
        N_487);
    
    \pwm_dead_time_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        pwm_dead_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_pwm_dead_time_val_o(0));
    
    \idq_pi_kp_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_kp_o(10));
    
    \idq_pi_ki_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(5));
    
    \idq_pi_ki_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_idq_pi_ki_o(11));
    
    \sqmng_dv_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(7));
    
    \sqmng_dv_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(12));
    
    \prdata_o_1_0_iv_0_12_4[4]\ : CFG3
      generic map(INIT => x"10")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(7), B => 
        prdata_o_1_0_iv_0_12_4_sx(4), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), Y => 
        \prdata_o_1_0_iv_0_12_4\(8));
    
    prdata_m2_0_a2_0_c : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => \prdata_m2_e_0\);
    
    \theta_gen_cmd_step_no_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(17), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(17));
    
    \theta_gen_cmd_step_no_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_cmd_step_no_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(4));
    
    \theta_gen_rate_limit_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => 
        theta_gen_rate_limit_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_theta_gen_rate_limit_o(2));
    
    start_motor_o_1_sqmuxa_0_a2_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_571, B => N_549, C => \N_505\, Y => 
        start_motor_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_12_0[6]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => SPEED_ID_IQ_PI_1_iq_pi_output_o(6), B => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(6), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_12_0(6));
    
    idq_pi_kp_o_0_sqmuxa_0_a2_0_a2 : CFG4
      generic map(INIT => x"0080")

      port map(A => idq_pi_ki_o_1_sqmuxa_4, B => N_550, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), Y => 
        idq_pi_kp_o_0_sqmuxa);
    
    \prdata_o_1_iv_0_0_a2_24_0_RNII6MN3[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_m5_e_0_4_1_Z, B => 
        \prdata_o_1_iv_0_0_a2_24_0\(1), C => prdata_m5_e_3, D => 
        prdata_o_1_2_0_a2_17_0(1), Y => \N_527\);
    
    \prdata_o_1_iv_0_0_a2_24_0_RNIFGNF2[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_m5_e_3, B => \N_503\, C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), D => 
        \prdata_o_1_iv_0_0_a2_24_0\(1), Y => \N_531\);
    
    \adc_channel_ch1_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(13), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(13));
    
    theta_gen_slew_count_o_1_sqmuxa_0_a2_0_a2_1 : CFG3
      generic map(INIT => x"01")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => \N_507\);
    
    \prdata_o_1_0_iv_0_0_0[6]\ : CFG4
      generic map(INIT => x"C0A0")

      port map(A => adc_interface_0_result_ch2_o(6), B => 
        adc_measurements_0_adc_result_ch3_o_6, C => \N_507\, D
         => MC_System_0_AMBA_SLAVE_1_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_0_2);
    
    id_ref_val_o_1_sqmuxa_0_a2_6_a2_0_RNIDFSG1 : CFG4
      generic map(INIT => x"0080")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(2), B => 
        \N_505\, C => ADC_SCALING_0_ib_adc_o_2, D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), Y => m20_i_a2_5_0);
    
    \adc_scale_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(9));
    
    \prdata_o_1_0_iv_0_1_sx[7]\ : CFG4
      generic map(INIT => x"EFFF")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(8), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), C => N_240, D => 
        prdata_N_7_5, Y => prdata_o_1_0_iv_0_1_sx(7));
    
    \sqmng_dv_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => sqmng_dv_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_sqmng_dv_o(2));
    
    \adc_channel_ch2_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch2_o(12));
    
    prdata_m2_0_a2_9_2 : CFG4
      generic map(INIT => x"0002")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), D => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), Y => prdata_m5_e_0_3);
    
    \adc_scale_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_scale_val_o(7));
    
    \adc_channel_ch1_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(10));
    
    \prdata_o_1_iv_0_0_a2_31[0]\ : CFG4
      generic map(INIT => x"2000")

      port map(A => \N_507\, B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), C => \N_503\, D => 
        \prdata_o_1_iv_0_0_a2_26_0\(1), Y => \N_524\);
    
    idq_pi_ki_o_1_sqmuxa_0_a2_3_a2_1 : CFG3
      generic map(INIT => x"02")

      port map(A => MC_System_0_AMBA_SLAVE_1_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), C => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), Y => N_521);
    
    \adc_channel_ch1_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_1_PWDATA(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_if_st_0_adc_channel_ch1_o(0));
    
    \prdata_o_1_iv_0_0_0_3_tz_cZ[1]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => STEPPER_THETA_1_step_count_o_1, B => 
        STEPPER_THETA_0_theta_output_o(1), C => \N_513\, D => 
        \N_509\, Y => prdata_o_1_iv_0_0_0_3_tz(1));
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_adc_scl_1 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_adc_scl_1;

architecture DEF_ARCH of mas_adc_scl_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal product_o_ONC : std_logic_vector(43 downto 36);
    signal MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(30) <= \product_o\(0);
    product_o(29) <= \product_o\(0);
    product_o(28) <= \product_o\(0);
    product_o(27) <= \product_o\(0);
    product_o(26) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
L2v6Hg8d6KM8MSfbxCxYH3Ykqlmwb++pDnGHfGGqPnK8QYqj23l67oDOV7Haodj6
Y06rMIT8CV8SayGnS18232KqwnTlFB1OUNIsKqjDirTsb+8QwJITo0VZUbnIBDrW
w+Ybke3+NNF9GsfboYZ+83DxMnVJ+LUirr/zfcYNiL0=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12525)
`protect data_block
[encoded data, 12288 characters]
YmTM67zkOxk5+kA0dXPcOC4GLfFDRclHsEXlIIM0qjQ=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity ADC_SCALING_1 is

    port( reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          adc_results_rdy_i    : in    std_logic;
          adc_scale_val_i      : in    std_logic_vector(17 downto 0);
          adc_result_ch0_i     : in    std_logic_vector(11 downto 0);
          adc_result_ch1_i     : in    std_logic_vector(11 downto 0);
          fault_threshold_i    : in    std_logic_vector(17 downto 0);
          done_o               : out   std_logic;
          calib_done_o         : out   std_logic;
          over_current_fault_o : out   std_logic;
          ia_adc_o             : out   std_logic_vector(17 downto 0);
          ib_adc_o             : out   std_logic_vector(17 downto 0)
        );

end ADC_SCALING_1;

architecture DEF_ARCH of ADC_SCALING_1 is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component mas_adc_scl_1
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \ia_adc_o\ : std_logic_vector(17 downto 0);
    signal \ib_adc_o\ : std_logic_vector(17 downto 0);
    signal MSC_net_100 : std_logic;
    signal s_mult0_in : std_logic_vector(17 downto 0);
    signal s_product : std_logic_vector(25 downto 8);
    signal s_adc_ch1_offset : std_logic_vector(30 downto 0);
    signal s_adc_ch0_offset : std_logic_vector(30 downto 0);
    signal s_state : std_logic_vector(1 downto 0);
    signal s_state_ns : std_logic_vector(1 downto 0);
    signal inf_abs1 : std_logic_vector(17 downto 0);
    signal inf_abs0 : std_logic_vector(17 downto 0);
    signal s_calib_cnt : std_logic_vector(13 downto 0);
    signal s_calib_cnt_cry : std_logic_vector(12 downto 0);
    signal s_calib_cnt_s : std_logic_vector(13 downto 0);
    signal un1_s_mult0_in_0 : std_logic_vector(16 downto 6);
    signal s_calib_cnt_cry_Y : std_logic_vector(12 downto 0);
    signal s_calib_cnt_s_FCO : std_logic_vector(13 to 13);
    signal s_calib_cnt_s_Y : std_logic_vector(13 to 13);
    signal s_calib_cnt_cry_cy_S : std_logic_vector(0 to 0);
    signal s_calib_cnt_cry_cy_Y : std_logic_vector(0 to 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1\, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o2\, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Z\, 
        MSC_net_476, MSC_net_477, MSC_net_478, MSC_net_479, 
        MSC_net_480, MSC_net_481, MSC_net_482, MSC_net_483, 
        MSC_net_484, MSC_net_485, MSC_net_486, MSC_net_487, 
        MSC_net_488, MSC_net_489, MSC_net_490, MSC_net_491, 
        MSC_net_492, MSC_net_493, MSC_net_494, MSC_net_495, 
        MSC_net_496, MSC_net_497, MSC_net_498, MSC_net_499, 
        MSC_net_500, MSC_net_501, MSC_net_502, MSC_net_503, 
        MSC_net_504, MSC_net_505, MSC_net_506, MSC_net_507, 
        MSC_net_508, MSC_net_509, MSC_net_510, MSC_net_511, 
        MSC_net_512, MSC_net_513, MSC_net_514, MSC_net_515, 
        MSC_net_516, MSC_net_517, MSC_net_518, MSC_net_519, 
        MSC_net_520, MSC_net_521, MSC_net_522, MSC_net_523, 
        MSC_net_524, MSC_net_525, MSC_net_526, MSC_net_527, 
        MSC_net_528, MSC_net_529, MSC_net_530, MSC_net_531, 
        MSC_net_532, MSC_net_533, MSC_net_534, MSC_net_535, 
        MSC_net_536, MSC_net_537, MSC_net_538, MSC_net_539, 
        MSC_net_540, MSC_net_541, MSC_net_542, MSC_net_543, 
        MSC_net_544, MSC_net_545, MSC_net_546, MSC_net_547, 
        MSC_net_548, MSC_net_549, MSC_net_550, MSC_net_551, 
        MSC_net_552, MSC_net_553, MSC_net_554, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, MSC_net_591, 
        MSC_net_592, MSC_net_593, MSC_net_594, MSC_net_595, 
        MSC_net_596, MSC_net_597, MSC_net_598, MSC_net_599, 
        MSC_net_600, MSC_net_601, MSC_net_602, MSC_net_603, 
        MSC_net_604, MSC_net_605, MSC_net_606, MSC_net_607, 
        MSC_net_608, MSC_net_609, MSC_net_610, MSC_net_611, 
        MSC_net_612, MSC_net_613, MSC_net_614, MSC_net_615, 
        MSC_net_616, MSC_net_617, MSC_net_618, MSC_net_619, 
        MSC_net_620, MSC_net_621, MSC_net_622, MSC_net_623, 
        MSC_net_624, MSC_net_625, MSC_net_626, MSC_net_627, 
        MSC_net_628, MSC_net_629, MSC_net_630, MSC_net_631, 
        MSC_net_632, MSC_net_633, MSC_net_634, MSC_net_635, 
        MSC_net_636, MSC_net_637, MSC_net_638, MSC_net_639, 
        MSC_net_640, MSC_net_641, MSC_net_642, MSC_net_643, 
        MSC_net_644, MSC_net_645, MSC_net_646, MSC_net_647, 
        MSC_net_648, MSC_net_649, MSC_net_650, MSC_net_651, 
        MSC_net_652, MSC_net_653, MSC_net_654, MSC_net_655, 
        MSC_net_656, MSC_net_657, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_17_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_17_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_17_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_17_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Y\, 
        MSC_net_730, MSC_net_731, MSC_net_732, MSC_net_733, 
        MSC_net_734, MSC_net_735, MSC_net_736, MSC_net_737, 
        MSC_net_738, MSC_net_739, MSC_net_740, MSC_net_741, 
        MSC_net_742, MSC_net_743, MSC_net_744, MSC_net_745, 
        MSC_net_746, MSC_net_747, MSC_net_748, MSC_net_749, 
        MSC_net_750, MSC_net_751, MSC_net_752, MSC_net_753, 
        MSC_net_754, MSC_net_755, MSC_net_756, MSC_net_757, 
        MSC_net_758, MSC_net_759, MSC_net_760, MSC_net_761, 
        MSC_net_762, MSC_net_763, MSC_net_764, MSC_net_765, 
        MSC_net_766, MSC_net_767, MSC_net_768, MSC_net_769, 
        MSC_net_770, MSC_net_771, MSC_net_772, MSC_net_773, 
        MSC_net_774, MSC_net_775, MSC_net_776, MSC_net_777, 
        MSC_net_778, MSC_net_779, MSC_net_780, MSC_net_781, 
        MSC_net_782, MSC_net_783, MSC_net_784, MSC_net_785, 
        MSC_net_786, MSC_net_787, MSC_net_788, MSC_net_789, 
        MSC_net_790, MSC_net_791, MSC_net_792, MSC_net_793, 
        MSC_net_794, MSC_net_795, MSC_net_796, MSC_net_797, 
        MSC_net_798, MSC_net_799, MSC_net_800, MSC_net_801, 
        MSC_net_802, MSC_net_803, MSC_net_804, MSC_net_805, 
        MSC_net_806, MSC_net_807, MSC_net_808, MSC_net_809, 
        MSC_net_810, MSC_net_811, MSC_net_812, MSC_net_813, 
        MSC_net_814, MSC_net_815, MSC_net_816 : std_logic;

    for all : mas_adc_scl_1
	Use entity work.mas_adc_scl_1(DEF_ARCH);
begin 

    calib_done_o <= MSC_net_100;
    ia_adc_o(17) <= \ia_adc_o\(17);
    ia_adc_o(16) <= \ia_adc_o\(16);
    ia_adc_o(15) <= \ia_adc_o\(15);
    ia_adc_o(14) <= \ia_adc_o\(14);
    ia_adc_o(13) <= \ia_adc_o\(13);
    ia_adc_o(12) <= \ia_adc_o\(12);
    ia_adc_o(11) <= \ia_adc_o\(11);
    ia_adc_o(10) <= \ia_adc_o\(10);
    ia_adc_o(9) <= \ia_adc_o\(9);
    ia_adc_o(8) <= \ia_adc_o\(8);
    ia_adc_o(7) <= \ia_adc_o\(7);
    ia_adc_o(6) <= \ia_adc_o\(6);
    ia_adc_o(5) <= \ia_adc_o\(5);
    ia_adc_o(4) <= \ia_adc_o\(4);
    ia_adc_o(3) <= \ia_adc_o\(3);
    ia_adc_o(2) <= \ia_adc_o\(2);
    ia_adc_o(1) <= \ia_adc_o\(1);
    ia_adc_o(0) <= \ia_adc_o\(0);
    ib_adc_o(17) <= \ib_adc_o\(17);
    ib_adc_o(16) <= \ib_adc_o\(16);
    ib_adc_o(15) <= \ib_adc_o\(15);
    ib_adc_o(14) <= \ib_adc_o\(14);
    ib_adc_o(13) <= \ib_adc_o\(13);
    ib_adc_o(12) <= \ib_adc_o\(12);
    ib_adc_o(11) <= \ib_adc_o\(11);
    ib_adc_o(10) <= \ib_adc_o\(10);
    ib_adc_o(9) <= \ib_adc_o\(9);
    ib_adc_o(8) <= \ib_adc_o\(8);
    ib_adc_o(7) <= \ib_adc_o\(7);
    ib_adc_o(6) <= \ib_adc_o\(6);
    ib_adc_o(5) <= \ib_adc_o\(5);
    ib_adc_o(4) <= \ib_adc_o\(4);
    ib_adc_o(3) <= \ib_adc_o\(3);
    ib_adc_o(2) <= \ib_adc_o\(2);
    ib_adc_o(1) <= \ib_adc_o\(1);
    ib_adc_o(0) <= \ib_adc_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
CN/HtD400ROkzBwbFAWxHbM0CLHuqtiGNvabqqouVbVa5NAsquk/z1BizQ8bXqju
QSuL0mf4Zn4DxLqXGnqDouGBD34N+Rf51Ae95c6dcMHyhOwbXR8+duybZyH3tj/2
HpOLniXCJ5swJXRM7nHjq5XG/iuEIAfwkbfJSo7Wnmc=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=141355)
`protect data_block
[encoded data, 139136 characters]
KYfPmt0KQIUsrBcTZGTGgHfZv+NCzvVP//uDEgP7X2U=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity pi_scheduler_spi_1 is

    port( s_pi_sel          : out   std_logic_vector(1 downto 0);
          iq_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_init_i         : in    std_logic_vector(17 downto 0);
          s_init            : out   std_logic_vector(17 downto 0);
          s_output_y        : in    std_logic_vector(17 downto 0);
          s_acc_out         : in    std_logic_vector(43 downto 0);
          iq_pi_act_input_i : in    std_logic_vector(17 downto 0);
          id_pi_act_input_i : in    std_logic_vector(17 downto 0);
          s_acc_in          : out   std_logic_vector(43 downto 0);
          iq_pi_start_i     : in    std_logic;
          reset_i           : in    std_logic;
          sys_clk_i         : in    std_logic;
          id_pi_done_o      : out   std_logic;
          s_done            : in    std_logic;
          iq_pi_done_o      : out   std_logic;
          s_start           : out   std_logic;
          s_pi_sel_1_rep2   : out   std_logic;
          s_pi_sel_0_rep1   : out   std_logic;
          clear_buffer_i    : in    std_logic;
          un3_init_o        : out   std_logic;
          id_pi_start_i     : in    std_logic;
          N_1328            : out   std_logic;
          N_1329            : out   std_logic;
          N_1330            : out   std_logic;
          N_1331            : out   std_logic;
          N_1332            : out   std_logic;
          N_1333            : out   std_logic;
          N_1334            : out   std_logic;
          N_1335            : out   std_logic;
          N_1336            : out   std_logic;
          N_1337            : out   std_logic;
          N_1338            : out   std_logic;
          N_1339            : out   std_logic;
          N_1340            : out   std_logic;
          N_1341            : out   std_logic;
          N_1342            : out   std_logic;
          N_1343            : out   std_logic;
          N_1344            : out   std_logic;
          N_1345            : out   std_logic;
          idq_en_i          : in    std_logic;
          s_en              : out   std_logic
        );

end pi_scheduler_spi_1;

architecture DEF_ARCH of pi_scheduler_spi_1 is 

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \s_pi_sel\ : std_logic_vector(1 downto 0);
    signal MSC_net_219, MSC_net_221, MSC_net_223, MSC_net_224
         : std_logic;
    signal s_pi_sel_dly : std_logic_vector(1 downto 0);
    signal s_speed_pi_acc_in : std_logic_vector(43 downto 0);
    signal s_speed_pi_acc_in_4 : std_logic_vector(43 downto 0);
    signal s_iq_acc_in : std_logic_vector(43 downto 0);
    signal s_id_acc_in : std_logic_vector(43 downto 0);
    signal speed_pi_output_y_o_5 : std_logic_vector(17 downto 0);
    signal s_pi_sel_fast : std_logic_vector(1 downto 0);
    signal MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, MSC_net_457, 
        MSC_net_458, MSC_net_459, MSC_net_460, MSC_net_461, 
        MSC_net_462, MSC_net_463, MSC_net_464, MSC_net_465, 
        MSC_net_466, MSC_net_467, MSC_net_468, MSC_net_469, 
        MSC_net_470, MSC_net_471, MSC_net_472, MSC_net_473, 
        MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, MSC_net_489, 
        MSC_net_490, MSC_net_491, MSC_net_492, MSC_net_493, 
        MSC_net_494, MSC_net_495, MSC_net_496, MSC_net_497, 
        MSC_net_498, MSC_net_499, MSC_net_500, MSC_net_501, 
        MSC_net_502, MSC_net_503, MSC_net_504, MSC_net_505, 
        MSC_net_506, MSC_net_507, MSC_net_508, MSC_net_509, 
        MSC_net_510, MSC_net_511, MSC_net_512, MSC_net_513, 
        MSC_net_514, MSC_net_515, MSC_net_516, MSC_net_517, 
        MSC_net_518, MSC_net_519, MSC_net_520, MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524 : std_logic;

begin 

    s_pi_sel(1) <= \s_pi_sel\(1);
    s_pi_sel(0) <= \s_pi_sel\(0);
    id_pi_done_o <= MSC_net_219;
    iq_pi_done_o <= MSC_net_221;
    s_pi_sel_1_rep2 <= MSC_net_223;
    s_pi_sel_0_rep1 <= MSC_net_224;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
YOCcu4xmVtSOqKKjippagtp3bs78ttPt4N7zfF/FdfX0Dw0gBF6nGJONDW/XhiBs
oFNlYhrWwDRoIiezy234XckoIdz/EiOOyGJFc2j8y277iSoNa76T0qlNgukPOnAx
p6657D+bIR4eSyX2ANAJkvXf8A5gYv3m9BdvtIZoDpc=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=112755)
`protect data_block
[encoded data, 110976 characters]
+wOzTKX8DkqZByz7kDIRyXSam6fNj7g9HT4/iVFIhzw=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_pi_spi_1 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_pi_spi_1;

architecture DEF_ARCH of mas_pi_spi_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_174, MSC_net_175, MSC_net_176 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
W1Z6a5kSjWgASlnvmOYBT57DFbHz1gWIO6J5MTEmG6QreuIEwVejK7K+mV35hMrl
XAt7cAWvIHcqIq1aVQGc0fQszPV3FbHXoihINRNt6j4WsvzVXMOlRoas1pAePSHZ
E6g5ZL612jUFUnI2Mz0agASEashXuJkVTDW8BI8iIBY=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12005)
`protect data_block
[encoded data, 11776 characters]
XjX/Cved2RHS87m0RHRRIm3UscUxVzkKOdBCBLV4wsc=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity pi_controller_spi_1 is

    port( s_acc_in_0        : in    std_logic_vector(43 downto 0);
          s_acc_out         : out   std_logic_vector(43 downto 0);
          s_output_y        : out   std_logic_vector(17 downto 0);
          s_init            : in    std_logic_vector(17 downto 0);
          id_pi_ref_input_i : in    std_logic_vector(17 downto 0);
          id_init_i         : in    std_logic_vector(17 downto 0);
          s_pi_sel          : in    std_logic_vector(1 downto 0);
          iq_pi_ki_i        : in    std_logic_vector(17 downto 0);
          iq_pi_kp_i        : in    std_logic_vector(17 downto 0);
          reset_i           : in    std_logic;
          sys_clk_i         : in    std_logic;
          s_done            : out   std_logic;
          s_en              : in    std_logic;
          N_1328            : in    std_logic;
          s_pi_sel_0_rep1   : in    std_logic;
          s_pi_sel_1_rep2   : in    std_logic;
          N_1329            : in    std_logic;
          N_1330            : in    std_logic;
          N_1331            : in    std_logic;
          N_1332            : in    std_logic;
          N_1333            : in    std_logic;
          N_1334            : in    std_logic;
          N_1335            : in    std_logic;
          N_1336            : in    std_logic;
          N_1337            : in    std_logic;
          N_1338            : in    std_logic;
          N_1339            : in    std_logic;
          N_1340            : in    std_logic;
          N_1341            : in    std_logic;
          N_1342            : in    std_logic;
          N_1343            : in    std_logic;
          N_1345            : in    std_logic;
          N_1344            : in    std_logic;
          s_start           : in    std_logic;
          un3_init_o        : in    std_logic
        );

end pi_controller_spi_1;

architecture DEF_ARCH of pi_controller_spi_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component mas_pi_spi_1
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

    signal s_piout : std_logic_vector(34 downto 1);
    signal s_piout_i : std_logic_vector(33 downto 16);
    signal s_acc_in : std_logic_vector(43 downto 0);
    signal s_inew : std_logic_vector(43 downto 0);
    signal s_product : std_logic_vector(43 downto 0);
    signal s_pout : std_logic_vector(43 downto 10);
    signal s_mult1_input : std_logic_vector(17 downto 0);
    signal s_mult1_input_6 : std_logic_vector(17 downto 0);
    signal s_add_cin : std_logic_vector(43 downto 0);
    signal s_add_cin_5 : std_logic_vector(43 downto 0);
    signal s_i_init_ds : std_logic_vector(17 downto 0);
    signal s_i_init_ds_2 : std_logic_vector(17 downto 1);
    signal s_state : std_logic_vector(4 downto 0);
    signal s_mult0_input : std_logic_vector(17 downto 0);
    signal s_error : std_logic_vector(17 downto 1);
    signal acc_out_o_3 : std_logic_vector(43 downto 0);
    signal output_y_o_5 : std_logic_vector(17 downto 0);
    signal s_state_ns : std_logic_vector(1 to 1);
    signal s_inew_RNIF2O61_S : std_logic_vector(16 to 16);
    signal s_inew_RNIF2O61_Y : std_logic_vector(16 to 16);
    signal s_pout_RNIGI6F2_Y : std_logic_vector(11 to 11);
    signal s_pout_RNIK5LN3_Y : std_logic_vector(12 to 12);
    signal s_pout_RNIRR305_Y : std_logic_vector(13 to 13);
    signal s_pout_RNISCJ86_Y : std_logic_vector(14 to 14);
    signal s_pout_RNI013H7_Y : std_logic_vector(15 to 15);
    signal s_pout_RNIODSN8_Y : std_logic_vector(16 to 16);
    signal s_pout_RNIJTLU9_Y : std_logic_vector(17 to 17);
    signal s_pout_RNIHGF5B_Y : std_logic_vector(18 to 18);
    signal s_pout_RNII69CC_Y : std_logic_vector(19 to 19);
    signal s_pout_RNIKJAND_Y : std_logic_vector(20 to 20);
    signal s_pout_RNIP3C2F_Y : std_logic_vector(21 to 21);
    signal s_pout_RNI1NDDG_Y : std_logic_vector(22 to 22);
    signal s_pout_RNICDFOH_Y : std_logic_vector(23 to 23);
    signal s_pout_RNIHUH3J_Y : std_logic_vector(24 to 24);
    signal s_pout_RNIPIKEK_Y : std_logic_vector(25 to 25);
    signal s_pout_RNI4ANPL_Y : std_logic_vector(26 to 26);
    signal s_pout_RNI1FG6N_Y : std_logic_vector(27 to 27);
    signal s_pout_RNI0M9JO_Y : std_logic_vector(28 to 28);
    signal s_pout_RNI1V20Q_Y : std_logic_vector(29 to 29);
    signal s_pout_RNIR1TCR_Y : std_logic_vector(30 to 30);
    signal s_pout_RNIN6NPS_Y : std_logic_vector(31 to 31);
    signal s_pout_RNILDH6U_Y : std_logic_vector(32 to 32);
    signal s_pout_RNILMBJV_Y : std_logic_vector(33 to 33);
    signal s_pout_RNIEP6011_Y : std_logic_vector(34 to 34);
    signal s_pout_RNI9U1D21_Y : std_logic_vector(35 to 35);
    signal s_pout_RNI65TP31_Y : std_logic_vector(36 to 36);
    signal s_pout_RNI5EO651_Y : std_logic_vector(37 to 37);
    signal s_pout_RNI5OJJ61_Y : std_logic_vector(38 to 38);
    signal s_pout_RNI63F081_Y : std_logic_vector(39 to 39);
    signal s_pout_RNIV6BD91_Y : std_logic_vector(40 to 40);
    signal s_pout_RNIPB7QA1_Y : std_logic_vector(41 to 41);
    signal s_pout_RNIKH37C1_Y : std_logic_vector(42 to 42);
    signal s_pout_RNICVR0F1_FCO : std_logic_vector(43 to 43);
    signal s_pout_RNICVR0F1_Y : std_logic_vector(43 to 43);
    signal s_pout_RNIGOVJD1_Y : std_logic_vector(43 to 43);
    signal s_state_ns_i_0 : std_logic_vector(0 to 0);
    signal s_iout : std_logic_vector(42 downto 0);
    signal acc_out_o_3_b_A : std_logic_vector(43 to 43);
    signal MSC_net_786, MSC_net_787, MSC_net_788, MSC_net_789, 
        MSC_net_790, MSC_net_791, MSC_net_792, MSC_net_793, 
        MSC_net_794, MSC_net_795, MSC_net_796, MSC_net_797, 
        MSC_net_798, MSC_net_799, MSC_net_800, MSC_net_801, 
        MSC_net_802, MSC_net_803, MSC_net_804, MSC_net_805, 
        MSC_net_806, MSC_net_807, MSC_net_808, MSC_net_809, 
        MSC_net_810, MSC_net_811, MSC_net_812, MSC_net_813, 
        MSC_net_814, MSC_net_815, MSC_net_816, MSC_net_817, 
        MSC_net_818, MSC_net_819, MSC_net_820, MSC_net_821, 
        MSC_net_822, MSC_net_823, MSC_net_824, MSC_net_825, 
        MSC_net_826, MSC_net_827, MSC_net_828, MSC_net_829, 
        MSC_net_830, MSC_net_831, MSC_net_832, MSC_net_833, 
        MSC_net_834, MSC_net_835, MSC_net_836, MSC_net_837, 
        MSC_net_838, MSC_net_839, MSC_net_840, MSC_net_841, 
        MSC_net_842, MSC_net_843, MSC_net_844, MSC_net_845, 
        MSC_net_846, MSC_net_847, MSC_net_848, MSC_net_849, 
        MSC_net_850, MSC_net_851, MSC_net_852, MSC_net_853, 
        MSC_net_854, MSC_net_855, MSC_net_856, MSC_net_857, 
        MSC_net_858, MSC_net_859, MSC_net_860, MSC_net_861, 
        MSC_net_862, MSC_net_863, MSC_net_864, MSC_net_865, 
        MSC_net_866, MSC_net_867, MSC_net_868, MSC_net_869, 
        MSC_net_870, MSC_net_871, MSC_net_872, MSC_net_873, 
        MSC_net_874, MSC_net_875, MSC_net_876, MSC_net_877, 
        MSC_net_878, MSC_net_879, MSC_net_880, MSC_net_881, 
        MSC_net_882, MSC_net_883, MSC_net_884, MSC_net_885, 
        MSC_net_886, MSC_net_887, MSC_net_888, MSC_net_889, 
        MSC_net_890, MSC_net_891, MSC_net_892, MSC_net_893, 
        MSC_net_894, MSC_net_895, MSC_net_896, MSC_net_897, 
        MSC_net_898, MSC_net_899, MSC_net_900, MSC_net_901, 
        MSC_net_902, MSC_net_903, MSC_net_904, MSC_net_905, 
        MSC_net_906, MSC_net_907, MSC_net_908, MSC_net_909, 
        MSC_net_910, MSC_net_911, MSC_net_912, MSC_net_913, 
        MSC_net_914, MSC_net_915, MSC_net_916, MSC_net_917, 
        MSC_net_918, MSC_net_919, MSC_net_920, MSC_net_921, 
        MSC_net_922, MSC_net_923, MSC_net_924, MSC_net_925, 
        MSC_net_926, MSC_net_927, MSC_net_928, MSC_net_929, 
        MSC_net_930, MSC_net_931, MSC_net_932, MSC_net_933, 
        MSC_net_934, MSC_net_935, MSC_net_936, MSC_net_937, 
        MSC_net_938, MSC_net_939, MSC_net_940, MSC_net_941, 
        MSC_net_942, MSC_net_943, MSC_net_944, MSC_net_945, 
        MSC_net_946, MSC_net_947, MSC_net_948, MSC_net_949, 
        MSC_net_950, MSC_net_951, MSC_net_952, MSC_net_953, 
        MSC_net_954, MSC_net_955, MSC_net_956, MSC_net_957, 
        MSC_net_958, MSC_net_959, MSC_net_960, MSC_net_961, 
        MSC_net_962, MSC_net_963, MSC_net_964, MSC_net_965, 
        MSC_net_966, MSC_net_967, MSC_net_968, MSC_net_969, 
        MSC_net_970, MSC_net_971, MSC_net_972, MSC_net_973, 
        MSC_net_974, MSC_net_975, MSC_net_976, MSC_net_977, 
        MSC_net_978, MSC_net_979, MSC_net_980, MSC_net_981, 
        MSC_net_982, MSC_net_983, MSC_net_984, MSC_net_985, 
        MSC_net_986, MSC_net_987, MSC_net_988, MSC_net_989, 
        MSC_net_990, MSC_net_991, MSC_net_992, MSC_net_993, 
        MSC_net_994, MSC_net_995, MSC_net_996, MSC_net_997, 
        MSC_net_998, MSC_net_999, MSC_net_1000, MSC_net_1001, 
        MSC_net_1002, MSC_net_1003, MSC_net_1004, MSC_net_1005, 
        MSC_net_1006, MSC_net_1007, MSC_net_1008, MSC_net_1009, 
        MSC_net_1010, MSC_net_1011, MSC_net_1012, MSC_net_1013, 
        MSC_net_1014, MSC_net_1015, MSC_net_1016, MSC_net_1017, 
        MSC_net_1018, MSC_net_1019, MSC_net_1020, MSC_net_1021, 
        MSC_net_1022, MSC_net_1023, MSC_net_1024, MSC_net_1025, 
        MSC_net_1026, MSC_net_1027, MSC_net_1028, MSC_net_1029, 
        MSC_net_1030, MSC_net_1031, MSC_net_1032, MSC_net_1033, 
        MSC_net_1034, MSC_net_1035, MSC_net_1036, MSC_net_1037, 
        MSC_net_1038, MSC_net_1039, MSC_net_1040, MSC_net_1041, 
        MSC_net_1042, MSC_net_1043, MSC_net_1044, MSC_net_1045, 
        MSC_net_1046, MSC_net_1047, MSC_net_1048, MSC_net_1049, 
        MSC_net_1050, MSC_net_1051, MSC_net_1052, MSC_net_1053, 
        MSC_net_1054, MSC_net_1055, MSC_net_1056, MSC_net_1057, 
        MSC_net_1058, MSC_net_1059, MSC_net_1060, MSC_net_1061, 
        MSC_net_1062, MSC_net_1063, MSC_net_1064, MSC_net_1065, 
        MSC_net_1066, MSC_net_1067, MSC_net_1068, MSC_net_1069, 
        MSC_net_1070, MSC_net_1071, MSC_net_1072, MSC_net_1073, 
        MSC_net_1074, MSC_net_1075, MSC_net_1076, MSC_net_1077, 
        MSC_net_1078, MSC_net_1079, MSC_net_1080, MSC_net_1081, 
        MSC_net_1082, MSC_net_1083, MSC_net_1084, MSC_net_1085, 
        MSC_net_1086, MSC_net_1087, MSC_net_1088, MSC_net_1089, 
        MSC_net_1090, MSC_net_1091, MSC_net_1092 : std_logic;

    for all : mas_pi_spi_1
	Use entity work.mas_pi_spi_1(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
dz6piJRvAdi2sAr3qxMYISV9PUPw6rqreoxQkOT3mJ5LChla21NlU9EEaIogE+lM
N/tPGtEQGZLbl79M6phNvbYQvc8Fkxk3YgpEYh9oPZOtJpNh8DXNjy7wr+w0xwt4
b+rCVuHlV/EY/RV0vOSQsKQnLrvVedWXePpDADdazHM=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=195130)
`protect data_block
[encoded data, 192128 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity SPEED_ID_IQ_PI_1 is

    port( reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          clear_buffer_i       : in    std_logic;
          speed_en_i           : in    std_logic;
          idq_en_i             : in    std_logic;
          speed_pi_start_i     : in    std_logic;
          id_pi_start_i        : in    std_logic;
          iq_pi_start_i        : in    std_logic;
          speed_init_i         : in    std_logic_vector(17 downto 0);
          id_init_i            : in    std_logic_vector(17 downto 0);
          iq_init_i            : in    std_logic_vector(17 downto 0);
          speed_pi_ref_input_i : in    std_logic_vector(17 downto 0);
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0);
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0);
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0);
          speed_pi_ymax_i      : in    std_logic_vector(17 downto 0);
          speed_pi_ymin_i      : in    std_logic_vector(17 downto 0);
          id_pi_ref_input_i    : in    std_logic_vector(17 downto 0);
          id_pi_act_input_i    : in    std_logic_vector(17 downto 0);
          id_pi_kp_i           : in    std_logic_vector(17 downto 0);
          id_pi_ki_i           : in    std_logic_vector(17 downto 0);
          idq_pi_ymax_i        : in    std_logic_vector(17 downto 0);
          idq_pi_ymin_i        : in    std_logic_vector(17 downto 0);
          iq_pi_ref_input_i    : in    std_logic_vector(17 downto 0);
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0);
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0);
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0);
          speed_pi_done_o      : out   std_logic;
          id_pi_done_o         : out   std_logic;
          iq_pi_done_o         : out   std_logic;
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0)
        );

end SPEED_ID_IQ_PI_1;

architecture DEF_ARCH of SPEED_ID_IQ_PI_1 is 

  component pi_scheduler_spi_1
    port( s_pi_sel          : out   std_logic_vector(1 downto 0);
          iq_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_init_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_init            : out   std_logic_vector(17 downto 0);
          s_output_y        : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_acc_out         : in    std_logic_vector(43 downto 0) := (others => 'U');
          iq_pi_act_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_act_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_acc_in          : out   std_logic_vector(43 downto 0);
          iq_pi_start_i     : in    std_logic := 'U';
          reset_i           : in    std_logic := 'U';
          sys_clk_i         : in    std_logic := 'U';
          id_pi_done_o      : out   std_logic;
          s_done            : in    std_logic := 'U';
          iq_pi_done_o      : out   std_logic;
          s_start           : out   std_logic;
          s_pi_sel_1_rep2   : out   std_logic;
          s_pi_sel_0_rep1   : out   std_logic;
          clear_buffer_i    : in    std_logic := 'U';
          un3_init_o        : out   std_logic;
          id_pi_start_i     : in    std_logic := 'U';
          N_1328            : out   std_logic;
          N_1329            : out   std_logic;
          N_1330            : out   std_logic;
          N_1331            : out   std_logic;
          N_1332            : out   std_logic;
          N_1333            : out   std_logic;
          N_1334            : out   std_logic;
          N_1335            : out   std_logic;
          N_1336            : out   std_logic;
          N_1337            : out   std_logic;
          N_1338            : out   std_logic;
          N_1339            : out   std_logic;
          N_1340            : out   std_logic;
          N_1341            : out   std_logic;
          N_1342            : out   std_logic;
          N_1343            : out   std_logic;
          N_1344            : out   std_logic;
          N_1345            : out   std_logic;
          idq_en_i          : in    std_logic := 'U';
          s_en              : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component pi_controller_spi_1
    port( s_acc_in_0        : in    std_logic_vector(43 downto 0) := (others => 'U');
          s_acc_out         : out   std_logic_vector(43 downto 0);
          s_output_y        : out   std_logic_vector(17 downto 0);
          s_init            : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_ref_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_init_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_pi_sel          : in    std_logic_vector(1 downto 0) := (others => 'U');
          iq_pi_ki_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_kp_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i           : in    std_logic := 'U';
          sys_clk_i         : in    std_logic := 'U';
          s_done            : out   std_logic;
          s_en              : in    std_logic := 'U';
          N_1328            : in    std_logic := 'U';
          s_pi_sel_0_rep1   : in    std_logic := 'U';
          s_pi_sel_1_rep2   : in    std_logic := 'U';
          N_1329            : in    std_logic := 'U';
          N_1330            : in    std_logic := 'U';
          N_1331            : in    std_logic := 'U';
          N_1332            : in    std_logic := 'U';
          N_1333            : in    std_logic := 'U';
          N_1334            : in    std_logic := 'U';
          N_1335            : in    std_logic := 'U';
          N_1336            : in    std_logic := 'U';
          N_1337            : in    std_logic := 'U';
          N_1338            : in    std_logic := 'U';
          N_1339            : in    std_logic := 'U';
          N_1340            : in    std_logic := 'U';
          N_1341            : in    std_logic := 'U';
          N_1342            : in    std_logic := 'U';
          N_1343            : in    std_logic := 'U';
          N_1345            : in    std_logic := 'U';
          N_1344            : in    std_logic := 'U';
          s_start           : in    std_logic := 'U';
          un3_init_o        : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \speed_pi_output_o\ : std_logic_vector(17 downto 0);
    signal s_acc_out : std_logic_vector(43 downto 0);
    signal s_output_y : std_logic_vector(17 downto 0);
    signal s_init : std_logic_vector(17 downto 0);
    signal \PI_SCHEDULER_INST.s_pi_sel\ : 
        std_logic_vector(1 downto 0);
    signal s_acc_in : std_logic_vector(43 downto 0);
    signal MSC_net_515, MSC_net_516, MSC_net_517, MSC_net_518, 
        \PI_SCHEDULER_INST.op_eq.un3_init_o\, MSC_net_520, 
        MSC_net_521, MSC_net_522, MSC_net_523, MSC_net_524, 
        MSC_net_525, MSC_net_526, MSC_net_527, MSC_net_528, 
        MSC_net_529, MSC_net_530, MSC_net_531, MSC_net_532, 
        MSC_net_533, MSC_net_534, MSC_net_535, MSC_net_536, 
        MSC_net_537, \PI_SCHEDULER_INST.s_pi_sel_1_rep2\, 
        \PI_SCHEDULER_INST.s_pi_sel_0_rep1\ : std_logic;

    for all : pi_scheduler_spi_1
	Use entity work.pi_scheduler_spi_1(DEF_ARCH);
    for all : pi_controller_spi_1
	Use entity work.pi_controller_spi_1(DEF_ARCH);
begin 

    \speed_pi_output_o\(17 downto 1) <= (OTHERS => 'U'); 
    speed_pi_done_o <= \speed_pi_output_o\(0);
    speed_pi_output_o(17) <= \speed_pi_output_o\(0);
    speed_pi_output_o(16) <= \speed_pi_output_o\(0);
    speed_pi_output_o(15) <= \speed_pi_output_o\(0);
    speed_pi_output_o(14) <= \speed_pi_output_o\(0);
    speed_pi_output_o(13) <= \speed_pi_output_o\(0);
    speed_pi_output_o(12) <= \speed_pi_output_o\(0);
    speed_pi_output_o(11) <= \speed_pi_output_o\(0);
    speed_pi_output_o(10) <= \speed_pi_output_o\(0);
    speed_pi_output_o(9) <= \speed_pi_output_o\(0);
    speed_pi_output_o(8) <= \speed_pi_output_o\(0);
    speed_pi_output_o(7) <= \speed_pi_output_o\(0);
    speed_pi_output_o(6) <= \speed_pi_output_o\(0);
    speed_pi_output_o(5) <= \speed_pi_output_o\(0);
    speed_pi_output_o(4) <= \speed_pi_output_o\(0);
    speed_pi_output_o(3) <= \speed_pi_output_o\(0);
    speed_pi_output_o(2) <= \speed_pi_output_o\(0);
    speed_pi_output_o(1) <= \speed_pi_output_o\(0);
    speed_pi_output_o(0) <= \speed_pi_output_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
A8ymnZdYWk5Zo5SBDoxZy2bQuSj23O/jCMV2M3oX67dX9s4X8dW26riPUFaTcI4+
GJ1gaNDTNxxR5AGJpT9HhPZ+l7yFEIclXwslQseBLaS05L9Pe1EWjNDuO5qPPfLQ
adN7KkcwHtuVwCQH4MMleelSlhFlwt36MG6RI4A75tM=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=25330)
`protect data_block
[encoded data, 24896 characters]
O6RSTr306QgIc7jWYDkA3oCeJ4uXZO9rwA8/o01RSSc=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity accumulator_st is

    port( s_stepcnt_buff                     : out   std_logic_vector(23 downto 0);
          s_theta_out_buff_17                : out   std_logic;
          s_theta_out_buff_0                 : out   std_logic;
          s_theta_out_buff_1                 : out   std_logic;
          s_theta_out_buff_2                 : out   std_logic;
          s_theta_out_buff_3                 : out   std_logic;
          s_theta_out_buff_4                 : out   std_logic;
          s_theta_out_buff_5                 : out   std_logic;
          s_theta_out_buff_6                 : out   std_logic;
          s_theta_out_buff_7                 : out   std_logic;
          s_theta_out_buff_8                 : out   std_logic;
          s_theta_out_buff_9                 : out   std_logic;
          s_count_buff                       : out   std_logic_vector(17 downto 0);
          s_count_3                          : out   std_logic_vector(16 downto 0);
          rate_limit_i                       : in    std_logic_vector(16 downto 10);
          s_step_cnt                         : in    std_logic_vector(23 downto 0);
          s_theta_output                     : in    std_logic_vector(17 downto 0);
          s_count                            : in    std_logic_vector(17 downto 0);
          reset_i                            : in    std_logic;
          sys_clk_i                          : in    std_logic;
          un1_s_count_buff_cry_17_RNIKLC01_Y : in    std_logic;
          s_count_3_cry_0_cy                 : in    std_logic;
          s_count_3_cry_16                   : out   std_logic;
          N_213                              : out   std_logic;
          un1_cmd_step_no_i_i_0              : in    std_logic;
          un2_s_step_cnt                     : in    std_logic;
          s_theta_output_6_0_cry_9           : in    std_logic;
          N_214                              : out   std_logic;
          N_215                              : out   std_logic;
          N_216                              : out   std_logic;
          N_217                              : out   std_logic;
          N_218                              : out   std_logic;
          s_theta_output_6_0_cry_16          : out   std_logic;
          N_219                              : out   std_logic;
          clear_buffer_i                     : in    std_logic
        );

end accumulator_st;

architecture DEF_ARCH of accumulator_st is 

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \s_count_buff\ : std_logic_vector(17 downto 0);
    signal step_count_buff_o_3 : std_logic_vector(23 downto 0);
    signal s_theta_out_buff : std_logic_vector(16 downto 10);
    signal theta_output_buff_o_3 : std_logic_vector(17 downto 0);
    signal count_buff_o_3 : std_logic_vector(17 downto 0);
    signal count_buff_o_RNIQ8B92_Y : std_logic_vector(0 to 0);
    signal count_buff_o_RNI1T9I3_Y : std_logic_vector(1 to 1);
    signal count_buff_o_RNI9I8R4_Y : std_logic_vector(2 to 2);
    signal count_buff_o_RNII8746_Y : std_logic_vector(3 to 3);
    signal count_buff_o_RNISV5D7_Y : std_logic_vector(4 to 4);
    signal count_buff_o_RNI7O4M8_Y : std_logic_vector(5 to 5);
    signal count_buff_o_RNIJH3V9_Y : std_logic_vector(6 to 6);
    signal count_buff_o_RNI0C28B_Y : std_logic_vector(7 to 7);
    signal count_buff_o_RNIE71HC_Y : std_logic_vector(8 to 8);
    signal count_buff_o_RNIT30QD_Y : std_logic_vector(9 to 9);
    signal count_buff_o_RNIKVR4F_Y : std_logic_vector(10 to 10);
    signal count_buff_o_RNICSNFG_Y : std_logic_vector(11 to 11);
    signal count_buff_o_RNI5QJQH_Y : std_logic_vector(12 to 12);
    signal count_buff_o_RNIVOF5J_Y : std_logic_vector(13 to 13);
    signal count_buff_o_RNIQOBGK_Y : std_logic_vector(14 to 14);
    signal count_buff_o_RNIMP7RL_Y : std_logic_vector(15 to 15);
    signal count_buff_o_RNIJR36N_Y : std_logic_vector(16 to 16);
    signal theta_output_buff_o_RNIJFJCD_Y : 
        std_logic_vector(10 to 10);
    signal theta_output_buff_o_RNIV44LE_Y : 
        std_logic_vector(11 to 11);
    signal theta_output_buff_o_RNIDSKTF_Y : 
        std_logic_vector(12 to 12);
    signal theta_output_buff_o_RNITL56H_Y : 
        std_logic_vector(13 to 13);
    signal theta_output_buff_o_RNIFHMEI_Y : 
        std_logic_vector(14 to 14);
    signal theta_output_buff_o_RNI3F7NJ_Y : 
        std_logic_vector(15 to 15);
    signal theta_output_buff_o_RNIPEOVK_Y : 
        std_logic_vector(16 to 16);
    signal MSC_net_245, MSC_net_246, MSC_net_247, MSC_net_248, 
        MSC_net_249, MSC_net_250, MSC_net_251, MSC_net_252, 
        MSC_net_253, MSC_net_254, MSC_net_255, MSC_net_256, 
        MSC_net_257, MSC_net_258, MSC_net_259, MSC_net_260, 
        MSC_net_261, MSC_net_262, MSC_net_263, MSC_net_264, 
        MSC_net_265, MSC_net_266, MSC_net_267, MSC_net_268
         : std_logic;

begin 

    \s_count_buff\(17) <= 'U';
    s_count_buff(16) <= \s_count_buff\(16);
    s_count_buff(15) <= \s_count_buff\(15);
    s_count_buff(14) <= \s_count_buff\(14);
    s_count_buff(13) <= \s_count_buff\(13);
    s_count_buff(12) <= \s_count_buff\(12);
    s_count_buff(11) <= \s_count_buff\(11);
    s_count_buff(10) <= \s_count_buff\(10);
    s_count_buff(9) <= \s_count_buff\(9);
    s_count_buff(8) <= \s_count_buff\(8);
    s_count_buff(7) <= \s_count_buff\(7);
    s_count_buff(6) <= \s_count_buff\(6);
    s_count_buff(5) <= \s_count_buff\(5);
    s_count_buff(4) <= \s_count_buff\(4);
    s_count_buff(3) <= \s_count_buff\(3);
    s_count_buff(2) <= \s_count_buff\(2);
    s_count_buff(1) <= \s_count_buff\(1);
    s_count_buff(0) <= \s_count_buff\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
VCYJySkoP1csXmerNLElGHh816kwXuq16O83egG5vM8ooPw8wuC++g3FtAO9zGyi
7OR3ofx7chCyTxgl3LbQ6TE0ubDdtP6OM9YGAHRn/TAbGuSbsTziZaJjBrKzOH7l
ScPtBb4Y34F3a0ySKjN+rm59D2lA23TX+8xhMjehiwA=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=47085)
`protect data_block
[encoded data, 46336 characters]
1mh6ceoFfJdiLGWiFO5gCw==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity STEPPER_THETA is

    port( reset_i        : in    std_logic;
          sys_clk_i      : in    std_logic;
          enable_i       : in    std_logic;
          mode_i         : in    std_logic;
          clear_buffer_i : in    std_logic;
          slew_cnt_i     : in    std_logic_vector(17 downto 0);
          rate_limit_i   : in    std_logic_vector(17 downto 0);
          cmd_step_no_i  : in    std_logic_vector(23 downto 0);
          theta_output_o : out   std_logic_vector(17 downto 0);
          step_count_o   : out   std_logic_vector(23 downto 0)
        );

end STEPPER_THETA;

architecture DEF_ARCH of STEPPER_THETA is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component accumulator_st
    port( s_stepcnt_buff                     : out   std_logic_vector(23 downto 0);
          s_theta_out_buff_17                : out   std_logic;
          s_theta_out_buff_0                 : out   std_logic;
          s_theta_out_buff_1                 : out   std_logic;
          s_theta_out_buff_2                 : out   std_logic;
          s_theta_out_buff_3                 : out   std_logic;
          s_theta_out_buff_4                 : out   std_logic;
          s_theta_out_buff_5                 : out   std_logic;
          s_theta_out_buff_6                 : out   std_logic;
          s_theta_out_buff_7                 : out   std_logic;
          s_theta_out_buff_8                 : out   std_logic;
          s_theta_out_buff_9                 : out   std_logic;
          s_count_buff                       : out   std_logic_vector(17 downto 0);
          s_count_3                          : out   std_logic_vector(16 downto 0);
          rate_limit_i                       : in    std_logic_vector(16 downto 10) := (others => 'U');
          s_step_cnt                         : in    std_logic_vector(23 downto 0) := (others => 'U');
          s_theta_output                     : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_count                            : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i                            : in    std_logic := 'U';
          sys_clk_i                          : in    std_logic := 'U';
          un1_s_count_buff_cry_17_RNIKLC01_Y : in    std_logic := 'U';
          s_count_3_cry_0_cy                 : in    std_logic := 'U';
          s_count_3_cry_16                   : out   std_logic;
          N_213                              : out   std_logic;
          un1_cmd_step_no_i_i_0              : in    std_logic := 'U';
          un2_s_step_cnt                     : in    std_logic := 'U';
          s_theta_output_6_0_cry_9           : in    std_logic := 'U';
          N_214                              : out   std_logic;
          N_215                              : out   std_logic;
          N_216                              : out   std_logic;
          N_217                              : out   std_logic;
          N_218                              : out   std_logic;
          s_theta_output_6_0_cry_16          : out   std_logic;
          N_219                              : out   std_logic;
          clear_buffer_i                     : in    std_logic := 'U'
        );
  end component;

    signal \theta_output_o\ : std_logic_vector(17 downto 0);
    signal \step_count_o\ : std_logic_vector(23 downto 0);
    signal s_count : std_logic_vector(17 downto 0);
    signal s_theta_out_buff : std_logic_vector(17 downto 0);
    signal s_count_buff : std_logic_vector(17 downto 0);
    signal s_stepcnt_buff : std_logic_vector(23 downto 0);
    signal s_count_1us : std_logic_vector(6 downto 0);
    signal un1_s_stepcnt_buff0 : std_logic_vector(23 downto 1);
    signal \THETA_STEP_COUNT_PROC.s_theta_output_6\ : 
        std_logic_vector(17 downto 0);
    signal 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_data_tmp\
         : std_logic_vector(11 downto 0);
    signal un1_s_stepcnt_buff1 : std_logic_vector(23 downto 1);
    signal s_count_1us_cry : std_logic_vector(5 downto 0);
    signal s_count_1us_s : std_logic_vector(6 downto 0);
    signal \THETA_STEP_COUNT_PROC.s_count_3\ : 
        std_logic_vector(17 downto 0);
    signal \THETA_STEP_COUNT_PROC.s_theta_output_6_RNO_FCO\ : 
        std_logic_vector(17 to 17);
    signal \THETA_STEP_COUNT_PROC.s_theta_output_6_RNO_Y\ : 
        std_logic_vector(17 to 17);
    signal rate_limit_i_RNI9S24C_Y : std_logic_vector(9 to 9);
    signal rate_limit_i_RNIFCJVA_Y : std_logic_vector(8 to 8);
    signal rate_limit_i_RNINU3R9_Y : std_logic_vector(7 to 7);
    signal rate_limit_i_RNI1JKM8_Y : std_logic_vector(6 to 6);
    signal rate_limit_i_RNID95I7_Y : std_logic_vector(5 to 5);
    signal rate_limit_i_RNIR1MD6_Y : std_logic_vector(4 to 4);
    signal rate_limit_i_RNIBS695_Y : std_logic_vector(3 to 3);
    signal rate_limit_i_RNITON44_Y : std_logic_vector(2 to 2);
    signal rate_limit_i_RNIHN803_Y : std_logic_vector(1 to 1);
    signal rate_limit_i_RNI7OPR1_Y : std_logic_vector(0 to 0);
    signal s_count_RNO_FCO : std_logic_vector(17 to 17);
    signal s_count_RNO_Y : std_logic_vector(17 to 17);
    signal s_count_1us_RNIAI1JC_Y : std_logic_vector(5 to 5);
    signal s_count_1us_RNO_FCO : std_logic_vector(6 to 6);
    signal s_count_1us_RNO_Y : std_logic_vector(6 to 6);
    signal s_count_1us_RNIBPINA_Y : std_logic_vector(4 to 4);
    signal s_count_1us_RNID14S8_Y : std_logic_vector(3 to 3);
    signal s_count_1us_RNIGAL07_Y : std_logic_vector(2 to 2);
    signal s_count_1us_RNIKK655_Y : std_logic_vector(1 to 1);
    signal s_count_1us_RNIPVN93_Y : std_logic_vector(0 to 0);
    signal MSC_net_321, MSC_net_322, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt\, 
        \THETA_STEP_COUNT_PROC.un1_clear_buffer_i_2_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_0_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_1_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_2_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_3_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_4_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_5_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_6_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_7_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_8_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_9_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_10_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_11_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_12_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_13_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_14_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_15_Z\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_16_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_0_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_1_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_2_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_3_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_4_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_5_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_6_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_7_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_8_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_9_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_10_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_11_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_12_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_13_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_14_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_15_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_16_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_17_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_18_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_19_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_20_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_21_Z\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_22_Z\, 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_0_400_i_o4_Z\, 
        \COUNT_1US_PROC.s_count_1us7lt6\, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_415_i_0\, 
        \THETA_STEP_COUNT_PROC.s_count_3_cry_16\, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_0\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_1\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_2\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_3\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_4\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_5\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_6\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_7\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_8\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_9\, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_16\, 
        MSC_net_444, 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_i_0\, 
        MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, MSC_net_457, 
        MSC_net_458, MSC_net_459, MSC_net_460, MSC_net_461, 
        MSC_net_462, MSC_net_463, MSC_net_464, MSC_net_465, 
        MSC_net_466, MSC_net_467, MSC_net_468, MSC_net_469, 
        MSC_net_470, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_0_0_cy\, 
        \THETA_STEP_COUNT_PROC.s_count_3_cry_0_cy\, MSC_net_473, 
        MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, MSC_net_489, 
        MSC_net_490, MSC_net_491, MSC_net_492, MSC_net_493, 
        MSC_net_494, MSC_net_495, MSC_net_496, MSC_net_497, 
        MSC_net_498, MSC_net_499, MSC_net_500, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_45_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_45_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_63_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_63_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_57_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_57_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_69_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_69_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_21_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_21_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_39_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_39_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_33_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_33_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_51_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_51_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_27_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_27_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_15_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_15_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_9_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_9_Y\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_1_S\, 
        \THETA_STEP_COUNT_PROC.op_eq.un1_cmd_step_no_i_0_I_1_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_17_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_17_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_16_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_16_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_15_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_15_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_14_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_14_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_13_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_13_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_12_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_12_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_11_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_11_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_10_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_10_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_9_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_9_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_8_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_8_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_7_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_7_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_6_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_6_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_5_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_5_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_4_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_4_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_3_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_3_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_2_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_2_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_1_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_1_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_0_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_0_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_23_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_23_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_22_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_22_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_21_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_21_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_20_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_20_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_19_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_19_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_18_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_18_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_17_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_17_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_16_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_16_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_15_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_15_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_14_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_14_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_13_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_13_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_12_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_12_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_11_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_11_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_10_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_10_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_9_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_9_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_8_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_8_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_7_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_7_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_6_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_6_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_5_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_5_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_4_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_4_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_3_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_3_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_2_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_2_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_1_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_1_Y\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_0_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_0_Y\, 
        MSC_net_609, MSC_net_610, MSC_net_611, MSC_net_612, 
        MSC_net_613, MSC_net_614, MSC_net_615, MSC_net_616, 
        MSC_net_617, MSC_net_618, MSC_net_619, MSC_net_620, 
        MSC_net_621, MSC_net_622, MSC_net_623, MSC_net_624, 
        MSC_net_625, MSC_net_626, MSC_net_627, MSC_net_628, 
        MSC_net_629, MSC_net_630, MSC_net_631, MSC_net_632, 
        MSC_net_633, MSC_net_634, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_23_RNIVQAN_S\, 
        \THETA_STEP_COUNT_PROC.un2_s_step_cnt_cry_23_RNIVQAN_Y\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_17_RNIKLC01_S\, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_17_RNIKLC01_Y\, 
        MSC_net_639, MSC_net_640 : std_logic;

    for all : accumulator_st
	Use entity work.accumulator_st(DEF_ARCH);
begin 

    theta_output_o(17) <= \theta_output_o\(17);
    theta_output_o(16) <= \theta_output_o\(16);
    theta_output_o(15) <= \theta_output_o\(15);
    theta_output_o(14) <= \theta_output_o\(14);
    theta_output_o(13) <= \theta_output_o\(13);
    theta_output_o(12) <= \theta_output_o\(12);
    theta_output_o(11) <= \theta_output_o\(11);
    theta_output_o(10) <= \theta_output_o\(10);
    theta_output_o(9) <= \theta_output_o\(9);
    theta_output_o(8) <= \theta_output_o\(8);
    theta_output_o(7) <= \theta_output_o\(7);
    theta_output_o(6) <= \theta_output_o\(6);
    theta_output_o(5) <= \theta_output_o\(5);
    theta_output_o(4) <= \theta_output_o\(4);
    theta_output_o(3) <= \theta_output_o\(3);
    theta_output_o(2) <= \theta_output_o\(2);
    theta_output_o(1) <= \theta_output_o\(1);
    theta_output_o(0) <= \theta_output_o\(0);
    step_count_o(23) <= \step_count_o\(23);
    step_count_o(22) <= \step_count_o\(22);
    step_count_o(21) <= \step_count_o\(21);
    step_count_o(20) <= \step_count_o\(20);
    step_count_o(19) <= \step_count_o\(19);
    step_count_o(18) <= \step_count_o\(18);
    step_count_o(17) <= \step_count_o\(17);
    step_count_o(16) <= \step_count_o\(16);
    step_count_o(15) <= \step_count_o\(15);
    step_count_o(14) <= \step_count_o\(14);
    step_count_o(13) <= \step_count_o\(13);
    step_count_o(12) <= \step_count_o\(12);
    step_count_o(11) <= \step_count_o\(11);
    step_count_o(10) <= \step_count_o\(10);
    step_count_o(9) <= \step_count_o\(9);
    step_count_o(8) <= \step_count_o\(8);
    step_count_o(7) <= \step_count_o\(7);
    step_count_o(6) <= \step_count_o\(6);
    step_count_o(5) <= \step_count_o\(5);
    step_count_o(4) <= \step_count_o\(4);
    step_count_o(3) <= \step_count_o\(3);
    step_count_o(2) <= \step_count_o\(2);
    step_count_o(1) <= \step_count_o\(1);
    step_count_o(0) <= \step_count_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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3wuFGHGCymnkbF0R11FAbab9o0VPYFxb6+yGBUN+ngAUfI0N6+HRxEPRdxLCD6YZ
03fpNOMRQfrRA/eLKZT4zyFjEtkpUOvkz5X+l76YOKU=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=122005)
`protect data_block
[encoded data, 120128 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity SEQ_CONTROLLER_1 is

    port( reset_i         : in    std_logic;
          sys_clk_i       : in    std_logic;
          fault_i         : in    std_logic;
          start_motor_i   : in    std_logic;
          stop_motor_i    : in    std_logic;
          fault_clear_i   : in    std_logic;
          speed_ref_i     : in    std_logic_vector(17 downto 0);
          speed_cl_i      : in    std_logic_vector(17 downto 0);
          vq_i            : in    std_logic_vector(17 downto 0);
          max_ar_i        : in    std_logic_vector(3 downto 0);
          calib_done_i    : in    std_logic;
          pwm_midmatch_i  : in    std_logic;
          foc_done_i      : in    std_logic;
          config_reg_i    : in    std_logic_vector(3 downto 0);
          adc_start_o     : out   std_logic;
          cl_status_o     : out   std_logic;
          en_idq_pi_o     : out   std_logic;
          en_pwm_o        : out   std_logic;
          motor_stopped_o : out   std_logic;
          reset_rl_o      : out   std_logic;
          soft_stop_o     : out   std_logic;
          sensor_reset_o  : out   std_logic;
          state_o         : out   std_logic_vector(3 downto 0)
        );

end SEQ_CONTROLLER_1;

architecture DEF_ARCH of SEQ_CONTROLLER_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal MSC_net_79 : std_logic;
    signal s_state : std_logic_vector(8 downto 0);
    signal s_adctrig_count : std_logic_vector(12 downto 0);
    signal s_state_ns : std_logic_vector(6 to 6);
    signal s_state_ns_i_0_i_a3 : std_logic_vector(4 to 4);
    signal s_state_ns_0_0_a3_0_0 : std_logic_vector(6 to 6);
    signal s_adctrig_count_cry : std_logic_vector(11 downto 0);
    signal s_adctrig_count_s : std_logic_vector(12 downto 0);
    signal s_sensor_calib_count : std_logic_vector(13 downto 0);
    signal s_sensor_calib_count_cry : 
        std_logic_vector(12 downto 0);
    signal s_sensor_calib_count_s : 
        std_logic_vector(13 downto 0);
    signal s_state_ns_i_0_7_i_o2_6 : std_logic_vector(2 to 2);
    signal s_state_ns_i_0_7_i_o2_7 : std_logic_vector(2 to 2);
    signal s_state_ns_i_0_7_i_o2_8 : std_logic_vector(2 to 2);
    signal s_state_ns_i_0_7_i_o2_9 : std_logic_vector(2 to 2);
    signal s_state_ns_i_i_0_a3_0_0 : std_logic_vector(1 to 1);
    signal s_state_ns_i_i_i_1 : std_logic_vector(0 to 0);
    signal s_sensor_calib_count_RNICLE93_Y : 
        std_logic_vector(12 to 12);
    signal s_sensor_calib_count_RNO_FCO : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNO_Y : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNI3PI33_Y : 
        std_logic_vector(11 to 11);
    signal s_sensor_calib_count_RNIRTMT2_Y : 
        std_logic_vector(10 to 10);
    signal s_sensor_calib_count_RNIK3RN2_Y : 
        std_logic_vector(9 to 9);
    signal s_sensor_calib_count_RNILCCG2_Y : 
        std_logic_vector(8 to 8);
    signal s_sensor_calib_count_RNINMT82_Y : 
        std_logic_vector(7 to 7);
    signal s_sensor_calib_count_RNIQ1F12_Y : 
        std_logic_vector(6 to 6);
    signal s_sensor_calib_count_RNIUD0Q1_Y : 
        std_logic_vector(5 to 5);
    signal s_sensor_calib_count_RNI3RHI1_Y : 
        std_logic_vector(4 to 4);
    signal s_sensor_calib_count_RNI993B1_Y : 
        std_logic_vector(3 to 3);
    signal s_sensor_calib_count_RNIGOK31_Y : 
        std_logic_vector(2 to 2);
    signal s_sensor_calib_count_RNIO86S_Y : 
        std_logic_vector(1 to 1);
    signal s_sensor_calib_count_RNI1QNK_Y : 
        std_logic_vector(0 to 0);
    signal s_sensor_calib_count_RNIBC9D_S : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNIBC9D_Y : 
        std_logic_vector(13 to 13);
    signal s_adctrig_count_RNII4KQB_Y : 
        std_logic_vector(11 to 11);
    signal s_adctrig_count_RNO_FCO : std_logic_vector(12 to 12);
    signal s_adctrig_count_RNO_Y : std_logic_vector(12 to 12);
    signal s_adctrig_count_RNIMPBJA_Y : 
        std_logic_vector(10 to 10);
    signal s_adctrig_count_RNIRF3C9_Y : std_logic_vector(9 to 9);
    signal s_adctrig_count_RNI8JDG8_Y : std_logic_vector(8 to 8);
    signal s_adctrig_count_RNIMNNK7_Y : std_logic_vector(7 to 7);
    signal s_adctrig_count_RNI5T1P6_Y : std_logic_vector(6 to 6);
    signal s_adctrig_count_RNIL3CT5_Y : std_logic_vector(5 to 5);
    signal s_adctrig_count_RNI6BM15_Y : std_logic_vector(4 to 4);
    signal s_adctrig_count_RNIOJ064_Y : std_logic_vector(3 to 3);
    signal s_adctrig_count_RNIBTAA3_Y : std_logic_vector(2 to 2);
    signal s_adctrig_count_RNIV7LE2_Y : std_logic_vector(1 to 1);
    signal s_adctrig_count_RNIKJVI1_Y : std_logic_vector(0 to 0);
    signal MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, \ADC_START_PROC.adc_start_o_3\, MSC_net_214, 
        MSC_net_215, MSC_net_216, MSC_net_217, MSC_net_218, 
        MSC_net_219, MSC_net_220, MSC_net_221, MSC_net_222, 
        MSC_net_223, MSC_net_224, MSC_net_225, MSC_net_226, 
        MSC_net_227, MSC_net_228, MSC_net_229, MSC_net_230, 
        MSC_net_231, MSC_net_232, MSC_net_233, MSC_net_234, 
        MSC_net_235, MSC_net_236, MSC_net_237, MSC_net_238, 
        MSC_net_239, MSC_net_240, MSC_net_241, MSC_net_242, 
        MSC_net_243, MSC_net_244, 
        \ADC_START_PROC.op_eq.un98_s_state_Z\, 
        \ADC_START_PROC.adc_start_o_3_iv_0_0_a3_0_0_Z\, 
        \ADC_START_PROC.op_eq.un98_s_state_7_Z\, 
        \ADC_START_PROC.op_eq.un98_s_state_8_Z\, MSC_net_249, 
        MSC_net_250, MSC_net_251, MSC_net_252, MSC_net_253, 
        MSC_net_254, MSC_net_255, MSC_net_256, 
        \ADC_START_PROC.op_eq.un98_s_state_1_Z\, MSC_net_258, 
        MSC_net_259 : std_logic;

begin 

    cl_status_o <= MSC_net_79;
    reset_rl_o <= MSC_net_79;
    soft_stop_o <= MSC_net_79;
    sensor_reset_o <= MSC_net_79;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
UEdWxueNB4L8Y5A+uFShCyOSQJer+ZY02jWwwCc4gF8m0psnhVYSVraBSGUF8nQs
3xSCCiileB6uJxw2RzbA4VxNC3i7XS+b7tLaVPZIlsY79irP4AYYNL6THMsNNE+d
9lS5YG2d960d4jnjv1pzFIb3ssu1yuV2kfpBtkX1h8I=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=40625)
`protect data_block
[encoded data, 40000 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_pwm_scl_1 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_pwm_scl_1;

architecture DEF_ARCH of mas_pwm_scl_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(15) <= \product_o\(0);
    product_o(14) <= \product_o\(0);
    product_o(13) <= \product_o\(0);
    product_o(12) <= \product_o\(0);
    product_o(11) <= \product_o\(0);
    product_o(10) <= \product_o\(0);
    product_o(9) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
CFdEx5TKVrub6Aaz9kn2184AUltGkPM1JEt7MaKi7I37zFZdoxUqdHi3OR2xiBIe
jBKFwrxrHchIjE/RAtw72MeXDQ0U1tFBQlVbRyYxd3F/p4g8poydAMwoDUqHUxWO
Fobt3RBGh/5AspMMNgSEP31hSiXT/YY+iQvB8hbEf48=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12375)
`protect data_block
[encoded data, 12160 characters]
ZpAWuZJ7GH4E8t0prxPjag==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity PWM_SCALING_1 is

    port( reset_i      : in    std_logic;
          sys_clk_i    : in    std_logic;
          start_i      : in    std_logic;
          va_i         : in    std_logic_vector(17 downto 0);
          vb_i         : in    std_logic_vector(17 downto 0);
          vc_i         : in    std_logic_vector(17 downto 0);
          pwm_period_i : in    std_logic_vector(17 downto 0);
          pwm_gain_i   : in    std_logic_vector(17 downto 0);
          Va_o         : out   std_logic_vector(17 downto 0);
          Vb_o         : out   std_logic_vector(17 downto 0);
          Vc_o         : out   std_logic_vector(17 downto 0);
          done_o       : out   std_logic
        );

end PWM_SCALING_1;

architecture DEF_ARCH of PWM_SCALING_1 is 

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component mas_pwm_scl_1
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \Vc_o\ : std_logic_vector(17 downto 0);
    signal s_mult_in0 : std_logic_vector(17 downto 0);
    signal s_product : std_logic_vector(33 downto 16);
    signal s_state : std_logic_vector(4 downto 0);
    signal s_state_ns : std_logic_vector(1 to 1);
    signal s_state_ns_i : std_logic_vector(4 to 4);
    signal \MUL_INP_GEN_PROC.s_mult_in0_4\ : 
        std_logic_vector(17 downto 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_236, MSC_net_237, MSC_net_238, MSC_net_239, 
        MSC_net_240, MSC_net_241, MSC_net_242, MSC_net_243, 
        MSC_net_244, MSC_net_245, MSC_net_246, MSC_net_247, 
        MSC_net_248, MSC_net_249, MSC_net_250, MSC_net_251, 
        MSC_net_252, MSC_net_253, MSC_net_254, MSC_net_255, 
        MSC_net_256, MSC_net_257, MSC_net_258, MSC_net_259, 
        MSC_net_260, MSC_net_261, MSC_net_262, MSC_net_263, 
        MSC_net_264, MSC_net_265, MSC_net_266, MSC_net_267, 
        MSC_net_268, MSC_net_269 : std_logic;

    for all : mas_pwm_scl_1
	Use entity work.mas_pwm_scl_1(DEF_ARCH);
begin 

    \Vc_o\(17 downto 1) <= (OTHERS => 'U'); 
    Vc_o(17) <= \Vc_o\(0);
    Vc_o(16) <= \Vc_o\(0);
    Vc_o(15) <= \Vc_o\(0);
    Vc_o(14) <= \Vc_o\(0);
    Vc_o(13) <= \Vc_o\(0);
    Vc_o(12) <= \Vc_o\(0);
    Vc_o(11) <= \Vc_o\(0);
    Vc_o(10) <= \Vc_o\(0);
    Vc_o(9) <= \Vc_o\(0);
    Vc_o(8) <= \Vc_o\(0);
    Vc_o(7) <= \Vc_o\(0);
    Vc_o(6) <= \Vc_o\(0);
    Vc_o(5) <= \Vc_o\(0);
    Vc_o(4) <= \Vc_o\(0);
    Vc_o(3) <= \Vc_o\(0);
    Vc_o(2) <= \Vc_o\(0);
    Vc_o(1) <= \Vc_o\(0);
    Vc_o(0) <= \Vc_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
SPLezSBEaTklL/Kn5B9PuhxUq7DnuLlYnMXL1O8jA3q2P1CozQ6VGafL7dWsGbvU
ekSUQsGLjgYpmmck4pB8K6xdf9fYHU2d58MxYIQtyFitSezeUdwNMhpWGjUq/8YE
CnZb/USX9XlDJpi9gpqg6FIzt7q3/EOHg1b5422hBng=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=33780)
`protect data_block
[encoded data, 33216 characters]
O8vToIoH6JCR9jNjb/EF/wrZhgi378hguo0OxfqX3Jo=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity PWM3PH_1 is

    port( reset_i        : in    std_logic;
          sys_clk_i      : in    std_logic;
          en_pwm_i       : in    std_logic;
          en_dual_trig_i : in    std_logic;
          va_i           : in    std_logic_vector(17 downto 0);
          vb_i           : in    std_logic_vector(17 downto 0);
          vc_i           : in    std_logic_vector(17 downto 0);
          pwm_period_i   : in    std_logic_vector(17 downto 0);
          dead_time_i    : in    std_logic_vector(17 downto 0);
          delay_time_i   : in    std_logic_vector(17 downto 0);
          midmatch_o     : out   std_logic;
          PWM_AH_o       : out   std_logic;
          PWM_BH_o       : out   std_logic;
          PWM_CH_o       : out   std_logic;
          PWM_AL_o       : out   std_logic;
          PWM_BL_o       : out   std_logic;
          PWM_CL_o       : out   std_logic
        );

end PWM3PH_1;

architecture DEF_ARCH of PWM3PH_1 is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal MSC_net_117 : std_logic;
    signal s_pwm_counter : std_logic_vector(16 downto 0);
    signal s_delay_counter : std_logic_vector(17 downto 0);
    signal \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4\ : 
        std_logic_vector(17 downto 1);
    signal \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_0_data_tmp\
         : std_logic_vector(8 downto 0);
    signal s_pwm_counter_cry : std_logic_vector(16 downto 0);
    signal s_pwm_counter_s : std_logic_vector(17 downto 0);
    signal s_delay_counter_s : std_logic_vector(17 downto 0);
    signal s_delay_counter_cry : std_logic_vector(16 downto 1);
    signal s_pwm_counter_Z : std_logic_vector(17 to 17);
    signal s_delay_counter_cry_Y : std_logic_vector(16 downto 1);
    signal s_delay_counter_s_FCO : std_logic_vector(17 to 17);
    signal s_delay_counter_s_Y : std_logic_vector(17 to 17);
    signal va_i_i : std_logic_vector(0 to 0);
    signal vb_i_i : std_logic_vector(0 to 0);
    signal s_pwm_counter_cry_Y : std_logic_vector(16 downto 0);
    signal s_pwm_counter_s_FCO : std_logic_vector(17 to 17);
    signal s_pwm_counter_s_Y : std_logic_vector(17 to 17);
    signal MSC_net_288, MSC_net_289, MSC_net_290, MSC_net_291, 
        MSC_net_292, MSC_net_293, MSC_net_294, MSC_net_295, 
        MSC_net_296, MSC_net_297, MSC_net_298, MSC_net_299, 
        MSC_net_300, MSC_net_301, MSC_net_302, MSC_net_303, 
        MSC_net_304, MSC_net_305, MSC_net_306, MSC_net_307, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i\, 
        \PWM_OUTPUT_GEN_PROC.va_i\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2\, 
        \PWM_OUTPUT_GEN_PROC.vb_i\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2\, MSC_net_313, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i\, MSC_net_318, MSC_net_319, 
        MSC_net_320, \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_16_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_16_Z\, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_1\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_2\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_3\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_4\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_5\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_6\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_7\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_8\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_9\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_10\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_11\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_12\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_13\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_14\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_15\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_16\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_16_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_5_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_7_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_13_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_15_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_16_Z\, 
        MSC_net_529, MSC_net_530, MSC_net_531, MSC_net_532, 
        MSC_net_533, MSC_net_534, MSC_net_535, MSC_net_536, 
        MSC_net_537, MSC_net_538, MSC_net_539, MSC_net_540, 
        MSC_net_541, MSC_net_542, MSC_net_543, MSC_net_544, 
        MSC_net_545, MSC_net_546, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_15_Z\, 
        MSC_net_553, MSC_net_554, MSC_net_555, MSC_net_556, 
        MSC_net_557, \PWM_OUTPUT_GEN_PROC.un10_va_i_17\, 
        MSC_net_559, MSC_net_560, MSC_net_561, MSC_net_562, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_RNIIS8A5_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_RNIIS8A5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_RNIV2JH4_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_RNIV2JH4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_RNIP1IO3_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_RNIP1IO3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_RNIR4HV2_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_RNIR4HV2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_RNI5CG62_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_RNI5CG62_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_RNIJ44P1_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_RNIJ44P1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_RNI91OB1_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_RNI91OB1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_RNI72CU_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_RNI72CU_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_RNID70H_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_RNID70H_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_va_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.un10_vb_i_cry_0_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_17_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_17_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_al_o2_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bl_o2_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_s_17_FCO\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_s_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.op_minus.un6_va_i_cry_0_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_16_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_FCO\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_15_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_13_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_11_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_9_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_7_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_Y\, 
        MSC_net_945, MSC_net_946, MSC_net_947, MSC_net_948, 
        MSC_net_949, MSC_net_950, MSC_net_951, MSC_net_952, 
        MSC_net_953, MSC_net_954, MSC_net_955, MSC_net_956, 
        MSC_net_957, MSC_net_958, MSC_net_959, MSC_net_960, 
        MSC_net_961, MSC_net_962, MSC_net_963, MSC_net_964, 
        MSC_net_965, MSC_net_966, MSC_net_967, MSC_net_968
         : std_logic;

begin 

    PWM_CH_o <= MSC_net_117;
    PWM_CL_o <= MSC_net_117;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
oGI3UltQ7WWZa+C/crzAwljYc4Bva4EyFeyeCWkSsyJIKWMjt6S0IoC7eaENB6Yt
IfeH2xcLuYHVW6vZwXfNOIJvUVKrSZbNOE1IsbSIl+US4xNNaJIsCcwe2/0HAvYJ
pLqODvRiMc95hY7z9vzLcYCOUWfI0StcogK1YvRQEQo=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=166620)
`protect data_block
[encoded data, 164032 characters]
bHKTVGCVzWbHJxOrMqUUfQ==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity adc_interface_1 is

    port( apb3_if_st_0_adc_control_reg_val_o  : in    std_logic_vector(5 downto 0);
          adc_interface_0_result_ch0_o        : out   std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch1_o : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch2_o        : out   std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch3_o : out   std_logic_vector(11 downto 0);
          apb3_if_st_0_adc_channel_ch2_o      : in    std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch1_o      : in    std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch3_o      : in    std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch0_o      : in    std_logic_vector(15 downto 0);
          MC_System_0_FIC_0_LOCK              : in    std_logic;
          MC_System_0_FAB_CCC_GL1             : in    std_logic;
          SEQ_CONTROLLER_1_adc_start_o_0      : in    std_logic;
          A1_ADC_SDI_I_c                      : in    std_logic;
          A1_ADC_SDO_O_c                      : out   std_logic;
          A1_ADC_CS_O_c                       : out   std_logic;
          A1_ADC_SCK_O_c                      : out   std_logic;
          adc_interface_0_results_rdy_o       : out   std_logic
        );

end adc_interface_1;

architecture DEF_ARCH of adc_interface_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \A1_ADC_CS_O_c\, \A1_ADC_SCK_O_c\ : std_logic;
    signal s_r_sck_count : std_logic_vector(4 downto 0);
    signal s_channel_cnt : std_logic_vector(2 downto 0);
    signal s_channel_cnt_5 : std_logic_vector(2 downto 0);
    signal s_r_adc_chnls_4_samp : std_logic_vector(2 downto 0);
    signal s_r_sck_sel : std_logic_vector(2 downto 0);
    signal s_r_adc_data : std_logic_vector(15 downto 0);
    signal s_r_adc_data_4 : std_logic_vector(12 downto 0);
    signal s_sdo : std_logic_vector(15 downto 0);
    signal s_sdo_14 : std_logic_vector(15 downto 0);
    signal present_state : std_logic_vector(4 downto 0);
    signal next_state : std_logic_vector(4 to 4);
    signal present_state_ns : std_logic_vector(3 downto 1);
    signal next_state_i_0 : std_logic_vector(4 to 4);
    signal s_r_sck_max_count : std_logic_vector(3 to 3);
    signal s_r_clock_count : std_logic_vector(7 downto 0);
    signal s_r_clock_count_s : std_logic_vector(7 downto 0);
    signal s_r_clock_count_cry : std_logic_vector(6 downto 0);
    signal s_r_clock_count_cry_Y : std_logic_vector(6 downto 0);
    signal s_r_clock_count_s_FCO : std_logic_vector(7 to 7);
    signal s_r_clock_count_s_Y : std_logic_vector(7 to 7);
    signal next_state_0_a3_0_i_0 : std_logic_vector(4 to 4);
    signal s_sdo_14_m2_ns_1 : std_logic_vector(0 to 0);
    signal s_sdo_14_m2 : std_logic_vector(15 downto 0);
    signal present_state_ns_0_a2_1_1 : std_logic_vector(1 to 1);
    signal present_state_ns_0_0 : std_logic_vector(1 to 1);
    signal s_sdo_14_m1 : std_logic_vector(15 downto 1);
    signal s_sdo_14_m3 : std_logic_vector(15 downto 1);
    signal \VCC\, N_1157_i_0, N_36_i_0, \GND\, N_1156_i_0, 
        N_1155_i_0, N_72, N_1158_i_0, s_r_sck_count_0_sqmuxa, 
        N_34_i_0, N_32_i_0, N_30_i_0, result_ch1_o_1_sqmuxa, 
        result_ch0_o_0_sqmuxa, result_ch2_o_1_sqmuxa, 
        result_ch3_o_1_sqmuxa, s_sdo_1_sqmuxa_3_i_0, 
        s_start_sig_ext_Z, un13_s_r_adc_results_ready, 
        s_adc_sdi_Z, N_63_i_0, N_39_i_0, N_173_i_0, 
        s_r_sck_enable_Z, adc_sdo_dly_Z, s_slave_select_2, 
        s_r_sck_Z, s_r_sck_10, N_1159_i_0, 
        s_r_clock_count_s_79_FCO, s_r_clock_count_s_79_S, 
        s_r_clock_count_s_79_Y, N_50, s_r_sck_10_7_am_1_1, 
        s_r_sck_10_7_am, s_r_sck_10_7_bm_1_1, s_r_sck_10_7_bm, 
        s_sdo_3_sqmuxa, s_sdo_14_sm0, un1_s_sdo_2_sqmuxa_0_a2_Z, 
        un22_s_r_sck, un1_s_r_sck, s_channel_cnt_0_sqmuxa_1_Z, 
        result_ch3_o_1_sqmuxa_0_a3_1, un1_s_sdo_1_sqmuxa_1_i_0_Z, 
        N_51, N_52, un1_s_sdo_0_sqmuxa_0_a2_Z, N_45, CO1, CO0, 
        N_120, N_119, N_118, N_117, N_116 : std_logic;

begin 

    A1_ADC_CS_O_c <= \A1_ADC_CS_O_c\;
    A1_ADC_SCK_O_c <= \A1_ADC_SCK_O_c\;

    s_r_sck : SLE
      port map(D => s_r_sck_10, CLK => MC_System_0_FAB_CCC_GL1, 
        EN => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => s_r_sck_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14[2]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(2), B => s_sdo(1), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(2));
    
    s_r_sck_enable : SLE
      port map(D => next_state_i_0(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_enable_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[6]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(6), B => 
        apb3_if_st_0_adc_channel_ch1_o(6), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(6));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[1]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(0), Y => 
        s_r_adc_data_4(1));
    
    \s_r_adc_data[13]\ : SLE
      port map(D => N_34_i_0, CLK => MC_System_0_FAB_CCC_GL1, EN
         => s_r_sck_count_0_sqmuxa, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_r_adc_data(13));
    
    un1_s_sdo_2_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"0002")

      port map(A => s_r_adc_chnls_4_samp(1), B => 
        s_r_adc_chnls_4_samp(2), C => s_channel_cnt(2), D => 
        s_channel_cnt(0), Y => un1_s_sdo_2_sqmuxa_0_a2_Z);
    
    \s_r_adc_data[4]\ : SLE
      port map(D => s_r_adc_data_4(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(4));
    
    s_slave_select : SLE
      port map(D => s_slave_select_2, CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => \A1_ADC_CS_O_c\);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[14]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(14), B => 
        apb3_if_st_0_adc_channel_ch1_o(14), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(14));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[1]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(1), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(1), Y => 
        s_sdo_14_m3(1));
    
    \s_r_adc_chnls_4_samp[0]\ : SLE
      port map(D => apb3_if_st_0_adc_control_reg_val_o(0), CLK
         => MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(0));
    
    \s_r_clock_count[4]\ : SLE
      port map(D => s_r_clock_count_s(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(4));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[10]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(10), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(10), Y => 
        s_sdo_14_m3(10));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[13]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(13), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(13), Y => 
        s_sdo_14_m3(13));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[10]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(10), B => s_sdo(9), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(10));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[7]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(7), B => 
        apb3_if_st_0_adc_channel_ch1_o(7), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(7));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[1]\ : CFG3
      generic map(INIT => x"12")

      port map(A => s_channel_cnt(1), B => present_state(4), C
         => CO0, Y => s_channel_cnt_5(1));
    
    \s_r_clock_count_cry[1]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(1), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(0), S => s_r_clock_count_s(1), Y => 
        s_r_clock_count_cry_Y(1), FCO => s_r_clock_count_cry(1));
    
    \SCK_GEN_PROC.s_r_sck_10_7_bm_1_1\ : CFG4
      generic map(INIT => x"3437")

      port map(A => s_r_clock_count(5), B => s_r_sck_sel(2), C
         => s_r_sck_sel(1), D => s_r_clock_count(1), Y => 
        s_r_sck_10_7_bm_1_1);
    
    \DATA_TRANSMIT_PROC.s_sdo_14[4]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(4), B => s_sdo(3), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(4));
    
    \s_sdo[2]\ : SLE
      port map(D => s_sdo_14(2), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[3]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(3), B => 
        apb3_if_st_0_adc_channel_ch1_o(3), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(3));
    
    s_sdo_1_sqmuxa_3_i : CFG2
      generic map(INIT => x"E")

      port map(A => un1_s_r_sck, B => \A1_ADC_CS_O_c\, Y => 
        s_sdo_1_sqmuxa_3_i_0);
    
    \s_r_clock_count_cry[4]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(4), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(3), S => s_r_clock_count_s(4), Y => 
        s_r_clock_count_cry_Y(4), FCO => s_r_clock_count_cry(4));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[7]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(7), B => s_sdo(6), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[5]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(5), B => s_sdo(4), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(5));
    
    \present_state_ns_0_a2_1_1[1]\ : CFG3
      generic map(INIT => x"02")

      port map(A => SEQ_CONTROLLER_1_adc_start_o_0, B => 
        present_state(1), C => present_state(0), Y => 
        present_state_ns_0_a2_1_1(1));
    
    s_r_sck_count_n3_i_o3 : CFG3
      generic map(INIT => x"7F")

      port map(A => s_r_sck_count(2), B => s_r_sck_count(1), C
         => s_r_sck_count(0), Y => N_51);
    
    \result_ch0_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(4));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[12]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(11), Y => 
        s_r_adc_data_4(12));
    
    \s_r_clock_count_cry[0]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(0), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_s_79_FCO, S => s_r_clock_count_s(0), Y
         => s_r_clock_count_cry_Y(0), FCO => 
        s_r_clock_count_cry(0));
    
    \result_ch1_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(8));
    
    s_r_clock_count_s_79 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \VCC\, B => s_r_sck_enable_Z, C => \GND\, D
         => \GND\, FCI => \VCC\, S => s_r_clock_count_s_79_S, Y
         => s_r_clock_count_s_79_Y, FCO => 
        s_r_clock_count_s_79_FCO);
    
    \SS_GEN_PROC.s_slave_select_2\ : CFG4
      generic map(INIT => x"5557")

      port map(A => s_start_sig_ext_Z, B => s_r_sck_count(4), C
         => s_r_sck_count(0), D => N_52, Y => s_slave_select_2);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[2]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(2), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(2), Y => s_sdo_14_m2(2));
    
    \s_sdo[5]\ : SLE
      port map(D => s_sdo_14(5), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(5));
    
    \result_ch3_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[9]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(9), B => s_sdo(8), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(9));
    
    \s_r_sck_count[0]\ : SLE
      port map(D => N_72, CLK => MC_System_0_FAB_CCC_GL1, EN => 
        N_36_i_0, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(0));
    
    \s_sdo[0]\ : SLE
      port map(D => s_sdo_14(0), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(0));
    
    \s_r_adc_data_RNO[13]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(12), Y => 
        N_34_i_0);
    
    s_r_sck_count_0_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => un1_s_r_sck, B => present_state(1), C => N_50, 
        Y => s_r_sck_count_0_sqmuxa);
    
    s_sdo_3_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"0400")

      port map(A => s_r_adc_chnls_4_samp(2), B => 
        s_r_adc_chnls_4_samp(0), C => s_channel_cnt(2), D => 
        s_r_adc_chnls_4_samp(1), Y => s_sdo_3_sqmuxa);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[11]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(11), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(11), Y => 
        s_sdo_14_m3(11));
    
    s_start_sig_ext : SLE
      port map(D => SEQ_CONTROLLER_1_adc_start_o_0, CLK => 
        MC_System_0_FAB_CCC_GL1, EN => un13_s_r_adc_results_ready, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_start_sig_ext_Z);
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[3]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(2), Y => 
        s_r_adc_data_4(3));
    
    \result_ch2_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[1]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(1), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(1), Y => s_sdo_14_m2(1));
    
    \s_r_adc_data[6]\ : SLE
      port map(D => s_r_adc_data_4(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(6));
    
    \result_ch1_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(6));
    
    un1_s_sdo_1_sqmuxa_1_i_0 : CFG3
      generic map(INIT => x"CD")

      port map(A => s_r_adc_chnls_4_samp(1), B => 
        s_channel_cnt(1), C => s_r_adc_chnls_4_samp(0), Y => 
        un1_s_sdo_1_sqmuxa_1_i_0_Z);
    
    s_adc_sdi : SLE
      port map(D => A1_ADC_SDI_I_c, CLK => 
        MC_System_0_FAB_CCC_GL1, EN => N_63_i_0, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_adc_sdi_Z);
    
    \result_ch1_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(4));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[7]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(7), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(7), Y => s_sdo_14_m2(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[15]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(15), B => 
        apb3_if_st_0_adc_channel_ch1_o(15), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(15));
    
    \START_SIG_PROC.un13_s_r_adc_results_ready_0\ : CFG3
      generic map(INIT => x"CD")

      port map(A => un22_s_r_sck, B => 
        SEQ_CONTROLLER_1_adc_start_o_0, C => 
        next_state_0_a3_0_i_0(4), Y => un13_s_r_adc_results_ready);
    
    s_adc_sdi_RNO : CFG2
      generic map(INIT => x"8")

      port map(A => un1_s_r_sck, B => present_state(1), Y => 
        N_63_i_0);
    
    \s_sdo[1]\ : SLE
      port map(D => s_sdo_14(1), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(1));
    
    \present_state[2]\ : SLE
      port map(D => N_39_i_0, CLK => MC_System_0_FAB_CCC_GL1, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        present_state(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[8]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(8), B => s_sdo(7), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(8));
    
    \s_r_clock_count[5]\ : SLE
      port map(D => s_r_clock_count_s(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(5));
    
    \result_ch3_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(3));
    
    result_ch3_o_1_sqmuxa_0_a3_1_2 : CFG4
      generic map(INIT => x"0001")

      port map(A => s_r_adc_data(15), B => s_r_adc_data(14), C
         => s_r_sck_count(3), D => s_r_sck_count(2), Y => 
        result_ch3_o_1_sqmuxa_0_a3_1);
    
    \s_r_clock_count[2]\ : SLE
      port map(D => s_r_clock_count_s(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[14]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(14), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(14), Y => s_sdo_14_m2(14));
    
    \s_sdo[15]\ : SLE
      port map(D => s_sdo_14(15), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(15));
    
    \s_sdo[12]\ : SLE
      port map(D => s_sdo_14(12), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(12));
    
    \s_r_clock_count[3]\ : SLE
      port map(D => s_r_clock_count_s(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(3));
    
    \s_r_adc_data[14]\ : SLE
      port map(D => N_32_i_0, CLK => MC_System_0_FAB_CCC_GL1, EN
         => s_r_sck_count_0_sqmuxa, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_r_adc_data(14));
    
    results_rdy_o : SLE
      port map(D => N_1159_i_0, CLK => MC_System_0_FAB_CCC_GL1, 
        EN => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_results_rdy_o);
    
    \result_ch2_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(2));
    
    \s_r_sck_count[4]\ : SLE
      port map(D => N_1155_i_0, CLK => MC_System_0_FAB_CCC_GL1, 
        EN => N_36_i_0, ALn => MC_System_0_FIC_0_LOCK, ADn => 
        \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(4));
    
    \result_ch1_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(10));
    
    result_ch3_o_1_sqmuxa_0_o3 : CFG4
      generic map(INIT => x"0180")

      port map(A => s_r_sck_max_count(3), B => s_r_sck_count(4), 
        C => s_r_sck_count(1), D => s_r_sck_count(0), Y => N_45);
    
    \s_r_adc_data[7]\ : SLE
      port map(D => s_r_adc_data_4(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(7));
    
    \result_ch0_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(2));
    
    \present_state_ns_0[3]\ : CFG4
      generic map(INIT => x"EACA")

      port map(A => present_state(1), B => present_state(2), C
         => un1_s_r_sck, D => N_50, Y => present_state_ns(3));
    
    \s_channel_cnt[0]\ : SLE
      port map(D => s_channel_cnt_5(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(0));
    
    result_ch2_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => result_ch3_o_1_sqmuxa_0_a3_1, D => N_45, Y => 
        result_ch2_o_1_sqmuxa);
    
    \result_ch1_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[0]\ : CFG4
      generic map(INIT => x"E400")

      port map(A => un1_s_sdo_0_sqmuxa_0_a2_Z, B => 
        s_sdo_14_m2(0), C => apb3_if_st_0_adc_channel_ch0_o(0), D
         => \A1_ADC_CS_O_c\, Y => s_sdo_14(0));
    
    \s_sdo[11]\ : SLE
      port map(D => s_sdo_14(11), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(11));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[10]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(10), B => 
        apb3_if_st_0_adc_channel_ch1_o(10), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(10));
    
    \s_r_sck_sel[0]\ : SLE
      port map(D => apb3_if_st_0_adc_control_reg_val_o(3), CLK
         => MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[13]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(13), B => 
        apb3_if_st_0_adc_channel_ch1_o(13), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(13));
    
    \s_r_sck_count_RNO[4]\ : CFG4
      generic map(INIT => x"A060")

      port map(A => s_r_sck_count(4), B => s_r_sck_count(3), C
         => present_state(1), D => N_51, Y => N_1155_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14[11]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(11), B => s_sdo(10), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(11));
    
    \s_r_adc_data[15]\ : SLE
      port map(D => N_30_i_0, CLK => MC_System_0_FAB_CCC_GL1, EN
         => s_r_sck_count_0_sqmuxa, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_r_adc_data(15));
    
    results_rdy_o_RNO : CFG2
      generic map(INIT => x"1")

      port map(A => un22_s_r_sck, B => next_state_0_a3_0_i_0(4), 
        Y => N_1159_i_0);
    
    \next_state_0[4]\ : CFG4
      generic map(INIT => x"11F1")

      port map(A => next_state_0_a3_0_i_0(4), B => un22_s_r_sck, 
        C => present_state(4), D => 
        SEQ_CONTROLLER_1_adc_start_o_0, Y => next_state(4));
    
    \s_r_adc_data[5]\ : SLE
      port map(D => s_r_adc_data_4(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(5));
    
    \s_r_adc_data[11]\ : SLE
      port map(D => s_r_adc_data_4(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(11));
    
    \s_r_adc_chnls_4_samp[1]\ : SLE
      port map(D => apb3_if_st_0_adc_control_reg_val_o(1), CLK
         => MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(1));
    
    \s_sdo[9]\ : SLE
      port map(D => s_sdo_14(9), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(9));
    
    \result_ch0_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(1));
    
    \s_r_sck_max_count[3]\ : SLE
      port map(D => \VCC\, CLK => MC_System_0_FAB_CCC_GL1, EN => 
        \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn
         => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_max_count(3));
    
    GND_Z : GND
      port map(Y => \GND\);
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[4]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(3), Y => 
        s_r_adc_data_4(4));
    
    \s_sdo[4]\ : SLE
      port map(D => s_sdo_14(4), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(4));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[2]\ : CFG4
      generic map(INIT => x"006A")

      port map(A => s_channel_cnt(2), B => CO0, C => 
        s_channel_cnt(1), D => present_state(4), Y => 
        s_channel_cnt_5(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2_ns[0]\ : CFG4
      generic map(INIT => x"08F8")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(0), C => s_sdo_14_sm0, D
         => s_sdo_14_m2_ns_1(0), Y => s_sdo_14_m2(0));
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \s_r_sck_sel[2]\ : SLE
      port map(D => apb3_if_st_0_adc_control_reg_val_o(5), CLK
         => MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[12]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(12), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(12), Y => 
        s_sdo_14_m3(12));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[15]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(15), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(15), Y => s_sdo_14_m2(15));
    
    \s_r_adc_data[10]\ : SLE
      port map(D => s_r_adc_data_4(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(10));
    
    \result_ch0_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[9]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(9), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(9), Y => s_sdo_14_m2(9));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[6]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(6), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(6), Y => 
        s_sdo_14_m3(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[3]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(3), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(3), Y => 
        s_sdo_14_m3(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[11]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(11), B => 
        apb3_if_st_0_adc_channel_ch1_o(11), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(11));
    
    \result_ch2_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[5]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(5), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(5), Y => s_sdo_14_m2(5));
    
    \result_ch2_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(10));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[10]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(9), Y => 
        s_r_adc_data_4(10));
    
    \result_ch3_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(4));
    
    result_ch1_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => result_ch3_o_1_sqmuxa_0_a3_1, D => N_45, Y => 
        result_ch1_o_1_sqmuxa);
    
    \DATA_TRANSMIT_PROC.s_sdo_14[13]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(13), B => s_sdo(12), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(13));
    
    \result_ch0_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(9));
    
    \result_ch3_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(6));
    
    sdo_o : SLE
      port map(D => adc_sdo_dly_Z, CLK => MC_System_0_FAB_CCC_GL1, 
        EN => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        A1_ADC_SDO_O_c);
    
    \s_r_clock_count_s[7]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(7), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(6), S => s_r_clock_count_s(7), Y => 
        s_r_clock_count_s_Y(7), FCO => s_r_clock_count_s_FCO(7));
    
    \result_ch1_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(11));
    
    \result_ch0_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(5));
    
    \result_ch0_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(0));
    
    \present_state_RNO[2]\ : CFG3
      generic map(INIT => x"A4")

      port map(A => present_state(3), B => present_state(2), C
         => un1_s_r_sck, Y => N_39_i_0);
    
    s_r_sck_count_n0_i_a2 : CFG2
      generic map(INIT => x"2")

      port map(A => present_state(1), B => s_r_sck_count(0), Y
         => N_72);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[4]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(4), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(4), Y => 
        s_sdo_14_m3(4));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2_ns_1[0]\ : CFG3
      generic map(INIT => x"53")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(0), B => 
        apb3_if_st_0_adc_channel_ch1_o(0), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m2_ns_1(0));
    
    \s_r_adc_data[8]\ : SLE
      port map(D => s_r_adc_data_4(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(8));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[0]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_adc_sdi_Z, Y => 
        s_r_adc_data_4(0));
    
    \s_r_clock_count[6]\ : SLE
      port map(D => s_r_clock_count_s(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(6));
    
    result_ch3_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => result_ch3_o_1_sqmuxa_0_a3_1, D => N_45, Y => 
        result_ch3_o_1_sqmuxa);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[1]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(1), B => 
        apb3_if_st_0_adc_channel_ch1_o(1), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(1));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[2]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(1), Y => 
        s_r_adc_data_4(2));
    
    \present_state[0]\ : SLE
      port map(D => N_173_i_0, CLK => MC_System_0_FAB_CCC_GL1, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        present_state(0));
    
    \result_ch3_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(1));
    
    \result_ch2_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(6));
    
    \s_r_sck_count[3]\ : SLE
      port map(D => N_1156_i_0, CLK => MC_System_0_FAB_CCC_GL1, 
        EN => N_36_i_0, ALn => MC_System_0_FIC_0_LOCK, ADn => 
        \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(3));
    
    \s_r_sck_count[1]\ : SLE
      port map(D => N_1158_i_0, CLK => MC_System_0_FAB_CCC_GL1, 
        EN => N_36_i_0, ALn => MC_System_0_FIC_0_LOCK, ADn => 
        \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(1));
    
    \present_state[3]\ : SLE
      port map(D => present_state_ns(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => present_state(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[10]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(10), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(10), Y => s_sdo_14_m2(10));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[7]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(6), Y => 
        s_r_adc_data_4(7));
    
    \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO2_0_o2\ : CFG4
      generic map(INIT => x"6F06")

      port map(A => s_r_adc_chnls_4_samp(2), B => 
        s_r_adc_chnls_4_samp(1), C => s_channel_cnt(2), D => CO1, 
        Y => un22_s_r_sck);
    
    s_r_sck_count_0_sqmuxa_0_o3 : CFG4
      generic map(INIT => x"5557")

      port map(A => s_r_sck_count(4), B => s_r_sck_count(1), C
         => s_r_sck_count(2), D => s_r_sck_count(3), Y => N_50);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[13]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(13), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(13), Y => s_sdo_14_m2(13));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[14]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(14), B => s_sdo(13), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(14));
    
    \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO1\ : CFG4
      generic map(INIT => x"045D")

      port map(A => s_r_adc_chnls_4_samp(1), B => 
        s_r_adc_chnls_4_samp(0), C => s_channel_cnt(0), D => 
        s_channel_cnt(1), Y => CO1);
    
    \s_r_clock_count_cry[6]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(6), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(5), S => s_r_clock_count_s(6), Y => 
        s_r_clock_count_cry_Y(6), FCO => s_r_clock_count_cry(6));
    
    \s_channel_cnt[2]\ : SLE
      port map(D => s_channel_cnt_5(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(2));
    
    \s_sdo[6]\ : SLE
      port map(D => s_sdo_14(6), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(6));
    
    \s_r_sck_count_RNIV4T02[4]\ : CFG4
      generic map(INIT => x"75F5")

      port map(A => present_state(1), B => s_r_sck_count(4), C
         => un1_s_r_sck, D => N_52, Y => N_36_i_0);
    
    \result_ch0_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(3));
    
    \result_ch0_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(7));
    
    \s_r_adc_data_RNO[15]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(14), Y => 
        N_30_i_0);
    
    \result_ch0_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(6));
    
    \present_state_ns_0[1]\ : CFG4
      generic map(INIT => x"F8F0")

      port map(A => present_state(0), B => un1_s_r_sck, C => 
        present_state_ns_0_0(1), D => un22_s_r_sck, Y => 
        present_state_ns(1));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[9]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(8), Y => 
        s_r_adc_data_4(9));
    
    un1_s_sdo_0_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"0001")

      port map(A => s_channel_cnt(1), B => 
        s_r_adc_chnls_4_samp(2), C => s_channel_cnt(2), D => 
        s_channel_cnt(0), Y => un1_s_sdo_0_sqmuxa_0_a2_Z);
    
    \result_ch3_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(10));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[15]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(15), B => s_sdo(14), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(15));
    
    \present_state[1]\ : SLE
      port map(D => present_state_ns(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => present_state(1));
    
    s_channel_cnt_0_sqmuxa_1 : CFG3
      generic map(INIT => x"20")

      port map(A => s_r_sck_Z, B => \A1_ADC_SCK_O_c\, C => 
        present_state(0), Y => s_channel_cnt_0_sqmuxa_1_Z);
    
    \result_ch3_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[3]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(3), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(3), Y => s_sdo_14_m2(3));
    
    \result_ch2_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(4));
    
    \SCK_GEN_PROC.s_r_sck_10_7_ns\ : CFG3
      generic map(INIT => x"D8")

      port map(A => s_r_sck_sel(0), B => s_r_sck_10_7_bm, C => 
        s_r_sck_10_7_am, Y => s_r_sck_10);
    
    \result_ch2_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(11));
    
    \s_r_sck_count_RNO[3]\ : CFG3
      generic map(INIT => x"84")

      port map(A => s_r_sck_count(3), B => present_state(1), C
         => N_51, Y => N_1156_i_0);
    
    \s_r_clock_count_cry[5]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(5), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(4), S => s_r_clock_count_s(5), Y => 
        s_r_clock_count_cry_Y(5), FCO => s_r_clock_count_cry(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[11]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(11), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(11), Y => s_sdo_14_m2(11));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[5]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(5), B => 
        apb3_if_st_0_adc_channel_ch1_o(5), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(5));
    
    \s_r_sck_count_RNO[2]\ : CFG4
      generic map(INIT => x"6A00")

      port map(A => s_r_sck_count(2), B => s_r_sck_count(1), C
         => s_r_sck_count(0), D => present_state(1), Y => 
        N_1157_i_0);
    
    \s_sdo[13]\ : SLE
      port map(D => s_sdo_14(13), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(13));
    
    \result_ch2_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(0));
    
    \s_sdo[7]\ : SLE
      port map(D => s_sdo_14(7), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[2]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(2), B => 
        apb3_if_st_0_adc_channel_ch1_o(2), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(2));
    
    \next_state_0_a3_0_i_0[4]\ : CFG3
      generic map(INIT => x"DF")

      port map(A => present_state(0), B => s_r_sck_Z, C => 
        \A1_ADC_SCK_O_c\, Y => next_state_0_a3_0_i_0(4));
    
    \result_ch3_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(2));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[11]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(10), Y => 
        s_r_adc_data_4(11));
    
    \result_ch3_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(7));
    
    \result_ch1_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(1));
    
    \SCK_GEN_PROC.s_r_sck_10_7_am_1_1\ : CFG4
      generic map(INIT => x"3437")

      port map(A => s_r_clock_count(4), B => s_r_sck_sel(2), C
         => s_r_sck_sel(1), D => s_r_clock_count(0), Y => 
        s_r_sck_10_7_am_1_1);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[5]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(5), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(5), Y => 
        s_sdo_14_m3(5));
    
    \result_ch1_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(9));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[12]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(12), B => 
        apb3_if_st_0_adc_channel_ch1_o(12), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(12));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[6]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(6), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(6), Y => s_sdo_14_m2(6));
    
    \present_state_RNO[0]\ : CFG4
      generic map(INIT => x"0C2A")

      port map(A => present_state(0), B => present_state(1), C
         => N_50, D => un1_s_r_sck, Y => N_173_i_0);
    
    \result_ch3_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(9));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[14]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(14), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(14), Y => 
        s_sdo_14_m3(14));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[7]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(7), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(7), Y => 
        s_sdo_14_m3(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[12]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(12), B => s_sdo(11), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(12));
    
    \present_state[4]\ : SLE
      port map(D => next_state(4), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \GND\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        present_state(4));
    
    \result_ch0_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(10));
    
    \s_r_adc_data[2]\ : SLE
      port map(D => s_r_adc_data_4(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[1]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(1), B => s_sdo(0), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(1));
    
    \s_r_clock_count_cry[2]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(2), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(1), S => s_r_clock_count_s(2), Y => 
        s_r_clock_count_cry_Y(2), FCO => s_r_clock_count_cry(2));
    
    \s_r_adc_data[12]\ : SLE
      port map(D => s_r_adc_data_4(12), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(12));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[4]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(4), B => 
        apb3_if_st_0_adc_channel_ch1_o(4), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(4));
    
    \s_r_adc_data[1]\ : SLE
      port map(D => s_r_adc_data_4(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(1));
    
    \SCK_GEN_PROC.s_r_sck_10_7_am\ : CFG4
      generic map(INIT => x"B931")

      port map(A => s_r_sck_sel(1), B => s_r_sck_10_7_am_1_1, C
         => s_r_clock_count(6), D => s_r_clock_count(2), Y => 
        s_r_sck_10_7_am);
    
    \s_sdo[10]\ : SLE
      port map(D => s_sdo_14(10), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(10));
    
    result_ch0_o_0_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"1000")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => result_ch3_o_1_sqmuxa_0_a3_1, D => N_45, Y => 
        result_ch0_o_0_sqmuxa);
    
    \result_ch2_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(8));
    
    \ADC_FSM_NS_PROC.un1_s_r_sck\ : CFG2
      generic map(INIT => x"2")

      port map(A => \A1_ADC_SCK_O_c\, B => s_r_sck_Z, Y => 
        un1_s_r_sck);
    
    \s_r_clock_count_cry[3]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(3), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(2), S => s_r_clock_count_s(3), Y => 
        s_r_clock_count_cry_Y(3), FCO => s_r_clock_count_cry(3));
    
    \result_ch3_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(11));
    
    \s_r_sck_count_RNO[1]\ : CFG3
      generic map(INIT => x"60")

      port map(A => s_r_sck_count(1), B => s_r_sck_count(0), C
         => present_state(1), Y => N_1158_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14[3]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(3), B => s_sdo(2), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[9]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(9), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(9), Y => 
        s_sdo_14_m3(9));
    
    \s_r_adc_chnls_4_samp[2]\ : SLE
      port map(D => apb3_if_st_0_adc_control_reg_val_o(2), CLK
         => MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[2]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(2), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(2), Y => 
        s_sdo_14_m3(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2s2\ : CFG4
      generic map(INIT => x"F0F1")

      port map(A => s_channel_cnt(2), B => 
        s_r_adc_chnls_4_samp(2), C => un1_s_sdo_2_sqmuxa_0_a2_Z, 
        D => un1_s_sdo_1_sqmuxa_1_i_0_Z, Y => s_sdo_14_sm0);
    
    \s_sdo[8]\ : SLE
      port map(D => s_sdo_14(8), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(8));
    
    \result_ch1_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(3));
    
    \next_state_0_i[4]\ : CFG4
      generic map(INIT => x"EE0E")

      port map(A => next_state_0_a3_0_i_0(4), B => un22_s_r_sck, 
        C => present_state(4), D => 
        SEQ_CONTROLLER_1_adc_start_o_0, Y => next_state_i_0(4));
    
    \s_r_sck_count_RNITVN11[2]\ : CFG3
      generic map(INIT => x"FE")

      port map(A => s_r_sck_count(3), B => s_r_sck_count(2), C
         => s_r_sck_count(1), Y => N_52);
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[0]\ : CFG4
      generic map(INIT => x"0078")

      port map(A => s_channel_cnt_0_sqmuxa_1_Z, B => un22_s_r_sck, 
        C => s_channel_cnt(0), D => present_state(4), Y => 
        s_channel_cnt_5(0));
    
    \result_ch2_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(9));
    
    \result_ch1_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[4]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(4), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(4), Y => s_sdo_14_m2(4));
    
    \s_r_adc_data[3]\ : SLE
      port map(D => s_r_adc_data_4(3), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14[6]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_m3(6), B => s_sdo(5), C => 
        \A1_ADC_CS_O_c\, Y => s_sdo_14(6));
    
    \SCK_GEN_PROC.s_r_sck_10_7_bm\ : CFG4
      generic map(INIT => x"B931")

      port map(A => s_r_sck_sel(1), B => s_r_sck_10_7_bm_1_1, C
         => s_r_clock_count(7), D => s_r_clock_count(3), Y => 
        s_r_sck_10_7_bm);
    
    \s_sdo[14]\ : SLE
      port map(D => s_sdo_14(14), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(14));
    
    \result_ch2_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[8]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(8), B => 
        apb3_if_st_0_adc_channel_ch1_o(8), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(8));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[6]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(5), Y => 
        s_r_adc_data_4(6));
    
    \result_ch1_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(0));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[5]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(4), Y => 
        s_r_adc_data_4(5));
    
    \s_r_sck_sel[1]\ : SLE
      port map(D => apb3_if_st_0_adc_control_reg_val_o(4), CLK
         => MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(1));
    
    \present_state_ns_0_0[1]\ : CFG4
      generic map(INIT => x"303A")

      port map(A => present_state_ns_0_a2_1_1(1), B => 
        un1_s_r_sck, C => present_state(3), D => present_state(2), 
        Y => present_state_ns_0_0(1));
    
    \s_r_adc_data[0]\ : SLE
      port map(D => s_r_adc_data_4(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(0));
    
    \result_ch3_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch3_o(8));
    
    \s_r_clock_count[1]\ : SLE
      port map(D => s_r_clock_count_s(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(1));
    
    \s_r_clock_count[0]\ : SLE
      port map(D => s_r_clock_count_s(0), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(0));
    
    adc_sdo_dly : SLE
      port map(D => s_sdo(15), CLK => MC_System_0_FAB_CCC_GL1, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        adc_sdo_dly_Z);
    
    s_channel_cnt_0_sqmuxa_1_RNIKES32 : CFG3
      generic map(INIT => x"80")

      port map(A => s_channel_cnt_0_sqmuxa_1_Z, B => un22_s_r_sck, 
        C => s_channel_cnt(0), Y => CO0);
    
    \s_sdo[3]\ : SLE
      port map(D => s_sdo_14(3), CLK => MC_System_0_FAB_CCC_GL1, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[15]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(15), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(15), Y => 
        s_sdo_14_m3(15));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[8]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(7), Y => 
        s_r_adc_data_4(8));
    
    \s_r_adc_data_RNO[14]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A1_ADC_CS_O_c\, B => s_r_adc_data(13), Y => 
        N_32_i_0);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m1[9]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_if_st_0_adc_channel_ch2_o(9), B => 
        apb3_if_st_0_adc_channel_ch1_o(9), C => 
        un1_s_sdo_2_sqmuxa_0_a2_Z, Y => s_sdo_14_m1(9));
    
    \s_r_sck_count[2]\ : SLE
      port map(D => N_1157_i_0, CLK => MC_System_0_FAB_CCC_GL1, 
        EN => N_36_i_0, ALn => MC_System_0_FIC_0_LOCK, ADn => 
        \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(2));
    
    \result_ch2_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[12]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(12), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(12), Y => s_sdo_14_m2(12));
    
    \s_r_adc_data[9]\ : SLE
      port map(D => s_r_adc_data_4(9), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => s_r_sck_count_0_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(9));
    
    \result_ch1_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_measurements_0_adc_result_ch1_o(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m3[8]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => apb3_if_st_0_adc_channel_ch0_o(8), B => 
        un1_s_sdo_0_sqmuxa_0_a2_Z, C => s_sdo_14_m2(8), Y => 
        s_sdo_14_m3(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m2[8]\ : CFG4
      generic map(INIT => x"F808")

      port map(A => s_sdo_3_sqmuxa, B => 
        apb3_if_st_0_adc_channel_ch3_o(8), C => s_sdo_14_sm0, D
         => s_sdo_14_m1(8), Y => s_sdo_14_m2(8));
    
    \s_channel_cnt[1]\ : SLE
      port map(D => s_channel_cnt_5(1), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(1));
    
    \result_ch0_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(11));
    
    \s_r_clock_count[7]\ : SLE
      port map(D => s_r_clock_count_s(7), CLK => 
        MC_System_0_FAB_CCC_GL1, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(7));
    
    sck_o : SLE
      port map(D => s_r_sck_Z, CLK => MC_System_0_FAB_CCC_GL1, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        \A1_ADC_SCK_O_c\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_rot_foc_1 is

    port( s_xo               : out   std_logic_vector(17 downto 0);
          s_yo               : out   std_logic_vector(17 downto 0);
          s_xi_8             : in    std_logic;
          s_xi_9             : in    std_logic;
          s_xi_10            : in    std_logic;
          s_xi_11            : in    std_logic;
          s_xi_12            : in    std_logic;
          s_xi_13            : in    std_logic;
          s_xi_14            : in    std_logic;
          s_xi_15            : in    std_logic;
          s_xi_16            : in    std_logic;
          s_yi               : in    std_logic_vector(16 downto 0);
          theta_i            : in    std_logic_vector(17 downto 0);
          vd_i               : in    std_logic_vector(8 downto 1);
          ialpha_i           : in    std_logic_vector(8 downto 1);
          start_park_i       : in    std_logic;
          start_park_i_i_0   : out   std_logic;
          reset_i            : in    std_logic;
          sys_clk_i          : in    std_logic;
          s_cordic_done      : out   std_logic;
          start_ipark_i      : in    std_logic;
          s_start_cordic_i_0 : out   std_logic
        );

end cordic_rot_foc_1;

architecture DEF_ARCH of cordic_rot_foc_1 is 

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal MSC_net_102 : std_logic;
    signal x_o_5 : std_logic_vector(17 downto 0);
    signal s_index : std_logic_vector(3 downto 0);
    signal s_index_7_iv_i_0 : std_logic_vector(3 downto 1);
    signal y_o_3_1 : std_logic_vector(17 downto 0);
    signal s_theta_c : std_logic_vector(17 downto 0);
    signal s_theta_c_9 : std_logic_vector(17 downto 0);
    signal s_xi_rot : std_logic_vector(17 downto 0);
    signal s_xi_rot_7 : std_logic_vector(17 downto 0);
    signal un1_s_theta_c3_i_0 : std_logic_vector(0 to 0);
    signal s_yi_rot : std_logic_vector(17 downto 1);
    signal s_yi_rot_7 : std_logic_vector(17 downto 0);
    signal s_theta_i : std_logic_vector(17 downto 0);
    signal s_theta : std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(0 to 0);
    signal un1_s_yout : std_logic_vector(17 downto 1);
    signal s_xi : std_logic_vector(7 downto 0);
    signal un1_s_xout : std_logic_vector(17 downto 1);
    signal un4_s_theta_c : std_logic_vector(14 downto 1);
    signal y_o_3 : std_logic_vector(17 downto 1);
    signal s_theta_i_RNI0KP4_FCO : std_logic_vector(17 to 17);
    signal s_theta_i_RNI0KP4_S : std_logic_vector(17 to 17);
    signal s_theta_i_RNI0KP4_Y : std_logic_vector(17 to 17);
    signal s_xi_rot_RNIVHRG_Y : std_logic_vector(0 to 0);
    signal s_xi_rot_RNIVGTS_Y : std_logic_vector(1 to 1);
    signal s_xi_rot_RNI0HV81_Y : std_logic_vector(2 to 2);
    signal s_xi_rot_RNI2I1L1_Y : std_logic_vector(3 to 3);
    signal s_xi_rot_RNI5K312_Y : std_logic_vector(4 to 4);
    signal s_xi_rot_RNI9N5D2_Y : std_logic_vector(5 to 5);
    signal s_xi_rot_RNIER7P2_Y : std_logic_vector(6 to 6);
    signal s_xi_rot_RNIK0A53_Y : std_logic_vector(7 to 7);
    signal s_xi_rot_RNIR6CH3_Y : std_logic_vector(8 to 8);
    signal s_xi_rot_RNI3EET3_Y : std_logic_vector(9 to 9);
    signal s_xi_rot_RNIJ1QH4_Y : std_logic_vector(10 to 10);
    signal s_xi_rot_RNI4M565_Y : std_logic_vector(11 to 11);
    signal s_xi_rot_RNIMBHQ5_Y : std_logic_vector(12 to 12);
    signal s_xi_rot_RNI92TE6_Y : std_logic_vector(13 to 13);
    signal s_xi_rot_RNITP837_Y : std_logic_vector(14 to 14);
    signal s_xi_rot_RNIIIKN7_Y : std_logic_vector(15 to 15);
    signal s_xi_rot_RNIV6C09_FCO : std_logic_vector(17 to 17);
    signal s_xi_rot_RNIV6C09_Y : std_logic_vector(17 to 17);
    signal s_xi_rot_RNI8C0C8_Y : std_logic_vector(16 to 16);
    signal un5_s_yout : std_logic_vector(16 downto 7);
    signal un4_s_theta_c_1 : std_logic_vector(1 to 1);
    signal un6_s_xout : std_logic_vector(16 downto 14);
    signal MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, MSC_net_406, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, MSC_net_433, MSC_net_434, MSC_net_435, 
        MSC_net_436, MSC_net_437, MSC_net_438, MSC_net_439, 
        MSC_net_440, MSC_net_441, MSC_net_442, MSC_net_443, 
        MSC_net_444, MSC_net_445, MSC_net_446, MSC_net_447, 
        MSC_net_448, MSC_net_449, MSC_net_450, MSC_net_451, 
        MSC_net_452, MSC_net_453, MSC_net_454, MSC_net_455, 
        MSC_net_456, MSC_net_457, MSC_net_458, MSC_net_459, 
        MSC_net_460, MSC_net_461, MSC_net_462, MSC_net_463, 
        MSC_net_464, MSC_net_465, MSC_net_466, MSC_net_467, 
        MSC_net_468, MSC_net_469, MSC_net_470, MSC_net_471, 
        MSC_net_472, MSC_net_473, MSC_net_474, MSC_net_475, 
        MSC_net_476, MSC_net_477, MSC_net_478, MSC_net_479, 
        MSC_net_480, MSC_net_481, MSC_net_482, MSC_net_483, 
        MSC_net_484, MSC_net_485, MSC_net_486, MSC_net_487, 
        MSC_net_488, MSC_net_489, MSC_net_490, MSC_net_491, 
        MSC_net_492, MSC_net_493, MSC_net_494, MSC_net_495, 
        MSC_net_496, MSC_net_497, MSC_net_498, MSC_net_499, 
        MSC_net_500, MSC_net_501, MSC_net_502, MSC_net_503, 
        MSC_net_504, MSC_net_505, MSC_net_506, MSC_net_507, 
        MSC_net_508, MSC_net_509, MSC_net_510, MSC_net_511, 
        MSC_net_512, MSC_net_513, MSC_net_514, MSC_net_515, 
        MSC_net_516, MSC_net_517, MSC_net_518, MSC_net_519, 
        MSC_net_520, MSC_net_521, MSC_net_522, MSC_net_523, 
        MSC_net_524, MSC_net_525, MSC_net_526, MSC_net_527, 
        MSC_net_528, MSC_net_529, MSC_net_530, MSC_net_531, 
        MSC_net_532, MSC_net_533, MSC_net_534, MSC_net_535, 
        MSC_net_536, MSC_net_537, MSC_net_538, MSC_net_539, 
        MSC_net_540, MSC_net_541, MSC_net_542, MSC_net_543, 
        MSC_net_544, MSC_net_545, MSC_net_546, MSC_net_547, 
        MSC_net_548, MSC_net_549, MSC_net_550, MSC_net_551, 
        MSC_net_552, MSC_net_553, MSC_net_554, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, MSC_net_591, 
        MSC_net_592, MSC_net_593, MSC_net_594, MSC_net_595, 
        MSC_net_596, MSC_net_597, MSC_net_598, MSC_net_599, 
        MSC_net_600, MSC_net_601, MSC_net_602, MSC_net_603, 
        MSC_net_604, MSC_net_605, MSC_net_606, MSC_net_607, 
        MSC_net_608, MSC_net_609, MSC_net_610, MSC_net_611, 
        MSC_net_612, MSC_net_613, MSC_net_614, MSC_net_615, 
        MSC_net_616, MSC_net_617, MSC_net_618, MSC_net_619, 
        MSC_net_620, MSC_net_621, MSC_net_622, MSC_net_623, 
        MSC_net_624, MSC_net_625, MSC_net_626, MSC_net_627, 
        MSC_net_628, MSC_net_629, MSC_net_630, MSC_net_631, 
        MSC_net_632, MSC_net_633, MSC_net_634, MSC_net_635, 
        MSC_net_636, MSC_net_637, MSC_net_638, MSC_net_639, 
        MSC_net_640, MSC_net_641, MSC_net_642, MSC_net_643, 
        MSC_net_644, MSC_net_645, MSC_net_646, MSC_net_647, 
        MSC_net_648, MSC_net_649, MSC_net_650, MSC_net_651, 
        MSC_net_652, MSC_net_653, MSC_net_654, MSC_net_655, 
        MSC_net_656, MSC_net_657, MSC_net_658, MSC_net_659, 
        MSC_net_660, MSC_net_661, MSC_net_662, MSC_net_663, 
        MSC_net_664, MSC_net_665, MSC_net_666, MSC_net_667, 
        MSC_net_668, MSC_net_669, MSC_net_670, MSC_net_671, 
        MSC_net_672, MSC_net_673, MSC_net_674, MSC_net_675, 
        MSC_net_676, MSC_net_677, MSC_net_678, MSC_net_679, 
        MSC_net_680, MSC_net_681, MSC_net_682, MSC_net_683, 
        MSC_net_684, MSC_net_685, MSC_net_686, MSC_net_687, 
        MSC_net_688, MSC_net_689, MSC_net_690, MSC_net_691, 
        MSC_net_692, MSC_net_693, MSC_net_694, MSC_net_695, 
        MSC_net_696, MSC_net_697, MSC_net_698, MSC_net_699, 
        MSC_net_700, MSC_net_701, MSC_net_702, MSC_net_703, 
        MSC_net_704, MSC_net_705, MSC_net_706, MSC_net_707, 
        MSC_net_708, MSC_net_709, MSC_net_710, MSC_net_711, 
        MSC_net_712, MSC_net_713, MSC_net_714, MSC_net_715, 
        MSC_net_716, MSC_net_717, MSC_net_718, MSC_net_719, 
        MSC_net_720, MSC_net_721, MSC_net_722, MSC_net_723, 
        MSC_net_724, MSC_net_725, MSC_net_726, MSC_net_727, 
        MSC_net_728, MSC_net_729, MSC_net_730, MSC_net_731, 
        MSC_net_732, MSC_net_733, MSC_net_734, MSC_net_735, 
        MSC_net_736, MSC_net_737, MSC_net_738, MSC_net_739, 
        MSC_net_740, MSC_net_741, MSC_net_742, MSC_net_743, 
        MSC_net_744, MSC_net_745, MSC_net_746, MSC_net_747, 
        MSC_net_748, MSC_net_749, MSC_net_750, MSC_net_751, 
        MSC_net_752, MSC_net_753, MSC_net_754, MSC_net_755, 
        MSC_net_756, MSC_net_757, MSC_net_758, MSC_net_759, 
        MSC_net_760, MSC_net_761, MSC_net_762, MSC_net_763, 
        MSC_net_764, MSC_net_765, MSC_net_766, MSC_net_767, 
        MSC_net_768, MSC_net_769, MSC_net_770, MSC_net_771, 
        MSC_net_772, MSC_net_773, MSC_net_774, MSC_net_775, 
        MSC_net_776, MSC_net_777, MSC_net_778, MSC_net_779, 
        MSC_net_780, MSC_net_781, MSC_net_782, MSC_net_783, 
        MSC_net_784, MSC_net_785, MSC_net_786, MSC_net_787, 
        MSC_net_788, MSC_net_789, MSC_net_790, MSC_net_791, 
        MSC_net_792, MSC_net_793, MSC_net_794, MSC_net_795, 
        MSC_net_796, MSC_net_797, MSC_net_798, MSC_net_799, 
        MSC_net_800, MSC_net_801, MSC_net_802, MSC_net_803, 
        MSC_net_804, MSC_net_805, MSC_net_806, MSC_net_807, 
        MSC_net_808, MSC_net_809, MSC_net_810, MSC_net_811, 
        MSC_net_812, MSC_net_813, MSC_net_814, MSC_net_815, 
        MSC_net_816, MSC_net_817, MSC_net_818, MSC_net_819, 
        MSC_net_820, MSC_net_821, MSC_net_822, MSC_net_823, 
        MSC_net_824, MSC_net_825, MSC_net_826, MSC_net_827, 
        MSC_net_828, MSC_net_829, MSC_net_830, MSC_net_831, 
        MSC_net_832 : std_logic;

begin 

    s_start_cordic_i_0 <= MSC_net_102;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
adXYnFyImPQO+aWhTCGgkfCjOwR3Anb/Vj7H9Zf8YgWBChz5VAUAtu9j3qwKFvy0
efV/RMjtzJ06FPOocager6Go/Hf2UzNJGEkIrSrO0Oyvpu6TYkOAKqISXmMcGiN5
X2OSIFrqryYrOguJ6R8R183P3Z2QmW/QZ+5MiiQ23Bs=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=150475)
`protect data_block
[encoded data, 148160 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_scale_1 is

    port( s_xo_scale           : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9);
          s_yo_scale           : out   std_logic_vector(17 downto 0);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 to 1);
          s_yo                 : in    std_logic_vector(17 downto 0);
          s_xo                 : in    std_logic_vector(17 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          s_done_o             : out   std_logic;
          s_mas_en_from_cordic : out   std_logic;
          N_15_i_0             : in    std_logic;
          s_mas_done_from_mas  : in    std_logic;
          s_cordic_done        : in    std_logic
        );

end cordic_scale_1;

architecture DEF_ARCH of cordic_scale_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal s_state : std_logic_vector(1 downto 0);
    signal MSC_net_118, MSC_net_119, MSC_net_120, MSC_net_121, 
        MSC_net_122, MSC_net_123, MSC_net_124, MSC_net_125, 
        MSC_net_126, MSC_net_127, MSC_net_128, MSC_net_129, 
        MSC_net_130, MSC_net_131, MSC_net_132, MSC_net_133, 
        MSC_net_134, MSC_net_135, MSC_net_136, MSC_net_137, 
        MSC_net_138, MSC_net_139, MSC_net_140, MSC_net_141, 
        MSC_net_142, MSC_net_143, MSC_net_144, MSC_net_145, 
        MSC_net_146 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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Brg2ny8tVvGrk650SUKzK68Tk8yoFIIDw19jZWn9RM8=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=25850)
`protect data_block
[encoded data, 25408 characters]
KziW4DetBg6l6RUgDGN5nbsiXRxRr1lpYuS+XbHyvTY=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_scheduler_foc_1 is

    port( iq_o                 : out   std_logic_vector(17 downto 0);
          valpha_o             : out   std_logic_vector(17 downto 0);
          vbeta_o              : out   std_logic_vector(17 downto 0);
          id_o                 : out   std_logic_vector(17 downto 0);
          vq_i                 : in    std_logic_vector(17 downto 1);
          ibeta_i              : in    std_logic_vector(17 downto 1);
          theta_i              : in    std_logic_vector(17 downto 0);
          vd_i                 : in    std_logic_vector(17 downto 1);
          ialpha_i             : in    std_logic_vector(17 downto 1);
          s_product_from_mas   : in    std_logic_vector(26 downto 9);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 to 1);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          s_start_cordic_i_0   : out   std_logic;
          ipark_done_o         : out   std_logic;
          park_done_o          : out   std_logic;
          start_park_i         : in    std_logic;
          start_ipark_i        : in    std_logic;
          s_mas_en_from_cordic : out   std_logic;
          N_15_i_0             : in    std_logic;
          s_mas_done_from_mas  : in    std_logic
        );

end cordic_scheduler_foc_1;

architecture DEF_ARCH of cordic_scheduler_foc_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component cordic_rot_foc_1
    port( s_xo               : out   std_logic_vector(17 downto 0);
          s_yo               : out   std_logic_vector(17 downto 0);
          s_xi_8             : in    std_logic := 'U';
          s_xi_9             : in    std_logic := 'U';
          s_xi_10            : in    std_logic := 'U';
          s_xi_11            : in    std_logic := 'U';
          s_xi_12            : in    std_logic := 'U';
          s_xi_13            : in    std_logic := 'U';
          s_xi_14            : in    std_logic := 'U';
          s_xi_15            : in    std_logic := 'U';
          s_xi_16            : in    std_logic := 'U';
          s_yi               : in    std_logic_vector(16 downto 0) := (others => 'U');
          theta_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          vd_i               : in    std_logic_vector(8 downto 1) := (others => 'U');
          ialpha_i           : in    std_logic_vector(8 downto 1) := (others => 'U');
          start_park_i       : in    std_logic := 'U';
          start_park_i_i_0   : out   std_logic;
          reset_i            : in    std_logic := 'U';
          sys_clk_i          : in    std_logic := 'U';
          s_cordic_done      : out   std_logic;
          start_ipark_i      : in    std_logic := 'U';
          s_start_cordic_i_0 : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component cordic_scale_1
    port( s_xo_scale           : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9) := (others => 'U');
          s_yo_scale           : out   std_logic_vector(17 downto 0);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 to 1) := (others => 'U');
          s_yo                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_xo                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          s_done_o             : out   std_logic;
          s_mas_en_from_cordic : out   std_logic;
          N_15_i_0             : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U';
          s_cordic_done        : in    std_logic := 'U'
        );
  end component;

    signal MSC_net_197 : std_logic;
    signal s_yo_scale : std_logic_vector(17 downto 0);
    signal s_xo_scale : std_logic_vector(17 downto 0);
    signal s_xi : std_logic_vector(16 downto 8);
    signal s_yi : std_logic_vector(16 downto 0);
    signal s_xo : std_logic_vector(17 downto 0);
    signal s_yo : std_logic_vector(17 downto 0);
    signal MSC_net_303, MSC_net_304, MSC_net_305, MSC_net_306, 
        MSC_net_307, MSC_net_308, MSC_net_309, MSC_net_310
         : std_logic;

    for all : cordic_rot_foc_1
	Use entity work.cordic_rot_foc_1(DEF_ARCH);
    for all : cordic_scale_1
	Use entity work.cordic_scale_1(DEF_ARCH);
begin 

    s_start_cordic_i_0 <= MSC_net_197;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=41535)
`protect data_block
[encoded data, 40896 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_scheduler_foc_1 is

    port( s_mas_sel            : out   std_logic_vector(1 to 1);
          s_mul_a_from_cordic  : in    std_logic_vector(17 downto 0);
          s_mul_a_to_mas       : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke  : in    std_logic_vector(1 to 1);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          s_start_cordic_i_0   : in    std_logic;
          s_mas_done_from_mas  : in    std_logic;
          N_15_i_0             : out   std_logic;
          s_mas_en_from_cordic : in    std_logic;
          s_mas_en_to_mas      : out   std_logic;
          N_17_i_0             : out   std_logic;
          N_14_i_0             : out   std_logic
        );

end mas_scheduler_foc_1;

architecture DEF_ARCH of mas_scheduler_foc_1 is 

  component GND
    port( Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \s_mas_sel\ : std_logic_vector(1 to 1);
    signal MSC_net_47, MSC_net_48 : std_logic;

begin 

    s_mas_sel(1) <= \s_mas_sel\(1);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
g5ol+1vC/Qx7IaiYNJvz9X9alaBrc4abZdymSTrGlt9ymZXMuKeg5eEw+JHJnqqe
KNk0XQyAT+vvr/5eRe+mwbQks2WbPhGluN7gza9UDIlemFBJxUTF5xeUtPFFKAis
9sv0uPBaeEzShCULBkwWUZsyx2x7K4ITIKvwTQsU1hM=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=5590)
`protect data_block
[encoded data, 5504 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_foc_1 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_foc_1;

architecture DEF_ARCH of mas_foc_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal product_o_ONC : std_logic_vector(43 downto 29);
    signal MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194, MSC_net_195, 
        MSC_net_196, MSC_net_197, MSC_net_198, MSC_net_199, 
        MSC_net_200, MSC_net_201, MSC_net_202, MSC_net_203, 
        MSC_net_204, MSC_net_205, MSC_net_206, MSC_net_207, 
        MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, MSC_net_213, MSC_net_214, MSC_net_215, 
        MSC_net_216, MSC_net_217, MSC_net_218, MSC_net_219, 
        MSC_net_220, MSC_net_221, MSC_net_222, MSC_net_223, 
        MSC_net_224, MSC_net_225, MSC_net_226, MSC_net_227, 
        MSC_net_228, MSC_net_229, MSC_net_230, MSC_net_231, 
        MSC_net_232, MSC_net_233, MSC_net_234, MSC_net_235, 
        MSC_net_236, MSC_net_237, MSC_net_238, MSC_net_239, 
        MSC_net_240, MSC_net_241, MSC_net_242, MSC_net_243, 
        MSC_net_244, MSC_net_245, MSC_net_246, MSC_net_247, 
        MSC_net_248, MSC_net_249, MSC_net_250 : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(30) <= \product_o\(0);
    product_o(29) <= \product_o\(0);
    product_o(28) <= \product_o\(0);
    product_o(27) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12655)
`protect data_block
[encoded data, 12416 characters]
wDkOBVmTLEKe4nXmeEzSA7ZfugYfzM19+Nd3omhrJJ0=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity clarke_foc_1 is

    port( s_mul_b_from_clarke : out   std_logic_vector(1 to 1);
          reset_i             : in    std_logic;
          sys_clk_i           : in    std_logic
        );

end clarke_foc_1;

architecture DEF_ARCH of clarke_foc_1 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \s_mul_b_from_clarke\ : std_logic_vector(1 to 1);
    signal MSC_net_3, MSC_net_4, MSC_net_5, MSC_net_6, MSC_net_7, 
        MSC_net_8, MSC_net_9, MSC_net_10, MSC_net_11, MSC_net_12, 
        MSC_net_13, MSC_net_14, MSC_net_15, MSC_net_16, 
        MSC_net_17, MSC_net_18, MSC_net_19, MSC_net_20, 
        MSC_net_21, MSC_net_22, MSC_net_23, MSC_net_24, 
        MSC_net_25, MSC_net_26, MSC_net_27, MSC_net_28, 
        MSC_net_29, MSC_net_30, MSC_net_31, MSC_net_32, 
        MSC_net_33, MSC_net_34, MSC_net_35, MSC_net_36, 
        MSC_net_37, MSC_net_38, MSC_net_39, MSC_net_40, 
        MSC_net_41 : std_logic;

begin 

    s_mul_b_from_clarke(1) <= \s_mul_b_from_clarke\(1);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
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`protect data_block
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`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity FOC_TRANSFORMS_1 is

    port( reset_i         : in    std_logic;
          sys_clk_i       : in    std_logic;
          start_clarke_i  : in    std_logic;
          start_park_i    : in    std_logic;
          start_ipark_i   : in    std_logic;
          start_iclarke_i : in    std_logic;
          ia_i            : in    std_logic_vector(17 downto 0);
          ib_i            : in    std_logic_vector(17 downto 0);
          ialpha_i        : in    std_logic_vector(17 downto 0);
          ibeta_i         : in    std_logic_vector(17 downto 0);
          vd_i            : in    std_logic_vector(17 downto 0);
          vq_i            : in    std_logic_vector(17 downto 0);
          valpha_i        : in    std_logic_vector(17 downto 0);
          vbeta_i         : in    std_logic_vector(17 downto 0);
          theta_i         : in    std_logic_vector(17 downto 0);
          clarke_done_o   : out   std_logic;
          park_done_o     : out   std_logic;
          ipark_done_o    : out   std_logic;
          iclarke_done_o  : out   std_logic;
          ialpha_o        : out   std_logic_vector(17 downto 0);
          ibeta_o         : out   std_logic_vector(17 downto 0);
          id_o            : out   std_logic_vector(17 downto 0);
          iq_o            : out   std_logic_vector(17 downto 0);
          valpha_o        : out   std_logic_vector(17 downto 0);
          vbeta_o         : out   std_logic_vector(17 downto 0);
          va_o            : out   std_logic_vector(17 downto 0);
          vb_o            : out   std_logic_vector(17 downto 0);
          vc_o            : out   std_logic_vector(17 downto 0)
        );

end FOC_TRANSFORMS_1;

architecture DEF_ARCH of FOC_TRANSFORMS_1 is 

  component cordic_scheduler_foc_1
    port( iq_o                 : out   std_logic_vector(17 downto 0);
          valpha_o             : out   std_logic_vector(17 downto 0);
          vbeta_o              : out   std_logic_vector(17 downto 0);
          id_o                 : out   std_logic_vector(17 downto 0);
          vq_i                 : in    std_logic_vector(17 downto 1) := (others => 'U');
          ibeta_i              : in    std_logic_vector(17 downto 1) := (others => 'U');
          theta_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          vd_i                 : in    std_logic_vector(17 downto 1) := (others => 'U');
          ialpha_i             : in    std_logic_vector(17 downto 1) := (others => 'U');
          s_product_from_mas   : in    std_logic_vector(26 downto 9) := (others => 'U');
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 to 1) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          s_start_cordic_i_0   : out   std_logic;
          ipark_done_o         : out   std_logic;
          park_done_o          : out   std_logic;
          start_park_i         : in    std_logic := 'U';
          start_ipark_i        : in    std_logic := 'U';
          s_mas_en_from_cordic : out   std_logic;
          N_15_i_0             : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_scheduler_foc_1
    port( s_mas_sel            : out   std_logic_vector(1 to 1);
          s_mul_a_from_cordic  : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_a_to_mas       : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke  : in    std_logic_vector(1 to 1) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          s_start_cordic_i_0   : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U';
          N_15_i_0             : out   std_logic;
          s_mas_en_from_cordic : in    std_logic := 'U';
          s_mas_en_to_mas      : out   std_logic;
          N_17_i_0             : out   std_logic;
          N_14_i_0             : out   std_logic
        );
  end component;

  component mas_foc_1
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component clarke_foc_1
    port( s_mul_b_from_clarke : out   std_logic_vector(1 to 1);
          reset_i             : in    std_logic := 'U';
          sys_clk_i           : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \ialpha_o\ : std_logic_vector(17 downto 0);
    signal s_mul_b_from_clarke : std_logic_vector(1 to 1);
    signal s_mul_a_from_cordic : std_logic_vector(17 downto 0);
    signal s_mul_a_to_mas : std_logic_vector(17 downto 0);
    signal s_product_from_mas : std_logic_vector(26 downto 9);
    signal \MAS_SCHEDULER_INST.s_mas_sel\ : 
        std_logic_vector(1 to 1);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_343, MSC_net_344, MSC_net_345, MSC_net_346, 
        MSC_net_347, MSC_net_348, MSC_net_349, MSC_net_350
         : std_logic;

    for all : cordic_scheduler_foc_1
	Use entity work.cordic_scheduler_foc_1(DEF_ARCH);
    for all : mas_scheduler_foc_1
	Use entity work.mas_scheduler_foc_1(DEF_ARCH);
    for all : mas_foc_1
	Use entity work.mas_foc_1(DEF_ARCH);
    for all : clarke_foc_1
	Use entity work.clarke_foc_1(DEF_ARCH);
begin 

    \ialpha_o\(17 downto 1) <= (OTHERS => 'U'); 
    clarke_done_o <= \ialpha_o\(0);
    iclarke_done_o <= \ialpha_o\(0);
    ialpha_o(17) <= \ialpha_o\(0);
    ialpha_o(16) <= \ialpha_o\(0);
    ialpha_o(15) <= \ialpha_o\(0);
    ialpha_o(14) <= \ialpha_o\(0);
    ialpha_o(13) <= \ialpha_o\(0);
    ialpha_o(12) <= \ialpha_o\(0);
    ialpha_o(11) <= \ialpha_o\(0);
    ialpha_o(10) <= \ialpha_o\(0);
    ialpha_o(9) <= \ialpha_o\(0);
    ialpha_o(8) <= \ialpha_o\(0);
    ialpha_o(7) <= \ialpha_o\(0);
    ialpha_o(6) <= \ialpha_o\(0);
    ialpha_o(5) <= \ialpha_o\(0);
    ialpha_o(4) <= \ialpha_o\(0);
    ialpha_o(3) <= \ialpha_o\(0);
    ialpha_o(2) <= \ialpha_o\(0);
    ialpha_o(1) <= \ialpha_o\(0);
    ialpha_o(0) <= \ialpha_o\(0);
    ibeta_o(17) <= \ialpha_o\(0);
    ibeta_o(16) <= \ialpha_o\(0);
    ibeta_o(15) <= \ialpha_o\(0);
    ibeta_o(14) <= \ialpha_o\(0);
    ibeta_o(13) <= \ialpha_o\(0);
    ibeta_o(12) <= \ialpha_o\(0);
    ibeta_o(11) <= \ialpha_o\(0);
    ibeta_o(10) <= \ialpha_o\(0);
    ibeta_o(9) <= \ialpha_o\(0);
    ibeta_o(8) <= \ialpha_o\(0);
    ibeta_o(7) <= \ialpha_o\(0);
    ibeta_o(6) <= \ialpha_o\(0);
    ibeta_o(5) <= \ialpha_o\(0);
    ibeta_o(4) <= \ialpha_o\(0);
    ibeta_o(3) <= \ialpha_o\(0);
    ibeta_o(2) <= \ialpha_o\(0);
    ibeta_o(1) <= \ialpha_o\(0);
    ibeta_o(0) <= \ialpha_o\(0);
    va_o(17) <= \ialpha_o\(0);
    va_o(16) <= \ialpha_o\(0);
    va_o(15) <= \ialpha_o\(0);
    va_o(14) <= \ialpha_o\(0);
    va_o(13) <= \ialpha_o\(0);
    va_o(12) <= \ialpha_o\(0);
    va_o(11) <= \ialpha_o\(0);
    va_o(10) <= \ialpha_o\(0);
    va_o(9) <= \ialpha_o\(0);
    va_o(8) <= \ialpha_o\(0);
    va_o(7) <= \ialpha_o\(0);
    va_o(6) <= \ialpha_o\(0);
    va_o(5) <= \ialpha_o\(0);
    va_o(4) <= \ialpha_o\(0);
    va_o(3) <= \ialpha_o\(0);
    va_o(2) <= \ialpha_o\(0);
    va_o(1) <= \ialpha_o\(0);
    va_o(0) <= \ialpha_o\(0);
    vb_o(17) <= \ialpha_o\(0);
    vb_o(16) <= \ialpha_o\(0);
    vb_o(15) <= \ialpha_o\(0);
    vb_o(14) <= \ialpha_o\(0);
    vb_o(13) <= \ialpha_o\(0);
    vb_o(12) <= \ialpha_o\(0);
    vb_o(11) <= \ialpha_o\(0);
    vb_o(10) <= \ialpha_o\(0);
    vb_o(9) <= \ialpha_o\(0);
    vb_o(8) <= \ialpha_o\(0);
    vb_o(7) <= \ialpha_o\(0);
    vb_o(6) <= \ialpha_o\(0);
    vb_o(5) <= \ialpha_o\(0);
    vb_o(4) <= \ialpha_o\(0);
    vb_o(3) <= \ialpha_o\(0);
    vb_o(2) <= \ialpha_o\(0);
    vb_o(1) <= \ialpha_o\(0);
    vb_o(0) <= \ialpha_o\(0);
    vc_o(17) <= \ialpha_o\(0);
    vc_o(16) <= \ialpha_o\(0);
    vc_o(15) <= \ialpha_o\(0);
    vc_o(14) <= \ialpha_o\(0);
    vc_o(13) <= \ialpha_o\(0);
    vc_o(12) <= \ialpha_o\(0);
    vc_o(11) <= \ialpha_o\(0);
    vc_o(10) <= \ialpha_o\(0);
    vc_o(9) <= \ialpha_o\(0);
    vc_o(8) <= \ialpha_o\(0);
    vc_o(7) <= \ialpha_o\(0);
    vc_o(6) <= \ialpha_o\(0);
    vc_o(5) <= \ialpha_o\(0);
    vc_o(4) <= \ialpha_o\(0);
    vc_o(3) <= \ialpha_o\(0);
    vc_o(2) <= \ialpha_o\(0);
    vc_o(1) <= \ialpha_o\(0);
    vc_o(0) <= \ialpha_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
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`protect data_block
[encoded data, 19712 characters]
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`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity Stepper_Axis is

    port( STEPPER_THETA_0_theta_output_o_17      : out   std_logic;
          STEPPER_THETA_1_step_count_o_6         : out   std_logic;
          STEPPER_THETA_1_step_count_o_9         : out   std_logic;
          STEPPER_THETA_1_step_count_o_11        : out   std_logic;
          STEPPER_THETA_1_step_count_o_12        : out   std_logic;
          STEPPER_THETA_1_step_count_o_15        : out   std_logic;
          STEPPER_THETA_1_step_count_o_23        : out   std_logic;
          FOC_TRANSFORMS_0_id_o_0                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_5                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_7                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_8                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_9                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_10               : out   std_logic;
          FOC_TRANSFORMS_0_id_o_12               : out   std_logic;
          FOC_TRANSFORMS_0_id_o_15               : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_0                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_1                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_2                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_3                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_5                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_6                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_7                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_8                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_10               : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_11               : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_12               : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_15               : out   std_logic;
          SPEED_ID_IQ_PI_1_id_pi_output_o_0      : out   std_logic;
          SPEED_ID_IQ_PI_1_id_pi_output_o_1      : out   std_logic;
          SPEED_ID_IQ_PI_1_iq_pi_output_o_0      : out   std_logic;
          SPEED_ID_IQ_PI_1_iq_pi_output_o_1      : out   std_logic;
          SEQ_CONTROLLER_1_state_o_0_1           : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_0            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_4            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_5            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_6            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_7            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_8            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_9            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_10           : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_11           : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_0             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_2             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_3             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_5             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_7             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_8             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_10            : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_12            : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_15            : out   std_logic;
          ADC_SCALING_0_ib_adc_o_1               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_4               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_5               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_6               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_8               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_9               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_11              : out   std_logic;
          ADC_SCALING_0_ib_adc_o_12              : out   std_logic;
          ADC_SCALING_0_ib_adc_o_15              : out   std_logic;
          adc_interface_0_result_ch0_o_0         : out   std_logic;
          adc_interface_0_result_ch0_o_5         : out   std_logic;
          adc_interface_0_result_ch0_o_6         : out   std_logic;
          adc_interface_0_result_ch0_o_7         : out   std_logic;
          adc_interface_0_result_ch0_o_8         : out   std_logic;
          adc_interface_0_result_ch0_o_9         : out   std_logic;
          adc_interface_0_result_ch0_o_11        : out   std_logic;
          ADC_SCALING_0_ia_adc_o_1               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_2               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_4               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_5               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_6               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_7               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_8               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_9               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_10              : out   std_logic;
          ADC_SCALING_0_ia_adc_o_11              : out   std_logic;
          ADC_SCALING_0_ia_adc_o_12              : out   std_logic;
          ADC_SCALING_0_ia_adc_o_15              : out   std_logic;
          ADC_SCALING_0_ia_adc_o_0               : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_0  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_1  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_5  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_7  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_8  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_9  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_10 : out   std_logic;
          adc_measurements_0_adc_result_ch3_o_1  : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWDATA        : in    std_logic_vector(23 downto 0);
          prdata_o_1_0_iv_0_12_4                 : out   std_logic_vector(8 to 8);
          prdata_o_1_2_0_a2_17_0                 : in    std_logic_vector(1 to 1);
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI      : out   std_logic_vector(0 to 0);
          prdata_o_1_iv_0_0_a2_45_0              : out   std_logic_vector(0 to 0);
          prdata_o_1_0_iv_0_1                    : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_4_2_1_0              : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_4_2               : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_5_0               : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_a2_26_0              : out   std_logic_vector(1 to 1);
          MC_System_0_AMBA_SLAVE_1_PADDR         : in    std_logic_vector(11 downto 0);
          prdata_o_1_iv_0_0_a2_24_0              : out   std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_a2_6_2_0             : out   std_logic;
          prdata_o_1_0_iv_0_a2_6_2_3             : out   std_logic;
          prdata_o_1_0_iv_0_a2_6_2_5             : out   std_logic;
          prdata_o_1_0_iv_0_a2_20_0              : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_a2_19_0              : out   std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_a2_14_1              : out   std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_0_0_0                : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_0_0_7                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_1                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_5                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_4                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_0_d0             : out   std_logic;
          prdata_o_1_0_iv_0_0_0_2                : out   std_logic;
          prdata_o_1_0_iv_0_1_1                  : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_12_1                 : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_0_2_tz_tz            : out   std_logic_vector(0 to 0);
          prdata_o_1_0_iv_0_3_0                  : out   std_logic;
          prdata_o_1_0_iv_0_3_3                  : out   std_logic;
          prdata_o_1_0_iv_0_1_6_tz               : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_2_tz_0               : out   std_logic;
          prdata_o_1_0_iv_0_2_tz_4               : out   std_logic;
          prdata_o_1_0_iv_0_2_tz_1               : out   std_logic;
          prdata_o_1_iv_0_0_0_3_tz               : out   std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_1_o2_0               : out   std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_0                    : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_11                   : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_5_5                  : out   std_logic;
          prdata_o_1_0_iv_0_5_7                  : out   std_logic;
          prdata_o_1_0_iv_0_5_2                  : out   std_logic;
          prdata_o_1_0_iv_0_5_0                  : out   std_logic;
          prdata_o_1_0_iv_0_5_4                  : out   std_logic;
          prdata_o_1_0_iv_0_5_1                  : out   std_logic;
          prdata_o_1_0_iv_0_5_12                 : out   std_logic;
          prdata_o_1_iv_0_0_12_4_3               : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_6                    : out   std_logic_vector(16 to 16);
          MC_System_0_AMBA_SLAVE_1_PRDATA        : out   std_logic_vector(14 downto 13);
          MC_System_0_FIC_0_LOCK                 : in    std_logic;
          MC_System_0_FAB_CCC_GL1                : in    std_logic;
          A1_PWM_WL_O_c                          : out   std_logic;
          A1_PWM_UH_O_c                          : out   std_logic;
          A1_PWM_VH_O_c                          : out   std_logic;
          A1_PWM_UL_O_c                          : out   std_logic;
          A1_PWM_VL_O_c                          : out   std_logic;
          A1_ADC_SDI_I_c                         : in    std_logic;
          A1_ADC_SDO_O_c                         : out   std_logic;
          A1_ADC_CS_O_c                          : out   std_logic;
          A1_ADC_SCK_O_c                         : out   std_logic;
          N_503                                  : out   std_logic;
          N_500                                  : out   std_logic;
          N_505                                  : out   std_logic;
          N_240                                  : in    std_logic;
          N_514                                  : out   std_logic;
          N_507                                  : out   std_logic;
          N_509                                  : out   std_logic;
          N_506                                  : out   std_logic;
          N_522                                  : out   std_logic;
          N_542                                  : out   std_logic;
          N_516                                  : out   std_logic;
          N_502                                  : in    std_logic;
          prdata_m2_e_0                          : out   std_logic;
          N_519                                  : out   std_logic;
          N_540                                  : out   std_logic;
          N_544                                  : out   std_logic;
          N_517                                  : out   std_logic;
          N_128                                  : out   std_logic;
          m20_m2_0_a2_1                          : out   std_logic;
          prdata_m1_e_11_0                       : out   std_logic;
          prdata_m1_0_a2_2_0                     : out   std_logic;
          N_513                                  : out   std_logic;
          prdata_m3_i_0                          : out   std_logic;
          prdata_m2_0_a2_0                       : out   std_logic;
          prdata_m2_e_0_0                        : out   std_logic;
          m20_i_a2_5_0                           : out   std_logic;
          prdata_m1_0_a2_0                       : out   std_logic;
          m20_i_a2_0_1                           : out   std_logic;
          prdata_m4_e_0                          : out   std_logic;
          N_518                                  : out   std_logic;
          N_533                                  : out   std_logic;
          N_397                                  : out   std_logic;
          N_355                                  : out   std_logic;
          N_531                                  : out   std_logic;
          N_527                                  : out   std_logic;
          N_529                                  : out   std_logic;
          N_508                                  : out   std_logic;
          m20_i_2_tz                             : out   std_logic;
          N_494                                  : out   std_logic;
          N_454                                  : out   std_logic;
          N_414                                  : out   std_logic;
          N_198                                  : out   std_logic;
          m20_i_11_5                             : out   std_logic;
          prdata_N_7_2                           : out   std_logic;
          N_349                                  : out   std_logic;
          N_534                                  : out   std_logic;
          N_260                                  : out   std_logic;
          N_363                                  : out   std_logic;
          N_377                                  : out   std_logic;
          N_405                                  : out   std_logic;
          N_455                                  : out   std_logic;
          N_495                                  : out   std_logic;
          N_524                                  : out   std_logic;
          N_528                                  : out   std_logic;
          m20_i_10_1                             : out   std_logic;
          m20_i_10_0                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE        : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx         : in    std_logic;
          MC_System_0_AMBA_SLAVE_1_PENABLE       : in    std_logic;
          N_215                                  : out   std_logic;
          N_315                                  : out   std_logic;
          N_317                                  : out   std_logic;
          N_318                                  : out   std_logic;
          N_319                                  : out   std_logic;
          N_320                                  : out   std_logic;
          N_321                                  : out   std_logic;
          N_354                                  : out   std_logic;
          N_396                                  : out   std_logic;
          N_122                                  : out   std_logic;
          N_549                                  : in    std_logic
        );

end Stepper_Axis;

architecture DEF_ARCH of Stepper_Axis is 

  component GND
    port( Y : out   std_logic
        );
  end component;

  component apb3_if_st
    port( apb3_if_st_0_adc_oc_thresh_o           : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_adc_scale_val_o           : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_id_ref_val_o              : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_idq_pi_ki_o               : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_idq_pi_kp_o               : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_pwm_dead_time_val_o       : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_pwm_delay_time_val_o      : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_pwm_period_val_o          : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_sqmng_dv_o                : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_theta_gen_rate_limit_o    : out   std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_1_PWDATA        : in    std_logic_vector(23 downto 0) := (others => 'U');
          apb3_if_st_0_theta_gen_slew_count_o    : out   std_logic_vector(17 downto 0);
          apb3_if_st_0_theta_gen_cmd_step_no_o_0 : out   std_logic_vector(23 downto 0);
          apb3_if_st_0_adc_control_reg_val_o     : out   std_logic_vector(5 downto 0);
          apb3_if_st_0_seq_cntl_config_o         : out   std_logic_vector(2 downto 1);
          apb3_if_st_0_adc_channel_ch0_o         : out   std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch1_o         : out   std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch2_o         : out   std_logic_vector(15 downto 0);
          apb3_if_st_0_adc_channel_ch3_o         : out   std_logic_vector(15 downto 0);
          prdata_o_1_0_iv_0_12_4                 : out   std_logic_vector(8 to 8);
          prdata_o_1_2_0_a2_17_0                 : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI      : out   std_logic_vector(0 to 0);
          prdata_o_1_iv_0_0_a2_45_0              : out   std_logic_vector(0 to 0);
          prdata_o_1_0_iv_0_1_0                  : out   std_logic;
          prdata_o_1_iv_0_0_4_2_1_0              : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_4_2               : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_5_0               : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_a2_26_0              : out   std_logic_vector(1 to 1);
          MC_System_0_AMBA_SLAVE_1_PADDR         : in    std_logic_vector(11 downto 0) := (others => 'U');
          prdata_o_1_iv_0_0_a2_24_0              : out   std_logic_vector(1 to 1);
          FOC_TRANSFORMS_0_vbeta_o_16            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_15            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_10            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_12            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_5             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_0             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_13            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_8             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_3             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_2             : out   std_logic;
          prdata_o_1_0_iv_0_a2_6_2_5             : out   std_logic;
          prdata_o_1_0_iv_0_a2_6_2_7             : out   std_logic;
          prdata_o_1_0_iv_0_a2_20_0              : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_a2_19_0              : out   std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_a2_14_1              : out   std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_0_0_0                : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_0_0_7                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_1                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_5                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_4                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_0_d0             : out   std_logic;
          prdata_o_1_0_iv_0_0_0_2                : out   std_logic;
          prdata_o_1_0_iv_0_1_1                  : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_12_1                 : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_0_2_tz_tz            : out   std_logic_vector(0 to 0);
          prdata_o_1_0_iv_0_3_0                  : out   std_logic;
          prdata_o_1_0_iv_0_3_3                  : out   std_logic;
          adc_measurements_0_adc_result_ch3_o_2  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_11 : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_5  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_9  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_8  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_4  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_10 : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_6  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_0  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_7  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch3_o_3  : in    std_logic := 'U';
          SEQ_CONTROLLER_1_state_o_0_3           : in    std_logic := 'U';
          SEQ_CONTROLLER_1_state_o_0_0           : in    std_logic := 'U';
          SEQ_CONTROLLER_1_state_o_0_2           : in    std_logic := 'U';
          SPEED_ID_IQ_PI_1_id_pi_output_o        : in    std_logic_vector(17 downto 2) := (others => 'U');
          SPEED_ID_IQ_PI_1_iq_pi_output_o        : in    std_logic_vector(17 downto 2) := (others => 'U');
          prdata_o_1_0_iv_0_1_6_tz               : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_2_tz_0               : out   std_logic;
          prdata_o_1_0_iv_0_2_tz_4               : out   std_logic;
          prdata_o_1_0_iv_0_2_tz_1               : out   std_logic;
          prdata_o_1_iv_0_0_0_3_tz               : out   std_logic_vector(1 to 1);
          STEPPER_THETA_0_theta_output_o         : in    std_logic_vector(17 downto 0) := (others => 'U');
          FOC_TRANSFORMS_1_valpha_o_16           : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_0            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_2            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_11           : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_14           : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_15           : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_13           : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_12           : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_1            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_1_o2_0               : out   std_logic_vector(17 to 17);
          adc_interface_0_result_ch2_o           : in    std_logic_vector(11 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_0_0_d0               : out   std_logic;
          adc_interface_0_result_ch0_o_3         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_1         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_9         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_2         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_0         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_7         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_0         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_4         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_2         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_10        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_8         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_5         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_3         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_1         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_13        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_16        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_14        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_17        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_22        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_21        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_20        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_19        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_18        : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_2  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_1  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_0  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_9  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_4  : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11                   : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_5_5                  : out   std_logic;
          prdata_o_1_0_iv_0_5_7                  : out   std_logic;
          prdata_o_1_0_iv_0_5_2                  : out   std_logic;
          prdata_o_1_0_iv_0_5_0                  : out   std_logic;
          prdata_o_1_0_iv_0_5_4                  : out   std_logic;
          prdata_o_1_0_iv_0_5_1                  : out   std_logic;
          prdata_o_1_0_iv_0_5_12                 : out   std_logic;
          ADC_SCALING_0_ib_adc_o_13              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_17              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_2               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_10              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_7               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_3               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_0               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_16              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_14              : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_4_3               : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_6_3                  : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_13               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_5                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_0                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_9                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_12               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_10               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_16               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_2                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_0                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_10               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_3                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_5                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_15               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_13               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_1                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_12               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_0               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_10              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_14              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_13              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_11              : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PRDATA        : out   std_logic_vector(14 downto 13);
          MC_System_0_FIC_0_LOCK                 : in    std_logic := 'U';
          MC_System_0_FAB_CCC_GL1                : in    std_logic := 'U';
          apb3_if_st_0_theta_gen_mode_o          : out   std_logic;
          apb3_if_st_0_stop_motor_o              : out   std_logic;
          apb3_if_st_0_start_motor_o             : out   std_logic;
          N_503                                  : out   std_logic;
          N_500                                  : out   std_logic;
          N_505                                  : out   std_logic;
          N_240                                  : in    std_logic := 'U';
          N_514                                  : out   std_logic;
          N_507                                  : out   std_logic;
          N_509                                  : out   std_logic;
          N_506                                  : out   std_logic;
          N_522                                  : out   std_logic;
          N_542                                  : out   std_logic;
          N_516                                  : out   std_logic;
          N_502                                  : in    std_logic := 'U';
          prdata_m2_e_0                          : out   std_logic;
          N_519                                  : out   std_logic;
          N_540                                  : out   std_logic;
          N_544                                  : out   std_logic;
          N_517                                  : out   std_logic;
          N_128                                  : out   std_logic;
          m20_m2_0_a2_1                          : out   std_logic;
          prdata_m1_e_11_0                       : out   std_logic;
          prdata_m1_0_a2_2_0                     : out   std_logic;
          N_513                                  : out   std_logic;
          prdata_m3_i_0                          : out   std_logic;
          prdata_m2_0_a2_0                       : out   std_logic;
          prdata_m2_e_0_0                        : out   std_logic;
          m20_i_a2_5_0                           : out   std_logic;
          prdata_m1_0_a2_0                       : out   std_logic;
          m20_i_a2_0_1                           : out   std_logic;
          prdata_m4_e_0                          : out   std_logic;
          N_518                                  : out   std_logic;
          N_533                                  : out   std_logic;
          N_397                                  : out   std_logic;
          N_355                                  : out   std_logic;
          N_531                                  : out   std_logic;
          N_527                                  : out   std_logic;
          N_529                                  : out   std_logic;
          N_508                                  : out   std_logic;
          m20_i_2_tz                             : out   std_logic;
          N_494                                  : out   std_logic;
          N_454                                  : out   std_logic;
          N_414                                  : out   std_logic;
          N_198                                  : out   std_logic;
          m20_i_11_5                             : out   std_logic;
          prdata_N_7_2                           : out   std_logic;
          N_349                                  : out   std_logic;
          N_534                                  : out   std_logic;
          N_260                                  : out   std_logic;
          N_363                                  : out   std_logic;
          N_377                                  : out   std_logic;
          N_405                                  : out   std_logic;
          N_455                                  : out   std_logic;
          N_495                                  : out   std_logic;
          N_524                                  : out   std_logic;
          N_528                                  : out   std_logic;
          m20_i_10_1                             : out   std_logic;
          m20_i_10_0                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE        : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PSELx         : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PENABLE       : in    std_logic := 'U';
          N_215                                  : out   std_logic;
          N_315                                  : out   std_logic;
          N_317                                  : out   std_logic;
          N_318                                  : out   std_logic;
          N_319                                  : out   std_logic;
          N_320                                  : out   std_logic;
          N_321                                  : out   std_logic;
          N_354                                  : out   std_logic;
          N_396                                  : out   std_logic;
          N_122                                  : out   std_logic;
          N_549                                  : in    std_logic := 'U'
        );
  end component;

  component ADC_SCALING_1
    port( reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          adc_results_rdy_i    : in    std_logic := 'U';
          adc_scale_val_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          adc_result_ch0_i     : in    std_logic_vector(11 downto 0) := (others => 'U');
          adc_result_ch1_i     : in    std_logic_vector(11 downto 0) := (others => 'U');
          fault_threshold_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          done_o               : out   std_logic;
          calib_done_o         : out   std_logic;
          over_current_fault_o : out   std_logic;
          ia_adc_o             : out   std_logic_vector(17 downto 0);
          ib_adc_o             : out   std_logic_vector(17 downto 0)
        );
  end component;

  component SPEED_ID_IQ_PI_1
    port( reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          clear_buffer_i       : in    std_logic := 'U';
          speed_en_i           : in    std_logic := 'U';
          idq_en_i             : in    std_logic := 'U';
          speed_pi_start_i     : in    std_logic := 'U';
          id_pi_start_i        : in    std_logic := 'U';
          iq_pi_start_i        : in    std_logic := 'U';
          speed_init_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_init_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_init_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ref_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ymax_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ymin_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_ref_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_act_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_kp_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_ki_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          idq_pi_ymax_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          idq_pi_ymin_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_ref_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_done_o      : out   std_logic;
          id_pi_done_o         : out   std_logic;
          iq_pi_done_o         : out   std_logic;
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0)
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component STEPPER_THETA
    port( reset_i        : in    std_logic := 'U';
          sys_clk_i      : in    std_logic := 'U';
          enable_i       : in    std_logic := 'U';
          mode_i         : in    std_logic := 'U';
          clear_buffer_i : in    std_logic := 'U';
          slew_cnt_i     : in    std_logic_vector(17 downto 0) := (others => 'U');
          rate_limit_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          cmd_step_no_i  : in    std_logic_vector(23 downto 0) := (others => 'U');
          theta_output_o : out   std_logic_vector(17 downto 0);
          step_count_o   : out   std_logic_vector(23 downto 0)
        );
  end component;

  component SEQ_CONTROLLER_1
    port( reset_i         : in    std_logic := 'U';
          sys_clk_i       : in    std_logic := 'U';
          fault_i         : in    std_logic := 'U';
          start_motor_i   : in    std_logic := 'U';
          stop_motor_i    : in    std_logic := 'U';
          fault_clear_i   : in    std_logic := 'U';
          speed_ref_i     : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_cl_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          vq_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          max_ar_i        : in    std_logic_vector(3 downto 0) := (others => 'U');
          calib_done_i    : in    std_logic := 'U';
          pwm_midmatch_i  : in    std_logic := 'U';
          foc_done_i      : in    std_logic := 'U';
          config_reg_i    : in    std_logic_vector(3 downto 0) := (others => 'U');
          adc_start_o     : out   std_logic;
          cl_status_o     : out   std_logic;
          en_idq_pi_o     : out   std_logic;
          en_pwm_o        : out   std_logic;
          motor_stopped_o : out   std_logic;
          reset_rl_o      : out   std_logic;
          soft_stop_o     : out   std_logic;
          sensor_reset_o  : out   std_logic;
          state_o         : out   std_logic_vector(3 downto 0)
        );
  end component;

  component PWM_SCALING_1
    port( reset_i      : in    std_logic := 'U';
          sys_clk_i    : in    std_logic := 'U';
          start_i      : in    std_logic := 'U';
          va_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vb_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vc_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_period_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_gain_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          Va_o         : out   std_logic_vector(17 downto 0);
          Vb_o         : out   std_logic_vector(17 downto 0);
          Vc_o         : out   std_logic_vector(17 downto 0);
          done_o       : out   std_logic
        );
  end component;

  component PWM3PH_1
    port( reset_i        : in    std_logic := 'U';
          sys_clk_i      : in    std_logic := 'U';
          en_pwm_i       : in    std_logic := 'U';
          en_dual_trig_i : in    std_logic := 'U';
          va_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          vb_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          vc_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_period_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          dead_time_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          delay_time_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          midmatch_o     : out   std_logic;
          PWM_AH_o       : out   std_logic;
          PWM_BH_o       : out   std_logic;
          PWM_CH_o       : out   std_logic;
          PWM_AL_o       : out   std_logic;
          PWM_BL_o       : out   std_logic;
          PWM_CL_o       : out   std_logic
        );
  end component;

  component adc_interface_1
    port( apb3_if_st_0_adc_control_reg_val_o  : in    std_logic_vector(5 downto 0) := (others => 'U');
          adc_interface_0_result_ch0_o        : out   std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch1_o : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch2_o        : out   std_logic_vector(11 downto 0);
          adc_measurements_0_adc_result_ch3_o : out   std_logic_vector(11 downto 0);
          apb3_if_st_0_adc_channel_ch2_o      : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_if_st_0_adc_channel_ch1_o      : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_if_st_0_adc_channel_ch3_o      : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_if_st_0_adc_channel_ch0_o      : in    std_logic_vector(15 downto 0) := (others => 'U');
          MC_System_0_FIC_0_LOCK              : in    std_logic := 'U';
          MC_System_0_FAB_CCC_GL1             : in    std_logic := 'U';
          SEQ_CONTROLLER_1_adc_start_o_0      : in    std_logic := 'U';
          A1_ADC_SDI_I_c                      : in    std_logic := 'U';
          A1_ADC_SDO_O_c                      : out   std_logic;
          A1_ADC_CS_O_c                       : out   std_logic;
          A1_ADC_SCK_O_c                      : out   std_logic;
          adc_interface_0_results_rdy_o       : out   std_logic
        );
  end component;

  component FOC_TRANSFORMS_1
    port( reset_i         : in    std_logic := 'U';
          sys_clk_i       : in    std_logic := 'U';
          start_clarke_i  : in    std_logic := 'U';
          start_park_i    : in    std_logic := 'U';
          start_ipark_i   : in    std_logic := 'U';
          start_iclarke_i : in    std_logic := 'U';
          ia_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          ib_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          ialpha_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          ibeta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vd_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          vq_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          valpha_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          vbeta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          theta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          clarke_done_o   : out   std_logic;
          park_done_o     : out   std_logic;
          ipark_done_o    : out   std_logic;
          iclarke_done_o  : out   std_logic;
          ialpha_o        : out   std_logic_vector(17 downto 0);
          ibeta_o         : out   std_logic_vector(17 downto 0);
          id_o            : out   std_logic_vector(17 downto 0);
          iq_o            : out   std_logic_vector(17 downto 0);
          valpha_o        : out   std_logic_vector(17 downto 0);
          vbeta_o         : out   std_logic_vector(17 downto 0);
          va_o            : out   std_logic_vector(17 downto 0);
          vb_o            : out   std_logic_vector(17 downto 0);
          vc_o            : out   std_logic_vector(17 downto 0)
        );
  end component;

    signal \STEPPER_THETA_0_theta_output_o_17\, 
        \FOC_TRANSFORMS_0_id_o_0\, \FOC_TRANSFORMS_0_id_o_5\, 
        \FOC_TRANSFORMS_0_id_o_7\, \FOC_TRANSFORMS_0_id_o_8\, 
        \FOC_TRANSFORMS_0_id_o_9\, \FOC_TRANSFORMS_0_id_o_10\, 
        \FOC_TRANSFORMS_0_id_o_12\, \FOC_TRANSFORMS_0_id_o_15\, 
        \FOC_TRANSFORMS_0_iq_o_0\, \FOC_TRANSFORMS_0_iq_o_1\, 
        \FOC_TRANSFORMS_0_iq_o_2\, \FOC_TRANSFORMS_0_iq_o_3\, 
        \FOC_TRANSFORMS_0_iq_o_5\, \FOC_TRANSFORMS_0_iq_o_6\, 
        \FOC_TRANSFORMS_0_iq_o_7\, \FOC_TRANSFORMS_0_iq_o_8\, 
        \FOC_TRANSFORMS_0_iq_o_10\, \FOC_TRANSFORMS_0_iq_o_11\, 
        \FOC_TRANSFORMS_0_iq_o_12\, \FOC_TRANSFORMS_0_iq_o_15\, 
        \SPEED_ID_IQ_PI_1_id_pi_output_o_1\, 
        \SPEED_ID_IQ_PI_1_iq_pi_output_o_1\, 
        \FOC_TRANSFORMS_1_valpha_o_0\, 
        \FOC_TRANSFORMS_1_valpha_o_4\, 
        \FOC_TRANSFORMS_1_valpha_o_5\, 
        \FOC_TRANSFORMS_1_valpha_o_6\, 
        \FOC_TRANSFORMS_1_valpha_o_7\, 
        \FOC_TRANSFORMS_1_valpha_o_8\, 
        \FOC_TRANSFORMS_1_valpha_o_9\, 
        \FOC_TRANSFORMS_1_valpha_o_10\, 
        \FOC_TRANSFORMS_1_valpha_o_11\, 
        \FOC_TRANSFORMS_0_vbeta_o_0\, 
        \FOC_TRANSFORMS_0_vbeta_o_2\, 
        \FOC_TRANSFORMS_0_vbeta_o_3\, 
        \FOC_TRANSFORMS_0_vbeta_o_5\, 
        \FOC_TRANSFORMS_0_vbeta_o_7\, 
        \FOC_TRANSFORMS_0_vbeta_o_8\, 
        \FOC_TRANSFORMS_0_vbeta_o_10\, 
        \FOC_TRANSFORMS_0_vbeta_o_12\, 
        \FOC_TRANSFORMS_0_vbeta_o_15\, \ADC_SCALING_0_ib_adc_o_1\, 
        \ADC_SCALING_0_ib_adc_o_4\, \ADC_SCALING_0_ib_adc_o_5\, 
        \ADC_SCALING_0_ib_adc_o_6\, \ADC_SCALING_0_ib_adc_o_8\, 
        \ADC_SCALING_0_ib_adc_o_9\, \ADC_SCALING_0_ib_adc_o_11\, 
        \ADC_SCALING_0_ib_adc_o_12\, \ADC_SCALING_0_ib_adc_o_15\, 
        \adc_interface_0_result_ch0_o_0\, 
        \adc_interface_0_result_ch0_o_5\, 
        \adc_interface_0_result_ch0_o_6\, 
        \adc_interface_0_result_ch0_o_7\, 
        \adc_interface_0_result_ch0_o_8\, 
        \adc_interface_0_result_ch0_o_9\, 
        \adc_interface_0_result_ch0_o_11\, 
        \ADC_SCALING_0_ia_adc_o_1\, \ADC_SCALING_0_ia_adc_o_2\, 
        \ADC_SCALING_0_ia_adc_o_4\, \ADC_SCALING_0_ia_adc_o_5\, 
        \ADC_SCALING_0_ia_adc_o_6\, \ADC_SCALING_0_ia_adc_o_7\, 
        \ADC_SCALING_0_ia_adc_o_8\, \ADC_SCALING_0_ia_adc_o_9\, 
        \ADC_SCALING_0_ia_adc_o_10\, \ADC_SCALING_0_ia_adc_o_11\, 
        \ADC_SCALING_0_ia_adc_o_12\, \ADC_SCALING_0_ia_adc_o_15\, 
        \A1_PWM_WL_O_c\ : std_logic;
    signal apb3_if_st_0_theta_gen_slew_count_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_st_0_theta_gen_rate_limit_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_st_0_theta_gen_cmd_step_no_o_0 : 
        std_logic_vector(23 downto 0);
    signal STEPPER_THETA_0_theta_output_o : 
        std_logic_vector(16 downto 0);
    signal STEPPER_THETA_1_step_count_o : 
        std_logic_vector(22 downto 0);
    signal apb3_if_st_0_sqmng_dv_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_st_0_id_ref_val_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_id_o : std_logic_vector(17 downto 1);
    signal apb3_if_st_0_idq_pi_kp_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_st_0_idq_pi_ki_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_iq_o : std_logic_vector(17 downto 4);
    signal speed_pi_output_o : std_logic_vector(17 downto 0);
    signal SPEED_ID_IQ_PI_1_id_pi_output_o : 
        std_logic_vector(17 downto 2);
    signal SPEED_ID_IQ_PI_1_iq_pi_output_o : 
        std_logic_vector(17 downto 2);
    signal apb3_if_st_0_seq_cntl_config_o : 
        std_logic_vector(2 downto 1);
    signal SEQ_CONTROLLER_1_state_o_0 : 
        std_logic_vector(3 downto 0);
    signal FOC_TRANSFORMS_1_valpha_o : 
        std_logic_vector(17 downto 1);
    signal FOC_TRANSFORMS_0_vbeta_o : 
        std_logic_vector(17 downto 1);
    signal apb3_if_st_0_pwm_period_val_o : 
        std_logic_vector(17 downto 0);
    signal PWM_SCALING_0_Va_o : std_logic_vector(17 downto 0);
    signal PWM_SCALING_0_Vb_o : std_logic_vector(17 downto 0);
    signal Vc_o : std_logic_vector(17 downto 0);
    signal apb3_if_st_0_pwm_dead_time_val_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_st_0_pwm_delay_time_val_o : 
        std_logic_vector(17 downto 0);
    signal ADC_SCALING_0_ia_adc_o : 
        std_logic_vector(17 downto 3);
    signal ADC_SCALING_0_ib_adc_o : 
        std_logic_vector(17 downto 0);
    signal ialpha_o : std_logic_vector(17 downto 0);
    signal ibeta_o : std_logic_vector(17 downto 0);
    signal va_o : std_logic_vector(17 downto 0);
    signal vb_o : std_logic_vector(17 downto 0);
    signal \vc_o\ : std_logic_vector(17 downto 0);
    signal apb3_if_st_0_adc_scale_val_o : 
        std_logic_vector(17 downto 0);
    signal adc_interface_0_result_ch0_o : 
        std_logic_vector(10 downto 1);
    signal adc_interface_0_result_ch2_o : 
        std_logic_vector(11 downto 0);
    signal apb3_if_st_0_adc_oc_thresh_o : 
        std_logic_vector(17 downto 0);
    signal apb3_if_st_0_adc_control_reg_val_o : 
        std_logic_vector(5 downto 0);
    signal adc_measurements_0_adc_result_ch1_o : 
        std_logic_vector(11 downto 2);
    signal adc_measurements_0_adc_result_ch3_o : 
        std_logic_vector(11 downto 0);
    signal apb3_if_st_0_adc_channel_ch2_o : 
        std_logic_vector(15 downto 0);
    signal apb3_if_st_0_adc_channel_ch1_o : 
        std_logic_vector(15 downto 0);
    signal apb3_if_st_0_adc_channel_ch3_o : 
        std_logic_vector(15 downto 0);
    signal apb3_if_st_0_adc_channel_ch0_o : 
        std_logic_vector(15 downto 0);
    signal ADC_SCALING_0_calib_done_o, 
        apb3_if_st_0_theta_gen_mode_o, 
        SEQ_CONTROLLER_1_motor_stopped_o, \GND\, 
        SEQ_CONTROLLER_1_en_idq_pi_o, 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, 
        FOC_TRANSFORMS_0_park_done_o, \VCC\, speed_pi_done_o, 
        SPEED_ID_IQ_PI_1_id_pi_done_o, 
        ADC_SCALING_0_over_current_fault_o, 
        apb3_if_st_0_start_motor_o, apb3_if_st_0_stop_motor_o, 
        PWM3PH_0_midmatch_o, PWM_SCALING_0_done_o, 
        SEQ_CONTROLLER_1_adc_start_o_0, cl_status_o, reset_rl_o, 
        soft_stop_o, sensor_reset_o, 
        FOC_TRANSFORMS_1_ipark_done_o, PWM_CH_o, PWM_CL_o, 
        ADC_SCALING_0_done_o, clarke_done_o, iclarke_done_o, 
        adc_interface_0_results_rdy_o : std_logic;

    for all : apb3_if_st
	Use entity work.apb3_if_st(DEF_ARCH);
    for all : ADC_SCALING_1
	Use entity work.ADC_SCALING_1(DEF_ARCH);
    for all : SPEED_ID_IQ_PI_1
	Use entity work.SPEED_ID_IQ_PI_1(DEF_ARCH);
    for all : STEPPER_THETA
	Use entity work.STEPPER_THETA(DEF_ARCH);
    for all : SEQ_CONTROLLER_1
	Use entity work.SEQ_CONTROLLER_1(DEF_ARCH);
    for all : PWM_SCALING_1
	Use entity work.PWM_SCALING_1(DEF_ARCH);
    for all : PWM3PH_1
	Use entity work.PWM3PH_1(DEF_ARCH);
    for all : adc_interface_1
	Use entity work.adc_interface_1(DEF_ARCH);
    for all : FOC_TRANSFORMS_1
	Use entity work.FOC_TRANSFORMS_1(DEF_ARCH);
begin 

    STEPPER_THETA_0_theta_output_o_17 <= 
        \STEPPER_THETA_0_theta_output_o_17\;
    FOC_TRANSFORMS_0_id_o_0 <= \FOC_TRANSFORMS_0_id_o_0\;
    FOC_TRANSFORMS_0_id_o_5 <= \FOC_TRANSFORMS_0_id_o_5\;
    FOC_TRANSFORMS_0_id_o_7 <= \FOC_TRANSFORMS_0_id_o_7\;
    FOC_TRANSFORMS_0_id_o_8 <= \FOC_TRANSFORMS_0_id_o_8\;
    FOC_TRANSFORMS_0_id_o_9 <= \FOC_TRANSFORMS_0_id_o_9\;
    FOC_TRANSFORMS_0_id_o_10 <= \FOC_TRANSFORMS_0_id_o_10\;
    FOC_TRANSFORMS_0_id_o_12 <= \FOC_TRANSFORMS_0_id_o_12\;
    FOC_TRANSFORMS_0_id_o_15 <= \FOC_TRANSFORMS_0_id_o_15\;
    FOC_TRANSFORMS_0_iq_o_0 <= \FOC_TRANSFORMS_0_iq_o_0\;
    FOC_TRANSFORMS_0_iq_o_1 <= \FOC_TRANSFORMS_0_iq_o_1\;
    FOC_TRANSFORMS_0_iq_o_2 <= \FOC_TRANSFORMS_0_iq_o_2\;
    FOC_TRANSFORMS_0_iq_o_3 <= \FOC_TRANSFORMS_0_iq_o_3\;
    FOC_TRANSFORMS_0_iq_o_5 <= \FOC_TRANSFORMS_0_iq_o_5\;
    FOC_TRANSFORMS_0_iq_o_6 <= \FOC_TRANSFORMS_0_iq_o_6\;
    FOC_TRANSFORMS_0_iq_o_7 <= \FOC_TRANSFORMS_0_iq_o_7\;
    FOC_TRANSFORMS_0_iq_o_8 <= \FOC_TRANSFORMS_0_iq_o_8\;
    FOC_TRANSFORMS_0_iq_o_10 <= \FOC_TRANSFORMS_0_iq_o_10\;
    FOC_TRANSFORMS_0_iq_o_11 <= \FOC_TRANSFORMS_0_iq_o_11\;
    FOC_TRANSFORMS_0_iq_o_12 <= \FOC_TRANSFORMS_0_iq_o_12\;
    FOC_TRANSFORMS_0_iq_o_15 <= \FOC_TRANSFORMS_0_iq_o_15\;
    SPEED_ID_IQ_PI_1_id_pi_output_o_1 <= 
        \SPEED_ID_IQ_PI_1_id_pi_output_o_1\;
    SPEED_ID_IQ_PI_1_iq_pi_output_o_1 <= 
        \SPEED_ID_IQ_PI_1_iq_pi_output_o_1\;
    FOC_TRANSFORMS_1_valpha_o_0 <= \FOC_TRANSFORMS_1_valpha_o_0\;
    FOC_TRANSFORMS_1_valpha_o_4 <= \FOC_TRANSFORMS_1_valpha_o_4\;
    FOC_TRANSFORMS_1_valpha_o_5 <= \FOC_TRANSFORMS_1_valpha_o_5\;
    FOC_TRANSFORMS_1_valpha_o_6 <= \FOC_TRANSFORMS_1_valpha_o_6\;
    FOC_TRANSFORMS_1_valpha_o_7 <= \FOC_TRANSFORMS_1_valpha_o_7\;
    FOC_TRANSFORMS_1_valpha_o_8 <= \FOC_TRANSFORMS_1_valpha_o_8\;
    FOC_TRANSFORMS_1_valpha_o_9 <= \FOC_TRANSFORMS_1_valpha_o_9\;
    FOC_TRANSFORMS_1_valpha_o_10 <= 
        \FOC_TRANSFORMS_1_valpha_o_10\;
    FOC_TRANSFORMS_1_valpha_o_11 <= 
        \FOC_TRANSFORMS_1_valpha_o_11\;
    FOC_TRANSFORMS_0_vbeta_o_0 <= \FOC_TRANSFORMS_0_vbeta_o_0\;
    FOC_TRANSFORMS_0_vbeta_o_2 <= \FOC_TRANSFORMS_0_vbeta_o_2\;
    FOC_TRANSFORMS_0_vbeta_o_3 <= \FOC_TRANSFORMS_0_vbeta_o_3\;
    FOC_TRANSFORMS_0_vbeta_o_5 <= \FOC_TRANSFORMS_0_vbeta_o_5\;
    FOC_TRANSFORMS_0_vbeta_o_7 <= \FOC_TRANSFORMS_0_vbeta_o_7\;
    FOC_TRANSFORMS_0_vbeta_o_8 <= \FOC_TRANSFORMS_0_vbeta_o_8\;
    FOC_TRANSFORMS_0_vbeta_o_10 <= \FOC_TRANSFORMS_0_vbeta_o_10\;
    FOC_TRANSFORMS_0_vbeta_o_12 <= \FOC_TRANSFORMS_0_vbeta_o_12\;
    FOC_TRANSFORMS_0_vbeta_o_15 <= \FOC_TRANSFORMS_0_vbeta_o_15\;
    ADC_SCALING_0_ib_adc_o_1 <= \ADC_SCALING_0_ib_adc_o_1\;
    ADC_SCALING_0_ib_adc_o_4 <= \ADC_SCALING_0_ib_adc_o_4\;
    ADC_SCALING_0_ib_adc_o_5 <= \ADC_SCALING_0_ib_adc_o_5\;
    ADC_SCALING_0_ib_adc_o_6 <= \ADC_SCALING_0_ib_adc_o_6\;
    ADC_SCALING_0_ib_adc_o_8 <= \ADC_SCALING_0_ib_adc_o_8\;
    ADC_SCALING_0_ib_adc_o_9 <= \ADC_SCALING_0_ib_adc_o_9\;
    ADC_SCALING_0_ib_adc_o_11 <= \ADC_SCALING_0_ib_adc_o_11\;
    ADC_SCALING_0_ib_adc_o_12 <= \ADC_SCALING_0_ib_adc_o_12\;
    ADC_SCALING_0_ib_adc_o_15 <= \ADC_SCALING_0_ib_adc_o_15\;
    adc_interface_0_result_ch0_o_0 <= 
        \adc_interface_0_result_ch0_o_0\;
    adc_interface_0_result_ch0_o_5 <= 
        \adc_interface_0_result_ch0_o_5\;
    adc_interface_0_result_ch0_o_6 <= 
        \adc_interface_0_result_ch0_o_6\;
    adc_interface_0_result_ch0_o_7 <= 
        \adc_interface_0_result_ch0_o_7\;
    adc_interface_0_result_ch0_o_8 <= 
        \adc_interface_0_result_ch0_o_8\;
    adc_interface_0_result_ch0_o_9 <= 
        \adc_interface_0_result_ch0_o_9\;
    adc_interface_0_result_ch0_o_11 <= 
        \adc_interface_0_result_ch0_o_11\;
    ADC_SCALING_0_ia_adc_o_1 <= \ADC_SCALING_0_ia_adc_o_1\;
    ADC_SCALING_0_ia_adc_o_2 <= \ADC_SCALING_0_ia_adc_o_2\;
    ADC_SCALING_0_ia_adc_o_4 <= \ADC_SCALING_0_ia_adc_o_4\;
    ADC_SCALING_0_ia_adc_o_5 <= \ADC_SCALING_0_ia_adc_o_5\;
    ADC_SCALING_0_ia_adc_o_6 <= \ADC_SCALING_0_ia_adc_o_6\;
    ADC_SCALING_0_ia_adc_o_7 <= \ADC_SCALING_0_ia_adc_o_7\;
    ADC_SCALING_0_ia_adc_o_8 <= \ADC_SCALING_0_ia_adc_o_8\;
    ADC_SCALING_0_ia_adc_o_9 <= \ADC_SCALING_0_ia_adc_o_9\;
    ADC_SCALING_0_ia_adc_o_10 <= \ADC_SCALING_0_ia_adc_o_10\;
    ADC_SCALING_0_ia_adc_o_11 <= \ADC_SCALING_0_ia_adc_o_11\;
    ADC_SCALING_0_ia_adc_o_12 <= \ADC_SCALING_0_ia_adc_o_12\;
    ADC_SCALING_0_ia_adc_o_15 <= \ADC_SCALING_0_ia_adc_o_15\;
    A1_PWM_WL_O_c <= \A1_PWM_WL_O_c\;

    GND_Z : GND
      port map(Y => \GND\);
    
    apb3_if_st_0 : apb3_if_st
      port map(apb3_if_st_0_adc_oc_thresh_o(17) => 
        apb3_if_st_0_adc_oc_thresh_o(17), 
        apb3_if_st_0_adc_oc_thresh_o(16) => 
        apb3_if_st_0_adc_oc_thresh_o(16), 
        apb3_if_st_0_adc_oc_thresh_o(15) => 
        apb3_if_st_0_adc_oc_thresh_o(15), 
        apb3_if_st_0_adc_oc_thresh_o(14) => 
        apb3_if_st_0_adc_oc_thresh_o(14), 
        apb3_if_st_0_adc_oc_thresh_o(13) => 
        apb3_if_st_0_adc_oc_thresh_o(13), 
        apb3_if_st_0_adc_oc_thresh_o(12) => 
        apb3_if_st_0_adc_oc_thresh_o(12), 
        apb3_if_st_0_adc_oc_thresh_o(11) => 
        apb3_if_st_0_adc_oc_thresh_o(11), 
        apb3_if_st_0_adc_oc_thresh_o(10) => 
        apb3_if_st_0_adc_oc_thresh_o(10), 
        apb3_if_st_0_adc_oc_thresh_o(9) => 
        apb3_if_st_0_adc_oc_thresh_o(9), 
        apb3_if_st_0_adc_oc_thresh_o(8) => 
        apb3_if_st_0_adc_oc_thresh_o(8), 
        apb3_if_st_0_adc_oc_thresh_o(7) => 
        apb3_if_st_0_adc_oc_thresh_o(7), 
        apb3_if_st_0_adc_oc_thresh_o(6) => 
        apb3_if_st_0_adc_oc_thresh_o(6), 
        apb3_if_st_0_adc_oc_thresh_o(5) => 
        apb3_if_st_0_adc_oc_thresh_o(5), 
        apb3_if_st_0_adc_oc_thresh_o(4) => 
        apb3_if_st_0_adc_oc_thresh_o(4), 
        apb3_if_st_0_adc_oc_thresh_o(3) => 
        apb3_if_st_0_adc_oc_thresh_o(3), 
        apb3_if_st_0_adc_oc_thresh_o(2) => 
        apb3_if_st_0_adc_oc_thresh_o(2), 
        apb3_if_st_0_adc_oc_thresh_o(1) => 
        apb3_if_st_0_adc_oc_thresh_o(1), 
        apb3_if_st_0_adc_oc_thresh_o(0) => 
        apb3_if_st_0_adc_oc_thresh_o(0), 
        apb3_if_st_0_adc_scale_val_o(17) => 
        apb3_if_st_0_adc_scale_val_o(17), 
        apb3_if_st_0_adc_scale_val_o(16) => 
        apb3_if_st_0_adc_scale_val_o(16), 
        apb3_if_st_0_adc_scale_val_o(15) => 
        apb3_if_st_0_adc_scale_val_o(15), 
        apb3_if_st_0_adc_scale_val_o(14) => 
        apb3_if_st_0_adc_scale_val_o(14), 
        apb3_if_st_0_adc_scale_val_o(13) => 
        apb3_if_st_0_adc_scale_val_o(13), 
        apb3_if_st_0_adc_scale_val_o(12) => 
        apb3_if_st_0_adc_scale_val_o(12), 
        apb3_if_st_0_adc_scale_val_o(11) => 
        apb3_if_st_0_adc_scale_val_o(11), 
        apb3_if_st_0_adc_scale_val_o(10) => 
        apb3_if_st_0_adc_scale_val_o(10), 
        apb3_if_st_0_adc_scale_val_o(9) => 
        apb3_if_st_0_adc_scale_val_o(9), 
        apb3_if_st_0_adc_scale_val_o(8) => 
        apb3_if_st_0_adc_scale_val_o(8), 
        apb3_if_st_0_adc_scale_val_o(7) => 
        apb3_if_st_0_adc_scale_val_o(7), 
        apb3_if_st_0_adc_scale_val_o(6) => 
        apb3_if_st_0_adc_scale_val_o(6), 
        apb3_if_st_0_adc_scale_val_o(5) => 
        apb3_if_st_0_adc_scale_val_o(5), 
        apb3_if_st_0_adc_scale_val_o(4) => 
        apb3_if_st_0_adc_scale_val_o(4), 
        apb3_if_st_0_adc_scale_val_o(3) => 
        apb3_if_st_0_adc_scale_val_o(3), 
        apb3_if_st_0_adc_scale_val_o(2) => 
        apb3_if_st_0_adc_scale_val_o(2), 
        apb3_if_st_0_adc_scale_val_o(1) => 
        apb3_if_st_0_adc_scale_val_o(1), 
        apb3_if_st_0_adc_scale_val_o(0) => 
        apb3_if_st_0_adc_scale_val_o(0), 
        apb3_if_st_0_id_ref_val_o(17) => 
        apb3_if_st_0_id_ref_val_o(17), 
        apb3_if_st_0_id_ref_val_o(16) => 
        apb3_if_st_0_id_ref_val_o(16), 
        apb3_if_st_0_id_ref_val_o(15) => 
        apb3_if_st_0_id_ref_val_o(15), 
        apb3_if_st_0_id_ref_val_o(14) => 
        apb3_if_st_0_id_ref_val_o(14), 
        apb3_if_st_0_id_ref_val_o(13) => 
        apb3_if_st_0_id_ref_val_o(13), 
        apb3_if_st_0_id_ref_val_o(12) => 
        apb3_if_st_0_id_ref_val_o(12), 
        apb3_if_st_0_id_ref_val_o(11) => 
        apb3_if_st_0_id_ref_val_o(11), 
        apb3_if_st_0_id_ref_val_o(10) => 
        apb3_if_st_0_id_ref_val_o(10), 
        apb3_if_st_0_id_ref_val_o(9) => 
        apb3_if_st_0_id_ref_val_o(9), 
        apb3_if_st_0_id_ref_val_o(8) => 
        apb3_if_st_0_id_ref_val_o(8), 
        apb3_if_st_0_id_ref_val_o(7) => 
        apb3_if_st_0_id_ref_val_o(7), 
        apb3_if_st_0_id_ref_val_o(6) => 
        apb3_if_st_0_id_ref_val_o(6), 
        apb3_if_st_0_id_ref_val_o(5) => 
        apb3_if_st_0_id_ref_val_o(5), 
        apb3_if_st_0_id_ref_val_o(4) => 
        apb3_if_st_0_id_ref_val_o(4), 
        apb3_if_st_0_id_ref_val_o(3) => 
        apb3_if_st_0_id_ref_val_o(3), 
        apb3_if_st_0_id_ref_val_o(2) => 
        apb3_if_st_0_id_ref_val_o(2), 
        apb3_if_st_0_id_ref_val_o(1) => 
        apb3_if_st_0_id_ref_val_o(1), 
        apb3_if_st_0_id_ref_val_o(0) => 
        apb3_if_st_0_id_ref_val_o(0), 
        apb3_if_st_0_idq_pi_ki_o(17) => 
        apb3_if_st_0_idq_pi_ki_o(17), 
        apb3_if_st_0_idq_pi_ki_o(16) => 
        apb3_if_st_0_idq_pi_ki_o(16), 
        apb3_if_st_0_idq_pi_ki_o(15) => 
        apb3_if_st_0_idq_pi_ki_o(15), 
        apb3_if_st_0_idq_pi_ki_o(14) => 
        apb3_if_st_0_idq_pi_ki_o(14), 
        apb3_if_st_0_idq_pi_ki_o(13) => 
        apb3_if_st_0_idq_pi_ki_o(13), 
        apb3_if_st_0_idq_pi_ki_o(12) => 
        apb3_if_st_0_idq_pi_ki_o(12), 
        apb3_if_st_0_idq_pi_ki_o(11) => 
        apb3_if_st_0_idq_pi_ki_o(11), 
        apb3_if_st_0_idq_pi_ki_o(10) => 
        apb3_if_st_0_idq_pi_ki_o(10), apb3_if_st_0_idq_pi_ki_o(9)
         => apb3_if_st_0_idq_pi_ki_o(9), 
        apb3_if_st_0_idq_pi_ki_o(8) => 
        apb3_if_st_0_idq_pi_ki_o(8), apb3_if_st_0_idq_pi_ki_o(7)
         => apb3_if_st_0_idq_pi_ki_o(7), 
        apb3_if_st_0_idq_pi_ki_o(6) => 
        apb3_if_st_0_idq_pi_ki_o(6), apb3_if_st_0_idq_pi_ki_o(5)
         => apb3_if_st_0_idq_pi_ki_o(5), 
        apb3_if_st_0_idq_pi_ki_o(4) => 
        apb3_if_st_0_idq_pi_ki_o(4), apb3_if_st_0_idq_pi_ki_o(3)
         => apb3_if_st_0_idq_pi_ki_o(3), 
        apb3_if_st_0_idq_pi_ki_o(2) => 
        apb3_if_st_0_idq_pi_ki_o(2), apb3_if_st_0_idq_pi_ki_o(1)
         => apb3_if_st_0_idq_pi_ki_o(1), 
        apb3_if_st_0_idq_pi_ki_o(0) => 
        apb3_if_st_0_idq_pi_ki_o(0), apb3_if_st_0_idq_pi_kp_o(17)
         => apb3_if_st_0_idq_pi_kp_o(17), 
        apb3_if_st_0_idq_pi_kp_o(16) => 
        apb3_if_st_0_idq_pi_kp_o(16), 
        apb3_if_st_0_idq_pi_kp_o(15) => 
        apb3_if_st_0_idq_pi_kp_o(15), 
        apb3_if_st_0_idq_pi_kp_o(14) => 
        apb3_if_st_0_idq_pi_kp_o(14), 
        apb3_if_st_0_idq_pi_kp_o(13) => 
        apb3_if_st_0_idq_pi_kp_o(13), 
        apb3_if_st_0_idq_pi_kp_o(12) => 
        apb3_if_st_0_idq_pi_kp_o(12), 
        apb3_if_st_0_idq_pi_kp_o(11) => 
        apb3_if_st_0_idq_pi_kp_o(11), 
        apb3_if_st_0_idq_pi_kp_o(10) => 
        apb3_if_st_0_idq_pi_kp_o(10), apb3_if_st_0_idq_pi_kp_o(9)
         => apb3_if_st_0_idq_pi_kp_o(9), 
        apb3_if_st_0_idq_pi_kp_o(8) => 
        apb3_if_st_0_idq_pi_kp_o(8), apb3_if_st_0_idq_pi_kp_o(7)
         => apb3_if_st_0_idq_pi_kp_o(7), 
        apb3_if_st_0_idq_pi_kp_o(6) => 
        apb3_if_st_0_idq_pi_kp_o(6), apb3_if_st_0_idq_pi_kp_o(5)
         => apb3_if_st_0_idq_pi_kp_o(5), 
        apb3_if_st_0_idq_pi_kp_o(4) => 
        apb3_if_st_0_idq_pi_kp_o(4), apb3_if_st_0_idq_pi_kp_o(3)
         => apb3_if_st_0_idq_pi_kp_o(3), 
        apb3_if_st_0_idq_pi_kp_o(2) => 
        apb3_if_st_0_idq_pi_kp_o(2), apb3_if_st_0_idq_pi_kp_o(1)
         => apb3_if_st_0_idq_pi_kp_o(1), 
        apb3_if_st_0_idq_pi_kp_o(0) => 
        apb3_if_st_0_idq_pi_kp_o(0), 
        apb3_if_st_0_pwm_dead_time_val_o(17) => 
        apb3_if_st_0_pwm_dead_time_val_o(17), 
        apb3_if_st_0_pwm_dead_time_val_o(16) => 
        apb3_if_st_0_pwm_dead_time_val_o(16), 
        apb3_if_st_0_pwm_dead_time_val_o(15) => 
        apb3_if_st_0_pwm_dead_time_val_o(15), 
        apb3_if_st_0_pwm_dead_time_val_o(14) => 
        apb3_if_st_0_pwm_dead_time_val_o(14), 
        apb3_if_st_0_pwm_dead_time_val_o(13) => 
        apb3_if_st_0_pwm_dead_time_val_o(13), 
        apb3_if_st_0_pwm_dead_time_val_o(12) => 
        apb3_if_st_0_pwm_dead_time_val_o(12), 
        apb3_if_st_0_pwm_dead_time_val_o(11) => 
        apb3_if_st_0_pwm_dead_time_val_o(11), 
        apb3_if_st_0_pwm_dead_time_val_o(10) => 
        apb3_if_st_0_pwm_dead_time_val_o(10), 
        apb3_if_st_0_pwm_dead_time_val_o(9) => 
        apb3_if_st_0_pwm_dead_time_val_o(9), 
        apb3_if_st_0_pwm_dead_time_val_o(8) => 
        apb3_if_st_0_pwm_dead_time_val_o(8), 
        apb3_if_st_0_pwm_dead_time_val_o(7) => 
        apb3_if_st_0_pwm_dead_time_val_o(7), 
        apb3_if_st_0_pwm_dead_time_val_o(6) => 
        apb3_if_st_0_pwm_dead_time_val_o(6), 
        apb3_if_st_0_pwm_dead_time_val_o(5) => 
        apb3_if_st_0_pwm_dead_time_val_o(5), 
        apb3_if_st_0_pwm_dead_time_val_o(4) => 
        apb3_if_st_0_pwm_dead_time_val_o(4), 
        apb3_if_st_0_pwm_dead_time_val_o(3) => 
        apb3_if_st_0_pwm_dead_time_val_o(3), 
        apb3_if_st_0_pwm_dead_time_val_o(2) => 
        apb3_if_st_0_pwm_dead_time_val_o(2), 
        apb3_if_st_0_pwm_dead_time_val_o(1) => 
        apb3_if_st_0_pwm_dead_time_val_o(1), 
        apb3_if_st_0_pwm_dead_time_val_o(0) => 
        apb3_if_st_0_pwm_dead_time_val_o(0), 
        apb3_if_st_0_pwm_delay_time_val_o(17) => 
        apb3_if_st_0_pwm_delay_time_val_o(17), 
        apb3_if_st_0_pwm_delay_time_val_o(16) => 
        apb3_if_st_0_pwm_delay_time_val_o(16), 
        apb3_if_st_0_pwm_delay_time_val_o(15) => 
        apb3_if_st_0_pwm_delay_time_val_o(15), 
        apb3_if_st_0_pwm_delay_time_val_o(14) => 
        apb3_if_st_0_pwm_delay_time_val_o(14), 
        apb3_if_st_0_pwm_delay_time_val_o(13) => 
        apb3_if_st_0_pwm_delay_time_val_o(13), 
        apb3_if_st_0_pwm_delay_time_val_o(12) => 
        apb3_if_st_0_pwm_delay_time_val_o(12), 
        apb3_if_st_0_pwm_delay_time_val_o(11) => 
        apb3_if_st_0_pwm_delay_time_val_o(11), 
        apb3_if_st_0_pwm_delay_time_val_o(10) => 
        apb3_if_st_0_pwm_delay_time_val_o(10), 
        apb3_if_st_0_pwm_delay_time_val_o(9) => 
        apb3_if_st_0_pwm_delay_time_val_o(9), 
        apb3_if_st_0_pwm_delay_time_val_o(8) => 
        apb3_if_st_0_pwm_delay_time_val_o(8), 
        apb3_if_st_0_pwm_delay_time_val_o(7) => 
        apb3_if_st_0_pwm_delay_time_val_o(7), 
        apb3_if_st_0_pwm_delay_time_val_o(6) => 
        apb3_if_st_0_pwm_delay_time_val_o(6), 
        apb3_if_st_0_pwm_delay_time_val_o(5) => 
        apb3_if_st_0_pwm_delay_time_val_o(5), 
        apb3_if_st_0_pwm_delay_time_val_o(4) => 
        apb3_if_st_0_pwm_delay_time_val_o(4), 
        apb3_if_st_0_pwm_delay_time_val_o(3) => 
        apb3_if_st_0_pwm_delay_time_val_o(3), 
        apb3_if_st_0_pwm_delay_time_val_o(2) => 
        apb3_if_st_0_pwm_delay_time_val_o(2), 
        apb3_if_st_0_pwm_delay_time_val_o(1) => 
        apb3_if_st_0_pwm_delay_time_val_o(1), 
        apb3_if_st_0_pwm_delay_time_val_o(0) => 
        apb3_if_st_0_pwm_delay_time_val_o(0), 
        apb3_if_st_0_pwm_period_val_o(17) => 
        apb3_if_st_0_pwm_period_val_o(17), 
        apb3_if_st_0_pwm_period_val_o(16) => 
        apb3_if_st_0_pwm_period_val_o(16), 
        apb3_if_st_0_pwm_period_val_o(15) => 
        apb3_if_st_0_pwm_period_val_o(15), 
        apb3_if_st_0_pwm_period_val_o(14) => 
        apb3_if_st_0_pwm_period_val_o(14), 
        apb3_if_st_0_pwm_period_val_o(13) => 
        apb3_if_st_0_pwm_period_val_o(13), 
        apb3_if_st_0_pwm_period_val_o(12) => 
        apb3_if_st_0_pwm_period_val_o(12), 
        apb3_if_st_0_pwm_period_val_o(11) => 
        apb3_if_st_0_pwm_period_val_o(11), 
        apb3_if_st_0_pwm_period_val_o(10) => 
        apb3_if_st_0_pwm_period_val_o(10), 
        apb3_if_st_0_pwm_period_val_o(9) => 
        apb3_if_st_0_pwm_period_val_o(9), 
        apb3_if_st_0_pwm_period_val_o(8) => 
        apb3_if_st_0_pwm_period_val_o(8), 
        apb3_if_st_0_pwm_period_val_o(7) => 
        apb3_if_st_0_pwm_period_val_o(7), 
        apb3_if_st_0_pwm_period_val_o(6) => 
        apb3_if_st_0_pwm_period_val_o(6), 
        apb3_if_st_0_pwm_period_val_o(5) => 
        apb3_if_st_0_pwm_period_val_o(5), 
        apb3_if_st_0_pwm_period_val_o(4) => 
        apb3_if_st_0_pwm_period_val_o(4), 
        apb3_if_st_0_pwm_period_val_o(3) => 
        apb3_if_st_0_pwm_period_val_o(3), 
        apb3_if_st_0_pwm_period_val_o(2) => 
        apb3_if_st_0_pwm_period_val_o(2), 
        apb3_if_st_0_pwm_period_val_o(1) => 
        apb3_if_st_0_pwm_period_val_o(1), 
        apb3_if_st_0_pwm_period_val_o(0) => 
        apb3_if_st_0_pwm_period_val_o(0), 
        apb3_if_st_0_sqmng_dv_o(17) => 
        apb3_if_st_0_sqmng_dv_o(17), apb3_if_st_0_sqmng_dv_o(16)
         => apb3_if_st_0_sqmng_dv_o(16), 
        apb3_if_st_0_sqmng_dv_o(15) => 
        apb3_if_st_0_sqmng_dv_o(15), apb3_if_st_0_sqmng_dv_o(14)
         => apb3_if_st_0_sqmng_dv_o(14), 
        apb3_if_st_0_sqmng_dv_o(13) => 
        apb3_if_st_0_sqmng_dv_o(13), apb3_if_st_0_sqmng_dv_o(12)
         => apb3_if_st_0_sqmng_dv_o(12), 
        apb3_if_st_0_sqmng_dv_o(11) => 
        apb3_if_st_0_sqmng_dv_o(11), apb3_if_st_0_sqmng_dv_o(10)
         => apb3_if_st_0_sqmng_dv_o(10), 
        apb3_if_st_0_sqmng_dv_o(9) => apb3_if_st_0_sqmng_dv_o(9), 
        apb3_if_st_0_sqmng_dv_o(8) => apb3_if_st_0_sqmng_dv_o(8), 
        apb3_if_st_0_sqmng_dv_o(7) => apb3_if_st_0_sqmng_dv_o(7), 
        apb3_if_st_0_sqmng_dv_o(6) => apb3_if_st_0_sqmng_dv_o(6), 
        apb3_if_st_0_sqmng_dv_o(5) => apb3_if_st_0_sqmng_dv_o(5), 
        apb3_if_st_0_sqmng_dv_o(4) => apb3_if_st_0_sqmng_dv_o(4), 
        apb3_if_st_0_sqmng_dv_o(3) => apb3_if_st_0_sqmng_dv_o(3), 
        apb3_if_st_0_sqmng_dv_o(2) => apb3_if_st_0_sqmng_dv_o(2), 
        apb3_if_st_0_sqmng_dv_o(1) => apb3_if_st_0_sqmng_dv_o(1), 
        apb3_if_st_0_sqmng_dv_o(0) => apb3_if_st_0_sqmng_dv_o(0), 
        apb3_if_st_0_theta_gen_rate_limit_o(17) => 
        apb3_if_st_0_theta_gen_rate_limit_o(17), 
        apb3_if_st_0_theta_gen_rate_limit_o(16) => 
        apb3_if_st_0_theta_gen_rate_limit_o(16), 
        apb3_if_st_0_theta_gen_rate_limit_o(15) => 
        apb3_if_st_0_theta_gen_rate_limit_o(15), 
        apb3_if_st_0_theta_gen_rate_limit_o(14) => 
        apb3_if_st_0_theta_gen_rate_limit_o(14), 
        apb3_if_st_0_theta_gen_rate_limit_o(13) => 
        apb3_if_st_0_theta_gen_rate_limit_o(13), 
        apb3_if_st_0_theta_gen_rate_limit_o(12) => 
        apb3_if_st_0_theta_gen_rate_limit_o(12), 
        apb3_if_st_0_theta_gen_rate_limit_o(11) => 
        apb3_if_st_0_theta_gen_rate_limit_o(11), 
        apb3_if_st_0_theta_gen_rate_limit_o(10) => 
        apb3_if_st_0_theta_gen_rate_limit_o(10), 
        apb3_if_st_0_theta_gen_rate_limit_o(9) => 
        apb3_if_st_0_theta_gen_rate_limit_o(9), 
        apb3_if_st_0_theta_gen_rate_limit_o(8) => 
        apb3_if_st_0_theta_gen_rate_limit_o(8), 
        apb3_if_st_0_theta_gen_rate_limit_o(7) => 
        apb3_if_st_0_theta_gen_rate_limit_o(7), 
        apb3_if_st_0_theta_gen_rate_limit_o(6) => 
        apb3_if_st_0_theta_gen_rate_limit_o(6), 
        apb3_if_st_0_theta_gen_rate_limit_o(5) => 
        apb3_if_st_0_theta_gen_rate_limit_o(5), 
        apb3_if_st_0_theta_gen_rate_limit_o(4) => 
        apb3_if_st_0_theta_gen_rate_limit_o(4), 
        apb3_if_st_0_theta_gen_rate_limit_o(3) => 
        apb3_if_st_0_theta_gen_rate_limit_o(3), 
        apb3_if_st_0_theta_gen_rate_limit_o(2) => 
        apb3_if_st_0_theta_gen_rate_limit_o(2), 
        apb3_if_st_0_theta_gen_rate_limit_o(1) => 
        apb3_if_st_0_theta_gen_rate_limit_o(1), 
        apb3_if_st_0_theta_gen_rate_limit_o(0) => 
        apb3_if_st_0_theta_gen_rate_limit_o(0), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0), 
        apb3_if_st_0_theta_gen_slew_count_o(17) => 
        apb3_if_st_0_theta_gen_slew_count_o(17), 
        apb3_if_st_0_theta_gen_slew_count_o(16) => 
        apb3_if_st_0_theta_gen_slew_count_o(16), 
        apb3_if_st_0_theta_gen_slew_count_o(15) => 
        apb3_if_st_0_theta_gen_slew_count_o(15), 
        apb3_if_st_0_theta_gen_slew_count_o(14) => 
        apb3_if_st_0_theta_gen_slew_count_o(14), 
        apb3_if_st_0_theta_gen_slew_count_o(13) => 
        apb3_if_st_0_theta_gen_slew_count_o(13), 
        apb3_if_st_0_theta_gen_slew_count_o(12) => 
        apb3_if_st_0_theta_gen_slew_count_o(12), 
        apb3_if_st_0_theta_gen_slew_count_o(11) => 
        apb3_if_st_0_theta_gen_slew_count_o(11), 
        apb3_if_st_0_theta_gen_slew_count_o(10) => 
        apb3_if_st_0_theta_gen_slew_count_o(10), 
        apb3_if_st_0_theta_gen_slew_count_o(9) => 
        apb3_if_st_0_theta_gen_slew_count_o(9), 
        apb3_if_st_0_theta_gen_slew_count_o(8) => 
        apb3_if_st_0_theta_gen_slew_count_o(8), 
        apb3_if_st_0_theta_gen_slew_count_o(7) => 
        apb3_if_st_0_theta_gen_slew_count_o(7), 
        apb3_if_st_0_theta_gen_slew_count_o(6) => 
        apb3_if_st_0_theta_gen_slew_count_o(6), 
        apb3_if_st_0_theta_gen_slew_count_o(5) => 
        apb3_if_st_0_theta_gen_slew_count_o(5), 
        apb3_if_st_0_theta_gen_slew_count_o(4) => 
        apb3_if_st_0_theta_gen_slew_count_o(4), 
        apb3_if_st_0_theta_gen_slew_count_o(3) => 
        apb3_if_st_0_theta_gen_slew_count_o(3), 
        apb3_if_st_0_theta_gen_slew_count_o(2) => 
        apb3_if_st_0_theta_gen_slew_count_o(2), 
        apb3_if_st_0_theta_gen_slew_count_o(1) => 
        apb3_if_st_0_theta_gen_slew_count_o(1), 
        apb3_if_st_0_theta_gen_slew_count_o(0) => 
        apb3_if_st_0_theta_gen_slew_count_o(0), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(23) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(23), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(22) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(22), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(21) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(21), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(20) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(20), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(19) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(19), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(18) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(18), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(17) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(17), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(16) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(16), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(15) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(15), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(14) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(14), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(13) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(13), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(12) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(12), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(11) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(11), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(10) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(10), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(9) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(9), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(8) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(8), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(7) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(7), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(6) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(6), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(5) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(5), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(4) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(4), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(3) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(3), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(2) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(2), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(1) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(1), 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(0) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(0), 
        apb3_if_st_0_adc_control_reg_val_o(5) => 
        apb3_if_st_0_adc_control_reg_val_o(5), 
        apb3_if_st_0_adc_control_reg_val_o(4) => 
        apb3_if_st_0_adc_control_reg_val_o(4), 
        apb3_if_st_0_adc_control_reg_val_o(3) => 
        apb3_if_st_0_adc_control_reg_val_o(3), 
        apb3_if_st_0_adc_control_reg_val_o(2) => 
        apb3_if_st_0_adc_control_reg_val_o(2), 
        apb3_if_st_0_adc_control_reg_val_o(1) => 
        apb3_if_st_0_adc_control_reg_val_o(1), 
        apb3_if_st_0_adc_control_reg_val_o(0) => 
        apb3_if_st_0_adc_control_reg_val_o(0), 
        apb3_if_st_0_seq_cntl_config_o(2) => 
        apb3_if_st_0_seq_cntl_config_o(2), 
        apb3_if_st_0_seq_cntl_config_o(1) => 
        apb3_if_st_0_seq_cntl_config_o(1), 
        apb3_if_st_0_adc_channel_ch0_o(15) => 
        apb3_if_st_0_adc_channel_ch0_o(15), 
        apb3_if_st_0_adc_channel_ch0_o(14) => 
        apb3_if_st_0_adc_channel_ch0_o(14), 
        apb3_if_st_0_adc_channel_ch0_o(13) => 
        apb3_if_st_0_adc_channel_ch0_o(13), 
        apb3_if_st_0_adc_channel_ch0_o(12) => 
        apb3_if_st_0_adc_channel_ch0_o(12), 
        apb3_if_st_0_adc_channel_ch0_o(11) => 
        apb3_if_st_0_adc_channel_ch0_o(11), 
        apb3_if_st_0_adc_channel_ch0_o(10) => 
        apb3_if_st_0_adc_channel_ch0_o(10), 
        apb3_if_st_0_adc_channel_ch0_o(9) => 
        apb3_if_st_0_adc_channel_ch0_o(9), 
        apb3_if_st_0_adc_channel_ch0_o(8) => 
        apb3_if_st_0_adc_channel_ch0_o(8), 
        apb3_if_st_0_adc_channel_ch0_o(7) => 
        apb3_if_st_0_adc_channel_ch0_o(7), 
        apb3_if_st_0_adc_channel_ch0_o(6) => 
        apb3_if_st_0_adc_channel_ch0_o(6), 
        apb3_if_st_0_adc_channel_ch0_o(5) => 
        apb3_if_st_0_adc_channel_ch0_o(5), 
        apb3_if_st_0_adc_channel_ch0_o(4) => 
        apb3_if_st_0_adc_channel_ch0_o(4), 
        apb3_if_st_0_adc_channel_ch0_o(3) => 
        apb3_if_st_0_adc_channel_ch0_o(3), 
        apb3_if_st_0_adc_channel_ch0_o(2) => 
        apb3_if_st_0_adc_channel_ch0_o(2), 
        apb3_if_st_0_adc_channel_ch0_o(1) => 
        apb3_if_st_0_adc_channel_ch0_o(1), 
        apb3_if_st_0_adc_channel_ch0_o(0) => 
        apb3_if_st_0_adc_channel_ch0_o(0), 
        apb3_if_st_0_adc_channel_ch1_o(15) => 
        apb3_if_st_0_adc_channel_ch1_o(15), 
        apb3_if_st_0_adc_channel_ch1_o(14) => 
        apb3_if_st_0_adc_channel_ch1_o(14), 
        apb3_if_st_0_adc_channel_ch1_o(13) => 
        apb3_if_st_0_adc_channel_ch1_o(13), 
        apb3_if_st_0_adc_channel_ch1_o(12) => 
        apb3_if_st_0_adc_channel_ch1_o(12), 
        apb3_if_st_0_adc_channel_ch1_o(11) => 
        apb3_if_st_0_adc_channel_ch1_o(11), 
        apb3_if_st_0_adc_channel_ch1_o(10) => 
        apb3_if_st_0_adc_channel_ch1_o(10), 
        apb3_if_st_0_adc_channel_ch1_o(9) => 
        apb3_if_st_0_adc_channel_ch1_o(9), 
        apb3_if_st_0_adc_channel_ch1_o(8) => 
        apb3_if_st_0_adc_channel_ch1_o(8), 
        apb3_if_st_0_adc_channel_ch1_o(7) => 
        apb3_if_st_0_adc_channel_ch1_o(7), 
        apb3_if_st_0_adc_channel_ch1_o(6) => 
        apb3_if_st_0_adc_channel_ch1_o(6), 
        apb3_if_st_0_adc_channel_ch1_o(5) => 
        apb3_if_st_0_adc_channel_ch1_o(5), 
        apb3_if_st_0_adc_channel_ch1_o(4) => 
        apb3_if_st_0_adc_channel_ch1_o(4), 
        apb3_if_st_0_adc_channel_ch1_o(3) => 
        apb3_if_st_0_adc_channel_ch1_o(3), 
        apb3_if_st_0_adc_channel_ch1_o(2) => 
        apb3_if_st_0_adc_channel_ch1_o(2), 
        apb3_if_st_0_adc_channel_ch1_o(1) => 
        apb3_if_st_0_adc_channel_ch1_o(1), 
        apb3_if_st_0_adc_channel_ch1_o(0) => 
        apb3_if_st_0_adc_channel_ch1_o(0), 
        apb3_if_st_0_adc_channel_ch2_o(15) => 
        apb3_if_st_0_adc_channel_ch2_o(15), 
        apb3_if_st_0_adc_channel_ch2_o(14) => 
        apb3_if_st_0_adc_channel_ch2_o(14), 
        apb3_if_st_0_adc_channel_ch2_o(13) => 
        apb3_if_st_0_adc_channel_ch2_o(13), 
        apb3_if_st_0_adc_channel_ch2_o(12) => 
        apb3_if_st_0_adc_channel_ch2_o(12), 
        apb3_if_st_0_adc_channel_ch2_o(11) => 
        apb3_if_st_0_adc_channel_ch2_o(11), 
        apb3_if_st_0_adc_channel_ch2_o(10) => 
        apb3_if_st_0_adc_channel_ch2_o(10), 
        apb3_if_st_0_adc_channel_ch2_o(9) => 
        apb3_if_st_0_adc_channel_ch2_o(9), 
        apb3_if_st_0_adc_channel_ch2_o(8) => 
        apb3_if_st_0_adc_channel_ch2_o(8), 
        apb3_if_st_0_adc_channel_ch2_o(7) => 
        apb3_if_st_0_adc_channel_ch2_o(7), 
        apb3_if_st_0_adc_channel_ch2_o(6) => 
        apb3_if_st_0_adc_channel_ch2_o(6), 
        apb3_if_st_0_adc_channel_ch2_o(5) => 
        apb3_if_st_0_adc_channel_ch2_o(5), 
        apb3_if_st_0_adc_channel_ch2_o(4) => 
        apb3_if_st_0_adc_channel_ch2_o(4), 
        apb3_if_st_0_adc_channel_ch2_o(3) => 
        apb3_if_st_0_adc_channel_ch2_o(3), 
        apb3_if_st_0_adc_channel_ch2_o(2) => 
        apb3_if_st_0_adc_channel_ch2_o(2), 
        apb3_if_st_0_adc_channel_ch2_o(1) => 
        apb3_if_st_0_adc_channel_ch2_o(1), 
        apb3_if_st_0_adc_channel_ch2_o(0) => 
        apb3_if_st_0_adc_channel_ch2_o(0), 
        apb3_if_st_0_adc_channel_ch3_o(15) => 
        apb3_if_st_0_adc_channel_ch3_o(15), 
        apb3_if_st_0_adc_channel_ch3_o(14) => 
        apb3_if_st_0_adc_channel_ch3_o(14), 
        apb3_if_st_0_adc_channel_ch3_o(13) => 
        apb3_if_st_0_adc_channel_ch3_o(13), 
        apb3_if_st_0_adc_channel_ch3_o(12) => 
        apb3_if_st_0_adc_channel_ch3_o(12), 
        apb3_if_st_0_adc_channel_ch3_o(11) => 
        apb3_if_st_0_adc_channel_ch3_o(11), 
        apb3_if_st_0_adc_channel_ch3_o(10) => 
        apb3_if_st_0_adc_channel_ch3_o(10), 
        apb3_if_st_0_adc_channel_ch3_o(9) => 
        apb3_if_st_0_adc_channel_ch3_o(9), 
        apb3_if_st_0_adc_channel_ch3_o(8) => 
        apb3_if_st_0_adc_channel_ch3_o(8), 
        apb3_if_st_0_adc_channel_ch3_o(7) => 
        apb3_if_st_0_adc_channel_ch3_o(7), 
        apb3_if_st_0_adc_channel_ch3_o(6) => 
        apb3_if_st_0_adc_channel_ch3_o(6), 
        apb3_if_st_0_adc_channel_ch3_o(5) => 
        apb3_if_st_0_adc_channel_ch3_o(5), 
        apb3_if_st_0_adc_channel_ch3_o(4) => 
        apb3_if_st_0_adc_channel_ch3_o(4), 
        apb3_if_st_0_adc_channel_ch3_o(3) => 
        apb3_if_st_0_adc_channel_ch3_o(3), 
        apb3_if_st_0_adc_channel_ch3_o(2) => 
        apb3_if_st_0_adc_channel_ch3_o(2), 
        apb3_if_st_0_adc_channel_ch3_o(1) => 
        apb3_if_st_0_adc_channel_ch3_o(1), 
        apb3_if_st_0_adc_channel_ch3_o(0) => 
        apb3_if_st_0_adc_channel_ch3_o(0), 
        prdata_o_1_0_iv_0_12_4(8) => prdata_o_1_0_iv_0_12_4(8), 
        prdata_o_1_2_0_a2_17_0(1) => prdata_o_1_2_0_a2_17_0(1), 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0) => 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0), 
        prdata_o_1_iv_0_0_a2_45_0(0) => 
        prdata_o_1_iv_0_0_a2_45_0(0), prdata_o_1_0_iv_0_1_0 => 
        prdata_o_1_0_iv_0_1(7), prdata_o_1_iv_0_0_4_2_1_0(3) => 
        prdata_o_1_iv_0_0_4_2_1_0(3), prdata_o_1_iv_0_0_12_4_2(3)
         => prdata_o_1_iv_0_0_12_4_2(3), 
        prdata_o_1_iv_0_0_12_5_0(3) => 
        prdata_o_1_iv_0_0_12_5_0(3), prdata_o_1_iv_0_0_a2_26_0(1)
         => prdata_o_1_iv_0_0_a2_26_0(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), 
        MC_System_0_AMBA_SLAVE_1_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), 
        MC_System_0_AMBA_SLAVE_1_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), 
        MC_System_0_AMBA_SLAVE_1_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        MC_System_0_AMBA_SLAVE_1_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), 
        MC_System_0_AMBA_SLAVE_1_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), 
        MC_System_0_AMBA_SLAVE_1_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), 
        MC_System_0_AMBA_SLAVE_1_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), 
        MC_System_0_AMBA_SLAVE_1_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        MC_System_0_AMBA_SLAVE_1_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        MC_System_0_AMBA_SLAVE_1_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        prdata_o_1_iv_0_0_a2_24_0(1) => 
        prdata_o_1_iv_0_0_a2_24_0(1), FOC_TRANSFORMS_0_vbeta_o_16
         => FOC_TRANSFORMS_0_vbeta_o(17), 
        FOC_TRANSFORMS_0_vbeta_o_15 => 
        FOC_TRANSFORMS_0_vbeta_o(16), FOC_TRANSFORMS_0_vbeta_o_10
         => FOC_TRANSFORMS_0_vbeta_o(11), 
        FOC_TRANSFORMS_0_vbeta_o_12 => 
        FOC_TRANSFORMS_0_vbeta_o(13), FOC_TRANSFORMS_0_vbeta_o_5
         => FOC_TRANSFORMS_0_vbeta_o(6), 
        FOC_TRANSFORMS_0_vbeta_o_0 => FOC_TRANSFORMS_0_vbeta_o(1), 
        FOC_TRANSFORMS_0_vbeta_o_13 => 
        FOC_TRANSFORMS_0_vbeta_o(14), FOC_TRANSFORMS_0_vbeta_o_8
         => FOC_TRANSFORMS_0_vbeta_o(9), 
        FOC_TRANSFORMS_0_vbeta_o_3 => FOC_TRANSFORMS_0_vbeta_o(4), 
        prdata_o_1_0_iv_0_a2_6_2_2 => prdata_o_1_0_iv_0_a2_6_2_0, 
        prdata_o_1_0_iv_0_a2_6_2_5 => prdata_o_1_0_iv_0_a2_6_2_3, 
        prdata_o_1_0_iv_0_a2_6_2_7 => prdata_o_1_0_iv_0_a2_6_2_5, 
        prdata_o_1_0_iv_0_a2_20_0(10) => 
        prdata_o_1_0_iv_0_a2_20_0(10), 
        prdata_o_1_0_iv_0_a2_19_0(10) => 
        prdata_o_1_0_iv_0_a2_19_0(10), 
        prdata_o_1_iv_0_0_a2_14_1(1) => 
        prdata_o_1_iv_0_0_a2_14_1(1), prdata_o_1_0_iv_0_0_0_0(10)
         => prdata_o_1_0_iv_0_0_0_0(10), prdata_o_1_0_iv_0_0_0_7
         => prdata_o_1_0_iv_0_0_0_7, prdata_o_1_0_iv_0_0_0_1 => 
        prdata_o_1_0_iv_0_0_0_1, prdata_o_1_0_iv_0_0_0_5 => 
        prdata_o_1_0_iv_0_0_0_5, prdata_o_1_0_iv_0_0_0_4 => 
        prdata_o_1_0_iv_0_0_0_4, prdata_o_1_0_iv_0_0_0_0_d0 => 
        prdata_o_1_0_iv_0_0_0_0_d0, prdata_o_1_0_iv_0_0_0_2 => 
        prdata_o_1_0_iv_0_0_0_2, prdata_o_1_0_iv_0_1_1(10) => 
        prdata_o_1_0_iv_0_1_1(10), prdata_o_1_0_iv_0_12_1(7) => 
        prdata_o_1_0_iv_0_12_1(7), prdata_o_1_iv_0_0_0_2_tz_tz(0)
         => prdata_o_1_iv_0_0_0_2_tz_tz(0), prdata_o_1_0_iv_0_3_0
         => prdata_o_1_0_iv_0_3_0, prdata_o_1_0_iv_0_3_3 => 
        prdata_o_1_0_iv_0_3_3, 
        adc_measurements_0_adc_result_ch3_o_2 => 
        adc_measurements_0_adc_result_ch3_o(2), 
        adc_measurements_0_adc_result_ch3_o_11 => 
        adc_measurements_0_adc_result_ch3_o(11), 
        adc_measurements_0_adc_result_ch3_o_5 => 
        adc_measurements_0_adc_result_ch3_o(5), 
        adc_measurements_0_adc_result_ch3_o_9 => 
        adc_measurements_0_adc_result_ch3_o(9), 
        adc_measurements_0_adc_result_ch3_o_8 => 
        adc_measurements_0_adc_result_ch3_o(8), 
        adc_measurements_0_adc_result_ch3_o_4 => 
        adc_measurements_0_adc_result_ch3_o(4), 
        adc_measurements_0_adc_result_ch3_o_10 => 
        adc_measurements_0_adc_result_ch3_o(10), 
        adc_measurements_0_adc_result_ch3_o_6 => 
        adc_measurements_0_adc_result_ch3_o(6), 
        adc_measurements_0_adc_result_ch3_o_0 => 
        adc_measurements_0_adc_result_ch3_o(0), 
        adc_measurements_0_adc_result_ch3_o_7 => 
        adc_measurements_0_adc_result_ch3_o(7), 
        adc_measurements_0_adc_result_ch3_o_3 => 
        adc_measurements_0_adc_result_ch3_o(3), 
        SEQ_CONTROLLER_1_state_o_0_3 => 
        SEQ_CONTROLLER_1_state_o_0(3), 
        SEQ_CONTROLLER_1_state_o_0_0 => 
        SEQ_CONTROLLER_1_state_o_0(0), 
        SEQ_CONTROLLER_1_state_o_0_2 => 
        SEQ_CONTROLLER_1_state_o_0(2), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(17) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(17), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(16) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(16), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(15) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(15), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(14) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(14), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(13) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(13), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(12) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(12), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(11) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(11), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(10) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(10), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(9) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(9), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(8) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(8), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(7) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(7), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(6) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(6), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(5) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(5), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(4) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(4), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(3) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(3), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(2) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(2), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(17) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(17), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(16) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(16), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(15) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(15), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(14) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(14), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(13) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(13), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(12) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(12), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(11) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(11), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(10) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(10), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(9) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(9), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(8) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(8), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(7) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(7), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(6) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(6), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(5) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(5), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(4) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(4), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(3) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(3), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(2) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(2), 
        prdata_o_1_0_iv_0_1_6_tz(10) => 
        prdata_o_1_0_iv_0_1_6_tz(10), prdata_o_1_0_iv_0_2_tz_0
         => prdata_o_1_0_iv_0_2_tz_0, prdata_o_1_0_iv_0_2_tz_4
         => prdata_o_1_0_iv_0_2_tz_4, prdata_o_1_0_iv_0_2_tz_1
         => prdata_o_1_0_iv_0_2_tz_1, prdata_o_1_iv_0_0_0_3_tz(1)
         => prdata_o_1_iv_0_0_0_3_tz(1), 
        STEPPER_THETA_0_theta_output_o(17) => 
        \STEPPER_THETA_0_theta_output_o_17\, 
        STEPPER_THETA_0_theta_output_o(16) => 
        STEPPER_THETA_0_theta_output_o(16), 
        STEPPER_THETA_0_theta_output_o(15) => 
        STEPPER_THETA_0_theta_output_o(15), 
        STEPPER_THETA_0_theta_output_o(14) => 
        STEPPER_THETA_0_theta_output_o(14), 
        STEPPER_THETA_0_theta_output_o(13) => 
        STEPPER_THETA_0_theta_output_o(13), 
        STEPPER_THETA_0_theta_output_o(12) => 
        STEPPER_THETA_0_theta_output_o(12), 
        STEPPER_THETA_0_theta_output_o(11) => 
        STEPPER_THETA_0_theta_output_o(11), 
        STEPPER_THETA_0_theta_output_o(10) => 
        STEPPER_THETA_0_theta_output_o(10), 
        STEPPER_THETA_0_theta_output_o(9) => 
        STEPPER_THETA_0_theta_output_o(9), 
        STEPPER_THETA_0_theta_output_o(8) => 
        STEPPER_THETA_0_theta_output_o(8), 
        STEPPER_THETA_0_theta_output_o(7) => 
        STEPPER_THETA_0_theta_output_o(7), 
        STEPPER_THETA_0_theta_output_o(6) => 
        STEPPER_THETA_0_theta_output_o(6), 
        STEPPER_THETA_0_theta_output_o(5) => 
        STEPPER_THETA_0_theta_output_o(5), 
        STEPPER_THETA_0_theta_output_o(4) => 
        STEPPER_THETA_0_theta_output_o(4), 
        STEPPER_THETA_0_theta_output_o(3) => 
        STEPPER_THETA_0_theta_output_o(3), 
        STEPPER_THETA_0_theta_output_o(2) => 
        STEPPER_THETA_0_theta_output_o(2), 
        STEPPER_THETA_0_theta_output_o(1) => 
        STEPPER_THETA_0_theta_output_o(1), 
        STEPPER_THETA_0_theta_output_o(0) => 
        STEPPER_THETA_0_theta_output_o(0), 
        FOC_TRANSFORMS_1_valpha_o_16 => 
        FOC_TRANSFORMS_1_valpha_o(17), 
        FOC_TRANSFORMS_1_valpha_o_0 => 
        FOC_TRANSFORMS_1_valpha_o(1), FOC_TRANSFORMS_1_valpha_o_2
         => FOC_TRANSFORMS_1_valpha_o(3), 
        FOC_TRANSFORMS_1_valpha_o_11 => 
        FOC_TRANSFORMS_1_valpha_o(12), 
        FOC_TRANSFORMS_1_valpha_o_14 => 
        FOC_TRANSFORMS_1_valpha_o(15), 
        FOC_TRANSFORMS_1_valpha_o_15 => 
        FOC_TRANSFORMS_1_valpha_o(16), 
        FOC_TRANSFORMS_1_valpha_o_13 => 
        FOC_TRANSFORMS_1_valpha_o(14), 
        FOC_TRANSFORMS_1_valpha_o_12 => 
        FOC_TRANSFORMS_1_valpha_o(13), 
        FOC_TRANSFORMS_1_valpha_o_1 => 
        FOC_TRANSFORMS_1_valpha_o(2), 
        prdata_o_1_0_iv_0_1_o2_0(17) => 
        prdata_o_1_0_iv_0_1_o2_0(17), 
        adc_interface_0_result_ch2_o(11) => 
        adc_interface_0_result_ch2_o(11), 
        adc_interface_0_result_ch2_o(10) => 
        adc_interface_0_result_ch2_o(10), 
        adc_interface_0_result_ch2_o(9) => 
        adc_interface_0_result_ch2_o(9), 
        adc_interface_0_result_ch2_o(8) => 
        adc_interface_0_result_ch2_o(8), 
        adc_interface_0_result_ch2_o(7) => 
        adc_interface_0_result_ch2_o(7), 
        adc_interface_0_result_ch2_o(6) => 
        adc_interface_0_result_ch2_o(6), 
        adc_interface_0_result_ch2_o(5) => 
        adc_interface_0_result_ch2_o(5), 
        adc_interface_0_result_ch2_o(4) => 
        adc_interface_0_result_ch2_o(4), 
        adc_interface_0_result_ch2_o(3) => 
        adc_interface_0_result_ch2_o(3), 
        adc_interface_0_result_ch2_o(2) => 
        adc_interface_0_result_ch2_o(2), 
        adc_interface_0_result_ch2_o(1) => 
        adc_interface_0_result_ch2_o(1), 
        adc_interface_0_result_ch2_o(0) => 
        adc_interface_0_result_ch2_o(0), prdata_o_1_0_iv_0_0_0_d0
         => prdata_o_1_0_iv_0_0(7), 
        adc_interface_0_result_ch0_o_3 => 
        adc_interface_0_result_ch0_o(4), 
        adc_interface_0_result_ch0_o_1 => 
        adc_interface_0_result_ch0_o(2), 
        adc_interface_0_result_ch0_o_9 => 
        adc_interface_0_result_ch0_o(10), 
        adc_interface_0_result_ch0_o_2 => 
        adc_interface_0_result_ch0_o(3), 
        adc_interface_0_result_ch0_o_0 => 
        adc_interface_0_result_ch0_o(1), 
        STEPPER_THETA_1_step_count_o_7 => 
        STEPPER_THETA_1_step_count_o(7), 
        STEPPER_THETA_1_step_count_o_0 => 
        STEPPER_THETA_1_step_count_o(0), 
        STEPPER_THETA_1_step_count_o_4 => 
        STEPPER_THETA_1_step_count_o(4), 
        STEPPER_THETA_1_step_count_o_2 => 
        STEPPER_THETA_1_step_count_o(2), 
        STEPPER_THETA_1_step_count_o_10 => 
        STEPPER_THETA_1_step_count_o(10), 
        STEPPER_THETA_1_step_count_o_8 => 
        STEPPER_THETA_1_step_count_o(8), 
        STEPPER_THETA_1_step_count_o_5 => 
        STEPPER_THETA_1_step_count_o(5), 
        STEPPER_THETA_1_step_count_o_3 => 
        STEPPER_THETA_1_step_count_o(3), 
        STEPPER_THETA_1_step_count_o_1 => 
        STEPPER_THETA_1_step_count_o(1), 
        STEPPER_THETA_1_step_count_o_13 => 
        STEPPER_THETA_1_step_count_o(13), 
        STEPPER_THETA_1_step_count_o_16 => 
        STEPPER_THETA_1_step_count_o(16), 
        STEPPER_THETA_1_step_count_o_14 => 
        STEPPER_THETA_1_step_count_o(14), 
        STEPPER_THETA_1_step_count_o_17 => 
        STEPPER_THETA_1_step_count_o(17), 
        STEPPER_THETA_1_step_count_o_22 => 
        STEPPER_THETA_1_step_count_o(22), 
        STEPPER_THETA_1_step_count_o_21 => 
        STEPPER_THETA_1_step_count_o(21), 
        STEPPER_THETA_1_step_count_o_20 => 
        STEPPER_THETA_1_step_count_o(20), 
        STEPPER_THETA_1_step_count_o_19 => 
        STEPPER_THETA_1_step_count_o(19), 
        STEPPER_THETA_1_step_count_o_18 => 
        STEPPER_THETA_1_step_count_o(18), 
        adc_measurements_0_adc_result_ch1_o_2 => 
        adc_measurements_0_adc_result_ch1_o(4), 
        adc_measurements_0_adc_result_ch1_o_1 => 
        adc_measurements_0_adc_result_ch1_o(3), 
        adc_measurements_0_adc_result_ch1_o_0 => 
        adc_measurements_0_adc_result_ch1_o(2), 
        adc_measurements_0_adc_result_ch1_o_9 => 
        adc_measurements_0_adc_result_ch1_o(11), 
        adc_measurements_0_adc_result_ch1_o_4 => 
        adc_measurements_0_adc_result_ch1_o(6), 
        prdata_o_1_iv_0_0_11(3) => prdata_o_1_iv_0_0_11(3), 
        prdata_o_1_0_iv_0_5_5 => prdata_o_1_0_iv_0_5_5, 
        prdata_o_1_0_iv_0_5_7 => prdata_o_1_0_iv_0_5_7, 
        prdata_o_1_0_iv_0_5_2 => prdata_o_1_0_iv_0_5_2, 
        prdata_o_1_0_iv_0_5_0 => prdata_o_1_0_iv_0_5_0, 
        prdata_o_1_0_iv_0_5_4 => prdata_o_1_0_iv_0_5_4, 
        prdata_o_1_0_iv_0_5_1 => prdata_o_1_0_iv_0_5_1, 
        prdata_o_1_0_iv_0_5_12 => prdata_o_1_0_iv_0_5_12, 
        ADC_SCALING_0_ib_adc_o_13 => ADC_SCALING_0_ib_adc_o(13), 
        ADC_SCALING_0_ib_adc_o_17 => ADC_SCALING_0_ib_adc_o(17), 
        ADC_SCALING_0_ib_adc_o_2 => ADC_SCALING_0_ib_adc_o(2), 
        ADC_SCALING_0_ib_adc_o_10 => ADC_SCALING_0_ib_adc_o(10), 
        ADC_SCALING_0_ib_adc_o_7 => ADC_SCALING_0_ib_adc_o(7), 
        ADC_SCALING_0_ib_adc_o_3 => ADC_SCALING_0_ib_adc_o(3), 
        ADC_SCALING_0_ib_adc_o_0 => ADC_SCALING_0_ib_adc_o(0), 
        ADC_SCALING_0_ib_adc_o_16 => ADC_SCALING_0_ib_adc_o(16), 
        ADC_SCALING_0_ib_adc_o_14 => ADC_SCALING_0_ib_adc_o(14), 
        prdata_o_1_iv_0_0_12_4_3(3) => 
        prdata_o_1_iv_0_0_12_4_3(3), prdata_o_1_0_iv_0_6_3 => 
        prdata_o_1_0_iv_0_6(16), FOC_TRANSFORMS_0_iq_o_13 => 
        FOC_TRANSFORMS_0_iq_o(17), FOC_TRANSFORMS_0_iq_o_5 => 
        FOC_TRANSFORMS_0_iq_o(9), FOC_TRANSFORMS_0_iq_o_0 => 
        FOC_TRANSFORMS_0_iq_o(4), FOC_TRANSFORMS_0_iq_o_9 => 
        FOC_TRANSFORMS_0_iq_o(13), FOC_TRANSFORMS_0_iq_o_12 => 
        FOC_TRANSFORMS_0_iq_o(16), FOC_TRANSFORMS_0_iq_o_10 => 
        FOC_TRANSFORMS_0_iq_o(14), FOC_TRANSFORMS_0_id_o_16 => 
        FOC_TRANSFORMS_0_id_o(17), FOC_TRANSFORMS_0_id_o_2 => 
        FOC_TRANSFORMS_0_id_o(3), FOC_TRANSFORMS_0_id_o_0 => 
        FOC_TRANSFORMS_0_id_o(1), FOC_TRANSFORMS_0_id_o_10 => 
        FOC_TRANSFORMS_0_id_o(11), FOC_TRANSFORMS_0_id_o_3 => 
        FOC_TRANSFORMS_0_id_o(4), FOC_TRANSFORMS_0_id_o_5 => 
        FOC_TRANSFORMS_0_id_o(6), FOC_TRANSFORMS_0_id_o_15 => 
        FOC_TRANSFORMS_0_id_o(16), FOC_TRANSFORMS_0_id_o_13 => 
        FOC_TRANSFORMS_0_id_o(14), FOC_TRANSFORMS_0_id_o_1 => 
        FOC_TRANSFORMS_0_id_o(2), FOC_TRANSFORMS_0_id_o_12 => 
        FOC_TRANSFORMS_0_id_o(13), ADC_SCALING_0_ia_adc_o_0 => 
        ADC_SCALING_0_ia_adc_o(3), ADC_SCALING_0_ia_adc_o_10 => 
        ADC_SCALING_0_ia_adc_o(13), ADC_SCALING_0_ia_adc_o_14 => 
        ADC_SCALING_0_ia_adc_o(17), ADC_SCALING_0_ia_adc_o_13 => 
        ADC_SCALING_0_ia_adc_o(16), ADC_SCALING_0_ia_adc_o_11 => 
        ADC_SCALING_0_ia_adc_o(14), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FAB_CCC_GL1 => MC_System_0_FAB_CCC_GL1, 
        apb3_if_st_0_theta_gen_mode_o => 
        apb3_if_st_0_theta_gen_mode_o, apb3_if_st_0_stop_motor_o
         => apb3_if_st_0_stop_motor_o, apb3_if_st_0_start_motor_o
         => apb3_if_st_0_start_motor_o, N_503 => N_503, N_500 => 
        N_500, N_505 => N_505, N_240 => N_240, N_514 => N_514, 
        N_507 => N_507, N_509 => N_509, N_506 => N_506, N_522 => 
        N_522, N_542 => N_542, N_516 => N_516, N_502 => N_502, 
        prdata_m2_e_0 => prdata_m2_e_0, N_519 => N_519, N_540 => 
        N_540, N_544 => N_544, N_517 => N_517, N_128 => N_128, 
        m20_m2_0_a2_1 => m20_m2_0_a2_1, prdata_m1_e_11_0 => 
        prdata_m1_e_11_0, prdata_m1_0_a2_2_0 => 
        prdata_m1_0_a2_2_0, N_513 => N_513, prdata_m3_i_0 => 
        prdata_m3_i_0, prdata_m2_0_a2_0 => prdata_m2_0_a2_0, 
        prdata_m2_e_0_0 => prdata_m2_e_0_0, m20_i_a2_5_0 => 
        m20_i_a2_5_0, prdata_m1_0_a2_0 => prdata_m1_0_a2_0, 
        m20_i_a2_0_1 => m20_i_a2_0_1, prdata_m4_e_0 => 
        prdata_m4_e_0, N_518 => N_518, N_533 => N_533, N_397 => 
        N_397, N_355 => N_355, N_531 => N_531, N_527 => N_527, 
        N_529 => N_529, N_508 => N_508, m20_i_2_tz => m20_i_2_tz, 
        N_494 => N_494, N_454 => N_454, N_414 => N_414, N_198 => 
        N_198, m20_i_11_5 => m20_i_11_5, prdata_N_7_2 => 
        prdata_N_7_2, N_349 => N_349, N_534 => N_534, N_260 => 
        N_260, N_363 => N_363, N_377 => N_377, N_405 => N_405, 
        N_455 => N_455, N_495 => N_495, N_524 => N_524, N_528 => 
        N_528, m20_i_10_1 => m20_i_10_1, m20_i_10_0 => m20_i_10_0, 
        MC_System_0_AMBA_SLAVE_1_PWRITE => 
        MC_System_0_AMBA_SLAVE_1_PWRITE, 
        MC_System_0_AMBA_SLAVE_1_PSELx => 
        MC_System_0_AMBA_SLAVE_1_PSELx, 
        MC_System_0_AMBA_SLAVE_1_PENABLE => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, N_215 => N_215, N_315
         => N_315, N_317 => N_317, N_318 => N_318, N_319 => N_319, 
        N_320 => N_320, N_321 => N_321, N_354 => N_354, N_396 => 
        N_396, N_122 => N_122, N_549 => N_549);
    
    MSC_i_44 : ADC_SCALING_1
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FAB_CCC_GL1, adc_results_rdy_i => 
        adc_interface_0_results_rdy_o, adc_scale_val_i(17) => 
        apb3_if_st_0_adc_scale_val_o(17), adc_scale_val_i(16) => 
        apb3_if_st_0_adc_scale_val_o(16), adc_scale_val_i(15) => 
        apb3_if_st_0_adc_scale_val_o(15), adc_scale_val_i(14) => 
        apb3_if_st_0_adc_scale_val_o(14), adc_scale_val_i(13) => 
        apb3_if_st_0_adc_scale_val_o(13), adc_scale_val_i(12) => 
        apb3_if_st_0_adc_scale_val_o(12), adc_scale_val_i(11) => 
        apb3_if_st_0_adc_scale_val_o(11), adc_scale_val_i(10) => 
        apb3_if_st_0_adc_scale_val_o(10), adc_scale_val_i(9) => 
        apb3_if_st_0_adc_scale_val_o(9), adc_scale_val_i(8) => 
        apb3_if_st_0_adc_scale_val_o(8), adc_scale_val_i(7) => 
        apb3_if_st_0_adc_scale_val_o(7), adc_scale_val_i(6) => 
        apb3_if_st_0_adc_scale_val_o(6), adc_scale_val_i(5) => 
        apb3_if_st_0_adc_scale_val_o(5), adc_scale_val_i(4) => 
        apb3_if_st_0_adc_scale_val_o(4), adc_scale_val_i(3) => 
        apb3_if_st_0_adc_scale_val_o(3), adc_scale_val_i(2) => 
        apb3_if_st_0_adc_scale_val_o(2), adc_scale_val_i(1) => 
        apb3_if_st_0_adc_scale_val_o(1), adc_scale_val_i(0) => 
        apb3_if_st_0_adc_scale_val_o(0), adc_result_ch0_i(11) => 
        \adc_interface_0_result_ch0_o_11\, adc_result_ch0_i(10)
         => adc_interface_0_result_ch0_o(10), adc_result_ch0_i(9)
         => \adc_interface_0_result_ch0_o_9\, adc_result_ch0_i(8)
         => \adc_interface_0_result_ch0_o_8\, adc_result_ch0_i(7)
         => \adc_interface_0_result_ch0_o_7\, adc_result_ch0_i(6)
         => \adc_interface_0_result_ch0_o_6\, adc_result_ch0_i(5)
         => \adc_interface_0_result_ch0_o_5\, adc_result_ch0_i(4)
         => adc_interface_0_result_ch0_o(4), adc_result_ch0_i(3)
         => adc_interface_0_result_ch0_o(3), adc_result_ch0_i(2)
         => adc_interface_0_result_ch0_o(2), adc_result_ch0_i(1)
         => adc_interface_0_result_ch0_o(1), adc_result_ch0_i(0)
         => \adc_interface_0_result_ch0_o_0\, 
        adc_result_ch1_i(11) => adc_interface_0_result_ch2_o(11), 
        adc_result_ch1_i(10) => adc_interface_0_result_ch2_o(10), 
        adc_result_ch1_i(9) => adc_interface_0_result_ch2_o(9), 
        adc_result_ch1_i(8) => adc_interface_0_result_ch2_o(8), 
        adc_result_ch1_i(7) => adc_interface_0_result_ch2_o(7), 
        adc_result_ch1_i(6) => adc_interface_0_result_ch2_o(6), 
        adc_result_ch1_i(5) => adc_interface_0_result_ch2_o(5), 
        adc_result_ch1_i(4) => adc_interface_0_result_ch2_o(4), 
        adc_result_ch1_i(3) => adc_interface_0_result_ch2_o(3), 
        adc_result_ch1_i(2) => adc_interface_0_result_ch2_o(2), 
        adc_result_ch1_i(1) => adc_interface_0_result_ch2_o(1), 
        adc_result_ch1_i(0) => adc_interface_0_result_ch2_o(0), 
        fault_threshold_i(17) => apb3_if_st_0_adc_oc_thresh_o(17), 
        fault_threshold_i(16) => apb3_if_st_0_adc_oc_thresh_o(16), 
        fault_threshold_i(15) => apb3_if_st_0_adc_oc_thresh_o(15), 
        fault_threshold_i(14) => apb3_if_st_0_adc_oc_thresh_o(14), 
        fault_threshold_i(13) => apb3_if_st_0_adc_oc_thresh_o(13), 
        fault_threshold_i(12) => apb3_if_st_0_adc_oc_thresh_o(12), 
        fault_threshold_i(11) => apb3_if_st_0_adc_oc_thresh_o(11), 
        fault_threshold_i(10) => apb3_if_st_0_adc_oc_thresh_o(10), 
        fault_threshold_i(9) => apb3_if_st_0_adc_oc_thresh_o(9), 
        fault_threshold_i(8) => apb3_if_st_0_adc_oc_thresh_o(8), 
        fault_threshold_i(7) => apb3_if_st_0_adc_oc_thresh_o(7), 
        fault_threshold_i(6) => apb3_if_st_0_adc_oc_thresh_o(6), 
        fault_threshold_i(5) => apb3_if_st_0_adc_oc_thresh_o(5), 
        fault_threshold_i(4) => apb3_if_st_0_adc_oc_thresh_o(4), 
        fault_threshold_i(3) => apb3_if_st_0_adc_oc_thresh_o(3), 
        fault_threshold_i(2) => apb3_if_st_0_adc_oc_thresh_o(2), 
        fault_threshold_i(1) => apb3_if_st_0_adc_oc_thresh_o(1), 
        fault_threshold_i(0) => apb3_if_st_0_adc_oc_thresh_o(0), 
        done_o => ADC_SCALING_0_done_o, calib_done_o => 
        ADC_SCALING_0_calib_done_o, over_current_fault_o => 
        ADC_SCALING_0_over_current_fault_o, ia_adc_o(17) => 
        ADC_SCALING_0_ia_adc_o(17), ia_adc_o(16) => 
        ADC_SCALING_0_ia_adc_o(16), ia_adc_o(15) => 
        \ADC_SCALING_0_ia_adc_o_15\, ia_adc_o(14) => 
        ADC_SCALING_0_ia_adc_o(14), ia_adc_o(13) => 
        ADC_SCALING_0_ia_adc_o(13), ia_adc_o(12) => 
        \ADC_SCALING_0_ia_adc_o_12\, ia_adc_o(11) => 
        \ADC_SCALING_0_ia_adc_o_11\, ia_adc_o(10) => 
        \ADC_SCALING_0_ia_adc_o_10\, ia_adc_o(9) => 
        \ADC_SCALING_0_ia_adc_o_9\, ia_adc_o(8) => 
        \ADC_SCALING_0_ia_adc_o_8\, ia_adc_o(7) => 
        \ADC_SCALING_0_ia_adc_o_7\, ia_adc_o(6) => 
        \ADC_SCALING_0_ia_adc_o_6\, ia_adc_o(5) => 
        \ADC_SCALING_0_ia_adc_o_5\, ia_adc_o(4) => 
        \ADC_SCALING_0_ia_adc_o_4\, ia_adc_o(3) => 
        ADC_SCALING_0_ia_adc_o(3), ia_adc_o(2) => 
        \ADC_SCALING_0_ia_adc_o_2\, ia_adc_o(1) => 
        \ADC_SCALING_0_ia_adc_o_1\, ia_adc_o(0) => 
        ADC_SCALING_0_ia_adc_o_0, ib_adc_o(17) => 
        ADC_SCALING_0_ib_adc_o(17), ib_adc_o(16) => 
        ADC_SCALING_0_ib_adc_o(16), ib_adc_o(15) => 
        \ADC_SCALING_0_ib_adc_o_15\, ib_adc_o(14) => 
        ADC_SCALING_0_ib_adc_o(14), ib_adc_o(13) => 
        ADC_SCALING_0_ib_adc_o(13), ib_adc_o(12) => 
        \ADC_SCALING_0_ib_adc_o_12\, ib_adc_o(11) => 
        \ADC_SCALING_0_ib_adc_o_11\, ib_adc_o(10) => 
        ADC_SCALING_0_ib_adc_o(10), ib_adc_o(9) => 
        \ADC_SCALING_0_ib_adc_o_9\, ib_adc_o(8) => 
        \ADC_SCALING_0_ib_adc_o_8\, ib_adc_o(7) => 
        ADC_SCALING_0_ib_adc_o(7), ib_adc_o(6) => 
        \ADC_SCALING_0_ib_adc_o_6\, ib_adc_o(5) => 
        \ADC_SCALING_0_ib_adc_o_5\, ib_adc_o(4) => 
        \ADC_SCALING_0_ib_adc_o_4\, ib_adc_o(3) => 
        ADC_SCALING_0_ib_adc_o(3), ib_adc_o(2) => 
        ADC_SCALING_0_ib_adc_o(2), ib_adc_o(1) => 
        \ADC_SCALING_0_ib_adc_o_1\, ib_adc_o(0) => 
        ADC_SCALING_0_ib_adc_o(0));
    
    MSC_i_48 : SPEED_ID_IQ_PI_1
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FAB_CCC_GL1, clear_buffer_i => 
        SEQ_CONTROLLER_1_motor_stopped_o, speed_en_i => \GND\, 
        idq_en_i => SEQ_CONTROLLER_1_en_idq_pi_o, 
        speed_pi_start_i => \GND\, id_pi_start_i => 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, iq_pi_start_i => 
        FOC_TRANSFORMS_0_park_done_o, speed_init_i(17) => \GND\, 
        speed_init_i(16) => \GND\, speed_init_i(15) => \GND\, 
        speed_init_i(14) => \GND\, speed_init_i(13) => \GND\, 
        speed_init_i(12) => \GND\, speed_init_i(11) => \GND\, 
        speed_init_i(10) => \GND\, speed_init_i(9) => \GND\, 
        speed_init_i(8) => \GND\, speed_init_i(7) => \GND\, 
        speed_init_i(6) => \GND\, speed_init_i(5) => \GND\, 
        speed_init_i(4) => \GND\, speed_init_i(3) => \GND\, 
        speed_init_i(2) => \GND\, speed_init_i(1) => \GND\, 
        speed_init_i(0) => \GND\, id_init_i(17) => 
        apb3_if_st_0_sqmng_dv_o(17), id_init_i(16) => 
        apb3_if_st_0_sqmng_dv_o(16), id_init_i(15) => 
        apb3_if_st_0_sqmng_dv_o(15), id_init_i(14) => 
        apb3_if_st_0_sqmng_dv_o(14), id_init_i(13) => 
        apb3_if_st_0_sqmng_dv_o(13), id_init_i(12) => 
        apb3_if_st_0_sqmng_dv_o(12), id_init_i(11) => 
        apb3_if_st_0_sqmng_dv_o(11), id_init_i(10) => 
        apb3_if_st_0_sqmng_dv_o(10), id_init_i(9) => 
        apb3_if_st_0_sqmng_dv_o(9), id_init_i(8) => 
        apb3_if_st_0_sqmng_dv_o(8), id_init_i(7) => 
        apb3_if_st_0_sqmng_dv_o(7), id_init_i(6) => 
        apb3_if_st_0_sqmng_dv_o(6), id_init_i(5) => 
        apb3_if_st_0_sqmng_dv_o(5), id_init_i(4) => 
        apb3_if_st_0_sqmng_dv_o(4), id_init_i(3) => 
        apb3_if_st_0_sqmng_dv_o(3), id_init_i(2) => 
        apb3_if_st_0_sqmng_dv_o(2), id_init_i(1) => 
        apb3_if_st_0_sqmng_dv_o(1), id_init_i(0) => 
        apb3_if_st_0_sqmng_dv_o(0), iq_init_i(17) => \GND\, 
        iq_init_i(16) => \GND\, iq_init_i(15) => \GND\, 
        iq_init_i(14) => \GND\, iq_init_i(13) => \GND\, 
        iq_init_i(12) => \GND\, iq_init_i(11) => \GND\, 
        iq_init_i(10) => \GND\, iq_init_i(9) => \GND\, 
        iq_init_i(8) => \GND\, iq_init_i(7) => \GND\, 
        iq_init_i(6) => \GND\, iq_init_i(5) => \GND\, 
        iq_init_i(4) => \GND\, iq_init_i(3) => \GND\, 
        iq_init_i(2) => \GND\, iq_init_i(1) => \GND\, 
        iq_init_i(0) => \GND\, speed_pi_ref_input_i(17) => \GND\, 
        speed_pi_ref_input_i(16) => \GND\, 
        speed_pi_ref_input_i(15) => \GND\, 
        speed_pi_ref_input_i(14) => \GND\, 
        speed_pi_ref_input_i(13) => \GND\, 
        speed_pi_ref_input_i(12) => \GND\, 
        speed_pi_ref_input_i(11) => \GND\, 
        speed_pi_ref_input_i(10) => \GND\, 
        speed_pi_ref_input_i(9) => \GND\, speed_pi_ref_input_i(8)
         => \GND\, speed_pi_ref_input_i(7) => \GND\, 
        speed_pi_ref_input_i(6) => \GND\, speed_pi_ref_input_i(5)
         => \GND\, speed_pi_ref_input_i(4) => \GND\, 
        speed_pi_ref_input_i(3) => \GND\, speed_pi_ref_input_i(2)
         => \GND\, speed_pi_ref_input_i(1) => \GND\, 
        speed_pi_ref_input_i(0) => \GND\, 
        speed_pi_act_input_i(17) => \GND\, 
        speed_pi_act_input_i(16) => \GND\, 
        speed_pi_act_input_i(15) => \GND\, 
        speed_pi_act_input_i(14) => \GND\, 
        speed_pi_act_input_i(13) => \GND\, 
        speed_pi_act_input_i(12) => \GND\, 
        speed_pi_act_input_i(11) => \GND\, 
        speed_pi_act_input_i(10) => \GND\, 
        speed_pi_act_input_i(9) => \GND\, speed_pi_act_input_i(8)
         => \GND\, speed_pi_act_input_i(7) => \GND\, 
        speed_pi_act_input_i(6) => \GND\, speed_pi_act_input_i(5)
         => \GND\, speed_pi_act_input_i(4) => \GND\, 
        speed_pi_act_input_i(3) => \GND\, speed_pi_act_input_i(2)
         => \GND\, speed_pi_act_input_i(1) => \GND\, 
        speed_pi_act_input_i(0) => \GND\, speed_pi_kp_i(17) => 
        \GND\, speed_pi_kp_i(16) => \GND\, speed_pi_kp_i(15) => 
        \GND\, speed_pi_kp_i(14) => \GND\, speed_pi_kp_i(13) => 
        \GND\, speed_pi_kp_i(12) => \GND\, speed_pi_kp_i(11) => 
        \GND\, speed_pi_kp_i(10) => \GND\, speed_pi_kp_i(9) => 
        \GND\, speed_pi_kp_i(8) => \GND\, speed_pi_kp_i(7) => 
        \GND\, speed_pi_kp_i(6) => \GND\, speed_pi_kp_i(5) => 
        \GND\, speed_pi_kp_i(4) => \GND\, speed_pi_kp_i(3) => 
        \GND\, speed_pi_kp_i(2) => \GND\, speed_pi_kp_i(1) => 
        \GND\, speed_pi_kp_i(0) => \GND\, speed_pi_ki_i(17) => 
        \GND\, speed_pi_ki_i(16) => \GND\, speed_pi_ki_i(15) => 
        \GND\, speed_pi_ki_i(14) => \GND\, speed_pi_ki_i(13) => 
        \GND\, speed_pi_ki_i(12) => \GND\, speed_pi_ki_i(11) => 
        \GND\, speed_pi_ki_i(10) => \GND\, speed_pi_ki_i(9) => 
        \GND\, speed_pi_ki_i(8) => \GND\, speed_pi_ki_i(7) => 
        \GND\, speed_pi_ki_i(6) => \GND\, speed_pi_ki_i(5) => 
        \GND\, speed_pi_ki_i(4) => \GND\, speed_pi_ki_i(3) => 
        \GND\, speed_pi_ki_i(2) => \GND\, speed_pi_ki_i(1) => 
        \GND\, speed_pi_ki_i(0) => \GND\, speed_pi_ymax_i(17) => 
        \GND\, speed_pi_ymax_i(16) => \GND\, speed_pi_ymax_i(15)
         => \GND\, speed_pi_ymax_i(14) => \GND\, 
        speed_pi_ymax_i(13) => \GND\, speed_pi_ymax_i(12) => 
        \GND\, speed_pi_ymax_i(11) => \GND\, speed_pi_ymax_i(10)
         => \GND\, speed_pi_ymax_i(9) => \GND\, 
        speed_pi_ymax_i(8) => \GND\, speed_pi_ymax_i(7) => \GND\, 
        speed_pi_ymax_i(6) => \GND\, speed_pi_ymax_i(5) => \GND\, 
        speed_pi_ymax_i(4) => \GND\, speed_pi_ymax_i(3) => \GND\, 
        speed_pi_ymax_i(2) => \GND\, speed_pi_ymax_i(1) => \GND\, 
        speed_pi_ymax_i(0) => \GND\, speed_pi_ymin_i(17) => \GND\, 
        speed_pi_ymin_i(16) => \GND\, speed_pi_ymin_i(15) => 
        \GND\, speed_pi_ymin_i(14) => \GND\, speed_pi_ymin_i(13)
         => \GND\, speed_pi_ymin_i(12) => \GND\, 
        speed_pi_ymin_i(11) => \GND\, speed_pi_ymin_i(10) => 
        \GND\, speed_pi_ymin_i(9) => \GND\, speed_pi_ymin_i(8)
         => \GND\, speed_pi_ymin_i(7) => \GND\, 
        speed_pi_ymin_i(6) => \GND\, speed_pi_ymin_i(5) => \GND\, 
        speed_pi_ymin_i(4) => \GND\, speed_pi_ymin_i(3) => \GND\, 
        speed_pi_ymin_i(2) => \GND\, speed_pi_ymin_i(1) => \GND\, 
        speed_pi_ymin_i(0) => \GND\, id_pi_ref_input_i(17) => 
        apb3_if_st_0_id_ref_val_o(17), id_pi_ref_input_i(16) => 
        apb3_if_st_0_id_ref_val_o(16), id_pi_ref_input_i(15) => 
        apb3_if_st_0_id_ref_val_o(15), id_pi_ref_input_i(14) => 
        apb3_if_st_0_id_ref_val_o(14), id_pi_ref_input_i(13) => 
        apb3_if_st_0_id_ref_val_o(13), id_pi_ref_input_i(12) => 
        apb3_if_st_0_id_ref_val_o(12), id_pi_ref_input_i(11) => 
        apb3_if_st_0_id_ref_val_o(11), id_pi_ref_input_i(10) => 
        apb3_if_st_0_id_ref_val_o(10), id_pi_ref_input_i(9) => 
        apb3_if_st_0_id_ref_val_o(9), id_pi_ref_input_i(8) => 
        apb3_if_st_0_id_ref_val_o(8), id_pi_ref_input_i(7) => 
        apb3_if_st_0_id_ref_val_o(7), id_pi_ref_input_i(6) => 
        apb3_if_st_0_id_ref_val_o(6), id_pi_ref_input_i(5) => 
        apb3_if_st_0_id_ref_val_o(5), id_pi_ref_input_i(4) => 
        apb3_if_st_0_id_ref_val_o(4), id_pi_ref_input_i(3) => 
        apb3_if_st_0_id_ref_val_o(3), id_pi_ref_input_i(2) => 
        apb3_if_st_0_id_ref_val_o(2), id_pi_ref_input_i(1) => 
        apb3_if_st_0_id_ref_val_o(1), id_pi_ref_input_i(0) => 
        apb3_if_st_0_id_ref_val_o(0), id_pi_act_input_i(17) => 
        FOC_TRANSFORMS_0_id_o(17), id_pi_act_input_i(16) => 
        FOC_TRANSFORMS_0_id_o(16), id_pi_act_input_i(15) => 
        \FOC_TRANSFORMS_0_id_o_15\, id_pi_act_input_i(14) => 
        FOC_TRANSFORMS_0_id_o(14), id_pi_act_input_i(13) => 
        FOC_TRANSFORMS_0_id_o(13), id_pi_act_input_i(12) => 
        \FOC_TRANSFORMS_0_id_o_12\, id_pi_act_input_i(11) => 
        FOC_TRANSFORMS_0_id_o(11), id_pi_act_input_i(10) => 
        \FOC_TRANSFORMS_0_id_o_10\, id_pi_act_input_i(9) => 
        \FOC_TRANSFORMS_0_id_o_9\, id_pi_act_input_i(8) => 
        \FOC_TRANSFORMS_0_id_o_8\, id_pi_act_input_i(7) => 
        \FOC_TRANSFORMS_0_id_o_7\, id_pi_act_input_i(6) => 
        FOC_TRANSFORMS_0_id_o(6), id_pi_act_input_i(5) => 
        \FOC_TRANSFORMS_0_id_o_5\, id_pi_act_input_i(4) => 
        FOC_TRANSFORMS_0_id_o(4), id_pi_act_input_i(3) => 
        FOC_TRANSFORMS_0_id_o(3), id_pi_act_input_i(2) => 
        FOC_TRANSFORMS_0_id_o(2), id_pi_act_input_i(1) => 
        FOC_TRANSFORMS_0_id_o(1), id_pi_act_input_i(0) => 
        \FOC_TRANSFORMS_0_id_o_0\, id_pi_kp_i(17) => 
        apb3_if_st_0_idq_pi_kp_o(17), id_pi_kp_i(16) => 
        apb3_if_st_0_idq_pi_kp_o(16), id_pi_kp_i(15) => 
        apb3_if_st_0_idq_pi_kp_o(15), id_pi_kp_i(14) => 
        apb3_if_st_0_idq_pi_kp_o(14), id_pi_kp_i(13) => 
        apb3_if_st_0_idq_pi_kp_o(13), id_pi_kp_i(12) => 
        apb3_if_st_0_idq_pi_kp_o(12), id_pi_kp_i(11) => 
        apb3_if_st_0_idq_pi_kp_o(11), id_pi_kp_i(10) => 
        apb3_if_st_0_idq_pi_kp_o(10), id_pi_kp_i(9) => 
        apb3_if_st_0_idq_pi_kp_o(9), id_pi_kp_i(8) => 
        apb3_if_st_0_idq_pi_kp_o(8), id_pi_kp_i(7) => 
        apb3_if_st_0_idq_pi_kp_o(7), id_pi_kp_i(6) => 
        apb3_if_st_0_idq_pi_kp_o(6), id_pi_kp_i(5) => 
        apb3_if_st_0_idq_pi_kp_o(5), id_pi_kp_i(4) => 
        apb3_if_st_0_idq_pi_kp_o(4), id_pi_kp_i(3) => 
        apb3_if_st_0_idq_pi_kp_o(3), id_pi_kp_i(2) => 
        apb3_if_st_0_idq_pi_kp_o(2), id_pi_kp_i(1) => 
        apb3_if_st_0_idq_pi_kp_o(1), id_pi_kp_i(0) => 
        apb3_if_st_0_idq_pi_kp_o(0), id_pi_ki_i(17) => 
        apb3_if_st_0_idq_pi_ki_o(17), id_pi_ki_i(16) => 
        apb3_if_st_0_idq_pi_ki_o(16), id_pi_ki_i(15) => 
        apb3_if_st_0_idq_pi_ki_o(15), id_pi_ki_i(14) => 
        apb3_if_st_0_idq_pi_ki_o(14), id_pi_ki_i(13) => 
        apb3_if_st_0_idq_pi_ki_o(13), id_pi_ki_i(12) => 
        apb3_if_st_0_idq_pi_ki_o(12), id_pi_ki_i(11) => 
        apb3_if_st_0_idq_pi_ki_o(11), id_pi_ki_i(10) => 
        apb3_if_st_0_idq_pi_ki_o(10), id_pi_ki_i(9) => 
        apb3_if_st_0_idq_pi_ki_o(9), id_pi_ki_i(8) => 
        apb3_if_st_0_idq_pi_ki_o(8), id_pi_ki_i(7) => 
        apb3_if_st_0_idq_pi_ki_o(7), id_pi_ki_i(6) => 
        apb3_if_st_0_idq_pi_ki_o(6), id_pi_ki_i(5) => 
        apb3_if_st_0_idq_pi_ki_o(5), id_pi_ki_i(4) => 
        apb3_if_st_0_idq_pi_ki_o(4), id_pi_ki_i(3) => 
        apb3_if_st_0_idq_pi_ki_o(3), id_pi_ki_i(2) => 
        apb3_if_st_0_idq_pi_ki_o(2), id_pi_ki_i(1) => 
        apb3_if_st_0_idq_pi_ki_o(1), id_pi_ki_i(0) => 
        apb3_if_st_0_idq_pi_ki_o(0), idq_pi_ymax_i(17) => \GND\, 
        idq_pi_ymax_i(16) => \VCC\, idq_pi_ymax_i(15) => \GND\, 
        idq_pi_ymax_i(14) => \GND\, idq_pi_ymax_i(13) => \GND\, 
        idq_pi_ymax_i(12) => \GND\, idq_pi_ymax_i(11) => \GND\, 
        idq_pi_ymax_i(10) => \GND\, idq_pi_ymax_i(9) => \GND\, 
        idq_pi_ymax_i(8) => \GND\, idq_pi_ymax_i(7) => \GND\, 
        idq_pi_ymax_i(6) => \GND\, idq_pi_ymax_i(5) => \GND\, 
        idq_pi_ymax_i(4) => \GND\, idq_pi_ymax_i(3) => \GND\, 
        idq_pi_ymax_i(2) => \GND\, idq_pi_ymax_i(1) => \GND\, 
        idq_pi_ymax_i(0) => \GND\, idq_pi_ymin_i(17) => \VCC\, 
        idq_pi_ymin_i(16) => \VCC\, idq_pi_ymin_i(15) => \GND\, 
        idq_pi_ymin_i(14) => \GND\, idq_pi_ymin_i(13) => \GND\, 
        idq_pi_ymin_i(12) => \GND\, idq_pi_ymin_i(11) => \GND\, 
        idq_pi_ymin_i(10) => \GND\, idq_pi_ymin_i(9) => \GND\, 
        idq_pi_ymin_i(8) => \GND\, idq_pi_ymin_i(7) => \GND\, 
        idq_pi_ymin_i(6) => \GND\, idq_pi_ymin_i(5) => \GND\, 
        idq_pi_ymin_i(4) => \GND\, idq_pi_ymin_i(3) => \GND\, 
        idq_pi_ymin_i(2) => \GND\, idq_pi_ymin_i(1) => \GND\, 
        idq_pi_ymin_i(0) => \GND\, iq_pi_ref_input_i(17) => \GND\, 
        iq_pi_ref_input_i(16) => \GND\, iq_pi_ref_input_i(15) => 
        \GND\, iq_pi_ref_input_i(14) => \GND\, 
        iq_pi_ref_input_i(13) => \GND\, iq_pi_ref_input_i(12) => 
        \GND\, iq_pi_ref_input_i(11) => \GND\, 
        iq_pi_ref_input_i(10) => \GND\, iq_pi_ref_input_i(9) => 
        \GND\, iq_pi_ref_input_i(8) => \GND\, 
        iq_pi_ref_input_i(7) => \GND\, iq_pi_ref_input_i(6) => 
        \GND\, iq_pi_ref_input_i(5) => \GND\, 
        iq_pi_ref_input_i(4) => \GND\, iq_pi_ref_input_i(3) => 
        \GND\, iq_pi_ref_input_i(2) => \GND\, 
        iq_pi_ref_input_i(1) => \GND\, iq_pi_ref_input_i(0) => 
        \GND\, iq_pi_act_input_i(17) => FOC_TRANSFORMS_0_iq_o(17), 
        iq_pi_act_input_i(16) => FOC_TRANSFORMS_0_iq_o(16), 
        iq_pi_act_input_i(15) => \FOC_TRANSFORMS_0_iq_o_15\, 
        iq_pi_act_input_i(14) => FOC_TRANSFORMS_0_iq_o(14), 
        iq_pi_act_input_i(13) => FOC_TRANSFORMS_0_iq_o(13), 
        iq_pi_act_input_i(12) => \FOC_TRANSFORMS_0_iq_o_12\, 
        iq_pi_act_input_i(11) => \FOC_TRANSFORMS_0_iq_o_11\, 
        iq_pi_act_input_i(10) => \FOC_TRANSFORMS_0_iq_o_10\, 
        iq_pi_act_input_i(9) => FOC_TRANSFORMS_0_iq_o(9), 
        iq_pi_act_input_i(8) => \FOC_TRANSFORMS_0_iq_o_8\, 
        iq_pi_act_input_i(7) => \FOC_TRANSFORMS_0_iq_o_7\, 
        iq_pi_act_input_i(6) => \FOC_TRANSFORMS_0_iq_o_6\, 
        iq_pi_act_input_i(5) => \FOC_TRANSFORMS_0_iq_o_5\, 
        iq_pi_act_input_i(4) => FOC_TRANSFORMS_0_iq_o(4), 
        iq_pi_act_input_i(3) => \FOC_TRANSFORMS_0_iq_o_3\, 
        iq_pi_act_input_i(2) => \FOC_TRANSFORMS_0_iq_o_2\, 
        iq_pi_act_input_i(1) => \FOC_TRANSFORMS_0_iq_o_1\, 
        iq_pi_act_input_i(0) => \FOC_TRANSFORMS_0_iq_o_0\, 
        iq_pi_kp_i(17) => \GND\, iq_pi_kp_i(16) => \GND\, 
        iq_pi_kp_i(15) => \GND\, iq_pi_kp_i(14) => \GND\, 
        iq_pi_kp_i(13) => \GND\, iq_pi_kp_i(12) => \GND\, 
        iq_pi_kp_i(11) => \GND\, iq_pi_kp_i(10) => \GND\, 
        iq_pi_kp_i(9) => \GND\, iq_pi_kp_i(8) => \GND\, 
        iq_pi_kp_i(7) => \GND\, iq_pi_kp_i(6) => \GND\, 
        iq_pi_kp_i(5) => \GND\, iq_pi_kp_i(4) => \GND\, 
        iq_pi_kp_i(3) => \GND\, iq_pi_kp_i(2) => \GND\, 
        iq_pi_kp_i(1) => \GND\, iq_pi_kp_i(0) => \GND\, 
        iq_pi_ki_i(17) => \GND\, iq_pi_ki_i(16) => \GND\, 
        iq_pi_ki_i(15) => \GND\, iq_pi_ki_i(14) => \GND\, 
        iq_pi_ki_i(13) => \GND\, iq_pi_ki_i(12) => \GND\, 
        iq_pi_ki_i(11) => \GND\, iq_pi_ki_i(10) => \GND\, 
        iq_pi_ki_i(9) => \GND\, iq_pi_ki_i(8) => \GND\, 
        iq_pi_ki_i(7) => \GND\, iq_pi_ki_i(6) => \GND\, 
        iq_pi_ki_i(5) => \GND\, iq_pi_ki_i(4) => \GND\, 
        iq_pi_ki_i(3) => \GND\, iq_pi_ki_i(2) => \GND\, 
        iq_pi_ki_i(1) => \GND\, iq_pi_ki_i(0) => \GND\, 
        speed_pi_done_o => speed_pi_done_o, id_pi_done_o => 
        SPEED_ID_IQ_PI_1_id_pi_done_o, iq_pi_done_o => 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, speed_pi_output_o(17) => 
        speed_pi_output_o(17), speed_pi_output_o(16) => 
        speed_pi_output_o(16), speed_pi_output_o(15) => 
        speed_pi_output_o(15), speed_pi_output_o(14) => 
        speed_pi_output_o(14), speed_pi_output_o(13) => 
        speed_pi_output_o(13), speed_pi_output_o(12) => 
        speed_pi_output_o(12), speed_pi_output_o(11) => 
        speed_pi_output_o(11), speed_pi_output_o(10) => 
        speed_pi_output_o(10), speed_pi_output_o(9) => 
        speed_pi_output_o(9), speed_pi_output_o(8) => 
        speed_pi_output_o(8), speed_pi_output_o(7) => 
        speed_pi_output_o(7), speed_pi_output_o(6) => 
        speed_pi_output_o(6), speed_pi_output_o(5) => 
        speed_pi_output_o(5), speed_pi_output_o(4) => 
        speed_pi_output_o(4), speed_pi_output_o(3) => 
        speed_pi_output_o(3), speed_pi_output_o(2) => 
        speed_pi_output_o(2), speed_pi_output_o(1) => 
        speed_pi_output_o(1), speed_pi_output_o(0) => 
        speed_pi_output_o(0), id_pi_output_o(17) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(17), id_pi_output_o(16)
         => SPEED_ID_IQ_PI_1_id_pi_output_o(16), 
        id_pi_output_o(15) => SPEED_ID_IQ_PI_1_id_pi_output_o(15), 
        id_pi_output_o(14) => SPEED_ID_IQ_PI_1_id_pi_output_o(14), 
        id_pi_output_o(13) => SPEED_ID_IQ_PI_1_id_pi_output_o(13), 
        id_pi_output_o(12) => SPEED_ID_IQ_PI_1_id_pi_output_o(12), 
        id_pi_output_o(11) => SPEED_ID_IQ_PI_1_id_pi_output_o(11), 
        id_pi_output_o(10) => SPEED_ID_IQ_PI_1_id_pi_output_o(10), 
        id_pi_output_o(9) => SPEED_ID_IQ_PI_1_id_pi_output_o(9), 
        id_pi_output_o(8) => SPEED_ID_IQ_PI_1_id_pi_output_o(8), 
        id_pi_output_o(7) => SPEED_ID_IQ_PI_1_id_pi_output_o(7), 
        id_pi_output_o(6) => SPEED_ID_IQ_PI_1_id_pi_output_o(6), 
        id_pi_output_o(5) => SPEED_ID_IQ_PI_1_id_pi_output_o(5), 
        id_pi_output_o(4) => SPEED_ID_IQ_PI_1_id_pi_output_o(4), 
        id_pi_output_o(3) => SPEED_ID_IQ_PI_1_id_pi_output_o(3), 
        id_pi_output_o(2) => SPEED_ID_IQ_PI_1_id_pi_output_o(2), 
        id_pi_output_o(1) => \SPEED_ID_IQ_PI_1_id_pi_output_o_1\, 
        id_pi_output_o(0) => SPEED_ID_IQ_PI_1_id_pi_output_o_0, 
        iq_pi_output_o(17) => SPEED_ID_IQ_PI_1_iq_pi_output_o(17), 
        iq_pi_output_o(16) => SPEED_ID_IQ_PI_1_iq_pi_output_o(16), 
        iq_pi_output_o(15) => SPEED_ID_IQ_PI_1_iq_pi_output_o(15), 
        iq_pi_output_o(14) => SPEED_ID_IQ_PI_1_iq_pi_output_o(14), 
        iq_pi_output_o(13) => SPEED_ID_IQ_PI_1_iq_pi_output_o(13), 
        iq_pi_output_o(12) => SPEED_ID_IQ_PI_1_iq_pi_output_o(12), 
        iq_pi_output_o(11) => SPEED_ID_IQ_PI_1_iq_pi_output_o(11), 
        iq_pi_output_o(10) => SPEED_ID_IQ_PI_1_iq_pi_output_o(10), 
        iq_pi_output_o(9) => SPEED_ID_IQ_PI_1_iq_pi_output_o(9), 
        iq_pi_output_o(8) => SPEED_ID_IQ_PI_1_iq_pi_output_o(8), 
        iq_pi_output_o(7) => SPEED_ID_IQ_PI_1_iq_pi_output_o(7), 
        iq_pi_output_o(6) => SPEED_ID_IQ_PI_1_iq_pi_output_o(6), 
        iq_pi_output_o(5) => SPEED_ID_IQ_PI_1_iq_pi_output_o(5), 
        iq_pi_output_o(4) => SPEED_ID_IQ_PI_1_iq_pi_output_o(4), 
        iq_pi_output_o(3) => SPEED_ID_IQ_PI_1_iq_pi_output_o(3), 
        iq_pi_output_o(2) => SPEED_ID_IQ_PI_1_iq_pi_output_o(2), 
        iq_pi_output_o(1) => \SPEED_ID_IQ_PI_1_iq_pi_output_o_1\, 
        iq_pi_output_o(0) => SPEED_ID_IQ_PI_1_iq_pi_output_o_0);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MSC_i_46 : STEPPER_THETA
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FAB_CCC_GL1, enable_i => 
        ADC_SCALING_0_calib_done_o, mode_i => 
        apb3_if_st_0_theta_gen_mode_o, clear_buffer_i => 
        SEQ_CONTROLLER_1_motor_stopped_o, slew_cnt_i(17) => 
        apb3_if_st_0_theta_gen_slew_count_o(17), slew_cnt_i(16)
         => apb3_if_st_0_theta_gen_slew_count_o(16), 
        slew_cnt_i(15) => apb3_if_st_0_theta_gen_slew_count_o(15), 
        slew_cnt_i(14) => apb3_if_st_0_theta_gen_slew_count_o(14), 
        slew_cnt_i(13) => apb3_if_st_0_theta_gen_slew_count_o(13), 
        slew_cnt_i(12) => apb3_if_st_0_theta_gen_slew_count_o(12), 
        slew_cnt_i(11) => apb3_if_st_0_theta_gen_slew_count_o(11), 
        slew_cnt_i(10) => apb3_if_st_0_theta_gen_slew_count_o(10), 
        slew_cnt_i(9) => apb3_if_st_0_theta_gen_slew_count_o(9), 
        slew_cnt_i(8) => apb3_if_st_0_theta_gen_slew_count_o(8), 
        slew_cnt_i(7) => apb3_if_st_0_theta_gen_slew_count_o(7), 
        slew_cnt_i(6) => apb3_if_st_0_theta_gen_slew_count_o(6), 
        slew_cnt_i(5) => apb3_if_st_0_theta_gen_slew_count_o(5), 
        slew_cnt_i(4) => apb3_if_st_0_theta_gen_slew_count_o(4), 
        slew_cnt_i(3) => apb3_if_st_0_theta_gen_slew_count_o(3), 
        slew_cnt_i(2) => apb3_if_st_0_theta_gen_slew_count_o(2), 
        slew_cnt_i(1) => apb3_if_st_0_theta_gen_slew_count_o(1), 
        slew_cnt_i(0) => apb3_if_st_0_theta_gen_slew_count_o(0), 
        rate_limit_i(17) => 
        apb3_if_st_0_theta_gen_rate_limit_o(17), rate_limit_i(16)
         => apb3_if_st_0_theta_gen_rate_limit_o(16), 
        rate_limit_i(15) => 
        apb3_if_st_0_theta_gen_rate_limit_o(15), rate_limit_i(14)
         => apb3_if_st_0_theta_gen_rate_limit_o(14), 
        rate_limit_i(13) => 
        apb3_if_st_0_theta_gen_rate_limit_o(13), rate_limit_i(12)
         => apb3_if_st_0_theta_gen_rate_limit_o(12), 
        rate_limit_i(11) => 
        apb3_if_st_0_theta_gen_rate_limit_o(11), rate_limit_i(10)
         => apb3_if_st_0_theta_gen_rate_limit_o(10), 
        rate_limit_i(9) => apb3_if_st_0_theta_gen_rate_limit_o(9), 
        rate_limit_i(8) => apb3_if_st_0_theta_gen_rate_limit_o(8), 
        rate_limit_i(7) => apb3_if_st_0_theta_gen_rate_limit_o(7), 
        rate_limit_i(6) => apb3_if_st_0_theta_gen_rate_limit_o(6), 
        rate_limit_i(5) => apb3_if_st_0_theta_gen_rate_limit_o(5), 
        rate_limit_i(4) => apb3_if_st_0_theta_gen_rate_limit_o(4), 
        rate_limit_i(3) => apb3_if_st_0_theta_gen_rate_limit_o(3), 
        rate_limit_i(2) => apb3_if_st_0_theta_gen_rate_limit_o(2), 
        rate_limit_i(1) => apb3_if_st_0_theta_gen_rate_limit_o(1), 
        rate_limit_i(0) => apb3_if_st_0_theta_gen_rate_limit_o(0), 
        cmd_step_no_i(23) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(23), 
        cmd_step_no_i(22) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(22), 
        cmd_step_no_i(21) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(21), 
        cmd_step_no_i(20) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(20), 
        cmd_step_no_i(19) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(19), 
        cmd_step_no_i(18) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(18), 
        cmd_step_no_i(17) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(17), 
        cmd_step_no_i(16) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(16), 
        cmd_step_no_i(15) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(15), 
        cmd_step_no_i(14) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(14), 
        cmd_step_no_i(13) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(13), 
        cmd_step_no_i(12) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(12), 
        cmd_step_no_i(11) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(11), 
        cmd_step_no_i(10) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(10), 
        cmd_step_no_i(9) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(9), 
        cmd_step_no_i(8) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(8), 
        cmd_step_no_i(7) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(7), 
        cmd_step_no_i(6) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(6), 
        cmd_step_no_i(5) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(5), 
        cmd_step_no_i(4) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(4), 
        cmd_step_no_i(3) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(3), 
        cmd_step_no_i(2) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(2), 
        cmd_step_no_i(1) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(1), 
        cmd_step_no_i(0) => 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0(0), 
        theta_output_o(17) => \STEPPER_THETA_0_theta_output_o_17\, 
        theta_output_o(16) => STEPPER_THETA_0_theta_output_o(16), 
        theta_output_o(15) => STEPPER_THETA_0_theta_output_o(15), 
        theta_output_o(14) => STEPPER_THETA_0_theta_output_o(14), 
        theta_output_o(13) => STEPPER_THETA_0_theta_output_o(13), 
        theta_output_o(12) => STEPPER_THETA_0_theta_output_o(12), 
        theta_output_o(11) => STEPPER_THETA_0_theta_output_o(11), 
        theta_output_o(10) => STEPPER_THETA_0_theta_output_o(10), 
        theta_output_o(9) => STEPPER_THETA_0_theta_output_o(9), 
        theta_output_o(8) => STEPPER_THETA_0_theta_output_o(8), 
        theta_output_o(7) => STEPPER_THETA_0_theta_output_o(7), 
        theta_output_o(6) => STEPPER_THETA_0_theta_output_o(6), 
        theta_output_o(5) => STEPPER_THETA_0_theta_output_o(5), 
        theta_output_o(4) => STEPPER_THETA_0_theta_output_o(4), 
        theta_output_o(3) => STEPPER_THETA_0_theta_output_o(3), 
        theta_output_o(2) => STEPPER_THETA_0_theta_output_o(2), 
        theta_output_o(1) => STEPPER_THETA_0_theta_output_o(1), 
        theta_output_o(0) => STEPPER_THETA_0_theta_output_o(0), 
        step_count_o(23) => STEPPER_THETA_1_step_count_o_23, 
        step_count_o(22) => STEPPER_THETA_1_step_count_o(22), 
        step_count_o(21) => STEPPER_THETA_1_step_count_o(21), 
        step_count_o(20) => STEPPER_THETA_1_step_count_o(20), 
        step_count_o(19) => STEPPER_THETA_1_step_count_o(19), 
        step_count_o(18) => STEPPER_THETA_1_step_count_o(18), 
        step_count_o(17) => STEPPER_THETA_1_step_count_o(17), 
        step_count_o(16) => STEPPER_THETA_1_step_count_o(16), 
        step_count_o(15) => STEPPER_THETA_1_step_count_o_15, 
        step_count_o(14) => STEPPER_THETA_1_step_count_o(14), 
        step_count_o(13) => STEPPER_THETA_1_step_count_o(13), 
        step_count_o(12) => STEPPER_THETA_1_step_count_o_12, 
        step_count_o(11) => STEPPER_THETA_1_step_count_o_11, 
        step_count_o(10) => STEPPER_THETA_1_step_count_o(10), 
        step_count_o(9) => STEPPER_THETA_1_step_count_o_9, 
        step_count_o(8) => STEPPER_THETA_1_step_count_o(8), 
        step_count_o(7) => STEPPER_THETA_1_step_count_o(7), 
        step_count_o(6) => STEPPER_THETA_1_step_count_o_6, 
        step_count_o(5) => STEPPER_THETA_1_step_count_o(5), 
        step_count_o(4) => STEPPER_THETA_1_step_count_o(4), 
        step_count_o(3) => STEPPER_THETA_1_step_count_o(3), 
        step_count_o(2) => STEPPER_THETA_1_step_count_o(2), 
        step_count_o(1) => STEPPER_THETA_1_step_count_o(1), 
        step_count_o(0) => STEPPER_THETA_1_step_count_o(0));
    
    MSC_i_43 : SEQ_CONTROLLER_1
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FAB_CCC_GL1, fault_i => 
        ADC_SCALING_0_over_current_fault_o, start_motor_i => 
        apb3_if_st_0_start_motor_o, stop_motor_i => 
        apb3_if_st_0_stop_motor_o, fault_clear_i => \GND\, 
        speed_ref_i(17) => \GND\, speed_ref_i(16) => \GND\, 
        speed_ref_i(15) => \GND\, speed_ref_i(14) => \GND\, 
        speed_ref_i(13) => \GND\, speed_ref_i(12) => \GND\, 
        speed_ref_i(11) => \GND\, speed_ref_i(10) => \GND\, 
        speed_ref_i(9) => \GND\, speed_ref_i(8) => \GND\, 
        speed_ref_i(7) => \GND\, speed_ref_i(6) => \GND\, 
        speed_ref_i(5) => \GND\, speed_ref_i(4) => \GND\, 
        speed_ref_i(3) => \GND\, speed_ref_i(2) => \GND\, 
        speed_ref_i(1) => \GND\, speed_ref_i(0) => \GND\, 
        speed_cl_i(17) => \GND\, speed_cl_i(16) => \GND\, 
        speed_cl_i(15) => \GND\, speed_cl_i(14) => \GND\, 
        speed_cl_i(13) => \GND\, speed_cl_i(12) => \GND\, 
        speed_cl_i(11) => \GND\, speed_cl_i(10) => \GND\, 
        speed_cl_i(9) => \GND\, speed_cl_i(8) => \GND\, 
        speed_cl_i(7) => \GND\, speed_cl_i(6) => \GND\, 
        speed_cl_i(5) => \GND\, speed_cl_i(4) => \GND\, 
        speed_cl_i(3) => \GND\, speed_cl_i(2) => \GND\, 
        speed_cl_i(1) => \GND\, speed_cl_i(0) => \GND\, vq_i(17)
         => \GND\, vq_i(16) => \GND\, vq_i(15) => \GND\, vq_i(14)
         => \GND\, vq_i(13) => \GND\, vq_i(12) => \GND\, vq_i(11)
         => \GND\, vq_i(10) => \GND\, vq_i(9) => \GND\, vq_i(8)
         => \GND\, vq_i(7) => \GND\, vq_i(6) => \GND\, vq_i(5)
         => \GND\, vq_i(4) => \GND\, vq_i(3) => \GND\, vq_i(2)
         => \GND\, vq_i(1) => \GND\, vq_i(0) => \GND\, 
        max_ar_i(3) => \GND\, max_ar_i(2) => \GND\, max_ar_i(1)
         => \GND\, max_ar_i(0) => \GND\, calib_done_i => 
        ADC_SCALING_0_calib_done_o, pwm_midmatch_i => 
        PWM3PH_0_midmatch_o, foc_done_i => PWM_SCALING_0_done_o, 
        config_reg_i(3) => \GND\, config_reg_i(2) => 
        apb3_if_st_0_seq_cntl_config_o(2), config_reg_i(1) => 
        apb3_if_st_0_seq_cntl_config_o(1), config_reg_i(0) => 
        \GND\, adc_start_o => SEQ_CONTROLLER_1_adc_start_o_0, 
        cl_status_o => cl_status_o, en_idq_pi_o => 
        SEQ_CONTROLLER_1_en_idq_pi_o, en_pwm_o => \A1_PWM_WL_O_c\, 
        motor_stopped_o => SEQ_CONTROLLER_1_motor_stopped_o, 
        reset_rl_o => reset_rl_o, soft_stop_o => soft_stop_o, 
        sensor_reset_o => sensor_reset_o, state_o(3) => 
        SEQ_CONTROLLER_1_state_o_0(3), state_o(2) => 
        SEQ_CONTROLLER_1_state_o_0(2), state_o(1) => 
        SEQ_CONTROLLER_1_state_o_0_1, state_o(0) => 
        SEQ_CONTROLLER_1_state_o_0(0));
    
    MSC_i_52 : PWM_SCALING_1
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FAB_CCC_GL1, start_i => 
        FOC_TRANSFORMS_1_ipark_done_o, va_i(17) => 
        FOC_TRANSFORMS_1_valpha_o(17), va_i(16) => 
        FOC_TRANSFORMS_1_valpha_o(16), va_i(15) => 
        FOC_TRANSFORMS_1_valpha_o(15), va_i(14) => 
        FOC_TRANSFORMS_1_valpha_o(14), va_i(13) => 
        FOC_TRANSFORMS_1_valpha_o(13), va_i(12) => 
        FOC_TRANSFORMS_1_valpha_o(12), va_i(11) => 
        \FOC_TRANSFORMS_1_valpha_o_11\, va_i(10) => 
        \FOC_TRANSFORMS_1_valpha_o_10\, va_i(9) => 
        \FOC_TRANSFORMS_1_valpha_o_9\, va_i(8) => 
        \FOC_TRANSFORMS_1_valpha_o_8\, va_i(7) => 
        \FOC_TRANSFORMS_1_valpha_o_7\, va_i(6) => 
        \FOC_TRANSFORMS_1_valpha_o_6\, va_i(5) => 
        \FOC_TRANSFORMS_1_valpha_o_5\, va_i(4) => 
        \FOC_TRANSFORMS_1_valpha_o_4\, va_i(3) => 
        FOC_TRANSFORMS_1_valpha_o(3), va_i(2) => 
        FOC_TRANSFORMS_1_valpha_o(2), va_i(1) => 
        FOC_TRANSFORMS_1_valpha_o(1), va_i(0) => 
        \FOC_TRANSFORMS_1_valpha_o_0\, vb_i(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), vb_i(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), vb_i(15) => 
        \FOC_TRANSFORMS_0_vbeta_o_15\, vb_i(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), vb_i(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), vb_i(12) => 
        \FOC_TRANSFORMS_0_vbeta_o_12\, vb_i(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), vb_i(10) => 
        \FOC_TRANSFORMS_0_vbeta_o_10\, vb_i(9) => 
        FOC_TRANSFORMS_0_vbeta_o(9), vb_i(8) => 
        \FOC_TRANSFORMS_0_vbeta_o_8\, vb_i(7) => 
        \FOC_TRANSFORMS_0_vbeta_o_7\, vb_i(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), vb_i(5) => 
        \FOC_TRANSFORMS_0_vbeta_o_5\, vb_i(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), vb_i(3) => 
        \FOC_TRANSFORMS_0_vbeta_o_3\, vb_i(2) => 
        \FOC_TRANSFORMS_0_vbeta_o_2\, vb_i(1) => 
        FOC_TRANSFORMS_0_vbeta_o(1), vb_i(0) => 
        \FOC_TRANSFORMS_0_vbeta_o_0\, vc_i(17) => \GND\, vc_i(16)
         => \GND\, vc_i(15) => \GND\, vc_i(14) => \GND\, vc_i(13)
         => \GND\, vc_i(12) => \GND\, vc_i(11) => \GND\, vc_i(10)
         => \GND\, vc_i(9) => \GND\, vc_i(8) => \GND\, vc_i(7)
         => \GND\, vc_i(6) => \GND\, vc_i(5) => \GND\, vc_i(4)
         => \GND\, vc_i(3) => \GND\, vc_i(2) => \GND\, vc_i(1)
         => \GND\, vc_i(0) => \GND\, pwm_period_i(17) => 
        apb3_if_st_0_pwm_period_val_o(17), pwm_period_i(16) => 
        apb3_if_st_0_pwm_period_val_o(16), pwm_period_i(15) => 
        apb3_if_st_0_pwm_period_val_o(15), pwm_period_i(14) => 
        apb3_if_st_0_pwm_period_val_o(14), pwm_period_i(13) => 
        apb3_if_st_0_pwm_period_val_o(13), pwm_period_i(12) => 
        apb3_if_st_0_pwm_period_val_o(12), pwm_period_i(11) => 
        apb3_if_st_0_pwm_period_val_o(11), pwm_period_i(10) => 
        apb3_if_st_0_pwm_period_val_o(10), pwm_period_i(9) => 
        apb3_if_st_0_pwm_period_val_o(9), pwm_period_i(8) => 
        apb3_if_st_0_pwm_period_val_o(8), pwm_period_i(7) => 
        apb3_if_st_0_pwm_period_val_o(7), pwm_period_i(6) => 
        apb3_if_st_0_pwm_period_val_o(6), pwm_period_i(5) => 
        apb3_if_st_0_pwm_period_val_o(5), pwm_period_i(4) => 
        apb3_if_st_0_pwm_period_val_o(4), pwm_period_i(3) => 
        apb3_if_st_0_pwm_period_val_o(3), pwm_period_i(2) => 
        apb3_if_st_0_pwm_period_val_o(2), pwm_period_i(1) => 
        apb3_if_st_0_pwm_period_val_o(1), pwm_period_i(0) => 
        apb3_if_st_0_pwm_period_val_o(0), pwm_gain_i(17) => \GND\, 
        pwm_gain_i(16) => \GND\, pwm_gain_i(15) => \GND\, 
        pwm_gain_i(14) => \GND\, pwm_gain_i(13) => \GND\, 
        pwm_gain_i(12) => \GND\, pwm_gain_i(11) => \GND\, 
        pwm_gain_i(10) => \GND\, pwm_gain_i(9) => \GND\, 
        pwm_gain_i(8) => \GND\, pwm_gain_i(7) => \GND\, 
        pwm_gain_i(6) => \GND\, pwm_gain_i(5) => \GND\, 
        pwm_gain_i(4) => \GND\, pwm_gain_i(3) => \GND\, 
        pwm_gain_i(2) => \GND\, pwm_gain_i(1) => \GND\, 
        pwm_gain_i(0) => \GND\, Va_o(17) => 
        PWM_SCALING_0_Va_o(17), Va_o(16) => 
        PWM_SCALING_0_Va_o(16), Va_o(15) => 
        PWM_SCALING_0_Va_o(15), Va_o(14) => 
        PWM_SCALING_0_Va_o(14), Va_o(13) => 
        PWM_SCALING_0_Va_o(13), Va_o(12) => 
        PWM_SCALING_0_Va_o(12), Va_o(11) => 
        PWM_SCALING_0_Va_o(11), Va_o(10) => 
        PWM_SCALING_0_Va_o(10), Va_o(9) => PWM_SCALING_0_Va_o(9), 
        Va_o(8) => PWM_SCALING_0_Va_o(8), Va_o(7) => 
        PWM_SCALING_0_Va_o(7), Va_o(6) => PWM_SCALING_0_Va_o(6), 
        Va_o(5) => PWM_SCALING_0_Va_o(5), Va_o(4) => 
        PWM_SCALING_0_Va_o(4), Va_o(3) => PWM_SCALING_0_Va_o(3), 
        Va_o(2) => PWM_SCALING_0_Va_o(2), Va_o(1) => 
        PWM_SCALING_0_Va_o(1), Va_o(0) => PWM_SCALING_0_Va_o(0), 
        Vb_o(17) => PWM_SCALING_0_Vb_o(17), Vb_o(16) => 
        PWM_SCALING_0_Vb_o(16), Vb_o(15) => 
        PWM_SCALING_0_Vb_o(15), Vb_o(14) => 
        PWM_SCALING_0_Vb_o(14), Vb_o(13) => 
        PWM_SCALING_0_Vb_o(13), Vb_o(12) => 
        PWM_SCALING_0_Vb_o(12), Vb_o(11) => 
        PWM_SCALING_0_Vb_o(11), Vb_o(10) => 
        PWM_SCALING_0_Vb_o(10), Vb_o(9) => PWM_SCALING_0_Vb_o(9), 
        Vb_o(8) => PWM_SCALING_0_Vb_o(8), Vb_o(7) => 
        PWM_SCALING_0_Vb_o(7), Vb_o(6) => PWM_SCALING_0_Vb_o(6), 
        Vb_o(5) => PWM_SCALING_0_Vb_o(5), Vb_o(4) => 
        PWM_SCALING_0_Vb_o(4), Vb_o(3) => PWM_SCALING_0_Vb_o(3), 
        Vb_o(2) => PWM_SCALING_0_Vb_o(2), Vb_o(1) => 
        PWM_SCALING_0_Vb_o(1), Vb_o(0) => PWM_SCALING_0_Vb_o(0), 
        Vc_o(17) => Vc_o(17), Vc_o(16) => Vc_o(16), Vc_o(15) => 
        Vc_o(15), Vc_o(14) => Vc_o(14), Vc_o(13) => Vc_o(13), 
        Vc_o(12) => Vc_o(12), Vc_o(11) => Vc_o(11), Vc_o(10) => 
        Vc_o(10), Vc_o(9) => Vc_o(9), Vc_o(8) => Vc_o(8), Vc_o(7)
         => Vc_o(7), Vc_o(6) => Vc_o(6), Vc_o(5) => Vc_o(5), 
        Vc_o(4) => Vc_o(4), Vc_o(3) => Vc_o(3), Vc_o(2) => 
        Vc_o(2), Vc_o(1) => Vc_o(1), Vc_o(0) => Vc_o(0), done_o
         => PWM_SCALING_0_done_o);
    
    MSC_i_54 : PWM3PH_1
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FAB_CCC_GL1, en_pwm_i => \A1_PWM_WL_O_c\, 
        en_dual_trig_i => \GND\, va_i(17) => 
        PWM_SCALING_0_Va_o(17), va_i(16) => 
        PWM_SCALING_0_Va_o(16), va_i(15) => 
        PWM_SCALING_0_Va_o(15), va_i(14) => 
        PWM_SCALING_0_Va_o(14), va_i(13) => 
        PWM_SCALING_0_Va_o(13), va_i(12) => 
        PWM_SCALING_0_Va_o(12), va_i(11) => 
        PWM_SCALING_0_Va_o(11), va_i(10) => 
        PWM_SCALING_0_Va_o(10), va_i(9) => PWM_SCALING_0_Va_o(9), 
        va_i(8) => PWM_SCALING_0_Va_o(8), va_i(7) => 
        PWM_SCALING_0_Va_o(7), va_i(6) => PWM_SCALING_0_Va_o(6), 
        va_i(5) => PWM_SCALING_0_Va_o(5), va_i(4) => 
        PWM_SCALING_0_Va_o(4), va_i(3) => PWM_SCALING_0_Va_o(3), 
        va_i(2) => PWM_SCALING_0_Va_o(2), va_i(1) => 
        PWM_SCALING_0_Va_o(1), va_i(0) => PWM_SCALING_0_Va_o(0), 
        vb_i(17) => PWM_SCALING_0_Vb_o(17), vb_i(16) => 
        PWM_SCALING_0_Vb_o(16), vb_i(15) => 
        PWM_SCALING_0_Vb_o(15), vb_i(14) => 
        PWM_SCALING_0_Vb_o(14), vb_i(13) => 
        PWM_SCALING_0_Vb_o(13), vb_i(12) => 
        PWM_SCALING_0_Vb_o(12), vb_i(11) => 
        PWM_SCALING_0_Vb_o(11), vb_i(10) => 
        PWM_SCALING_0_Vb_o(10), vb_i(9) => PWM_SCALING_0_Vb_o(9), 
        vb_i(8) => PWM_SCALING_0_Vb_o(8), vb_i(7) => 
        PWM_SCALING_0_Vb_o(7), vb_i(6) => PWM_SCALING_0_Vb_o(6), 
        vb_i(5) => PWM_SCALING_0_Vb_o(5), vb_i(4) => 
        PWM_SCALING_0_Vb_o(4), vb_i(3) => PWM_SCALING_0_Vb_o(3), 
        vb_i(2) => PWM_SCALING_0_Vb_o(2), vb_i(1) => 
        PWM_SCALING_0_Vb_o(1), vb_i(0) => PWM_SCALING_0_Vb_o(0), 
        vc_i(17) => \GND\, vc_i(16) => \GND\, vc_i(15) => \GND\, 
        vc_i(14) => \GND\, vc_i(13) => \GND\, vc_i(12) => \GND\, 
        vc_i(11) => \GND\, vc_i(10) => \GND\, vc_i(9) => \GND\, 
        vc_i(8) => \GND\, vc_i(7) => \GND\, vc_i(6) => \GND\, 
        vc_i(5) => \GND\, vc_i(4) => \GND\, vc_i(3) => \GND\, 
        vc_i(2) => \GND\, vc_i(1) => \GND\, vc_i(0) => \GND\, 
        pwm_period_i(17) => apb3_if_st_0_pwm_period_val_o(17), 
        pwm_period_i(16) => apb3_if_st_0_pwm_period_val_o(16), 
        pwm_period_i(15) => apb3_if_st_0_pwm_period_val_o(15), 
        pwm_period_i(14) => apb3_if_st_0_pwm_period_val_o(14), 
        pwm_period_i(13) => apb3_if_st_0_pwm_period_val_o(13), 
        pwm_period_i(12) => apb3_if_st_0_pwm_period_val_o(12), 
        pwm_period_i(11) => apb3_if_st_0_pwm_period_val_o(11), 
        pwm_period_i(10) => apb3_if_st_0_pwm_period_val_o(10), 
        pwm_period_i(9) => apb3_if_st_0_pwm_period_val_o(9), 
        pwm_period_i(8) => apb3_if_st_0_pwm_period_val_o(8), 
        pwm_period_i(7) => apb3_if_st_0_pwm_period_val_o(7), 
        pwm_period_i(6) => apb3_if_st_0_pwm_period_val_o(6), 
        pwm_period_i(5) => apb3_if_st_0_pwm_period_val_o(5), 
        pwm_period_i(4) => apb3_if_st_0_pwm_period_val_o(4), 
        pwm_period_i(3) => apb3_if_st_0_pwm_period_val_o(3), 
        pwm_period_i(2) => apb3_if_st_0_pwm_period_val_o(2), 
        pwm_period_i(1) => apb3_if_st_0_pwm_period_val_o(1), 
        pwm_period_i(0) => apb3_if_st_0_pwm_period_val_o(0), 
        dead_time_i(17) => apb3_if_st_0_pwm_dead_time_val_o(17), 
        dead_time_i(16) => apb3_if_st_0_pwm_dead_time_val_o(16), 
        dead_time_i(15) => apb3_if_st_0_pwm_dead_time_val_o(15), 
        dead_time_i(14) => apb3_if_st_0_pwm_dead_time_val_o(14), 
        dead_time_i(13) => apb3_if_st_0_pwm_dead_time_val_o(13), 
        dead_time_i(12) => apb3_if_st_0_pwm_dead_time_val_o(12), 
        dead_time_i(11) => apb3_if_st_0_pwm_dead_time_val_o(11), 
        dead_time_i(10) => apb3_if_st_0_pwm_dead_time_val_o(10), 
        dead_time_i(9) => apb3_if_st_0_pwm_dead_time_val_o(9), 
        dead_time_i(8) => apb3_if_st_0_pwm_dead_time_val_o(8), 
        dead_time_i(7) => apb3_if_st_0_pwm_dead_time_val_o(7), 
        dead_time_i(6) => apb3_if_st_0_pwm_dead_time_val_o(6), 
        dead_time_i(5) => apb3_if_st_0_pwm_dead_time_val_o(5), 
        dead_time_i(4) => apb3_if_st_0_pwm_dead_time_val_o(4), 
        dead_time_i(3) => apb3_if_st_0_pwm_dead_time_val_o(3), 
        dead_time_i(2) => apb3_if_st_0_pwm_dead_time_val_o(2), 
        dead_time_i(1) => apb3_if_st_0_pwm_dead_time_val_o(1), 
        dead_time_i(0) => apb3_if_st_0_pwm_dead_time_val_o(0), 
        delay_time_i(17) => apb3_if_st_0_pwm_delay_time_val_o(17), 
        delay_time_i(16) => apb3_if_st_0_pwm_delay_time_val_o(16), 
        delay_time_i(15) => apb3_if_st_0_pwm_delay_time_val_o(15), 
        delay_time_i(14) => apb3_if_st_0_pwm_delay_time_val_o(14), 
        delay_time_i(13) => apb3_if_st_0_pwm_delay_time_val_o(13), 
        delay_time_i(12) => apb3_if_st_0_pwm_delay_time_val_o(12), 
        delay_time_i(11) => apb3_if_st_0_pwm_delay_time_val_o(11), 
        delay_time_i(10) => apb3_if_st_0_pwm_delay_time_val_o(10), 
        delay_time_i(9) => apb3_if_st_0_pwm_delay_time_val_o(9), 
        delay_time_i(8) => apb3_if_st_0_pwm_delay_time_val_o(8), 
        delay_time_i(7) => apb3_if_st_0_pwm_delay_time_val_o(7), 
        delay_time_i(6) => apb3_if_st_0_pwm_delay_time_val_o(6), 
        delay_time_i(5) => apb3_if_st_0_pwm_delay_time_val_o(5), 
        delay_time_i(4) => apb3_if_st_0_pwm_delay_time_val_o(4), 
        delay_time_i(3) => apb3_if_st_0_pwm_delay_time_val_o(3), 
        delay_time_i(2) => apb3_if_st_0_pwm_delay_time_val_o(2), 
        delay_time_i(1) => apb3_if_st_0_pwm_delay_time_val_o(1), 
        delay_time_i(0) => apb3_if_st_0_pwm_delay_time_val_o(0), 
        midmatch_o => PWM3PH_0_midmatch_o, PWM_AH_o => 
        A1_PWM_UH_O_c, PWM_BH_o => A1_PWM_VH_O_c, PWM_CH_o => 
        PWM_CH_o, PWM_AL_o => A1_PWM_UL_O_c, PWM_BL_o => 
        A1_PWM_VL_O_c, PWM_CL_o => PWM_CL_o);
    
    adc_interface_0 : adc_interface_1
      port map(apb3_if_st_0_adc_control_reg_val_o(5) => 
        apb3_if_st_0_adc_control_reg_val_o(5), 
        apb3_if_st_0_adc_control_reg_val_o(4) => 
        apb3_if_st_0_adc_control_reg_val_o(4), 
        apb3_if_st_0_adc_control_reg_val_o(3) => 
        apb3_if_st_0_adc_control_reg_val_o(3), 
        apb3_if_st_0_adc_control_reg_val_o(2) => 
        apb3_if_st_0_adc_control_reg_val_o(2), 
        apb3_if_st_0_adc_control_reg_val_o(1) => 
        apb3_if_st_0_adc_control_reg_val_o(1), 
        apb3_if_st_0_adc_control_reg_val_o(0) => 
        apb3_if_st_0_adc_control_reg_val_o(0), 
        adc_interface_0_result_ch0_o(11) => 
        \adc_interface_0_result_ch0_o_11\, 
        adc_interface_0_result_ch0_o(10) => 
        adc_interface_0_result_ch0_o(10), 
        adc_interface_0_result_ch0_o(9) => 
        \adc_interface_0_result_ch0_o_9\, 
        adc_interface_0_result_ch0_o(8) => 
        \adc_interface_0_result_ch0_o_8\, 
        adc_interface_0_result_ch0_o(7) => 
        \adc_interface_0_result_ch0_o_7\, 
        adc_interface_0_result_ch0_o(6) => 
        \adc_interface_0_result_ch0_o_6\, 
        adc_interface_0_result_ch0_o(5) => 
        \adc_interface_0_result_ch0_o_5\, 
        adc_interface_0_result_ch0_o(4) => 
        adc_interface_0_result_ch0_o(4), 
        adc_interface_0_result_ch0_o(3) => 
        adc_interface_0_result_ch0_o(3), 
        adc_interface_0_result_ch0_o(2) => 
        adc_interface_0_result_ch0_o(2), 
        adc_interface_0_result_ch0_o(1) => 
        adc_interface_0_result_ch0_o(1), 
        adc_interface_0_result_ch0_o(0) => 
        \adc_interface_0_result_ch0_o_0\, 
        adc_measurements_0_adc_result_ch1_o(11) => 
        adc_measurements_0_adc_result_ch1_o(11), 
        adc_measurements_0_adc_result_ch1_o(10) => 
        adc_measurements_0_adc_result_ch1_o_10, 
        adc_measurements_0_adc_result_ch1_o(9) => 
        adc_measurements_0_adc_result_ch1_o_9, 
        adc_measurements_0_adc_result_ch1_o(8) => 
        adc_measurements_0_adc_result_ch1_o_8, 
        adc_measurements_0_adc_result_ch1_o(7) => 
        adc_measurements_0_adc_result_ch1_o_7, 
        adc_measurements_0_adc_result_ch1_o(6) => 
        adc_measurements_0_adc_result_ch1_o(6), 
        adc_measurements_0_adc_result_ch1_o(5) => 
        adc_measurements_0_adc_result_ch1_o_5, 
        adc_measurements_0_adc_result_ch1_o(4) => 
        adc_measurements_0_adc_result_ch1_o(4), 
        adc_measurements_0_adc_result_ch1_o(3) => 
        adc_measurements_0_adc_result_ch1_o(3), 
        adc_measurements_0_adc_result_ch1_o(2) => 
        adc_measurements_0_adc_result_ch1_o(2), 
        adc_measurements_0_adc_result_ch1_o(1) => 
        adc_measurements_0_adc_result_ch1_o_1, 
        adc_measurements_0_adc_result_ch1_o(0) => 
        adc_measurements_0_adc_result_ch1_o_0, 
        adc_interface_0_result_ch2_o(11) => 
        adc_interface_0_result_ch2_o(11), 
        adc_interface_0_result_ch2_o(10) => 
        adc_interface_0_result_ch2_o(10), 
        adc_interface_0_result_ch2_o(9) => 
        adc_interface_0_result_ch2_o(9), 
        adc_interface_0_result_ch2_o(8) => 
        adc_interface_0_result_ch2_o(8), 
        adc_interface_0_result_ch2_o(7) => 
        adc_interface_0_result_ch2_o(7), 
        adc_interface_0_result_ch2_o(6) => 
        adc_interface_0_result_ch2_o(6), 
        adc_interface_0_result_ch2_o(5) => 
        adc_interface_0_result_ch2_o(5), 
        adc_interface_0_result_ch2_o(4) => 
        adc_interface_0_result_ch2_o(4), 
        adc_interface_0_result_ch2_o(3) => 
        adc_interface_0_result_ch2_o(3), 
        adc_interface_0_result_ch2_o(2) => 
        adc_interface_0_result_ch2_o(2), 
        adc_interface_0_result_ch2_o(1) => 
        adc_interface_0_result_ch2_o(1), 
        adc_interface_0_result_ch2_o(0) => 
        adc_interface_0_result_ch2_o(0), 
        adc_measurements_0_adc_result_ch3_o(11) => 
        adc_measurements_0_adc_result_ch3_o(11), 
        adc_measurements_0_adc_result_ch3_o(10) => 
        adc_measurements_0_adc_result_ch3_o(10), 
        adc_measurements_0_adc_result_ch3_o(9) => 
        adc_measurements_0_adc_result_ch3_o(9), 
        adc_measurements_0_adc_result_ch3_o(8) => 
        adc_measurements_0_adc_result_ch3_o(8), 
        adc_measurements_0_adc_result_ch3_o(7) => 
        adc_measurements_0_adc_result_ch3_o(7), 
        adc_measurements_0_adc_result_ch3_o(6) => 
        adc_measurements_0_adc_result_ch3_o(6), 
        adc_measurements_0_adc_result_ch3_o(5) => 
        adc_measurements_0_adc_result_ch3_o(5), 
        adc_measurements_0_adc_result_ch3_o(4) => 
        adc_measurements_0_adc_result_ch3_o(4), 
        adc_measurements_0_adc_result_ch3_o(3) => 
        adc_measurements_0_adc_result_ch3_o(3), 
        adc_measurements_0_adc_result_ch3_o(2) => 
        adc_measurements_0_adc_result_ch3_o(2), 
        adc_measurements_0_adc_result_ch3_o(1) => 
        adc_measurements_0_adc_result_ch3_o_1, 
        adc_measurements_0_adc_result_ch3_o(0) => 
        adc_measurements_0_adc_result_ch3_o(0), 
        apb3_if_st_0_adc_channel_ch2_o(15) => 
        apb3_if_st_0_adc_channel_ch2_o(15), 
        apb3_if_st_0_adc_channel_ch2_o(14) => 
        apb3_if_st_0_adc_channel_ch2_o(14), 
        apb3_if_st_0_adc_channel_ch2_o(13) => 
        apb3_if_st_0_adc_channel_ch2_o(13), 
        apb3_if_st_0_adc_channel_ch2_o(12) => 
        apb3_if_st_0_adc_channel_ch2_o(12), 
        apb3_if_st_0_adc_channel_ch2_o(11) => 
        apb3_if_st_0_adc_channel_ch2_o(11), 
        apb3_if_st_0_adc_channel_ch2_o(10) => 
        apb3_if_st_0_adc_channel_ch2_o(10), 
        apb3_if_st_0_adc_channel_ch2_o(9) => 
        apb3_if_st_0_adc_channel_ch2_o(9), 
        apb3_if_st_0_adc_channel_ch2_o(8) => 
        apb3_if_st_0_adc_channel_ch2_o(8), 
        apb3_if_st_0_adc_channel_ch2_o(7) => 
        apb3_if_st_0_adc_channel_ch2_o(7), 
        apb3_if_st_0_adc_channel_ch2_o(6) => 
        apb3_if_st_0_adc_channel_ch2_o(6), 
        apb3_if_st_0_adc_channel_ch2_o(5) => 
        apb3_if_st_0_adc_channel_ch2_o(5), 
        apb3_if_st_0_adc_channel_ch2_o(4) => 
        apb3_if_st_0_adc_channel_ch2_o(4), 
        apb3_if_st_0_adc_channel_ch2_o(3) => 
        apb3_if_st_0_adc_channel_ch2_o(3), 
        apb3_if_st_0_adc_channel_ch2_o(2) => 
        apb3_if_st_0_adc_channel_ch2_o(2), 
        apb3_if_st_0_adc_channel_ch2_o(1) => 
        apb3_if_st_0_adc_channel_ch2_o(1), 
        apb3_if_st_0_adc_channel_ch2_o(0) => 
        apb3_if_st_0_adc_channel_ch2_o(0), 
        apb3_if_st_0_adc_channel_ch1_o(15) => 
        apb3_if_st_0_adc_channel_ch1_o(15), 
        apb3_if_st_0_adc_channel_ch1_o(14) => 
        apb3_if_st_0_adc_channel_ch1_o(14), 
        apb3_if_st_0_adc_channel_ch1_o(13) => 
        apb3_if_st_0_adc_channel_ch1_o(13), 
        apb3_if_st_0_adc_channel_ch1_o(12) => 
        apb3_if_st_0_adc_channel_ch1_o(12), 
        apb3_if_st_0_adc_channel_ch1_o(11) => 
        apb3_if_st_0_adc_channel_ch1_o(11), 
        apb3_if_st_0_adc_channel_ch1_o(10) => 
        apb3_if_st_0_adc_channel_ch1_o(10), 
        apb3_if_st_0_adc_channel_ch1_o(9) => 
        apb3_if_st_0_adc_channel_ch1_o(9), 
        apb3_if_st_0_adc_channel_ch1_o(8) => 
        apb3_if_st_0_adc_channel_ch1_o(8), 
        apb3_if_st_0_adc_channel_ch1_o(7) => 
        apb3_if_st_0_adc_channel_ch1_o(7), 
        apb3_if_st_0_adc_channel_ch1_o(6) => 
        apb3_if_st_0_adc_channel_ch1_o(6), 
        apb3_if_st_0_adc_channel_ch1_o(5) => 
        apb3_if_st_0_adc_channel_ch1_o(5), 
        apb3_if_st_0_adc_channel_ch1_o(4) => 
        apb3_if_st_0_adc_channel_ch1_o(4), 
        apb3_if_st_0_adc_channel_ch1_o(3) => 
        apb3_if_st_0_adc_channel_ch1_o(3), 
        apb3_if_st_0_adc_channel_ch1_o(2) => 
        apb3_if_st_0_adc_channel_ch1_o(2), 
        apb3_if_st_0_adc_channel_ch1_o(1) => 
        apb3_if_st_0_adc_channel_ch1_o(1), 
        apb3_if_st_0_adc_channel_ch1_o(0) => 
        apb3_if_st_0_adc_channel_ch1_o(0), 
        apb3_if_st_0_adc_channel_ch3_o(15) => 
        apb3_if_st_0_adc_channel_ch3_o(15), 
        apb3_if_st_0_adc_channel_ch3_o(14) => 
        apb3_if_st_0_adc_channel_ch3_o(14), 
        apb3_if_st_0_adc_channel_ch3_o(13) => 
        apb3_if_st_0_adc_channel_ch3_o(13), 
        apb3_if_st_0_adc_channel_ch3_o(12) => 
        apb3_if_st_0_adc_channel_ch3_o(12), 
        apb3_if_st_0_adc_channel_ch3_o(11) => 
        apb3_if_st_0_adc_channel_ch3_o(11), 
        apb3_if_st_0_adc_channel_ch3_o(10) => 
        apb3_if_st_0_adc_channel_ch3_o(10), 
        apb3_if_st_0_adc_channel_ch3_o(9) => 
        apb3_if_st_0_adc_channel_ch3_o(9), 
        apb3_if_st_0_adc_channel_ch3_o(8) => 
        apb3_if_st_0_adc_channel_ch3_o(8), 
        apb3_if_st_0_adc_channel_ch3_o(7) => 
        apb3_if_st_0_adc_channel_ch3_o(7), 
        apb3_if_st_0_adc_channel_ch3_o(6) => 
        apb3_if_st_0_adc_channel_ch3_o(6), 
        apb3_if_st_0_adc_channel_ch3_o(5) => 
        apb3_if_st_0_adc_channel_ch3_o(5), 
        apb3_if_st_0_adc_channel_ch3_o(4) => 
        apb3_if_st_0_adc_channel_ch3_o(4), 
        apb3_if_st_0_adc_channel_ch3_o(3) => 
        apb3_if_st_0_adc_channel_ch3_o(3), 
        apb3_if_st_0_adc_channel_ch3_o(2) => 
        apb3_if_st_0_adc_channel_ch3_o(2), 
        apb3_if_st_0_adc_channel_ch3_o(1) => 
        apb3_if_st_0_adc_channel_ch3_o(1), 
        apb3_if_st_0_adc_channel_ch3_o(0) => 
        apb3_if_st_0_adc_channel_ch3_o(0), 
        apb3_if_st_0_adc_channel_ch0_o(15) => 
        apb3_if_st_0_adc_channel_ch0_o(15), 
        apb3_if_st_0_adc_channel_ch0_o(14) => 
        apb3_if_st_0_adc_channel_ch0_o(14), 
        apb3_if_st_0_adc_channel_ch0_o(13) => 
        apb3_if_st_0_adc_channel_ch0_o(13), 
        apb3_if_st_0_adc_channel_ch0_o(12) => 
        apb3_if_st_0_adc_channel_ch0_o(12), 
        apb3_if_st_0_adc_channel_ch0_o(11) => 
        apb3_if_st_0_adc_channel_ch0_o(11), 
        apb3_if_st_0_adc_channel_ch0_o(10) => 
        apb3_if_st_0_adc_channel_ch0_o(10), 
        apb3_if_st_0_adc_channel_ch0_o(9) => 
        apb3_if_st_0_adc_channel_ch0_o(9), 
        apb3_if_st_0_adc_channel_ch0_o(8) => 
        apb3_if_st_0_adc_channel_ch0_o(8), 
        apb3_if_st_0_adc_channel_ch0_o(7) => 
        apb3_if_st_0_adc_channel_ch0_o(7), 
        apb3_if_st_0_adc_channel_ch0_o(6) => 
        apb3_if_st_0_adc_channel_ch0_o(6), 
        apb3_if_st_0_adc_channel_ch0_o(5) => 
        apb3_if_st_0_adc_channel_ch0_o(5), 
        apb3_if_st_0_adc_channel_ch0_o(4) => 
        apb3_if_st_0_adc_channel_ch0_o(4), 
        apb3_if_st_0_adc_channel_ch0_o(3) => 
        apb3_if_st_0_adc_channel_ch0_o(3), 
        apb3_if_st_0_adc_channel_ch0_o(2) => 
        apb3_if_st_0_adc_channel_ch0_o(2), 
        apb3_if_st_0_adc_channel_ch0_o(1) => 
        apb3_if_st_0_adc_channel_ch0_o(1), 
        apb3_if_st_0_adc_channel_ch0_o(0) => 
        apb3_if_st_0_adc_channel_ch0_o(0), MC_System_0_FIC_0_LOCK
         => MC_System_0_FIC_0_LOCK, MC_System_0_FAB_CCC_GL1 => 
        MC_System_0_FAB_CCC_GL1, SEQ_CONTROLLER_1_adc_start_o_0
         => SEQ_CONTROLLER_1_adc_start_o_0, A1_ADC_SDI_I_c => 
        A1_ADC_SDI_I_c, A1_ADC_SDO_O_c => A1_ADC_SDO_O_c, 
        A1_ADC_CS_O_c => A1_ADC_CS_O_c, A1_ADC_SCK_O_c => 
        A1_ADC_SCK_O_c, adc_interface_0_results_rdy_o => 
        adc_interface_0_results_rdy_o);
    
    MSC_i_36 : FOC_TRANSFORMS_1
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FAB_CCC_GL1, start_clarke_i => \GND\, 
        start_park_i => ADC_SCALING_0_done_o, start_ipark_i => 
        SPEED_ID_IQ_PI_1_id_pi_done_o, start_iclarke_i => \GND\, 
        ia_i(17) => \GND\, ia_i(16) => \GND\, ia_i(15) => \GND\, 
        ia_i(14) => \GND\, ia_i(13) => \GND\, ia_i(12) => \GND\, 
        ia_i(11) => \GND\, ia_i(10) => \GND\, ia_i(9) => \GND\, 
        ia_i(8) => \GND\, ia_i(7) => \GND\, ia_i(6) => \GND\, 
        ia_i(5) => \GND\, ia_i(4) => \GND\, ia_i(3) => \GND\, 
        ia_i(2) => \GND\, ia_i(1) => \GND\, ia_i(0) => \GND\, 
        ib_i(17) => \GND\, ib_i(16) => \GND\, ib_i(15) => \GND\, 
        ib_i(14) => \GND\, ib_i(13) => \GND\, ib_i(12) => \GND\, 
        ib_i(11) => \GND\, ib_i(10) => \GND\, ib_i(9) => \GND\, 
        ib_i(8) => \GND\, ib_i(7) => \GND\, ib_i(6) => \GND\, 
        ib_i(5) => \GND\, ib_i(4) => \GND\, ib_i(3) => \GND\, 
        ib_i(2) => \GND\, ib_i(1) => \GND\, ib_i(0) => \GND\, 
        ialpha_i(17) => ADC_SCALING_0_ia_adc_o(17), ialpha_i(16)
         => ADC_SCALING_0_ia_adc_o(16), ialpha_i(15) => 
        \ADC_SCALING_0_ia_adc_o_15\, ialpha_i(14) => 
        ADC_SCALING_0_ia_adc_o(14), ialpha_i(13) => 
        ADC_SCALING_0_ia_adc_o(13), ialpha_i(12) => 
        \ADC_SCALING_0_ia_adc_o_12\, ialpha_i(11) => 
        \ADC_SCALING_0_ia_adc_o_11\, ialpha_i(10) => 
        \ADC_SCALING_0_ia_adc_o_10\, ialpha_i(9) => 
        \ADC_SCALING_0_ia_adc_o_9\, ialpha_i(8) => 
        \ADC_SCALING_0_ia_adc_o_8\, ialpha_i(7) => 
        \ADC_SCALING_0_ia_adc_o_7\, ialpha_i(6) => 
        \ADC_SCALING_0_ia_adc_o_6\, ialpha_i(5) => 
        \ADC_SCALING_0_ia_adc_o_5\, ialpha_i(4) => 
        \ADC_SCALING_0_ia_adc_o_4\, ialpha_i(3) => 
        ADC_SCALING_0_ia_adc_o(3), ialpha_i(2) => 
        \ADC_SCALING_0_ia_adc_o_2\, ialpha_i(1) => 
        \ADC_SCALING_0_ia_adc_o_1\, ialpha_i(0) => \GND\, 
        ibeta_i(17) => ADC_SCALING_0_ib_adc_o(17), ibeta_i(16)
         => ADC_SCALING_0_ib_adc_o(16), ibeta_i(15) => 
        \ADC_SCALING_0_ib_adc_o_15\, ibeta_i(14) => 
        ADC_SCALING_0_ib_adc_o(14), ibeta_i(13) => 
        ADC_SCALING_0_ib_adc_o(13), ibeta_i(12) => 
        \ADC_SCALING_0_ib_adc_o_12\, ibeta_i(11) => 
        \ADC_SCALING_0_ib_adc_o_11\, ibeta_i(10) => 
        ADC_SCALING_0_ib_adc_o(10), ibeta_i(9) => 
        \ADC_SCALING_0_ib_adc_o_9\, ibeta_i(8) => 
        \ADC_SCALING_0_ib_adc_o_8\, ibeta_i(7) => 
        ADC_SCALING_0_ib_adc_o(7), ibeta_i(6) => 
        \ADC_SCALING_0_ib_adc_o_6\, ibeta_i(5) => 
        \ADC_SCALING_0_ib_adc_o_5\, ibeta_i(4) => 
        \ADC_SCALING_0_ib_adc_o_4\, ibeta_i(3) => 
        ADC_SCALING_0_ib_adc_o(3), ibeta_i(2) => 
        ADC_SCALING_0_ib_adc_o(2), ibeta_i(1) => 
        \ADC_SCALING_0_ib_adc_o_1\, ibeta_i(0) => \GND\, vd_i(17)
         => SPEED_ID_IQ_PI_1_id_pi_output_o(17), vd_i(16) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(16), vd_i(15) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(15), vd_i(14) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(14), vd_i(13) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(13), vd_i(12) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(12), vd_i(11) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(11), vd_i(10) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(10), vd_i(9) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(9), vd_i(8) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(8), vd_i(7) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(7), vd_i(6) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(6), vd_i(5) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(5), vd_i(4) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(4), vd_i(3) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(3), vd_i(2) => 
        SPEED_ID_IQ_PI_1_id_pi_output_o(2), vd_i(1) => 
        \SPEED_ID_IQ_PI_1_id_pi_output_o_1\, vd_i(0) => \GND\, 
        vq_i(17) => SPEED_ID_IQ_PI_1_iq_pi_output_o(17), vq_i(16)
         => SPEED_ID_IQ_PI_1_iq_pi_output_o(16), vq_i(15) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(15), vq_i(14) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(14), vq_i(13) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(13), vq_i(12) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(12), vq_i(11) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(11), vq_i(10) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(10), vq_i(9) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(9), vq_i(8) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(8), vq_i(7) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(7), vq_i(6) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(6), vq_i(5) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(5), vq_i(4) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(4), vq_i(3) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(3), vq_i(2) => 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(2), vq_i(1) => 
        \SPEED_ID_IQ_PI_1_iq_pi_output_o_1\, vq_i(0) => \GND\, 
        valpha_i(17) => \GND\, valpha_i(16) => \GND\, 
        valpha_i(15) => \GND\, valpha_i(14) => \GND\, 
        valpha_i(13) => \GND\, valpha_i(12) => \GND\, 
        valpha_i(11) => \GND\, valpha_i(10) => \GND\, valpha_i(9)
         => \GND\, valpha_i(8) => \GND\, valpha_i(7) => \GND\, 
        valpha_i(6) => \GND\, valpha_i(5) => \GND\, valpha_i(4)
         => \GND\, valpha_i(3) => \GND\, valpha_i(2) => \GND\, 
        valpha_i(1) => \GND\, valpha_i(0) => \GND\, vbeta_i(17)
         => \GND\, vbeta_i(16) => \GND\, vbeta_i(15) => \GND\, 
        vbeta_i(14) => \GND\, vbeta_i(13) => \GND\, vbeta_i(12)
         => \GND\, vbeta_i(11) => \GND\, vbeta_i(10) => \GND\, 
        vbeta_i(9) => \GND\, vbeta_i(8) => \GND\, vbeta_i(7) => 
        \GND\, vbeta_i(6) => \GND\, vbeta_i(5) => \GND\, 
        vbeta_i(4) => \GND\, vbeta_i(3) => \GND\, vbeta_i(2) => 
        \GND\, vbeta_i(1) => \GND\, vbeta_i(0) => \GND\, 
        theta_i(17) => \STEPPER_THETA_0_theta_output_o_17\, 
        theta_i(16) => STEPPER_THETA_0_theta_output_o(16), 
        theta_i(15) => STEPPER_THETA_0_theta_output_o(15), 
        theta_i(14) => STEPPER_THETA_0_theta_output_o(14), 
        theta_i(13) => STEPPER_THETA_0_theta_output_o(13), 
        theta_i(12) => STEPPER_THETA_0_theta_output_o(12), 
        theta_i(11) => STEPPER_THETA_0_theta_output_o(11), 
        theta_i(10) => STEPPER_THETA_0_theta_output_o(10), 
        theta_i(9) => STEPPER_THETA_0_theta_output_o(9), 
        theta_i(8) => STEPPER_THETA_0_theta_output_o(8), 
        theta_i(7) => STEPPER_THETA_0_theta_output_o(7), 
        theta_i(6) => STEPPER_THETA_0_theta_output_o(6), 
        theta_i(5) => STEPPER_THETA_0_theta_output_o(5), 
        theta_i(4) => STEPPER_THETA_0_theta_output_o(4), 
        theta_i(3) => STEPPER_THETA_0_theta_output_o(3), 
        theta_i(2) => STEPPER_THETA_0_theta_output_o(2), 
        theta_i(1) => STEPPER_THETA_0_theta_output_o(1), 
        theta_i(0) => STEPPER_THETA_0_theta_output_o(0), 
        clarke_done_o => clarke_done_o, park_done_o => 
        FOC_TRANSFORMS_0_park_done_o, ipark_done_o => 
        FOC_TRANSFORMS_1_ipark_done_o, iclarke_done_o => 
        iclarke_done_o, ialpha_o(17) => ialpha_o(17), 
        ialpha_o(16) => ialpha_o(16), ialpha_o(15) => 
        ialpha_o(15), ialpha_o(14) => ialpha_o(14), ialpha_o(13)
         => ialpha_o(13), ialpha_o(12) => ialpha_o(12), 
        ialpha_o(11) => ialpha_o(11), ialpha_o(10) => 
        ialpha_o(10), ialpha_o(9) => ialpha_o(9), ialpha_o(8) => 
        ialpha_o(8), ialpha_o(7) => ialpha_o(7), ialpha_o(6) => 
        ialpha_o(6), ialpha_o(5) => ialpha_o(5), ialpha_o(4) => 
        ialpha_o(4), ialpha_o(3) => ialpha_o(3), ialpha_o(2) => 
        ialpha_o(2), ialpha_o(1) => ialpha_o(1), ialpha_o(0) => 
        ialpha_o(0), ibeta_o(17) => ibeta_o(17), ibeta_o(16) => 
        ibeta_o(16), ibeta_o(15) => ibeta_o(15), ibeta_o(14) => 
        ibeta_o(14), ibeta_o(13) => ibeta_o(13), ibeta_o(12) => 
        ibeta_o(12), ibeta_o(11) => ibeta_o(11), ibeta_o(10) => 
        ibeta_o(10), ibeta_o(9) => ibeta_o(9), ibeta_o(8) => 
        ibeta_o(8), ibeta_o(7) => ibeta_o(7), ibeta_o(6) => 
        ibeta_o(6), ibeta_o(5) => ibeta_o(5), ibeta_o(4) => 
        ibeta_o(4), ibeta_o(3) => ibeta_o(3), ibeta_o(2) => 
        ibeta_o(2), ibeta_o(1) => ibeta_o(1), ibeta_o(0) => 
        ibeta_o(0), id_o(17) => FOC_TRANSFORMS_0_id_o(17), 
        id_o(16) => FOC_TRANSFORMS_0_id_o(16), id_o(15) => 
        \FOC_TRANSFORMS_0_id_o_15\, id_o(14) => 
        FOC_TRANSFORMS_0_id_o(14), id_o(13) => 
        FOC_TRANSFORMS_0_id_o(13), id_o(12) => 
        \FOC_TRANSFORMS_0_id_o_12\, id_o(11) => 
        FOC_TRANSFORMS_0_id_o(11), id_o(10) => 
        \FOC_TRANSFORMS_0_id_o_10\, id_o(9) => 
        \FOC_TRANSFORMS_0_id_o_9\, id_o(8) => 
        \FOC_TRANSFORMS_0_id_o_8\, id_o(7) => 
        \FOC_TRANSFORMS_0_id_o_7\, id_o(6) => 
        FOC_TRANSFORMS_0_id_o(6), id_o(5) => 
        \FOC_TRANSFORMS_0_id_o_5\, id_o(4) => 
        FOC_TRANSFORMS_0_id_o(4), id_o(3) => 
        FOC_TRANSFORMS_0_id_o(3), id_o(2) => 
        FOC_TRANSFORMS_0_id_o(2), id_o(1) => 
        FOC_TRANSFORMS_0_id_o(1), id_o(0) => 
        \FOC_TRANSFORMS_0_id_o_0\, iq_o(17) => 
        FOC_TRANSFORMS_0_iq_o(17), iq_o(16) => 
        FOC_TRANSFORMS_0_iq_o(16), iq_o(15) => 
        \FOC_TRANSFORMS_0_iq_o_15\, iq_o(14) => 
        FOC_TRANSFORMS_0_iq_o(14), iq_o(13) => 
        FOC_TRANSFORMS_0_iq_o(13), iq_o(12) => 
        \FOC_TRANSFORMS_0_iq_o_12\, iq_o(11) => 
        \FOC_TRANSFORMS_0_iq_o_11\, iq_o(10) => 
        \FOC_TRANSFORMS_0_iq_o_10\, iq_o(9) => 
        FOC_TRANSFORMS_0_iq_o(9), iq_o(8) => 
        \FOC_TRANSFORMS_0_iq_o_8\, iq_o(7) => 
        \FOC_TRANSFORMS_0_iq_o_7\, iq_o(6) => 
        \FOC_TRANSFORMS_0_iq_o_6\, iq_o(5) => 
        \FOC_TRANSFORMS_0_iq_o_5\, iq_o(4) => 
        FOC_TRANSFORMS_0_iq_o(4), iq_o(3) => 
        \FOC_TRANSFORMS_0_iq_o_3\, iq_o(2) => 
        \FOC_TRANSFORMS_0_iq_o_2\, iq_o(1) => 
        \FOC_TRANSFORMS_0_iq_o_1\, iq_o(0) => 
        \FOC_TRANSFORMS_0_iq_o_0\, valpha_o(17) => 
        FOC_TRANSFORMS_1_valpha_o(17), valpha_o(16) => 
        FOC_TRANSFORMS_1_valpha_o(16), valpha_o(15) => 
        FOC_TRANSFORMS_1_valpha_o(15), valpha_o(14) => 
        FOC_TRANSFORMS_1_valpha_o(14), valpha_o(13) => 
        FOC_TRANSFORMS_1_valpha_o(13), valpha_o(12) => 
        FOC_TRANSFORMS_1_valpha_o(12), valpha_o(11) => 
        \FOC_TRANSFORMS_1_valpha_o_11\, valpha_o(10) => 
        \FOC_TRANSFORMS_1_valpha_o_10\, valpha_o(9) => 
        \FOC_TRANSFORMS_1_valpha_o_9\, valpha_o(8) => 
        \FOC_TRANSFORMS_1_valpha_o_8\, valpha_o(7) => 
        \FOC_TRANSFORMS_1_valpha_o_7\, valpha_o(6) => 
        \FOC_TRANSFORMS_1_valpha_o_6\, valpha_o(5) => 
        \FOC_TRANSFORMS_1_valpha_o_5\, valpha_o(4) => 
        \FOC_TRANSFORMS_1_valpha_o_4\, valpha_o(3) => 
        FOC_TRANSFORMS_1_valpha_o(3), valpha_o(2) => 
        FOC_TRANSFORMS_1_valpha_o(2), valpha_o(1) => 
        FOC_TRANSFORMS_1_valpha_o(1), valpha_o(0) => 
        \FOC_TRANSFORMS_1_valpha_o_0\, vbeta_o(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), vbeta_o(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), vbeta_o(15) => 
        \FOC_TRANSFORMS_0_vbeta_o_15\, vbeta_o(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), vbeta_o(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), vbeta_o(12) => 
        \FOC_TRANSFORMS_0_vbeta_o_12\, vbeta_o(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), vbeta_o(10) => 
        \FOC_TRANSFORMS_0_vbeta_o_10\, vbeta_o(9) => 
        FOC_TRANSFORMS_0_vbeta_o(9), vbeta_o(8) => 
        \FOC_TRANSFORMS_0_vbeta_o_8\, vbeta_o(7) => 
        \FOC_TRANSFORMS_0_vbeta_o_7\, vbeta_o(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), vbeta_o(5) => 
        \FOC_TRANSFORMS_0_vbeta_o_5\, vbeta_o(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), vbeta_o(3) => 
        \FOC_TRANSFORMS_0_vbeta_o_3\, vbeta_o(2) => 
        \FOC_TRANSFORMS_0_vbeta_o_2\, vbeta_o(1) => 
        FOC_TRANSFORMS_0_vbeta_o(1), vbeta_o(0) => 
        \FOC_TRANSFORMS_0_vbeta_o_0\, va_o(17) => va_o(17), 
        va_o(16) => va_o(16), va_o(15) => va_o(15), va_o(14) => 
        va_o(14), va_o(13) => va_o(13), va_o(12) => va_o(12), 
        va_o(11) => va_o(11), va_o(10) => va_o(10), va_o(9) => 
        va_o(9), va_o(8) => va_o(8), va_o(7) => va_o(7), va_o(6)
         => va_o(6), va_o(5) => va_o(5), va_o(4) => va_o(4), 
        va_o(3) => va_o(3), va_o(2) => va_o(2), va_o(1) => 
        va_o(1), va_o(0) => va_o(0), vb_o(17) => vb_o(17), 
        vb_o(16) => vb_o(16), vb_o(15) => vb_o(15), vb_o(14) => 
        vb_o(14), vb_o(13) => vb_o(13), vb_o(12) => vb_o(12), 
        vb_o(11) => vb_o(11), vb_o(10) => vb_o(10), vb_o(9) => 
        vb_o(9), vb_o(8) => vb_o(8), vb_o(7) => vb_o(7), vb_o(6)
         => vb_o(6), vb_o(5) => vb_o(5), vb_o(4) => vb_o(4), 
        vb_o(3) => vb_o(3), vb_o(2) => vb_o(2), vb_o(1) => 
        vb_o(1), vb_o(0) => vb_o(0), vc_o(17) => \vc_o\(17), 
        vc_o(16) => \vc_o\(16), vc_o(15) => \vc_o\(15), vc_o(14)
         => \vc_o\(14), vc_o(13) => \vc_o\(13), vc_o(12) => 
        \vc_o\(12), vc_o(11) => \vc_o\(11), vc_o(10) => 
        \vc_o\(10), vc_o(9) => \vc_o\(9), vc_o(8) => \vc_o\(8), 
        vc_o(7) => \vc_o\(7), vc_o(6) => \vc_o\(6), vc_o(5) => 
        \vc_o\(5), vc_o(4) => \vc_o\(4), vc_o(3) => \vc_o\(3), 
        vc_o(2) => \vc_o\(2), vc_o(1) => \vc_o\(1), vc_o(0) => 
        \vc_o\(0));
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_top is

    port( A0_ADC_SDI_I   : in    std_logic;
          A1_ADC_SDI_I   : in    std_logic;
          DEVRST_N       : in    std_logic;
          USB_ULPI_DIR   : in    std_logic;
          USB_ULPI_NXT   : in    std_logic;
          USB_ULPI_XCLK  : in    std_logic;
          A0_ADC_CS_O    : out   std_logic;
          A0_ADC_SCK_O   : out   std_logic;
          A0_ADC_SDO_O   : out   std_logic;
          A0_PWM_UH_O    : out   std_logic;
          A0_PWM_UL_O    : out   std_logic;
          A0_PWM_VH_O    : out   std_logic;
          A0_PWM_VL_O    : out   std_logic;
          A0_PWM_WH_O    : out   std_logic;
          A0_PWM_WL_O    : out   std_logic;
          A0_RUNNING_LED : out   std_logic;
          A1_ADC_CS_O    : out   std_logic;
          A1_ADC_SCK_O   : out   std_logic;
          A1_ADC_SDO_O   : out   std_logic;
          A1_PWM_UH_O    : out   std_logic;
          A1_PWM_UL_O    : out   std_logic;
          A1_PWM_VH_O    : out   std_logic;
          A1_PWM_VL_O    : out   std_logic;
          A1_PWM_WH_O    : out   std_logic;
          A1_PWM_WL_O    : out   std_logic;
          A1_RUNNING_LED : out   std_logic;
          GPIO_0_M2F     : out   std_logic;
          USB_ULPI_STP   : out   std_logic;
          USB_ULPI_DATA  : inout std_logic_vector(7 downto 0) := (others => 'Z')
        );

end MC_System_top;

architecture DEF_ARCH of MC_System_top is 

  component GND
    port( Y : out   std_logic
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MC_System
    port( prdata_o_1_2_0_a2_11_0                 : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_2_0_a2_12_0                 : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_26_0              : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_2_0_0_2                     : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_2_0_0_0                     : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_2_0_0_1                     : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI      : in    std_logic_vector(0 to 0) := (others => 'U');
          prdata_o_1_2_0_a2_17_0                 : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_iv_0_a2_20_0              : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_iv_0_0_a2_24_0              : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_iv_0_0_0_0                : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1_6_tz               : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1                    : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_0_iv_0_0                    : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_iv_0_0_0_2_tz_tz            : in    std_logic_vector(0 to 0) := (others => 'U');
          prdata_o_1_iv_0_0_4_2_1_0              : in    std_logic_vector(3 to 3) := (others => 'U');
          SPEED_ID_IQ_PI_1_id_pi_output_o        : in    std_logic_vector(1 downto 0) := (others => 'U');
          SPEED_ID_IQ_PI_1_iq_pi_output_o        : in    std_logic_vector(1 downto 0) := (others => 'U');
          prdata_o_1_2_0_0_4_2                   : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_iv_0_0_12_5_0               : in    std_logic_vector(3 to 3) := (others => 'U');
          STEPPER_THETA_0_theta_output_o         : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_a2_45_0              : in    std_logic_vector(0 to 0) := (others => 'U');
          adc_measurements_0_adc_result_ch3_o    : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_14_1              : in    std_logic_vector(1 to 1) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_0             : in    std_logic_vector(1 to 1) := (others => 'U');
          SEQ_CONTROLLER_1_state_o_2             : in    std_logic := 'U';
          SEQ_CONTROLLER_1_state_o_0_d0          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_1               : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_4               : in    std_logic := 'U';
          prdata_o_1_0_iv_0_2_tz_0               : in    std_logic := 'U';
          prdata_o_1_0_iv_0_12_1                 : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_0_iv_0_12_4                 : in    std_logic_vector(8 to 8) := (others => 'U');
          prdata_o_1_0_iv_0_a2_19_0              : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_0_iv_0_1_1                  : in    std_logic_vector(10 to 10) := (others => 'U');
          FOC_TRANSFORMS_1_valpha_o_0            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_5            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_8            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_9            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_4            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_7            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_10           : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_6            : in    std_logic := 'U';
          FOC_TRANSFORMS_1_valpha_o_11           : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_17        : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_3         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_6         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_9         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_0         : in    std_logic := 'U';
          STEPPER_THETA_1_step_count_o_5         : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_3             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_0             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_a2_6_2_5             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_0             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_3             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_5             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_8             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_12            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_15            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_7             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_10            : in    std_logic := 'U';
          FOC_TRANSFORMS_0_vbeta_o_2             : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_0                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_1                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_5                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_8                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_12               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_15               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_7                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_10               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_6                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_11               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_2                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_1                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_4                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_0_d0             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_2                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_7                : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_0_5                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_0                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_5                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_8                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_9                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_7                : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_10               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_12               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_15               : in    std_logic := 'U';
          prdata_o_1_0_iv_0_3_0                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_3_3                  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_0  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_5  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_8  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_10 : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_1  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_9  : in    std_logic := 'U';
          adc_measurements_0_adc_result_ch1_o_7  : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_6         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_11        : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_7         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_0         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_5         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_8         : in    std_logic := 'U';
          adc_interface_0_result_ch0_o_9         : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_0               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_7               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_10              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_2               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_5               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_8               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_9               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_12              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_15              : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_4               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_1               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_6               : in    std_logic := 'U';
          ADC_SCALING_0_ia_adc_o_11              : in    std_logic := 'U';
          prdata_o_1_0_iv_0_1_o2_0               : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_11                   : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_2_0_0_5                     : in    std_logic_vector(3 to 3) := (others => 'U');
          ADC_SCALING_0_ib_adc_o_10              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_5               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_4               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_7               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_8               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_11              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_14              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_3               : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o_0               : in    std_logic := 'U';
          prdata_o_1_iv_0_0_0_3_tz               : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_0_1                         : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_2                         : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_0                         : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_3_0_0_2                     : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_3_0_0_3                     : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_3_0_0_0                     : in    std_logic_vector(11 to 11) := (others => 'U');
          prdata_o_1_8_2                         : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_8_3                         : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_8_0                         : in    std_logic_vector(6 to 6) := (others => 'U');
          prdata_o_1_iv_0_0_12_4_3               : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_iv_0_0_12_4_2               : in    std_logic_vector(3 to 3) := (others => 'U');
          prdata_o_1_0_iv_0_5_1                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_4                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_2                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_7                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_5                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_0                  : in    std_logic := 'U';
          prdata_o_1_0_iv_0_5_12                 : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6                    : in    std_logic_vector(16 to 16) := (others => 'U');
          MC_System_0_AMBA_SLAVE_1_PRDATA        : in    std_logic_vector(14 downto 13) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA_0      : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_15     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_12     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_13     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PRDATA_14     : in    std_logic := 'U';
          USB_ULPI_DATA                          : inout   std_logic_vector(7 downto 0);
          MC_System_0_AMBA_SLAVE_1_PADDR         : inout   std_logic_vector(11 downto 0);
          MC_System_0_AMBA_SLAVE_1_PWDATA        : out   std_logic_vector(23 downto 0);
          MC_System_0_FIC_0_LOCK                 : out   std_logic;
          MC_System_0_FIC_0_CLK                  : out   std_logic;
          MC_System_0_FAB_CCC_GL1                : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx         : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PSELx         : out   std_logic;
          N_1342                                 : in    std_logic := 'U';
          N_2598                                 : in    std_logic := 'U';
          N_2644                                 : in    std_logic := 'U';
          N_1396                                 : in    std_logic := 'U';
          N_2631                                 : in    std_logic := 'U';
          prdata_m2_e_1_1                        : in    std_logic := 'U';
          N_1360                                 : in    std_logic := 'U';
          N_1288                                 : in    std_logic := 'U';
          prdata_m1_0_a2_0                       : in    std_logic := 'U';
          N_522                                  : in    std_logic := 'U';
          N_527                                  : in    std_logic := 'U';
          N_542                                  : in    std_logic := 'U';
          prdata_m4_e_0                          : in    std_logic := 'U';
          prdata_m1_0_a2_2_0                     : in    std_logic := 'U';
          N_509                                  : in    std_logic := 'U';
          N_529                                  : in    std_logic := 'U';
          N_503                                  : in    std_logic := 'U';
          prdata_m2_e_0                          : in    std_logic := 'U';
          N_508                                  : in    std_logic := 'U';
          N_2652                                 : in    std_logic := 'U';
          N_768                                  : in    std_logic := 'U';
          N_1345                                 : in    std_logic := 'U';
          N_2647                                 : in    std_logic := 'U';
          N_2531                                 : in    std_logic := 'U';
          N_513                                  : in    std_logic := 'U';
          N_502                                  : in    std_logic := 'U';
          N_534                                  : in    std_logic := 'U';
          N_500                                  : in    std_logic := 'U';
          N_514                                  : in    std_logic := 'U';
          N_506                                  : in    std_logic := 'U';
          N_505                                  : in    std_logic := 'U';
          N_518                                  : in    std_logic := 'U';
          N_2574                                 : in    std_logic := 'U';
          N_1346                                 : in    std_logic := 'U';
          N_531                                  : in    std_logic := 'U';
          N_2640                                 : in    std_logic := 'U';
          N_738                                  : in    std_logic := 'U';
          N_533                                  : in    std_logic := 'U';
          N_507                                  : in    std_logic := 'U';
          prdata_m1_e_0_1                        : in    std_logic := 'U';
          N_1398                                 : in    std_logic := 'U';
          N_1378                                 : in    std_logic := 'U';
          N_2627                                 : in    std_logic := 'U';
          prdata_m2_0_a2_0                       : in    std_logic := 'U';
          N_455                                  : in    std_logic := 'U';
          N_495                                  : in    std_logic := 'U';
          N_892                                  : in    std_logic := 'U';
          N_771                                  : in    std_logic := 'U';
          N_773                                  : in    std_logic := 'U';
          N_750                                  : in    std_logic := 'U';
          N_2639                                 : in    std_logic := 'U';
          N_775                                  : in    std_logic := 'U';
          N_763                                  : in    std_logic := 'U';
          N_2645                                 : in    std_logic := 'U';
          N_1351                                 : in    std_logic := 'U';
          N_1169                                 : in    std_logic := 'U';
          N_1279                                 : in    std_logic := 'U';
          N_793                                  : in    std_logic := 'U';
          N_791                                  : in    std_logic := 'U';
          N_782                                  : in    std_logic := 'U';
          N_893                                  : in    std_logic := 'U';
          N_788                                  : in    std_logic := 'U';
          N_772                                  : in    std_logic := 'U';
          N_749                                  : in    std_logic := 'U';
          N_774                                  : in    std_logic := 'U';
          N_762                                  : in    std_logic := 'U';
          N_1347                                 : in    std_logic := 'U';
          N_1165                                 : in    std_logic := 'U';
          N_1275                                 : in    std_logic := 'U';
          N_792                                  : in    std_logic := 'U';
          N_878                                  : in    std_logic := 'U';
          N_859                                  : in    std_logic := 'U';
          N_880                                  : in    std_logic := 'U';
          N_870                                  : in    std_logic := 'U';
          prdata_m2_e_0_0                        : in    std_logic := 'U';
          prdata_m1_e_11_0                       : in    std_logic := 'U';
          N_414                                  : in    std_logic := 'U';
          N_516                                  : in    std_logic := 'U';
          N_397                                  : in    std_logic := 'U';
          N_355                                  : in    std_logic := 'U';
          N_198                                  : in    std_logic := 'U';
          m20_i_2_tz                             : in    std_logic := 'U';
          m20_i_a2_0_1                           : in    std_logic := 'U';
          m20_m2_0_a2_1                          : in    std_logic := 'U';
          N_349                                  : in    std_logic := 'U';
          m20_i_a2_5_0                           : in    std_logic := 'U';
          N_517                                  : in    std_logic := 'U';
          N_128                                  : in    std_logic := 'U';
          N_528                                  : in    std_logic := 'U';
          N_524                                  : in    std_logic := 'U';
          N_454                                  : in    std_logic := 'U';
          N_494                                  : in    std_logic := 'U';
          N_894                                  : in    std_logic := 'U';
          N_1326                                 : in    std_logic := 'U';
          N_2646                                 : in    std_logic := 'U';
          N_770                                  : in    std_logic := 'U';
          N_777                                  : in    std_logic := 'U';
          N_883                                  : in    std_logic := 'U';
          N_1333                                 : in    std_logic := 'U';
          N_790                                  : in    std_logic := 'U';
          N_895                                  : in    std_logic := 'U';
          N_769                                  : in    std_logic := 'U';
          N_776                                  : in    std_logic := 'U';
          N_832                                  : in    std_logic := 'U';
          N_1329                                 : in    std_logic := 'U';
          N_789                                  : in    std_logic := 'U';
          N_876                                  : in    std_logic := 'U';
          N_882                                  : in    std_logic := 'U';
          prdata_m3_i_0                          : in    std_logic := 'U';
          N_260                                  : in    std_logic := 'U';
          N_766                                  : in    std_logic := 'U';
          N_739                                  : in    std_logic := 'U';
          N_891                                  : in    std_logic := 'U';
          N_767                                  : in    std_logic := 'U';
          N_875                                  : in    std_logic := 'U';
          N_396                                  : in    std_logic := 'U';
          N_405                                  : in    std_logic := 'U';
          N_354                                  : in    std_logic := 'U';
          N_363                                  : in    std_logic := 'U';
          prdata_N_7_2                           : in    std_logic := 'U';
          m20_i_10_1                             : in    std_logic := 'U';
          m20_i_10_0                             : in    std_logic := 'U';
          N_215                                  : in    std_logic := 'U';
          N_377                                  : in    std_logic := 'U';
          N_2495                                 : in    std_logic := 'U';
          N_2498                                 : in    std_logic := 'U';
          m20_i_11_5                             : in    std_logic := 'U';
          N_122                                  : in    std_logic := 'U';
          N_317                                  : in    std_logic := 'U';
          N_318                                  : in    std_logic := 'U';
          N_319                                  : in    std_logic := 'U';
          N_320                                  : in    std_logic := 'U';
          N_321                                  : in    std_logic := 'U';
          N_315                                  : in    std_logic := 'U';
          USB_ULPI_XCLK                          : in    std_logic := 'U';
          USB_ULPI_STP                           : out   std_logic;
          USB_ULPI_NXT                           : in    std_logic := 'U';
          USB_ULPI_DIR                           : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PENABLE       : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE        : out   std_logic;
          GPIO_0_M2F_c                           : out   std_logic
        );
  end component;

  component Bldc_Axis
    port( SEQ_CONTROLLER_1_state_o_1         : out   std_logic;
          SEQ_CONTROLLER_1_state_o_3         : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWDATA    : in    std_logic_vector(17 downto 0) := (others => 'U');
          prdata_o_1_2_0_a2_17_0             : out   std_logic_vector(1 to 1);
          prdata_o_1_2_0_a2_11_0             : out   std_logic_vector(1 to 1);
          MC_System_0_AMBA_SLAVE_1_PADDR     : in    std_logic_vector(11 downto 0) := (others => 'U');
          prdata_o_1_2_0_a2_12_0             : out   std_logic_vector(1 to 1);
          prdata_o_1_2_0_0_1                 : out   std_logic_vector(2 to 2);
          prdata_o_1_0_1                     : out   std_logic_vector(16 to 16);
          prdata_o_1_0_0                     : out   std_logic_vector(16 to 16);
          prdata_o_1_2_0_0_5                 : out   std_logic_vector(3 to 3);
          prdata_o_1_2_0_0_2                 : out   std_logic_vector(2 to 2);
          prdata_o_1_2_0_0_0                 : out   std_logic_vector(2 to 2);
          prdata_o_1_3_0_0_3                 : out   std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_2                 : out   std_logic_vector(11 to 11);
          prdata_o_1_3_0_0_0                 : out   std_logic_vector(11 to 11);
          prdata_o_1_8_3                     : out   std_logic_vector(6 to 6);
          prdata_o_1_8_2                     : out   std_logic_vector(6 to 6);
          prdata_o_1_8_0                     : out   std_logic_vector(6 to 6);
          prdata_o_1_0_2                     : out   std_logic_vector(16 to 16);
          prdata_o_1_2_0_0_4_2               : out   std_logic_vector(3 to 3);
          MC_System_0_AMBA_SLAVE_0_PRDATA_12 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_13 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_15 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_14 : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PRDATA_0  : out   std_logic;
          MC_System_0_FIC_0_LOCK             : in    std_logic := 'U';
          MC_System_0_FIC_0_CLK              : in    std_logic := 'U';
          A0_PWM_VL_O_c                      : out   std_logic;
          A0_PWM_UH_O_c                      : out   std_logic;
          A0_PWM_VH_O_c                      : out   std_logic;
          A0_PWM_WH_O_c                      : out   std_logic;
          A0_ADC_SDI_I_c                     : in    std_logic := 'U';
          A0_ADC_SDO_O_c                     : out   std_logic;
          A0_ADC_CS_O_c                      : out   std_logic;
          A0_ADC_SCK_O_c                     : out   std_logic;
          N_2627                             : out   std_logic;
          N_2574                             : out   std_logic;
          prdata_m2_e_1_1                    : out   std_logic;
          N_2645                             : out   std_logic;
          N_739                              : out   std_logic;
          N_766                              : out   std_logic;
          N_768                              : out   std_logic;
          N_769                              : out   std_logic;
          N_1345                             : out   std_logic;
          N_767                              : out   std_logic;
          N_875                              : out   std_logic;
          N_770                              : out   std_logic;
          N_771                              : out   std_logic;
          N_772                              : out   std_logic;
          N_876                              : out   std_logic;
          N_773                              : out   std_logic;
          N_1333                             : out   std_logic;
          N_1347                             : out   std_logic;
          N_1351                             : out   std_logic;
          N_1326                             : out   std_logic;
          N_1346                             : out   std_logic;
          N_878                              : out   std_logic;
          N_789                              : out   std_logic;
          N_791                              : out   std_logic;
          N_1329                             : out   std_logic;
          N_1342                             : out   std_logic;
          N_790                              : out   std_logic;
          N_891                              : out   std_logic;
          N_1360                             : out   std_logic;
          N_1378                             : out   std_logic;
          N_1396                             : out   std_logic;
          N_774                              : out   std_logic;
          N_775                              : out   std_logic;
          N_776                              : out   std_logic;
          N_777                              : out   std_logic;
          N_792                              : out   std_logic;
          N_793                              : out   std_logic;
          N_832                              : out   std_logic;
          N_880                              : out   std_logic;
          N_882                              : out   std_logic;
          N_883                              : out   std_logic;
          N_892                              : out   std_logic;
          N_893                              : out   std_logic;
          N_894                              : out   std_logic;
          N_895                              : out   std_logic;
          N_738                              : out   std_logic;
          N_502                              : out   std_logic;
          N_240                              : out   std_logic;
          N_549                              : out   std_logic;
          N_870                              : out   std_logic;
          N_859                              : out   std_logic;
          N_788                              : out   std_logic;
          N_782                              : out   std_logic;
          N_763                              : out   std_logic;
          N_762                              : out   std_logic;
          N_750                              : out   std_logic;
          N_749                              : out   std_logic;
          N_1288                             : out   std_logic;
          N_1279                             : out   std_logic;
          N_1275                             : out   std_logic;
          N_1169                             : out   std_logic;
          N_1165                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE    : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PENABLE   : in    std_logic := 'U';
          prdata_m1_e_0_1                    : out   std_logic;
          N_2631                             : out   std_logic;
          N_1398                             : out   std_logic;
          N_519                              : in    std_logic := 'U';
          N_540                              : in    std_logic := 'U';
          N_2644                             : out   std_logic;
          N_2639                             : out   std_logic;
          N_2647                             : out   std_logic;
          N_2640                             : out   std_logic;
          N_2598                             : out   std_logic;
          N_2646                             : out   std_logic;
          N_2652                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx     : in    std_logic := 'U';
          N_2495                             : out   std_logic;
          N_2498                             : out   std_logic;
          N_2531                             : out   std_logic;
          N_542                              : in    std_logic := 'U';
          N_544                              : in    std_logic := 'U'
        );
  end component;

  component Stepper_Axis
    port( STEPPER_THETA_0_theta_output_o_17      : out   std_logic;
          STEPPER_THETA_1_step_count_o_6         : out   std_logic;
          STEPPER_THETA_1_step_count_o_9         : out   std_logic;
          STEPPER_THETA_1_step_count_o_11        : out   std_logic;
          STEPPER_THETA_1_step_count_o_12        : out   std_logic;
          STEPPER_THETA_1_step_count_o_15        : out   std_logic;
          STEPPER_THETA_1_step_count_o_23        : out   std_logic;
          FOC_TRANSFORMS_0_id_o_0                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_5                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_7                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_8                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_9                : out   std_logic;
          FOC_TRANSFORMS_0_id_o_10               : out   std_logic;
          FOC_TRANSFORMS_0_id_o_12               : out   std_logic;
          FOC_TRANSFORMS_0_id_o_15               : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_0                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_1                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_2                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_3                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_5                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_6                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_7                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_8                : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_10               : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_11               : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_12               : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_15               : out   std_logic;
          SPEED_ID_IQ_PI_1_id_pi_output_o_0      : out   std_logic;
          SPEED_ID_IQ_PI_1_id_pi_output_o_1      : out   std_logic;
          SPEED_ID_IQ_PI_1_iq_pi_output_o_0      : out   std_logic;
          SPEED_ID_IQ_PI_1_iq_pi_output_o_1      : out   std_logic;
          SEQ_CONTROLLER_1_state_o_0_1           : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_0            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_4            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_5            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_6            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_7            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_8            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_9            : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_10           : out   std_logic;
          FOC_TRANSFORMS_1_valpha_o_11           : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_0             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_2             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_3             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_5             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_7             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_8             : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_10            : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_12            : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o_15            : out   std_logic;
          ADC_SCALING_0_ib_adc_o_1               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_4               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_5               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_6               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_8               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_9               : out   std_logic;
          ADC_SCALING_0_ib_adc_o_11              : out   std_logic;
          ADC_SCALING_0_ib_adc_o_12              : out   std_logic;
          ADC_SCALING_0_ib_adc_o_15              : out   std_logic;
          adc_interface_0_result_ch0_o_0         : out   std_logic;
          adc_interface_0_result_ch0_o_5         : out   std_logic;
          adc_interface_0_result_ch0_o_6         : out   std_logic;
          adc_interface_0_result_ch0_o_7         : out   std_logic;
          adc_interface_0_result_ch0_o_8         : out   std_logic;
          adc_interface_0_result_ch0_o_9         : out   std_logic;
          adc_interface_0_result_ch0_o_11        : out   std_logic;
          ADC_SCALING_0_ia_adc_o_1               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_2               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_4               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_5               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_6               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_7               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_8               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_9               : out   std_logic;
          ADC_SCALING_0_ia_adc_o_10              : out   std_logic;
          ADC_SCALING_0_ia_adc_o_11              : out   std_logic;
          ADC_SCALING_0_ia_adc_o_12              : out   std_logic;
          ADC_SCALING_0_ia_adc_o_15              : out   std_logic;
          ADC_SCALING_0_ia_adc_o_0               : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_0  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_1  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_5  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_7  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_8  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_9  : out   std_logic;
          adc_measurements_0_adc_result_ch1_o_10 : out   std_logic;
          adc_measurements_0_adc_result_ch3_o_1  : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWDATA        : in    std_logic_vector(23 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_12_4                 : out   std_logic_vector(8 to 8);
          prdata_o_1_2_0_a2_17_0                 : in    std_logic_vector(1 to 1) := (others => 'U');
          prdata_o_1_iv_0_0_a2_49_0_RNIGNRI      : out   std_logic_vector(0 to 0);
          prdata_o_1_iv_0_0_a2_45_0              : out   std_logic_vector(0 to 0);
          prdata_o_1_0_iv_0_1                    : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_4_2_1_0              : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_4_2               : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_12_5_0               : out   std_logic_vector(3 to 3);
          prdata_o_1_iv_0_0_a2_26_0              : out   std_logic_vector(1 to 1);
          MC_System_0_AMBA_SLAVE_1_PADDR         : in    std_logic_vector(11 downto 0) := (others => 'U');
          prdata_o_1_iv_0_0_a2_24_0              : out   std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_a2_6_2_0             : out   std_logic;
          prdata_o_1_0_iv_0_a2_6_2_3             : out   std_logic;
          prdata_o_1_0_iv_0_a2_6_2_5             : out   std_logic;
          prdata_o_1_0_iv_0_a2_20_0              : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_a2_19_0              : out   std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_a2_14_1              : out   std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_0_0_0                : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_0_0_7                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_1                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_5                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_4                : out   std_logic;
          prdata_o_1_0_iv_0_0_0_0_d0             : out   std_logic;
          prdata_o_1_0_iv_0_0_0_2                : out   std_logic;
          prdata_o_1_0_iv_0_1_1                  : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_12_1                 : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_0_2_tz_tz            : out   std_logic_vector(0 to 0);
          prdata_o_1_0_iv_0_3_0                  : out   std_logic;
          prdata_o_1_0_iv_0_3_3                  : out   std_logic;
          prdata_o_1_0_iv_0_1_6_tz               : out   std_logic_vector(10 to 10);
          prdata_o_1_0_iv_0_2_tz_0               : out   std_logic;
          prdata_o_1_0_iv_0_2_tz_4               : out   std_logic;
          prdata_o_1_0_iv_0_2_tz_1               : out   std_logic;
          prdata_o_1_iv_0_0_0_3_tz               : out   std_logic_vector(1 to 1);
          prdata_o_1_0_iv_0_1_o2_0               : out   std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_0                    : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_11                   : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_5_5                  : out   std_logic;
          prdata_o_1_0_iv_0_5_7                  : out   std_logic;
          prdata_o_1_0_iv_0_5_2                  : out   std_logic;
          prdata_o_1_0_iv_0_5_0                  : out   std_logic;
          prdata_o_1_0_iv_0_5_4                  : out   std_logic;
          prdata_o_1_0_iv_0_5_1                  : out   std_logic;
          prdata_o_1_0_iv_0_5_12                 : out   std_logic;
          prdata_o_1_iv_0_0_12_4_3               : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_6                    : out   std_logic_vector(16 to 16);
          MC_System_0_AMBA_SLAVE_1_PRDATA        : out   std_logic_vector(14 downto 13);
          MC_System_0_FIC_0_LOCK                 : in    std_logic := 'U';
          MC_System_0_FAB_CCC_GL1                : in    std_logic := 'U';
          A1_PWM_WL_O_c                          : out   std_logic;
          A1_PWM_UH_O_c                          : out   std_logic;
          A1_PWM_VH_O_c                          : out   std_logic;
          A1_PWM_UL_O_c                          : out   std_logic;
          A1_PWM_VL_O_c                          : out   std_logic;
          A1_ADC_SDI_I_c                         : in    std_logic := 'U';
          A1_ADC_SDO_O_c                         : out   std_logic;
          A1_ADC_CS_O_c                          : out   std_logic;
          A1_ADC_SCK_O_c                         : out   std_logic;
          N_503                                  : out   std_logic;
          N_500                                  : out   std_logic;
          N_505                                  : out   std_logic;
          N_240                                  : in    std_logic := 'U';
          N_514                                  : out   std_logic;
          N_507                                  : out   std_logic;
          N_509                                  : out   std_logic;
          N_506                                  : out   std_logic;
          N_522                                  : out   std_logic;
          N_542                                  : out   std_logic;
          N_516                                  : out   std_logic;
          N_502                                  : in    std_logic := 'U';
          prdata_m2_e_0                          : out   std_logic;
          N_519                                  : out   std_logic;
          N_540                                  : out   std_logic;
          N_544                                  : out   std_logic;
          N_517                                  : out   std_logic;
          N_128                                  : out   std_logic;
          m20_m2_0_a2_1                          : out   std_logic;
          prdata_m1_e_11_0                       : out   std_logic;
          prdata_m1_0_a2_2_0                     : out   std_logic;
          N_513                                  : out   std_logic;
          prdata_m3_i_0                          : out   std_logic;
          prdata_m2_0_a2_0                       : out   std_logic;
          prdata_m2_e_0_0                        : out   std_logic;
          m20_i_a2_5_0                           : out   std_logic;
          prdata_m1_0_a2_0                       : out   std_logic;
          m20_i_a2_0_1                           : out   std_logic;
          prdata_m4_e_0                          : out   std_logic;
          N_518                                  : out   std_logic;
          N_533                                  : out   std_logic;
          N_397                                  : out   std_logic;
          N_355                                  : out   std_logic;
          N_531                                  : out   std_logic;
          N_527                                  : out   std_logic;
          N_529                                  : out   std_logic;
          N_508                                  : out   std_logic;
          m20_i_2_tz                             : out   std_logic;
          N_494                                  : out   std_logic;
          N_454                                  : out   std_logic;
          N_414                                  : out   std_logic;
          N_198                                  : out   std_logic;
          m20_i_11_5                             : out   std_logic;
          prdata_N_7_2                           : out   std_logic;
          N_349                                  : out   std_logic;
          N_534                                  : out   std_logic;
          N_260                                  : out   std_logic;
          N_363                                  : out   std_logic;
          N_377                                  : out   std_logic;
          N_405                                  : out   std_logic;
          N_455                                  : out   std_logic;
          N_495                                  : out   std_logic;
          N_524                                  : out   std_logic;
          N_528                                  : out   std_logic;
          m20_i_10_1                             : out   std_logic;
          m20_i_10_0                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_1_PWRITE        : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PSELx         : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_1_PENABLE       : in    std_logic := 'U';
          N_215                                  : out   std_logic;
          N_315                                  : out   std_logic;
          N_317                                  : out   std_logic;
          N_318                                  : out   std_logic;
          N_319                                  : out   std_logic;
          N_320                                  : out   std_logic;
          N_321                                  : out   std_logic;
          N_354                                  : out   std_logic;
          N_396                                  : out   std_logic;
          N_122                                  : out   std_logic;
          N_549                                  : in    std_logic := 'U'
        );
  end component;

    signal MC_System_0_AMBA_SLAVE_1_PADDR : 
        std_logic_vector(11 downto 0);
    signal MC_System_0_AMBA_SLAVE_1_PWDATA : 
        std_logic_vector(23 downto 0);
    signal \Stepper_Axis_0.adc_interface_0_result_ch0_o\ : 
        std_logic_vector(11 downto 0);
    signal \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\
         : std_logic_vector(10 downto 0);
    signal \Stepper_Axis_0.adc_measurements_0_adc_result_ch3_o\
         : std_logic_vector(1 to 1);
    signal \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\ : 
        std_logic_vector(15 downto 0);
    signal \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\ : 
        std_logic_vector(15 downto 1);
    signal \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\ : 
        std_logic_vector(15 downto 0);
    signal \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\ : 
        std_logic_vector(15 downto 0);
    signal \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\ : 
        std_logic_vector(11 downto 0);
    signal \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\ : 
        std_logic_vector(15 downto 0);
    signal \Stepper_Axis_0.SPEED_ID_IQ_PI_1_id_pi_output_o\ : 
        std_logic_vector(1 downto 0);
    signal \Stepper_Axis_0.SPEED_ID_IQ_PI_1_iq_pi_output_o\ : 
        std_logic_vector(1 downto 0);
    signal \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\ : 
        std_logic_vector(23 downto 6);
    signal \Stepper_Axis_0.STEPPER_THETA_0_theta_output_o\ : 
        std_logic_vector(17 to 17);
    signal \Stepper_Axis_0.SEQ_CONTROLLER_1_state_o_0\ : 
        std_logic_vector(1 to 1);
    signal \Bldc_Axis_0.SEQ_CONTROLLER_1_state_o\ : 
        std_logic_vector(3 downto 1);
    signal MC_System_0_AMBA_SLAVE_0_PRDATA : 
        std_logic_vector(15 downto 0);
    signal MC_System_0_AMBA_SLAVE_1_PRDATA : 
        std_logic_vector(14 downto 13);
    signal 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_4_2_1_0\
         : std_logic_vector(3 to 3);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0\ : 
        std_logic_vector(7 to 7);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_0_3_tz\
         : std_logic_vector(1 to 1);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_12_0\ : 
        std_logic_vector(1 to 1);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_5\ : 
        std_logic_vector(3 to 3);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1\ : 
        std_logic_vector(7 to 7);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_11\ : 
        std_logic_vector(3 to 3);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\ : 
        std_logic_vector(16 downto 4);
    signal 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_0_2_tz_tz\
         : std_logic_vector(0 to 0);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_17_0\ : 
        std_logic_vector(1 to 1);
    signal 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_26_0\
         : std_logic_vector(1 to 1);
    signal 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_24_0\
         : std_logic_vector(1 to 1);
    signal 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_45_0\
         : std_logic_vector(0 to 0);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_o2_0\
         : std_logic_vector(17 to 17);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_3\ : 
        std_logic_vector(15 downto 12);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_2_tz\
         : std_logic_vector(8 downto 4);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_6_tz\
         : std_logic_vector(10 to 10);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_12_4\
         : std_logic_vector(8 to 8);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_5_0\
         : std_logic_vector(3 to 3);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_12_1\
         : std_logic_vector(7 to 7);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_1\ : 
        std_logic_vector(10 to 10);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\ : 
        std_logic_vector(11 downto 4);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0_0\
         : std_logic_vector(10 to 10);
    signal 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_14_1\
         : std_logic_vector(1 to 1);
    signal 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_19_0\
         : std_logic_vector(10 to 10);
    signal 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_20_0\
         : std_logic_vector(10 to 10);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_11_0\ : 
        std_logic_vector(1 to 1);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_6_2\
         : std_logic_vector(11 downto 6);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_4_2\
         : std_logic_vector(3 to 3);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_4_3\
         : std_logic_vector(3 to 3);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_4_2\ : 
        std_logic_vector(3 to 3);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0\ : 
        std_logic_vector(16 to 16);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1\ : 
        std_logic_vector(16 to 16);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2\ : 
        std_logic_vector(16 to 16);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_0\ : 
        std_logic_vector(6 to 6);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_2\ : 
        std_logic_vector(6 to 6);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_3\ : 
        std_logic_vector(6 to 6);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_0\ : 
        std_logic_vector(11 to 11);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_2\ : 
        std_logic_vector(11 to 11);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_3\ : 
        std_logic_vector(11 to 11);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_0\ : 
        std_logic_vector(2 to 2);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_1\ : 
        std_logic_vector(2 to 2);
    signal \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_2\ : 
        std_logic_vector(2 to 2);
    signal \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_6\ : 
        std_logic_vector(16 to 16);
    signal prdata_o_1_iv_0_0_a2_49_0_RNIGNRI : 
        std_logic_vector(0 to 0);
    signal MC_System_0_AMBA_SLAVE_1_PENABLE, 
        MC_System_0_AMBA_SLAVE_1_PWRITE, MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK, MC_System_0_FAB_CCC_GL1, \GND\, 
        \VCC\, A0_ADC_SDI_I_c, A1_ADC_SDI_I_c, A0_ADC_CS_O_c, 
        A0_ADC_SCK_O_c, A0_ADC_SDO_O_c, A0_PWM_UH_O_c, 
        A0_PWM_VH_O_c, A0_PWM_VL_O_c, A0_PWM_WH_O_c, 
        A1_ADC_CS_O_c, A1_ADC_SCK_O_c, A1_ADC_SDO_O_c, 
        A1_PWM_UH_O_c, A1_PWM_UL_O_c, A1_PWM_VH_O_c, 
        A1_PWM_VL_O_c, A1_PWM_WL_O_c, GPIO_0_M2F_c, 
        \Bldc_Axis_0.N_2627\, \Stepper_Axis_0.N_549\, 
        \Stepper_Axis_0.N_509\, \Stepper_Axis_0.N_513\, 
        \Stepper_Axis_0.N_508\, \Stepper_Axis_0.N_516\, 
        \Stepper_Axis_0.N_517\, \Stepper_Axis_0.N_518\, 
        \Stepper_Axis_0.N_506\, \Stepper_Axis_0.N_531\, 
        \Stepper_Axis_0.N_505\, \Stepper_Axis_0.N_533\, 
        \Stepper_Axis_0.N_542\, \Stepper_Axis_0.N_544\, 
        \Stepper_Axis_0.N_540\, MC_System_0_AMBA_SLAVE_0_PSELx, 
        \Bldc_Axis_0.N_2498\, \Bldc_Axis_0.N_2495\, 
        \Bldc_Axis_0.N_2531\, \Bldc_Axis_0.N_2574\, 
        \Bldc_Axis_0.N_2598\, MC_System_0_AMBA_SLAVE_1_PSELx, 
        \Stepper_Axis_0.N_128\, \Stepper_Axis_0.N_198\, 
        \Stepper_Axis_0.N_260\, \Stepper_Axis_0.N_215\, 
        \Stepper_Axis_0.N_349\, \Stepper_Axis_0.N_363\, 
        \Stepper_Axis_0.N_354\, \Stepper_Axis_0.N_355\, 
        \Stepper_Axis_0.N_377\, \Stepper_Axis_0.N_405\, 
        \Stepper_Axis_0.N_396\, \Stepper_Axis_0.N_397\, 
        \Stepper_Axis_0.N_414\, \Stepper_Axis_0.N_454\, 
        \Stepper_Axis_0.N_455\, \Stepper_Axis_0.N_494\, 
        \Stepper_Axis_0.N_495\, \Stepper_Axis_0.N_122\, 
        \Stepper_Axis_0.N_321\, \Stepper_Axis_0.N_320\, 
        \Stepper_Axis_0.N_319\, \Stepper_Axis_0.N_318\, 
        \Stepper_Axis_0.N_317\, \Stepper_Axis_0.N_315\, 
        \Stepper_Axis_0.N_528\, \Stepper_Axis_0.N_524\, 
        \Stepper_Axis_0.N_519\, \Stepper_Axis_0.N_534\, 
        \Stepper_Axis_0.N_529\, \Stepper_Axis_0.N_527\, 
        \Stepper_Axis_0.N_514\, \Stepper_Axis_0.N_503\, 
        \Stepper_Axis_0.N_507\, \Bldc_Axis_0.N_1165\, 
        \Bldc_Axis_0.N_1169\, \Bldc_Axis_0.N_1275\, 
        \Bldc_Axis_0.N_1279\, \Bldc_Axis_0.N_1329\, 
        \Bldc_Axis_0.N_1333\, \Bldc_Axis_0.N_1347\, 
        \Bldc_Axis_0.N_1351\, \Bldc_Axis_0.N_1345\, 
        \Bldc_Axis_0.N_1360\, \Bldc_Axis_0.N_1288\, 
        \Bldc_Axis_0.N_1342\, \Bldc_Axis_0.N_1326\, 
        \Bldc_Axis_0.N_1346\, \Bldc_Axis_0.N_1378\, 
        \Bldc_Axis_0.N_1396\, \Bldc_Axis_0.N_738\, 
        \Bldc_Axis_0.N_739\, \Bldc_Axis_0.N_749\, 
        \Bldc_Axis_0.N_750\, \Bldc_Axis_0.N_762\, 
        \Bldc_Axis_0.N_763\, \Bldc_Axis_0.N_766\, 
        \Bldc_Axis_0.N_767\, \Bldc_Axis_0.N_768\, 
        \Bldc_Axis_0.N_769\, \Bldc_Axis_0.N_770\, 
        \Bldc_Axis_0.N_771\, \Bldc_Axis_0.N_772\, 
        \Bldc_Axis_0.N_773\, \Bldc_Axis_0.N_774\, 
        \Bldc_Axis_0.N_775\, \Bldc_Axis_0.N_776\, 
        \Bldc_Axis_0.N_777\, \Bldc_Axis_0.N_782\, 
        \Bldc_Axis_0.N_788\, \Bldc_Axis_0.N_789\, 
        \Bldc_Axis_0.N_790\, \Bldc_Axis_0.N_791\, 
        \Bldc_Axis_0.N_792\, \Bldc_Axis_0.N_793\, 
        \Bldc_Axis_0.N_832\, \Bldc_Axis_0.N_859\, 
        \Bldc_Axis_0.N_870\, \Bldc_Axis_0.N_875\, 
        \Bldc_Axis_0.N_876\, \Bldc_Axis_0.N_878\, 
        \Bldc_Axis_0.N_880\, \Bldc_Axis_0.N_882\, 
        \Bldc_Axis_0.N_883\, \Bldc_Axis_0.N_891\, 
        \Bldc_Axis_0.N_892\, \Bldc_Axis_0.N_893\, 
        \Bldc_Axis_0.N_894\, \Bldc_Axis_0.N_895\, 
        \Bldc_Axis_0.N_1398\, \Bldc_Axis_0.N_2652\, 
        \Bldc_Axis_0.N_2647\, \Bldc_Axis_0.N_2631\, 
        \Bldc_Axis_0.N_2646\, \Bldc_Axis_0.N_2645\, 
        \Bldc_Axis_0.N_2644\, \Bldc_Axis_0.N_2640\, 
        \Bldc_Axis_0.N_2639\, \Stepper_Axis_0.N_240\, 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_2_tz\, 
        \Bldc_Axis_0.apb3_if_0.prdata_m2_e_1_1\, 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_11_5\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_N_7_2\, 
        \Stepper_Axis_0.N_502\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_e_0\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_0_a2_2_0\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_e_11_0\, 
        \Stepper_Axis_0.N_500\, 
        \Bldc_Axis_0.apb3_if_0.prdata_m1_e_0_1\, 
        \Stepper_Axis_0.apb3_if_st_0.m20_m2_0_a2_1\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m4_e_0\, 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_a2_0_1\, 
        \Stepper_Axis_0.N_522\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_0_a2_0\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_e_0_0\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_0_a2_0\, 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m3_i_0\, 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_a2_5_0\, 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_10_0\, 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_10_1\ : std_logic;

    for all : MC_System
	Use entity work.MC_System(DEF_ARCH);
    for all : Bldc_Axis
	Use entity work.Bldc_Axis(DEF_ARCH);
    for all : Stepper_Axis
	Use entity work.Stepper_Axis(DEF_ARCH);
begin 


    GND_Z : GND
      port map(Y => \GND\);
    
    A1_PWM_UL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_PWM_UL_O_c, PAD => A1_PWM_UL_O);
    
    A1_ADC_SDI_I_ibuf : INBUF
      generic map(IOSTD => "")

      port map(PAD => A1_ADC_SDI_I, Y => A1_ADC_SDI_I_c);
    
    A0_PWM_VH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VH_O_c, PAD => A0_PWM_VH_O);
    
    A0_PWM_UH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_UH_O_c, PAD => A0_PWM_UH_O);
    
    A1_PWM_VH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_PWM_VH_O_c, PAD => A1_PWM_VH_O);
    
    A0_PWM_WL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VL_O_c, PAD => A0_PWM_WL_O);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MC_System_0 : MC_System
      port map(prdata_o_1_2_0_a2_11_0(1) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_11_0\(1), 
        prdata_o_1_2_0_a2_12_0(1) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_12_0\(1), 
        prdata_o_1_iv_0_0_a2_26_0(1) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_26_0\(1), 
        prdata_o_1_2_0_0_2(2) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_2\(2), 
        prdata_o_1_2_0_0_0(2) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_0\(2), 
        prdata_o_1_2_0_0_1(2) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_1\(2), 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0) => 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0), 
        prdata_o_1_2_0_a2_17_0(1) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_17_0\(1), 
        prdata_o_1_0_iv_0_a2_20_0(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_20_0\(10), 
        prdata_o_1_iv_0_0_a2_24_0(1) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_24_0\(1), 
        prdata_o_1_0_iv_0_0_0_0(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0_0\(10), 
        prdata_o_1_0_iv_0_1_6_tz(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_6_tz\(10), 
        prdata_o_1_0_iv_0_1(7) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1\(7), 
        prdata_o_1_0_iv_0_0(7) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0\(7), 
        prdata_o_1_iv_0_0_0_2_tz_tz(0) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_0_2_tz_tz\(0), 
        prdata_o_1_iv_0_0_4_2_1_0(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_4_2_1_0\(3), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(1) => 
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_id_pi_output_o\(1), 
        SPEED_ID_IQ_PI_1_id_pi_output_o(0) => 
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_id_pi_output_o\(0), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(1) => 
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_iq_pi_output_o\(1), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o(0) => 
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_iq_pi_output_o\(0), 
        prdata_o_1_2_0_0_4_2(3) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_4_2\(3), 
        prdata_o_1_iv_0_0_12_5_0(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_5_0\(3), 
        STEPPER_THETA_0_theta_output_o(17) => 
        \Stepper_Axis_0.STEPPER_THETA_0_theta_output_o\(17), 
        prdata_o_1_iv_0_0_a2_45_0(0) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_45_0\(0), 
        adc_measurements_0_adc_result_ch3_o(1) => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch3_o\(1), 
        prdata_o_1_iv_0_0_a2_14_1(1) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_14_1\(1), 
        SEQ_CONTROLLER_1_state_o_0(1) => 
        \Stepper_Axis_0.SEQ_CONTROLLER_1_state_o_0\(1), 
        SEQ_CONTROLLER_1_state_o_2 => 
        \Bldc_Axis_0.SEQ_CONTROLLER_1_state_o\(3), 
        SEQ_CONTROLLER_1_state_o_0_d0 => 
        \Bldc_Axis_0.SEQ_CONTROLLER_1_state_o\(1), 
        prdata_o_1_0_iv_0_2_tz_1 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_2_tz\(5), 
        prdata_o_1_0_iv_0_2_tz_4 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_2_tz\(8), 
        prdata_o_1_0_iv_0_2_tz_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_2_tz\(4), 
        prdata_o_1_0_iv_0_12_1(7) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_12_1\(7), 
        prdata_o_1_0_iv_0_12_4(8) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_12_4\(8), 
        prdata_o_1_0_iv_0_a2_19_0(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_19_0\(10), 
        prdata_o_1_0_iv_0_1_1(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_1\(10), 
        FOC_TRANSFORMS_1_valpha_o_0 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(0), 
        FOC_TRANSFORMS_1_valpha_o_5 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(5), 
        FOC_TRANSFORMS_1_valpha_o_8 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(8), 
        FOC_TRANSFORMS_1_valpha_o_9 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(9), 
        FOC_TRANSFORMS_1_valpha_o_4 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(4), 
        FOC_TRANSFORMS_1_valpha_o_7 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(7), 
        FOC_TRANSFORMS_1_valpha_o_10 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(10), 
        FOC_TRANSFORMS_1_valpha_o_6 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(6), 
        FOC_TRANSFORMS_1_valpha_o_11 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(11), 
        STEPPER_THETA_1_step_count_o_17 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(23), 
        STEPPER_THETA_1_step_count_o_3 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(9), 
        STEPPER_THETA_1_step_count_o_6 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(12), 
        STEPPER_THETA_1_step_count_o_9 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(15), 
        STEPPER_THETA_1_step_count_o_0 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(6), 
        STEPPER_THETA_1_step_count_o_5 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(11), 
        prdata_o_1_0_iv_0_a2_6_2_3 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_6_2\(9), 
        prdata_o_1_0_iv_0_a2_6_2_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_6_2\(6), 
        prdata_o_1_0_iv_0_a2_6_2_5 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_6_2\(11), 
        FOC_TRANSFORMS_0_vbeta_o_0 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(0), 
        FOC_TRANSFORMS_0_vbeta_o_3 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(3), 
        FOC_TRANSFORMS_0_vbeta_o_5 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(5), 
        FOC_TRANSFORMS_0_vbeta_o_8 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(8), 
        FOC_TRANSFORMS_0_vbeta_o_12 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(12), 
        FOC_TRANSFORMS_0_vbeta_o_15 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(15), 
        FOC_TRANSFORMS_0_vbeta_o_7 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(7), 
        FOC_TRANSFORMS_0_vbeta_o_10 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(10), 
        FOC_TRANSFORMS_0_vbeta_o_2 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(2), 
        FOC_TRANSFORMS_0_iq_o_0 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(0), 
        FOC_TRANSFORMS_0_iq_o_1 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(1), 
        FOC_TRANSFORMS_0_iq_o_3 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(3), 
        FOC_TRANSFORMS_0_iq_o_5 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(5), 
        FOC_TRANSFORMS_0_iq_o_8 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(8), 
        FOC_TRANSFORMS_0_iq_o_12 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(12), 
        FOC_TRANSFORMS_0_iq_o_15 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(15), 
        FOC_TRANSFORMS_0_iq_o_7 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(7), 
        FOC_TRANSFORMS_0_iq_o_10 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(10), 
        FOC_TRANSFORMS_0_iq_o_6 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(6), 
        FOC_TRANSFORMS_0_iq_o_11 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(11), 
        FOC_TRANSFORMS_0_iq_o_2 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(2), 
        prdata_o_1_0_iv_0_0_0_1 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(5), 
        prdata_o_1_0_iv_0_0_0_4 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(8), 
        prdata_o_1_0_iv_0_0_0_0_d0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(4), 
        prdata_o_1_0_iv_0_0_0_2 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(6), 
        prdata_o_1_0_iv_0_0_0_7 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(11), 
        prdata_o_1_0_iv_0_0_0_5 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(9), 
        FOC_TRANSFORMS_0_id_o_0 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(0), 
        FOC_TRANSFORMS_0_id_o_5 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(5), 
        FOC_TRANSFORMS_0_id_o_8 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(8), 
        FOC_TRANSFORMS_0_id_o_9 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(9), 
        FOC_TRANSFORMS_0_id_o_7 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(7), 
        FOC_TRANSFORMS_0_id_o_10 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(10), 
        FOC_TRANSFORMS_0_id_o_12 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(12), 
        FOC_TRANSFORMS_0_id_o_15 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(15), 
        prdata_o_1_0_iv_0_3_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_3\(12), 
        prdata_o_1_0_iv_0_3_3 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_3\(15), 
        adc_measurements_0_adc_result_ch1_o_0 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(0), 
        adc_measurements_0_adc_result_ch1_o_5 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(5), 
        adc_measurements_0_adc_result_ch1_o_8 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(8), 
        adc_measurements_0_adc_result_ch1_o_10 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(10), 
        adc_measurements_0_adc_result_ch1_o_1 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(1), 
        adc_measurements_0_adc_result_ch1_o_9 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(9), 
        adc_measurements_0_adc_result_ch1_o_7 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(7), 
        adc_interface_0_result_ch0_o_6 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(6), 
        adc_interface_0_result_ch0_o_11 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(11), 
        adc_interface_0_result_ch0_o_7 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(7), 
        adc_interface_0_result_ch0_o_0 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(0), 
        adc_interface_0_result_ch0_o_5 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(5), 
        adc_interface_0_result_ch0_o_8 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(8), 
        adc_interface_0_result_ch0_o_9 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(9), 
        ADC_SCALING_0_ia_adc_o_0 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(0), 
        ADC_SCALING_0_ia_adc_o_7 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(7), 
        ADC_SCALING_0_ia_adc_o_10 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(10), 
        ADC_SCALING_0_ia_adc_o_2 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(2), 
        ADC_SCALING_0_ia_adc_o_5 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(5), 
        ADC_SCALING_0_ia_adc_o_8 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(8), 
        ADC_SCALING_0_ia_adc_o_9 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(9), 
        ADC_SCALING_0_ia_adc_o_12 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(12), 
        ADC_SCALING_0_ia_adc_o_15 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(15), 
        ADC_SCALING_0_ia_adc_o_4 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(4), 
        ADC_SCALING_0_ia_adc_o_1 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(1), 
        ADC_SCALING_0_ia_adc_o_6 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(6), 
        ADC_SCALING_0_ia_adc_o_11 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(11), 
        prdata_o_1_0_iv_0_1_o2_0(17) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_o2_0\(17), 
        prdata_o_1_iv_0_0_11(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_11\(3), 
        prdata_o_1_2_0_0_5(3) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_5\(3), 
        ADC_SCALING_0_ib_adc_o_10 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(11), 
        ADC_SCALING_0_ib_adc_o_5 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(6), 
        ADC_SCALING_0_ib_adc_o_4 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(5), 
        ADC_SCALING_0_ib_adc_o_7 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(8), 
        ADC_SCALING_0_ib_adc_o_8 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(9), 
        ADC_SCALING_0_ib_adc_o_11 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(12), 
        ADC_SCALING_0_ib_adc_o_14 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(15), 
        ADC_SCALING_0_ib_adc_o_3 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(4), 
        ADC_SCALING_0_ib_adc_o_0 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(1), 
        prdata_o_1_iv_0_0_0_3_tz(1) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_0_3_tz\(1), 
        prdata_o_1_0_1(16) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1\(16), 
        prdata_o_1_0_2(16) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2\(16), 
        prdata_o_1_0_0(16) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0\(16), 
        prdata_o_1_3_0_0_2(11) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_2\(11), 
        prdata_o_1_3_0_0_3(11) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_3\(11), 
        prdata_o_1_3_0_0_0(11) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_0\(11), 
        prdata_o_1_8_2(6) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_2\(6), 
        prdata_o_1_8_3(6) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_3\(6), 
        prdata_o_1_8_0(6) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_0\(6), 
        prdata_o_1_iv_0_0_12_4_3(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_4_3\(3), 
        prdata_o_1_iv_0_0_12_4_2(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_4_2\(3), 
        prdata_o_1_0_iv_0_5_1 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(5), 
        prdata_o_1_0_iv_0_5_4 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(8), 
        prdata_o_1_0_iv_0_5_2 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(6), 
        prdata_o_1_0_iv_0_5_7 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(11), 
        prdata_o_1_0_iv_0_5_5 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(9), 
        prdata_o_1_0_iv_0_5_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(4), 
        prdata_o_1_0_iv_0_5_12 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(16), 
        prdata_o_1_0_iv_0_6(16) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_6\(16), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(0), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(15), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(12), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(14), USB_ULPI_DATA(7) => 
        USB_ULPI_DATA(7), USB_ULPI_DATA(6) => USB_ULPI_DATA(6), 
        USB_ULPI_DATA(5) => USB_ULPI_DATA(5), USB_ULPI_DATA(4)
         => USB_ULPI_DATA(4), USB_ULPI_DATA(3) => 
        USB_ULPI_DATA(3), USB_ULPI_DATA(2) => USB_ULPI_DATA(2), 
        USB_ULPI_DATA(1) => USB_ULPI_DATA(1), USB_ULPI_DATA(0)
         => USB_ULPI_DATA(0), MC_System_0_AMBA_SLAVE_1_PADDR(11)
         => MC_System_0_AMBA_SLAVE_1_PADDR(11), 
        MC_System_0_AMBA_SLAVE_1_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), 
        MC_System_0_AMBA_SLAVE_1_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), 
        MC_System_0_AMBA_SLAVE_1_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        MC_System_0_AMBA_SLAVE_1_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), 
        MC_System_0_AMBA_SLAVE_1_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), 
        MC_System_0_AMBA_SLAVE_1_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), 
        MC_System_0_AMBA_SLAVE_1_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), 
        MC_System_0_AMBA_SLAVE_1_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        MC_System_0_AMBA_SLAVE_1_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        MC_System_0_AMBA_SLAVE_1_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK => MC_System_0_FIC_0_CLK, 
        MC_System_0_FAB_CCC_GL1 => MC_System_0_FAB_CCC_GL1, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, 
        MC_System_0_AMBA_SLAVE_1_PSELx => 
        MC_System_0_AMBA_SLAVE_1_PSELx, N_1342 => 
        \Bldc_Axis_0.N_1342\, N_2598 => \Bldc_Axis_0.N_2598\, 
        N_2644 => \Bldc_Axis_0.N_2644\, N_1396 => 
        \Bldc_Axis_0.N_1396\, N_2631 => \Bldc_Axis_0.N_2631\, 
        prdata_m2_e_1_1 => 
        \Bldc_Axis_0.apb3_if_0.prdata_m2_e_1_1\, N_1360 => 
        \Bldc_Axis_0.N_1360\, N_1288 => \Bldc_Axis_0.N_1288\, 
        prdata_m1_0_a2_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_0_a2_0\, N_522 => 
        \Stepper_Axis_0.N_522\, N_527 => \Stepper_Axis_0.N_527\, 
        N_542 => \Stepper_Axis_0.N_542\, prdata_m4_e_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m4_e_0\, 
        prdata_m1_0_a2_2_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_0_a2_2_0\, N_509
         => \Stepper_Axis_0.N_509\, N_529 => 
        \Stepper_Axis_0.N_529\, N_503 => \Stepper_Axis_0.N_503\, 
        prdata_m2_e_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_e_0\, N_508 => 
        \Stepper_Axis_0.N_508\, N_2652 => \Bldc_Axis_0.N_2652\, 
        N_768 => \Bldc_Axis_0.N_768\, N_1345 => 
        \Bldc_Axis_0.N_1345\, N_2647 => \Bldc_Axis_0.N_2647\, 
        N_2531 => \Bldc_Axis_0.N_2531\, N_513 => 
        \Stepper_Axis_0.N_513\, N_502 => \Stepper_Axis_0.N_502\, 
        N_534 => \Stepper_Axis_0.N_534\, N_500 => 
        \Stepper_Axis_0.N_500\, N_514 => \Stepper_Axis_0.N_514\, 
        N_506 => \Stepper_Axis_0.N_506\, N_505 => 
        \Stepper_Axis_0.N_505\, N_518 => \Stepper_Axis_0.N_518\, 
        N_2574 => \Bldc_Axis_0.N_2574\, N_1346 => 
        \Bldc_Axis_0.N_1346\, N_531 => \Stepper_Axis_0.N_531\, 
        N_2640 => \Bldc_Axis_0.N_2640\, N_738 => 
        \Bldc_Axis_0.N_738\, N_533 => \Stepper_Axis_0.N_533\, 
        N_507 => \Stepper_Axis_0.N_507\, prdata_m1_e_0_1 => 
        \Bldc_Axis_0.apb3_if_0.prdata_m1_e_0_1\, N_1398 => 
        \Bldc_Axis_0.N_1398\, N_1378 => \Bldc_Axis_0.N_1378\, 
        N_2627 => \Bldc_Axis_0.N_2627\, prdata_m2_0_a2_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_0_a2_0\, N_455 => 
        \Stepper_Axis_0.N_455\, N_495 => \Stepper_Axis_0.N_495\, 
        N_892 => \Bldc_Axis_0.N_892\, N_771 => 
        \Bldc_Axis_0.N_771\, N_773 => \Bldc_Axis_0.N_773\, N_750
         => \Bldc_Axis_0.N_750\, N_2639 => \Bldc_Axis_0.N_2639\, 
        N_775 => \Bldc_Axis_0.N_775\, N_763 => 
        \Bldc_Axis_0.N_763\, N_2645 => \Bldc_Axis_0.N_2645\, 
        N_1351 => \Bldc_Axis_0.N_1351\, N_1169 => 
        \Bldc_Axis_0.N_1169\, N_1279 => \Bldc_Axis_0.N_1279\, 
        N_793 => \Bldc_Axis_0.N_793\, N_791 => 
        \Bldc_Axis_0.N_791\, N_782 => \Bldc_Axis_0.N_782\, N_893
         => \Bldc_Axis_0.N_893\, N_788 => \Bldc_Axis_0.N_788\, 
        N_772 => \Bldc_Axis_0.N_772\, N_749 => 
        \Bldc_Axis_0.N_749\, N_774 => \Bldc_Axis_0.N_774\, N_762
         => \Bldc_Axis_0.N_762\, N_1347 => \Bldc_Axis_0.N_1347\, 
        N_1165 => \Bldc_Axis_0.N_1165\, N_1275 => 
        \Bldc_Axis_0.N_1275\, N_792 => \Bldc_Axis_0.N_792\, N_878
         => \Bldc_Axis_0.N_878\, N_859 => \Bldc_Axis_0.N_859\, 
        N_880 => \Bldc_Axis_0.N_880\, N_870 => 
        \Bldc_Axis_0.N_870\, prdata_m2_e_0_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_e_0_0\, 
        prdata_m1_e_11_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_e_11_0\, N_414 => 
        \Stepper_Axis_0.N_414\, N_516 => \Stepper_Axis_0.N_516\, 
        N_397 => \Stepper_Axis_0.N_397\, N_355 => 
        \Stepper_Axis_0.N_355\, N_198 => \Stepper_Axis_0.N_198\, 
        m20_i_2_tz => \Stepper_Axis_0.apb3_if_st_0.m20_i_2_tz\, 
        m20_i_a2_0_1 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_a2_0_1\, m20_m2_0_a2_1
         => \Stepper_Axis_0.apb3_if_st_0.m20_m2_0_a2_1\, N_349
         => \Stepper_Axis_0.N_349\, m20_i_a2_5_0 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_a2_5_0\, N_517 => 
        \Stepper_Axis_0.N_517\, N_128 => \Stepper_Axis_0.N_128\, 
        N_528 => \Stepper_Axis_0.N_528\, N_524 => 
        \Stepper_Axis_0.N_524\, N_454 => \Stepper_Axis_0.N_454\, 
        N_494 => \Stepper_Axis_0.N_494\, N_894 => 
        \Bldc_Axis_0.N_894\, N_1326 => \Bldc_Axis_0.N_1326\, 
        N_2646 => \Bldc_Axis_0.N_2646\, N_770 => 
        \Bldc_Axis_0.N_770\, N_777 => \Bldc_Axis_0.N_777\, N_883
         => \Bldc_Axis_0.N_883\, N_1333 => \Bldc_Axis_0.N_1333\, 
        N_790 => \Bldc_Axis_0.N_790\, N_895 => 
        \Bldc_Axis_0.N_895\, N_769 => \Bldc_Axis_0.N_769\, N_776
         => \Bldc_Axis_0.N_776\, N_832 => \Bldc_Axis_0.N_832\, 
        N_1329 => \Bldc_Axis_0.N_1329\, N_789 => 
        \Bldc_Axis_0.N_789\, N_876 => \Bldc_Axis_0.N_876\, N_882
         => \Bldc_Axis_0.N_882\, prdata_m3_i_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m3_i_0\, N_260 => 
        \Stepper_Axis_0.N_260\, N_766 => \Bldc_Axis_0.N_766\, 
        N_739 => \Bldc_Axis_0.N_739\, N_891 => 
        \Bldc_Axis_0.N_891\, N_767 => \Bldc_Axis_0.N_767\, N_875
         => \Bldc_Axis_0.N_875\, N_396 => \Stepper_Axis_0.N_396\, 
        N_405 => \Stepper_Axis_0.N_405\, N_354 => 
        \Stepper_Axis_0.N_354\, N_363 => \Stepper_Axis_0.N_363\, 
        prdata_N_7_2 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_N_7_2\, m20_i_10_1
         => \Stepper_Axis_0.apb3_if_st_0.m20_i_10_1\, m20_i_10_0
         => \Stepper_Axis_0.apb3_if_st_0.m20_i_10_0\, N_215 => 
        \Stepper_Axis_0.N_215\, N_377 => \Stepper_Axis_0.N_377\, 
        N_2495 => \Bldc_Axis_0.N_2495\, N_2498 => 
        \Bldc_Axis_0.N_2498\, m20_i_11_5 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_11_5\, N_122 => 
        \Stepper_Axis_0.N_122\, N_317 => \Stepper_Axis_0.N_317\, 
        N_318 => \Stepper_Axis_0.N_318\, N_319 => 
        \Stepper_Axis_0.N_319\, N_320 => \Stepper_Axis_0.N_320\, 
        N_321 => \Stepper_Axis_0.N_321\, N_315 => 
        \Stepper_Axis_0.N_315\, USB_ULPI_XCLK => USB_ULPI_XCLK, 
        USB_ULPI_STP => USB_ULPI_STP, USB_ULPI_NXT => 
        USB_ULPI_NXT, USB_ULPI_DIR => USB_ULPI_DIR, 
        MC_System_0_AMBA_SLAVE_1_PENABLE => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, 
        MC_System_0_AMBA_SLAVE_1_PWRITE => 
        MC_System_0_AMBA_SLAVE_1_PWRITE, GPIO_0_M2F_c => 
        GPIO_0_M2F_c);
    
    A1_PWM_WH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_PWM_WL_O_c, PAD => A1_PWM_WH_O);
    
    A1_PWM_UH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_PWM_UH_O_c, PAD => A1_PWM_UH_O);
    
    A1_ADC_SDO_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_ADC_SDO_O_c, PAD => A1_ADC_SDO_O);
    
    A0_ADC_SCK_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_ADC_SCK_O_c, PAD => A0_ADC_SCK_O);
    
    Bldc_Axis_0 : Bldc_Axis
      port map(SEQ_CONTROLLER_1_state_o_1 => 
        \Bldc_Axis_0.SEQ_CONTROLLER_1_state_o\(1), 
        SEQ_CONTROLLER_1_state_o_3 => 
        \Bldc_Axis_0.SEQ_CONTROLLER_1_state_o\(3), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0), 
        prdata_o_1_2_0_a2_17_0(1) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_17_0\(1), 
        prdata_o_1_2_0_a2_11_0(1) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_11_0\(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), 
        MC_System_0_AMBA_SLAVE_1_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), 
        MC_System_0_AMBA_SLAVE_1_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), 
        MC_System_0_AMBA_SLAVE_1_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        MC_System_0_AMBA_SLAVE_1_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), 
        MC_System_0_AMBA_SLAVE_1_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), 
        MC_System_0_AMBA_SLAVE_1_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), 
        MC_System_0_AMBA_SLAVE_1_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), 
        MC_System_0_AMBA_SLAVE_1_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        MC_System_0_AMBA_SLAVE_1_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        MC_System_0_AMBA_SLAVE_1_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        prdata_o_1_2_0_a2_12_0(1) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_12_0\(1), 
        prdata_o_1_2_0_0_1(2) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_1\(2), 
        prdata_o_1_0_1(16) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1\(16), 
        prdata_o_1_0_0(16) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0\(16), 
        prdata_o_1_2_0_0_5(3) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_5\(3), 
        prdata_o_1_2_0_0_2(2) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_2\(2), 
        prdata_o_1_2_0_0_0(2) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_0\(2), 
        prdata_o_1_3_0_0_3(11) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_3\(11), 
        prdata_o_1_3_0_0_2(11) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_2\(11), 
        prdata_o_1_3_0_0_0(11) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3_0_0_0\(11), 
        prdata_o_1_8_3(6) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_3\(6), 
        prdata_o_1_8_2(6) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_2\(6), 
        prdata_o_1_8_0(6) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_8_0\(6), 
        prdata_o_1_0_2(16) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2\(16), 
        prdata_o_1_2_0_0_4_2(3) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_0_4_2\(3), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_12 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(12), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_13 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_15 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(15), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_14 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(14), 
        MC_System_0_AMBA_SLAVE_0_PRDATA_0 => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(0), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK => MC_System_0_FIC_0_CLK, 
        A0_PWM_VL_O_c => A0_PWM_VL_O_c, A0_PWM_UH_O_c => 
        A0_PWM_UH_O_c, A0_PWM_VH_O_c => A0_PWM_VH_O_c, 
        A0_PWM_WH_O_c => A0_PWM_WH_O_c, A0_ADC_SDI_I_c => 
        A0_ADC_SDI_I_c, A0_ADC_SDO_O_c => A0_ADC_SDO_O_c, 
        A0_ADC_CS_O_c => A0_ADC_CS_O_c, A0_ADC_SCK_O_c => 
        A0_ADC_SCK_O_c, N_2627 => \Bldc_Axis_0.N_2627\, N_2574
         => \Bldc_Axis_0.N_2574\, prdata_m2_e_1_1 => 
        \Bldc_Axis_0.apb3_if_0.prdata_m2_e_1_1\, N_2645 => 
        \Bldc_Axis_0.N_2645\, N_739 => \Bldc_Axis_0.N_739\, N_766
         => \Bldc_Axis_0.N_766\, N_768 => \Bldc_Axis_0.N_768\, 
        N_769 => \Bldc_Axis_0.N_769\, N_1345 => 
        \Bldc_Axis_0.N_1345\, N_767 => \Bldc_Axis_0.N_767\, N_875
         => \Bldc_Axis_0.N_875\, N_770 => \Bldc_Axis_0.N_770\, 
        N_771 => \Bldc_Axis_0.N_771\, N_772 => 
        \Bldc_Axis_0.N_772\, N_876 => \Bldc_Axis_0.N_876\, N_773
         => \Bldc_Axis_0.N_773\, N_1333 => \Bldc_Axis_0.N_1333\, 
        N_1347 => \Bldc_Axis_0.N_1347\, N_1351 => 
        \Bldc_Axis_0.N_1351\, N_1326 => \Bldc_Axis_0.N_1326\, 
        N_1346 => \Bldc_Axis_0.N_1346\, N_878 => 
        \Bldc_Axis_0.N_878\, N_789 => \Bldc_Axis_0.N_789\, N_791
         => \Bldc_Axis_0.N_791\, N_1329 => \Bldc_Axis_0.N_1329\, 
        N_1342 => \Bldc_Axis_0.N_1342\, N_790 => 
        \Bldc_Axis_0.N_790\, N_891 => \Bldc_Axis_0.N_891\, N_1360
         => \Bldc_Axis_0.N_1360\, N_1378 => \Bldc_Axis_0.N_1378\, 
        N_1396 => \Bldc_Axis_0.N_1396\, N_774 => 
        \Bldc_Axis_0.N_774\, N_775 => \Bldc_Axis_0.N_775\, N_776
         => \Bldc_Axis_0.N_776\, N_777 => \Bldc_Axis_0.N_777\, 
        N_792 => \Bldc_Axis_0.N_792\, N_793 => 
        \Bldc_Axis_0.N_793\, N_832 => \Bldc_Axis_0.N_832\, N_880
         => \Bldc_Axis_0.N_880\, N_882 => \Bldc_Axis_0.N_882\, 
        N_883 => \Bldc_Axis_0.N_883\, N_892 => 
        \Bldc_Axis_0.N_892\, N_893 => \Bldc_Axis_0.N_893\, N_894
         => \Bldc_Axis_0.N_894\, N_895 => \Bldc_Axis_0.N_895\, 
        N_738 => \Bldc_Axis_0.N_738\, N_502 => 
        \Stepper_Axis_0.N_502\, N_240 => \Stepper_Axis_0.N_240\, 
        N_549 => \Stepper_Axis_0.N_549\, N_870 => 
        \Bldc_Axis_0.N_870\, N_859 => \Bldc_Axis_0.N_859\, N_788
         => \Bldc_Axis_0.N_788\, N_782 => \Bldc_Axis_0.N_782\, 
        N_763 => \Bldc_Axis_0.N_763\, N_762 => 
        \Bldc_Axis_0.N_762\, N_750 => \Bldc_Axis_0.N_750\, N_749
         => \Bldc_Axis_0.N_749\, N_1288 => \Bldc_Axis_0.N_1288\, 
        N_1279 => \Bldc_Axis_0.N_1279\, N_1275 => 
        \Bldc_Axis_0.N_1275\, N_1169 => \Bldc_Axis_0.N_1169\, 
        N_1165 => \Bldc_Axis_0.N_1165\, 
        MC_System_0_AMBA_SLAVE_1_PWRITE => 
        MC_System_0_AMBA_SLAVE_1_PWRITE, 
        MC_System_0_AMBA_SLAVE_1_PENABLE => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, prdata_m1_e_0_1 => 
        \Bldc_Axis_0.apb3_if_0.prdata_m1_e_0_1\, N_2631 => 
        \Bldc_Axis_0.N_2631\, N_1398 => \Bldc_Axis_0.N_1398\, 
        N_519 => \Stepper_Axis_0.N_519\, N_540 => 
        \Stepper_Axis_0.N_540\, N_2644 => \Bldc_Axis_0.N_2644\, 
        N_2639 => \Bldc_Axis_0.N_2639\, N_2647 => 
        \Bldc_Axis_0.N_2647\, N_2640 => \Bldc_Axis_0.N_2640\, 
        N_2598 => \Bldc_Axis_0.N_2598\, N_2646 => 
        \Bldc_Axis_0.N_2646\, N_2652 => \Bldc_Axis_0.N_2652\, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, N_2495 => 
        \Bldc_Axis_0.N_2495\, N_2498 => \Bldc_Axis_0.N_2498\, 
        N_2531 => \Bldc_Axis_0.N_2531\, N_542 => 
        \Stepper_Axis_0.N_542\, N_544 => \Stepper_Axis_0.N_544\);
    
    Stepper_Axis_0 : Stepper_Axis
      port map(STEPPER_THETA_0_theta_output_o_17 => 
        \Stepper_Axis_0.STEPPER_THETA_0_theta_output_o\(17), 
        STEPPER_THETA_1_step_count_o_6 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(6), 
        STEPPER_THETA_1_step_count_o_9 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(9), 
        STEPPER_THETA_1_step_count_o_11 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(11), 
        STEPPER_THETA_1_step_count_o_12 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(12), 
        STEPPER_THETA_1_step_count_o_15 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(15), 
        STEPPER_THETA_1_step_count_o_23 => 
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o\(23), 
        FOC_TRANSFORMS_0_id_o_0 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(0), 
        FOC_TRANSFORMS_0_id_o_5 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(5), 
        FOC_TRANSFORMS_0_id_o_7 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(7), 
        FOC_TRANSFORMS_0_id_o_8 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(8), 
        FOC_TRANSFORMS_0_id_o_9 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(9), 
        FOC_TRANSFORMS_0_id_o_10 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(10), 
        FOC_TRANSFORMS_0_id_o_12 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(12), 
        FOC_TRANSFORMS_0_id_o_15 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o\(15), 
        FOC_TRANSFORMS_0_iq_o_0 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(0), 
        FOC_TRANSFORMS_0_iq_o_1 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(1), 
        FOC_TRANSFORMS_0_iq_o_2 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(2), 
        FOC_TRANSFORMS_0_iq_o_3 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(3), 
        FOC_TRANSFORMS_0_iq_o_5 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(5), 
        FOC_TRANSFORMS_0_iq_o_6 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(6), 
        FOC_TRANSFORMS_0_iq_o_7 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(7), 
        FOC_TRANSFORMS_0_iq_o_8 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(8), 
        FOC_TRANSFORMS_0_iq_o_10 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(10), 
        FOC_TRANSFORMS_0_iq_o_11 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(11), 
        FOC_TRANSFORMS_0_iq_o_12 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(12), 
        FOC_TRANSFORMS_0_iq_o_15 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o\(15), 
        SPEED_ID_IQ_PI_1_id_pi_output_o_0 => 
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_id_pi_output_o\(0), 
        SPEED_ID_IQ_PI_1_id_pi_output_o_1 => 
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_id_pi_output_o\(1), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o_0 => 
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_iq_pi_output_o\(0), 
        SPEED_ID_IQ_PI_1_iq_pi_output_o_1 => 
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_iq_pi_output_o\(1), 
        SEQ_CONTROLLER_1_state_o_0_1 => 
        \Stepper_Axis_0.SEQ_CONTROLLER_1_state_o_0\(1), 
        FOC_TRANSFORMS_1_valpha_o_0 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(0), 
        FOC_TRANSFORMS_1_valpha_o_4 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(4), 
        FOC_TRANSFORMS_1_valpha_o_5 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(5), 
        FOC_TRANSFORMS_1_valpha_o_6 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(6), 
        FOC_TRANSFORMS_1_valpha_o_7 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(7), 
        FOC_TRANSFORMS_1_valpha_o_8 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(8), 
        FOC_TRANSFORMS_1_valpha_o_9 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(9), 
        FOC_TRANSFORMS_1_valpha_o_10 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(10), 
        FOC_TRANSFORMS_1_valpha_o_11 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o\(11), 
        FOC_TRANSFORMS_0_vbeta_o_0 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(0), 
        FOC_TRANSFORMS_0_vbeta_o_2 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(2), 
        FOC_TRANSFORMS_0_vbeta_o_3 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(3), 
        FOC_TRANSFORMS_0_vbeta_o_5 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(5), 
        FOC_TRANSFORMS_0_vbeta_o_7 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(7), 
        FOC_TRANSFORMS_0_vbeta_o_8 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(8), 
        FOC_TRANSFORMS_0_vbeta_o_10 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(10), 
        FOC_TRANSFORMS_0_vbeta_o_12 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(12), 
        FOC_TRANSFORMS_0_vbeta_o_15 => 
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o\(15), 
        ADC_SCALING_0_ib_adc_o_1 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(1), 
        ADC_SCALING_0_ib_adc_o_4 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(4), 
        ADC_SCALING_0_ib_adc_o_5 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(5), 
        ADC_SCALING_0_ib_adc_o_6 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(6), 
        ADC_SCALING_0_ib_adc_o_8 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(8), 
        ADC_SCALING_0_ib_adc_o_9 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(9), 
        ADC_SCALING_0_ib_adc_o_11 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(11), 
        ADC_SCALING_0_ib_adc_o_12 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(12), 
        ADC_SCALING_0_ib_adc_o_15 => 
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o\(15), 
        adc_interface_0_result_ch0_o_0 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(0), 
        adc_interface_0_result_ch0_o_5 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(5), 
        adc_interface_0_result_ch0_o_6 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(6), 
        adc_interface_0_result_ch0_o_7 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(7), 
        adc_interface_0_result_ch0_o_8 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(8), 
        adc_interface_0_result_ch0_o_9 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(9), 
        adc_interface_0_result_ch0_o_11 => 
        \Stepper_Axis_0.adc_interface_0_result_ch0_o\(11), 
        ADC_SCALING_0_ia_adc_o_1 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(1), 
        ADC_SCALING_0_ia_adc_o_2 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(2), 
        ADC_SCALING_0_ia_adc_o_4 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(4), 
        ADC_SCALING_0_ia_adc_o_5 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(5), 
        ADC_SCALING_0_ia_adc_o_6 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(6), 
        ADC_SCALING_0_ia_adc_o_7 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(7), 
        ADC_SCALING_0_ia_adc_o_8 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(8), 
        ADC_SCALING_0_ia_adc_o_9 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(9), 
        ADC_SCALING_0_ia_adc_o_10 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(10), 
        ADC_SCALING_0_ia_adc_o_11 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(11), 
        ADC_SCALING_0_ia_adc_o_12 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(12), 
        ADC_SCALING_0_ia_adc_o_15 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(15), 
        ADC_SCALING_0_ia_adc_o_0 => 
        \Stepper_Axis_0.ADC_SCALING_0_ia_adc_o\(0), 
        adc_measurements_0_adc_result_ch1_o_0 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(0), 
        adc_measurements_0_adc_result_ch1_o_1 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(1), 
        adc_measurements_0_adc_result_ch1_o_5 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(5), 
        adc_measurements_0_adc_result_ch1_o_7 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(7), 
        adc_measurements_0_adc_result_ch1_o_8 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(8), 
        adc_measurements_0_adc_result_ch1_o_9 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(9), 
        adc_measurements_0_adc_result_ch1_o_10 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o\(10), 
        adc_measurements_0_adc_result_ch3_o_1 => 
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch3_o\(1), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(23), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(22), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(21), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(20), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(19), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(18), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_1_PWDATA(0), 
        prdata_o_1_0_iv_0_12_4(8) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_12_4\(8), 
        prdata_o_1_2_0_a2_17_0(1) => 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2_0_a2_17_0\(1), 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0) => 
        prdata_o_1_iv_0_0_a2_49_0_RNIGNRI(0), 
        prdata_o_1_iv_0_0_a2_45_0(0) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_45_0\(0), 
        prdata_o_1_0_iv_0_1(7) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1\(7), 
        prdata_o_1_iv_0_0_4_2_1_0(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_4_2_1_0\(3), 
        prdata_o_1_iv_0_0_12_4_2(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_4_2\(3), 
        prdata_o_1_iv_0_0_12_5_0(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_5_0\(3), 
        prdata_o_1_iv_0_0_a2_26_0(1) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_26_0\(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(11), 
        MC_System_0_AMBA_SLAVE_1_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(10), 
        MC_System_0_AMBA_SLAVE_1_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(9), 
        MC_System_0_AMBA_SLAVE_1_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(8), 
        MC_System_0_AMBA_SLAVE_1_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(7), 
        MC_System_0_AMBA_SLAVE_1_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(6), 
        MC_System_0_AMBA_SLAVE_1_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(5), 
        MC_System_0_AMBA_SLAVE_1_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(4), 
        MC_System_0_AMBA_SLAVE_1_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(3), 
        MC_System_0_AMBA_SLAVE_1_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(2), 
        MC_System_0_AMBA_SLAVE_1_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(1), 
        MC_System_0_AMBA_SLAVE_1_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_1_PADDR(0), 
        prdata_o_1_iv_0_0_a2_24_0(1) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_24_0\(1), 
        prdata_o_1_0_iv_0_a2_6_2_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_6_2\(6), 
        prdata_o_1_0_iv_0_a2_6_2_3 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_6_2\(9), 
        prdata_o_1_0_iv_0_a2_6_2_5 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_6_2\(11), 
        prdata_o_1_0_iv_0_a2_20_0(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_20_0\(10), 
        prdata_o_1_0_iv_0_a2_19_0(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_a2_19_0\(10), 
        prdata_o_1_iv_0_0_a2_14_1(1) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_a2_14_1\(1), 
        prdata_o_1_0_iv_0_0_0_0(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0_0\(10), 
        prdata_o_1_0_iv_0_0_0_7 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(11), 
        prdata_o_1_0_iv_0_0_0_1 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(5), 
        prdata_o_1_0_iv_0_0_0_5 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(9), 
        prdata_o_1_0_iv_0_0_0_4 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(8), 
        prdata_o_1_0_iv_0_0_0_0_d0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(4), 
        prdata_o_1_0_iv_0_0_0_2 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0_0\(6), 
        prdata_o_1_0_iv_0_1_1(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_1\(10), 
        prdata_o_1_0_iv_0_12_1(7) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_12_1\(7), 
        prdata_o_1_iv_0_0_0_2_tz_tz(0) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_0_2_tz_tz\(0), 
        prdata_o_1_0_iv_0_3_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_3\(12), 
        prdata_o_1_0_iv_0_3_3 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_3\(15), 
        prdata_o_1_0_iv_0_1_6_tz(10) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_6_tz\(10), 
        prdata_o_1_0_iv_0_2_tz_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_2_tz\(4), 
        prdata_o_1_0_iv_0_2_tz_4 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_2_tz\(8), 
        prdata_o_1_0_iv_0_2_tz_1 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_2_tz\(5), 
        prdata_o_1_iv_0_0_0_3_tz(1) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_0_3_tz\(1), 
        prdata_o_1_0_iv_0_1_o2_0(17) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_1_o2_0\(17), 
        prdata_o_1_0_iv_0_0(7) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_0\(7), 
        prdata_o_1_iv_0_0_11(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_11\(3), 
        prdata_o_1_0_iv_0_5_5 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(9), 
        prdata_o_1_0_iv_0_5_7 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(11), 
        prdata_o_1_0_iv_0_5_2 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(6), 
        prdata_o_1_0_iv_0_5_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(4), 
        prdata_o_1_0_iv_0_5_4 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(8), 
        prdata_o_1_0_iv_0_5_1 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(5), 
        prdata_o_1_0_iv_0_5_12 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_5\(16), 
        prdata_o_1_iv_0_0_12_4_3(3) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_0_0_12_4_3\(3), 
        prdata_o_1_0_iv_0_6(16) => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_0_6\(16), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(14), 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13) => 
        MC_System_0_AMBA_SLAVE_1_PRDATA(13), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FAB_CCC_GL1 => MC_System_0_FAB_CCC_GL1, 
        A1_PWM_WL_O_c => A1_PWM_WL_O_c, A1_PWM_UH_O_c => 
        A1_PWM_UH_O_c, A1_PWM_VH_O_c => A1_PWM_VH_O_c, 
        A1_PWM_UL_O_c => A1_PWM_UL_O_c, A1_PWM_VL_O_c => 
        A1_PWM_VL_O_c, A1_ADC_SDI_I_c => A1_ADC_SDI_I_c, 
        A1_ADC_SDO_O_c => A1_ADC_SDO_O_c, A1_ADC_CS_O_c => 
        A1_ADC_CS_O_c, A1_ADC_SCK_O_c => A1_ADC_SCK_O_c, N_503
         => \Stepper_Axis_0.N_503\, N_500 => 
        \Stepper_Axis_0.N_500\, N_505 => \Stepper_Axis_0.N_505\, 
        N_240 => \Stepper_Axis_0.N_240\, N_514 => 
        \Stepper_Axis_0.N_514\, N_507 => \Stepper_Axis_0.N_507\, 
        N_509 => \Stepper_Axis_0.N_509\, N_506 => 
        \Stepper_Axis_0.N_506\, N_522 => \Stepper_Axis_0.N_522\, 
        N_542 => \Stepper_Axis_0.N_542\, N_516 => 
        \Stepper_Axis_0.N_516\, N_502 => \Stepper_Axis_0.N_502\, 
        prdata_m2_e_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_e_0\, N_519 => 
        \Stepper_Axis_0.N_519\, N_540 => \Stepper_Axis_0.N_540\, 
        N_544 => \Stepper_Axis_0.N_544\, N_517 => 
        \Stepper_Axis_0.N_517\, N_128 => \Stepper_Axis_0.N_128\, 
        m20_m2_0_a2_1 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_m2_0_a2_1\, 
        prdata_m1_e_11_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_e_11_0\, 
        prdata_m1_0_a2_2_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_0_a2_2_0\, N_513
         => \Stepper_Axis_0.N_513\, prdata_m3_i_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m3_i_0\, 
        prdata_m2_0_a2_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_0_a2_0\, 
        prdata_m2_e_0_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m2_e_0_0\, 
        m20_i_a2_5_0 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_a2_5_0\, 
        prdata_m1_0_a2_0 => 
        \Stepper_Axis_0.apb3_if_st_0.prdata_m1_0_a2_0\, 
        m20_i_a2_0_1 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_a2_0_1\, prdata_m4_e_0
         => \Stepper_Axis_0.apb3_if_st_0.prdata_m4_e_0\, N_518
         => \Stepper_Axis_0.N_518\, N_533 => 
        \Stepper_Axis_0.N_533\, N_397 => \Stepper_Axis_0.N_397\, 
        N_355 => \Stepper_Axis_0.N_355\, N_531 => 
        \Stepper_Axis_0.N_531\, N_527 => \Stepper_Axis_0.N_527\, 
        N_529 => \Stepper_Axis_0.N_529\, N_508 => 
        \Stepper_Axis_0.N_508\, m20_i_2_tz => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_2_tz\, N_494 => 
        \Stepper_Axis_0.N_494\, N_454 => \Stepper_Axis_0.N_454\, 
        N_414 => \Stepper_Axis_0.N_414\, N_198 => 
        \Stepper_Axis_0.N_198\, m20_i_11_5 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_11_5\, prdata_N_7_2
         => \Stepper_Axis_0.apb3_if_st_0.prdata_N_7_2\, N_349 => 
        \Stepper_Axis_0.N_349\, N_534 => \Stepper_Axis_0.N_534\, 
        N_260 => \Stepper_Axis_0.N_260\, N_363 => 
        \Stepper_Axis_0.N_363\, N_377 => \Stepper_Axis_0.N_377\, 
        N_405 => \Stepper_Axis_0.N_405\, N_455 => 
        \Stepper_Axis_0.N_455\, N_495 => \Stepper_Axis_0.N_495\, 
        N_524 => \Stepper_Axis_0.N_524\, N_528 => 
        \Stepper_Axis_0.N_528\, m20_i_10_1 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_10_1\, m20_i_10_0 => 
        \Stepper_Axis_0.apb3_if_st_0.m20_i_10_0\, 
        MC_System_0_AMBA_SLAVE_1_PWRITE => 
        MC_System_0_AMBA_SLAVE_1_PWRITE, 
        MC_System_0_AMBA_SLAVE_1_PSELx => 
        MC_System_0_AMBA_SLAVE_1_PSELx, 
        MC_System_0_AMBA_SLAVE_1_PENABLE => 
        MC_System_0_AMBA_SLAVE_1_PENABLE, N_215 => 
        \Stepper_Axis_0.N_215\, N_315 => \Stepper_Axis_0.N_315\, 
        N_317 => \Stepper_Axis_0.N_317\, N_318 => 
        \Stepper_Axis_0.N_318\, N_319 => \Stepper_Axis_0.N_319\, 
        N_320 => \Stepper_Axis_0.N_320\, N_321 => 
        \Stepper_Axis_0.N_321\, N_354 => \Stepper_Axis_0.N_354\, 
        N_396 => \Stepper_Axis_0.N_396\, N_122 => 
        \Stepper_Axis_0.N_122\, N_549 => \Stepper_Axis_0.N_549\);
    
    A0_PWM_WH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_WH_O_c, PAD => A0_PWM_WH_O);
    
    A0_PWM_VL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VL_O_c, PAD => A0_PWM_VL_O);
    
    A0_PWM_UL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VL_O_c, PAD => A0_PWM_UL_O);
    
    A1_PWM_VL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_PWM_VL_O_c, PAD => A1_PWM_VL_O);
    
    A0_ADC_SDO_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_ADC_SDO_O_c, PAD => A0_ADC_SDO_O);
    
    GPIO_0_M2F_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => GPIO_0_M2F_c, PAD => GPIO_0_M2F);
    
    A0_ADC_CS_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_ADC_CS_O_c, PAD => A0_ADC_CS_O);
    
    A1_RUNNING_LED_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_PWM_VL_O_c, PAD => A1_RUNNING_LED);
    
    A1_ADC_CS_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_ADC_CS_O_c, PAD => A1_ADC_CS_O);
    
    A1_PWM_WL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_PWM_WL_O_c, PAD => A1_PWM_WL_O);
    
    A1_ADC_SCK_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A1_ADC_SCK_O_c, PAD => A1_ADC_SCK_O);
    
    A0_RUNNING_LED_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VL_O_c, PAD => A0_RUNNING_LED);
    
    A0_ADC_SDI_I_ibuf : INBUF
      generic map(IOSTD => "")

      port map(PAD => A0_ADC_SDI_I, Y => A0_ADC_SDI_I_c);
    

end DEF_ARCH; 
