`

    #Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016
    #install: F:\Microsemi\Libero_SoC_v11.8\SynplifyPro
    #OS: Windows 8 6.2
    #Hostname: W1064L-ASHWINM

    # Fri Dec 01 17:24:05 2017

    #Implementation: synthesis

    Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

    Synopsys VHDL Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

    @N:CD720 : std.vhd(146) | Setting time resolution to ps
    @N: : MC_System_top.vhd(17) | Top entity is set to MC_System_top.
    VHDL syntax check successful!
    @N:CD231 : std1164.vhd(890) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
    @N:CD630 : MC_System_top.vhd(17) | Synthesizing work.mc_system_top.rtl.
    @N:CD630 : Stepper_Axis.vhd(19) | Synthesizing work.stepper_axis.rtl.
    Post processing for work.accumulator_st.accumulator_st
    Post processing for work.stepper_theta.stepper_theta
    Post processing for work.mas_pi_spi.mas_pi_spi
    Post processing for work.pi_controller_spi.pi_controller_spi
    Post processing for work.pi_scheduler_spi.pi_scheduler_spi
    Post processing for work.speed_id_iq_pi.speed_id_iq_pi
    Post processing for work.seq_controller.seq_controller
    Post processing for work.mas_pwm_scl.mas_pwm_scl
    Post processing for work.pwm_scaling.pwm_scaling
    Post processing for work.pwm3ph.pwm3ph
    Post processing for work.mas_scheduler_foc.mas_scheduler_foc
    Post processing for work.mas_foc.mas_foc
    Post processing for work.inverse_clarke_foc.inverse_clarke_foc
    Post processing for work.cordic_scale.cordic_scale
    Post processing for work.cordic_rot_foc.cordic_rot_foc
    Post processing for work.cordic_scheduler_foc.cordic_scheduler_foc
    Post processing for work.clarke_foc.clarke_foc
    Post processing for work.foc_transforms.foc_transforms
    @N:CD630 : apb3_if_st.vhd(33) | Synthesizing work.apb3_if_st.apb3_if_st.
    Post processing for work.apb3_if_st.apb3_if_st
    Post processing for adc_scaling_lib.mas_adc_scl.mas_adc_scl
    Post processing for adc_scaling_lib.adc_scaling.adc_scaling
    @N:CD630 : adc_interface_795x.vhd(32) | Synthesizing work.adc_interface_795x.adc_interface.
    @N:CD231 : adc_interface_795x.vhd(128) | Using onehot encoding for type adc_op_state. For example, enumeration idle is mapped to "100000".
    @N:CD604 : adc_interface_795x.vhd(289) | OTHERS clause is not synthesized.
    @N:CD630 : adc_interface_795x.vhd(434) | Synthesizing work.spi_engine.spi_engine.
    Post processing for work.spi_engine.spi_engine
    @W:CL271 : adc_interface_795x.vhd(539) | Pruning unused bits 7 to 3 of s_sys_clk_count_4(7 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
    Post processing for work.adc_interface_795x.adc_interface
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(1) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(2) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(3) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(4) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(5) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(13) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(14) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL190 : adc_interface_795x.vhd(197) | Optimizing register bit s_spi_mosi(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL279 : adc_interface_795x.vhd(197) | Pruning register bits 15 to 13 of s_spi_mosi(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
    @W:CL279 : adc_interface_795x.vhd(197) | Pruning register bits 5 to 0 of s_spi_mosi(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
    Post processing for work.stepper_axis.rtl
    @N:CD630 : MC_System.vhd(17) | Synthesizing work.mc_system.rtl.
    @N:CD630 : MC_System_sb.vhd(20) | Synthesizing work.mc_system_sb.rtl.
    @N:CD630 : smartfusion2.vhd(786) | Synthesizing smartfusion2.sysreset.syn_black_box.
    Post processing for smartfusion2.sysreset.syn_black_box
    @N:CD630 : MC_System_sb_MSS.vhd(17) | Synthesizing work.mc_system_sb_mss.rtl.
    @N:CD630 : smartfusion2.vhd(434) | Synthesizing smartfusion2.bibuf.syn_black_box.
    Post processing for smartfusion2.bibuf.syn_black_box
    @N:CD630 : smartfusion2.vhd(403) | Synthesizing smartfusion2.inbuf.syn_black_box.
    Post processing for smartfusion2.inbuf.syn_black_box
    @N:CD630 : smartfusion2.vhd(423) | Synthesizing smartfusion2.tribuff.syn_black_box.
    Post processing for smartfusion2.tribuff.syn_black_box
    @N:CD630 : MC_System_sb_MSS_syn.vhd(10) | Synthesizing work.mss_010.def_arch.
    Post processing for work.mss_010.def_arch
    Post processing for work.mc_system_sb_mss.rtl
    @N:CD630 : MC_System_sb_FABOSC_0_OSC.vhd(8) | Synthesizing work.mc_system_sb_fabosc_0_osc.def_arch.
    @N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box.
    Post processing for smartfusion2.clkint.syn_black_box
    @N:CD630 : osc_comps.vhd(19) | Synthesizing work.rcosc_25_50mhz.def_arch.
    Post processing for work.rcosc_25_50mhz.def_arch
    @N:CD630 : osc_comps.vhd(79) | Synthesizing work.rcosc_25_50mhz_fab.def_arch.
    Post processing for work.rcosc_25_50mhz_fab.def_arch
    Post processing for work.mc_system_sb_fabosc_0_osc.def_arch
    @W:CL240 : MC_System_sb_FABOSC_0_OSC.vhd(16) | Signal XTLOSC_O2F is floating; a simulation mismatch is possible.
    @W:CL240 : MC_System_sb_FABOSC_0_OSC.vhd(15) | Signal XTLOSC_CCC is floating; a simulation mismatch is possible.
    @W:CL240 : MC_System_sb_FABOSC_0_OSC.vhd(14) | Signal RCOSC_1MHZ_O2F is floating; a simulation mismatch is possible.
    @W:CL240 : MC_System_sb_FABOSC_0_OSC.vhd(13) | Signal RCOSC_1MHZ_CCC is floating; a simulation mismatch is possible.
    @N:CD630 : coreresetp.vhd(27) | Synthesizing work.coreresetp.rtl.
    @W:CD434 : coreresetp.vhd(477) | Signal soft_ext_reset_out in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(478) | Signal soft_reset_f2m in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(479) | Signal soft_m3_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(480) | Signal soft_mddr_ddr_axi_s_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(481) | Signal soft_fddr_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(482) | Signal soft_sdif0_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(483) | Signal soft_sdif0_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(484) | Signal soft_sdif1_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(485) | Signal soft_sdif1_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(486) | Signal soft_sdif2_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(487) | Signal soft_sdif2_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(488) | Signal soft_sdif3_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(489) | Signal soft_sdif3_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(490) | Signal soft_sdif0_0_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD434 : coreresetp.vhd(491) | Signal soft_sdif0_1_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    Post processing for work.coreresetp.rtl
    @W:CL169 : coreresetp.vhd(1519) | Pruning unused register count_ddr_2(13 downto 0). Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1495) | Pruning unused register count_sdif3_1(12 downto 0). Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1471) | Pruning unused register count_sdif2_1(12 downto 0). Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1447) | Pruning unused register count_sdif1_1(12 downto 0). Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1423) | Pruning unused register count_sdif0_2(12 downto 0). Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_ddr_enable_rcosc_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_ddr_enable_q1_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_sdif3_enable_rcosc_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_sdif2_enable_rcosc_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_sdif1_enable_rcosc_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_sdif0_enable_rcosc_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_sdif3_enable_q1_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_sdif2_enable_q1_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_sdif1_enable_q1_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1395) | Pruning unused register count_sdif0_enable_q1_2. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1311) | Pruning unused register count_sdif3_enable_3. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1252) | Pruning unused register count_sdif2_enable_3. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1193) | Pruning unused register count_sdif1_enable_3. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1134) | Pruning unused register count_sdif0_enable_3. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1059) | Pruning unused register count_ddr_enable_3. Make sure that there are no unused intermediate registers.
    @W:CL177 : coreresetp.vhd(1331) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.vhd(936) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL190 : coreresetp.vhd(1376) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL169 : coreresetp.vhd(1059) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1376) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(1376) | Pruning unused register sm2_state(2 downto 0). Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(792) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.vhd(792) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
    @N:CD630 : coreapb3.vhd(34) | Synthesizing coreapb3_lib.coreapb3.coreapb3_arch.
    @N:CD604 : coreapb3.vhd(665) | OTHERS clause is not synthesized.
    @W:CD434 : coreapb3.vhd(1453) | Signal infill in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    @W:CD638 : coreapb3.vhd(616) | Signal ia_prdata is undriven. Either assign the signal a value or remove the signal declaration.
    @N:CD630 : coreapb3_muxptob3.vhd(33) | Synthesizing coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch.
    Post processing for coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch
    Post processing for coreapb3_lib.coreapb3.coreapb3_arch
    @N:CD630 : MC_System_sb_CCC_0_FCCC.vhd(8) | Synthesizing work.mc_system_sb_ccc_0_fccc.def_arch.
    @N:CD630 : smartfusion2.vhd(794) | Synthesizing smartfusion2.ccc.syn_black_box.
    Post processing for smartfusion2.ccc.syn_black_box
    @N:CD630 : smartfusion2.vhd(576) | Synthesizing smartfusion2.gnd.syn_black_box.
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(582) | Synthesizing smartfusion2.vcc.syn_black_box.
    Post processing for smartfusion2.vcc.syn_black_box
    Post processing for work.mc_system_sb_ccc_0_fccc.def_arch
    Post processing for work.mc_system_sb.rtl
    Post processing for work.mc_system.rtl
    @N:CD630 : Bldc_Axis.vhd(19) | Synthesizing work.bldc_axis.rtl.
    Post processing for work.svm.svm
    Post processing for work.accumulator_rl.accumulator_rl
    Post processing for work.rate_limiter.rate_limiter
    Post processing for work.accumulator_olmng.accumulator_olmng
    Post processing for work.mas_olmng.mas_olmng
    Post processing for work.olmng.olmng
    Post processing for work.accumulator_be.accumulator_be
    Post processing for work.filter_be.filter_be
    Post processing for work.mas_pll.mas_pll
    Post processing for work.pll_theta_be.pll_theta_be
    Post processing for work.mas_pi_be.mas_pi_be
    Post processing for work.pi_controller_be.pi_controller_be
    Post processing for work.cordic_rot_be.cordic_rot_be
    Post processing for work.mas_bm_be.mas_bm_be
    Post processing for work.bldc_model.bldc_model
    Post processing for work.bldc_estimator.bldc_estimator
    @N:CD630 : apb3_if.vhd(33) | Synthesizing work.apb3_if.apb3_if.
    Post processing for work.apb3_if.apb3_if
    Post processing for work.bldc_axis.rtl
    Post processing for work.mc_system_top.rtl
    @W:CL246 : apb3_if.vhd(63) | Input port bits 31 to 12 of paddr_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
    @W:CL246 : apb3_if.vhd(65) | Input port bits 31 to 18 of pwdata_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
    Extracted state machine for register s_state
    State machine has 7 reachable states with original encodings of:
       00000001
       00000100
       00001000
       00010000
       00100000
       01000000
       10000000
    Extracted state machine for register s_state
    State machine has 5 reachable states with original encodings of:
       00001
       00010
       00100
       01000
       10000
    Extracted state machine for register s_state
    State machine has 3 reachable states with original encodings of:
       00
       10
       11
    Extracted state machine for register s_ramp_present_state
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    Extracted state machine for register s_state
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    @N:CL159 : coreapb3.vhd(75) | Input IADDR is unused.
    @N:CL159 : coreapb3.vhd(76) | Input PRESETN is unused.
    @N:CL159 : coreapb3.vhd(77) | Input PCLK is unused.
    @N:CL159 : coreapb3.vhd(109) | Input PRDATAS2 is unused.
    @N:CL159 : coreapb3.vhd(110) | Input PRDATAS3 is unused.
    @N:CL159 : coreapb3.vhd(111) | Input PRDATAS4 is unused.
    @N:CL159 : coreapb3.vhd(112) | Input PRDATAS5 is unused.
    @N:CL159 : coreapb3.vhd(113) | Input PRDATAS6 is unused.
    @N:CL159 : coreapb3.vhd(114) | Input PRDATAS7 is unused.
    @N:CL159 : coreapb3.vhd(115) | Input PRDATAS8 is unused.
    @N:CL159 : coreapb3.vhd(116) | Input PRDATAS9 is unused.
    @N:CL159 : coreapb3.vhd(117) | Input PRDATAS10 is unused.
    @N:CL159 : coreapb3.vhd(118) | Input PRDATAS11 is unused.
    @N:CL159 : coreapb3.vhd(119) | Input PRDATAS12 is unused.
    @N:CL159 : coreapb3.vhd(120) | Input PRDATAS13 is unused.
    @N:CL159 : coreapb3.vhd(121) | Input PRDATAS14 is unused.
    @N:CL159 : coreapb3.vhd(122) | Input PRDATAS15 is unused.
    @N:CL159 : coreapb3.vhd(126) | Input PREADYS2 is unused.
    @N:CL159 : coreapb3.vhd(127) | Input PREADYS3 is unused.
    @N:CL159 : coreapb3.vhd(128) | Input PREADYS4 is unused.
    @N:CL159 : coreapb3.vhd(129) | Input PREADYS5 is unused.
    @N:CL159 : coreapb3.vhd(130) | Input PREADYS6 is unused.
    @N:CL159 : coreapb3.vhd(131) | Input PREADYS7 is unused.
    @N:CL159 : coreapb3.vhd(132) | Input PREADYS8 is unused.
    @N:CL159 : coreapb3.vhd(133) | Input PREADYS9 is unused.
    @N:CL159 : coreapb3.vhd(134) | Input PREADYS10 is unused.
    @N:CL159 : coreapb3.vhd(135) | Input PREADYS11 is unused.
    @N:CL159 : coreapb3.vhd(136) | Input PREADYS12 is unused.
    @N:CL159 : coreapb3.vhd(137) | Input PREADYS13 is unused.
    @N:CL159 : coreapb3.vhd(138) | Input PREADYS14 is unused.
    @N:CL159 : coreapb3.vhd(139) | Input PREADYS15 is unused.
    @N:CL159 : coreapb3.vhd(143) | Input PSLVERRS2 is unused.
    @N:CL159 : coreapb3.vhd(144) | Input PSLVERRS3 is unused.
    @N:CL159 : coreapb3.vhd(145) | Input PSLVERRS4 is unused.
    @N:CL159 : coreapb3.vhd(146) | Input PSLVERRS5 is unused.
    @N:CL159 : coreapb3.vhd(147) | Input PSLVERRS6 is unused.
    @N:CL159 : coreapb3.vhd(148) | Input PSLVERRS7 is unused.
    @N:CL159 : coreapb3.vhd(149) | Input PSLVERRS8 is unused.
    @N:CL159 : coreapb3.vhd(150) | Input PSLVERRS9 is unused.
    @N:CL159 : coreapb3.vhd(151) | Input PSLVERRS10 is unused.
    @N:CL159 : coreapb3.vhd(152) | Input PSLVERRS11 is unused.
    @N:CL159 : coreapb3.vhd(153) | Input PSLVERRS12 is unused.
    @N:CL159 : coreapb3.vhd(154) | Input PSLVERRS13 is unused.
    @N:CL159 : coreapb3.vhd(155) | Input PSLVERRS14 is unused.
    @N:CL159 : coreapb3.vhd(156) | Input PSLVERRS15 is unused.
    @W:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.vhd(936) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
    @N:CL201 : coreresetp.vhd(1311) | Trying to extract state machine for register sdif3_state.
    Extracted state machine for register sdif3_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1252) | Trying to extract state machine for register sdif2_state.
    Extracted state machine for register sdif2_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1193) | Trying to extract state machine for register sdif1_state.
    Extracted state machine for register sdif1_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1134) | Trying to extract state machine for register sdif0_state.
    Extracted state machine for register sdif0_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1059) | Trying to extract state machine for register sm0_state.
    Extracted state machine for register sm0_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @N:CL159 : coreresetp.vhd(96) | Input CLK_LTSSM is unused.
    @N:CL159 : coreresetp.vhd(123) | Input FPLL_LOCK is unused.
    @N:CL159 : coreresetp.vhd(126) | Input SDIF0_SPLL_LOCK is unused.
    @N:CL159 : coreresetp.vhd(135) | Input SDIF1_SPLL_LOCK is unused.
    @N:CL159 : coreresetp.vhd(139) | Input SDIF2_SPLL_LOCK is unused.
    @N:CL159 : coreresetp.vhd(143) | Input SDIF3_SPLL_LOCK is unused.
    @N:CL159 : coreresetp.vhd(157) | Input SDIF0_PSEL is unused.
    @N:CL159 : coreresetp.vhd(158) | Input SDIF0_PWRITE is unused.
    @N:CL159 : coreresetp.vhd(159) | Input SDIF0_PRDATA is unused.
    @N:CL159 : coreresetp.vhd(160) | Input SDIF1_PSEL is unused.
    @N:CL159 : coreresetp.vhd(161) | Input SDIF1_PWRITE is unused.
    @N:CL159 : coreresetp.vhd(162) | Input SDIF1_PRDATA is unused.
    @N:CL159 : coreresetp.vhd(163) | Input SDIF2_PSEL is unused.
    @N:CL159 : coreresetp.vhd(164) | Input SDIF2_PWRITE is unused.
    @N:CL159 : coreresetp.vhd(165) | Input SDIF2_PRDATA is unused.
    @N:CL159 : coreresetp.vhd(166) | Input SDIF3_PSEL is unused.
    @N:CL159 : coreresetp.vhd(167) | Input SDIF3_PWRITE is unused.
    @N:CL159 : coreresetp.vhd(168) | Input SDIF3_PRDATA is unused.
    @N:CL159 : coreresetp.vhd(174) | Input SOFT_EXT_RESET_OUT is unused.
    @N:CL159 : coreresetp.vhd(175) | Input SOFT_RESET_F2M is unused.
    @N:CL159 : coreresetp.vhd(176) | Input SOFT_M3_RESET is unused.
    @N:CL159 : coreresetp.vhd(177) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused.
    @N:CL159 : coreresetp.vhd(178) | Input SOFT_FDDR_CORE_RESET is unused.
    @N:CL159 : coreresetp.vhd(179) | Input SOFT_SDIF0_PHY_RESET is unused.
    @N:CL159 : coreresetp.vhd(180) | Input SOFT_SDIF0_CORE_RESET is unused.
    @N:CL159 : coreresetp.vhd(181) | Input SOFT_SDIF1_PHY_RESET is unused.
    @N:CL159 : coreresetp.vhd(182) | Input SOFT_SDIF1_CORE_RESET is unused.
    @N:CL159 : coreresetp.vhd(183) | Input SOFT_SDIF2_PHY_RESET is unused.
    @N:CL159 : coreresetp.vhd(184) | Input SOFT_SDIF2_CORE_RESET is unused.
    @N:CL159 : coreresetp.vhd(185) | Input SOFT_SDIF3_PHY_RESET is unused.
    @N:CL159 : coreresetp.vhd(186) | Input SOFT_SDIF3_CORE_RESET is unused.
    @N:CL159 : coreresetp.vhd(190) | Input SOFT_SDIF0_0_CORE_RESET is unused.
    @N:CL159 : coreresetp.vhd(191) | Input SOFT_SDIF0_1_CORE_RESET is unused.
    @N:CL159 : MC_System_sb_FABOSC_0_OSC.vhd(10) | Input XTL is unused.
    @N:CL201 : adc_interface_795x.vhd(197) | Trying to extract state machine for register state.
    Extracted state machine for register state
    State machine has 6 reachable states with original encodings of:
       000001
       000010
       000100
       001000
       010000
       100000
    @W:CL279 : adc_interface_795x.vhd(197) | Pruning register bits 12 to 11 of s_spi_mosi(12 downto 6). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
    Extracted state machine for register s_state
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    @W:CL246 : apb3_if_st.vhd(60) | Input port bits 31 to 12 of paddr_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
    @W:CL246 : apb3_if_st.vhd(62) | Input port bits 31 to 24 of pwdata_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
    Extracted state machine for register s_state
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    Extracted state machine for register s_state
    State machine has 5 reachable states with original encodings of:
       00001
       00010
       00100
       01000
       10000
    Extracted state machine for register s_state
    State machine has 9 reachable states with original encodings of:
       000000001
       000000010
       000000100
       000001000
       000010000
       000100000
       001000000
       010000000
       100000000
    Extracted state machine for register s_state
    State machine has 5 reachable states with original encodings of:
       00001
       00010
       00100
       01000
       10000

    At c_vhdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 118MB peak: 125MB)

    Process took 0h:00m:04s realtime, 0h:00m:04s cputime

    Process completed successfully.
    # Fri Dec 01 17:24:10 2017

    ###########################################################]
    Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 82MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Dec 01 17:24:11 2017

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:05s realtime, 0h:00m:05s cputime

    Process completed successfully.
    # Fri Dec 01 17:24:11 2017

    ###########################################################]
    Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Dec 01 17:24:13 2017

    ###########################################################]
    Pre-mapping Report

    # Fri Dec 01 17:24:13 2017

    Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
    Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
    Product Version L-2016.09M-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @A:MF827 :  | No constraint file specified.
    Linked File: MC_System_top_1_scck.rpt
    Printing clock  summary report in "F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLSLST10\LiberoProject\SK2ABLSLST10\SK2ABLSLST10_5_1\synthesis\MC_System_top_1_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 136MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 136MB)

    @W:BN132 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:MO129 : coreresetp.vhd(703) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(719) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(735) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(751) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(781) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(703) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(719) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(735) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(751) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(781) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(703) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(719) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(735) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(751) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.vhd(1331) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch4_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch5_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch6_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch7_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch8_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch9_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch10_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch11_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch12_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch13_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch14_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch15_o[11:0] (in view: work.adc_interface_795x_0(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if.vhd(626) | Removing sequential instance adc_control_reg_val_o[5:0] (in view: work.apb3_if(apb3_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if.vhd(626) | Removing sequential instance adc_channel_ch0_o[15:0] (in view: work.apb3_if(apb3_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if.vhd(626) | Removing sequential instance adc_channel_ch1_o[15:0] (in view: work.apb3_if(apb3_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if.vhd(626) | Removing sequential instance adc_channel_ch2_o[15:0] (in view: work.apb3_if(apb3_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if.vhd(626) | Removing sequential instance adc_channel_ch3_o[15:0] (in view: work.apb3_if(apb3_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN115 : mc_system_sb.vhd(530) | Removing instance CORERESETP_0 (in view: work.MC_System_sb(rtl)) of type view:work.CoreResetP(rtl) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch4_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch5_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch6_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch7_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch8_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch9_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch10_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch11_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch12_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch13_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch14_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : adc_interface_795x.vhd(303) | Removing sequential instance result_ch15_o[11:0] (in view: work.adc_interface_795x_1(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if_st.vhd(435) | Removing sequential instance adc_control_reg_val_o[5:0] (in view: work.apb3_if_st(apb3_if_st)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if_st.vhd(435) | Removing sequential instance adc_channel_ch0_o[15:0] (in view: work.apb3_if_st(apb3_if_st)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if_st.vhd(435) | Removing sequential instance adc_channel_ch1_o[15:0] (in view: work.apb3_if_st(apb3_if_st)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if_st.vhd(435) | Removing sequential instance adc_channel_ch2_o[15:0] (in view: work.apb3_if_st(apb3_if_st)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : apb3_if_st.vhd(435) | Removing sequential instance adc_channel_ch3_o[15:0] (in view: work.apb3_if_st(apb3_if_st)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance INIT_DONE_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance sdif0_state[0:3] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance sdif1_state[0:3] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance sdif2_state[0:3] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance sdif3_state[0:3] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance sm0_state[0:6] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(922) | Removing sequential instance CONFIG2_DONE_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(936) | Removing sequential instance sdif3_spll_lock_q2 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(908) | Removing sequential instance CONFIG1_DONE_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif3_core_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif2_core_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif1_core_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(922) | Removing sequential instance CONFIG2_DONE_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(936) | Removing sequential instance sdif3_spll_lock_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(908) | Removing sequential instance CONFIG1_DONE_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif0_core_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance ddr_settled_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif3_core_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif2_core_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif1_core_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif0_core_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance ddr_settled_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1495) | Removing sequential instance release_sdif3_core (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1471) | Removing sequential instance release_sdif2_core (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1447) | Removing sequential instance release_sdif1_core (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1423) | Removing sequential instance release_sdif0_core (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(1519) | Removing sequential instance ddr_settled (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(770) | Removing sequential instance sm0_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(894) | Removing sequential instance sdif3_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(883) | Removing sequential instance sdif2_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(872) | Removing sequential instance sdif1_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(861) | Removing sequential instance sdif0_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(770) | Removing sequential instance sm0_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(850) | Removing sequential instance sm0_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(894) | Removing sequential instance sdif3_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(883) | Removing sequential instance sdif2_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(872) | Removing sequential instance sdif1_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(861) | Removing sequential instance sdif0_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(850) | Removing sequential instance sm0_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(608) | Removing sequential instance MSS_HPMS_READY_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(593) | Removing sequential instance mss_ready_select (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(593) | Removing sequential instance mss_ready_state (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(577) | Removing sequential instance FIC_2_APB_M_PRESET_N_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(565) | Removing sequential instance RESET_N_M2F_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(577) | Removing sequential instance FIC_2_APB_M_PRESET_N_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(565) | Removing sequential instance RESET_N_M2F_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(553) | Removing sequential instance POWER_ON_RESET_N_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.vhd(553) | Removing sequential instance POWER_ON_RESET_N_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    syn_allowed_resources : blockrams=21,dsps=22  set on top level netlist MC_System_top

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 161MB peak: 163MB)

    Clock Summary
    *****************

    Start                                              Requested     Requested     Clock        Clock                   Clock
    Clock                                              Frequency     Period        Type         Group                   Load
    -------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_1     3491
    MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     1727
    System                                             100.0 MHz     10.000        system       system_clkgroup         0
    =========================================================================================================================

    @W:MT530 : adc_interface_795x.vhd(632) | Found inferred clock MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock which controls 1727 sequential elements including Stepper_Axis_0.adc_interface_795x_0.spi_engine_inst.s_sck_count[5:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : adc_interface_795x.vhd(632) | Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 3491 sequential elements including Bldc_Axis_0.adc_interface_795x_0.spi_engine_inst.s_sck_count[5:0]. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLSLST10\LiberoProject\SK2ABLSLST10\SK2ABLSLST10_5_1\synthesis\MC_System_top_1.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 163MB)

    Encoding state machine state[0:5] (in view: work.adc_interface_795x_0(adc_interface))
    original code -> new code
       000001 -> 000001
       000010 -> 000010
       000100 -> 000100
       001000 -> 001000
       010000 -> 010000
       100000 -> 100000
    Encoding state machine s_state[0:3] (in view: adc_scaling_lib.ADC_SCALING_0(adc_scaling))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine s_state[0:6] (in view: work.bldc_model(bldc_model))
    original code -> new code
       00000001 -> 0000001
       00000100 -> 0000010
       00001000 -> 0000100
       00010000 -> 0001000
       00100000 -> 0010000
       01000000 -> 0100000
       10000000 -> 1000000
    Encoding state machine s_state[0:4] (in view: work.pi_controller_be(pi_controller_be))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_state[0:2] (in view: work.cordic_scale_0(cordic_scale))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine s_state[0:2] (in view: work.OLMNG(olmng))
    original code -> new code
       00 -> 00
       10 -> 01
       11 -> 10
    Encoding state machine s_state[0:4] (in view: work.PWM_SCALING_0(pwm_scaling))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_ramp_present_state[0:2] (in view: work.RATE_LIMITER(rate_limiter))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine s_state[0:8] (in view: work.SEQ_CONTROLLER_0(seq_controller))
    original code -> new code
       000000001 -> 000000001
       000000010 -> 000000010
       000000100 -> 000000100
       000001000 -> 000001000
       000010000 -> 000010000
       000100000 -> 000100000
       001000000 -> 001000000
       010000000 -> 010000000
       100000000 -> 100000000
    Encoding state machine s_state[0:4] (in view: work.pi_controller_spi_0(pi_controller_spi))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_state[0:2] (in view: work.SVM(svm))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine state[0:5] (in view: work.adc_interface_795x_1(adc_interface))
    original code -> new code
       000001 -> 000001
       000010 -> 000010
       000100 -> 000100
       001000 -> 001000
       010000 -> 010000
       100000 -> 100000
    Encoding state machine s_state[0:3] (in view: adc_scaling_lib.ADC_SCALING_1(adc_scaling))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine s_state[0:2] (in view: work.cordic_scale_1(cordic_scale))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine s_state[0:4] (in view: work.PWM_SCALING_1(pwm_scaling))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_state[0:8] (in view: work.SEQ_CONTROLLER_1(seq_controller))
    original code -> new code
       000000001 -> 000000001
       000000010 -> 000000010
       000000100 -> 000000100
       000001000 -> 000001000
       000010000 -> 000010000
       000100000 -> 000100000
       001000000 -> 001000000
       010000000 -> 010000000
       100000000 -> 100000000
    Encoding state machine s_state[0:4] (in view: work.pi_controller_spi_1(pi_controller_spi))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    @N:BN362 : apb3_if.vhd(626) | Removing sequential instance pwm_gain_val_o[0] (in view: work.apb3_if(apb3_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 176MB peak: 179MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 179MB)

    Process took 0h:00m:03s realtime, 0h:00m:02s cputime
    # Fri Dec 01 17:24:16 2017

    ###########################################################]
    Map & Optimize Report

    # Fri Dec 01 17:24:16 2017

    Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
    Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
    Product Version L-2016.09M-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)

    @W:BN114 : mc_system_sb.vhd(674) | Removing instance SYSRESET_POR (in view: work.MC_System_sb(rtl)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances.

    Available hyper_sources - for debug and ip models
    	None Found

    @W:FA239 : coreapb3.vhd(648) | ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
    @W:FA239 : coreapb3.vhd(648) | ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
    @N:MO106 : coreapb3.vhd(648) | Found ROM .delname. (in view: work.MC_System_sb(rtl)) with 16 words by 2 bits.

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 157MB)

    @N:BN362 : apb3_if.vhd(626) | Removing sequential instance apb3_if_0.pwm_gain_val_o[0] (in view: work.Bldc_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    Encoding state machine state[0:5] (in view: work.adc_interface_795x_0(adc_interface))
    original code -> new code
       000001 -> 000001
       000010 -> 000010
       000100 -> 000100
       001000 -> 001000
       010000 -> 010000
       100000 -> 100000
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[15] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[14] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[13] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[12] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[11] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[10] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[9] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[8] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[7] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[6] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[5] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[4] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[3] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[2] (in view view:work.adc_interface_795x_0(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:BN132 : adc_interface_795x.vhd(368) | Removing instance Bldc_Axis_0.adc_interface_795x_0.s_channel_sel[1] because it is equivalent to instance Bldc_Axis_0.adc_interface_795x_0.s_channel_sel[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[0] (in view view:work.spi_engine_0(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[1] (in view view:work.spi_engine_0(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[2] (in view view:work.spi_engine_0(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[3] (in view view:work.spi_engine_0(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[4] (in view view:work.spi_engine_0(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[5] (in view view:work.spi_engine_0(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    Encoding state machine s_state[0:3] (in view: adc_scaling_lib.ADC_SCALING_0(adc_scaling))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine s_state[0:6] (in view: work.bldc_model(bldc_model))
    original code -> new code
       00000001 -> 0000001
       00000100 -> 0000010
       00001000 -> 0000100
       00010000 -> 0001000
       00100000 -> 0010000
       01000000 -> 0100000
       10000000 -> 1000000
    Encoding state machine s_state[0:4] (in view: work.pi_controller_be(pi_controller_be))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_state[0:2] (in view: work.cordic_scale_0(cordic_scale))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine s_state[0:2] (in view: work.OLMNG(olmng))
    original code -> new code
       00 -> 00
       10 -> 01
       11 -> 10
    Encoding state machine s_state[0:4] (in view: work.PWM_SCALING_0(pwm_scaling))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_ramp_present_state[0:2] (in view: work.RATE_LIMITER(rate_limiter))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine s_state[0:8] (in view: work.SEQ_CONTROLLER_0(seq_controller))
    original code -> new code
       000000001 -> 000000001
       000000010 -> 000000010
       000000100 -> 000000100
       000001000 -> 000001000
       000010000 -> 000010000
       000100000 -> 000100000
       001000000 -> 001000000
       010000000 -> 010000000
       100000000 -> 100000000
    Encoding state machine s_state[0:4] (in view: work.pi_controller_spi_0(pi_controller_spi))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_state[0:2] (in view: work.SVM(svm))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine state[0:5] (in view: work.adc_interface_795x_1(adc_interface))
    original code -> new code
       000001 -> 000001
       000010 -> 000010
       000100 -> 000100
       001000 -> 001000
       010000 -> 010000
       100000 -> 100000
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[15] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[14] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[13] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[12] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[11] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[10] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[9] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[8] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[7] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[6] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[5] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[4] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[3] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(368) | Register bit s_channel_sel[1] (in view view:work.adc_interface_795x_1(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:BN132 : adc_interface_795x.vhd(368) | Removing instance Stepper_Axis_0.adc_interface_795x_0.s_channel_sel[2] because it is equivalent to instance Stepper_Axis_0.adc_interface_795x_0.s_channel_sel[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[0] (in view view:work.spi_engine_1(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[1] (in view view:work.spi_engine_1(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[2] (in view view:work.spi_engine_1(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[3] (in view view:work.spi_engine_1(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[4] (in view view:work.spi_engine_1(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    @W:MO160 : adc_interface_795x.vhd(584) | Register bit s_sdo_reg[5] (in view view:work.spi_engine_1(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
    Encoding state machine s_state[0:3] (in view: adc_scaling_lib.ADC_SCALING_1(adc_scaling))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine s_state[0:2] (in view: work.cordic_scale_1(cordic_scale))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine s_state[0:4] (in view: work.PWM_SCALING_1(pwm_scaling))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_state[0:8] (in view: work.SEQ_CONTROLLER_1(seq_controller))
    original code -> new code
       000000001 -> 000000001
       000000010 -> 000000010
       000000100 -> 000000100
       000001000 -> 000001000
       000010000 -> 000010000
       000100000 -> 000100000
       001000000 -> 001000000
       010000000 -> 010000000
       100000000 -> 100000000
    Encoding state machine s_state[0:4] (in view: work.pi_controller_spi_1(pi_controller_spi))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000

    Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 190MB)

    Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB)

    @N:BN362 : apb3_if_st.vhd(435) | Removing sequential instance Stepper_Axis_0.apb3_if_st_0.seq_cntl_config_o[0] (in view: work.MC_System_top(rtl)) because it does not drive other instances.
    @A:BN291 : apb3_if_st.vhd(435) | Boundary register Stepper_Axis_0.apb3_if_st_0.seq_cntl_config_o[0] (in view: work.MC_System_top(rtl)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @N:BN362 : apb3_if_st.vhd(435) | Removing sequential instance Stepper_Axis_0.apb3_if_st_0.seq_cntl_config_o[3] (in view: work.MC_System_top(rtl)) because it does not drive other instances.
    @A:BN291 : apb3_if_st.vhd(435) | Boundary register Stepper_Axis_0.apb3_if_st_0.seq_cntl_config_o[3] (in view: work.MC_System_top(rtl)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 191MB peak: 197MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 190MB peak: 214MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 194MB peak: 214MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 194MB peak: 214MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 191MB peak: 214MB)

    Finished preparing to map (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 195MB peak: 214MB)

    Finished technology mapping (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 231MB peak: 277MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:18s		    -3.72ns		7768 /      4577
       2		0h:00m:18s		    -3.72ns		6825 /      4577
       3		0h:00m:18s		    -3.13ns		6825 /      4577
       4		0h:00m:19s		    -3.04ns		6824 /      4577
    Timing driven replication report
    Added 1 Registers via timing driven replication
    Added 1 LUTs via timing driven replication

       5		0h:00m:20s		    -3.04ns		6825 /      4578
       6		0h:00m:20s		    -2.55ns		6826 /      4578

       7		0h:00m:21s		    -2.55ns		6826 /      4578
    @N:FP130 :  | Promoting Net MC_System_0_FIC_0_LOCK on CLKINT  I_171

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:22s; Memory used current: 243MB peak: 277MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:23s; Memory used current: 245MB peak: 277MB)

    @S |Clock Optimization Summary

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    2 gated/generated clock tree(s) driving 4603 clock pin(s) of sequential element(s)
    0 instances converted, 4603 sequential instances remain driven by gated/generated clocks

    =================================================================================================== Gated/Generated Clocks ===================================================================================================
    Clock Tree ID     Driving Element                               Drive Element Type     Fanout     Sample Instance                                                  Explanation
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        MC_System_0.MC_System_sb_0.CCC_0.CCC_INST     CCC                    3094       MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     No gated clock conversion method for cell cell:work.MSS_010
    ClockId0002        MC_System_0.MC_System_sb_0.CCC_0.CCC_INST     CCC                    1509       Stepper_Axis_0.apb3_if_st_0.start_motor_o                        No gated clock conversion method for cell cell:ACG4.SLE
    ==============================================================================================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Start Writing Netlists (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:24s; Memory used current: 184MB peak: 277MB)

    Writing Analyst data base F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLSLST10\LiberoProject\SK2ABLSLST10\SK2ABLSLST10_5_1\synthesis\synwork\MC_System_top_1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:27s; Memory used current: 229MB peak: 277MB)

    Writing Verilog Simulation files
    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 225MB peak: 277MB)

    Start final timing analysis (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:29s; Memory used current: 226MB peak: 277MB)

    @W:MT246 : mc_system_sb_ccc_0_fccc.vhd(110) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.CCC_0.GL0_net"
    @W:MT420 :  | Found inferred clock MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.CCC_0.GL1_net"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Fri Dec 01 17:24:46 2017
    #

    Top view:               MC_System_top
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -0.647

                                                       Requested     Estimated      Requested     Estimated                Clock        Clock
    Starting Clock                                     Frequency     Frequency      Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     93.9 MHz       10.000        10.647        -0.647     inferred     Inferred_clkgroup_1
    MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     100.0 MHz     139.4 MHz      10.000        7.174         2.826      inferred     Inferred_clkgroup_0
    System                                             100.0 MHz     1029.4 MHz     10.000        0.971         9.029      system       system_clkgroup
    =======================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                        Ending                                          |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                          System                                          |  10.000      9.029   |  No paths    -      |  No paths    -      |  No paths    -
    System                                          MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      1.547   |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock  |  10.000      2.826   |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      -0.647  |  No paths    -      |  No paths    -      |  No paths    -
    =======================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                     Starting                                                                                                                 Arrival
    Instance                                                         Reference                                          Type        Pin                Net                                    Time        Slack
                                                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[10]     MC_System_0_AMBA_SLAVE_0_PADDR[10]     3.357       -0.647
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[8]      MC_System_0_AMBA_SLAVE_0_PADDR[8]      3.354       -0.588
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[6]      MC_System_0_AMBA_SLAVE_0_PADDR[6]      3.185       -0.414
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[11]     MC_System_0_AMBA_SLAVE_0_PADDR[11]     3.057       -0.342
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[9]      MC_System_0_AMBA_SLAVE_0_PADDR[9]      3.175       -0.330
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[1]      MC_System_0_AMBA_SLAVE_0_PADDR[1]      3.058       -0.285
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[4]      MC_System_0_AMBA_SLAVE_0_PADDR[4]      3.026       -0.273
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[0]      MC_System_0_AMBA_SLAVE_0_PADDR[0]      3.112       -0.230
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[3]      MC_System_0_AMBA_SLAVE_0_PADDR[3]      3.040       -0.215
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[7]      MC_System_0_AMBA_SLAVE_0_PADDR[7]      3.055       -0.200
    ============================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                     Starting                                                                                                                                  Required
    Instance                                                         Reference                                          Type        Pin                 Net                                                    Time         Slack
                                                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[5]      PRDATA_N_8_i                                           9.672        -0.647
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        -0.588
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[10]     PRDATA_N_7_i                                           9.723        -0.435
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[3]      PRDATA_N_7_1_i                                         9.483        -0.414
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[14]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[14]     9.688        -0.401
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[11]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]     9.650        -0.401
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[6]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]      9.651        -0.400
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[12]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[12]     9.698        -0.391
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[7]      PRDATA_N_7_0_i                                         9.763        -0.325
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.604        -0.178
    ==============================================================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.328
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.672

        - Propagation time:                      10.319
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.647

        Number of logic level(s):                7
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[5]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                           Pin                Pin               Arrival     No. of
    Name                                                                         Type        Name               Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                 MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -
    MC_System_0_AMBA_SLAVE_0_PADDR[10]                                           Net         -                  -       0.994     -           21
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o192_1                  CFG4        D                  In      -         4.351       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o192_1                  CFG4        Y                  Out     0.276     4.627       -
    idq_pi_kp_o_0_sqmuxa_1                                                       Net         -                  -       0.648     -           5
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o190                    CFG4        C                  In      -         5.274       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o190                    CFG4        Y                  Out     0.177     5.451       -
    prdata_o190                                                                  Net         -                  -       0.761     -           12
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_1            CFG4        D                  In      -         6.212       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_1            CFG4        Y                  Out     0.284     6.496       -
    PRDATA_m6_2_1                                                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_7            CFG4        B                  In      -         6.979       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_7            CFG4        Y                  Out     0.143     7.122       -
    PRDATA_m6_2_7                                                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_10           CFG4        D                  In      -         7.605       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_10           CFG4        Y                  Out     0.250     7.855       -
    PRDATA_m6_2_10                                                               Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2              CFG4        D                  In      -         8.338       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2              CFG4        Y                  Out     0.250     8.589       -
    PRDATA_N_12_mux                                                              Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_RNI8S2G1     CFG4        D                  In      -         9.072       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_RNI8S2G1     CFG4        Y                  Out     0.276     9.348       -
    PRDATA_N_8_i                                                                 Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                 MSS_010     F_HM0_RDATA[5]     In      -         10.319      -
    ====================================================================================================================================================
    Total path delay (propagation time + setup) of 10.647 is 5.340(50.2%) logic and 5.307(49.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      10.000
        - Setup time:                            0.316
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.684

        - Propagation time:                      10.272
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.588

        Number of logic level(s):                7
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[8]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[1]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                Pin                Pin               Arrival     No. of
    Name                                                              Type        Name               Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_ADDR[8]      Out     3.354     3.354       -
    MC_System_0_AMBA_SLAVE_0_PADDR[8]                                 Net         -                  -       1.005     -           96
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o182_1_1     CFG4        D                  In      -         4.359       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o182_1_1     CFG4        Y                  Out     0.284     4.643       -
    prdata_o182_1_1                                                   Net         -                  -       0.706     -           8
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o182         CFG4        D                  In      -         5.349       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o182         CFG4        Y                  Out     0.250     5.599       -
    prdata_o182                                                       Net         -                  -       0.722     -           9
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9_N_5L8                 CFG4        D                  In      -         6.321       -
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9_N_5L8                 CFG4        Y                  Out     0.276     6.597       -
    prdata_o_1_iv_9_N_5L8                                             Net         -                  -       0.483     -           1
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9[1]                    CFG4        C                  In      -         7.080       -
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9[1]                    CFG4        Y                  Out     0.196     7.276       -
    prdata_o_1_iv_9[1]                                                Net         -                  -       0.483     -           1
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12[1]                   CFG4        D                  In      -         7.759       -
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12[1]                   CFG4        Y                  Out     0.250     8.010       -
    prdata_o_1_iv_12[1]                                               Net         -                  -       0.483     -           1
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_3_RNIEA3I[1]            CFG4        C                  In      -         8.493       -
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_3_RNIEA3I[1]            CFG4        Y                  Out     0.182     8.675       -
    MC_System_0_AMBA_SLAVE_1_PRDATA[1]                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]     CFG4        B                  In      -         9.158       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]     CFG4        Y                  Out     0.143     9.301       -
    MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]                 Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_RDATA[1]     In      -         10.272      -
    =========================================================================================================================================
    Total path delay (propagation time + setup) of 10.588 is 5.251(49.6%) logic and 5.337(50.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      10.000
        - Setup time:                            0.328
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.672

        - Propagation time:                      10.225
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.553

        Number of logic level(s):                7
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[8]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[5]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                           Pin                Pin               Arrival     No. of
    Name                                                                         Type        Name               Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                 MSS_010     F_HM0_ADDR[8]      Out     3.354     3.354       -
    MC_System_0_AMBA_SLAVE_0_PADDR[8]                                            Net         -                  -       1.005     -           96
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o192_1                  CFG4        C                  In      -         4.359       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o192_1                  CFG4        Y                  Out     0.196     4.555       -
    idq_pi_kp_o_0_sqmuxa_1                                                       Net         -                  -       0.648     -           5
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o190                    CFG4        C                  In      -         5.203       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o190                    CFG4        Y                  Out     0.182     5.385       -
    prdata_o190                                                                  Net         -                  -       0.761     -           12
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_1            CFG4        D                  In      -         6.146       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_1            CFG4        Y                  Out     0.276     6.422       -
    PRDATA_m6_2_1                                                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_7            CFG4        B                  In      -         6.905       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_7            CFG4        Y                  Out     0.143     7.048       -
    PRDATA_m6_2_7                                                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_10           CFG4        D                  In      -         7.532       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_10           CFG4        Y                  Out     0.236     7.768       -
    PRDATA_m6_2_10                                                               Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2              CFG4        D                  In      -         8.251       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2              CFG4        Y                  Out     0.236     8.487       -
    PRDATA_N_12_mux                                                              Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_RNI8S2G1     CFG4        D                  In      -         8.970       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_RNI8S2G1     CFG4        Y                  Out     0.284     9.254       -
    PRDATA_N_8_i                                                                 Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                 MSS_010     F_HM0_RDATA[5]     In      -         10.225      -
    ====================================================================================================================================================
    Total path delay (propagation time + setup) of 10.553 is 5.235(49.6%) logic and 5.318(50.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      10.000
        - Setup time:                            0.328
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.672

        - Propagation time:                      10.159
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.487

        Number of logic level(s):                7
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[5]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                           Pin                Pin               Arrival     No. of
    Name                                                                         Type        Name               Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                 MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -
    MC_System_0_AMBA_SLAVE_0_PADDR[10]                                           Net         -                  -       0.994     -           21
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o191_1                  CFG4        D                  In      -         4.351       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o191_1                  CFG4        Y                  Out     0.276     4.627       -
    prdata_o191_1                                                                Net         -                  -       0.648     -           5
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o191                    CFG4        B                  In      -         5.274       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o191                    CFG4        Y                  Out     0.143     5.418       -
    prdata_o191                                                                  Net         -                  -       0.722     -           9
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_1            CFG4        C                  In      -         6.139       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_1            CFG4        Y                  Out     0.196     6.335       -
    PRDATA_m6_2_1                                                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_7            CFG4        B                  In      -         6.819       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_7            CFG4        Y                  Out     0.143     6.962       -
    PRDATA_m6_2_7                                                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_10           CFG4        D                  In      -         7.445       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_10           CFG4        Y                  Out     0.250     7.695       -
    PRDATA_m6_2_10                                                               Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2              CFG4        D                  In      -         8.178       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2              CFG4        Y                  Out     0.250     8.428       -
    PRDATA_N_12_mux                                                              Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_RNI8S2G1     CFG4        D                  In      -         8.912       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m6_2_RNI8S2G1     CFG4        Y                  Out     0.276     9.187       -
    PRDATA_N_8_i                                                                 Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                 MSS_010     F_HM0_RDATA[5]     In      -         10.159      -
    ====================================================================================================================================================
    Total path delay (propagation time + setup) of 10.487 is 5.219(49.8%) logic and 5.267(50.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      10.000
        - Setup time:                            0.316
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.684

        - Propagation time:                      10.146
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.462

        Number of logic level(s):                7
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[1]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                Pin                Pin               Arrival     No. of
    Name                                                              Type        Name               Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -
    MC_System_0_AMBA_SLAVE_0_PADDR[10]                                Net         -                  -       0.994     -           21
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o182_1_1     CFG4        C                  In      -         4.351       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o182_1_1     CFG4        Y                  Out     0.194     4.545       -
    prdata_o182_1_1                                                   Net         -                  -       0.706     -           8
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o182         CFG4        D                  In      -         5.251       -
    Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o182         CFG4        Y                  Out     0.236     5.487       -
    prdata_o182                                                       Net         -                  -       0.722     -           9
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9_N_5L8                 CFG4        D                  In      -         6.208       -
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9_N_5L8                 CFG4        Y                  Out     0.284     6.492       -
    prdata_o_1_iv_9_N_5L8                                             Net         -                  -       0.483     -           1
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9[1]                    CFG4        C                  In      -         6.976       -
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9[1]                    CFG4        Y                  Out     0.194     7.169       -
    prdata_o_1_iv_9[1]                                                Net         -                  -       0.483     -           1
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12[1]                   CFG4        D                  In      -         7.653       -
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12[1]                   CFG4        Y                  Out     0.236     7.889       -
    prdata_o_1_iv_12[1]                                               Net         -                  -       0.483     -           1
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_3_RNIEA3I[1]            CFG4        C                  In      -         8.372       -
    Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_3_RNIEA3I[1]            CFG4        Y                  Out     0.177     8.548       -
    MC_System_0_AMBA_SLAVE_1_PRDATA[1]                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]     CFG4        B                  In      -         9.032       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]     CFG4        Y                  Out     0.143     9.175       -
    MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]                 Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_RDATA[1]     In      -         10.146      -
    =========================================================================================================================================
    Total path delay (propagation time + setup) of 10.462 is 5.136(49.1%) logic and 5.326(50.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                                         Starting                                                                            Arrival
    Instance                                                                             Reference                                          Type     Pin     Net             Time        Slack
                                                                                         Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.s_pi_sel[0]                        MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_pi_sel[0]     0.094       2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.s_pi_sel[1]                        MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_pi_sel[1]     0.094       2.836
    Stepper_Axis_0.SEQ_CONTROLLER_0.s_state[2]                                           MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_state[2]      0.094       2.937
    Stepper_Axis_0.SEQ_CONTROLLER_0.s_state[6]                                           MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_state[6]      0.094       3.005
    Stepper_Axis_0.SEQ_CONTROLLER_0.s_state[3]                                           MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       N_417_li        0.094       3.148
    Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[0]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_index[0]      0.094       3.192
    Stepper_Axis_0.SEQ_CONTROLLER_0.s_state[4]                                           MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_state[4]      0.094       3.254
    Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[1]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_index[1]      0.094       3.310
    Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[3]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_index[3]      0.094       3.383
    Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[2]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_index[2]      0.094       3.450
    ==========================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                         Starting                                                                                Required
    Instance                                                             Reference                                          Type     Pin     Net                 Time         Slack
                                                                         Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[33]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[33]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[34]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[34]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[35]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[35]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[36]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[36]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[37]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[37]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[38]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[38]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[39]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[39]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[40]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[40]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[41]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[41]     9.778        2.826
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[42]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       acc_out_o_2[42]     9.778        2.826
    ===============================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.778

        - Propagation time:                      6.952
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 2.826

        Number of logic level(s):                38
        Starting point:                          Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.s_pi_sel[0] / Q
        Ending point:                            Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[33] / D
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK

    Instance / Net                                                                                      Pin      Pin               Arrival     No. of
    Name                                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.s_pi_sel[0]                              SLE      Q        Out     0.094     0.094       -
    s_pi_sel[0]                                                                                Net      -        -       1.585     -           87
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.en_o                                     CFG3     C        In      -         1.679       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.en_o                                     CFG3     Y        Out     0.182     1.861       -
    s_en                                                                                       Net      -        -       1.069     -           81
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.s_pout_RNI58SE2[11]                     ARI1     B        In      -         2.930       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.s_pout_RNI58SE2[11]                     ARI1     S        Out     0.268     3.198       -
    s_piout[1]                                                                                 Net      -        -       0.977     -           2
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_1      ARI1     B        In      -         4.175       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_1      ARI1     FCO      Out     0.155     4.330       -
    un1_ymax_i_cry_1                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_2      ARI1     FCI      In      -         4.330       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_2      ARI1     FCO      Out     0.014     4.344       -
    un1_ymax_i_cry_2                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_3      ARI1     FCI      In      -         4.344       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_3      ARI1     FCO      Out     0.014     4.358       -
    un1_ymax_i_cry_3                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_4      ARI1     FCI      In      -         4.358       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_4      ARI1     FCO      Out     0.014     4.372       -
    un1_ymax_i_cry_4                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_5      ARI1     FCI      In      -         4.372       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_5      ARI1     FCO      Out     0.014     4.386       -
    un1_ymax_i_cry_5                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_6      ARI1     FCI      In      -         4.386       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_6      ARI1     FCO      Out     0.014     4.401       -
    un1_ymax_i_cry_6                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_7      ARI1     FCI      In      -         4.401       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_7      ARI1     FCO      Out     0.014     4.415       -
    un1_ymax_i_cry_7                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_8      ARI1     FCI      In      -         4.415       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_8      ARI1     FCO      Out     0.014     4.429       -
    un1_ymax_i_cry_8                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_9      ARI1     FCI      In      -         4.429       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_9      ARI1     FCO      Out     0.014     4.443       -
    un1_ymax_i_cry_9                                                                           Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_10     ARI1     FCI      In      -         4.443       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_10     ARI1     FCO      Out     0.014     4.457       -
    un1_ymax_i_cry_10                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_11     ARI1     FCI      In      -         4.457       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_11     ARI1     FCO      Out     0.014     4.472       -
    un1_ymax_i_cry_11                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_12     ARI1     FCI      In      -         4.472       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_12     ARI1     FCO      Out     0.014     4.486       -
    un1_ymax_i_cry_12                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_13     ARI1     FCI      In      -         4.486       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_13     ARI1     FCO      Out     0.014     4.500       -
    un1_ymax_i_cry_13                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_14     ARI1     FCI      In      -         4.500       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_14     ARI1     FCO      Out     0.014     4.514       -
    un1_ymax_i_cry_14                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_15     ARI1     FCI      In      -         4.514       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_15     ARI1     FCO      Out     0.014     4.528       -
    un1_ymax_i_cry_15                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_16     ARI1     FCI      In      -         4.528       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_16     ARI1     FCO      Out     0.014     4.543       -
    un1_ymax_i_cry_16                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_17     ARI1     FCI      In      -         4.543       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_17     ARI1     FCO      Out     0.014     4.557       -
    un1_ymax_i_cry_17                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_18     ARI1     FCI      In      -         4.557       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_18     ARI1     FCO      Out     0.014     4.571       -
    un1_ymax_i_cry_18                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_19     ARI1     FCI      In      -         4.571       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_19     ARI1     FCO      Out     0.014     4.585       -
    un1_ymax_i_cry_19                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_20     ARI1     FCI      In      -         4.585       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_20     ARI1     FCO      Out     0.014     4.599       -
    un1_ymax_i_cry_20                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_21     ARI1     FCI      In      -         4.599       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_21     ARI1     FCO      Out     0.014     4.614       -
    un1_ymax_i_cry_21                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_22     ARI1     FCI      In      -         4.614       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_22     ARI1     FCO      Out     0.014     4.628       -
    un1_ymax_i_cry_22                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_23     ARI1     FCI      In      -         4.628       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_23     ARI1     FCO      Out     0.014     4.642       -
    un1_ymax_i_cry_23                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_24     ARI1     FCI      In      -         4.642       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_24     ARI1     FCO      Out     0.014     4.656       -
    un1_ymax_i_cry_24                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_25     ARI1     FCI      In      -         4.656       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_25     ARI1     FCO      Out     0.014     4.670       -
    un1_ymax_i_cry_25                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_26     ARI1     FCI      In      -         4.670       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_26     ARI1     FCO      Out     0.014     4.685       -
    un1_ymax_i_cry_26                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_27     ARI1     FCI      In      -         4.685       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_27     ARI1     FCO      Out     0.014     4.699       -
    un1_ymax_i_cry_27                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_28     ARI1     FCI      In      -         4.699       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_28     ARI1     FCO      Out     0.014     4.713       -
    un1_ymax_i_cry_28                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_29     ARI1     FCI      In      -         4.713       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_29     ARI1     FCO      Out     0.014     4.727       -
    un1_ymax_i_cry_29                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_30     ARI1     FCI      In      -         4.727       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_30     ARI1     FCO      Out     0.014     4.741       -
    un1_ymax_i_cry_30                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_31     ARI1     FCI      In      -         4.741       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_31     ARI1     FCO      Out     0.014     4.756       -
    un1_ymax_i_cry_31                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_32     ARI1     FCI      In      -         4.756       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_32     ARI1     FCO      Out     0.014     4.770       -
    un1_ymax_i_cry_32                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_33     ARI1     FCI      In      -         4.770       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_33     ARI1     FCO      Out     0.014     4.784       -
    un1_ymax_i_cry_33                                                                          Net      -        -       0.000     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_34     ARI1     FCI      In      -         4.784       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.un1_ymax_i_cry_34     ARI1     FCO      Out     0.014     4.798       -
    un1_ymax_i                                                                                 Net      -        -       0.896     -           48
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.acc_out_o_2_101       CFG4     C        In      -         5.695       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.acc_out_o_2_101       CFG4     Y        Out     0.194     5.889       -
    acc_out_o_2_17                                                                             Net      -        -       0.749     -           11
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.acc_out_o_2[33]       CFG4     C        In      -         6.637       -
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.PI_CONT_FSM_PROC\.acc_out_o_2[33]       CFG4     Y        Out     0.177     6.814       -
    acc_out_o_2[33]                                                                            Net      -        -       0.138     -           1
    Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.acc_out_o[33]                           SLE      D        In      -         6.952       -
    =====================================================================================================================================================
    Total path delay (propagation time + setup) of 7.174 is 1.760(24.5%) logic and 5.414(75.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                             Starting                                                                                           Arrival
    Instance                                                 Reference     Type               Pin        Net                                                    Time        Slack
                                                             Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                System        CCC                LOCK       LOCK                                                   0.000       1.547
    MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
    =============================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                     Starting                                                                                             Required
    Instance                                                         Reference     Type        Pin                 Net                                                    Time         Slack
                                                                     Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[3]      PRDATA_N_7_1_i                                         9.483        1.547
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        1.776
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[10]     PRDATA_N_7_i                                           9.723        1.846
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[7]      PRDATA_N_7_0_i                                         9.763        2.033
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.604        2.139
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[29]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.625        2.160
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[30]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.629        2.164
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[24]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.678        2.213
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[28]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.688        2.223
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[27]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.694        2.229
    ========================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.517
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.483

        - Propagation time:                      7.936
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 1.547

        Number of logic level(s):                8
        Starting point:                          MC_System_0.MC_System_sb_0.CCC_0.CCC_INST / LOCK
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
        The start point is clocked by            System [rising]
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                                Pin                Pin               Arrival     No. of
    Name                                                                              Type        Name               Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                                         CCC         LOCK               Out     0.000     0.000       -
    LOCK                                                                              Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                                 CLKINT      A                  In      -         0.971       -
    MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                                 CLKINT      Y                  Out     0.326     1.298       -
    MC_System_0_FIC_0_LOCK                                                            Net         -                  -       0.993     -           4621
    Bldc_Axis_0.OLMNG_0.theta_o[3]                                                    CFG4        D                  In      -         2.291       -
    Bldc_Axis_0.OLMNG_0.theta_o[3]                                                    CFG4        Y                  Out     0.250     2.541       -
    theta_o[3]                                                                        Net         -                  -       0.590     -           3
    Bldc_Axis_0.apb3_if_0.prdata_o_1_15_i_m2_0_0_wmux[3]                              ARI1        D                  In      -         3.131       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_15_i_m2_0_0_wmux[3]                              ARI1        Y                  Out     0.284     3.415       -
    prdata_o_1_15_i_m2_0_0_y0[3]                                                      Net         -                  -       0.324     -           1
    Bldc_Axis_0.apb3_if_0.prdata_o_1_15_i_m2_0_wmux_0[3]                              ARI1        A                  In      -         3.739       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_15_i_m2_0_wmux_0[3]                              ARI1        Y                  Out     0.087     3.826       -
    N_1378                                                                            Net         -                  -       0.971     -           1
    Bldc_Axis_0.apb3_if_0.prdata_o_1_24_2[3]                                          CFG4        B                  In      -         4.797       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_24_2[3]                                          CFG4        Y                  Out     0.143     4.940       -
    prdata_o_1_24_2[3]                                                                Net         -                  -       0.483     -           1
    Bldc_Axis_0.apb3_if_0.prdata_o_1_24_5[3]                                          CFG4        C                  In      -         5.423       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_24_5[3]                                          CFG4        Y                  Out     0.182     5.605       -
    prdata_o_1_24_5[3]                                                                Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m1_e                   CFG4        B                  In      -         6.089       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m1_e                   CFG4        Y                  Out     0.143     6.231       -
    PRDATA_N_8_mux_1                                                                  Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m5_e_1_10_RNID5311     CFG4        D                  In      -         6.715       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_m5_e_1_10_RNID5311     CFG4        Y                  Out     0.250     6.965       -
    PRDATA_N_7_1_i                                                                    Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                      MSS_010     F_HM0_RDATA[3]     In      -         7.936       -
    =========================================================================================================================================================
    Total path delay (propagation time + setup) of 8.453 is 2.183(25.8%) logic and 6.271(74.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:29s; Memory used current: 226MB peak: 277MB)

    Finished timing report (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:29s; Memory used current: 226MB peak: 277MB)

    ---------------------------------------
    Resource Usage Report for MC_System_top

    Mapping to part: m2s010fbga484-1
    Cell usage:
    CCC             1 use
    CLKINT          3 uses
    MSS_010         1 use
    RCOSC_25_50MHZ  1 use
    CFG1           52 uses
    CFG2           1084 uses
    CFG3           1567 uses
    CFG4           1564 uses

    Carry cells:
    ARI1            2424 uses - used for arithmetic functions
    ARI1            144 uses - used for Wide-Mux implementation
    Total ARI1      2568 uses

    Sequential Cells:
    SLE            4578 uses

    DSP Blocks:   12 of 22 (54%)
     MACC:         9 MultAdds
     MACC:         3 Mults

    I/O ports: 36
    I/O primitives: 35
    BIBUF          8 uses
    INBUF          5 uses
    OUTBUF         21 uses
    TRIBUFF        1 use

    Global Clock Buffers: 3 of 8 (37%)

    Total LUTs:    6835

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
    MACC     Interface Logic : SLEs = 432; LUTs = 432;

    Total number of SLEs after P&R:  4578 + 0 + 0 + 432 = 5010;
    Total number of LUTs after P&R:  6835 + 0 + 0 + 432 = 7267;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:29s; Memory used current: 47MB peak: 277MB)

    Process took 0h:00m:30s realtime, 0h:00m:29s cputime
    # Fri Dec 01 17:24:46 2017

    ###########################################################]

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