Timing Report Max Delay Analysis

SmartTime Version Libero SoC v11.8 SP1
Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)
Date: Wed Oct 04 15:21:22 2017


Design: MC_System_top
Family: SmartFusion2
Die: M2S010
Package: 484 FBGA
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0                       
Period (ns):                9.411                                                                           
Frequency (MHz):            106.259                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -1.085                                                                          
External Hold (ns):         1.161                                                                           
Min Clock-To-Out (ns):      4.843                                                                           
Max Clock-To-Out (ns):      12.599                                                                          

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1                       
Period (ns):                7.992                                                                           
Frequency (MHz):            125.125                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -0.835                                                                          
External Hold (ns):         0.997                                                                           
Min Clock-To-Out (ns):      5.260                                                                           
Max Clock-To-Out (ns):      9.701                                                                           

Clock Domain:               MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT                     
Period (ns):                N/A                                                                             
Frequency (MHz):            N/A                                                                             
Required Period (ns):       20.000                                                                          
Required Frequency (MHz):   50.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

                            Input to Output                                                                 
Min Delay (ns):             N/A                                                                             
Max Delay (ns):             N/A                                                                             

END SUMMARY
-----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[8]:EN
  Delay (ns):                  8.769                                                                           
  Slack (ns):                  0.589                                                                           
  Arrival (ns):                13.259                                                                          
  Required (ns):               13.848                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.411                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[9]:EN
  Delay (ns):                  8.769                                                                           
  Slack (ns):                  0.590                                                                           
  Arrival (ns):                13.259                                                                          
  Required (ns):               13.849                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.410                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[3]:EN
  Delay (ns):                  8.782                                                                           
  Slack (ns):                  0.597                                                                           
  Arrival (ns):                13.272                                                                          
  Required (ns):               13.869                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.403                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[5]:EN
  Delay (ns):                  8.782                                                                           
  Slack (ns):                  0.597                                                                           
  Arrival (ns):                13.272                                                                          
  Required (ns):               13.869                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.403                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[4]:EN
  Delay (ns):                  8.782                                                                           
  Slack (ns):                  0.597                                                                           
  Arrival (ns):                13.272                                                                          
  Required (ns):               13.869                                                                          
  Setup (ns):                  0.308                                                                           
  Minimum Period (ns):         9.403                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Bldc_Axis_0/apb3_if_0/angle_ki_o[8]:EN
  data required time                             13.848    
  data arrival time                          -   13.259    
  slack                                          0.589     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.302          cell: ADLIB:MSS_010_IP
  5.792                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[11] (r)
               +     2.290          net: MC_System_0_AMBA_SLAVE_0_PADDR[11]
  8.082                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_3_1:B (r)
               +     0.143          cell: ADLIB:CFG4
  8.225                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_3_1:Y (f)
               +     0.778          net: Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_3_1_Z
  9.003                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:A (f)
               +     0.287          cell: ADLIB:CFG4
  9.290                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:Y (f)
               +     0.597          net: Bldc_Axis_0/apb3_if_0/N_1807
  9.887                        Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:D (f)
               +     0.209          cell: ADLIB:CFG4
  10.096                       Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:Y (f)
               +     1.198          net: Bldc_Axis_0/apb3_if_0/N_1819
  11.294                       Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa_0_a2:A (f)
               +     0.209          cell: ADLIB:CFG3
  11.503                       Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa_0_a2:Y (f)
               +     1.756          net: Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa
  13.259                       Bldc_Axis_0/apb3_if_0/angle_ki_o[8]:EN (f)
                                    
  13.259                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn (f)
               +     0.286          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth
  13.433                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB23:An (f)
               +     0.251          cell: ADLIB:RGB
  13.684                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB23:YL (r)
               +     0.472          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB23_rgbl_net_1
  14.156                       Bldc_Axis_0/apb3_if_0/angle_ki_o[8]:CLK (r)
               -     0.308          Library setup time: ADLIB:SLE
  13.848                       Bldc_Axis_0/apb3_if_0/angle_ki_o[8]:EN
                                    
  13.848                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A0_ADC_SDI_I
  To:                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  2.815                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                2.815                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.165                                                                           
  External Setup (ns):         -1.085                                                                          


Expanded Path 1
  From: A0_ADC_SDI_I
  To: Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   2.815     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A0_ADC_SDI_I (f)
               +     0.000          net: A0_ADC_SDI_I
  0.000                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.392          net: A0_ADC_SDI_I_ibuf/U0/YIN1
  1.792                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.159          cell: ADLIB:IOINFF_BYPASS
  1.951                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     0.864          net: A0_ADC_SDI_I_c
  2.815                        Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  2.815                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.161          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn (f)
               +     0.275          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB17:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB17:YR (r)
               +     0.495          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB17_rgbr_net_1
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.165          Library setup time: ADLIB:SLE
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Bldc_Axis_0/MSC_i_11/s_state[0]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  8.424                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                12.599                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           12.599                                                                          

Path 2
  From:                        Bldc_Axis_0/MSC_i_11/s_state[8]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  8.190                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                12.363                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           12.363                                                                          

Path 3
  From:                        Bldc_Axis_0/MSC_i_11/s_state[7]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  7.964                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                12.126                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           12.126                                                                          

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_STP
  Delay (ns):                  6.768                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.258                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.258                                                                          

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_DATA[0]
  Delay (ns):                  6.758                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.248                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.248                                                                          


Expanded Path 1
  From: Bldc_Axis_0/MSC_i_11/s_state[0]:CLK
  To: A0_RUNNING_LED
  data required time                             N/C       
  data arrival time                          -   12.599    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn (f)
               +     0.283          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB17:An (f)
               +     0.251          cell: ADLIB:RGB
  3.681                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB17:YL (r)
               +     0.494          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB17_rgbl_net_1
  4.175                        Bldc_Axis_0/MSC_i_11/s_state[0]:CLK (r)
               +     0.092          cell: ADLIB:SLE
  4.267                        Bldc_Axis_0/MSC_i_11/s_state[0]:Q (r)
               +     0.643          net: Bldc_Axis_0/MSC_i_11/MSC_net_265
  4.910                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:A (r)
               +     0.100          cell: ADLIB:CFG2
  5.010                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:Y (f)
               +     1.042          net: Bldc_Axis_0/MSC_i_11/MSC_net_285
  6.052                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  6.139                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:Y (f)
               +     2.727          net: A0_PWM_UL_O_c
  8.866                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  9.196                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:Y (f)
               +     0.701          net: A0_RUNNING_LED_obuf/U0/DOUT
  9.897                        A0_RUNNING_LED_obuf/U0/U_IOPAD:D (f)
               +     2.702          cell: ADLIB:IOPAD_TRI
  12.599                       A0_RUNNING_LED_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A0_RUNNING_LED
  12.599                       A0_RUNNING_LED (f)
                                    
  12.599                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A0_RUNNING_LED (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

Path 1
  From:                        Stepper_Axis_0/MSC_i_45/s_theta_output[9]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[9]
  Delay (ns):                  6.124                                                                           
  Slack (ns):                  3.844                                                                           
  Arrival (ns):                10.333                                                                          
  Required (ns):               14.177                                                                          
  Setup (ns):                  0.307                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[3]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  Delay (ns):                  5.815                                                                           
  Slack (ns):                  4.031                                                                           
  Arrival (ns):                10.020                                                                          
  Required (ns):               14.051                                                                          
  Setup (ns):                  0.433                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[8]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[8]
  Delay (ns):                  5.675                                                                           
  Slack (ns):                  4.379                                                                           
  Arrival (ns):                9.872                                                                           
  Required (ns):               14.251                                                                          
  Setup (ns):                  0.233                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_45/s_theta_output[4]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[4]
  Delay (ns):                  5.525                                                                           
  Slack (ns):                  4.385                                                                           
  Arrival (ns):                9.722                                                                           
  Required (ns):               14.107                                                                          
  Setup (ns):                  0.377                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[5]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[5]
  Delay (ns):                  5.656                                                                           
  Slack (ns):                  4.391                                                                           
  Arrival (ns):                9.849                                                                           
  Required (ns):               14.240                                                                          
  Setup (ns):                  0.244                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_45/s_theta_output[9]:CLK
  To: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[9]
  data required time                             14.177    
  data arrival time                          -   10.333    
  slack                                          3.844     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.436                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB5:An (f)
               +     0.251          cell: ADLIB:RGB
  3.687                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB5:YL (r)
               +     0.522          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB5_rgbl_net_1
  4.209                        Stepper_Axis_0/MSC_i_45/s_theta_output[9]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.296                        Stepper_Axis_0/MSC_i_45/s_theta_output[9]:Q (r)
               +     2.370          net: Stepper_Axis_0/STEPPER_THETA_0_theta_output_o[9]
  6.666                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8_RNO_0[9]:C (r)
               +     0.270          cell: ADLIB:CFG4
  6.936                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8_RNO_0[9]:Y (r)
               +     0.433          net: Stepper_Axis_0/apb3_if_st_0/STEPPER_THETA_0_theta_output_o_m_out_0
  7.369                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8[9]:D (r)
               +     0.158          cell: ADLIB:CFG4
  7.527                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8[9]:Y (r)
               +     0.657          net: Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8[9]
  8.184                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_7[9]:C (r)
               +     0.074          cell: ADLIB:CFG3
  8.258                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_7[9]:Y (r)
               +     0.228          net: Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_7_Z[9]
  8.486                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv[9]:C (r)
               +     0.158          cell: ADLIB:CFG4
  8.644                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv[9]:Y (r)
               +     0.539          net: MC_System_0_AMBA_SLAVE_1_PRDATA[9]
  9.183                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA[9]:B (r)
               +     0.074          cell: ADLIB:CFG4
  9.257                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA[9]:Y (r)
               +     0.621          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]
  9.878                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_4:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  10.087                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_4:IPB (r)
               +     0.246          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[9]
  10.333                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[9] (r)
                                    
  10.333                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  13.430                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  13.680                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  14.065                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  14.274                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.210          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  14.484                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               -     0.307          Library setup time: ADLIB:MSS_010_IP
  14.177                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[9]
                                    
  14.177                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

SET Register to Register

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/s_state[6]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[12]:D
  Delay (ns):                  7.735                                                                           
  Slack (ns):                  2.008                                                                           
  Arrival (ns):                11.916                                                                          
  Required (ns):               13.924                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.992                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_42/s_state[6]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:D
  Delay (ns):                  7.721                                                                           
  Slack (ns):                  2.012                                                                           
  Arrival (ns):                11.902                                                                          
  Required (ns):               13.914                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.988                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[6]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[5]:D
  Delay (ns):                  7.735                                                                           
  Slack (ns):                  2.020                                                                           
  Arrival (ns):                11.916                                                                          
  Required (ns):               13.936                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.980                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[6]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[4]:D
  Delay (ns):                  7.735                                                                           
  Slack (ns):                  2.020                                                                           
  Arrival (ns):                11.916                                                                          
  Required (ns):               13.936                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.980                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_42/s_state[6]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[3]:D
  Delay (ns):                  7.734                                                                           
  Slack (ns):                  2.021                                                                           
  Arrival (ns):                11.915                                                                          
  Required (ns):               13.936                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.979                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/s_state[6]:CLK
  To: Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[12]:D
  data required time                             13.924    
  data arrival time                          -   11.916    
  slack                                          2.008     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.290          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.437                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8:An (f)
               +     0.251          cell: ADLIB:RGB
  3.688                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8:YL (r)
               +     0.493          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8_rgbl_net_1
  4.181                        Stepper_Axis_0/MSC_i_42/s_state[6]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.268                        Stepper_Axis_0/MSC_i_42/s_state[6]:Q (r)
               +     0.400          net: Stepper_Axis_0/MSC_i_42/MSC_net_82
  4.668                        Stepper_Axis_0/MSC_i_42/s_state_RNIRILT[4]:C (r)
               +     0.158          cell: ADLIB:CFG4
  4.826                        Stepper_Axis_0/MSC_i_42/s_state_RNIRILT[4]:Y (r)
               +     1.312          net: Stepper_Axis_0/SEQ_CONTROLLER_1_en_idq_pi_o
  6.138                        Stepper_Axis_0/MSC_i_47/MSC_i_50/en_o:B (r)
               +     0.074          cell: ADLIB:CFG3
  6.212                        Stepper_Axis_0/MSC_i_47/MSC_i_50/en_o:Y (r)
               +     0.531          net: Stepper_Axis_0/MSC_i_47/MSC_net_516
  6.743                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIRILAC[19]:B (r)
               +     0.235          cell: ADLIB:ARI1_CC
  6.978                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIRILAC[19]:UB (f)
               +     0.000          net: NET_CC_CONFIG6757
  6.978                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:UB[0] (f)
               +     0.697          cell: ADLIB:CC_CONFIG
  7.675                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:CO (r)
               +     0.000          net: CI_TO_CO6727
  7.675                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_2:CI (r)
               +     0.222          cell: ADLIB:CC_CONFIG
  7.897                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_2:CC[4] (r)
               +     0.000          net: NET_CC_CONFIG6806
  7.897                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIBD5721[35]:CC (r)
               +     0.066          cell: ADLIB:ARI1_CC
  7.963                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIBD5721[35]:S (r)
               +     1.126          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_231
  9.089                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_25_RNO:A (r)
               +     0.100          cell: ADLIB:CFG1
  9.189                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_25_RNO:Y (f)
               +     0.426          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_264
  9.615                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_25:A (f)
               +     0.121          cell: ADLIB:ARI1_CC
  9.736                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_25:P (f)
               +     0.000          net: NET_CC_CONFIG954
  9.736                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:P[9] (f)
               +     0.345          cell: ADLIB:CC_CONFIG
  10.081                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:CO (r)
               +     0.000          net: CI_TO_CO926
  10.081                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CI (r)
               +     0.292          cell: ADLIB:CC_CONFIG
  10.373                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CC[7] (r)
               +     0.000          net: NET_CC_CONFIG986
  10.373                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CC (r)
               +     0.066          cell: ADLIB:FCEND_BUFF_CC
  10.439                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CO (r)
               +     0.817          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_945
  11.256                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:B (r)
               +     0.100          cell: ADLIB:CFG2
  11.356                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:Y (f)
               +     0.387          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_1054
  11.743                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[12]:B (f)
               +     0.099          cell: ADLIB:CFG4
  11.842                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[12]:Y (r)
               +     0.074          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_670
  11.916                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[12]:D (r)
                                    
  11.916                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.293          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.440                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:An (f)
               +     0.251          cell: ADLIB:RGB
  13.691                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:YL (r)
               +     0.487          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13_rgbl_net_1
  14.178                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[12]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.924                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[12]:D
                                    
  13.924                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A1_ADC_SDI_I
  To:                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  3.035                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                3.035                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.174                                                                           
  External Setup (ns):         -0.835                                                                          


Expanded Path 1
  From: A1_ADC_SDI_I
  To: Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   3.035     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A1_ADC_SDI_I (f)
               +     0.000          net: A1_ADC_SDI_I
  0.000                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.112          net: A1_ADC_SDI_I_ibuf/U0/YIN1
  1.512                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.141          cell: ADLIB:IOINFF_BYPASS
  1.653                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     1.382          net: A1_ADC_SDI_I_c
  3.035                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  3.035                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.161          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.279          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB3:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB3:YR (r)
               +     0.470          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB3_rgbr_net_1
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.174          Library setup time: ADLIB:SLE
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  5.516                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.701                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.701                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  5.505                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.690                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.690                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  5.342                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.527                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.527                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  5.331                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.516                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.516                                                                           

Path 5
  From:                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sck:CLK
  To:                          A1_ADC_SCK_O
  Delay (ns):                  5.225                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.406                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.406                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To: A1_PWM_WL_O
  data required time                             N/C       
  data arrival time                          -   9.701     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.290          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.437                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8:An (f)
               +     0.251          cell: ADLIB:RGB
  3.688                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8:YL (r)
               +     0.497          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8_rgbl_net_1
  4.185                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.272                        Stepper_Axis_0/MSC_i_42/s_state[0]:Q (r)
               +     0.657          net: Stepper_Axis_0/MSC_i_42/MSC_net_88
  4.929                        Stepper_Axis_0/MSC_i_42/s_state_RNIUPQE[8]:A (r)
               +     0.100          cell: ADLIB:CFG2
  5.029                        Stepper_Axis_0/MSC_i_42/s_state_RNIUPQE[8]:Y (f)
               +     0.573          net: Stepper_Axis_0/MSC_i_42/MSC_net_255
  5.602                        Stepper_Axis_0/MSC_i_42/ADC_START_PROC.un103_s_state_i_a2_0_a2_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.689                        Stepper_Axis_0/MSC_i_42/ADC_START_PROC.un103_s_state_i_a2_0_a2_0_a2:Y (f)
               +     1.900          net: A1_PWM_WH_O_c
  7.589                        A1_PWM_WL_O_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  7.919                        A1_PWM_WL_O_obuf/U0/U_IOOUTFF:Y (f)
               +     0.096          net: A1_PWM_WL_O_obuf/U0/DOUT
  8.015                        A1_PWM_WL_O_obuf/U0/U_IOPAD:D (f)
               +     1.686          cell: ADLIB:IOPAD_TRI
  9.701                        A1_PWM_WL_O_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A1_PWM_WL_O
  9.701                        A1_PWM_WL_O (f)
                                    
  9.701                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A1_PWM_WL_O (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[2]:EN
  Delay (ns):                  8.348                                                                           
  Slack (ns):                  1.088                                                                           
  Arrival (ns):                12.838                                                                          
  Required (ns):               13.926                                                                          
  Setup (ns):                  0.254                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[6]:EN
  Delay (ns):                  8.348                                                                           
  Slack (ns):                  1.088                                                                           
  Arrival (ns):                12.838                                                                          
  Required (ns):               13.926                                                                          
  Setup (ns):                  0.254                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[4]:EN
  Delay (ns):                  8.348                                                                           
  Slack (ns):                  1.088                                                                           
  Arrival (ns):                12.838                                                                          
  Required (ns):               13.926                                                                          
  Setup (ns):                  0.254                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[1]:EN
  Delay (ns):                  8.348                                                                           
  Slack (ns):                  1.099                                                                           
  Arrival (ns):                12.838                                                                          
  Required (ns):               13.937                                                                          
  Setup (ns):                  0.254                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[5]:EN
  Delay (ns):                  8.348                                                                           
  Slack (ns):                  1.099                                                                           
  Arrival (ns):                12.838                                                                          
  Required (ns):               13.937                                                                          
  Setup (ns):                  0.254                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[2]:EN
  data required time                             13.926    
  data arrival time                          -   12.838    
  slack                                          1.088     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.327          cell: ADLIB:MSS_010_IP
  5.817                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[13] (f)
               +     0.941          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[13]
  6.758                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:B (f)
               +     0.147          cell: ADLIB:CFG4
  6.905                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:Y (r)
               +     1.345          net: MC_System_0_AMBA_SLAVE_1_PSELx
  8.250                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:B (r)
               +     0.074          cell: ADLIB:CFG4
  8.324                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:Y (r)
               +     0.460          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_1
  8.784                        Stepper_Axis_0/apb3_if_st_0/idq_pi_ki_o_1_sqmuxa_7:C (r)
               +     0.158          cell: ADLIB:CFG3
  8.942                        Stepper_Axis_0/apb3_if_st_0/idq_pi_ki_o_1_sqmuxa_7:Y (r)
               +     0.355          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_7
  9.297                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_0:B (r)
               +     0.074          cell: ADLIB:CFG2
  9.371                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_0:Y (r)
               +     0.247          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_0_Z
  9.618                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa:D (r)
               +     0.202          cell: ADLIB:CFG4
  9.820                        Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa:Y (r)
               +     3.018          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_Z
  12.838                       Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[2]:EN (r)
                                    
  12.838                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.290          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.437                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8:An (f)
               +     0.251          cell: ADLIB:RGB
  13.688                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8:YL (r)
               +     0.492          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB8_rgbl_net_1
  14.180                       Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[2]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.926                       Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[2]:EN
                                    
  13.926                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

No Path 

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path 

END SET Input to Output

----------------------------------------------------

Path set User Sets

