Timing Report Max Delay Analysis

SmartTime Version Libero SoC v11.8 SP1
Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)
Date: Wed Oct 04 15:04:34 2017


Design: MC_System_top
Family: SmartFusion2
Die: M2S010
Package: 484 FBGA
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0                       
Period (ns):                10.587                                                                          
Frequency (MHz):            94.455                                                                          
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -0.878                                                                          
External Hold (ns):         1.022                                                                           
Min Clock-To-Out (ns):      4.842                                                                           
Max Clock-To-Out (ns):      11.635                                                                          

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1                       
Period (ns):                8.065                                                                           
Frequency (MHz):            123.993                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -1.041                                                                          
External Hold (ns):         1.131                                                                           
Min Clock-To-Out (ns):      5.144                                                                           
Max Clock-To-Out (ns):      9.766                                                                           

Clock Domain:               MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT                     
Period (ns):                N/A                                                                             
Frequency (MHz):            N/A                                                                             
Required Period (ns):       20.000                                                                          
Required Frequency (MHz):   50.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

                            Input to Output                                                                 
Min Delay (ns):             N/A                                                                             
Max Delay (ns):             N/A                                                                             

END SUMMARY
-----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:EN
  Delay (ns):                  9.988                                                                           
  Slack (ns):                  -0.587                                                                          
  Arrival (ns):                14.478                                                                          
  Required (ns):               13.891                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         10.587                                                                          

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[9]:EN
  Delay (ns):                  9.988                                                                           
  Slack (ns):                  -0.579                                                                          
  Arrival (ns):                14.478                                                                          
  Required (ns):               13.899                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         10.579                                                                          

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[8]:EN
  Delay (ns):                  9.988                                                                           
  Slack (ns):                  -0.579                                                                          
  Arrival (ns):                14.478                                                                          
  Required (ns):               13.899                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         10.579                                                                          

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[1]:EN
  Delay (ns):                  9.438                                                                           
  Slack (ns):                  -0.003                                                                          
  Arrival (ns):                13.928                                                                          
  Required (ns):               13.925                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         10.003                                                                          

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[3]:EN
  Delay (ns):                  9.438                                                                           
  Slack (ns):                  -0.003                                                                          
  Arrival (ns):                13.928                                                                          
  Required (ns):               13.925                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         10.003                                                                          


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:EN
  data required time                             13.891    
  data arrival time                          -   14.478    
  slack                                          -0.587    
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.349          cell: ADLIB:MSS_010_IP
  5.839                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[14] (f)
               +     1.001          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[14]
  6.840                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:A (f)
               +     0.099          cell: ADLIB:CFG2
  6.939                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:Y (r)
               +     0.097          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/AMBA_SLAVE_0_PSELS0_i_2
  7.036                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[0]:D (r)
               +     0.074          cell: ADLIB:CFG4
  7.110                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[0]:Y (r)
               +     1.406          net: MC_System_0_AMBA_SLAVE_0_PSELx
  8.516                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:B (r)
               +     0.265          cell: ADLIB:CFG4
  8.781                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:Y (r)
               +     0.608          net: Bldc_Axis_0/apb3_if_0/N_1807
  9.389                        Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:D (r)
               +     0.202          cell: ADLIB:CFG4
  9.591                        Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:Y (r)
               +     1.131          net: Bldc_Axis_0/apb3_if_0/N_1819
  10.722                       Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa_0_a2:A (r)
               +     0.202          cell: ADLIB:CFG3
  10.924                       Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa_0_a2:Y (r)
               +     3.554          net: Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa
  14.478                       Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:EN (r)
                                    
  14.478                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.283          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  13.429                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An (f)
               +     0.251          cell: ADLIB:RGB
  13.680                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL (r)
               +     0.465          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1
  14.145                       Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.891                       Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:EN
                                    
  13.891                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A0_ADC_SDI_I
  To:                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  3.016                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                3.016                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.165                                                                           
  External Setup (ns):         -0.878                                                                          


Expanded Path 1
  From: A0_ADC_SDI_I
  To: Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   3.016     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A0_ADC_SDI_I (f)
               +     0.000          net: A0_ADC_SDI_I
  0.000                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.392          net: A0_ADC_SDI_I_ibuf/U0/YIN1
  1.792                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.159          cell: ADLIB:IOINFF_BYPASS
  1.951                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     1.065          net: A0_ADC_SDI_I_c
  3.016                        Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  3.016                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.160          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.269          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB10:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB10:YR (r)
               +     0.496          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB10_rgbr_net_1
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.165          Library setup time: ADLIB:SLE
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Bldc_Axis_0/MSC_i_11/s_state[8]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  7.468                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.635                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.635                                                                          

Path 2
  From:                        Bldc_Axis_0/MSC_i_11/s_state[0]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  7.391                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.553                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.553                                                                          

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_STP
  Delay (ns):                  6.768                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.258                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.258                                                                          

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_DATA[0]
  Delay (ns):                  6.758                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.248                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.248                                                                          

Path 5
  From:                        Bldc_Axis_0/MSC_i_11/s_state[7]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  7.002                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.159                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.159                                                                          


Expanded Path 1
  From: Bldc_Axis_0/MSC_i_11/s_state[8]:CLK
  To: A0_RUNNING_LED
  data required time                             N/C       
  data arrival time                          -   11.635    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn (f)
               +     0.277          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth
  3.424                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB14:An (f)
               +     0.251          cell: ADLIB:RGB
  3.675                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB14:YL (r)
               +     0.492          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB14_rgbl_net_1
  4.167                        Bldc_Axis_0/MSC_i_11/s_state[8]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.254                        Bldc_Axis_0/MSC_i_11/s_state[8]:Q (r)
               +     0.624          net: Bldc_Axis_0/MSC_i_11/MSC_net_83
  4.878                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:B (r)
               +     0.100          cell: ADLIB:CFG2
  4.978                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:Y (f)
               +     0.511          net: Bldc_Axis_0/MSC_i_11/MSC_net_285
  5.489                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.576                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:Y (f)
               +     2.326          net: A0_PWM_UL_O_c
  7.902                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  8.232                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:Y (f)
               +     0.701          net: A0_RUNNING_LED_obuf/U0/DOUT
  8.933                        A0_RUNNING_LED_obuf/U0/U_IOPAD:D (f)
               +     2.702          cell: ADLIB:IOPAD_TRI
  11.635                       A0_RUNNING_LED_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A0_RUNNING_LED
  11.635                       A0_RUNNING_LED (f)
                                    
  11.635                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A0_RUNNING_LED (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

Path 1
  From:                        Stepper_Axis_0/MSC_i_43/s_ia[3]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  Delay (ns):                  5.474                                                                           
  Slack (ns):                  4.397                                                                           
  Arrival (ns):                9.654                                                                           
  Required (ns):               14.051                                                                          
  Setup (ns):                  0.433                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[3]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  Delay (ns):                  5.190                                                                           
  Slack (ns):                  4.703                                                                           
  Arrival (ns):                9.348                                                                           
  Required (ns):               14.051                                                                          
  Setup (ns):                  0.433                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[2]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[2]
  Delay (ns):                  5.411                                                                           
  Slack (ns):                  4.705                                                                           
  Arrival (ns):                9.569                                                                           
  Required (ns):               14.274                                                                          
  Setup (ns):                  0.210                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_43/s_ib[3]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  Delay (ns):                  5.156                                                                           
  Slack (ns):                  4.717                                                                           
  Arrival (ns):                9.334                                                                           
  Required (ns):               14.051                                                                          
  Setup (ns):                  0.433                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[0]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[0]
  Delay (ns):                  5.230                                                                           
  Slack (ns):                  4.797                                                                           
  Arrival (ns):                9.388                                                                           
  Required (ns):               14.185                                                                          
  Setup (ns):                  0.299                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_43/s_ia[3]:CLK
  To: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
  data required time                             14.051    
  data arrival time                          -   9.654     
  slack                                          4.397     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.436                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB20:An (f)
               +     0.250          cell: ADLIB:RGB
  3.686                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB20:YR (r)
               +     0.494          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB20_rgbr_net_1
  4.180                        Stepper_Axis_0/MSC_i_43/s_ia[3]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.267                        Stepper_Axis_0/MSC_i_43/s_ia[3]:Q (r)
               +     1.653          net: Stepper_Axis_0_ADC_SCALING_0_ia_adc_o[3]
  5.920                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_tz:B (r)
               +     0.336          cell: ADLIB:CFG4
  6.256                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_tz:Y (f)
               +     1.088          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_tz_Z
  7.344                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_0:A (f)
               +     0.087          cell: ADLIB:CFG4
  7.431                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_0:Y (f)
               +     0.093          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_0_0_Z
  7.524                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9:C (f)
               +     0.087          cell: ADLIB:CFG3
  7.611                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9:Y (f)
               +     0.219          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_9_Z
  7.830                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0:C (f)
               +     0.164          cell: ADLIB:CFG3
  7.994                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0:Y (f)
               +     0.095          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_N_12_mux_0
  8.089                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_RNINQHB1:D (f)
               +     0.099          cell: ADLIB:CFG4
  8.188                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m6_e_0_RNINQHB1:Y (r)
               +     0.092          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_N_8_0_i_1
  8.280                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m3_0_a3_5_RNII15M2:C (r)
               +     0.074          cell: ADLIB:CFG4
  8.354                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA_m3_0_a3_5_RNII15M2:Y (r)
               +     0.884          net: MC_System_0/MC_System_sb_0/PRDATA_N_8_0_i
  9.238                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:A (r)
               +     0.194          cell: ADLIB:IP_INTERFACE
  9.432                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:IPA (r)
               +     0.222          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[3]
  9.654                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3] (r)
                                    
  9.654                        data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  13.430                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  13.680                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  14.065                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  14.274                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.210          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  14.484                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               -     0.433          Library setup time: ADLIB:MSS_010_IP
  14.051                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[3]
                                    
  14.051                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

SET Register to Register

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[9]:D
  Delay (ns):                  7.797                                                                           
  Slack (ns):                  1.935                                                                           
  Arrival (ns):                11.984                                                                          
  Required (ns):               13.919                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.065                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[8]:D
  Delay (ns):                  7.803                                                                           
  Slack (ns):                  1.940                                                                           
  Arrival (ns):                11.990                                                                          
  Required (ns):               13.930                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.060                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:D
  Delay (ns):                  7.802                                                                           
  Slack (ns):                  1.942                                                                           
  Arrival (ns):                11.989                                                                          
  Required (ns):               13.931                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.058                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[5]:D
  Delay (ns):                  7.802                                                                           
  Slack (ns):                  1.942                                                                           
  Arrival (ns):                11.989                                                                          
  Required (ns):               13.931                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.058                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[10]:D
  Delay (ns):                  7.795                                                                           
  Slack (ns):                  1.949                                                                           
  Arrival (ns):                11.982                                                                          
  Required (ns):               13.931                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         8.051                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To: Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[9]:D
  data required time                             13.919    
  data arrival time                          -   11.984    
  slack                                          1.935     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.436                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB21:An (f)
               +     0.250          cell: ADLIB:RGB
  3.686                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB21:YR (r)
               +     0.501          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB21_rgbr_net_1
  4.187                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  4.295                        Stepper_Axis_0/MSC_i_42/s_state[2]:Q (f)
               +     0.970          net: Stepper_Axis_0/MSC_i_42/MSC_net_86
  5.265                        Stepper_Axis_0/MSC_i_42/s_state_RNIRILT[4]:D (f)
               +     0.164          cell: ADLIB:CFG4
  5.429                        Stepper_Axis_0/MSC_i_42/s_state_RNIRILT[4]:Y (f)
               +     0.095          net: Stepper_Axis_0/SEQ_CONTROLLER_1_en_idq_pi_o
  5.524                        Stepper_Axis_0/MSC_i_47/MSC_i_50/en_o:B (f)
               +     0.087          cell: ADLIB:CFG3
  5.611                        Stepper_Axis_0/MSC_i_47/MSC_i_50/en_o:Y (f)
               +     0.725          net: Stepper_Axis_0/MSC_i_47/MSC_net_516
  6.336                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]:B (f)
               +     0.231          cell: ADLIB:ARI1_CC
  6.567                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]:UB (r)
               +     0.000          net: NET_CC_CONFIG6731
  6.567                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_0:UB[0] (r)
               +     0.701          cell: ADLIB:CC_CONFIG
  7.268                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_0:CO (f)
               +     0.000          net: CI_TO_CO6728
  7.268                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:CI (f)
               +     0.294          cell: ADLIB:CC_CONFIG
  7.562                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:CC[5] (f)
               +     0.000          net: NET_CC_CONFIG6783
  7.562                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIBHM8N[27]:CC (f)
               +     0.073          cell: ADLIB:ARI1_CC
  7.635                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIBHM8N[27]:S (f)
               +     0.778          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_239
  8.413                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_17_RNO:A (f)
               +     0.099          cell: ADLIB:CFG1
  8.512                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_17_RNO:Y (r)
               +     0.879          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_272
  9.391                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_17:A (r)
               +     0.134          cell: ADLIB:ARI1_CC
  9.525                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_17:P (f)
               +     0.000          net: NET_CC_CONFIG930
  9.525                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:P[1] (f)
               +     0.623          cell: ADLIB:CC_CONFIG
  10.148                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:CO (r)
               +     0.000          net: CI_TO_CO926
  10.148                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CI (r)
               +     0.292          cell: ADLIB:CC_CONFIG
  10.440                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CC[7] (r)
               +     0.000          net: NET_CC_CONFIG986
  10.440                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CC (r)
               +     0.066          cell: ADLIB:FCEND_BUFF_CC
  10.506                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CO (r)
               +     0.829          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_945
  11.335                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:B (r)
               +     0.100          cell: ADLIB:CFG2
  11.435                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:Y (f)
               +     0.375          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_1054
  11.810                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[9]:B (f)
               +     0.099          cell: ADLIB:CFG4
  11.909                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[9]:Y (r)
               +     0.075          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_673
  11.984                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[9]:D (r)
                                    
  11.984                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.292          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.439                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB25:An (f)
               +     0.250          cell: ADLIB:RGB
  13.689                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB25:YR (r)
               +     0.484          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB25_rgbr_net_1
  14.173                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[9]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.919                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[9]:D
                                    
  13.919                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A1_ADC_SDI_I
  To:                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  2.859                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                2.859                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.165                                                                           
  External Setup (ns):         -1.041                                                                          


Expanded Path 1
  From: A1_ADC_SDI_I
  To: Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   2.859     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A1_ADC_SDI_I (f)
               +     0.000          net: A1_ADC_SDI_I
  0.000                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.112          net: A1_ADC_SDI_I_ibuf/U0/YIN1
  1.512                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.141          cell: ADLIB:IOINFF_BYPASS
  1.653                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     1.206          net: A1_ADC_SDI_I_c
  2.859                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  2.859                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.161          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.278          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB16:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB16:YR (r)
               +     0.492          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB16_rgbr_net_1
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.165          Library setup time: ADLIB:SLE
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  5.585                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.766                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.766                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  5.581                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.762                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.762                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  5.261                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.432                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.432                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  5.257                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.428                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.428                                                                           

Path 5
  From:                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sck:CLK
  To:                          A1_ADC_SCK_O
  Delay (ns):                  5.144                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.314                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.314                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To: A1_PWM_WH_O
  data required time                             N/C       
  data arrival time                          -   9.766     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.436                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB21:An (f)
               +     0.250          cell: ADLIB:RGB
  3.686                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB21:YR (r)
               +     0.495          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB21_rgbr_net_1
  4.181                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.268                        Stepper_Axis_0/MSC_i_42/s_state[0]:Q (r)
               +     0.632          net: Stepper_Axis_0/MSC_i_42/MSC_net_88
  4.900                        Stepper_Axis_0/MSC_i_42/s_state_RNIUPQE[8]:A (r)
               +     0.143          cell: ADLIB:CFG2
  5.043                        Stepper_Axis_0/MSC_i_42/s_state_RNIUPQE[8]:Y (f)
               +     0.667          net: Stepper_Axis_0/MSC_i_42/MSC_net_255
  5.710                        Stepper_Axis_0/MSC_i_42/ADC_START_PROC.un103_s_state_i_a2_0_a2_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.797                        Stepper_Axis_0/MSC_i_42/ADC_START_PROC.un103_s_state_i_a2_0_a2_0_a2:Y (f)
               +     1.873          net: A1_PWM_WH_O_c
  7.670                        A1_PWM_WH_O_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  8.000                        A1_PWM_WH_O_obuf/U0/U_IOOUTFF:Y (f)
               +     0.040          net: A1_PWM_WH_O_obuf/U0/DOUT
  8.040                        A1_PWM_WH_O_obuf/U0/U_IOPAD:D (f)
               +     1.726          cell: ADLIB:IOPAD_TRI
  9.766                        A1_PWM_WH_O_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A1_PWM_WH_O
  9.766                        A1_PWM_WH_O (f)
                                    
  9.766                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A1_PWM_WH_O (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[9]:EN
  Delay (ns):                  8.572                                                                           
  Slack (ns):                  0.799                                                                           
  Arrival (ns):                13.062                                                                          
  Required (ns):               13.861                                                                          
  Setup (ns):                  0.308                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[11]:EN
  Delay (ns):                  8.572                                                                           
  Slack (ns):                  0.811                                                                           
  Arrival (ns):                13.062                                                                          
  Required (ns):               13.873                                                                          
  Setup (ns):                  0.308                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[10]:EN
  Delay (ns):                  8.572                                                                           
  Slack (ns):                  0.812                                                                           
  Arrival (ns):                13.062                                                                          
  Required (ns):               13.874                                                                          
  Setup (ns):                  0.308                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[17]:EN
  Delay (ns):                  8.550                                                                           
  Slack (ns):                  0.891                                                                           
  Arrival (ns):                13.040                                                                          
  Required (ns):               13.931                                                                          
  Setup (ns):                  0.254                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o[13]:EN
  Delay (ns):                  8.385                                                                           
  Slack (ns):                  1.043                                                                           
  Arrival (ns):                12.875                                                                          
  Required (ns):               13.918                                                                          
  Setup (ns):                  0.254                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[9]:EN
  data required time                             13.861    
  data arrival time                          -   13.062    
  slack                                          0.799     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.350          cell: ADLIB:MSS_010_IP
  5.840                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[14] (r)
               +     1.003          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[14]
  6.843                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:A (r)
               +     0.100          cell: ADLIB:CFG2
  6.943                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:Y (f)
               +     0.349          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/AMBA_SLAVE_0_PSELS0_i_2
  7.292                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:D (f)
               +     0.087          cell: ADLIB:CFG4
  7.379                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:Y (f)
               +     1.458          net: MC_System_0_AMBA_SLAVE_1_PSELx
  8.837                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:B (f)
               +     0.164          cell: ADLIB:CFG4
  9.001                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:Y (f)
               +     0.103          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_1
  9.104                        Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7:C (f)
               +     0.087          cell: ADLIB:CFG3
  9.191                        Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7:Y (f)
               +     1.113          net: Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7_Z
  10.304                       Stepper_Axis_0/apb3_if_st_0/adc_scale_val_o_1_sqmuxa_0:B (f)
               +     0.209          cell: ADLIB:CFG2
  10.513                       Stepper_Axis_0/apb3_if_st_0/adc_scale_val_o_1_sqmuxa_0:Y (f)
               +     0.305          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_0
  10.818                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2:D (f)
               +     0.287          cell: ADLIB:CFG4
  11.105                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2:Y (f)
               +     0.220          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2_Z
  11.325                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa:D (f)
               +     0.164          cell: ADLIB:CFG4
  11.489                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa:Y (f)
               +     1.573          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_Z
  13.062                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[9]:EN (f)
                                    
  13.062                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.290          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.437                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB22:An (f)
               +     0.250          cell: ADLIB:RGB
  13.687                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB22:YR (r)
               +     0.482          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB22_rgbr_net_1
  14.169                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[9]:CLK (r)
               -     0.308          Library setup time: ADLIB:SLE
  13.861                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[9]:EN
                                    
  13.861                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

No Path 

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path 

END SET Input to Output

----------------------------------------------------

Path set User Sets

