--=================================================================================================
-- File Name                           : olmng.vhd

-- Description                         : This module implements an open loop manager.

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2016 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

--=================================================================================================
-- olmng entity declaration
--=================================================================================================
ENTITY OLMNG IS
GENERIC(
-- Generic list    
    -- Specifies the number of clock delays required before the mas_olmng done signal is asserted.
    g_NO_MCYCLE_PATH                   : INTEGER RANGE 0 to 4 := 2
);
port (
-- Port list
    -- System reset
    reset_i                            : IN  STD_LOGIC;
    
    -- System clock
    sys_clk_i                          : IN  STD_LOGIC;
    
    -- Control input specifies the start of olmng operation
    start_i                            : IN  STD_LOGIC;
	
	-- Control signal indicates motor has stopped
	clear_buffer_i					   : IN  STD_LOGIC;
    
    -- Control input specifies the direction of rotation
    direction_config_i                 : IN  STD_LOGIC;
    
    -- Control input specifies the mode of operation 0 - open loop, 1 - closed loop
    cl_status_i	                       : IN  STD_LOGIC;
    
    -- Control input specifies the theta factor value for omega calculation
	theta_factor_i	                   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Data input specifies the reference speed information from rate limier
	speed_ref_i	                       : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Control input specifies the dv value 
	dv_i	                           : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Control input specifies the estimated theta value from position and speed estimator    
	theta_cl_i                         : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Control input specifies the iq reference value
	iq_ref_in_i                        : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Control output specifies the completion of olmng operation
    done_o	                           : OUT STD_LOGIC;

    -- Theta output
    theta_o                            : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Control output specifies the initialization value for speed pi controller
    init_speedpi_o	                   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Control output specifies the initialization value for id,iq pi controller
    init_iqpi_o	                       : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)

);
END olmng;

--=================================================================================================
-- olmng architecture body
--=================================================================================================
ARCHITECTURE olmng OF olmng IS
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