`timescale 1 ns/100 ps
// Version: v11.7 SP1 11.7.1.14


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MSS_010(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_BASE,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [15:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_BASE;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [2:0] DM_IN;
input  [17:0] DRAM_DQ_IN;
input  [2:0] DRAM_DQS_IN;
input  [1:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [2:0] DRAM_DM_RDQS_OUT;
output [17:0] DRAM_DQ_OUT;
output [2:0] DRAM_DQS_OUT;
output [1:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [2:0] DM_OE;
output [17:0] DRAM_DQ_OE;
output [2:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module MC_System_sb_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GND, VCC;
    
    RCOSC_25_50MHZ #( .FREQUENCY(50.000000) )  I_RCOSC_25_50MHZ (
        .CLKOUT(FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC_Z (.Y(VCC));
    GND GND_Z (.Y(GND));
    
endmodule


module COREAPB3_MUXPTOB3(
       prdata_o_1_0,
       ADC_SCALING_0_ib_adc_o,
       STEPPER_THETA_1_step_count_o,
       adc_interface_0_result_ch0_o,
       adc_interface_0_result_ch2_o,
       adc_measurements_0_adc_result_ch3_o,
       adc_measurements_0_adc_result_ch1_o,
       MC_System_0_AMBA_SLAVE_1_PADDR_0,
       MC_System_0_AMBA_SLAVE_1_PADDR_2,
       MC_System_0_AMBA_SLAVE_1_PADDR_3,
       SEQ_CONTROLLER_1_state_o_0,
       prdata_o_1_0_a2_12_0,
       prdata_o_1_0_a2_10_0,
       FOC_TRANSFORMS_1_valpha_o,
       prdata_o_1_iv_12_1,
       FOC_TRANSFORMS_0_vbeta_o,
       prdata_o_1_iv_12_0_2,
       SPEED_ID_IQ_PI_1_iq_pi_output_o,
       FOC_TRANSFORMS_0_iq_o_0,
       FOC_TRANSFORMS_0_iq_o_9,
       FOC_TRANSFORMS_0_id_o_0,
       FOC_TRANSFORMS_0_id_o_9,
       prdata_o_1_iv_9,
       SPEED_ID_IQ_PI_1_id_pi_output_o_m,
       prdata_o_1_0_1,
       prdata_o_1_0_2,
       prdata_o_1_0_0,
       prdata_o_1_3,
       prdata_o_1_4,
       prdata_o_1_2,
       prdata_o_1_24_3,
       prdata_o_1_24_4,
       prdata_o_1_24_2,
       prdata_o_1_12_2,
       prdata_o_1_12_3,
       prdata_o_1_12_1,
       prdata_o_1_0_iv_6,
       prdata_o_1_0_iv_7,
       prdata_o_1_0_iv_10,
       prdata_o_1_0_iv_11,
       prdata_o_1_iv_11_0,
       prdata_o_1_iv_11_1,
       prdata_o_1_iv_11_3,
       prdata_o_1_iv_12,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       N_2661,
       N_1077,
       N_2660,
       N_2785,
       N_1014,
       N_2779,
       N_2704,
       N_184,
       adc_channel_ch3_o_1_sqmuxa_0_a2_0_0,
       N_172,
       N_174,
       prdata_o197_0_a2_0_a2_0_out,
       prdata_o201_0_a2_0_0,
       N_201,
       N_193,
       N_187,
       N_2470,
       g2,
       g1_0,
       MC_System_0_AMBA_SLAVE_1_PSELx,
       N_106,
       N_108,
       N_202,
       N_1083,
       N_104,
       N_179,
       N_107,
       N_105,
       N_233,
       N_194,
       N_1080,
       N_2522,
       N_2784,
       N_1007,
       N_2532,
       N_2778,
       prdata_o195_0_a2_0,
       prdata_o191,
       N_1508,
       N_2542,
       N_2791,
       N_2734,
       N_2585,
       prdata_o190,
       N_2606,
       N_2728,
       N_54,
       N_157,
       N_151,
       N_152,
       N_153,
       N_154,
       N_155,
       N_156
    );
input  [3:3] prdata_o_1_0;
input  [2:2] ADC_SCALING_0_ib_adc_o;
input  [2:2] STEPPER_THETA_1_step_count_o;
input  [2:2] adc_interface_0_result_ch0_o;
input  [2:2] adc_interface_0_result_ch2_o;
input  [2:2] adc_measurements_0_adc_result_ch3_o;
input  [2:2] adc_measurements_0_adc_result_ch1_o;
input  MC_System_0_AMBA_SLAVE_1_PADDR_0;
input  MC_System_0_AMBA_SLAVE_1_PADDR_2;
input  MC_System_0_AMBA_SLAVE_1_PADDR_3;
input  [2:2] SEQ_CONTROLLER_1_state_o_0;
input  [15:15] prdata_o_1_0_a2_12_0;
input  [15:15] prdata_o_1_0_a2_10_0;
input  [11:11] FOC_TRANSFORMS_1_valpha_o;
input  [3:3] prdata_o_1_iv_12_1;
input  [11:11] FOC_TRANSFORMS_0_vbeta_o;
input  [3:3] prdata_o_1_iv_12_0_2;
input  [0:0] SPEED_ID_IQ_PI_1_iq_pi_output_o;
input  FOC_TRANSFORMS_0_iq_o_0;
input  FOC_TRANSFORMS_0_iq_o_9;
input  FOC_TRANSFORMS_0_id_o_0;
input  FOC_TRANSFORMS_0_id_o_9;
input  [0:0] prdata_o_1_iv_9;
input  [0:0] SPEED_ID_IQ_PI_1_id_pi_output_o_m;
input  [16:12] prdata_o_1_0_1;
input  [16:12] prdata_o_1_0_2;
input  [16:12] prdata_o_1_0_0;
input  [3:2] prdata_o_1_3;
input  [2:2] prdata_o_1_4;
input  [3:2] prdata_o_1_2;
input  [1:1] prdata_o_1_24_3;
input  [1:1] prdata_o_1_24_4;
input  [1:1] prdata_o_1_24_2;
input  [11:4] prdata_o_1_12_2;
input  [11:4] prdata_o_1_12_3;
input  [11:4] prdata_o_1_12_1;
input  [16:12] prdata_o_1_0_iv_6;
input  [16:12] prdata_o_1_0_iv_7;
input  [10:4] prdata_o_1_0_iv_10;
input  [10:4] prdata_o_1_0_iv_11;
input  prdata_o_1_iv_11_0;
input  prdata_o_1_iv_11_1;
input  prdata_o_1_iv_11_3;
input  [3:1] prdata_o_1_iv_12;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3;
input  MC_System_0_AMBA_SLAVE_0_PSELx;
input  N_2661;
input  N_1077;
input  N_2660;
input  N_2785;
input  N_1014;
input  N_2779;
input  N_2704;
input  N_184;
input  adc_channel_ch3_o_1_sqmuxa_0_a2_0_0;
input  N_172;
input  N_174;
input  prdata_o197_0_a2_0_a2_0_out;
input  prdata_o201_0_a2_0_0;
input  N_201;
input  N_193;
input  N_187;
input  N_2470;
input  g2;
input  g1_0;
input  MC_System_0_AMBA_SLAVE_1_PSELx;
input  N_106;
input  N_108;
input  N_202;
input  N_1083;
input  N_104;
input  N_179;
input  N_107;
input  N_105;
input  N_233;
input  N_194;
input  N_1080;
input  N_2522;
input  N_2784;
input  N_1007;
input  N_2532;
input  N_2778;
input  prdata_o195_0_a2_0;
input  prdata_o191;
input  N_1508;
input  N_2542;
input  N_2791;
input  N_2734;
input  N_2585;
input  prdata_o190;
input  N_2606;
input  N_2728;
input  N_54;
input  N_157;
input  N_151;
input  N_152;
input  N_153;
input  N_154;
input  N_155;
input  N_156;

    wire [17:17] PRDATA_1_a3_1_1;
    wire [3:3] PRDATA_1_a3_0_1_0;
    wire [0:0] PRDATA_1_a3_c;
    wire r_m2_0_a2_1_1, N_42, PRDATA_m1_e_2_Z, N_98, g0_3_a7_2_0_Z, 
        g0_3_a7_3_1_Z, N_16_0, g0_3_a7_1_0_Z, g0_3_a7_0_0_Z, N_6, N_7, 
        g0_3_1_Z, g0_3_0_Z, g1_3_Z, g1, N_100, PRDATA_m8_0_a3_1_1, 
        PRDATA_m8_0_a3_2_Z, PRDATA_m8_0_a3_1_Z, PRDATA_m8_0_a3_0_0_Z, 
        r_m1_0_a2_0, PRDATA_m1_e_Z, PRDATA_m8_0_a3_4_Z, PRDATA_m7_2_Z, 
        PRDATA_m7_1_Z, PRDATA_m8_0_a3_5_Z, r_N_3_mux, N_104_0, N_72, 
        N_74, N_76, N_78, N_80, N_84, N_86, N_88, N_90, N_92, N_94, 
        N_96, N_102, N_82, GND, VCC;
    
    CFG4 #( .INIT(16'hEAAA) )  g0_3_o7 (.A(N_16_0), .B(N_174), .C(
        adc_measurements_0_adc_result_ch1_o[2]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR_0), .Y(N_6));
    CFG4 #( .INIT(16'hCCC8) )  \PRDATA_1_a3_c_0[0]  (.A(PRDATA_m1_e_Z), 
        .B(MC_System_0_AMBA_SLAVE_1_PSELx), .C(prdata_o_1_iv_9[0]), .D(
        SPEED_ID_IQ_PI_1_id_pi_output_o_m[0]), .Y(PRDATA_1_a3_c[0]));
    CFG4 #( .INIT(16'hFAF8) )  \PRDATA_1_a3_1[6]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(prdata_o_1_0_iv_10[6]), .C(
        N_92), .D(prdata_o_1_0_iv_11[6]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6));
    CFG4 #( .INIT(16'hFFC8) )  \PRDATA_1_a3_0_RNIV2U8D[2]  (.A(g1), .B(
        MC_System_0_AMBA_SLAVE_1_PSELx), .C(prdata_o_1_iv_12[2]), .D(
        N_100), .Y(MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[5]  (.A(
        prdata_o_1_12_2[5]), .B(prdata_o_1_12_3[5]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_12_1[5]), .Y(
        N_94));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[8]  (.A(
        prdata_o_1_12_2[8]), .B(prdata_o_1_12_3[8]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_12_1[8]), .Y(
        N_88));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[7]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_90), .C(
        prdata_o_1_0_iv_10[7]), .D(prdata_o_1_0_iv_11[7]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7));
    CFG4 #( .INIT(16'hFAF8) )  \PRDATA_1_a3_1[12]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(prdata_o_1_0_iv_6[12]), .C(
        N_80), .D(prdata_o_1_0_iv_7[12]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12));
    CFG4 #( .INIT(16'h153F) )  PRDATA_m8_0_a3_2 (.A(
        FOC_TRANSFORMS_1_valpha_o[11]), .B(N_104), .C(N_187), .D(
        prdata_o_1_iv_12_1[3]), .Y(PRDATA_m8_0_a3_2_Z));
    CFG4 #( .INIT(16'hFCEC) )  \PRDATA_1[19]  (.A(N_54), .B(N_42), .C(
        MC_System_0_AMBA_SLAVE_1_PSELx), .D(N_152), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19));
    CFG4 #( .INIT(16'hECA0) )  g0_3_1 (.A(g0_3_a7_3_1_Z), .B(
        g0_3_a7_0_0_Z), .C(prdata_o201_0_a2_0_0), .D(N_201), .Y(
        g0_3_1_Z));
    CFG2 #( .INIT(4'h8) )  g0_3_a7_2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR_0), .B(
        ADC_SCALING_0_ib_adc_o[2]), .Y(g0_3_a7_2_0_Z));
    CFG4 #( .INIT(16'hFCEC) )  \PRDATA_1[23]  (.A(N_54), .B(N_42), .C(
        MC_System_0_AMBA_SLAVE_1_PSELx), .D(N_156), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31));
    CFG4 #( .INIT(16'h135F) )  PRDATA_m7_2 (.A(N_1508), .B(N_2542), .C(
        N_193), .D(N_2791), .Y(PRDATA_m7_2_Z));
    CFG4 #( .INIT(16'h0007) )  \PRDATA_1_a3_0_1_0[3]  (.A(N_1014), .B(
        N_2779), .C(N_2704), .D(prdata_o_1_0[3]), .Y(
        PRDATA_1_a3_0_1_0[3]));
    CFG4 #( .INIT(16'hFCEC) )  \PRDATA_1[22]  (.A(N_54), .B(N_42), .C(
        MC_System_0_AMBA_SLAVE_1_PSELx), .D(N_155), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[8]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_88), .C(
        prdata_o_1_0_iv_10[8]), .D(prdata_o_1_0_iv_11[8]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8));
    CFG4 #( .INIT(16'h8000) )  PRDATA_m1_e_2 (.A(N_202), .B(N_1083), 
        .C(prdata_o_1_0_a2_12_0[15]), .D(prdata_o_1_0_a2_10_0[15]), .Y(
        PRDATA_m1_e_2_Z));
    CFG3 #( .INIT(8'h08) )  g0_3_a7_3_1 (.A(N_184), .B(
        STEPPER_THETA_1_step_count_o[2]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR_0), .Y(g0_3_a7_3_1_Z));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[1]  (.A(
        prdata_o_1_24_3[1]), .B(prdata_o_1_24_4[1]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_24_2[1]), .Y(
        N_102));
    CFG4 #( .INIT(16'h57DF) )  PRDATA_m8_0_a3_0_tz (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR_3), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR_2), .C(N_106), .D(N_108), .Y(
        PRDATA_m8_0_a3_1_1));
    CFG4 #( .INIT(16'h135F) )  PRDATA_m8_0_a3_0_0 (.A(N_107), .B(N_105)
        , .C(N_233), .D(N_194), .Y(PRDATA_m8_0_a3_0_0_Z));
    CFG4 #( .INIT(16'hFAF8) )  \PRDATA_1_a3_1[1]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(prdata_o_1_iv_11_1), .C(
        N_102), .D(prdata_o_1_iv_12[1]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[2]  (.A(prdata_o_1_3[2]), 
        .B(prdata_o_1_4[2]), .C(MC_System_0_AMBA_SLAVE_0_PSELx), .D(
        prdata_o_1_2[2]), .Y(N_100));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[3]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_98), .C(
        prdata_o_1_iv_11_3), .D(prdata_o_1_iv_12[3]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3));
    CFG4 #( .INIT(16'hECA0) )  g0_3_0 (.A(g0_3_a7_1_0_Z), .B(
        g0_3_a7_2_0_Z), .C(N_193), .D(N_187), .Y(g0_3_0_Z));
    CFG4 #( .INIT(16'h72F0) )  \PRDATA_1_a3[0]  (.A(PRDATA_m7_1_Z), .B(
        r_N_3_mux), .C(MC_System_0_AMBA_SLAVE_0_PSELx), .D(
        PRDATA_m7_2_Z), .Y(N_104_0));
    CFG4 #( .INIT(16'h0013) )  \PRDATA_1_a3_1_1[17]  (.A(N_1077), .B(
        N_2660), .C(N_2785), .D(PRDATA_m1_e_2_Z), .Y(
        PRDATA_1_a3_1_1[17]));
    CFG4 #( .INIT(16'h8AAA) )  \PRDATA_1_a3_1[17]  (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(N_2661), .C(r_m2_0_a2_1_1), 
        .D(PRDATA_1_a3_1_1[17]), .Y(N_42));
    CFG4 #( .INIT(16'h7000) )  PRDATA_m8_0_a3_5 (.A(
        FOC_TRANSFORMS_0_id_o_9), .B(prdata_o190), .C(
        PRDATA_m8_0_a3_0_0_Z), .D(PRDATA_m8_0_a3_1_Z), .Y(
        PRDATA_m8_0_a3_5_Z));
    CFG4 #( .INIT(16'h1300) )  PRDATA_m7_1 (.A(N_2779), .B(N_2734), .C(
        N_2585), .D(MC_System_0_AMBA_SLAVE_0_PSELx), .Y(PRDATA_m7_1_Z));
    CFG4 #( .INIT(16'hFFFE) )  g0_3 (.A(g0_3_1_Z), .B(g0_3_0_Z), .C(
        N_7), .D(g1_3_Z), .Y(g1));
    CFG4 #( .INIT(16'hCCC8) )  \PRDATA_1_a3_0[14]  (.A(
        prdata_o_1_0_1[14]), .B(MC_System_0_AMBA_SLAVE_0_PSELx), .C(
        prdata_o_1_0_2[14]), .D(prdata_o_1_0_0[14]), .Y(N_76));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[9]  (.A(
        prdata_o_1_12_2[9]), .B(prdata_o_1_12_3[9]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_12_1[9]), .Y(
        N_86));
    CFG4 #( .INIT(16'h4000) )  g0_3_a3 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR_0), .B(
        adc_interface_0_result_ch0_o[2]), .C(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .D(N_172), .Y(N_16_0));
    CFG4 #( .INIT(16'h8000) )  PRDATA_m1_e (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]), .D(prdata_o195_0_a2_0), 
        .Y(PRDATA_m1_e_Z));
    CFG4 #( .INIT(16'hCCC8) )  \PRDATA_1_a3_0[15]  (.A(
        prdata_o_1_0_1[15]), .B(MC_System_0_AMBA_SLAVE_0_PSELx), .C(
        prdata_o_1_0_2[15]), .D(prdata_o_1_0_0[15]), .Y(N_74));
    CFG4 #( .INIT(16'hFFF8) )  g1_3 (.A(N_2470), .B(
        SEQ_CONTROLLER_1_state_o_0[2]), .C(g2), .D(g1_0), .Y(g1_3_Z));
    CFG4 #( .INIT(16'h2A3F) )  PRDATA_m8_0_a3_1 (.A(PRDATA_m8_0_a3_1_1)
        , .B(FOC_TRANSFORMS_0_vbeta_o[11]), .C(prdata_o_1_iv_12_0_2[3])
        , .D(N_179), .Y(PRDATA_m8_0_a3_1_Z));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[6]  (.A(
        prdata_o_1_12_2[6]), .B(prdata_o_1_12_3[6]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_12_1[6]), .Y(
        N_92));
    CFG4 #( .INIT(16'hFAF8) )  \PRDATA_1_a3_1[9]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(prdata_o_1_0_iv_10[9]), .C(
        N_86), .D(prdata_o_1_0_iv_11[9]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9));
    CFG4 #( .INIT(16'hFCEC) )  \PRDATA_1[21]  (.A(N_54), .B(N_42), .C(
        MC_System_0_AMBA_SLAVE_1_PSELx), .D(N_154), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21));
    CFG4 #( .INIT(16'h8000) )  g0_3_a7 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR_3), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR_2), .C(N_6), .D(
        prdata_o197_0_a2_0_a2_0_out), .Y(N_7));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[14]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_76), .C(
        prdata_o_1_0_iv_6[14]), .D(prdata_o_1_0_iv_7[14]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14));
    CFG4 #( .INIT(16'hA0C0) )  g0_3_a7_1_0 (.A(FOC_TRANSFORMS_0_iq_o_0)
        , .B(FOC_TRANSFORMS_0_id_o_0), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR_2), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR_0), .Y(g0_3_a7_1_0_Z));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[4]  (.A(
        prdata_o_1_12_2[4]), .B(prdata_o_1_12_3[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_12_1[4]), .Y(
        N_96));
    CFG4 #( .INIT(16'hCCC8) )  \PRDATA_1_a3_0[13]  (.A(
        prdata_o_1_0_1[13]), .B(MC_System_0_AMBA_SLAVE_0_PSELx), .C(
        prdata_o_1_0_2[13]), .D(prdata_o_1_0_0[13]), .Y(N_78));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[10]  (.A(
        prdata_o_1_12_2[10]), .B(prdata_o_1_12_3[10]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_12_1[10]), .Y(
        N_84));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_74), .C(
        prdata_o_1_0_iv_6[15]), .D(prdata_o_1_0_iv_7[15]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15));
    CFG4 #( .INIT(16'hF0B0) )  \PRDATA_1_a3_0[3]  (.A(prdata_o_1_3[3]), 
        .B(PRDATA_1_a3_0_1_0[3]), .C(MC_System_0_AMBA_SLAVE_0_PSELx), 
        .D(prdata_o_1_2[3]), .Y(N_98));
    GND GND_Z (.Y(GND));
    VCC VCC_Z (.Y(VCC));
    CFG4 #( .INIT(16'h153F) )  \PRDATA_1_a3_1_RNO[17]  (.A(N_1080), .B(
        N_2522), .C(N_2784), .D(N_2779), .Y(r_m2_0_a2_1_1));
    CFG4 #( .INIT(16'hFFEC) )  \PRDATA_1_a3_1[0]  (.A(
        prdata_o_1_iv_11_0), .B(PRDATA_1_a3_c[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PSELx), .D(N_104_0), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[7]  (.A(
        prdata_o_1_12_2[7]), .B(prdata_o_1_12_3[7]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_12_1[7]), .Y(
        N_90));
    CFG4 #( .INIT(16'hCCC8) )  \PRDATA_1_a3_0[16]  (.A(
        prdata_o_1_0_1[16]), .B(MC_System_0_AMBA_SLAVE_0_PSELx), .C(
        prdata_o_1_0_2[16]), .D(prdata_o_1_0_0[16]), .Y(N_72));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA_1_a3_0[11]  (.A(
        prdata_o_1_12_2[11]), .B(prdata_o_1_12_3[11]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_o_1_12_1[11]), .Y(
        N_82));
    CFG4 #( .INIT(16'hC0A0) )  g0_3_a7_0_0 (.A(
        adc_interface_0_result_ch2_o[2]), .B(
        adc_measurements_0_adc_result_ch3_o[2]), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR_0), .Y(g0_3_a7_0_0_Z));
    CFG4 #( .INIT(16'h153F) )  \PRDATA_1_a3_RNO_0[0]  (.A(N_1007), .B(
        N_2532), .C(N_2778), .D(N_2784), .Y(r_m1_0_a2_0));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[13]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_78), .C(
        prdata_o_1_0_iv_6[13]), .D(prdata_o_1_0_iv_7[13]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13));
    CFG3 #( .INIT(8'h4C) )  PRDATA_m8_0_a3_4 (.A(prdata_o191), .B(
        PRDATA_m8_0_a3_2_Z), .C(FOC_TRANSFORMS_0_iq_o_9), .Y(
        PRDATA_m8_0_a3_4_Z));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[10]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_84), .C(
        prdata_o_1_0_iv_10[10]), .D(prdata_o_1_0_iv_11[10]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[5]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_94), .C(
        prdata_o_1_0_iv_10[5]), .D(prdata_o_1_0_iv_11[5]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5));
    CFG4 #( .INIT(16'h0700) )  \PRDATA_1_a3_RNO[0]  (.A(N_2606), .B(
        N_2785), .C(N_2728), .D(r_m1_0_a2_0), .Y(r_N_3_mux));
    CFG4 #( .INIT(16'hFCEC) )  \PRDATA_1[20]  (.A(N_54), .B(N_42), .C(
        MC_System_0_AMBA_SLAVE_1_PSELx), .D(N_153), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[4]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_96), .C(
        prdata_o_1_0_iv_10[4]), .D(prdata_o_1_0_iv_11[4]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4));
    CFG4 #( .INIT(16'hFCEC) )  \PRDATA_1[18]  (.A(N_54), .B(N_42), .C(
        MC_System_0_AMBA_SLAVE_1_PSELx), .D(N_151), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18));
    CFG4 #( .INIT(16'hEEEC) )  \PRDATA_1_a3_1[16]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_72), .C(
        prdata_o_1_0_iv_6[16]), .D(prdata_o_1_0_iv_7[16]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16));
    CFG4 #( .INIT(16'hCCC8) )  \PRDATA_1_a3_0[12]  (.A(
        prdata_o_1_0_1[12]), .B(MC_System_0_AMBA_SLAVE_0_PSELx), .C(
        prdata_o_1_0_2[12]), .D(prdata_o_1_0_0[12]), .Y(N_80));
    CFG4 #( .INIT(16'hCEEE) )  \PRDATA[11]  (.A(
        MC_System_0_AMBA_SLAVE_1_PSELx), .B(N_82), .C(
        PRDATA_m8_0_a3_4_Z), .D(PRDATA_m8_0_a3_5_Z), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11));
    CFG4 #( .INIT(16'hFCEC) )  \PRDATA_1[17]  (.A(N_54), .B(N_42), .C(
        MC_System_0_AMBA_SLAVE_1_PSELx), .D(N_157), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17));
    
endmodule


module 
        CoreAPB3_32_0_1_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_16_3_19(
        
       prdata_o_1_0,
       ADC_SCALING_0_ib_adc_o,
       STEPPER_THETA_1_step_count_o,
       adc_interface_0_result_ch0_o,
       adc_interface_0_result_ch2_o,
       adc_measurements_0_adc_result_ch3_o,
       adc_measurements_0_adc_result_ch1_o,
       MC_System_0_AMBA_SLAVE_1_PADDR_13,
       MC_System_0_AMBA_SLAVE_1_PADDR_12,
       MC_System_0_AMBA_SLAVE_1_PADDR_11,
       MC_System_0_AMBA_SLAVE_1_PADDR_10,
       MC_System_0_AMBA_SLAVE_1_PADDR_0,
       MC_System_0_AMBA_SLAVE_1_PADDR_2,
       MC_System_0_AMBA_SLAVE_1_PADDR_3,
       SEQ_CONTROLLER_1_state_o_0,
       prdata_o_1_0_a2_12_0,
       prdata_o_1_0_a2_10_0,
       FOC_TRANSFORMS_1_valpha_o,
       prdata_o_1_iv_12_1,
       FOC_TRANSFORMS_0_vbeta_o,
       prdata_o_1_iv_12_0_2,
       SPEED_ID_IQ_PI_1_iq_pi_output_o,
       FOC_TRANSFORMS_0_iq_o_0,
       FOC_TRANSFORMS_0_iq_o_9,
       FOC_TRANSFORMS_0_id_o_0,
       FOC_TRANSFORMS_0_id_o_9,
       prdata_o_1_iv_9,
       SPEED_ID_IQ_PI_1_id_pi_output_o_m,
       prdata_o_1_0_1,
       prdata_o_1_0_2,
       prdata_o_1_0_0,
       prdata_o_1_3,
       prdata_o_1_4,
       prdata_o_1_2,
       prdata_o_1_24_3,
       prdata_o_1_24_4,
       prdata_o_1_24_2,
       prdata_o_1_12_2,
       prdata_o_1_12_3,
       prdata_o_1_12_1,
       prdata_o_1_0_iv_6,
       prdata_o_1_0_iv_7,
       prdata_o_1_0_iv_10,
       prdata_o_1_0_iv_11,
       prdata_o_1_iv_11_0,
       prdata_o_1_iv_11_1,
       prdata_o_1_iv_11_3,
       prdata_o_1_iv_12,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       MC_System_0_AMBA_SLAVE_1_PSELx,
       N_2661,
       N_1077,
       N_2660,
       N_2785,
       N_1014,
       N_2779,
       N_2704,
       N_184,
       adc_channel_ch3_o_1_sqmuxa_0_a2_0_0,
       N_172,
       N_174,
       prdata_o197_0_a2_0_a2_0_out,
       prdata_o201_0_a2_0_0,
       N_201,
       N_193,
       N_187,
       N_2470,
       g2,
       g1,
       N_106,
       N_108,
       N_202,
       N_1083,
       N_104,
       N_179,
       N_107,
       N_105,
       N_233,
       N_194,
       N_1080,
       N_2522,
       N_2784,
       N_1007,
       N_2532,
       N_2778,
       prdata_o195_0_a2_0,
       prdata_o191,
       N_1508,
       N_2542,
       N_2791,
       N_2734,
       N_2585,
       prdata_o190,
       N_2606,
       N_2728,
       N_54,
       N_157,
       N_151,
       N_152,
       N_153,
       N_154,
       N_155,
       N_156
    );
input  [3:3] prdata_o_1_0;
input  [2:2] ADC_SCALING_0_ib_adc_o;
input  [2:2] STEPPER_THETA_1_step_count_o;
input  [2:2] adc_interface_0_result_ch0_o;
input  [2:2] adc_interface_0_result_ch2_o;
input  [2:2] adc_measurements_0_adc_result_ch3_o;
input  [2:2] adc_measurements_0_adc_result_ch1_o;
input  MC_System_0_AMBA_SLAVE_1_PADDR_13;
input  MC_System_0_AMBA_SLAVE_1_PADDR_12;
input  MC_System_0_AMBA_SLAVE_1_PADDR_11;
input  MC_System_0_AMBA_SLAVE_1_PADDR_10;
input  MC_System_0_AMBA_SLAVE_1_PADDR_0;
input  MC_System_0_AMBA_SLAVE_1_PADDR_2;
input  MC_System_0_AMBA_SLAVE_1_PADDR_3;
input  [2:2] SEQ_CONTROLLER_1_state_o_0;
input  [15:15] prdata_o_1_0_a2_12_0;
input  [15:15] prdata_o_1_0_a2_10_0;
input  [11:11] FOC_TRANSFORMS_1_valpha_o;
input  [3:3] prdata_o_1_iv_12_1;
input  [11:11] FOC_TRANSFORMS_0_vbeta_o;
input  [3:3] prdata_o_1_iv_12_0_2;
input  [0:0] SPEED_ID_IQ_PI_1_iq_pi_output_o;
input  FOC_TRANSFORMS_0_iq_o_0;
input  FOC_TRANSFORMS_0_iq_o_9;
input  FOC_TRANSFORMS_0_id_o_0;
input  FOC_TRANSFORMS_0_id_o_9;
input  [0:0] prdata_o_1_iv_9;
input  [0:0] SPEED_ID_IQ_PI_1_id_pi_output_o_m;
input  [16:12] prdata_o_1_0_1;
input  [16:12] prdata_o_1_0_2;
input  [16:12] prdata_o_1_0_0;
input  [3:2] prdata_o_1_3;
input  [2:2] prdata_o_1_4;
input  [3:2] prdata_o_1_2;
input  [1:1] prdata_o_1_24_3;
input  [1:1] prdata_o_1_24_4;
input  [1:1] prdata_o_1_24_2;
input  [11:4] prdata_o_1_12_2;
input  [11:4] prdata_o_1_12_3;
input  [11:4] prdata_o_1_12_1;
input  [16:12] prdata_o_1_0_iv_6;
input  [16:12] prdata_o_1_0_iv_7;
input  [10:4] prdata_o_1_0_iv_10;
input  [10:4] prdata_o_1_0_iv_11;
input  prdata_o_1_iv_11_0;
input  prdata_o_1_iv_11_1;
input  prdata_o_1_iv_11_3;
input  [3:1] prdata_o_1_iv_12;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx;
output MC_System_0_AMBA_SLAVE_0_PSELx;
output MC_System_0_AMBA_SLAVE_1_PSELx;
input  N_2661;
input  N_1077;
input  N_2660;
input  N_2785;
input  N_1014;
input  N_2779;
input  N_2704;
input  N_184;
input  adc_channel_ch3_o_1_sqmuxa_0_a2_0_0;
input  N_172;
input  N_174;
input  prdata_o197_0_a2_0_a2_0_out;
input  prdata_o201_0_a2_0_0;
input  N_201;
input  N_193;
input  N_187;
input  N_2470;
input  g2;
input  g1;
input  N_106;
input  N_108;
input  N_202;
input  N_1083;
input  N_104;
input  N_179;
input  N_107;
input  N_105;
input  N_233;
input  N_194;
input  N_1080;
input  N_2522;
input  N_2784;
input  N_1007;
input  N_2532;
input  N_2778;
input  prdata_o195_0_a2_0;
input  prdata_o191;
input  N_1508;
input  N_2542;
input  N_2791;
input  N_2734;
input  N_2585;
input  prdata_o190;
input  N_2606;
input  N_2728;
input  N_54;
input  N_157;
input  N_151;
input  N_152;
input  N_153;
input  N_154;
input  N_155;
input  N_156;

    wire [0:0] iPSELS_raw_0_a2_0_0;
    wire GND, VCC;
    
    CFG2 #( .INIT(4'h4) )  \iPSELS_raw_0_a2_0_0[0]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR_13), .B(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx), .Y(
        iPSELS_raw_0_a2_0_0[0]));
    CFG4 #( .INIT(16'h1000) )  \iPSELS_raw_0_a2[1]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR_12), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR_11), .C(iPSELS_raw_0_a2_0_0[0]), 
        .D(MC_System_0_AMBA_SLAVE_1_PADDR_10), .Y(
        MC_System_0_AMBA_SLAVE_1_PSELx));
    CFG4 #( .INIT(16'h0010) )  \iPSELS_raw_0_a2[0]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR_12), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR_11), .C(iPSELS_raw_0_a2_0_0[0]), 
        .D(MC_System_0_AMBA_SLAVE_1_PADDR_10), .Y(
        MC_System_0_AMBA_SLAVE_0_PSELx));
    COREAPB3_MUXPTOB3 u_mux_p_to_b3 (.prdata_o_1_0({prdata_o_1_0[3]}), 
        .ADC_SCALING_0_ib_adc_o({ADC_SCALING_0_ib_adc_o[2]}), 
        .STEPPER_THETA_1_step_count_o({STEPPER_THETA_1_step_count_o[2]})
        , .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[2]}), 
        .adc_interface_0_result_ch2_o({adc_interface_0_result_ch2_o[2]})
        , .adc_measurements_0_adc_result_ch3_o({
        adc_measurements_0_adc_result_ch3_o[2]}), 
        .adc_measurements_0_adc_result_ch1_o({
        adc_measurements_0_adc_result_ch1_o[2]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_0(
        MC_System_0_AMBA_SLAVE_1_PADDR_0), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_2(
        MC_System_0_AMBA_SLAVE_1_PADDR_2), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_3(
        MC_System_0_AMBA_SLAVE_1_PADDR_3), .SEQ_CONTROLLER_1_state_o_0({
        SEQ_CONTROLLER_1_state_o_0[2]}), .prdata_o_1_0_a2_12_0({
        prdata_o_1_0_a2_12_0[15]}), .prdata_o_1_0_a2_10_0({
        prdata_o_1_0_a2_10_0[15]}), .FOC_TRANSFORMS_1_valpha_o({
        FOC_TRANSFORMS_1_valpha_o[11]}), .prdata_o_1_iv_12_1({
        prdata_o_1_iv_12_1[3]}), .FOC_TRANSFORMS_0_vbeta_o({
        FOC_TRANSFORMS_0_vbeta_o[11]}), .prdata_o_1_iv_12_0_2({
        prdata_o_1_iv_12_0_2[3]}), .SPEED_ID_IQ_PI_1_iq_pi_output_o({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]}), .FOC_TRANSFORMS_0_iq_o_0(
        FOC_TRANSFORMS_0_iq_o_0), .FOC_TRANSFORMS_0_iq_o_9(
        FOC_TRANSFORMS_0_iq_o_9), .FOC_TRANSFORMS_0_id_o_0(
        FOC_TRANSFORMS_0_id_o_0), .FOC_TRANSFORMS_0_id_o_9(
        FOC_TRANSFORMS_0_id_o_9), .prdata_o_1_iv_9({prdata_o_1_iv_9[0]})
        , .SPEED_ID_IQ_PI_1_id_pi_output_o_m({
        SPEED_ID_IQ_PI_1_id_pi_output_o_m[0]}), .prdata_o_1_0_1({
        prdata_o_1_0_1[16], prdata_o_1_0_1[15], prdata_o_1_0_1[14], 
        prdata_o_1_0_1[13], prdata_o_1_0_1[12]}), .prdata_o_1_0_2({
        prdata_o_1_0_2[16], prdata_o_1_0_2[15], prdata_o_1_0_2[14], 
        prdata_o_1_0_2[13], prdata_o_1_0_2[12]}), .prdata_o_1_0_0({
        prdata_o_1_0_0[16], prdata_o_1_0_0[15], prdata_o_1_0_0[14], 
        prdata_o_1_0_0[13], prdata_o_1_0_0[12]}), .prdata_o_1_3({
        prdata_o_1_3[3], prdata_o_1_3[2]}), .prdata_o_1_4({
        prdata_o_1_4[2]}), .prdata_o_1_2({prdata_o_1_2[3], 
        prdata_o_1_2[2]}), .prdata_o_1_24_3({prdata_o_1_24_3[1]}), 
        .prdata_o_1_24_4({prdata_o_1_24_4[1]}), .prdata_o_1_24_2({
        prdata_o_1_24_2[1]}), .prdata_o_1_12_2({prdata_o_1_12_2[11], 
        prdata_o_1_12_2[10], prdata_o_1_12_2[9], prdata_o_1_12_2[8], 
        prdata_o_1_12_2[7], prdata_o_1_12_2[6], prdata_o_1_12_2[5], 
        prdata_o_1_12_2[4]}), .prdata_o_1_12_3({prdata_o_1_12_3[11], 
        prdata_o_1_12_3[10], prdata_o_1_12_3[9], prdata_o_1_12_3[8], 
        prdata_o_1_12_3[7], prdata_o_1_12_3[6], prdata_o_1_12_3[5], 
        prdata_o_1_12_3[4]}), .prdata_o_1_12_1({prdata_o_1_12_1[11], 
        prdata_o_1_12_1[10], prdata_o_1_12_1[9], prdata_o_1_12_1[8], 
        prdata_o_1_12_1[7], prdata_o_1_12_1[6], prdata_o_1_12_1[5], 
        prdata_o_1_12_1[4]}), .prdata_o_1_0_iv_6({
        prdata_o_1_0_iv_6[16], prdata_o_1_0_iv_6[15], 
        prdata_o_1_0_iv_6[14], prdata_o_1_0_iv_6[13], 
        prdata_o_1_0_iv_6[12]}), .prdata_o_1_0_iv_7({
        prdata_o_1_0_iv_7[16], prdata_o_1_0_iv_7[15], 
        prdata_o_1_0_iv_7[14], prdata_o_1_0_iv_7[13], 
        prdata_o_1_0_iv_7[12]}), .prdata_o_1_0_iv_10({
        prdata_o_1_0_iv_10[10], prdata_o_1_0_iv_10[9], 
        prdata_o_1_0_iv_10[8], prdata_o_1_0_iv_10[7], 
        prdata_o_1_0_iv_10[6], prdata_o_1_0_iv_10[5], 
        prdata_o_1_0_iv_10[4]}), .prdata_o_1_0_iv_11({
        prdata_o_1_0_iv_11[10], prdata_o_1_0_iv_11[9], 
        prdata_o_1_0_iv_11[8], prdata_o_1_0_iv_11[7], 
        prdata_o_1_0_iv_11[6], prdata_o_1_0_iv_11[5], 
        prdata_o_1_0_iv_11[4]}), .prdata_o_1_iv_11_0(
        prdata_o_1_iv_11_0), .prdata_o_1_iv_11_1(prdata_o_1_iv_11_1), 
        .prdata_o_1_iv_11_3(prdata_o_1_iv_11_3), .prdata_o_1_iv_12({
        prdata_o_1_iv_12[3], prdata_o_1_iv_12[2], prdata_o_1_iv_12[1]})
        , .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3), 
        .MC_System_0_AMBA_SLAVE_0_PSELx(MC_System_0_AMBA_SLAVE_0_PSELx)
        , .N_2661(N_2661), .N_1077(N_1077), .N_2660(N_2660), .N_2785(
        N_2785), .N_1014(N_1014), .N_2779(N_2779), .N_2704(N_2704), 
        .N_184(N_184), .adc_channel_ch3_o_1_sqmuxa_0_a2_0_0(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .N_172(N_172), .N_174(
        N_174), .prdata_o197_0_a2_0_a2_0_out(
        prdata_o197_0_a2_0_a2_0_out), .prdata_o201_0_a2_0_0(
        prdata_o201_0_a2_0_0), .N_201(N_201), .N_193(N_193), .N_187(
        N_187), .N_2470(N_2470), .g2(g2), .g1_0(g1), 
        .MC_System_0_AMBA_SLAVE_1_PSELx(MC_System_0_AMBA_SLAVE_1_PSELx)
        , .N_106(N_106), .N_108(N_108), .N_202(N_202), .N_1083(N_1083), 
        .N_104(N_104), .N_179(N_179), .N_107(N_107), .N_105(N_105), 
        .N_233(N_233), .N_194(N_194), .N_1080(N_1080), .N_2522(N_2522), 
        .N_2784(N_2784), .N_1007(N_1007), .N_2532(N_2532), .N_2778(
        N_2778), .prdata_o195_0_a2_0(prdata_o195_0_a2_0), .prdata_o191(
        prdata_o191), .N_1508(N_1508), .N_2542(N_2542), .N_2791(N_2791)
        , .N_2734(N_2734), .N_2585(N_2585), .prdata_o190(prdata_o190), 
        .N_2606(N_2606), .N_2728(N_2728), .N_54(N_54), .N_157(N_157), 
        .N_151(N_151), .N_152(N_152), .N_153(N_153), .N_154(N_154), 
        .N_155(N_155), .N_156(N_156));
    VCC VCC_Z (.Y(VCC));
    GND GND_Z (.Y(GND));
    
endmodule


module MC_System_sb_CCC_0_FCCC(
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       MC_System_0_FAB_CCC_GL1,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output MC_System_0_FIC_0_LOCK;
output MC_System_0_FIC_0_CLK;
output MC_System_0_FAB_CCC_GL1;
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire [7:0] PRDATA;
    wire LOCK, GL0_net, GL1_net, Y0, Y1, Y2, Y3, BUSY, VCC, GND, GL2, 
        GL3;
    
    CLKINT GL1_INST (.A(GL1_net), .Y(MC_System_0_FAB_CCC_GL1));
    VCC VCC_Z (.Y(VCC));
    CLKINT GL0_INST (.A(GL0_net), .Y(MC_System_0_FIC_0_CLK));
    CCC #( .INIT(210'h0000007FB8000044D64000318C6307C1F18C61EC0404040400301)
        , .VCOFREQUENCY(800.000000) )  CCC_INST (.Y0(Y0), .Y1(Y1), .Y2(
        Y2), .Y3(Y3), .PRDATA({PRDATA[7], PRDATA[6], PRDATA[5], 
        PRDATA[4], PRDATA[3], PRDATA[2], PRDATA[1], PRDATA[0]}), .LOCK(
        LOCK), .BUSY(BUSY), .CLK0(VCC), .CLK1(VCC), .CLK2(VCC), .CLK3(
        VCC), .NGMUX0_SEL(GND), .NGMUX1_SEL(GND), .NGMUX2_SEL(GND), 
        .NGMUX3_SEL(GND), .NGMUX0_HOLD_N(VCC), .NGMUX1_HOLD_N(VCC), 
        .NGMUX2_HOLD_N(VCC), .NGMUX3_HOLD_N(VCC), .NGMUX0_ARST_N(VCC), 
        .NGMUX1_ARST_N(VCC), .NGMUX2_ARST_N(VCC), .NGMUX3_ARST_N(VCC), 
        .PLL_BYPASS_N(VCC), .PLL_ARST_N(VCC), .PLL_POWERDOWN_N(VCC), 
        .GPD0_ARST_N(VCC), .GPD1_ARST_N(VCC), .GPD2_ARST_N(VCC), 
        .GPD3_ARST_N(VCC), .PRESET_N(GND), .PCLK(VCC), .PSEL(VCC), 
        .PENABLE(VCC), .PWRITE(VCC), .PADDR({VCC, VCC, VCC, VCC, VCC, 
        VCC}), .PWDATA({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}), 
        .CLK0_PAD(GND), .CLK1_PAD(GND), .CLK2_PAD(GND), .CLK3_PAD(GND), 
        .GL0(GL0_net), .GL1(GL1_net), .GL2(GL2), .GL3(GL3), 
        .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND), .XTLOSC(GND));
    GND GND_Z (.Y(GND));
    CLKINT CCC_INST_RNI2QPF (.A(LOCK), .Y(MC_System_0_FIC_0_LOCK));
    
endmodule


module MC_System_sb_MSS(
       USB_ULPI_DATA,
       MC_System_0_AMBA_SLAVE_1_PADDR_0,
       MC_System_0_AMBA_SLAVE_1_PADDR_1,
       MC_System_0_AMBA_SLAVE_1_PADDR_2,
       MC_System_0_AMBA_SLAVE_1_PADDR_3,
       MC_System_0_AMBA_SLAVE_1_PADDR_4,
       MC_System_0_AMBA_SLAVE_1_PADDR_5,
       MC_System_0_AMBA_SLAVE_1_PADDR_6,
       MC_System_0_AMBA_SLAVE_1_PADDR_7,
       MC_System_0_AMBA_SLAVE_1_PADDR_8,
       MC_System_0_AMBA_SLAVE_1_PADDR_9,
       MC_System_0_AMBA_SLAVE_1_PADDR_10,
       MC_System_0_AMBA_SLAVE_1_PADDR_11,
       MC_System_0_AMBA_SLAVE_1_PADDR_12,
       MC_System_0_AMBA_SLAVE_1_PADDR_13,
       MC_System_0_AMBA_SLAVE_1_PADDR_14,
       MC_System_0_AMBA_SLAVE_1_PADDR_15,
       MC_System_0_AMBA_SLAVE_1_PWDATA_0,
       MC_System_0_AMBA_SLAVE_1_PWDATA_1,
       MC_System_0_AMBA_SLAVE_1_PWDATA_2,
       MC_System_0_AMBA_SLAVE_1_PWDATA_3,
       MC_System_0_AMBA_SLAVE_1_PWDATA_4,
       MC_System_0_AMBA_SLAVE_1_PWDATA_5,
       MC_System_0_AMBA_SLAVE_1_PWDATA_6,
       MC_System_0_AMBA_SLAVE_1_PWDATA_7,
       MC_System_0_AMBA_SLAVE_1_PWDATA_8,
       MC_System_0_AMBA_SLAVE_1_PWDATA_9,
       MC_System_0_AMBA_SLAVE_1_PWDATA_10,
       MC_System_0_AMBA_SLAVE_1_PWDATA_11,
       MC_System_0_AMBA_SLAVE_1_PWDATA_12,
       MC_System_0_AMBA_SLAVE_1_PWDATA_13,
       MC_System_0_AMBA_SLAVE_1_PWDATA_14,
       MC_System_0_AMBA_SLAVE_1_PWDATA_15,
       MC_System_0_AMBA_SLAVE_1_PWDATA_16,
       MC_System_0_AMBA_SLAVE_1_PWDATA_17,
       MC_System_0_AMBA_SLAVE_1_PWDATA_18,
       MC_System_0_AMBA_SLAVE_1_PWDATA_19,
       MC_System_0_AMBA_SLAVE_1_PWDATA_20,
       MC_System_0_AMBA_SLAVE_1_PWDATA_21,
       MC_System_0_AMBA_SLAVE_1_PWDATA_22,
       MC_System_0_AMBA_SLAVE_1_PWDATA_23,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31,
       USB_ULPI_XCLK,
       USB_ULPI_STP,
       USB_ULPI_NXT,
       USB_ULPI_DIR,
       MC_System_0_AMBA_SLAVE_1_PENABLE,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx,
       MC_System_0_AMBA_SLAVE_1_PWRITE,
       GPIO_0_M2F_c,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK
    );
inout  [7:0] USB_ULPI_DATA;
output MC_System_0_AMBA_SLAVE_1_PADDR_0;
output MC_System_0_AMBA_SLAVE_1_PADDR_1;
output MC_System_0_AMBA_SLAVE_1_PADDR_2;
output MC_System_0_AMBA_SLAVE_1_PADDR_3;
output MC_System_0_AMBA_SLAVE_1_PADDR_4;
output MC_System_0_AMBA_SLAVE_1_PADDR_5;
output MC_System_0_AMBA_SLAVE_1_PADDR_6;
output MC_System_0_AMBA_SLAVE_1_PADDR_7;
output MC_System_0_AMBA_SLAVE_1_PADDR_8;
output MC_System_0_AMBA_SLAVE_1_PADDR_9;
output MC_System_0_AMBA_SLAVE_1_PADDR_10;
output MC_System_0_AMBA_SLAVE_1_PADDR_11;
output MC_System_0_AMBA_SLAVE_1_PADDR_12;
output MC_System_0_AMBA_SLAVE_1_PADDR_13;
output MC_System_0_AMBA_SLAVE_1_PADDR_14;
output MC_System_0_AMBA_SLAVE_1_PADDR_15;
output MC_System_0_AMBA_SLAVE_1_PWDATA_0;
output MC_System_0_AMBA_SLAVE_1_PWDATA_1;
output MC_System_0_AMBA_SLAVE_1_PWDATA_2;
output MC_System_0_AMBA_SLAVE_1_PWDATA_3;
output MC_System_0_AMBA_SLAVE_1_PWDATA_4;
output MC_System_0_AMBA_SLAVE_1_PWDATA_5;
output MC_System_0_AMBA_SLAVE_1_PWDATA_6;
output MC_System_0_AMBA_SLAVE_1_PWDATA_7;
output MC_System_0_AMBA_SLAVE_1_PWDATA_8;
output MC_System_0_AMBA_SLAVE_1_PWDATA_9;
output MC_System_0_AMBA_SLAVE_1_PWDATA_10;
output MC_System_0_AMBA_SLAVE_1_PWDATA_11;
output MC_System_0_AMBA_SLAVE_1_PWDATA_12;
output MC_System_0_AMBA_SLAVE_1_PWDATA_13;
output MC_System_0_AMBA_SLAVE_1_PWDATA_14;
output MC_System_0_AMBA_SLAVE_1_PWDATA_15;
output MC_System_0_AMBA_SLAVE_1_PWDATA_16;
output MC_System_0_AMBA_SLAVE_1_PWDATA_17;
output MC_System_0_AMBA_SLAVE_1_PWDATA_18;
output MC_System_0_AMBA_SLAVE_1_PWDATA_19;
output MC_System_0_AMBA_SLAVE_1_PWDATA_20;
output MC_System_0_AMBA_SLAVE_1_PWDATA_21;
output MC_System_0_AMBA_SLAVE_1_PWDATA_22;
output MC_System_0_AMBA_SLAVE_1_PWDATA_23;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31;
input  USB_ULPI_XCLK;
output USB_ULPI_STP;
input  USB_ULPI_NXT;
input  USB_ULPI_DIR;
output MC_System_0_AMBA_SLAVE_1_PENABLE;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx;
output MC_System_0_AMBA_SLAVE_1_PWRITE;
output GPIO_0_M2F_c;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;

    wire [7:0] EDAC_ERROR;
    wire [31:0] F_FM0_RDATA;
    wire [31:16] MC_System_0_AMBA_SLAVE_1_PADDR;
    wire [1:0] F_HM0_SIZE;
    wire [31:24] MC_System_0_AMBA_SLAVE_1_PWDATA;
    wire [1:0] FAB_OPMODE;
    wire [3:0] FAB_VCONTROL;
    wire [1:0] FAB_XCVRSEL;
    wire [7:0] FAB_XDATAOUT;
    wire [1:0] FIC32_0_MASTER;
    wire [1:0] FIC32_1_MASTER;
    wire [15:0] H2F_INTERRUPT;
    wire [15:2] PER2_FABRIC_PADDR;
    wire [31:0] PER2_FABRIC_PWDATA;
    wire [9:0] TCGF;
    wire [3:0] TRACEDATA;
    wire [3:0] TXD_RIF;
    wire [7:0] TXDF;
    wire [3:0] F_BID;
    wire [1:0] F_BRESP_HRESP0;
    wire [63:0] F_RDATA_HRDATA01;
    wire [3:0] F_RID;
    wire [1:0] F_RRESP_HRESP1;
    wire [15:0] MDDR_FABRIC_PRDATA;
    wire [15:0] DRAM_ADDR;
    wire [2:0] DRAM_BA;
    wire [2:0] DRAM_DM_RDQS_OUT;
    wire [17:0] DRAM_DQ_OUT;
    wire [2:0] DRAM_DQS_OUT;
    wire [1:0] DRAM_FIFO_WE_OUT;
    wire [2:0] DM_OE;
    wire [17:0] DRAM_DQ_OE;
    wire [2:0] DRAM_DQS_OE;
    wire USB_ULPI_XCLK_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT, 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE, 
        USB_ULPI_NXT_PAD_Y, USB_ULPI_DIR_PAD_Y, USB_ULPI_DATA_7_PAD_Y, 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT, 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE, 
        USB_ULPI_DATA_6_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT, 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE, USB_ULPI_DATA_5_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT, 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE, USB_ULPI_DATA_4_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT, 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE, USB_ULPI_DATA_3_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT, 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE, 
        USB_ULPI_DATA_2_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT, 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE, 
        USB_ULPI_DATA_1_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT, 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE, 
        USB_ULPI_DATA_0_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT, 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE, 
        CAN_RXBUS_MGPIO3A_H2F_A, CAN_RXBUS_MGPIO3A_H2F_B, 
        CAN_TX_EBL_MGPIO4A_H2F_A, CAN_TX_EBL_MGPIO4A_H2F_B, 
        CAN_TXBUS_MGPIO2A_H2F_A, CAN_TXBUS_MGPIO2A_H2F_B, 
        CLK_CONFIG_APB, COMMS_INT, 
        MC_System_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N, F_FM0_READYOUT, 
        F_FM0_RESP, F_HM0_TRANS1, FAB_CHRGVBUS, FAB_DISCHRGVBUS, 
        FAB_DMPULLDOWN, FAB_DPPULLDOWN, FAB_DRVVBUS, FAB_IDPULLUP, 
        FAB_SUSPENDM, FAB_TERMSEL, FAB_TXVALID, FAB_VCONTROLLOADM, 
        FACC_GLMUX_SEL, MC_System_sb_MSS_TMP_0_MSS_RESET_N_M2F, 
        GTX_CLK, H2F_NMI, H2FCALIB, I2C0_SCL_MGPIO31B_H2F_A, 
        I2C0_SCL_MGPIO31B_H2F_B, I2C0_SDA_MGPIO30B_H2F_A, 
        I2C0_SDA_MGPIO30B_H2F_B, I2C1_SCL_MGPIO1A_H2F_A, 
        I2C1_SCL_MGPIO1A_H2F_B, I2C1_SDA_MGPIO0A_H2F_A, MDCF, MDOENF, 
        MDOF, MMUART0_CTS_MGPIO19B_H2F_A, MMUART0_CTS_MGPIO19B_H2F_B, 
        MMUART0_DCD_MGPIO22B_H2F_A, MMUART0_DCD_MGPIO22B_H2F_B, 
        MMUART0_DSR_MGPIO20B_H2F_A, MMUART0_DSR_MGPIO20B_H2F_B, 
        MMUART0_DTR_MGPIO18B_H2F_A, MMUART0_DTR_MGPIO18B_H2F_B, 
        MMUART0_RI_MGPIO21B_H2F_A, MMUART0_RI_MGPIO21B_H2F_B, 
        MMUART0_RTS_MGPIO17B_H2F_A, MMUART0_RTS_MGPIO17B_H2F_B, 
        MMUART0_RXD_MGPIO28B_H2F_A, MMUART0_RXD_MGPIO28B_H2F_B, 
        MMUART0_SCK_MGPIO29B_H2F_A, MMUART0_SCK_MGPIO29B_H2F_B, 
        MMUART0_TXD_MGPIO27B_H2F_A, MMUART0_TXD_MGPIO27B_H2F_B, 
        MMUART1_DTR_MGPIO12B_H2F_A, MMUART1_RTS_MGPIO11B_H2F_A, 
        MMUART1_RTS_MGPIO11B_H2F_B, MMUART1_RXD_MGPIO26B_H2F_A, 
        MMUART1_RXD_MGPIO26B_H2F_B, MMUART1_SCK_MGPIO25B_H2F_A, 
        MMUART1_SCK_MGPIO25B_H2F_B, MMUART1_TXD_MGPIO24B_H2F_A, 
        MMUART1_TXD_MGPIO24B_H2F_B, MPLL_LOCK, PER2_FABRIC_PENABLE, 
        PER2_FABRIC_PSEL, PER2_FABRIC_PWRITE, RTC_MATCH, SLEEPDEEP, 
        SLEEPHOLDACK, SLEEPING, SMBALERT_NO0, SMBALERT_NO1, SMBSUS_NO0, 
        SMBSUS_NO1, SPI0_CLK_OUT, SPI0_SDI_MGPIO5A_H2F_A, 
        SPI0_SDI_MGPIO5A_H2F_B, SPI0_SDO_MGPIO6A_H2F_A, 
        SPI0_SDO_MGPIO6A_H2F_B, SPI0_SS0_MGPIO7A_H2F_A, 
        SPI0_SS0_MGPIO7A_H2F_B, SPI0_SS1_MGPIO8A_H2F_A, 
        SPI0_SS1_MGPIO8A_H2F_B, SPI0_SS2_MGPIO9A_H2F_A, 
        SPI0_SS2_MGPIO9A_H2F_B, SPI0_SS3_MGPIO10A_H2F_A, 
        SPI0_SS3_MGPIO10A_H2F_B, SPI0_SS4_MGPIO19A_H2F_A, 
        SPI0_SS5_MGPIO20A_H2F_A, SPI0_SS6_MGPIO21A_H2F_A, 
        SPI0_SS7_MGPIO22A_H2F_A, SPI1_CLK_OUT, SPI1_SDI_MGPIO11A_H2F_A, 
        SPI1_SDI_MGPIO11A_H2F_B, SPI1_SDO_MGPIO12A_H2F_A, 
        SPI1_SDO_MGPIO12A_H2F_B, SPI1_SS0_MGPIO13A_H2F_A, 
        SPI1_SS0_MGPIO13A_H2F_B, SPI1_SS1_MGPIO14A_H2F_A, 
        SPI1_SS1_MGPIO14A_H2F_B, SPI1_SS2_MGPIO15A_H2F_A, 
        SPI1_SS2_MGPIO15A_H2F_B, SPI1_SS3_MGPIO16A_H2F_A, 
        SPI1_SS3_MGPIO16A_H2F_B, SPI1_SS4_MGPIO17A_H2F_A, 
        SPI1_SS5_MGPIO18A_H2F_A, SPI1_SS6_MGPIO23A_H2F_A, 
        SPI1_SS7_MGPIO24A_H2F_A, TRACECLK, TX_CLK, TX_ENF, TX_ERRF, 
        TXCTL_EN_RIF, TXEV, WDOGTIMEOUT, F_ARREADY_HREADYOUT1, 
        F_AWREADY_HREADYOUT0, F_BVALID, F_RLAST, F_RVALID, F_WREADY, 
        MDDR_FABRIC_PREADY, MDDR_FABRIC_PSLVERR, VCC, GND, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT, DRAM_CASN, DRAM_CKE, 
        DRAM_CLK, DRAM_CSN, DRAM_ODT, DRAM_RASN, DRAM_RSTN, DRAM_WEN, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OUT, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT, MMUART0_DCD_MGPIO22B_OUT, 
        MMUART0_DSR_MGPIO20B_OUT, MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT, 
        MMUART0_RI_MGPIO21B_OUT, MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT, RGMII_MDC_RMII_MDC_OUT, 
        RGMII_RX_CLK_OUT, RGMII_TX_CLK_OUT, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT, SPI0_SCK_USBA_XCLK_OUT, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OUT, SPI0_SDO_USBA_STP_MGPIO6A_OUT, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT, SPI0_SS1_USBA_DATA5_MGPIO8A_OUT, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT, SPI1_SCK_OUT, 
        SPI1_SDI_MGPIO11A_OUT, SPI1_SDO_MGPIO12A_OUT, 
        SPI1_SS0_MGPIO13A_OUT, SPI1_SS1_MGPIO14A_OUT, 
        SPI1_SS2_MGPIO15A_OUT, SPI1_SS3_MGPIO16A_OUT, 
        SPI1_SS4_MGPIO17A_OUT, SPI1_SS5_MGPIO18A_OUT, 
        SPI1_SS6_MGPIO23A_OUT, SPI1_SS7_MGPIO24A_OUT, USBC_XCLK_OUT, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE, I2C1_SDA_USBA_DATA3_MGPIO0A_OE, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE, MMUART0_DCD_MGPIO22B_OE, 
        MMUART0_DSR_MGPIO20B_OE, MMUART0_DTR_USBC_DATA6_MGPIO18B_OE, 
        MMUART0_RI_MGPIO21B_OE, MMUART0_RTS_USBC_DATA5_MGPIO17B_OE, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE, RGMII_MDC_RMII_MDC_OE, 
        RGMII_RX_CLK_OE, RGMII_TX_CLK_OE, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE, SPI0_SCK_USBA_XCLK_OE, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OE, SPI0_SDO_USBA_STP_MGPIO6A_OE, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE, SPI0_SS1_USBA_DATA5_MGPIO8A_OE, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE, SPI1_SCK_OE, 
        SPI1_SDI_MGPIO11A_OE, SPI1_SDO_MGPIO12A_OE, 
        SPI1_SS0_MGPIO13A_OE, SPI1_SS1_MGPIO14A_OE, 
        SPI1_SS2_MGPIO15A_OE, SPI1_SS3_MGPIO16A_OE, 
        SPI1_SS4_MGPIO17A_OE, SPI1_SS5_MGPIO18A_OE, 
        SPI1_SS6_MGPIO23A_OE, SPI1_SS7_MGPIO24A_OE, USBC_XCLK_OE;
    
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_5_PAD (.PAD(USB_ULPI_DATA[5]), 
        .D(MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT), .E(
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE), .Y(
        USB_ULPI_DATA_5_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_4_PAD (.PAD(USB_ULPI_DATA[4]), 
        .D(MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT), .E(
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE), .Y(
        USB_ULPI_DATA_4_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_7_PAD (.PAD(USB_ULPI_DATA[7]), 
        .D(MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT), .E(
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE), .Y(
        USB_ULPI_DATA_7_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_3_PAD (.PAD(USB_ULPI_DATA[3]), 
        .D(MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT), .E(
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE), .Y(
        USB_ULPI_DATA_3_PAD_Y));
    INBUF #( .IOSTD("") )  USB_ULPI_NXT_PAD (.PAD(USB_ULPI_NXT), .Y(
        USB_ULPI_NXT_PAD_Y));
    GND GND_Z (.Y(GND));
    INBUF #( .IOSTD("") )  USB_ULPI_XCLK_PAD (.PAD(USB_ULPI_XCLK), .Y(
        USB_ULPI_XCLK_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_6_PAD (.PAD(USB_ULPI_DATA[6]), 
        .D(MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT), .E(
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE), .Y(
        USB_ULPI_DATA_6_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_2_PAD (.PAD(USB_ULPI_DATA[2]), 
        .D(MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT), .E(
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE), .Y(
        USB_ULPI_DATA_2_PAD_Y));
    INBUF #( .IOSTD("") )  USB_ULPI_DIR_PAD (.PAD(USB_ULPI_DIR), .Y(
        USB_ULPI_DIR_PAD_Y));
    MSS_010 #( .INIT(1438'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000120481204812048120D8120D8120E00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104003FFFFE4000000000001100000000F0F01C00000182CFFC010842108421000001FE34001FF8000000400000000020091007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'b11111111111111111111111111111111111111111111111111111111)
        , .MEMORYFILE("ENVM_init.mem"), .RTC_MAIN_XTL_FREQ(0.000000), .RTC_MAIN_XTL_MODE("")
        , .DDR_CLK_FREQ(0.000000) )  MSS_ADLIB_INST (
        .CAN_RXBUS_MGPIO3A_H2F_A(CAN_RXBUS_MGPIO3A_H2F_A), 
        .CAN_RXBUS_MGPIO3A_H2F_B(CAN_RXBUS_MGPIO3A_H2F_B), 
        .CAN_TX_EBL_MGPIO4A_H2F_A(CAN_TX_EBL_MGPIO4A_H2F_A), 
        .CAN_TX_EBL_MGPIO4A_H2F_B(CAN_TX_EBL_MGPIO4A_H2F_B), 
        .CAN_TXBUS_MGPIO2A_H2F_A(CAN_TXBUS_MGPIO2A_H2F_A), 
        .CAN_TXBUS_MGPIO2A_H2F_B(CAN_TXBUS_MGPIO2A_H2F_B), 
        .CLK_CONFIG_APB(CLK_CONFIG_APB), .COMMS_INT(COMMS_INT), 
        .CONFIG_PRESET_N(MC_System_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N), 
        .EDAC_ERROR({EDAC_ERROR[7], EDAC_ERROR[6], EDAC_ERROR[5], 
        EDAC_ERROR[4], EDAC_ERROR[3], EDAC_ERROR[2], EDAC_ERROR[1], 
        EDAC_ERROR[0]}), .F_FM0_RDATA({F_FM0_RDATA[31], 
        F_FM0_RDATA[30], F_FM0_RDATA[29], F_FM0_RDATA[28], 
        F_FM0_RDATA[27], F_FM0_RDATA[26], F_FM0_RDATA[25], 
        F_FM0_RDATA[24], F_FM0_RDATA[23], F_FM0_RDATA[22], 
        F_FM0_RDATA[21], F_FM0_RDATA[20], F_FM0_RDATA[19], 
        F_FM0_RDATA[18], F_FM0_RDATA[17], F_FM0_RDATA[16], 
        F_FM0_RDATA[15], F_FM0_RDATA[14], F_FM0_RDATA[13], 
        F_FM0_RDATA[12], F_FM0_RDATA[11], F_FM0_RDATA[10], 
        F_FM0_RDATA[9], F_FM0_RDATA[8], F_FM0_RDATA[7], F_FM0_RDATA[6], 
        F_FM0_RDATA[5], F_FM0_RDATA[4], F_FM0_RDATA[3], F_FM0_RDATA[2], 
        F_FM0_RDATA[1], F_FM0_RDATA[0]}), .F_FM0_READYOUT(
        F_FM0_READYOUT), .F_FM0_RESP(F_FM0_RESP), .F_HM0_ADDR({
        MC_System_0_AMBA_SLAVE_1_PADDR[31], 
        MC_System_0_AMBA_SLAVE_1_PADDR[30], 
        MC_System_0_AMBA_SLAVE_1_PADDR[29], 
        MC_System_0_AMBA_SLAVE_1_PADDR[28], 
        MC_System_0_AMBA_SLAVE_1_PADDR[27], 
        MC_System_0_AMBA_SLAVE_1_PADDR[26], 
        MC_System_0_AMBA_SLAVE_1_PADDR[25], 
        MC_System_0_AMBA_SLAVE_1_PADDR[24], 
        MC_System_0_AMBA_SLAVE_1_PADDR[23], 
        MC_System_0_AMBA_SLAVE_1_PADDR[22], 
        MC_System_0_AMBA_SLAVE_1_PADDR[21], 
        MC_System_0_AMBA_SLAVE_1_PADDR[20], 
        MC_System_0_AMBA_SLAVE_1_PADDR[19], 
        MC_System_0_AMBA_SLAVE_1_PADDR[18], 
        MC_System_0_AMBA_SLAVE_1_PADDR[17], 
        MC_System_0_AMBA_SLAVE_1_PADDR[16], 
        MC_System_0_AMBA_SLAVE_1_PADDR_15, 
        MC_System_0_AMBA_SLAVE_1_PADDR_14, 
        MC_System_0_AMBA_SLAVE_1_PADDR_13, 
        MC_System_0_AMBA_SLAVE_1_PADDR_12, 
        MC_System_0_AMBA_SLAVE_1_PADDR_11, 
        MC_System_0_AMBA_SLAVE_1_PADDR_10, 
        MC_System_0_AMBA_SLAVE_1_PADDR_9, 
        MC_System_0_AMBA_SLAVE_1_PADDR_8, 
        MC_System_0_AMBA_SLAVE_1_PADDR_7, 
        MC_System_0_AMBA_SLAVE_1_PADDR_6, 
        MC_System_0_AMBA_SLAVE_1_PADDR_5, 
        MC_System_0_AMBA_SLAVE_1_PADDR_4, 
        MC_System_0_AMBA_SLAVE_1_PADDR_3, 
        MC_System_0_AMBA_SLAVE_1_PADDR_2, 
        MC_System_0_AMBA_SLAVE_1_PADDR_1, 
        MC_System_0_AMBA_SLAVE_1_PADDR_0}), .F_HM0_ENABLE(
        MC_System_0_AMBA_SLAVE_1_PENABLE), .F_HM0_SEL(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx), .F_HM0_SIZE({
        F_HM0_SIZE[1], F_HM0_SIZE[0]}), .F_HM0_TRANS1(F_HM0_TRANS1), 
        .F_HM0_WDATA({MC_System_0_AMBA_SLAVE_1_PWDATA[31], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[30], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[29], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[28], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[27], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[26], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[25], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[24], 
        MC_System_0_AMBA_SLAVE_1_PWDATA_23, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_22, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_21, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_20, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_19, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_18, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_17, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_16, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_15, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_14, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_13, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_12, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_11, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_10, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_9, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_8, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_7, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_6, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_5, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_4, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_3, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_2, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_1, 
        MC_System_0_AMBA_SLAVE_1_PWDATA_0}), .F_HM0_WRITE(
        MC_System_0_AMBA_SLAVE_1_PWRITE), .FAB_CHRGVBUS(FAB_CHRGVBUS), 
        .FAB_DISCHRGVBUS(FAB_DISCHRGVBUS), .FAB_DMPULLDOWN(
        FAB_DMPULLDOWN), .FAB_DPPULLDOWN(FAB_DPPULLDOWN), .FAB_DRVVBUS(
        FAB_DRVVBUS), .FAB_IDPULLUP(FAB_IDPULLUP), .FAB_OPMODE({
        FAB_OPMODE[1], FAB_OPMODE[0]}), .FAB_SUSPENDM(FAB_SUSPENDM), 
        .FAB_TERMSEL(FAB_TERMSEL), .FAB_TXVALID(FAB_TXVALID), 
        .FAB_VCONTROL({FAB_VCONTROL[3], FAB_VCONTROL[2], 
        FAB_VCONTROL[1], FAB_VCONTROL[0]}), .FAB_VCONTROLLOADM(
        FAB_VCONTROLLOADM), .FAB_XCVRSEL({FAB_XCVRSEL[1], 
        FAB_XCVRSEL[0]}), .FAB_XDATAOUT({FAB_XDATAOUT[7], 
        FAB_XDATAOUT[6], FAB_XDATAOUT[5], FAB_XDATAOUT[4], 
        FAB_XDATAOUT[3], FAB_XDATAOUT[2], FAB_XDATAOUT[1], 
        FAB_XDATAOUT[0]}), .FACC_GLMUX_SEL(FACC_GLMUX_SEL), 
        .FIC32_0_MASTER({FIC32_0_MASTER[1], FIC32_0_MASTER[0]}), 
        .FIC32_1_MASTER({FIC32_1_MASTER[1], FIC32_1_MASTER[0]}), 
        .FPGA_RESET_N(MC_System_sb_MSS_TMP_0_MSS_RESET_N_M2F), 
        .GTX_CLK(GTX_CLK), .H2F_INTERRUPT({H2F_INTERRUPT[15], 
        H2F_INTERRUPT[14], H2F_INTERRUPT[13], H2F_INTERRUPT[12], 
        H2F_INTERRUPT[11], H2F_INTERRUPT[10], H2F_INTERRUPT[9], 
        H2F_INTERRUPT[8], H2F_INTERRUPT[7], H2F_INTERRUPT[6], 
        H2F_INTERRUPT[5], H2F_INTERRUPT[4], H2F_INTERRUPT[3], 
        H2F_INTERRUPT[2], H2F_INTERRUPT[1], H2F_INTERRUPT[0]}), 
        .H2F_NMI(H2F_NMI), .H2FCALIB(H2FCALIB), 
        .I2C0_SCL_MGPIO31B_H2F_A(I2C0_SCL_MGPIO31B_H2F_A), 
        .I2C0_SCL_MGPIO31B_H2F_B(I2C0_SCL_MGPIO31B_H2F_B), 
        .I2C0_SDA_MGPIO30B_H2F_A(I2C0_SDA_MGPIO30B_H2F_A), 
        .I2C0_SDA_MGPIO30B_H2F_B(I2C0_SDA_MGPIO30B_H2F_B), 
        .I2C1_SCL_MGPIO1A_H2F_A(I2C1_SCL_MGPIO1A_H2F_A), 
        .I2C1_SCL_MGPIO1A_H2F_B(I2C1_SCL_MGPIO1A_H2F_B), 
        .I2C1_SDA_MGPIO0A_H2F_A(I2C1_SDA_MGPIO0A_H2F_A), 
        .I2C1_SDA_MGPIO0A_H2F_B(GPIO_0_M2F_c), .MDCF(MDCF), .MDOENF(
        MDOENF), .MDOF(MDOF), .MMUART0_CTS_MGPIO19B_H2F_A(
        MMUART0_CTS_MGPIO19B_H2F_A), .MMUART0_CTS_MGPIO19B_H2F_B(
        MMUART0_CTS_MGPIO19B_H2F_B), .MMUART0_DCD_MGPIO22B_H2F_A(
        MMUART0_DCD_MGPIO22B_H2F_A), .MMUART0_DCD_MGPIO22B_H2F_B(
        MMUART0_DCD_MGPIO22B_H2F_B), .MMUART0_DSR_MGPIO20B_H2F_A(
        MMUART0_DSR_MGPIO20B_H2F_A), .MMUART0_DSR_MGPIO20B_H2F_B(
        MMUART0_DSR_MGPIO20B_H2F_B), .MMUART0_DTR_MGPIO18B_H2F_A(
        MMUART0_DTR_MGPIO18B_H2F_A), .MMUART0_DTR_MGPIO18B_H2F_B(
        MMUART0_DTR_MGPIO18B_H2F_B), .MMUART0_RI_MGPIO21B_H2F_A(
        MMUART0_RI_MGPIO21B_H2F_A), .MMUART0_RI_MGPIO21B_H2F_B(
        MMUART0_RI_MGPIO21B_H2F_B), .MMUART0_RTS_MGPIO17B_H2F_A(
        MMUART0_RTS_MGPIO17B_H2F_A), .MMUART0_RTS_MGPIO17B_H2F_B(
        MMUART0_RTS_MGPIO17B_H2F_B), .MMUART0_RXD_MGPIO28B_H2F_A(
        MMUART0_RXD_MGPIO28B_H2F_A), .MMUART0_RXD_MGPIO28B_H2F_B(
        MMUART0_RXD_MGPIO28B_H2F_B), .MMUART0_SCK_MGPIO29B_H2F_A(
        MMUART0_SCK_MGPIO29B_H2F_A), .MMUART0_SCK_MGPIO29B_H2F_B(
        MMUART0_SCK_MGPIO29B_H2F_B), .MMUART0_TXD_MGPIO27B_H2F_A(
        MMUART0_TXD_MGPIO27B_H2F_A), .MMUART0_TXD_MGPIO27B_H2F_B(
        MMUART0_TXD_MGPIO27B_H2F_B), .MMUART1_DTR_MGPIO12B_H2F_A(
        MMUART1_DTR_MGPIO12B_H2F_A), .MMUART1_RTS_MGPIO11B_H2F_A(
        MMUART1_RTS_MGPIO11B_H2F_A), .MMUART1_RTS_MGPIO11B_H2F_B(
        MMUART1_RTS_MGPIO11B_H2F_B), .MMUART1_RXD_MGPIO26B_H2F_A(
        MMUART1_RXD_MGPIO26B_H2F_A), .MMUART1_RXD_MGPIO26B_H2F_B(
        MMUART1_RXD_MGPIO26B_H2F_B), .MMUART1_SCK_MGPIO25B_H2F_A(
        MMUART1_SCK_MGPIO25B_H2F_A), .MMUART1_SCK_MGPIO25B_H2F_B(
        MMUART1_SCK_MGPIO25B_H2F_B), .MMUART1_TXD_MGPIO24B_H2F_A(
        MMUART1_TXD_MGPIO24B_H2F_A), .MMUART1_TXD_MGPIO24B_H2F_B(
        MMUART1_TXD_MGPIO24B_H2F_B), .MPLL_LOCK(MPLL_LOCK), 
        .PER2_FABRIC_PADDR({PER2_FABRIC_PADDR[15], 
        PER2_FABRIC_PADDR[14], PER2_FABRIC_PADDR[13], 
        PER2_FABRIC_PADDR[12], PER2_FABRIC_PADDR[11], 
        PER2_FABRIC_PADDR[10], PER2_FABRIC_PADDR[9], 
        PER2_FABRIC_PADDR[8], PER2_FABRIC_PADDR[7], 
        PER2_FABRIC_PADDR[6], PER2_FABRIC_PADDR[5], 
        PER2_FABRIC_PADDR[4], PER2_FABRIC_PADDR[3], 
        PER2_FABRIC_PADDR[2]}), .PER2_FABRIC_PENABLE(
        PER2_FABRIC_PENABLE), .PER2_FABRIC_PSEL(PER2_FABRIC_PSEL), 
        .PER2_FABRIC_PWDATA({PER2_FABRIC_PWDATA[31], 
        PER2_FABRIC_PWDATA[30], PER2_FABRIC_PWDATA[29], 
        PER2_FABRIC_PWDATA[28], PER2_FABRIC_PWDATA[27], 
        PER2_FABRIC_PWDATA[26], PER2_FABRIC_PWDATA[25], 
        PER2_FABRIC_PWDATA[24], PER2_FABRIC_PWDATA[23], 
        PER2_FABRIC_PWDATA[22], PER2_FABRIC_PWDATA[21], 
        PER2_FABRIC_PWDATA[20], PER2_FABRIC_PWDATA[19], 
        PER2_FABRIC_PWDATA[18], PER2_FABRIC_PWDATA[17], 
        PER2_FABRIC_PWDATA[16], PER2_FABRIC_PWDATA[15], 
        PER2_FABRIC_PWDATA[14], PER2_FABRIC_PWDATA[13], 
        PER2_FABRIC_PWDATA[12], PER2_FABRIC_PWDATA[11], 
        PER2_FABRIC_PWDATA[10], PER2_FABRIC_PWDATA[9], 
        PER2_FABRIC_PWDATA[8], PER2_FABRIC_PWDATA[7], 
        PER2_FABRIC_PWDATA[6], PER2_FABRIC_PWDATA[5], 
        PER2_FABRIC_PWDATA[4], PER2_FABRIC_PWDATA[3], 
        PER2_FABRIC_PWDATA[2], PER2_FABRIC_PWDATA[1], 
        PER2_FABRIC_PWDATA[0]}), .PER2_FABRIC_PWRITE(
        PER2_FABRIC_PWRITE), .RTC_MATCH(RTC_MATCH), .SLEEPDEEP(
        SLEEPDEEP), .SLEEPHOLDACK(SLEEPHOLDACK), .SLEEPING(SLEEPING), 
        .SMBALERT_NO0(SMBALERT_NO0), .SMBALERT_NO1(SMBALERT_NO1), 
        .SMBSUS_NO0(SMBSUS_NO0), .SMBSUS_NO1(SMBSUS_NO1), 
        .SPI0_CLK_OUT(SPI0_CLK_OUT), .SPI0_SDI_MGPIO5A_H2F_A(
        SPI0_SDI_MGPIO5A_H2F_A), .SPI0_SDI_MGPIO5A_H2F_B(
        SPI0_SDI_MGPIO5A_H2F_B), .SPI0_SDO_MGPIO6A_H2F_A(
        SPI0_SDO_MGPIO6A_H2F_A), .SPI0_SDO_MGPIO6A_H2F_B(
        SPI0_SDO_MGPIO6A_H2F_B), .SPI0_SS0_MGPIO7A_H2F_A(
        SPI0_SS0_MGPIO7A_H2F_A), .SPI0_SS0_MGPIO7A_H2F_B(
        SPI0_SS0_MGPIO7A_H2F_B), .SPI0_SS1_MGPIO8A_H2F_A(
        SPI0_SS1_MGPIO8A_H2F_A), .SPI0_SS1_MGPIO8A_H2F_B(
        SPI0_SS1_MGPIO8A_H2F_B), .SPI0_SS2_MGPIO9A_H2F_A(
        SPI0_SS2_MGPIO9A_H2F_A), .SPI0_SS2_MGPIO9A_H2F_B(
        SPI0_SS2_MGPIO9A_H2F_B), .SPI0_SS3_MGPIO10A_H2F_A(
        SPI0_SS3_MGPIO10A_H2F_A), .SPI0_SS3_MGPIO10A_H2F_B(
        SPI0_SS3_MGPIO10A_H2F_B), .SPI0_SS4_MGPIO19A_H2F_A(
        SPI0_SS4_MGPIO19A_H2F_A), .SPI0_SS5_MGPIO20A_H2F_A(
        SPI0_SS5_MGPIO20A_H2F_A), .SPI0_SS6_MGPIO21A_H2F_A(
        SPI0_SS6_MGPIO21A_H2F_A), .SPI0_SS7_MGPIO22A_H2F_A(
        SPI0_SS7_MGPIO22A_H2F_A), .SPI1_CLK_OUT(SPI1_CLK_OUT), 
        .SPI1_SDI_MGPIO11A_H2F_A(SPI1_SDI_MGPIO11A_H2F_A), 
        .SPI1_SDI_MGPIO11A_H2F_B(SPI1_SDI_MGPIO11A_H2F_B), 
        .SPI1_SDO_MGPIO12A_H2F_A(SPI1_SDO_MGPIO12A_H2F_A), 
        .SPI1_SDO_MGPIO12A_H2F_B(SPI1_SDO_MGPIO12A_H2F_B), 
        .SPI1_SS0_MGPIO13A_H2F_A(SPI1_SS0_MGPIO13A_H2F_A), 
        .SPI1_SS0_MGPIO13A_H2F_B(SPI1_SS0_MGPIO13A_H2F_B), 
        .SPI1_SS1_MGPIO14A_H2F_A(SPI1_SS1_MGPIO14A_H2F_A), 
        .SPI1_SS1_MGPIO14A_H2F_B(SPI1_SS1_MGPIO14A_H2F_B), 
        .SPI1_SS2_MGPIO15A_H2F_A(SPI1_SS2_MGPIO15A_H2F_A), 
        .SPI1_SS2_MGPIO15A_H2F_B(SPI1_SS2_MGPIO15A_H2F_B), 
        .SPI1_SS3_MGPIO16A_H2F_A(SPI1_SS3_MGPIO16A_H2F_A), 
        .SPI1_SS3_MGPIO16A_H2F_B(SPI1_SS3_MGPIO16A_H2F_B), 
        .SPI1_SS4_MGPIO17A_H2F_A(SPI1_SS4_MGPIO17A_H2F_A), 
        .SPI1_SS5_MGPIO18A_H2F_A(SPI1_SS5_MGPIO18A_H2F_A), 
        .SPI1_SS6_MGPIO23A_H2F_A(SPI1_SS6_MGPIO23A_H2F_A), 
        .SPI1_SS7_MGPIO24A_H2F_A(SPI1_SS7_MGPIO24A_H2F_A), .TCGF({
        TCGF[9], TCGF[8], TCGF[7], TCGF[6], TCGF[5], TCGF[4], TCGF[3], 
        TCGF[2], TCGF[1], TCGF[0]}), .TRACECLK(TRACECLK), .TRACEDATA({
        TRACEDATA[3], TRACEDATA[2], TRACEDATA[1], TRACEDATA[0]}), 
        .TX_CLK(TX_CLK), .TX_ENF(TX_ENF), .TX_ERRF(TX_ERRF), 
        .TXCTL_EN_RIF(TXCTL_EN_RIF), .TXD_RIF({TXD_RIF[3], TXD_RIF[2], 
        TXD_RIF[1], TXD_RIF[0]}), .TXDF({TXDF[7], TXDF[6], TXDF[5], 
        TXDF[4], TXDF[3], TXDF[2], TXDF[1], TXDF[0]}), .TXEV(TXEV), 
        .WDOGTIMEOUT(WDOGTIMEOUT), .F_ARREADY_HREADYOUT1(
        F_ARREADY_HREADYOUT1), .F_AWREADY_HREADYOUT0(
        F_AWREADY_HREADYOUT0), .F_BID({F_BID[3], F_BID[2], F_BID[1], 
        F_BID[0]}), .F_BRESP_HRESP0({F_BRESP_HRESP0[1], 
        F_BRESP_HRESP0[0]}), .F_BVALID(F_BVALID), .F_RDATA_HRDATA01({
        F_RDATA_HRDATA01[63], F_RDATA_HRDATA01[62], 
        F_RDATA_HRDATA01[61], F_RDATA_HRDATA01[60], 
        F_RDATA_HRDATA01[59], F_RDATA_HRDATA01[58], 
        F_RDATA_HRDATA01[57], F_RDATA_HRDATA01[56], 
        F_RDATA_HRDATA01[55], F_RDATA_HRDATA01[54], 
        F_RDATA_HRDATA01[53], F_RDATA_HRDATA01[52], 
        F_RDATA_HRDATA01[51], F_RDATA_HRDATA01[50], 
        F_RDATA_HRDATA01[49], F_RDATA_HRDATA01[48], 
        F_RDATA_HRDATA01[47], F_RDATA_HRDATA01[46], 
        F_RDATA_HRDATA01[45], F_RDATA_HRDATA01[44], 
        F_RDATA_HRDATA01[43], F_RDATA_HRDATA01[42], 
        F_RDATA_HRDATA01[41], F_RDATA_HRDATA01[40], 
        F_RDATA_HRDATA01[39], F_RDATA_HRDATA01[38], 
        F_RDATA_HRDATA01[37], F_RDATA_HRDATA01[36], 
        F_RDATA_HRDATA01[35], F_RDATA_HRDATA01[34], 
        F_RDATA_HRDATA01[33], F_RDATA_HRDATA01[32], 
        F_RDATA_HRDATA01[31], F_RDATA_HRDATA01[30], 
        F_RDATA_HRDATA01[29], F_RDATA_HRDATA01[28], 
        F_RDATA_HRDATA01[27], F_RDATA_HRDATA01[26], 
        F_RDATA_HRDATA01[25], F_RDATA_HRDATA01[24], 
        F_RDATA_HRDATA01[23], F_RDATA_HRDATA01[22], 
        F_RDATA_HRDATA01[21], F_RDATA_HRDATA01[20], 
        F_RDATA_HRDATA01[19], F_RDATA_HRDATA01[18], 
        F_RDATA_HRDATA01[17], F_RDATA_HRDATA01[16], 
        F_RDATA_HRDATA01[15], F_RDATA_HRDATA01[14], 
        F_RDATA_HRDATA01[13], F_RDATA_HRDATA01[12], 
        F_RDATA_HRDATA01[11], F_RDATA_HRDATA01[10], 
        F_RDATA_HRDATA01[9], F_RDATA_HRDATA01[8], F_RDATA_HRDATA01[7], 
        F_RDATA_HRDATA01[6], F_RDATA_HRDATA01[5], F_RDATA_HRDATA01[4], 
        F_RDATA_HRDATA01[3], F_RDATA_HRDATA01[2], F_RDATA_HRDATA01[1], 
        F_RDATA_HRDATA01[0]}), .F_RID({F_RID[3], F_RID[2], F_RID[1], 
        F_RID[0]}), .F_RLAST(F_RLAST), .F_RRESP_HRESP1({
        F_RRESP_HRESP1[1], F_RRESP_HRESP1[0]}), .F_RVALID(F_RVALID), 
        .F_WREADY(F_WREADY), .MDDR_FABRIC_PRDATA({
        MDDR_FABRIC_PRDATA[15], MDDR_FABRIC_PRDATA[14], 
        MDDR_FABRIC_PRDATA[13], MDDR_FABRIC_PRDATA[12], 
        MDDR_FABRIC_PRDATA[11], MDDR_FABRIC_PRDATA[10], 
        MDDR_FABRIC_PRDATA[9], MDDR_FABRIC_PRDATA[8], 
        MDDR_FABRIC_PRDATA[7], MDDR_FABRIC_PRDATA[6], 
        MDDR_FABRIC_PRDATA[5], MDDR_FABRIC_PRDATA[4], 
        MDDR_FABRIC_PRDATA[3], MDDR_FABRIC_PRDATA[2], 
        MDDR_FABRIC_PRDATA[1], MDDR_FABRIC_PRDATA[0]}), 
        .MDDR_FABRIC_PREADY(MDDR_FABRIC_PREADY), .MDDR_FABRIC_PSLVERR(
        MDDR_FABRIC_PSLVERR), .CAN_RXBUS_F2H_SCP(VCC), 
        .CAN_TX_EBL_F2H_SCP(VCC), .CAN_TXBUS_F2H_SCP(VCC), .COLF(VCC), 
        .CRSF(VCC), .F2_DMAREADY({VCC, VCC}), .F2H_INTERRUPT({GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND}), .F2HCALIB(VCC), .F_DMAREADY({VCC, VCC}), 
        .F_FM0_ADDR({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .F_FM0_ENABLE(GND), .F_FM0_MASTLOCK(GND), .F_FM0_READY(VCC), 
        .F_FM0_SEL(GND), .F_FM0_SIZE({GND, GND}), .F_FM0_TRANS1(GND), 
        .F_FM0_WDATA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .F_FM0_WRITE(GND), .F_HM0_RDATA({
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0}), 
        .F_HM0_READY(VCC), .F_HM0_RESP(GND), .FAB_AVALID(VCC), 
        .FAB_HOSTDISCON(VCC), .FAB_IDDIG(VCC), .FAB_LINESTATE({VCC, 
        VCC}), .FAB_M3_RESET_N(VCC), .FAB_PLL_LOCK(
        MC_System_0_FIC_0_LOCK), .FAB_RXACTIVE(VCC), .FAB_RXERROR(VCC), 
        .FAB_RXVALID(VCC), .FAB_RXVALIDH(GND), .FAB_SESSEND(VCC), 
        .FAB_TXREADY(VCC), .FAB_VBUSVALID(VCC), .FAB_VSTATUS({VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC}), .FAB_XDATAIN({VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC}), .GTX_CLKPF(VCC), .I2C0_BCLK(VCC), 
        .I2C0_SCL_F2H_SCP(VCC), .I2C0_SDA_F2H_SCP(VCC), .I2C1_BCLK(VCC)
        , .I2C1_SCL_F2H_SCP(VCC), .I2C1_SDA_F2H_SCP(VCC), .MDIF(VCC), 
        .MGPIO0A_F2H_GPIN(VCC), .MGPIO10A_F2H_GPIN(VCC), 
        .MGPIO11A_F2H_GPIN(VCC), .MGPIO11B_F2H_GPIN(VCC), 
        .MGPIO12A_F2H_GPIN(VCC), .MGPIO13A_F2H_GPIN(VCC), 
        .MGPIO14A_F2H_GPIN(VCC), .MGPIO15A_F2H_GPIN(VCC), 
        .MGPIO16A_F2H_GPIN(VCC), .MGPIO17B_F2H_GPIN(VCC), 
        .MGPIO18B_F2H_GPIN(VCC), .MGPIO19B_F2H_GPIN(VCC), 
        .MGPIO1A_F2H_GPIN(VCC), .MGPIO20B_F2H_GPIN(VCC), 
        .MGPIO21B_F2H_GPIN(VCC), .MGPIO22B_F2H_GPIN(VCC), 
        .MGPIO24B_F2H_GPIN(VCC), .MGPIO25B_F2H_GPIN(VCC), 
        .MGPIO26B_F2H_GPIN(VCC), .MGPIO27B_F2H_GPIN(VCC), 
        .MGPIO28B_F2H_GPIN(VCC), .MGPIO29B_F2H_GPIN(VCC), 
        .MGPIO2A_F2H_GPIN(VCC), .MGPIO30B_F2H_GPIN(VCC), 
        .MGPIO31B_F2H_GPIN(VCC), .MGPIO3A_F2H_GPIN(VCC), 
        .MGPIO4A_F2H_GPIN(VCC), .MGPIO5A_F2H_GPIN(VCC), 
        .MGPIO6A_F2H_GPIN(VCC), .MGPIO7A_F2H_GPIN(VCC), 
        .MGPIO8A_F2H_GPIN(VCC), .MGPIO9A_F2H_GPIN(VCC), 
        .MMUART0_CTS_F2H_SCP(VCC), .MMUART0_DCD_F2H_SCP(VCC), 
        .MMUART0_DSR_F2H_SCP(VCC), .MMUART0_DTR_F2H_SCP(VCC), 
        .MMUART0_RI_F2H_SCP(VCC), .MMUART0_RTS_F2H_SCP(VCC), 
        .MMUART0_RXD_F2H_SCP(VCC), .MMUART0_SCK_F2H_SCP(VCC), 
        .MMUART0_TXD_F2H_SCP(VCC), .MMUART1_CTS_F2H_SCP(VCC), 
        .MMUART1_DCD_F2H_SCP(VCC), .MMUART1_DSR_F2H_SCP(VCC), 
        .MMUART1_RI_F2H_SCP(VCC), .MMUART1_RTS_F2H_SCP(VCC), 
        .MMUART1_RXD_F2H_SCP(VCC), .MMUART1_SCK_F2H_SCP(VCC), 
        .MMUART1_TXD_F2H_SCP(VCC), .PER2_FABRIC_PRDATA({GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND}), .PER2_FABRIC_PREADY(VCC), 
        .PER2_FABRIC_PSLVERR(GND), .RCGF({VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC}), .RX_CLKPF(VCC), .RX_DVF(VCC), .RX_ERRF(
        VCC), .RX_EV(VCC), .RXDF({VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC}), .SLEEPHOLDREQ(GND), .SMBALERT_NI0(VCC), .SMBALERT_NI1(
        VCC), .SMBSUS_NI0(VCC), .SMBSUS_NI1(VCC), .SPI0_CLK_IN(VCC), 
        .SPI0_SDI_F2H_SCP(VCC), .SPI0_SDO_F2H_SCP(VCC), 
        .SPI0_SS0_F2H_SCP(VCC), .SPI0_SS1_F2H_SCP(VCC), 
        .SPI0_SS2_F2H_SCP(VCC), .SPI0_SS3_F2H_SCP(VCC), .SPI1_CLK_IN(
        VCC), .SPI1_SDI_F2H_SCP(VCC), .SPI1_SDO_F2H_SCP(VCC), 
        .SPI1_SS0_F2H_SCP(VCC), .SPI1_SS1_F2H_SCP(VCC), 
        .SPI1_SS2_F2H_SCP(VCC), .SPI1_SS3_F2H_SCP(VCC), .TX_CLKPF(VCC), 
        .USER_MSS_GPIO_RESET_N(VCC), .USER_MSS_RESET_N(VCC), .XCLK_FAB(
        VCC), .CLK_BASE(MC_System_0_FIC_0_CLK), .CLK_MDDR_APB(VCC), 
        .F_ARADDR_HADDR1({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}), 
        .F_ARBURST_HTRANS1({GND, GND}), .F_ARID_HSEL1({GND, GND, GND, 
        GND}), .F_ARLEN_HBURST1({GND, GND, GND, GND}), 
        .F_ARLOCK_HMASTLOCK1({GND, GND}), .F_ARSIZE_HSIZE1({GND, GND}), 
        .F_ARVALID_HWRITE1(GND), .F_AWADDR_HADDR0({VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC}), .F_AWBURST_HTRANS0({GND, GND}), 
        .F_AWID_HSEL0({GND, GND, GND, GND}), .F_AWLEN_HBURST0({GND, 
        GND, GND, GND}), .F_AWLOCK_HMASTLOCK0({GND, GND}), 
        .F_AWSIZE_HSIZE0({GND, GND}), .F_AWVALID_HWRITE0(GND), 
        .F_BREADY(GND), .F_RMW_AXI(GND), .F_RREADY(GND), 
        .F_WDATA_HWDATA01({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC}), .F_WID_HREADY01({GND, GND, 
        GND, GND}), .F_WLAST(GND), .F_WSTRB({GND, GND, GND, GND, GND, 
        GND, GND, GND}), .F_WVALID(GND), .FPGA_MDDR_ARESET_N(VCC), 
        .MDDR_FABRIC_PADDR({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC}), .MDDR_FABRIC_PENABLE(VCC), .MDDR_FABRIC_PSEL(VCC), 
        .MDDR_FABRIC_PWDATA({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}), .MDDR_FABRIC_PWRITE(
        VCC), .PRESET_N(GND), .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND), .DM_IN({GND, GND, GND}), 
        .DRAM_DQ_IN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND}), .DRAM_DQS_IN({GND, 
        GND, GND}), .DRAM_FIFO_WE_IN({GND, GND}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND), 
        .MMUART0_DCD_MGPIO22B_IN(GND), .MMUART0_DSR_MGPIO20B_IN(GND), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND), 
        .MMUART0_RI_MGPIO21B_IN(GND), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(GND), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(GND), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(USB_ULPI_XCLK_PAD_Y), 
        .RGMII_MDC_RMII_MDC_IN(GND), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(USB_ULPI_DATA_7_PAD_Y), 
        .RGMII_RX_CLK_IN(GND), .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(
        USB_ULPI_DATA_2_PAD_Y), .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(
        USB_ULPI_DATA_0_PAD_Y), .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(
        USB_ULPI_DATA_1_PAD_Y), .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(
        USB_ULPI_DATA_3_PAD_Y), .RGMII_RXD3_USBB_DATA4_IN(
        USB_ULPI_DATA_4_PAD_Y), .RGMII_TX_CLK_IN(GND), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(USB_ULPI_NXT_PAD_Y), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(USB_ULPI_DIR_PAD_Y), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND), 
        .RGMII_TXD2_USBB_DATA5_IN(USB_ULPI_DATA_5_PAD_Y), 
        .RGMII_TXD3_USBB_DATA6_IN(USB_ULPI_DATA_6_PAD_Y), 
        .SPI0_SCK_USBA_XCLK_IN(GND), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND)
        , .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND), .SPI1_SCK_IN(GND), 
        .SPI1_SDI_MGPIO11A_IN(GND), .SPI1_SDO_MGPIO12A_IN(GND), 
        .SPI1_SS0_MGPIO13A_IN(GND), .SPI1_SS1_MGPIO14A_IN(GND), 
        .SPI1_SS2_MGPIO15A_IN(GND), .SPI1_SS3_MGPIO16A_IN(GND), 
        .SPI1_SS4_MGPIO17A_IN(GND), .SPI1_SS5_MGPIO18A_IN(GND), 
        .SPI1_SS6_MGPIO23A_IN(GND), .SPI1_SS7_MGPIO24A_IN(GND), 
        .USBC_XCLK_IN(GND), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT), .DRAM_ADDR({DRAM_ADDR[15], 
        DRAM_ADDR[14], DRAM_ADDR[13], DRAM_ADDR[12], DRAM_ADDR[11], 
        DRAM_ADDR[10], DRAM_ADDR[9], DRAM_ADDR[8], DRAM_ADDR[7], 
        DRAM_ADDR[6], DRAM_ADDR[5], DRAM_ADDR[4], DRAM_ADDR[3], 
        DRAM_ADDR[2], DRAM_ADDR[1], DRAM_ADDR[0]}), .DRAM_BA({
        DRAM_BA[2], DRAM_BA[1], DRAM_BA[0]}), .DRAM_CASN(DRAM_CASN), 
        .DRAM_CKE(DRAM_CKE), .DRAM_CLK(DRAM_CLK), .DRAM_CSN(DRAM_CSN), 
        .DRAM_DM_RDQS_OUT({DRAM_DM_RDQS_OUT[2], DRAM_DM_RDQS_OUT[1], 
        DRAM_DM_RDQS_OUT[0]}), .DRAM_DQ_OUT({DRAM_DQ_OUT[17], 
        DRAM_DQ_OUT[16], DRAM_DQ_OUT[15], DRAM_DQ_OUT[14], 
        DRAM_DQ_OUT[13], DRAM_DQ_OUT[12], DRAM_DQ_OUT[11], 
        DRAM_DQ_OUT[10], DRAM_DQ_OUT[9], DRAM_DQ_OUT[8], 
        DRAM_DQ_OUT[7], DRAM_DQ_OUT[6], DRAM_DQ_OUT[5], DRAM_DQ_OUT[4], 
        DRAM_DQ_OUT[3], DRAM_DQ_OUT[2], DRAM_DQ_OUT[1], DRAM_DQ_OUT[0]})
        , .DRAM_DQS_OUT({DRAM_DQS_OUT[2], DRAM_DQS_OUT[1], 
        DRAM_DQS_OUT[0]}), .DRAM_FIFO_WE_OUT({DRAM_FIFO_WE_OUT[1], 
        DRAM_FIFO_WE_OUT[0]}), .DRAM_ODT(DRAM_ODT), .DRAM_RASN(
        DRAM_RASN), .DRAM_RSTN(DRAM_RSTN), .DRAM_WEN(DRAM_WEN), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(
        I2C0_SCL_USBC_DATA1_MGPIO31B_OUT), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT), 
        .MMUART0_DCD_MGPIO22B_OUT(MMUART0_DCD_MGPIO22B_OUT), 
        .MMUART0_DSR_MGPIO20B_OUT(MMUART0_DSR_MGPIO20B_OUT), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT), .MMUART0_RI_MGPIO21B_OUT(
        MMUART0_RI_MGPIO21B_OUT), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT), .RGMII_MDC_RMII_MDC_OUT(
        RGMII_MDC_RMII_MDC_OUT), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT), 
        .RGMII_RX_CLK_OUT(RGMII_RX_CLK_OUT), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT), 
        .RGMII_RXD3_USBB_DATA4_OUT(
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT), .RGMII_TX_CLK_OUT(
        RGMII_TX_CLK_OUT), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT), 
        .RGMII_TXD2_USBB_DATA5_OUT(
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT), 
        .RGMII_TXD3_USBB_DATA6_OUT(
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT), 
        .SPI0_SCK_USBA_XCLK_OUT(SPI0_SCK_USBA_XCLK_OUT), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(SPI0_SDI_USBA_DIR_MGPIO5A_OUT), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(SPI0_SDO_USBA_STP_MGPIO6A_OUT), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(SPI0_SS0_USBA_NXT_MGPIO7A_OUT), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT), .SPI1_SCK_OUT(SPI1_SCK_OUT), 
        .SPI1_SDI_MGPIO11A_OUT(SPI1_SDI_MGPIO11A_OUT), 
        .SPI1_SDO_MGPIO12A_OUT(SPI1_SDO_MGPIO12A_OUT), 
        .SPI1_SS0_MGPIO13A_OUT(SPI1_SS0_MGPIO13A_OUT), 
        .SPI1_SS1_MGPIO14A_OUT(SPI1_SS1_MGPIO14A_OUT), 
        .SPI1_SS2_MGPIO15A_OUT(SPI1_SS2_MGPIO15A_OUT), 
        .SPI1_SS3_MGPIO16A_OUT(SPI1_SS3_MGPIO16A_OUT), 
        .SPI1_SS4_MGPIO17A_OUT(SPI1_SS4_MGPIO17A_OUT), 
        .SPI1_SS5_MGPIO18A_OUT(SPI1_SS5_MGPIO18A_OUT), 
        .SPI1_SS6_MGPIO23A_OUT(SPI1_SS6_MGPIO23A_OUT), 
        .SPI1_SS7_MGPIO24A_OUT(SPI1_SS7_MGPIO24A_OUT), .USBC_XCLK_OUT(
        USBC_XCLK_OUT), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE), .DM_OE({DM_OE[2], DM_OE[1], 
        DM_OE[0]}), .DRAM_DQ_OE({DRAM_DQ_OE[17], DRAM_DQ_OE[16], 
        DRAM_DQ_OE[15], DRAM_DQ_OE[14], DRAM_DQ_OE[13], DRAM_DQ_OE[12], 
        DRAM_DQ_OE[11], DRAM_DQ_OE[10], DRAM_DQ_OE[9], DRAM_DQ_OE[8], 
        DRAM_DQ_OE[7], DRAM_DQ_OE[6], DRAM_DQ_OE[5], DRAM_DQ_OE[4], 
        DRAM_DQ_OE[3], DRAM_DQ_OE[2], DRAM_DQ_OE[1], DRAM_DQ_OE[0]}), 
        .DRAM_DQS_OE({DRAM_DQS_OE[2], DRAM_DQS_OE[1], DRAM_DQS_OE[0]}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(I2C1_SCL_USBA_DATA4_MGPIO1A_OE)
        , .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE), .MMUART0_DCD_MGPIO22B_OE(
        MMUART0_DCD_MGPIO22B_OE), .MMUART0_DSR_MGPIO20B_OE(
        MMUART0_DSR_MGPIO20B_OE), .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OE), .MMUART0_RI_MGPIO21B_OE(
        MMUART0_RI_MGPIO21B_OE), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(
        MMUART0_RXD_USBC_STP_MGPIO28B_OE), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE), .RGMII_MDC_RMII_MDC_OE(
        RGMII_MDC_RMII_MDC_OE), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE), 
        .RGMII_RX_CLK_OE(RGMII_RX_CLK_OE), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE), 
        .RGMII_RXD3_USBB_DATA4_OE(
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE), .RGMII_TX_CLK_OE(
        RGMII_TX_CLK_OE), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE), 
        .RGMII_TXD2_USBB_DATA5_OE(
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE), 
        .RGMII_TXD3_USBB_DATA6_OE(
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE), 
        .SPI0_SCK_USBA_XCLK_OE(SPI0_SCK_USBA_XCLK_OE), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(SPI0_SDI_USBA_DIR_MGPIO5A_OE), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OE(SPI0_SDO_USBA_STP_MGPIO6A_OE), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OE(SPI0_SS0_USBA_NXT_MGPIO7A_OE), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(SPI0_SS1_USBA_DATA5_MGPIO8A_OE)
        , .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE), .SPI1_SCK_OE(SPI1_SCK_OE), 
        .SPI1_SDI_MGPIO11A_OE(SPI1_SDI_MGPIO11A_OE), 
        .SPI1_SDO_MGPIO12A_OE(SPI1_SDO_MGPIO12A_OE), 
        .SPI1_SS0_MGPIO13A_OE(SPI1_SS0_MGPIO13A_OE), 
        .SPI1_SS1_MGPIO14A_OE(SPI1_SS1_MGPIO14A_OE), 
        .SPI1_SS2_MGPIO15A_OE(SPI1_SS2_MGPIO15A_OE), 
        .SPI1_SS3_MGPIO16A_OE(SPI1_SS3_MGPIO16A_OE), 
        .SPI1_SS4_MGPIO17A_OE(SPI1_SS4_MGPIO17A_OE), 
        .SPI1_SS5_MGPIO18A_OE(SPI1_SS5_MGPIO18A_OE), 
        .SPI1_SS6_MGPIO23A_OE(SPI1_SS6_MGPIO23A_OE), 
        .SPI1_SS7_MGPIO24A_OE(SPI1_SS7_MGPIO24A_OE), .USBC_XCLK_OE(
        USBC_XCLK_OE));
    VCC VCC_Z (.Y(VCC));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_0_PAD (.PAD(USB_ULPI_DATA[0]), 
        .D(MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT), .E(
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE), .Y(
        USB_ULPI_DATA_0_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_1_PAD (.PAD(USB_ULPI_DATA[1]), 
        .D(MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT), .E(
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE), .Y(
        USB_ULPI_DATA_1_PAD_Y));
    TRIBUFF #( .IOSTD("") )  USB_ULPI_STP_PAD (.D(
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT), .E(
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE), .PAD(
        USB_ULPI_STP));
    
endmodule


module MC_System_sb(
       prdata_o_1_0,
       ADC_SCALING_0_ib_adc_o,
       STEPPER_THETA_1_step_count_o,
       adc_interface_0_result_ch0_o,
       adc_interface_0_result_ch2_o,
       adc_measurements_0_adc_result_ch3_o,
       adc_measurements_0_adc_result_ch1_o,
       SEQ_CONTROLLER_1_state_o_0,
       prdata_o_1_0_a2_12_0,
       prdata_o_1_0_a2_10_0,
       FOC_TRANSFORMS_1_valpha_o,
       prdata_o_1_iv_12_1,
       FOC_TRANSFORMS_0_vbeta_o,
       prdata_o_1_iv_12_0_2,
       SPEED_ID_IQ_PI_1_iq_pi_output_o,
       FOC_TRANSFORMS_0_iq_o_0,
       FOC_TRANSFORMS_0_iq_o_9,
       FOC_TRANSFORMS_0_id_o_0,
       FOC_TRANSFORMS_0_id_o_9,
       prdata_o_1_iv_9,
       SPEED_ID_IQ_PI_1_id_pi_output_o_m,
       prdata_o_1_0_1,
       prdata_o_1_0_2,
       prdata_o_1_0_0,
       prdata_o_1_3,
       prdata_o_1_4,
       prdata_o_1_2,
       prdata_o_1_24_3,
       prdata_o_1_24_4,
       prdata_o_1_24_2,
       prdata_o_1_12_2,
       prdata_o_1_12_3,
       prdata_o_1_12_1,
       prdata_o_1_0_iv_6,
       prdata_o_1_0_iv_7,
       prdata_o_1_0_iv_10,
       prdata_o_1_0_iv_11,
       prdata_o_1_iv_11_0,
       prdata_o_1_iv_11_1,
       prdata_o_1_iv_11_3,
       prdata_o_1_iv_12,
       USB_ULPI_DATA,
       MC_System_0_AMBA_SLAVE_1_PADDR_2,
       MC_System_0_AMBA_SLAVE_1_PADDR_4,
       MC_System_0_AMBA_SLAVE_1_PADDR_5,
       MC_System_0_AMBA_SLAVE_1_PADDR_0,
       MC_System_0_AMBA_SLAVE_1_PADDR_1,
       MC_System_0_AMBA_SLAVE_1_PADDR_3,
       MC_System_0_AMBA_SLAVE_1_PADDR_6,
       MC_System_0_AMBA_SLAVE_1_PADDR_7,
       MC_System_0_AMBA_SLAVE_1_PADDR_8,
       MC_System_0_AMBA_SLAVE_1_PADDR_9,
       MC_System_0_AMBA_SLAVE_1_PADDR_10,
       MC_System_0_AMBA_SLAVE_1_PADDR_11,
       MC_System_0_AMBA_SLAVE_1_PWDATA,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       MC_System_0_FAB_CCC_GL1,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       MC_System_0_AMBA_SLAVE_1_PSELx,
       N_2661,
       N_1077,
       N_2660,
       N_2785,
       N_1014,
       N_2779,
       N_2704,
       N_184,
       adc_channel_ch3_o_1_sqmuxa_0_a2_0_0,
       N_172,
       N_174,
       prdata_o197_0_a2_0_a2_0_out,
       prdata_o201_0_a2_0_0,
       N_201,
       N_193,
       N_187,
       N_2470,
       g2,
       g1,
       N_106,
       N_108,
       N_202,
       N_1083,
       N_104,
       N_179,
       N_107,
       N_105,
       N_233,
       N_194,
       N_1080,
       N_2522,
       N_2784,
       N_1007,
       N_2532,
       N_2778,
       prdata_o195_0_a2_0,
       prdata_o191,
       N_1508,
       N_2542,
       N_2791,
       N_2734,
       N_2585,
       prdata_o190,
       N_2606,
       N_2728,
       N_54,
       N_157,
       N_151,
       N_152,
       N_153,
       N_154,
       N_155,
       N_156,
       USB_ULPI_XCLK,
       USB_ULPI_STP,
       USB_ULPI_NXT,
       USB_ULPI_DIR,
       MC_System_0_AMBA_SLAVE_1_PENABLE,
       MC_System_0_AMBA_SLAVE_1_PWRITE,
       GPIO_0_M2F_c
    );
input  [3:3] prdata_o_1_0;
input  [2:2] ADC_SCALING_0_ib_adc_o;
input  [2:2] STEPPER_THETA_1_step_count_o;
input  [2:2] adc_interface_0_result_ch0_o;
input  [2:2] adc_interface_0_result_ch2_o;
input  [2:2] adc_measurements_0_adc_result_ch3_o;
input  [2:2] adc_measurements_0_adc_result_ch1_o;
input  [2:2] SEQ_CONTROLLER_1_state_o_0;
input  [15:15] prdata_o_1_0_a2_12_0;
input  [15:15] prdata_o_1_0_a2_10_0;
input  [11:11] FOC_TRANSFORMS_1_valpha_o;
input  [3:3] prdata_o_1_iv_12_1;
input  [11:11] FOC_TRANSFORMS_0_vbeta_o;
input  [3:3] prdata_o_1_iv_12_0_2;
input  [0:0] SPEED_ID_IQ_PI_1_iq_pi_output_o;
input  FOC_TRANSFORMS_0_iq_o_0;
input  FOC_TRANSFORMS_0_iq_o_9;
input  FOC_TRANSFORMS_0_id_o_0;
input  FOC_TRANSFORMS_0_id_o_9;
input  [0:0] prdata_o_1_iv_9;
input  [0:0] SPEED_ID_IQ_PI_1_id_pi_output_o_m;
input  [16:12] prdata_o_1_0_1;
input  [16:12] prdata_o_1_0_2;
input  [16:12] prdata_o_1_0_0;
input  [3:2] prdata_o_1_3;
input  [2:2] prdata_o_1_4;
input  [3:2] prdata_o_1_2;
input  [1:1] prdata_o_1_24_3;
input  [1:1] prdata_o_1_24_4;
input  [1:1] prdata_o_1_24_2;
input  [11:4] prdata_o_1_12_2;
input  [11:4] prdata_o_1_12_3;
input  [11:4] prdata_o_1_12_1;
input  [16:12] prdata_o_1_0_iv_6;
input  [16:12] prdata_o_1_0_iv_7;
input  [10:4] prdata_o_1_0_iv_10;
input  [10:4] prdata_o_1_0_iv_11;
input  prdata_o_1_iv_11_0;
input  prdata_o_1_iv_11_1;
input  prdata_o_1_iv_11_3;
input  [3:1] prdata_o_1_iv_12;
inout  [7:0] USB_ULPI_DATA;
inout  MC_System_0_AMBA_SLAVE_1_PADDR_2;
inout  MC_System_0_AMBA_SLAVE_1_PADDR_4;
inout  MC_System_0_AMBA_SLAVE_1_PADDR_5;
output MC_System_0_AMBA_SLAVE_1_PADDR_0;
output MC_System_0_AMBA_SLAVE_1_PADDR_1;
output MC_System_0_AMBA_SLAVE_1_PADDR_3;
output MC_System_0_AMBA_SLAVE_1_PADDR_6;
output MC_System_0_AMBA_SLAVE_1_PADDR_7;
output MC_System_0_AMBA_SLAVE_1_PADDR_8;
output MC_System_0_AMBA_SLAVE_1_PADDR_9;
output MC_System_0_AMBA_SLAVE_1_PADDR_10;
output MC_System_0_AMBA_SLAVE_1_PADDR_11;
output [23:0] MC_System_0_AMBA_SLAVE_1_PWDATA;
output MC_System_0_FIC_0_LOCK;
output MC_System_0_FIC_0_CLK;
output MC_System_0_FAB_CCC_GL1;
output MC_System_0_AMBA_SLAVE_0_PSELx;
output MC_System_0_AMBA_SLAVE_1_PSELx;
input  N_2661;
input  N_1077;
input  N_2660;
input  N_2785;
input  N_1014;
input  N_2779;
input  N_2704;
input  N_184;
input  adc_channel_ch3_o_1_sqmuxa_0_a2_0_0;
input  N_172;
input  N_174;
input  prdata_o197_0_a2_0_a2_0_out;
input  prdata_o201_0_a2_0_0;
input  N_201;
input  N_193;
input  N_187;
input  N_2470;
input  g2;
input  g1;
input  N_106;
input  N_108;
input  N_202;
input  N_1083;
input  N_104;
input  N_179;
input  N_107;
input  N_105;
input  N_233;
input  N_194;
input  N_1080;
input  N_2522;
input  N_2784;
input  N_1007;
input  N_2532;
input  N_2778;
input  prdata_o195_0_a2_0;
input  prdata_o191;
input  N_1508;
input  N_2542;
input  N_2791;
input  N_2734;
input  N_2585;
input  prdata_o190;
input  N_2606;
input  N_2728;
input  N_54;
input  N_157;
input  N_151;
input  N_152;
input  N_153;
input  N_154;
input  N_155;
input  N_156;
input  USB_ULPI_XCLK;
output USB_ULPI_STP;
input  USB_ULPI_NXT;
input  USB_ULPI_DIR;
output MC_System_0_AMBA_SLAVE_1_PENABLE;
output MC_System_0_AMBA_SLAVE_1_PWRITE;
output GPIO_0_M2F_c;

    wire [15:12] MC_System_0_AMBA_SLAVE_1_PADDR;
    wire [31:0] MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA;
    wire FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, GND, VCC;
    
    MC_System_sb_FABOSC_0_OSC FABOSC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    
        CoreAPB3_32_0_1_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_16_3_19 
        CoreAPB3_0 (.prdata_o_1_0({prdata_o_1_0[3]}), 
        .ADC_SCALING_0_ib_adc_o({ADC_SCALING_0_ib_adc_o[2]}), 
        .STEPPER_THETA_1_step_count_o({STEPPER_THETA_1_step_count_o[2]})
        , .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[2]}), 
        .adc_interface_0_result_ch2_o({adc_interface_0_result_ch2_o[2]})
        , .adc_measurements_0_adc_result_ch3_o({
        adc_measurements_0_adc_result_ch3_o[2]}), 
        .adc_measurements_0_adc_result_ch1_o({
        adc_measurements_0_adc_result_ch1_o[2]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_13(
        MC_System_0_AMBA_SLAVE_1_PADDR[15]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_12(
        MC_System_0_AMBA_SLAVE_1_PADDR[14]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_11(
        MC_System_0_AMBA_SLAVE_1_PADDR[13]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_10(
        MC_System_0_AMBA_SLAVE_1_PADDR[12]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_0(
        MC_System_0_AMBA_SLAVE_1_PADDR_2), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_2(
        MC_System_0_AMBA_SLAVE_1_PADDR_4), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_3(
        MC_System_0_AMBA_SLAVE_1_PADDR_5), .SEQ_CONTROLLER_1_state_o_0({
        SEQ_CONTROLLER_1_state_o_0[2]}), .prdata_o_1_0_a2_12_0({
        prdata_o_1_0_a2_12_0[15]}), .prdata_o_1_0_a2_10_0({
        prdata_o_1_0_a2_10_0[15]}), .FOC_TRANSFORMS_1_valpha_o({
        FOC_TRANSFORMS_1_valpha_o[11]}), .prdata_o_1_iv_12_1({
        prdata_o_1_iv_12_1[3]}), .FOC_TRANSFORMS_0_vbeta_o({
        FOC_TRANSFORMS_0_vbeta_o[11]}), .prdata_o_1_iv_12_0_2({
        prdata_o_1_iv_12_0_2[3]}), .SPEED_ID_IQ_PI_1_iq_pi_output_o({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]}), .FOC_TRANSFORMS_0_iq_o_0(
        FOC_TRANSFORMS_0_iq_o_0), .FOC_TRANSFORMS_0_iq_o_9(
        FOC_TRANSFORMS_0_iq_o_9), .FOC_TRANSFORMS_0_id_o_0(
        FOC_TRANSFORMS_0_id_o_0), .FOC_TRANSFORMS_0_id_o_9(
        FOC_TRANSFORMS_0_id_o_9), .prdata_o_1_iv_9({prdata_o_1_iv_9[0]})
        , .SPEED_ID_IQ_PI_1_id_pi_output_o_m({
        SPEED_ID_IQ_PI_1_id_pi_output_o_m[0]}), .prdata_o_1_0_1({
        prdata_o_1_0_1[16], prdata_o_1_0_1[15], prdata_o_1_0_1[14], 
        prdata_o_1_0_1[13], prdata_o_1_0_1[12]}), .prdata_o_1_0_2({
        prdata_o_1_0_2[16], prdata_o_1_0_2[15], prdata_o_1_0_2[14], 
        prdata_o_1_0_2[13], prdata_o_1_0_2[12]}), .prdata_o_1_0_0({
        prdata_o_1_0_0[16], prdata_o_1_0_0[15], prdata_o_1_0_0[14], 
        prdata_o_1_0_0[13], prdata_o_1_0_0[12]}), .prdata_o_1_3({
        prdata_o_1_3[3], prdata_o_1_3[2]}), .prdata_o_1_4({
        prdata_o_1_4[2]}), .prdata_o_1_2({prdata_o_1_2[3], 
        prdata_o_1_2[2]}), .prdata_o_1_24_3({prdata_o_1_24_3[1]}), 
        .prdata_o_1_24_4({prdata_o_1_24_4[1]}), .prdata_o_1_24_2({
        prdata_o_1_24_2[1]}), .prdata_o_1_12_2({prdata_o_1_12_2[11], 
        prdata_o_1_12_2[10], prdata_o_1_12_2[9], prdata_o_1_12_2[8], 
        prdata_o_1_12_2[7], prdata_o_1_12_2[6], prdata_o_1_12_2[5], 
        prdata_o_1_12_2[4]}), .prdata_o_1_12_3({prdata_o_1_12_3[11], 
        prdata_o_1_12_3[10], prdata_o_1_12_3[9], prdata_o_1_12_3[8], 
        prdata_o_1_12_3[7], prdata_o_1_12_3[6], prdata_o_1_12_3[5], 
        prdata_o_1_12_3[4]}), .prdata_o_1_12_1({prdata_o_1_12_1[11], 
        prdata_o_1_12_1[10], prdata_o_1_12_1[9], prdata_o_1_12_1[8], 
        prdata_o_1_12_1[7], prdata_o_1_12_1[6], prdata_o_1_12_1[5], 
        prdata_o_1_12_1[4]}), .prdata_o_1_0_iv_6({
        prdata_o_1_0_iv_6[16], prdata_o_1_0_iv_6[15], 
        prdata_o_1_0_iv_6[14], prdata_o_1_0_iv_6[13], 
        prdata_o_1_0_iv_6[12]}), .prdata_o_1_0_iv_7({
        prdata_o_1_0_iv_7[16], prdata_o_1_0_iv_7[15], 
        prdata_o_1_0_iv_7[14], prdata_o_1_0_iv_7[13], 
        prdata_o_1_0_iv_7[12]}), .prdata_o_1_0_iv_10({
        prdata_o_1_0_iv_10[10], prdata_o_1_0_iv_10[9], 
        prdata_o_1_0_iv_10[8], prdata_o_1_0_iv_10[7], 
        prdata_o_1_0_iv_10[6], prdata_o_1_0_iv_10[5], 
        prdata_o_1_0_iv_10[4]}), .prdata_o_1_0_iv_11({
        prdata_o_1_0_iv_11[10], prdata_o_1_0_iv_11[9], 
        prdata_o_1_0_iv_11[8], prdata_o_1_0_iv_11[7], 
        prdata_o_1_0_iv_11[6], prdata_o_1_0_iv_11[5], 
        prdata_o_1_0_iv_11[4]}), .prdata_o_1_iv_11_0(
        prdata_o_1_iv_11_0), .prdata_o_1_iv_11_1(prdata_o_1_iv_11_1), 
        .prdata_o_1_iv_11_3(prdata_o_1_iv_11_3), .prdata_o_1_iv_12({
        prdata_o_1_iv_12[3], prdata_o_1_iv_12[2], prdata_o_1_iv_12[1]})
        , .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[19]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[20]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[21]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[22]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[10]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[12]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[15]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[14]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[8]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[7]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx), 
        .MC_System_0_AMBA_SLAVE_0_PSELx(MC_System_0_AMBA_SLAVE_0_PSELx)
        , .MC_System_0_AMBA_SLAVE_1_PSELx(
        MC_System_0_AMBA_SLAVE_1_PSELx), .N_2661(N_2661), .N_1077(
        N_1077), .N_2660(N_2660), .N_2785(N_2785), .N_1014(N_1014), 
        .N_2779(N_2779), .N_2704(N_2704), .N_184(N_184), 
        .adc_channel_ch3_o_1_sqmuxa_0_a2_0_0(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .N_172(N_172), .N_174(
        N_174), .prdata_o197_0_a2_0_a2_0_out(
        prdata_o197_0_a2_0_a2_0_out), .prdata_o201_0_a2_0_0(
        prdata_o201_0_a2_0_0), .N_201(N_201), .N_193(N_193), .N_187(
        N_187), .N_2470(N_2470), .g2(g2), .g1(g1), .N_106(N_106), 
        .N_108(N_108), .N_202(N_202), .N_1083(N_1083), .N_104(N_104), 
        .N_179(N_179), .N_107(N_107), .N_105(N_105), .N_233(N_233), 
        .N_194(N_194), .N_1080(N_1080), .N_2522(N_2522), .N_2784(
        N_2784), .N_1007(N_1007), .N_2532(N_2532), .N_2778(N_2778), 
        .prdata_o195_0_a2_0(prdata_o195_0_a2_0), .prdata_o191(
        prdata_o191), .N_1508(N_1508), .N_2542(N_2542), .N_2791(N_2791)
        , .N_2734(N_2734), .N_2585(N_2585), .prdata_o190(prdata_o190), 
        .N_2606(N_2606), .N_2728(N_2728), .N_54(N_54), .N_157(N_157), 
        .N_151(N_151), .N_152(N_152), .N_153(N_153), .N_154(N_154), 
        .N_155(N_155), .N_156(N_156));
    MC_System_sb_CCC_0_FCCC CCC_0 (.MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FIC_0_CLK(
        MC_System_0_FIC_0_CLK), .MC_System_0_FAB_CCC_GL1(
        MC_System_0_FAB_CCC_GL1), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC_Z (.Y(VCC));
    MC_System_sb_MSS MC_System_sb_MSS_0 (.USB_ULPI_DATA({
        USB_ULPI_DATA[7], USB_ULPI_DATA[6], USB_ULPI_DATA[5], 
        USB_ULPI_DATA[4], USB_ULPI_DATA[3], USB_ULPI_DATA[2], 
        USB_ULPI_DATA[1], USB_ULPI_DATA[0]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_0(
        MC_System_0_AMBA_SLAVE_1_PADDR_0), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_1(
        MC_System_0_AMBA_SLAVE_1_PADDR_1), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_2(
        MC_System_0_AMBA_SLAVE_1_PADDR_2), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_3(
        MC_System_0_AMBA_SLAVE_1_PADDR_3), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_4(
        MC_System_0_AMBA_SLAVE_1_PADDR_4), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_5(
        MC_System_0_AMBA_SLAVE_1_PADDR_5), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_6(
        MC_System_0_AMBA_SLAVE_1_PADDR_6), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_7(
        MC_System_0_AMBA_SLAVE_1_PADDR_7), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_8(
        MC_System_0_AMBA_SLAVE_1_PADDR_8), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_9(
        MC_System_0_AMBA_SLAVE_1_PADDR_9), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_10(
        MC_System_0_AMBA_SLAVE_1_PADDR_10), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_11(
        MC_System_0_AMBA_SLAVE_1_PADDR_11), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_12(
        MC_System_0_AMBA_SLAVE_1_PADDR[12]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_13(
        MC_System_0_AMBA_SLAVE_1_PADDR[13]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_14(
        MC_System_0_AMBA_SLAVE_1_PADDR[14]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_15(
        MC_System_0_AMBA_SLAVE_1_PADDR[15]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_0(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_1(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_2(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_3(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_4(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_5(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_6(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_7(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_8(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_9(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_10(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_11(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_12(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_13(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_14(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_15(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_16(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_17(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_18(
        MC_System_0_AMBA_SLAVE_1_PWDATA[18]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_19(
        MC_System_0_AMBA_SLAVE_1_PWDATA[19]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_20(
        MC_System_0_AMBA_SLAVE_1_PWDATA[20]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_21(
        MC_System_0_AMBA_SLAVE_1_PWDATA[21]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_22(
        MC_System_0_AMBA_SLAVE_1_PWDATA[22]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA_23(
        MC_System_0_AMBA_SLAVE_1_PWDATA[23]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[7]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[8]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[10]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[12]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[14]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[15]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_18(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_19(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[19]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_20(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[20]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_21(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[21]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_22(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[22]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]), 
        .USB_ULPI_XCLK(USB_ULPI_XCLK), .USB_ULPI_STP(USB_ULPI_STP), 
        .USB_ULPI_NXT(USB_ULPI_NXT), .USB_ULPI_DIR(USB_ULPI_DIR), 
        .MC_System_0_AMBA_SLAVE_1_PENABLE(
        MC_System_0_AMBA_SLAVE_1_PENABLE), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx), 
        .MC_System_0_AMBA_SLAVE_1_PWRITE(
        MC_System_0_AMBA_SLAVE_1_PWRITE), .GPIO_0_M2F_c(GPIO_0_M2F_c), 
        .MC_System_0_FIC_0_LOCK(MC_System_0_FIC_0_LOCK), 
        .MC_System_0_FIC_0_CLK(MC_System_0_FIC_0_CLK));
    GND GND_Z (.Y(GND));
    
endmodule


module MC_System(
       prdata_o_1_0,
       ADC_SCALING_0_ib_adc_o,
       STEPPER_THETA_1_step_count_o,
       adc_interface_0_result_ch0_o,
       adc_interface_0_result_ch2_o,
       adc_measurements_0_adc_result_ch3_o,
       adc_measurements_0_adc_result_ch1_o,
       SEQ_CONTROLLER_1_state_o_0,
       prdata_o_1_0_a2_12_0,
       prdata_o_1_0_a2_10_0,
       FOC_TRANSFORMS_1_valpha_o,
       prdata_o_1_iv_12_1,
       FOC_TRANSFORMS_0_vbeta_o,
       prdata_o_1_iv_12_0_2,
       SPEED_ID_IQ_PI_1_iq_pi_output_o,
       FOC_TRANSFORMS_0_iq_o_0,
       FOC_TRANSFORMS_0_iq_o_9,
       FOC_TRANSFORMS_0_id_o_0,
       FOC_TRANSFORMS_0_id_o_9,
       prdata_o_1_iv_9,
       SPEED_ID_IQ_PI_1_id_pi_output_o_m,
       prdata_o_1_0_1,
       prdata_o_1_0_2,
       prdata_o_1_0_0,
       prdata_o_1_3,
       prdata_o_1_4,
       prdata_o_1_2,
       prdata_o_1_24_3,
       prdata_o_1_24_4,
       prdata_o_1_24_2,
       prdata_o_1_12_2,
       prdata_o_1_12_3,
       prdata_o_1_12_1,
       prdata_o_1_0_iv_6,
       prdata_o_1_0_iv_7,
       prdata_o_1_0_iv_10,
       prdata_o_1_0_iv_11,
       prdata_o_1_iv_11_0,
       prdata_o_1_iv_11_1,
       prdata_o_1_iv_11_3,
       prdata_o_1_iv_12,
       USB_ULPI_DATA,
       MC_System_0_AMBA_SLAVE_1_PADDR,
       MC_System_0_AMBA_SLAVE_1_PWDATA,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       MC_System_0_FAB_CCC_GL1,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       MC_System_0_AMBA_SLAVE_1_PSELx,
       N_2661,
       N_1077,
       N_2660,
       N_2785,
       N_1014,
       N_2779,
       N_2704,
       N_184,
       adc_channel_ch3_o_1_sqmuxa_0_a2_0_0,
       N_172,
       N_174,
       prdata_o197_0_a2_0_a2_0_out,
       prdata_o201_0_a2_0_0,
       N_201,
       N_193,
       N_187,
       N_2470,
       g2,
       g1,
       N_106,
       N_108,
       N_202,
       N_1083,
       N_104,
       N_179,
       N_107,
       N_105,
       N_233,
       N_194,
       N_1080,
       N_2522,
       N_2784,
       N_1007,
       N_2532,
       N_2778,
       prdata_o195_0_a2_0,
       prdata_o191,
       N_1508,
       N_2542,
       N_2791,
       N_2734,
       N_2585,
       prdata_o190,
       N_2606,
       N_2728,
       N_54,
       N_157,
       N_151,
       N_152,
       N_153,
       N_154,
       N_155,
       N_156,
       USB_ULPI_XCLK,
       USB_ULPI_STP,
       USB_ULPI_NXT,
       USB_ULPI_DIR,
       MC_System_0_AMBA_SLAVE_1_PENABLE,
       MC_System_0_AMBA_SLAVE_1_PWRITE,
       GPIO_0_M2F_c
    );
input  [3:3] prdata_o_1_0;
input  [2:2] ADC_SCALING_0_ib_adc_o;
input  [2:2] STEPPER_THETA_1_step_count_o;
input  [2:2] adc_interface_0_result_ch0_o;
input  [2:2] adc_interface_0_result_ch2_o;
input  [2:2] adc_measurements_0_adc_result_ch3_o;
input  [2:2] adc_measurements_0_adc_result_ch1_o;
input  [2:2] SEQ_CONTROLLER_1_state_o_0;
input  [15:15] prdata_o_1_0_a2_12_0;
input  [15:15] prdata_o_1_0_a2_10_0;
input  [11:11] FOC_TRANSFORMS_1_valpha_o;
input  [3:3] prdata_o_1_iv_12_1;
input  [11:11] FOC_TRANSFORMS_0_vbeta_o;
input  [3:3] prdata_o_1_iv_12_0_2;
input  [0:0] SPEED_ID_IQ_PI_1_iq_pi_output_o;
input  FOC_TRANSFORMS_0_iq_o_0;
input  FOC_TRANSFORMS_0_iq_o_9;
input  FOC_TRANSFORMS_0_id_o_0;
input  FOC_TRANSFORMS_0_id_o_9;
input  [0:0] prdata_o_1_iv_9;
input  [0:0] SPEED_ID_IQ_PI_1_id_pi_output_o_m;
input  [16:12] prdata_o_1_0_1;
input  [16:12] prdata_o_1_0_2;
input  [16:12] prdata_o_1_0_0;
input  [3:2] prdata_o_1_3;
input  [2:2] prdata_o_1_4;
input  [3:2] prdata_o_1_2;
input  [1:1] prdata_o_1_24_3;
input  [1:1] prdata_o_1_24_4;
input  [1:1] prdata_o_1_24_2;
input  [11:4] prdata_o_1_12_2;
input  [11:4] prdata_o_1_12_3;
input  [11:4] prdata_o_1_12_1;
input  [16:12] prdata_o_1_0_iv_6;
input  [16:12] prdata_o_1_0_iv_7;
input  [10:4] prdata_o_1_0_iv_10;
input  [10:4] prdata_o_1_0_iv_11;
input  prdata_o_1_iv_11_0;
input  prdata_o_1_iv_11_1;
input  prdata_o_1_iv_11_3;
input  [3:1] prdata_o_1_iv_12;
inout  [7:0] USB_ULPI_DATA;
inout  [11:0] MC_System_0_AMBA_SLAVE_1_PADDR;
output [23:0] MC_System_0_AMBA_SLAVE_1_PWDATA;
output MC_System_0_FIC_0_LOCK;
output MC_System_0_FIC_0_CLK;
output MC_System_0_FAB_CCC_GL1;
output MC_System_0_AMBA_SLAVE_0_PSELx;
output MC_System_0_AMBA_SLAVE_1_PSELx;
input  N_2661;
input  N_1077;
input  N_2660;
input  N_2785;
input  N_1014;
input  N_2779;
input  N_2704;
input  N_184;
input  adc_channel_ch3_o_1_sqmuxa_0_a2_0_0;
input  N_172;
input  N_174;
input  prdata_o197_0_a2_0_a2_0_out;
input  prdata_o201_0_a2_0_0;
input  N_201;
input  N_193;
input  N_187;
input  N_2470;
input  g2;
input  g1;
input  N_106;
input  N_108;
input  N_202;
input  N_1083;
input  N_104;
input  N_179;
input  N_107;
input  N_105;
input  N_233;
input  N_194;
input  N_1080;
input  N_2522;
input  N_2784;
input  N_1007;
input  N_2532;
input  N_2778;
input  prdata_o195_0_a2_0;
input  prdata_o191;
input  N_1508;
input  N_2542;
input  N_2791;
input  N_2734;
input  N_2585;
input  prdata_o190;
input  N_2606;
input  N_2728;
input  N_54;
input  N_157;
input  N_151;
input  N_152;
input  N_153;
input  N_154;
input  N_155;
input  N_156;
input  USB_ULPI_XCLK;
output USB_ULPI_STP;
input  USB_ULPI_NXT;
input  USB_ULPI_DIR;
output MC_System_0_AMBA_SLAVE_1_PENABLE;
output MC_System_0_AMBA_SLAVE_1_PWRITE;
output GPIO_0_M2F_c;

    wire GND, VCC;
    
    VCC VCC_Z (.Y(VCC));
    MC_System_sb MC_System_sb_0 (.prdata_o_1_0({prdata_o_1_0[3]}), 
        .ADC_SCALING_0_ib_adc_o({ADC_SCALING_0_ib_adc_o[2]}), 
        .STEPPER_THETA_1_step_count_o({STEPPER_THETA_1_step_count_o[2]})
        , .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[2]}), 
        .adc_interface_0_result_ch2_o({adc_interface_0_result_ch2_o[2]})
        , .adc_measurements_0_adc_result_ch3_o({
        adc_measurements_0_adc_result_ch3_o[2]}), 
        .adc_measurements_0_adc_result_ch1_o({
        adc_measurements_0_adc_result_ch1_o[2]}), 
        .SEQ_CONTROLLER_1_state_o_0({SEQ_CONTROLLER_1_state_o_0[2]}), 
        .prdata_o_1_0_a2_12_0({prdata_o_1_0_a2_12_0[15]}), 
        .prdata_o_1_0_a2_10_0({prdata_o_1_0_a2_10_0[15]}), 
        .FOC_TRANSFORMS_1_valpha_o({FOC_TRANSFORMS_1_valpha_o[11]}), 
        .prdata_o_1_iv_12_1({prdata_o_1_iv_12_1[3]}), 
        .FOC_TRANSFORMS_0_vbeta_o({FOC_TRANSFORMS_0_vbeta_o[11]}), 
        .prdata_o_1_iv_12_0_2({prdata_o_1_iv_12_0_2[3]}), 
        .SPEED_ID_IQ_PI_1_iq_pi_output_o({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]}), .FOC_TRANSFORMS_0_iq_o_0(
        FOC_TRANSFORMS_0_iq_o_0), .FOC_TRANSFORMS_0_iq_o_9(
        FOC_TRANSFORMS_0_iq_o_9), .FOC_TRANSFORMS_0_id_o_0(
        FOC_TRANSFORMS_0_id_o_0), .FOC_TRANSFORMS_0_id_o_9(
        FOC_TRANSFORMS_0_id_o_9), .prdata_o_1_iv_9({prdata_o_1_iv_9[0]})
        , .SPEED_ID_IQ_PI_1_id_pi_output_o_m({
        SPEED_ID_IQ_PI_1_id_pi_output_o_m[0]}), .prdata_o_1_0_1({
        prdata_o_1_0_1[16], prdata_o_1_0_1[15], prdata_o_1_0_1[14], 
        prdata_o_1_0_1[13], prdata_o_1_0_1[12]}), .prdata_o_1_0_2({
        prdata_o_1_0_2[16], prdata_o_1_0_2[15], prdata_o_1_0_2[14], 
        prdata_o_1_0_2[13], prdata_o_1_0_2[12]}), .prdata_o_1_0_0({
        prdata_o_1_0_0[16], prdata_o_1_0_0[15], prdata_o_1_0_0[14], 
        prdata_o_1_0_0[13], prdata_o_1_0_0[12]}), .prdata_o_1_3({
        prdata_o_1_3[3], prdata_o_1_3[2]}), .prdata_o_1_4({
        prdata_o_1_4[2]}), .prdata_o_1_2({prdata_o_1_2[3], 
        prdata_o_1_2[2]}), .prdata_o_1_24_3({prdata_o_1_24_3[1]}), 
        .prdata_o_1_24_4({prdata_o_1_24_4[1]}), .prdata_o_1_24_2({
        prdata_o_1_24_2[1]}), .prdata_o_1_12_2({prdata_o_1_12_2[11], 
        prdata_o_1_12_2[10], prdata_o_1_12_2[9], prdata_o_1_12_2[8], 
        prdata_o_1_12_2[7], prdata_o_1_12_2[6], prdata_o_1_12_2[5], 
        prdata_o_1_12_2[4]}), .prdata_o_1_12_3({prdata_o_1_12_3[11], 
        prdata_o_1_12_3[10], prdata_o_1_12_3[9], prdata_o_1_12_3[8], 
        prdata_o_1_12_3[7], prdata_o_1_12_3[6], prdata_o_1_12_3[5], 
        prdata_o_1_12_3[4]}), .prdata_o_1_12_1({prdata_o_1_12_1[11], 
        prdata_o_1_12_1[10], prdata_o_1_12_1[9], prdata_o_1_12_1[8], 
        prdata_o_1_12_1[7], prdata_o_1_12_1[6], prdata_o_1_12_1[5], 
        prdata_o_1_12_1[4]}), .prdata_o_1_0_iv_6({
        prdata_o_1_0_iv_6[16], prdata_o_1_0_iv_6[15], 
        prdata_o_1_0_iv_6[14], prdata_o_1_0_iv_6[13], 
        prdata_o_1_0_iv_6[12]}), .prdata_o_1_0_iv_7({
        prdata_o_1_0_iv_7[16], prdata_o_1_0_iv_7[15], 
        prdata_o_1_0_iv_7[14], prdata_o_1_0_iv_7[13], 
        prdata_o_1_0_iv_7[12]}), .prdata_o_1_0_iv_10({
        prdata_o_1_0_iv_10[10], prdata_o_1_0_iv_10[9], 
        prdata_o_1_0_iv_10[8], prdata_o_1_0_iv_10[7], 
        prdata_o_1_0_iv_10[6], prdata_o_1_0_iv_10[5], 
        prdata_o_1_0_iv_10[4]}), .prdata_o_1_0_iv_11({
        prdata_o_1_0_iv_11[10], prdata_o_1_0_iv_11[9], 
        prdata_o_1_0_iv_11[8], prdata_o_1_0_iv_11[7], 
        prdata_o_1_0_iv_11[6], prdata_o_1_0_iv_11[5], 
        prdata_o_1_0_iv_11[4]}), .prdata_o_1_iv_11_0(
        prdata_o_1_iv_11_0), .prdata_o_1_iv_11_1(prdata_o_1_iv_11_1), 
        .prdata_o_1_iv_11_3(prdata_o_1_iv_11_3), .prdata_o_1_iv_12({
        prdata_o_1_iv_12[3], prdata_o_1_iv_12[2], prdata_o_1_iv_12[1]})
        , .USB_ULPI_DATA({USB_ULPI_DATA[7], USB_ULPI_DATA[6], 
        USB_ULPI_DATA[5], USB_ULPI_DATA[4], USB_ULPI_DATA[3], 
        USB_ULPI_DATA[2], USB_ULPI_DATA[1], USB_ULPI_DATA[0]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_2(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_4(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_5(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_0(
        MC_System_0_AMBA_SLAVE_1_PADDR[0]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_1(
        MC_System_0_AMBA_SLAVE_1_PADDR[1]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_3(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_6(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_7(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_8(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_9(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_10(
        MC_System_0_AMBA_SLAVE_1_PADDR[10]), 
        .MC_System_0_AMBA_SLAVE_1_PADDR_11(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA({
        MC_System_0_AMBA_SLAVE_1_PWDATA[23], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[22], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[21], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[20], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[19], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[18], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FIC_0_CLK(
        MC_System_0_FIC_0_CLK), .MC_System_0_FAB_CCC_GL1(
        MC_System_0_FAB_CCC_GL1), .MC_System_0_AMBA_SLAVE_0_PSELx(
        MC_System_0_AMBA_SLAVE_0_PSELx), 
        .MC_System_0_AMBA_SLAVE_1_PSELx(MC_System_0_AMBA_SLAVE_1_PSELx)
        , .N_2661(N_2661), .N_1077(N_1077), .N_2660(N_2660), .N_2785(
        N_2785), .N_1014(N_1014), .N_2779(N_2779), .N_2704(N_2704), 
        .N_184(N_184), .adc_channel_ch3_o_1_sqmuxa_0_a2_0_0(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .N_172(N_172), .N_174(
        N_174), .prdata_o197_0_a2_0_a2_0_out(
        prdata_o197_0_a2_0_a2_0_out), .prdata_o201_0_a2_0_0(
        prdata_o201_0_a2_0_0), .N_201(N_201), .N_193(N_193), .N_187(
        N_187), .N_2470(N_2470), .g2(g2), .g1(g1), .N_106(N_106), 
        .N_108(N_108), .N_202(N_202), .N_1083(N_1083), .N_104(N_104), 
        .N_179(N_179), .N_107(N_107), .N_105(N_105), .N_233(N_233), 
        .N_194(N_194), .N_1080(N_1080), .N_2522(N_2522), .N_2784(
        N_2784), .N_1007(N_1007), .N_2532(N_2532), .N_2778(N_2778), 
        .prdata_o195_0_a2_0(prdata_o195_0_a2_0), .prdata_o191(
        prdata_o191), .N_1508(N_1508), .N_2542(N_2542), .N_2791(N_2791)
        , .N_2734(N_2734), .N_2585(N_2585), .prdata_o190(prdata_o190), 
        .N_2606(N_2606), .N_2728(N_2728), .N_54(N_54), .N_157(N_157), 
        .N_151(N_151), .N_152(N_152), .N_153(N_153), .N_154(N_154), 
        .N_155(N_155), .N_156(N_156), .USB_ULPI_XCLK(USB_ULPI_XCLK), 
        .USB_ULPI_STP(USB_ULPI_STP), .USB_ULPI_NXT(USB_ULPI_NXT), 
        .USB_ULPI_DIR(USB_ULPI_DIR), .MC_System_0_AMBA_SLAVE_1_PENABLE(
        MC_System_0_AMBA_SLAVE_1_PENABLE), 
        .MC_System_0_AMBA_SLAVE_1_PWRITE(
        MC_System_0_AMBA_SLAVE_1_PWRITE), .GPIO_0_M2F_c(GPIO_0_M2F_c));
    GND GND_Z (.Y(GND));
    
endmodule


module SVM(
       reset_i,
       sys_clk_i,
       start_i,
       va_i,
       vb_i,
       vc_i,
       va3h_o,
       vb3h_o,
       vc3h_o,
       done_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  [17:0] va_i;
input  [17:0] vb_i;
input  [17:0] vc_i;
output [17:0] va3h_o;
output [17:0] vb3h_o;
output [17:0] vc3h_o;
output done_o;

    wire [17:1] s_v3h;
    wire [17:1] s_min_value;
    wire [17:0] s_max_value;
    wire [1:0] s_state;
    wire [0:0] s_state_ns;
    wire [17:0] \SVM_FSM_PROC.s_max_value_8 ;
    wire [17:0] \SVM_FSM_PROC.s_min_value_8 ;
    wire [17:0] \SVM_FSM_PROC.s_min_value_8_am ;
    wire [17:0] \SVM_FSM_PROC.s_min_value_8_bm ;
    wire [17:0] \SVM_FSM_PROC.s_max_value_8_am ;
    wire [17:0] \SVM_FSM_PROC.s_max_value_8_bm ;
    wire MSC_net_275, MSC_net_276, MSC_net_277, MSC_net_278, 
        MSC_net_279, MSC_net_280, MSC_net_281, MSC_net_282, 
        MSC_net_283, MSC_net_284, MSC_net_285, MSC_net_286, 
        MSC_net_287, MSC_net_288, MSC_net_289, MSC_net_290, 
        MSC_net_291, MSC_net_292, MSC_net_293, MSC_net_294, 
        MSC_net_295, MSC_net_296, MSC_net_297, MSC_net_298, 
        MSC_net_299, MSC_net_300, MSC_net_301, MSC_net_302, 
        MSC_net_303, MSC_net_304, MSC_net_305, MSC_net_306, 
        MSC_net_307, MSC_net_308, MSC_net_309, MSC_net_310, 
        MSC_net_311, MSC_net_312, MSC_net_313, MSC_net_314, 
        MSC_net_315, MSC_net_316, MSC_net_317, MSC_net_318, 
        MSC_net_319, MSC_net_320, MSC_net_321, MSC_net_322, 
        MSC_net_323, MSC_net_324, MSC_net_325, MSC_net_326, 
        MSC_net_327, MSC_net_328, MSC_net_329, MSC_net_330, 
        MSC_net_331, MSC_net_332, MSC_net_333, MSC_net_334, 
        \SVM_FSM_PROC.s_min_value_8_sn_N_5 , 
        \SVM_FSM_PROC.s_max_value_8_sn_N_5 , MSC_net_337, MSC_net_338, 
        MSC_net_339, MSC_net_340, MSC_net_341, MSC_net_342, 
        MSC_net_343, MSC_net_344, MSC_net_345, MSC_net_346, 
        MSC_net_347, MSC_net_348, MSC_net_349, MSC_net_350, 
        MSC_net_351, MSC_net_352, MSC_net_353, MSC_net_354, 
        MSC_net_355, MSC_net_356, MSC_net_357, MSC_net_358, 
        MSC_net_359, MSC_net_360, MSC_net_361, MSC_net_362, 
        MSC_net_363, MSC_net_364, MSC_net_365, MSC_net_366, 
        MSC_net_367, MSC_net_368, MSC_net_369, MSC_net_370, 
        MSC_net_371, MSC_net_372, MSC_net_373, MSC_net_374, 
        MSC_net_375, MSC_net_376, MSC_net_377, MSC_net_378, 
        MSC_net_379, MSC_net_380, MSC_net_381, MSC_net_382, 
        MSC_net_383, MSC_net_384, MSC_net_385, MSC_net_386, 
        MSC_net_387, MSC_net_388, MSC_net_389, MSC_net_390, 
        MSC_net_391, MSC_net_392, MSC_net_393, MSC_net_394, 
        MSC_net_395, MSC_net_396, MSC_net_397, MSC_net_398, 
        MSC_net_399, MSC_net_400, MSC_net_401, MSC_net_402, 
        MSC_net_403, MSC_net_404, MSC_net_405, MSC_net_406, 
        MSC_net_407, MSC_net_408, MSC_net_409, MSC_net_410, 
        MSC_net_411, MSC_net_412, MSC_net_413, MSC_net_414, 
        MSC_net_415, MSC_net_416, MSC_net_417, MSC_net_418, 
        MSC_net_419, MSC_net_420, MSC_net_421, MSC_net_422, 
        MSC_net_423, MSC_net_424, MSC_net_425, MSC_net_426, 
        MSC_net_427, MSC_net_428, MSC_net_429, MSC_net_430, 
        MSC_net_431, MSC_net_432, MSC_net_433, MSC_net_434, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, MSC_net_442, 
        MSC_net_443, MSC_net_444, MSC_net_445, MSC_net_446, 
        MSC_net_447, MSC_net_448, MSC_net_449, MSC_net_450, 
        MSC_net_451, MSC_net_452, MSC_net_453, MSC_net_454, 
        MSC_net_455, MSC_net_456, MSC_net_457, MSC_net_458, 
        MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, MSC_net_470, 
        MSC_net_471, MSC_net_472, MSC_net_473, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488, MSC_net_489, MSC_net_490, 
        MSC_net_491, MSC_net_492, MSC_net_493, MSC_net_494, 
        MSC_net_495, MSC_net_496, MSC_net_497, MSC_net_498, 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, MSC_net_518, 
        MSC_net_519, MSC_net_520, MSC_net_521, MSC_net_522, 
        MSC_net_523, MSC_net_524, MSC_net_525, MSC_net_526, 
        MSC_net_527, MSC_net_528, MSC_net_529, MSC_net_530, 
        MSC_net_531, MSC_net_532, MSC_net_533, MSC_net_534, 
        MSC_net_535, MSC_net_536, MSC_net_537, MSC_net_538, 
        MSC_net_539, MSC_net_540, MSC_net_541, MSC_net_542, 
        MSC_net_543, MSC_net_544, MSC_net_545, MSC_net_546, 
        MSC_net_547, MSC_net_548, MSC_net_549, MSC_net_550, 
        MSC_net_551, MSC_net_552, MSC_net_553, MSC_net_554, 
        MSC_net_555, MSC_net_556, MSC_net_557, MSC_net_558, 
        MSC_net_559, MSC_net_560, MSC_net_561, MSC_net_562, 
        MSC_net_563, MSC_net_564, MSC_net_565, MSC_net_566, 
        MSC_net_567, MSC_net_568, MSC_net_569, MSC_net_570, 
        MSC_net_571, MSC_net_572, MSC_net_573, MSC_net_574, 
        MSC_net_575, MSC_net_576, MSC_net_577, MSC_net_578, 
        MSC_net_579, MSC_net_580, MSC_net_581, MSC_net_582, 
        MSC_net_583, MSC_net_584, MSC_net_585, MSC_net_586, 
        MSC_net_587, MSC_net_588, MSC_net_589, MSC_net_590, 
        MSC_net_591, MSC_net_592, MSC_net_593, MSC_net_594, 
        MSC_net_595, MSC_net_596, MSC_net_597, MSC_net_598, 
        MSC_net_599, MSC_net_600, MSC_net_601, MSC_net_602, 
        MSC_net_603, MSC_net_604, MSC_net_605, MSC_net_606, 
        MSC_net_607, MSC_net_608, MSC_net_609, MSC_net_610, 
        MSC_net_611, MSC_net_612, MSC_net_613, MSC_net_614, 
        MSC_net_615, MSC_net_616, MSC_net_617, MSC_net_618, 
        MSC_net_619, MSC_net_620, MSC_net_621, MSC_net_622, 
        MSC_net_623, MSC_net_624, MSC_net_625, MSC_net_626, 
        MSC_net_627, MSC_net_628, MSC_net_629, MSC_net_630, 
        MSC_net_631, MSC_net_632, MSC_net_633, MSC_net_634, 
        MSC_net_635, MSC_net_636, MSC_net_637, MSC_net_638, 
        MSC_net_639, MSC_net_640, MSC_net_641, MSC_net_642, 
        MSC_net_643, MSC_net_644, MSC_net_645, MSC_net_646;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
RWouaz2V3Lk2h5jrp6qzi1qV5IEXnNJUXq0kXpWT7GxPcWyxWvcIaWf3OM/BYpSi
vfHppWDNtfuOm7Qf+TeF1yr1fu73zaXLuxlbCvSQVIKdo8JHDvzyeoWWQuIDxbs0
2itmjIuNeFV2lfEaAKilRsZX67zbr56gj21NDYfoeP8=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=92650)
`pragma protect data_block
[encoded data, 91200 characters]
mjjY9+5EEYMFSplO9/R79Q==

`pragma protect end_protected

endmodule


module SEQ_CONTROLLER_Z1_layer1_1(
       SEQ_CONTROLLER_1_state_o,
       apb3_if_0_seq_cntl_cl_omega_o,
       RATE_LIMITER_0_rl_out_o,
       SPEED_ID_IQ_PI_1_iq_pi_output_o,
       apb3_if_0_seq_cntl_config_o,
       apb3_if_0_auto_restart_no_o,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       SEQ_CONTROLLER_1_adc_start_o,
       SEQ_CONTROLLER_0_cl_status_o,
       apb3_if_0_start_motor_o,
       apb3_if_0_fault_clr_o,
       ADC_SCALING_1_calib_done_o,
       apb3_if_0_stop_motor_o,
       N_2197_i,
       A0_PWM_VL_O_c_i_0,
       N_326_i_0,
       PWM_SCALING_1_done_o,
       N_2370_i_0,
       N_326,
       A0_PWM_VL_O_c,
       N_894_i_0,
       PWM3PH_1_midmatch_o
    );
output [3:0] SEQ_CONTROLLER_1_state_o;
input  [17:0] apb3_if_0_seq_cntl_cl_omega_o;
input  [17:0] RATE_LIMITER_0_rl_out_o;
input  [17:0] SPEED_ID_IQ_PI_1_iq_pi_output_o;
input  [3:0] apb3_if_0_seq_cntl_config_o;
input  [3:0] apb3_if_0_auto_restart_no_o;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;
output SEQ_CONTROLLER_1_adc_start_o;
output SEQ_CONTROLLER_0_cl_status_o;
input  apb3_if_0_start_motor_o;
input  apb3_if_0_fault_clr_o;
input  ADC_SCALING_1_calib_done_o;
input  apb3_if_0_stop_motor_o;
input  N_2197_i;
output A0_PWM_VL_O_c_i_0;
output N_326_i_0;
input  PWM_SCALING_1_done_o;
output N_2370_i_0;
output N_326;
output A0_PWM_VL_O_c;
output N_894_i_0;
input  PWM3PH_1_midmatch_o;

    wire [8:0] s_state;
    wire [3:0] s_restart_count;
    wire [8:0] s_state_ns;
    wire [12:0] s_adctrig_count;
    wire [12:0] s_adctrig_count_s;
    wire [13:0] s_sensor_calib_count;
    wire [13:0] s_sensor_calib_count_s;
    wire [2:1] s_state_fast;
    wire [1:1] s_state_RNIL5O9_S;
    wire [1:1] s_state_RNIL5O9_Y;
    wire [11:0] s_adctrig_count_cry;
    wire [0:0] s_adctrig_count_RNIP17O_Y;
    wire [1:1] s_adctrig_count_RNIUUL61_Y;
    wire [2:2] s_adctrig_count_RNI4T4L1_Y;
    wire [3:3] s_adctrig_count_RNIBSJ32_Y;
    wire [4:4] s_adctrig_count_RNIJS2I2_Y;
    wire [5:5] s_adctrig_count_RNISTH03_Y;
    wire [6:6] s_adctrig_count_RNI601F3_Y;
    wire [7:7] s_adctrig_count_RNIH3GT3_Y;
    wire [8:8] s_adctrig_count_RNIT7VB4_Y;
    wire [9:9] s_adctrig_count_RNIADEQ4_Y;
    wire [10:10] s_adctrig_count_RNIVEJF5_Y;
    wire [12:12] s_adctrig_count_RNO_FCO_0;
    wire [12:12] s_adctrig_count_RNO_Y_0;
    wire [11:11] s_adctrig_count_RNILHO46_Y;
    wire [13:13] s_sensor_calib_count_RNI5HLC_S;
    wire [13:13] s_sensor_calib_count_RNI5HLC_Y;
    wire [12:0] s_sensor_calib_count_cry;
    wire [0:0] s_sensor_calib_count_RNIADMK_Y;
    wire [1:1] s_sensor_calib_count_RNIGANS_Y;
    wire [2:2] s_sensor_calib_count_RNIN8O41_Y;
    wire [3:3] s_sensor_calib_count_RNIV7PC1_Y;
    wire [4:4] s_sensor_calib_count_RNI88QK1_Y;
    wire [5:5] s_sensor_calib_count_RNII9RS1_Y;
    wire [6:6] s_sensor_calib_count_RNITBS42_Y;
    wire [7:7] s_sensor_calib_count_RNI9FTC2_Y;
    wire [8:8] s_sensor_calib_count_RNIMJUK2_Y;
    wire [9:9] s_sensor_calib_count_RNI4PVS2_Y;
    wire [10:10] s_sensor_calib_count_RNIQGS53_Y;
    wire [11:11] s_sensor_calib_count_RNIH9PE3_Y;
    wire [13:13] s_sensor_calib_count_RNO_FCO_0;
    wire [13:13] s_sensor_calib_count_RNO_Y_0;
    wire [12:12] s_sensor_calib_count_RNI93MN3_Y;
    wire [17:0] inf_abs0;
    wire [17:0] inf_abs1;
    wire [1:1] s_state_ns_i_0_0_0_0;
    wire [6:6] s_state_ns_i_2_1;
    wire [6:6] s_state_ns_i_3_a1_1;
    wire [6:6] s_state_ns_i_3_a0_2;
    wire [6:6] s_state_ns_i_a2_33_1;
    wire [6:6] s_state_ns_i_o3_26_0_0_a2_0_0_2;
    wire [6:6] s_state_ns_i_3_a1_1_1;
    wire [6:6] s_state_ns_i_o3_26_0_0_a2_0_0_2_1;
    wire [7:7] s_state_ns_i_a2_28_0;
    wire [0:0] s_state_ns_0_0;
    wire [0:0] s_state_ns_0_a2_2;
    wire [2:2] s_restart_count_4_i_0_o3_0_0;
    wire [4:4] s_state_ns_i_i_2_0_4_i_m2_a3;
    wire [0:0] s_state_ns_0_a2_3_1;
    wire [1:1] s_restart_count_4_i_0_o2_0;
    wire [7:7] s_state_ns_i_o2_10_i_a2_0;
    wire [4:4] s_state_ns_i_i_2_0_4_i_a2_4_0;
    wire [4:4] s_state_ns_i_i_2_0_4_i_m2_a0_2;
    wire [4:4] s_state_ns_i_i_2_0_4_i_o2_2_0;
    wire [3:3] s_state_ns_i_i_i_0;
    wire [5:5] s_state_ns_i_i_a2_i_15_i_i_2;
    wire [0:0] s_state_ns_0_a2_0_1;
    wire [4:4] s_state_ns_i_i_2_0_4_i_a2_4_1;
    wire [5:5] s_state_ns_i_i_a2_i_15_i_i_3;
    wire [4:4] s_state_ns_i_i_2_0_4_i_m2_a0;
    wire [5:5] s_state_ns_i_i_a2_i_15_i_i_5;
    wire [4:4] s_state_ns_i_i_2_0_4_i_3_1;
    wire [3:3] s_state_ns_i_i_i_2;
    wire VCC, N_893_i_0, GND, N_892_i_0, N_1542_i_0, N_254_i_0, 
        N_2369_i_0, N_258_i_0, N_260_i_0, s_sensor_calib_rr_Z, 
        N_109_i_0, N_222_i_0, N_356, N_224_i_0, N_212_i_0, N_294_i_0, 
        N_84_i_0, N_79_i_0, N_170_i_0, adc_start_o_4, cl_status_o5, 
        s_start_motor_dly_Z, s_fault_clear_sync_Z, N_572_li, N_162_i_0, 
        adc_start_o5, N_294_i_0_fast, N_212_i_0_fast, 
        s_adctrig_count_cry_cy, s_sensor_calib_count_cry_cy, 
        un1_inf_abs1_cry_0, un1_inf_abs1_cry_0_S, un1_inf_abs1_cry_0_Y, 
        un1_inf_abs1_cry_1, un1_inf_abs1_cry_1_S, un1_inf_abs1_cry_1_Y, 
        un1_inf_abs1_cry_2, un1_inf_abs1_cry_2_S, un1_inf_abs1_cry_2_Y, 
        un1_inf_abs1_cry_3, un1_inf_abs1_cry_3_S, un1_inf_abs1_cry_3_Y, 
        un1_inf_abs1_cry_4, un1_inf_abs1_cry_4_S, un1_inf_abs1_cry_4_Y, 
        un1_inf_abs1_cry_5, un1_inf_abs1_cry_5_S, un1_inf_abs1_cry_5_Y, 
        un1_inf_abs1_cry_6, un1_inf_abs1_cry_6_S, un1_inf_abs1_cry_6_Y, 
        un1_inf_abs1_cry_7, un1_inf_abs1_cry_7_S, un1_inf_abs1_cry_7_Y, 
        un1_inf_abs1_cry_8, un1_inf_abs1_cry_8_S, un1_inf_abs1_cry_8_Y, 
        un1_inf_abs1_cry_9, un1_inf_abs1_cry_9_S, un1_inf_abs1_cry_9_Y, 
        un1_inf_abs1_cry_10, un1_inf_abs1_cry_10_S, 
        un1_inf_abs1_cry_10_Y, un1_inf_abs1_cry_11, 
        un1_inf_abs1_cry_11_S, un1_inf_abs1_cry_11_Y, 
        un1_inf_abs1_cry_12, un1_inf_abs1_cry_12_S, 
        un1_inf_abs1_cry_12_Y, un1_inf_abs1_cry_13, 
        un1_inf_abs1_cry_13_S, un1_inf_abs1_cry_13_Y, 
        un1_speed_cl_i_cry_0, un1_speed_cl_i_cry_0_S, 
        un1_speed_cl_i_cry_0_Y, un1_speed_cl_i_cry_1, 
        un1_speed_cl_i_cry_1_S, un1_speed_cl_i_cry_1_Y, 
        un1_speed_cl_i_cry_2, un1_speed_cl_i_cry_2_S, 
        un1_speed_cl_i_cry_2_Y, un1_speed_cl_i_cry_3, 
        un1_speed_cl_i_cry_3_S, un1_speed_cl_i_cry_3_Y, 
        un1_speed_cl_i_cry_4, un1_speed_cl_i_cry_4_S, 
        un1_speed_cl_i_cry_4_Y, un1_speed_cl_i_cry_5, 
        un1_speed_cl_i_cry_5_S, un1_speed_cl_i_cry_5_Y, 
        un1_speed_cl_i_cry_6, un1_speed_cl_i_cry_6_S, 
        un1_speed_cl_i_cry_6_Y, un1_speed_cl_i_cry_7, 
        un1_speed_cl_i_cry_7_S, un1_speed_cl_i_cry_7_Y, 
        un1_speed_cl_i_cry_8, un1_speed_cl_i_cry_8_S, 
        un1_speed_cl_i_cry_8_Y, un1_speed_cl_i_cry_9, 
        un1_speed_cl_i_cry_9_S, un1_speed_cl_i_cry_9_Y, 
        un1_speed_cl_i_cry_10, un1_speed_cl_i_cry_10_S, 
        un1_speed_cl_i_cry_10_Y, un1_speed_cl_i_cry_11, 
        un1_speed_cl_i_cry_11_S, un1_speed_cl_i_cry_11_Y, 
        un1_speed_cl_i_cry_12, un1_speed_cl_i_cry_12_S, 
        un1_speed_cl_i_cry_12_Y, un1_speed_cl_i_cry_13, 
        un1_speed_cl_i_cry_13_S, un1_speed_cl_i_cry_13_Y, 
        un1_speed_cl_i_cry_14, un1_speed_cl_i_cry_14_S, 
        un1_speed_cl_i_cry_14_Y, un1_speed_cl_i_cry_15, 
        un1_speed_cl_i_cry_15_S, un1_speed_cl_i_cry_15_Y, 
        un1_speed_cl_i_cry_16, un1_speed_cl_i_cry_16_S, 
        un1_speed_cl_i_cry_16_Y, un1_speed_cl_i, 
        un1_speed_cl_i_cry_17_S, un1_speed_cl_i_cry_17_Y, 
        un1_inf_abs0_2_cry_0, un1_inf_abs0_2_cry_0_S, 
        un1_inf_abs0_2_cry_0_Y, un1_inf_abs0_2_cry_1, 
        un1_inf_abs0_2_cry_1_S, un1_inf_abs0_2_cry_1_Y, 
        un1_inf_abs0_2_cry_2, un1_inf_abs0_2_cry_2_S, 
        un1_inf_abs0_2_cry_2_Y, un1_inf_abs0_2_cry_3, 
        un1_inf_abs0_2_cry_3_S, un1_inf_abs0_2_cry_3_Y, 
        un1_inf_abs0_2_cry_4, un1_inf_abs0_2_cry_4_S, 
        un1_inf_abs0_2_cry_4_Y, un1_inf_abs0_2_cry_5, 
        un1_inf_abs0_2_cry_5_S, un1_inf_abs0_2_cry_5_Y, 
        un1_inf_abs0_2_cry_6, un1_inf_abs0_2_cry_6_S, 
        un1_inf_abs0_2_cry_6_Y, un1_inf_abs0_2_cry_7, 
        un1_inf_abs0_2_cry_7_S, un1_inf_abs0_2_cry_7_Y, 
        un1_inf_abs0_2_cry_8, un1_inf_abs0_2_cry_8_S, 
        un1_inf_abs0_2_cry_8_Y, un1_inf_abs0_2_cry_9, 
        un1_inf_abs0_2_cry_9_S, un1_inf_abs0_2_cry_9_Y, 
        un1_inf_abs0_2_cry_10, un1_inf_abs0_2_cry_10_S, 
        un1_inf_abs0_2_cry_10_Y, un1_inf_abs0_2_cry_11, 
        un1_inf_abs0_2_cry_11_S, un1_inf_abs0_2_cry_11_Y, 
        un1_inf_abs0_2_cry_12, un1_inf_abs0_2_cry_12_S, 
        un1_inf_abs0_2_cry_12_Y, un1_inf_abs0_2_cry_13, 
        un1_inf_abs0_2_cry_13_S, un1_inf_abs0_2_cry_13_Y, 
        un1_inf_abs0_2_cry_14, un1_inf_abs0_2_cry_14_S, 
        un1_inf_abs0_2_cry_14_Y, un1_inf_abs0_2_cry_15, 
        un1_inf_abs0_2_cry_15_S, un1_inf_abs0_2_cry_15_Y, 
        un1_inf_abs0_2_cry_16, un1_inf_abs0_2_cry_16_S, 
        un1_inf_abs0_2_cry_16_Y, un1_inf_abs0_2, 
        un1_inf_abs0_2_cry_17_S, un1_inf_abs0_2_cry_17_Y, 
        inf_abs0_s_0_172_FCO, inf_abs0_s_0_172_S, inf_abs0_s_0_172_Y, 
        inf_abs0_cry_0_Z, inf_abs0_cry_0_Y, inf_abs0_cry_1_Z, 
        inf_abs0_cry_1_Y, inf_abs0_cry_2_Z, inf_abs0_cry_2_Y, 
        inf_abs0_cry_3_Z, inf_abs0_cry_3_Y, inf_abs0_cry_4_Z, 
        inf_abs0_cry_4_Y, inf_abs0_cry_5_Z, inf_abs0_cry_5_Y, 
        inf_abs0_cry_6_Z, inf_abs0_cry_6_Y, inf_abs0_cry_7_Z, 
        inf_abs0_cry_7_Y, inf_abs0_cry_8_Z, inf_abs0_cry_8_Y, 
        inf_abs0_cry_9_Z, inf_abs0_cry_9_Y, inf_abs0_cry_10_Z, 
        inf_abs0_cry_10_Y, inf_abs0_cry_11_Z, inf_abs0_cry_11_Y, 
        inf_abs0_cry_12_Z, inf_abs0_cry_12_Y, inf_abs0_cry_13_Z, 
        inf_abs0_cry_13_Y, inf_abs0_cry_14_Z, inf_abs0_cry_14_Y, 
        inf_abs0_cry_15_Z, inf_abs0_cry_15_Y, inf_abs0_cry_16_Y, 
        un1_inf_abs1_cry_14, inf_abs1_cry_14_RNIE4MR_S, 
        inf_abs1_cry_14_RNIE4MR_Y, un1_inf_abs1_cry_15, 
        inf_abs1_cry_15_RNIIDM31_S, inf_abs1_cry_15_RNIIDM31_Y, 
        un1_inf_abs1_cry_16, inf_abs1_cry_16_RNINMMB1_S, 
        inf_abs1_cry_16_RNINMMB1_Y, un1_inf_abs1, 
        inf_abs1_cry_16_RNISVMJ1_S, inf_abs1_cry_16_RNISVMJ1_Y, 
        inf_abs1_s_0_173_FCO, inf_abs1_s_0_173_S, inf_abs1_s_0_173_Y, 
        inf_abs1_cry_0_Z, inf_abs1_cry_0_Y, inf_abs1_cry_1_Z, 
        inf_abs1_cry_1_Y, inf_abs1_cry_2_Z, inf_abs1_cry_2_Y, 
        inf_abs1_cry_3_Z, inf_abs1_cry_3_Y, inf_abs1_cry_4_Z, 
        inf_abs1_cry_4_Y, inf_abs1_cry_5_Z, inf_abs1_cry_5_Y, 
        inf_abs1_cry_6_Z, inf_abs1_cry_6_Y, inf_abs1_cry_7_Z, 
        inf_abs1_cry_7_Y, inf_abs1_cry_8_Z, inf_abs1_cry_8_Y, 
        inf_abs1_cry_9_Z, inf_abs1_cry_9_Y, inf_abs1_cry_10_Z, 
        inf_abs1_cry_10_Y, inf_abs1_cry_11_Z, inf_abs1_cry_11_Y, 
        inf_abs1_cry_12_Z, inf_abs1_cry_12_Y, inf_abs1_cry_13_Z, 
        inf_abs1_cry_13_Y, inf_abs1_cry_14_Z, inf_abs1_cry_14_Y, 
        inf_abs1_cry_15_Z, inf_abs1_cry_15_Y, inf_abs1_cry_16_Y, N_231, 
        N_253, N_216, N_205, N_187, N_294_i_1, N_1082, N_222_i_1, 
        N_203, N_243, N_185, un1_max_ar_i_NE, adc_start_o5_8, 
        adc_start_o5_7, adc_start_o5_1, N_224_i_1, N_667, N_2481, 
        N_226, N_213, N_499, N_477, N_508, N_403, N_401, N_208, 
        un1_inf_abs0_1_14_3, N_482_i_0_i_0_i_o2_0_o3_6, 
        un1_inf_abs0_1_8, s_state87, un1_max_ar_i_0, 
        un1_inf_abs0_1_14_4, s_m6_0_a2_2, N_482_i_0_i_0_i_o2_0_o3_9, 
        N_482_i_0_i_0_i_o2_0_o3_8, N_482_i_0_i_0_i_o2_0_o3_7, 
        un1_max_ar_i_NE_0, un1_inf_abs0_1_12, un1_inf_abs0_1_9, 
        s_state88, s_state_0_sqmuxa_1_out, N_212, N_268, N_305, 
        N_440_i, N_498, s_state_1_sqmuxa_1_0_0_Z, d_m6_1, s_N_13_mux, 
        un1_inf_abs0_1_14, N_435, un1_inf_abs0_1_1, N_430, 
        un1_stop_motor_i_1, un1_inf_abs0_1, N_288, d_N_7, N_199, N_215, 
        N_219, N_451, N_264, N_218, N_511, N_113, N_112, N_111, N_110, 
        N_109, N_108, N_107, N_106, N_105;
    
    CFG4 #( .INIT(16'h0200) )  \s_state_ns_i_i_2_0_4_i_m2_a3[4]  (.A(
        s_state[1]), .B(s_state[2]), .C(apb3_if_0_seq_cntl_config_o[1])
        , .D(ADC_SCALING_1_calib_done_o), .Y(
        s_state_ns_i_i_2_0_4_i_m2_a3[4]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_6 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_5_Z), .S(inf_abs1[6]), .Y(inf_abs1_cry_6_Y), .FCO(
        inf_abs1_cry_6_Z));
    CFG2 #( .INIT(4'h8) )  \s_state_ns_0_a2_6[0]  (.A(N_477), .B(
        s_state[6]), .Y(N_508));
    SLE \s_sensor_calib_count[3]  (.D(s_sensor_calib_count_s[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[3]));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_0 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[0]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_s_0_172_FCO), .S(inf_abs0[0]), .Y(
        inf_abs0_cry_0_Y), .FCO(inf_abs0_cry_0_Z));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNILHO46[11]  (.A(VCC)
        , .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[11]), .D(GND), 
        .FCI(s_adctrig_count_cry[10]), .S(s_adctrig_count_s[11]), .Y(
        s_adctrig_count_RNILHO46_Y[11]), .FCO(s_adctrig_count_cry[11]));
    CFG3 #( .INIT(8'h20) )  s_state_0_sqmuxa_1_s (.A(
        apb3_if_0_seq_cntl_config_o[3]), .B(N_2197_i), .C(
        PWM_SCALING_1_done_o), .Y(s_state_0_sqmuxa_1_out));
    CFG4 #( .INIT(16'hFCFE) )  \s_state_ns_i_i_2_0_4_i_o2[4]  (.A(
        N_356), .B(N_2481), .C(N_451), .D(un1_inf_abs0_1), .Y(N_218));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_5  (.A(inf_abs0[5]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[5]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_4), .S(un1_speed_cl_i_cry_5_S), .Y(
        un1_speed_cl_i_cry_5_Y), .FCO(un1_speed_cl_i_cry_5));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_15  (.A(inf_abs0[15]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[15]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_14), .S(un1_speed_cl_i_cry_15_S), .Y(
        un1_speed_cl_i_cry_15_Y), .FCO(un1_speed_cl_i_cry_15));
    SLE \s_adctrig_count[7]  (.D(s_adctrig_count_s[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[7]));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_12 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[12]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_11_Z), .S(inf_abs0[12]), .Y(
        inf_abs0_cry_12_Y), .FCO(inf_abs0_cry_12_Z));
    CFG4 #( .INIT(16'hF0F8) )  \s_state_ns_i_i_i_o3[3]  (.A(
        un1_inf_abs0_1_14), .B(un1_inf_abs0_1_1), .C(s_state[5]), .D(
        s_restart_count_4_i_0_o2_0[1]), .Y(N_215));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIMJUK2[8]  (.A(
        VCC), .B(s_sensor_calib_count[8]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[7]), .S(s_sensor_calib_count_s[8]), 
        .Y(s_sensor_calib_count_RNIMJUK2_Y[8]), .FCO(
        s_sensor_calib_count_cry[8]));
    CFG3 #( .INIT(8'hFE) )  \s_state_ns_i_i_2_0_4_i_o2_0[4]  (.A(
        s_state[8]), .B(N_435), .C(N_430), .Y(N_231));
    CFG2 #( .INIT(4'h1) )  \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_8  
        (.A(inf_abs0[16]), .B(inf_abs0[15]), .Y(un1_inf_abs0_1_8));
    CFG4 #( .INIT(16'hFFF6) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_max_ar_i_NE  (.A(
        s_restart_count[1]), .B(apb3_if_0_auto_restart_no_o[1]), .C(
        un1_max_ar_i_NE_0), .D(un1_max_ar_i_0), .Y(un1_max_ar_i_NE));
    CFG4 #( .INIT(16'h5101) )  \s_state_RNO[3]  (.A(
        s_state_ns_i_i_i_2[3]), .B(N_511), .C(s_state[3]), .D(
        un1_inf_abs0_2), .Y(N_84_i_0));
    CFG2 #( .INIT(4'h8) )  \s_state_RNIE9HI[6]  (.A(s_state[6]), .B(
        apb3_if_0_seq_cntl_config_o[3]), .Y(N_2370_i_0));
    CFG4 #( .INIT(16'h0800) )  \s_state_ns_i_i_2_0_4_i_m2_a0_2[4]  (.A(
        s_state[2]), .B(s_state_0_sqmuxa_1_out), .C(N_203), .D(
        un1_inf_abs0_1_8), .Y(s_state_ns_i_i_2_0_4_i_m2_a0_2[4]));
    SLE \s_sensor_calib_count[10]  (.D(s_sensor_calib_count_s[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[10]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNISTH03[5]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[5]), .D(GND), 
        .FCI(s_adctrig_count_cry[4]), .S(s_adctrig_count_s[5]), .Y(
        s_adctrig_count_RNISTH03_Y[5]), .FCO(s_adctrig_count_cry[5]));
    SLE \s_adctrig_count[2]  (.D(s_adctrig_count_s[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[2]));
    CFG4 #( .INIT(16'h5F57) )  s_state_1_sqmuxa_1_0_0_RNINSAS (.A(
        s_state[6]), .B(s_state87), .C(s_state_1_sqmuxa_1_0_0_Z), .D(
        un1_inf_abs0_1), .Y(N_264));
    CFG4 #( .INIT(16'hFEFF) )  \s_state_ns_i_i_a2_i_15_i_i_2[5]  (.A(
        s_state[8]), .B(N_430), .C(un1_inf_abs0_2), .D(N_212), .Y(
        s_state_ns_i_i_a2_i_15_i_i_2[5]));
    SLE \s_sensor_calib_count[7]  (.D(s_sensor_calib_count_s[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[7]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_17  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[17]), .B(inf_abs0[17]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_16), .S(
        un1_inf_abs0_2_cry_17_S), .Y(un1_inf_abs0_2_cry_17_Y), .FCO(
        un1_inf_abs0_2));
    CFG3 #( .INIT(8'h01) )  \s_state_ns_0_a2_RNO[0]  (.A(N_356), .B(
        N_208), .C(N_187), .Y(s_state_ns_0_a2_2[0]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIUUL61[1]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[1]), .D(GND), 
        .FCI(s_adctrig_count_cry[0]), .S(s_adctrig_count_s[1]), .Y(
        s_adctrig_count_RNIUUL61_Y[1]), .FCO(s_adctrig_count_cry[1]));
    SLE s_start_motor_dly (.D(apb3_if_0_start_motor_o), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_start_motor_dly_Z));
    SLE \s_adctrig_count[0]  (.D(s_adctrig_count_s[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[0]));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_7  (.A(inf_abs0[7]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[7]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_6), .S(un1_speed_cl_i_cry_7_S), .Y(
        un1_speed_cl_i_cry_7_Y), .FCO(un1_speed_cl_i_cry_7));
    SLE \s_sensor_calib_count[9]  (.D(s_sensor_calib_count_s[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[9]));
    CFG4 #( .INIT(16'h0080) )  \ADC_START_PROC.adc_start_o5  (.A(
        s_adctrig_count[11]), .B(adc_start_o5_8), .C(adc_start_o5_7), 
        .D(adc_start_o5_1), .Y(adc_start_o5));
    CFG3 #( .INIT(8'hA2) )  \s_state_ns_0_0_RNO[8]  (.A(N_356), .B(
        un1_max_ar_i_NE), .C(N_2197_i), .Y(N_288));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_13  (.A(inf_abs0[16])
        , .B(inf_abs1[13]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_12)
        , .S(un1_inf_abs1_cry_13_S), .Y(un1_inf_abs1_cry_13_Y), .FCO(
        un1_inf_abs1_cry_13));
    CFG3 #( .INIT(8'h01) )  \s_state_ns_i_o2_11_0_o2_i_a2[7]  (.A(
        apb3_if_0_seq_cntl_config_o[3]), .B(N_2197_i), .C(
        PWM_SCALING_1_done_o), .Y(N_440_i));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_4 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_3_Z), .S(inf_abs1[4]), .Y(inf_abs1_cry_4_Y), .FCO(
        inf_abs1_cry_4_Z));
    SLE adc_start_o (.D(adc_start_o_4), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_adc_start_o));
    CFG4 #( .INIT(16'hDFCE) )  \s_state_ns_0_0[8]  (.A(s_state[8]), .B(
        N_288), .C(N_572_li), .D(N_2197_i), .Y(s_state_ns[8]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNI88QK1[4]  (.A(
        VCC), .B(s_sensor_calib_count[4]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[3]), .S(s_sensor_calib_count_s[4]), 
        .Y(s_sensor_calib_count_RNI88QK1_Y[4]), .FCO(
        s_sensor_calib_count_cry[4]));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_6 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[6]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_5_Z), .S(inf_abs0[6]), .Y(
        inf_abs0_cry_6_Y), .FCO(inf_abs0_cry_6_Z));
    CFG4 #( .INIT(16'hFFFE) )  \state_o_RNO[0]  (.A(s_state[1]), .B(
        s_state[3]), .C(s_state[6]), .D(s_state[5]), .Y(N_893_i_0));
    CFG2 #( .INIT(4'hD) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_stop_motor_i_1_0_o2_0_o2  (.A(
        un1_max_ar_i_NE), .B(N_2481), .Y(un1_stop_motor_i_1));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_11  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[11]), .B(inf_abs0[11]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_10), .S(
        un1_inf_abs0_2_cry_11_S), .Y(un1_inf_abs0_2_cry_11_Y), .FCO(
        un1_inf_abs0_2_cry_11));
    CFG4 #( .INIT(16'hFAF2) )  \s_state_RNO_1[7]  (.A(N_356), .B(
        un1_max_ar_i_NE), .C(N_212), .D(un1_inf_abs0_1), .Y(N_226));
    ARI1 #( .INIT(20'h45500) )  inf_abs1_cry_15_RNIIDM31 (.A(VCC), .B(
        inf_abs1[15]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_14), .S(
        inf_abs1_cry_15_RNIIDM31_S), .Y(inf_abs1_cry_15_RNIIDM31_Y), 
        .FCO(un1_inf_abs1_cry_15));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNI93MN3[12]  (
        .A(VCC), .B(s_sensor_calib_count[12]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[11]), .S(s_sensor_calib_count_s[12]), 
        .Y(s_sensor_calib_count_RNI93MN3_Y[12]), .FCO(
        s_sensor_calib_count_cry[12]));
    CFG3 #( .INIT(8'h41) )  \s_restart_count_RNO[1]  (.A(s_state[0]), 
        .B(N_199), .C(s_restart_count[1]), .Y(N_2369_i_0));
    CFG4 #( .INIT(16'h0501) )  \s_state_ns_i_a2_28_0[7]  (.A(N_2481), 
        .B(s_state_ns_i_o2_10_i_a2_0[7]), .C(N_243), .D(un1_inf_abs0_1)
        , .Y(s_state_ns_i_a2_28_0[7]));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_16 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[16]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_15_Z), .S(inf_abs0[16]), .Y(
        inf_abs0_cry_16_Y), .FCO(inf_abs0[17]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_5 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_4_Z), .S(inf_abs1[5]), .Y(inf_abs1_cry_5_Y), .FCO(
        inf_abs1_cry_5_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_9  (.A(inf_abs0[12]), 
        .B(inf_abs1[9]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_8), 
        .S(un1_inf_abs1_cry_9_S), .Y(un1_inf_abs1_cry_9_Y), .FCO(
        un1_inf_abs1_cry_9));
    CFG4 #( .INIT(16'h0001) )  \s_state_RNO[2]  (.A(N_231), .B(N_253), 
        .C(N_187), .D(N_294_i_1), .Y(N_294_i_0));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIP17O[0]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[0]), .D(GND), 
        .FCI(s_adctrig_count_cry_cy), .S(s_adctrig_count_s[0]), .Y(
        s_adctrig_count_RNIP17O_Y[0]), .FCO(s_adctrig_count_cry[0]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNI601F3[6]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[6]), .D(GND), 
        .FCI(s_adctrig_count_cry[5]), .S(s_adctrig_count_s[6]), .Y(
        s_adctrig_count_RNI601F3_Y[6]), .FCO(s_adctrig_count_cry[6]));
    SLE s_fault_clear_sync (.D(apb3_if_0_fault_clr_o), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_fault_clear_sync_Z));
    SLE \s_adctrig_count[5]  (.D(s_adctrig_count_s[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[5]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_8  (.A(inf_abs0[11]), 
        .B(inf_abs1[8]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_7), 
        .S(un1_inf_abs1_cry_8_S), .Y(un1_inf_abs1_cry_8_Y), .FCO(
        un1_inf_abs1_cry_8));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIH9PE3[11]  (
        .A(VCC), .B(s_sensor_calib_count[11]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[10]), .S(s_sensor_calib_count_s[11]), 
        .Y(s_sensor_calib_count_RNIH9PE3_Y[11]), .FCO(
        s_sensor_calib_count_cry[11]));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_10 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[10]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_9_Z), .S(inf_abs0[10]), .Y(
        inf_abs0_cry_10_Y), .FCO(inf_abs0_cry_10_Z));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_1 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[1]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_0_Z), .S(inf_abs0[1]), .Y(
        inf_abs0_cry_1_Y), .FCO(inf_abs0_cry_1_Z));
    SLE \s_restart_count[0]  (.D(N_254_i_0), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_restart_count[0]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_0  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[0]), .B(inf_abs0[0]), .C(GND), 
        .D(GND), .FCI(GND), .S(un1_inf_abs0_2_cry_0_S), .Y(
        un1_inf_abs0_2_cry_0_Y), .FCO(un1_inf_abs0_2_cry_0));
    ARI1 #( .INIT(20'h5AA55) )  inf_abs1_cry_14_RNIE4MR (.A(
        inf_abs0[17]), .B(inf_abs1[14]), .C(GND), .D(GND), .FCI(
        un1_inf_abs1_cry_13), .S(inf_abs1_cry_14_RNIE4MR_S), .Y(
        inf_abs1_cry_14_RNIE4MR_Y), .FCO(un1_inf_abs1_cry_14));
    CFG4 #( .INIT(16'h8000) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1  (.A(un1_inf_abs0_1_8), 
        .B(un1_inf_abs0_1_9), .C(un1_inf_abs0_1_14), .D(
        un1_inf_abs0_1_12), .Y(un1_inf_abs0_1));
    CFG4 #( .INIT(16'hFEFA) )  \s_state_ns_i_i_i_2[3]  (.A(
        s_state_ns_i_i_i_0[3]), .B(apb3_if_0_seq_cntl_config_o[2]), .C(
        N_218), .D(N_215), .Y(s_state_ns_i_i_i_2[3]));
    SLE \s_state[5]  (.D(N_170_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(s_state[5]));
    CFG3 #( .INIT(8'h01) )  \s_state_ns_i_a2_33_1[6]  (.A(N_356), .B(
        N_2481), .C(N_477), .Y(s_state_ns_i_a2_33_1[6]));
    CFG4 #( .INIT(16'h8000) )  \ADC_START_PROC.adc_start_o5_8  (.A(
        s_adctrig_count[7]), .B(s_adctrig_count[6]), .C(
        s_adctrig_count[5]), .D(s_adctrig_count[4]), .Y(adc_start_o5_8)
        );
    CFG4 #( .INIT(16'hFFFE) )  \s_state_RNIGDKK[4]  (.A(s_state[5]), 
        .B(s_state[4]), .C(N_213), .D(s_state[2]), .Y(N_894_i_0));
    SLE \s_state[7]  (.D(N_224_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(N_356));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_15 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[15]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_14_Z), .S(inf_abs0[15]), .Y(
        inf_abs0_cry_15_Y), .FCO(inf_abs0_cry_15_Z));
    CFG4 #( .INIT(16'h3100) )  \s_state_RNO[7]  (.A(
        s_state_ns_i_a2_28_0[7]), .B(s_state[8]), .C(N_224_i_1), .D(
        N_667), .Y(N_224_i_0));
    CFG3 #( .INIT(8'hB8) )  s_sensor_calib_rr_RNO (.A(
        s_sensor_calib_rr_Z), .B(N_2481), .C(N_203), .Y(N_109_i_0));
    CFG2 #( .INIT(4'hB) )  \s_state_ns_a2_64_0_i_0_o2[8]  (.A(N_2197_i)
        , .B(apb3_if_0_stop_motor_o), .Y(N_208));
    CFG2 #( .INIT(4'h7) )  
        \FSM_SEQ_CONTROLLER_PROC.s_restart_count_4_i_0_o3_0_0[2]  (.A(
        s_restart_count[1]), .B(s_restart_count[2]), .Y(
        s_restart_count_4_i_0_o3_0_0[2]));
    CFG3 #( .INIT(8'h31) )  \s_state_ns_i_i_2_0_4_i_a2[4]  (.A(
        apb3_if_0_seq_cntl_config_o[2]), .B(s_state[4]), .C(s_state[3])
        , .Y(N_305));
    CFG2 #( .INIT(4'hB) )  \s_state_ns_i_i_i_0[3]  (.A(N_231), .B(
        N_305), .Y(s_state_ns_i_i_i_0[3]));
    CFG4 #( .INIT(16'hFFFE) )  \s_sensor_calib_count_RNI63401[3]  (.A(
        s_sensor_calib_count[6]), .B(s_sensor_calib_count[5]), .C(
        s_sensor_calib_count[4]), .D(s_sensor_calib_count[3]), .Y(
        N_482_i_0_i_0_i_o2_0_o3_7));
    CFG4 #( .INIT(16'h4150) )  \s_restart_count_RNO[2]  (.A(s_state[0])
        , .B(N_199), .C(s_restart_count[2]), .D(s_restart_count[1]), 
        .Y(N_258_i_0));
    CFG4 #( .INIT(16'hFF02) )  \s_state_ns_i_i_2_0_4_i_o2_1[4]  (.A(
        s_state_ns_i_i_2_0_4_i_a2_4_1[4]), .B(
        s_state_ns_i_i_2_0_4_i_m2_a0[4]), .C(N_215), .D(N_218), .Y(
        N_511));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNO[13]  (.A(VCC)
        , .B(s_sensor_calib_count[13]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[12]), .S(s_sensor_calib_count_s[13]), 
        .Y(s_sensor_calib_count_RNO_Y_0[13]), .FCO(
        s_sensor_calib_count_RNO_FCO_0[13]));
    CFG3 #( .INIT(8'hF7) )  \s_state_ns_i_a2_52_0_a2_i_o2[6]  (.A(
        un1_max_ar_i_NE), .B(apb3_if_0_stop_motor_o), .C(N_2197_i), .Y(
        N_205));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIN8O41[2]  (.A(
        VCC), .B(s_sensor_calib_count[2]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[1]), .S(s_sensor_calib_count_s[2]), 
        .Y(s_sensor_calib_count_RNIN8O41_Y[2]), .FCO(
        s_sensor_calib_count_cry[2]));
    CFG4 #( .INIT(16'hEF00) )  \s_state_ns_i_3_a1_1[6]  (.A(
        s_state_ns_i_o3_26_0_0_a2_0_0_2[6]), .B(N_2197_i), .C(N_243), 
        .D(s_state_ns_i_3_a1_1_1[6]), .Y(s_state_ns_i_3_a1_1[6]));
    CFG2 #( .INIT(4'hE) )  \un11_i_a2_0_a2_0_o2[1]  (.A(N_356), .B(
        s_state[6]), .Y(N_213));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_2  (.A(inf_abs0[2]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[2]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_1), .S(un1_speed_cl_i_cry_2_S), .Y(
        un1_speed_cl_i_cry_2_Y), .FCO(un1_speed_cl_i_cry_2));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_12  (.A(inf_abs0[12]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[12]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_11), .S(un1_speed_cl_i_cry_12_S), .Y(
        un1_speed_cl_i_cry_12_Y), .FCO(un1_speed_cl_i_cry_12));
    SLE \s_state[3]  (.D(N_84_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(s_state[3]));
    CFG4 #( .INIT(16'h0001) )  \s_state_fast_RNO[2]  (.A(N_231), .B(
        N_253), .C(N_187), .D(N_294_i_1), .Y(N_294_i_0_fast));
    CFG3 #( .INIT(8'h04) )  \s_state_ns_0_a2_3_1[0]  (.A(N_213), .B(
        s_state[1]), .C(N_208), .Y(s_state_ns_0_a2_3_1[0]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_3 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_2_Z), .S(inf_abs1[3]), .Y(inf_abs1_cry_3_Y), .FCO(
        inf_abs1_cry_3_Z));
    ARI1 #( .INIT(20'h47700) )  \s_state_RNIL5O9[1]  (.A(VCC), .B(
        ADC_SCALING_1_calib_done_o), .C(s_state[1]), .D(GND), .FCI(VCC)
        , .S(s_state_RNIL5O9_S[1]), .Y(s_state_RNIL5O9_Y[1]), .FCO(
        s_adctrig_count_cry_cy));
    CFG4 #( .INIT(16'h8CCC) )  \s_state_ns_i_i_2_0_4_i_a2_4_1[4]  (.A(
        N_203), .B(s_state_ns_i_i_2_0_4_i_a2_4_0[4]), .C(s_state[2]), 
        .D(s_state88), .Y(s_state_ns_i_i_2_0_4_i_a2_4_1[4]));
    SLE \state_o[0]  (.D(N_893_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_state_o[0]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_4  (.A(inf_abs0[7]), 
        .B(inf_abs1[4]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_3), 
        .S(un1_inf_abs1_cry_4_S), .Y(un1_inf_abs1_cry_4_Y), .FCO(
        un1_inf_abs1_cry_4));
    CFG4 #( .INIT(16'h31FD) )  \s_state_RNIQL6G4[2]  (.A(
        apb3_if_0_seq_cntl_config_o[1]), .B(s_state[2]), .C(
        s_state_RNIL5O9_Y[1]), .D(N_203), .Y(N_294_i_1));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_13 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[13]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_12_Z), .S(inf_abs0[13]), .Y(
        inf_abs0_cry_13_Y), .FCO(inf_abs0_cry_13_Z));
    SLE \s_sensor_calib_count[6]  (.D(s_sensor_calib_count_s[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[6]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_4  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[4]), .B(inf_abs0[4]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_3), .S(un1_inf_abs0_2_cry_4_S)
        , .Y(un1_inf_abs0_2_cry_4_Y), .FCO(un1_inf_abs0_2_cry_4));
    CFG2 #( .INIT(4'hE) )  N_479_i_i_o2 (.A(N_2197_i), .B(
        apb3_if_0_stop_motor_o), .Y(N_2481));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_12  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[12]), .B(inf_abs0[12]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_11), .S(
        un1_inf_abs0_2_cry_12_S), .Y(un1_inf_abs0_2_cry_12_Y), .FCO(
        un1_inf_abs0_2_cry_12));
    ARI1 #( .INIT(20'h44400) )  \s_sensor_calib_count_RNI5HLC[13]  (.A(
        VCC), .B(s_sensor_calib_count[13]), .C(s_state[2]), .D(GND), 
        .FCI(VCC), .S(s_sensor_calib_count_RNI5HLC_S[13]), .Y(
        s_sensor_calib_count_RNI5HLC_Y[13]), .FCO(
        s_sensor_calib_count_cry_cy));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_2  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[2]), .B(inf_abs0[2]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_1), .S(un1_inf_abs0_2_cry_2_S)
        , .Y(un1_inf_abs0_2_cry_2_Y), .FCO(un1_inf_abs0_2_cry_2));
    CFG4 #( .INIT(16'h4404) )  \s_state_ns_0_a2_0_1[0]  (.A(N_216), .B(
        N_498), .C(un1_inf_abs0_1), .D(s_restart_count_4_i_0_o2_0[1]), 
        .Y(s_state_ns_0_a2_0_1[0]));
    CFG4 #( .INIT(16'h1F00) )  \s_state_RNIDI331[6]  (.A(
        apb3_if_0_seq_cntl_config_o[3]), .B(PWM_SCALING_1_done_o), .C(
        N_2197_i), .D(s_state[6]), .Y(N_435));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_10  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[10]), .B(inf_abs0[10]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_9), .S(
        un1_inf_abs0_2_cry_10_S), .Y(un1_inf_abs0_2_cry_10_Y), .FCO(
        un1_inf_abs0_2_cry_10));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIH3GT3[7]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[7]), .D(GND), 
        .FCI(s_adctrig_count_cry[6]), .S(s_adctrig_count_s[7]), .Y(
        s_adctrig_count_RNIH3GT3_Y[7]), .FCO(s_adctrig_count_cry[7]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_13  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[13]), .B(inf_abs0[13]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_12), .S(
        un1_inf_abs0_2_cry_13_S), .Y(un1_inf_abs0_2_cry_13_Y), .FCO(
        un1_inf_abs0_2_cry_13));
    SLE \s_adctrig_count[11]  (.D(s_adctrig_count_s[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[11]));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_0  (.A(inf_abs0[0]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[0]), .C(GND), .D(GND), .FCI(GND), 
        .S(un1_speed_cl_i_cry_0_S), .Y(un1_speed_cl_i_cry_0_Y), .FCO(
        un1_speed_cl_i_cry_0));
    CFG4 #( .INIT(16'h00A8) )  \s_state_ns_i_3_a0_RNO[6]  (.A(
        apb3_if_0_stop_motor_o), .B(s_state[6]), .C(N_356), .D(N_185), 
        .Y(d_m6_1));
    CFG3 #( .INIT(8'h45) )  \s_state_ns_i_0_0_0_a3[1]  (.A(s_state[1]), 
        .B(s_start_motor_dly_Z), .C(apb3_if_0_start_motor_o), .Y(N_498)
        );
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIADMK[0]  (.A(
        VCC), .B(s_sensor_calib_count[0]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry_cy), .S(s_sensor_calib_count_s[0]), 
        .Y(s_sensor_calib_count_RNIADMK_Y[0]), .FCO(
        s_sensor_calib_count_cry[0]));
    CFG2 #( .INIT(4'h6) )  \FSM_SEQ_CONTROLLER_PROC.un1_max_ar_i_0  (
        .A(s_restart_count[0]), .B(apb3_if_0_auto_restart_no_o[0]), .Y(
        un1_max_ar_i_0));
    CFG4 #( .INIT(16'h0100) )  reset_rl_o_i_a3_0_a2 (.A(
        s_sensor_calib_rr_Z), .B(s_state[0]), .C(N_356), .D(N_499), .Y(
        N_326));
    CFG4 #( .INIT(16'hFFFE) )  \s_sensor_calib_count_RNITCTJ3[0]  (.A(
        N_482_i_0_i_0_i_o2_0_o3_8), .B(N_482_i_0_i_0_i_o2_0_o3_7), .C(
        N_482_i_0_i_0_i_o2_0_o3_6), .D(N_482_i_0_i_0_i_o2_0_o3_9), .Y(
        N_203));
    ARI1 #( .INIT(20'h45500) )  inf_abs1_cry_16_RNISVMJ1 (.A(VCC), .B(
        inf_abs1[17]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_16), .S(
        inf_abs1_cry_16_RNISVMJ1_S), .Y(inf_abs1_cry_16_RNISVMJ1_Y), 
        .FCO(un1_inf_abs1));
    CFG2 #( .INIT(4'h4) )  \s_state_ns_i_i_2_0_4_i_a2_1[4]  (.A(
        un1_max_ar_i_NE), .B(N_356), .Y(N_430));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_3 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[3]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_2_Z), .S(inf_abs0[3]), .Y(
        inf_abs0_cry_3_Y), .FCO(inf_abs0_cry_3_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_6  (.A(inf_abs0[9]), 
        .B(inf_abs1[6]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_5), 
        .S(un1_inf_abs1_cry_6_S), .Y(un1_inf_abs1_cry_6_Y), .FCO(
        un1_inf_abs1_cry_6));
    SLE \s_adctrig_count[10]  (.D(s_adctrig_count_s[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[10]));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_2 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[2]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_1_Z), .S(inf_abs0[2]), .Y(
        inf_abs0_cry_2_Y), .FCO(inf_abs0_cry_2_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_0  (.A(inf_abs0[3]), 
        .B(inf_abs1[0]), .C(GND), .D(GND), .FCI(GND), .S(
        un1_inf_abs1_cry_0_S), .Y(un1_inf_abs1_cry_0_Y), .FCO(
        un1_inf_abs1_cry_0));
    CFG4 #( .INIT(16'h5101) )  \s_state_RNO[4]  (.A(
        s_state_ns_i_i_2_0_4_i_3_1[4]), .B(N_511), .C(s_state[4]), .D(
        un1_inf_abs0_2), .Y(N_79_i_0));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIJS2I2[4]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[4]), .D(GND), 
        .FCI(s_adctrig_count_cry[3]), .S(s_adctrig_count_s[4]), .Y(
        s_adctrig_count_RNIJS2I2_Y[4]), .FCO(s_adctrig_count_cry[4]));
    CFG4 #( .INIT(16'h7BDE) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_max_ar_i_NE_0  (.A(
        apb3_if_0_auto_restart_no_o[3]), .B(
        apb3_if_0_auto_restart_no_o[2]), .C(s_restart_count[3]), .D(
        s_restart_count[2]), .Y(un1_max_ar_i_NE_0));
    SLE \s_sensor_calib_count[5]  (.D(s_sensor_calib_count_s[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[5]));
    SLE \s_adctrig_count[12]  (.D(s_adctrig_count_s[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[12]));
    CFG3 #( .INIT(8'hFE) )  \s_state_ns_i_i_2_0_4_i_3_1[4]  (.A(N_305), 
        .B(N_231), .C(N_218), .Y(s_state_ns_i_i_2_0_4_i_3_1[4]));
    CFG3 #( .INIT(8'hFE) )  \state_o_RNO[2]  (.A(s_state[5]), .B(N_213)
        , .C(s_state[4]), .Y(N_1542_i_0));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_8  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[8]), .B(inf_abs0[8]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_7), .S(un1_inf_abs0_2_cry_8_S)
        , .Y(un1_inf_abs0_2_cry_8_Y), .FCO(un1_inf_abs0_2_cry_8));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIVEJF5[10]  (.A(VCC)
        , .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[10]), .D(GND), 
        .FCI(s_adctrig_count_cry[9]), .S(s_adctrig_count_s[10]), .Y(
        s_adctrig_count_RNIVEJF5_Y[10]), .FCO(s_adctrig_count_cry[10]));
    GND GND_Z (.Y(GND));
    CFG4 #( .INIT(16'hFFFE) )  \s_state_RNO[0]  (.A(N_508), .B(
        s_state_ns_0_0[0]), .C(N_403), .D(N_401), .Y(s_state_ns[0]));
    CFG4 #( .INIT(16'h4000) )  \s_state_ns_0_a2_0[0]  (.A(s_state[8]), 
        .B(s_state_ns_0_a2_0_1[0]), .C(N_219), .D(N_264), .Y(N_403));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_0 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_s_0_173_FCO), .S(inf_abs1[0]), .Y(inf_abs1_cry_0_Y), 
        .FCO(inf_abs1_cry_0_Z));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIQGS53[10]  (
        .A(VCC), .B(s_sensor_calib_count[10]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[9]), .S(s_sensor_calib_count_s[10]), 
        .Y(s_sensor_calib_count_RNIQGS53_Y[10]), .FCO(
        s_sensor_calib_count_cry[10]));
    SLE \s_restart_count[3]  (.D(N_260_i_0), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_restart_count[3]));
    CFG4 #( .INIT(16'hFEFF) )  reset_rl_o_i_a3_0_a2_i (.A(
        s_sensor_calib_rr_Z), .B(s_state[0]), .C(N_356), .D(N_499), .Y(
        N_326_i_0));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_9 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[9]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_8_Z), .S(inf_abs0[9]), .Y(
        inf_abs0_cry_9_Y), .FCO(inf_abs0_cry_9_Z));
    VCC VCC_Z (.Y(VCC));
    SLE \s_adctrig_count[1]  (.D(s_adctrig_count_s[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[1]));
    SLE \state_o[3]  (.D(s_state[8]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_state_o[3]));
    CFG4 #( .INIT(16'h0031) )  \s_state_RNO_0[7]  (.A(s_state[6]), .B(
        N_2481), .C(N_243), .D(N_226), .Y(N_224_i_1));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_13  (.A(inf_abs0[13]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[13]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_12), .S(un1_speed_cl_i_cry_13_S), .Y(
        un1_speed_cl_i_cry_13_Y), .FCO(un1_speed_cl_i_cry_13));
    CFG4 #( .INIT(16'h8000) )  \ADC_START_PROC.adc_start_o5_7  (.A(
        s_adctrig_count[3]), .B(s_adctrig_count[2]), .C(
        s_adctrig_count[1]), .D(s_adctrig_count[0]), .Y(adc_start_o5_7)
        );
    SLE \s_state_fast[1]  (.D(N_212_i_0_fast), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_state_fast[1]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_12  (.A(inf_abs0[15])
        , .B(inf_abs1[12]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_11)
        , .S(un1_inf_abs1_cry_12_S), .Y(un1_inf_abs1_cry_12_Y), .FCO(
        un1_inf_abs1_cry_12));
    CFG4 #( .INIT(16'h00EC) )  \s_state_RNIIFR84[1]  (.A(s_state[2]), 
        .B(s_state[1]), .C(N_203), .D(N_2481), .Y(N_162_i_0));
    CFG4 #( .INIT(16'h5455) )  \s_state_ns_i_i_2_0_4_i_a2_4_0[4]  (.A(
        s_state_ns_i_i_2_0_4_i_m2_a3[4]), .B(N_203), .C(s_state[6]), 
        .D(s_state[2]), .Y(s_state_ns_i_i_2_0_4_i_a2_4_0[4]));
    CFG2 #( .INIT(4'h1) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_14_3  (.A(inf_abs0[11])
        , .B(inf_abs0[10]), .Y(un1_inf_abs0_1_14_3));
    CFG4 #( .INIT(16'h0F01) )  \s_state_RNO_0[6]  (.A(
        s_state_ns_i_3_a1_1[6]), .B(s_state_ns_i_3_a0_2[6]), .C(
        s_state_ns_i_2_1[6]), .D(s_state_ns_i_a2_33_1[6]), .Y(
        N_222_i_1));
    SLE \s_restart_count[2]  (.D(N_258_i_0), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_restart_count[2]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_7  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[7]), .B(inf_abs0[7]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_6), .S(un1_inf_abs0_2_cry_7_S)
        , .Y(un1_inf_abs0_2_cry_7_Y), .FCO(un1_inf_abs0_2_cry_7));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_3  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[3]), .B(inf_abs0[3]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_2), .S(un1_inf_abs0_2_cry_3_S)
        , .Y(un1_inf_abs0_2_cry_3_Y), .FCO(un1_inf_abs0_2_cry_3));
    CFG4 #( .INIT(16'h7FFF) )  \ADC_START_PROC.adc_start_o5_1  (.A(
        s_adctrig_count[12]), .B(s_adctrig_count[10]), .C(
        s_adctrig_count[9]), .D(s_adctrig_count[8]), .Y(adc_start_o5_1)
        );
    CFG2 #( .INIT(4'h4) )  \FSM_SEQ_CONTROLLER_PROC.s_state87  (.A(
        N_2197_i), .B(apb3_if_0_seq_cntl_config_o[3]), .Y(s_state87));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_10  (.A(inf_abs0[10]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[10]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_9), .S(un1_speed_cl_i_cry_10_S), .Y(
        un1_speed_cl_i_cry_10_Y), .FCO(un1_speed_cl_i_cry_10));
    CFG3 #( .INIT(8'hFB) )  \s_state_ns_i_i_2_0_4_i_o2_2_0[4]  (.A(
        N_430), .B(un1_inf_abs0_2), .C(N_435), .Y(
        s_state_ns_i_i_2_0_4_i_o2_2_0[4]));
    CFG4 #( .INIT(16'h00C8) )  \s_state_ns_i_3_a1_1_1[6]  (.A(
        s_state[6]), .B(apb3_if_0_stop_motor_o), .C(
        s_state_ns_i_o3_26_0_0_a2_0_0_2[6]), .D(N_185), .Y(
        s_state_ns_i_3_a1_1_1[6]));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_8 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[8]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_7_Z), .S(inf_abs0[8]), .Y(
        inf_abs0_cry_8_Y), .FCO(inf_abs0_cry_8_Z));
    CFG3 #( .INIT(8'h10) )  \FSM_SEQ_CONTROLLER_PROC.s_state88  (.A(
        apb3_if_0_seq_cntl_config_o[3]), .B(N_2197_i), .C(
        PWM_SCALING_1_done_o), .Y(s_state88));
    SLE \state_o[1]  (.D(N_892_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_state_o[1]));
    CFG4 #( .INIT(16'h0001) )  \s_state_RNO[5]  (.A(
        s_state_ns_i_i_a2_i_15_i_i_5[5]), .B(N_508), .C(N_253), .D(
        s_state_ns_i_i_a2_i_15_i_i_3[5]), .Y(N_170_i_0));
    SLE s_sensor_calib_rr (.D(N_109_i_0), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_state[2]), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(
        VCC), .SD(GND), .LAT(GND), .Q(s_sensor_calib_rr_Z));
    SLE \s_sensor_calib_count[1]  (.D(s_sensor_calib_count_s[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[1]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNI4T4L1[2]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[2]), .D(GND), 
        .FCI(s_adctrig_count_cry[1]), .S(s_adctrig_count_s[2]), .Y(
        s_adctrig_count_RNI4T4L1_Y[2]), .FCO(s_adctrig_count_cry[2]));
    SLE \state_o[2]  (.D(N_1542_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_state_o[2]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_7  (.A(inf_abs0[10]), 
        .B(inf_abs1[7]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_6), 
        .S(un1_inf_abs1_cry_7_S), .Y(un1_inf_abs1_cry_7_Y), .FCO(
        un1_inf_abs1_cry_7));
    CFG4 #( .INIT(16'h31F5) )  \s_state_RNO_1[6]  (.A(N_356), .B(
        apb3_if_0_stop_motor_o), .C(N_205), .D(N_187), .Y(
        s_state_ns_i_2_1[6]));
    CFG2 #( .INIT(4'hE) )  \s_state_ns_i_i_a2_i_0_o2[2]  (.A(N_185), 
        .B(s_state[5]), .Y(N_187));
    CFG2 #( .INIT(4'hD) )  \s_state_ns_i_0_0_0_0[1]  (.A(
        s_state_RNIL5O9_Y[1]), .B(N_498), .Y(s_state_ns_i_0_0_0_0[1]));
    ARI1 #( .INIT(20'h4AA00) )  inf_abs0_s_0_172 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[17]), .C(GND), .D(GND), .FCI(VCC), .S(
        inf_abs0_s_0_172_S), .Y(inf_abs0_s_0_172_Y), .FCO(
        inf_abs0_s_0_172_FCO));
    CFG3 #( .INIT(8'hF4) )  \s_state_ns_i_i_a2_i_15_i_i_3[5]  (.A(
        N_185), .B(N_268), .C(s_state_ns_i_i_a2_i_15_i_i_2[5]), .Y(
        s_state_ns_i_i_a2_i_15_i_i_3[5]));
    SLE \s_sensor_calib_count[4]  (.D(s_sensor_calib_count_s[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[4]));
    CFG4 #( .INIT(16'h0001) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_14_4  (.A(inf_abs0[4]), 
        .B(inf_abs0[5]), .C(inf_abs0[6]), .D(inf_abs0[7]), .Y(
        un1_inf_abs0_1_14_4));
    CFG3 #( .INIT(8'h80) )  \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_1  
        (.A(un1_inf_abs0_1_8), .B(un1_inf_abs0_1_12), .C(
        un1_inf_abs0_1_9), .Y(un1_inf_abs0_1_1));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_11 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_10_Z), .S(inf_abs1[11]), .Y(inf_abs1_cry_11_Y), 
        .FCO(inf_abs1_cry_11_Z));
    SLE \s_adctrig_count[9]  (.D(s_adctrig_count_s[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[9]));
    CFG4 #( .INIT(16'h0001) )  \s_state_fast_RNO[1]  (.A(N_231), .B(
        N_253), .C(s_state_ns_i_0_0_0_0[1]), .D(N_216), .Y(
        N_212_i_0_fast));
    SLE \s_sensor_calib_count[11]  (.D(s_sensor_calib_count_s[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[11]));
    SLE \s_state[0]  (.D(s_state_ns[0]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(GND), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_state[0]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_14 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_13_Z), .S(inf_abs1[14]), .Y(inf_abs1_cry_14_Y), 
        .FCO(inf_abs1_cry_14_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_1  (.A(inf_abs0[1]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[1]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_0), .S(un1_speed_cl_i_cry_1_S), .Y(
        un1_speed_cl_i_cry_1_Y), .FCO(un1_speed_cl_i_cry_1));
    CFG3 #( .INIT(8'h31) )  \s_state_ns_i_o3_26_0_0_a2_0_0_2_1[6]  (.A(
        apb3_if_0_stop_motor_o), .B(N_2197_i), .C(N_356), .Y(
        s_state_ns_i_o3_26_0_0_a2_0_0_2_1[6]));
    ARI1 #( .INIT(20'h45500) )  inf_abs1_cry_16_RNINMMB1 (.A(VCC), .B(
        inf_abs1[16]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_15), .S(
        inf_abs1_cry_16_RNINMMB1_S), .Y(inf_abs1_cry_16_RNINMMB1_Y), 
        .FCO(un1_inf_abs1_cry_16));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_1  (.A(inf_abs0[4]), 
        .B(inf_abs1[1]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_0), 
        .S(un1_inf_abs1_cry_1_S), .Y(un1_inf_abs1_cry_1_Y), .FCO(
        un1_inf_abs1_cry_1));
    SLE \s_adctrig_count[8]  (.D(s_adctrig_count_s[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[8]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_9 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_8_Z), .S(inf_abs1[9]), .Y(inf_abs1_cry_9_Y), .FCO(
        inf_abs1_cry_9_Z));
    SLE \s_state_fast[2]  (.D(N_294_i_0_fast), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_state_fast[2]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_5  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[5]), .B(inf_abs0[5]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_4), .S(un1_inf_abs0_2_cry_5_S)
        , .Y(un1_inf_abs0_2_cry_5_Y), .FCO(un1_inf_abs0_2_cry_5));
    CFG4 #( .INIT(16'h8000) )  \s_state_ns_i_i_2_0_4_i_m2_a0[4]  (.A(
        un1_inf_abs0_1_12), .B(un1_inf_abs0_1_9), .C(un1_inf_abs0_1_14)
        , .D(s_state_ns_i_i_2_0_4_i_m2_a0_2[4]), .Y(
        s_state_ns_i_i_2_0_4_i_m2_a0[4]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIGANS[1]  (.A(
        VCC), .B(s_sensor_calib_count[1]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[0]), .S(s_sensor_calib_count_s[1]), 
        .Y(s_sensor_calib_count_RNIGANS_Y[1]), .FCO(
        s_sensor_calib_count_cry[1]));
    CFG4 #( .INIT(16'h000E) )  \s_state_RNO[6]  (.A(N_1082), .B(
        N_222_i_1), .C(N_2197_i), .D(s_state[8]), .Y(N_222_i_0));
    SLE s_fault_clear_sync1 (.D(s_fault_clear_sync_Z), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(N_572_li));
    ARI1 #( .INIT(20'h4AA00) )  inf_abs1_s_0_173 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .C(GND), .D(GND), .FCI(
        VCC), .S(inf_abs1_s_0_173_S), .Y(inf_abs1_s_0_173_Y), .FCO(
        inf_abs1_s_0_173_FCO));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNII9RS1[5]  (.A(
        VCC), .B(s_sensor_calib_count[5]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[4]), .S(s_sensor_calib_count_s[5]), 
        .Y(s_sensor_calib_count_RNII9RS1_Y[5]), .FCO(
        s_sensor_calib_count_cry[5]));
    CFG4 #( .INIT(16'hFFFE) )  \s_sensor_calib_count_RNI41401[0]  (.A(
        s_sensor_calib_count[8]), .B(s_sensor_calib_count[7]), .C(
        s_sensor_calib_count[1]), .D(s_sensor_calib_count[0]), .Y(
        N_482_i_0_i_0_i_o2_0_o3_9));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIBSJ32[3]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[3]), .D(GND), 
        .FCI(s_adctrig_count_cry[2]), .S(s_adctrig_count_s[3]), .Y(
        s_adctrig_count_RNIBSJ32_Y[3]), .FCO(s_adctrig_count_cry[3]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_12 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_11_Z), .S(inf_abs1[12]), .Y(inf_abs1_cry_12_Y), 
        .FCO(inf_abs1_cry_12_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_11  (.A(inf_abs0[11]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[11]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_10), .S(un1_speed_cl_i_cry_11_S), .Y(
        un1_speed_cl_i_cry_11_Y), .FCO(un1_speed_cl_i_cry_11));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_6  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[6]), .B(inf_abs0[6]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_5), .S(un1_inf_abs0_2_cry_6_S)
        , .Y(un1_inf_abs0_2_cry_6_Y), .FCO(un1_inf_abs0_2_cry_6));
    CFG3 #( .INIT(8'hDF) )  
        \FSM_SEQ_CONTROLLER_PROC.s_restart_count_4_i_0_o2_0[1]  (.A(
        N_356), .B(N_2481), .C(un1_max_ar_i_NE), .Y(
        s_restart_count_4_i_0_o2_0[1]));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_4  (.A(inf_abs0[4]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[4]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_3), .S(un1_speed_cl_i_cry_4_S), .Y(
        un1_speed_cl_i_cry_4_Y), .FCO(un1_speed_cl_i_cry_4));
    SLE \s_adctrig_count[4]  (.D(s_adctrig_count_s[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[4]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNI9FTC2[7]  (.A(
        VCC), .B(s_sensor_calib_count[7]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[6]), .S(s_sensor_calib_count_s[7]), 
        .Y(s_sensor_calib_count_RNI9FTC2_Y[7]), .FCO(
        s_sensor_calib_count_cry[7]));
    CFG2 #( .INIT(4'hE) )  \s_state_ns_i_0_0_0_o2_RNI7PMI[1]  (.A(
        N_216), .B(N_213), .Y(A0_PWM_VL_O_c));
    SLE \s_state[1]  (.D(N_212_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(s_state[1]));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_14  (.A(inf_abs0[14]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[14]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_13), .S(un1_speed_cl_i_cry_14_S), .Y(
        un1_speed_cl_i_cry_14_Y), .FCO(un1_speed_cl_i_cry_14));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNI4PVS2[9]  (.A(
        VCC), .B(s_sensor_calib_count[9]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[8]), .S(s_sensor_calib_count_s[9]), 
        .Y(s_sensor_calib_count_RNI4PVS2_Y[9]), .FCO(
        s_sensor_calib_count_cry[9]));
    SLE \s_adctrig_count[6]  (.D(s_adctrig_count_s[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[6]));
    SLE \s_sensor_calib_count[0]  (.D(s_sensor_calib_count_s[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[0]));
    CFG4 #( .INIT(16'hB000) )  \s_state_ns_i_i_a2_i_15_i_i_5[5]  (.A(
        apb3_if_0_seq_cntl_config_o[2]), .B(s_state[5]), .C(s_state[6])
        , .D(N_243), .Y(s_state_ns_i_i_a2_i_15_i_i_5[5]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNO[12]  (.A(VCC), .B(
        s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[12]), .D(GND), .FCI(
        s_adctrig_count_cry[11]), .S(s_adctrig_count_s[12]), .Y(
        s_adctrig_count_RNO_Y_0[12]), .FCO(
        s_adctrig_count_RNO_FCO_0[12]));
    SLE cl_status_o (.D(cl_status_o5), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(SEQ_CONTROLLER_0_cl_status_o));
    CFG3 #( .INIT(8'h7F) )  \s_state_ns_i_a3_15_0_a3_i_o2[7]  (.A(
        apb3_if_0_seq_cntl_config_o[0]), .B(s_state[5]), .C(
        un1_inf_abs1), .Y(N_212));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_5  (.A(inf_abs0[8]), 
        .B(inf_abs1[5]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_4), 
        .S(un1_inf_abs1_cry_5_S), .Y(un1_inf_abs1_cry_5_Y), .FCO(
        un1_inf_abs1_cry_5));
    CFG4 #( .INIT(16'hCFEE) )  \s_state_ns_i_0_0_0_o2_0[1]  (.A(N_356), 
        .B(N_2481), .C(s_restart_count_4_i_0_o2_0[1]), .D(
        un1_inf_abs0_1), .Y(N_253));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_5 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[5]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_4_Z), .S(inf_abs0[5]), .Y(
        inf_abs0_cry_5_Y), .FCO(inf_abs0_cry_5_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_3  (.A(inf_abs0[6]), 
        .B(inf_abs1[3]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_2), 
        .S(un1_inf_abs1_cry_3_S), .Y(un1_inf_abs1_cry_3_Y), .FCO(
        un1_inf_abs1_cry_3));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_8  (.A(inf_abs0[8]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[8]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_7), .S(un1_speed_cl_i_cry_8_S), .Y(
        un1_speed_cl_i_cry_8_Y), .FCO(un1_speed_cl_i_cry_8));
    CFG4 #( .INIT(16'hA8A0) )  \s_state_ns_i_i_2_0_4_i_a3[4]  (.A(
        s_state[5]), .B(apb3_if_0_seq_cntl_config_o[0]), .C(
        s_state_ns_i_i_2_0_4_i_o2_2_0[4]), .D(un1_inf_abs1), .Y(N_451));
    CFG4 #( .INIT(16'h3020) )  \s_state_ns_i_o2_7_0_a2_3_a2[6]  (.A(
        s_state87), .B(N_477), .C(s_state[6]), .D(N_440_i), .Y(N_1082));
    CFG4 #( .INIT(16'h8000) )  \s_state_ns_i_3_a0_RNO_2[6]  (.A(
        apb3_if_0_seq_cntl_config_o[3]), .B(PWM_SCALING_1_done_o), .C(
        s_state[6]), .D(apb3_if_0_stop_motor_o), .Y(s_m6_0_a2_2));
    SLE \s_sensor_calib_count[8]  (.D(s_sensor_calib_count_s[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[8]));
    SLE \s_state[2]  (.D(N_294_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(s_state[2]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_11  (.A(inf_abs0[14])
        , .B(inf_abs1[11]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_10)
        , .S(un1_inf_abs1_cry_11_S), .Y(un1_inf_abs1_cry_11_Y), .FCO(
        un1_inf_abs1_cry_11));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_16 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_15_Z), .S(inf_abs1[16]), .Y(inf_abs1_cry_16_Y), 
        .FCO(inf_abs1[17]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_2 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_1_Z), .S(inf_abs1[2]), .Y(inf_abs1_cry_2_Y), .FCO(
        inf_abs1_cry_2_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_16  (.A(inf_abs0[16]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[16]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_15), .S(un1_speed_cl_i_cry_16_S), .Y(
        un1_speed_cl_i_cry_16_Y), .FCO(un1_speed_cl_i_cry_16));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_8 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_7_Z), .S(inf_abs1[8]), .Y(inf_abs1_cry_8_Y), .FCO(
        inf_abs1_cry_8_Z));
    CFG4 #( .INIT(16'h0004) )  \s_state_ns_i_3_a0_RNO_0[6]  (.A(N_185), 
        .B(s_m6_0_a2_2), .C(N_2197_i), .D(N_356), .Y(s_N_13_mux));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_10 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_9_Z), .S(inf_abs1[10]), .Y(inf_abs1_cry_10_Y), 
        .FCO(inf_abs1_cry_10_Z));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_1 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_0_Z), .S(inf_abs1[1]), .Y(inf_abs1_cry_1_Y), .FCO(
        inf_abs1_cry_1_Z));
    CFG4 #( .INIT(16'h2122) )  \s_restart_count_RNO[0]  (.A(
        s_restart_count[0]), .B(s_state[0]), .C(
        s_restart_count_4_i_0_o2_0[1]), .D(un1_inf_abs0_1), .Y(
        N_254_i_0));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIADEQ4[9]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[9]), .D(GND), 
        .FCI(s_adctrig_count_cry[8]), .S(s_adctrig_count_s[9]), .Y(
        s_adctrig_count_RNIADEQ4_Y[9]), .FCO(s_adctrig_count_cry[9]));
    CFG4 #( .INIT(16'hFF80) )  \s_state_ns_i_o2_7[5]  (.A(
        un1_inf_abs0_1_14), .B(un1_inf_abs0_1_1), .C(
        s_state_0_sqmuxa_1_out), .D(s_state88), .Y(N_477));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_17  (.A(inf_abs0[17]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[17]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_16), .S(un1_speed_cl_i_cry_17_S), .Y(
        un1_speed_cl_i_cry_17_Y), .FCO(un1_speed_cl_i));
    SLE \s_adctrig_count[3]  (.D(s_adctrig_count_s[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(N_162_i_0), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[3]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_15  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[15]), .B(inf_abs0[15]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_14), .S(
        un1_inf_abs0_2_cry_15_S), .Y(un1_inf_abs0_2_cry_15_Y), .FCO(
        un1_inf_abs0_2_cry_15));
    CFG4 #( .INIT(16'h0001) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_9  (.A(inf_abs0[0]), 
        .B(inf_abs0[3]), .C(inf_abs0[2]), .D(inf_abs0[1]), .Y(
        un1_inf_abs0_1_9));
    CFG4 #( .INIT(16'h05CD) )  \s_state_ns_i_o3_2[7]  (.A(N_2481), .B(
        s_state_ns_i_o2_10_i_a2_0[7]), .C(N_212), .D(un1_inf_abs0_1), 
        .Y(N_667));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_16  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[16]), .B(inf_abs0[16]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_15), .S(
        un1_inf_abs0_2_cry_16_S), .Y(un1_inf_abs0_2_cry_16_Y), .FCO(
        un1_inf_abs0_2_cry_16));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_4 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[4]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_3_Z), .S(inf_abs0[4]), .Y(
        inf_abs0_cry_4_Y), .FCO(inf_abs0_cry_4_Z));
    CFG4 #( .INIT(16'h0001) )  \s_state_RNO[1]  (.A(N_231), .B(N_253), 
        .C(s_state_ns_i_0_0_0_0[1]), .D(N_216), .Y(N_212_i_0));
    CFG4 #( .INIT(16'hAA08) )  \s_state_ns_0_a2[0]  (.A(
        s_state_ns_0_a2_2[0]), .B(N_264), .C(s_state[8]), .D(
        s_state[2]), .Y(N_401));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_7 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[7]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_6_Z), .S(inf_abs0[7]), .Y(
        inf_abs0_cry_7_Y), .FCO(inf_abs0_cry_7_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_10  (.A(inf_abs0[13])
        , .B(inf_abs1[10]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_9), 
        .S(un1_inf_abs1_cry_10_S), .Y(un1_inf_abs1_cry_10_Y), .FCO(
        un1_inf_abs1_cry_10));
    SLE \s_state[4]  (.D(N_79_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(s_state[4]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_15 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_14_Z), .S(inf_abs1[15]), .Y(inf_abs1_cry_15_Y), 
        .FCO(inf_abs1_cry_15_Z));
    CFG4 #( .INIT(16'h0001) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_12  (.A(inf_abs0[13]), 
        .B(inf_abs0[14]), .C(inf_abs0[17]), .D(inf_abs0[12]), .Y(
        un1_inf_abs0_1_12));
    CFG3 #( .INIT(8'h07) )  s_state_1_sqmuxa_1_0_0 (.A(
        apb3_if_0_seq_cntl_config_o[3]), .B(N_2197_i), .C(
        PWM_SCALING_1_done_o), .Y(s_state_1_sqmuxa_1_0_0_Z));
    CFG4 #( .INIT(16'h207D) )  \s_state_ns_i_o3_26_0_0_a2_0_0_2[6]  (
        .A(s_state_ns_i_o3_26_0_0_a2_0_0_2_1[6]), .B(
        apb3_if_0_stop_motor_o), .C(un1_max_ar_i_NE), .D(N_187), .Y(
        s_state_ns_i_o3_26_0_0_a2_0_0_2[6]));
    CFG4 #( .INIT(16'hFFFE) )  \s_sensor_calib_count_RNIJFN21[9]  (.A(
        s_sensor_calib_count[12]), .B(s_sensor_calib_count[11]), .C(
        s_sensor_calib_count[10]), .D(s_sensor_calib_count[9]), .Y(
        N_482_i_0_i_0_i_o2_0_o3_8));
    CFG2 #( .INIT(4'hE) )  \s_state_ns_i_0_0_0_o2[1]  (.A(N_187), .B(
        s_state[2]), .Y(N_216));
    CFG4 #( .INIT(16'hFF70) )  s_state_1_sqmuxa_1_0 (.A(
        un1_inf_abs0_1_14), .B(un1_inf_abs0_1_1), .C(s_state87), .D(
        s_state_1_sqmuxa_1_0_0_Z), .Y(N_243));
    CFG4 #( .INIT(16'h4441) )  \s_restart_count_RNO[3]  (.A(s_state[0])
        , .B(s_restart_count[3]), .C(N_199), .D(
        s_restart_count_4_i_0_o3_0_0[2]), .Y(N_260_i_0));
    SLE \s_sensor_calib_count[2]  (.D(s_sensor_calib_count_s[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[2]));
    SLE \s_sensor_calib_count[13]  (.D(s_sensor_calib_count_s[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[13]));
    CFG3 #( .INIT(8'hB3) )  \s_state_ns_i_i_a2_i_15_i_i_o3[5]  (.A(
        apb3_if_0_seq_cntl_config_o[0]), .B(s_state[5]), .C(
        un1_inf_abs1), .Y(N_268));
    CFG4 #( .INIT(16'h1F11) )  \s_state_ns_0_o3[0]  (.A(N_2197_i), .B(
        N_356), .C(un1_stop_motor_i_1), .D(un1_inf_abs0_1), .Y(N_219));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_3  (.A(inf_abs0[3]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[3]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_2), .S(un1_speed_cl_i_cry_3_S), .Y(
        un1_speed_cl_i_cry_3_Y), .FCO(un1_speed_cl_i_cry_3));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIV7PC1[3]  (.A(
        VCC), .B(s_sensor_calib_count[3]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[2]), .S(s_sensor_calib_count_s[3]), 
        .Y(s_sensor_calib_count_RNIV7PC1_Y[3]), .FCO(
        s_sensor_calib_count_cry[3]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_7 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_6_Z), .S(inf_abs1[7]), .Y(inf_abs1_cry_7_Y), .FCO(
        inf_abs1_cry_7_Z));
    CFG4 #( .INIT(16'hC0E2) )  \s_state_ns_i_3_a0[6]  (.A(d_m6_1), .B(
        s_N_13_mux), .C(un1_inf_abs0_1), .D(d_N_7), .Y(
        s_state_ns_i_3_a0_2[6]));
    CFG3 #( .INIT(8'hFE) )  \state_o_RNO[1]  (.A(s_state[3]), .B(
        s_state[2]), .C(N_213), .Y(N_892_i_0));
    CFG4 #( .INIT(16'hFF7F) )  
        \FSM_SEQ_CONTROLLER_PROC.s_restart_count_4_i_0_o3[1]  (.A(
        un1_inf_abs0_1_14), .B(un1_inf_abs0_1_1), .C(
        s_restart_count[0]), .D(s_restart_count_4_i_0_o2_0[1]), .Y(
        N_199));
    CFG2 #( .INIT(4'hE) )  \s_state_ns_i_a3_0_0_a2_0_o3[6]  (.A(
        s_state[3]), .B(s_state[4]), .Y(N_185));
    SLE \s_sensor_calib_count[12]  (.D(s_sensor_calib_count_s[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[12]));
    CFG2 #( .INIT(4'hD) )  \s_sensor_calib_count_RNI0PTG[2]  (.A(
        s_sensor_calib_count[13]), .B(s_sensor_calib_count[2]), .Y(
        N_482_i_0_i_0_i_o2_0_o3_6));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_9  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[9]), .B(inf_abs0[9]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_8), .S(un1_inf_abs0_2_cry_9_S)
        , .Y(un1_inf_abs0_2_cry_9_Y), .FCO(un1_inf_abs0_2_cry_9));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_9  (.A(inf_abs0[9]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[9]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_8), .S(un1_speed_cl_i_cry_9_S), .Y(
        un1_speed_cl_i_cry_9_Y), .FCO(un1_speed_cl_i_cry_9));
    SLE \s_state[6]  (.D(N_222_i_0), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(s_state[6]));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_2  (.A(inf_abs0[5]), 
        .B(inf_abs1[2]), .C(GND), .D(GND), .FCI(un1_inf_abs1_cry_1), 
        .S(un1_inf_abs1_cry_2_S), .Y(un1_inf_abs1_cry_2_Y), .FCO(
        un1_inf_abs1_cry_2));
    CFG4 #( .INIT(16'hECA0) )  \ADC_START_PROC.adc_start_o_4_iv_0_0  (
        .A(s_state[1]), .B(PWM3PH_1_midmatch_o), .C(adc_start_o5), .D(
        A0_PWM_VL_O_c), .Y(adc_start_o_4));
    CFG4 #( .INIT(16'hF222) )  \s_state_ns_0_0[0]  (.A(
        s_state_ns_0_a2_3_1[0]), .B(N_187), .C(N_572_li), .D(
        s_state[8]), .Y(s_state_ns_0_0[0]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNITBS42[6]  (.A(
        VCC), .B(s_sensor_calib_count[6]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[5]), .S(s_sensor_calib_count_s[6]), 
        .Y(s_sensor_calib_count_RNITBS42_Y[6]), .FCO(
        s_sensor_calib_count_cry[6]));
    ARI1 #( .INIT(20'h46600) )  inf_abs1_cry_13 (.A(VCC), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13]), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .D(GND), .FCI(
        inf_abs1_cry_12_Z), .S(inf_abs1[13]), .Y(inf_abs1_cry_13_Y), 
        .FCO(inf_abs1_cry_13_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_1  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[1]), .B(inf_abs0[1]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_0), .S(un1_inf_abs0_2_cry_1_S)
        , .Y(un1_inf_abs0_2_cry_1_Y), .FCO(un1_inf_abs0_2_cry_1));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_11 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[11]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_10_Z), .S(inf_abs0[11]), .Y(
        inf_abs0_cry_11_Y), .FCO(inf_abs0_cry_11_Z));
    CFG2 #( .INIT(4'h4) )  \s_state_ns_i_o2_10_i_a2_0[7]  (.A(
        un1_stop_motor_i_1), .B(N_356), .Y(
        s_state_ns_i_o2_10_i_a2_0[7]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIT7VB4[8]  (.A(VCC), 
        .B(s_state_RNIL5O9_Y[1]), .C(s_adctrig_count[8]), .D(GND), 
        .FCI(s_adctrig_count_cry[7]), .S(s_adctrig_count_s[8]), .Y(
        s_adctrig_count_RNIT7VB4_Y[8]), .FCO(s_adctrig_count_cry[8]));
    SLE \s_state[8]  (.D(s_state_ns[8]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_state[8]));
    CFG2 #( .INIT(4'h1) )  \s_state_fast_RNIHKRN[1]  (.A(
        s_state_fast[1]), .B(s_state_fast[2]), .Y(N_499));
    ARI1 #( .INIT(20'h5AA55) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_14  (.A(
        apb3_if_0_seq_cntl_cl_omega_o[14]), .B(inf_abs0[14]), .C(GND), 
        .D(GND), .FCI(un1_inf_abs0_2_cry_13), .S(
        un1_inf_abs0_2_cry_14_S), .Y(un1_inf_abs0_2_cry_14_Y), .FCO(
        un1_inf_abs0_2_cry_14));
    ARI1 #( .INIT(20'h46600) )  inf_abs0_cry_14 (.A(VCC), .B(
        RATE_LIMITER_0_rl_out_o[14]), .C(RATE_LIMITER_0_rl_out_o[17]), 
        .D(GND), .FCI(inf_abs0_cry_13_Z), .S(inf_abs0[14]), .Y(
        inf_abs0_cry_14_Y), .FCO(inf_abs0_cry_14_Z));
    ARI1 #( .INIT(20'h5AA55) )  
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_6  (.A(inf_abs0[6]), .B(
        apb3_if_0_seq_cntl_cl_omega_o[6]), .C(GND), .D(GND), .FCI(
        un1_speed_cl_i_cry_5), .S(un1_speed_cl_i_cry_6_S), .Y(
        un1_speed_cl_i_cry_6_Y), .FCO(un1_speed_cl_i_cry_6));
    CFG4 #( .INIT(16'h1000) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_14  (.A(inf_abs0[8]), 
        .B(inf_abs0[9]), .C(un1_inf_abs0_1_14_3), .D(
        un1_inf_abs0_1_14_4), .Y(un1_inf_abs0_1_14));
    CFG4 #( .INIT(16'h008D) )  \s_state_ns_i_3_a0_RNO_1[6]  (.A(N_356), 
        .B(un1_max_ar_i_NE), .C(PWM_SCALING_1_done_o), .D(N_2197_i), 
        .Y(d_N_7));
    CFG2 #( .INIT(4'h1) )  \s_state_ns_i_0_0_0_o2_RNI7PMI_0[1]  (.A(
        N_216), .B(N_213), .Y(A0_PWM_VL_O_c_i_0));
    SLE \s_restart_count[1]  (.D(N_2369_i_0), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_restart_count[1]));
    CFG4 #( .INIT(16'hFEFA) )  \EN_SPEED_PI_PROC.cl_status_o5_0_0  (.A(
        s_state[5]), .B(s_state[6]), .C(N_356), .D(un1_speed_cl_i), .Y(
        cl_status_o5));
    
endmodule


module accumulator_rl_18s(
       s_ref_val_buf,
       s_ramp_out,
       reset_i,
       sys_clk_i,
       N_680_i,
       reset_rl_i,
       s_rl_done
    );
output [16:0] s_ref_val_buf;
input  [17:0] s_ramp_out;
input  reset_i;
input  sys_clk_i;
output N_680_i;
input  reset_rl_i;
input  s_rl_done;

    wire [17:0] rl_out_prev_o_3;
    wire MSC_net_58, MSC_net_59, MSC_net_60;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
CaY5wQifhrNLQVGxFD4mUFzqmIlV5MK0qLTkjfBEw66evtSWPv10NYwukI1tnALY
oXwoQiqvr1jVnQYVqP9zF+R1MQaPVpKCYSkBYGG+OjEvNFXaAX3TwHdXF96lwHpT
jA+jGycl7Z0vLhLPs2iG6u2Q5t7JRns1uP9L1DxxRsQ=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8885)
`pragma protect data_block
[encoded data, 8704 characters]
iLfL/e/yy45NLT2MGx3A9pbw3beCKEeW/SOkaCr6odQ=

`pragma protect end_protected

endmodule


module RATE_LIMITER(
       reset_i,
       sys_clk_i,
       start_i,
       soft_stop_i,
       reset_rl_i,
       direction_i,
       slew_count_i,
       rate_count_i,
       rl_in_i,
       rl_out_o,
       rl_done_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  soft_stop_i;
input  reset_rl_i;
input  direction_i;
input  [17:0] slew_count_i;
input  [17:0] rate_count_i;
input  [17:0] rl_in_i;
output [17:0] rl_out_o;
output rl_done_o;

    wire [16:0] s_ref_val_buf;
    wire [17:1] s_set_ref;
    wire [18:0] s_count;
    wire [1:0] s_ramp_present_state;
    wire [1:1] s_ramp_present_state_ns;
    wire [17:0] s_ramp_out_8;
    wire [17:0] un2_s_rate_count_minus;
    wire [17:0] s_set_ref_5;
    wire [17:1] s_rl_in;
    wire [18:1] s_diff_Z;
    wire [18:1] s_rate_count_minus;
    wire [17:0] s_count_cry;
    wire [18:0] s_count_s;
    wire [0:0] s_ramp_present_state_i_0;
    wire [0:0] rate_count_i_i;
    wire [0:0] s_count_i;
    wire [16:16] un2_s_rate_count_minus_RNI4LS8I_Y;
    wire [17:17] s_ramp_out_8_RNO_FCO;
    wire [17:17] s_ramp_out_8_RNO_Y;
    wire [15:15] un2_s_rate_count_minus_RNIFGJAH_Y;
    wire [14:14] un2_s_rate_count_minus_RNITEACG_Y;
    wire [13:13] un2_s_rate_count_minus_RNIEG1EF_Y;
    wire [12:12] un2_s_rate_count_minus_RNI2LOFE_Y;
    wire [11:11] un2_s_rate_count_minus_RNIPSFHD_Y;
    wire [10:10] un2_s_rate_count_minus_RNIJ77JC_Y;
    wire [9:9] un2_s_rate_count_minus_RNIGLUKB_Y;
    wire [8:8] un2_s_rate_count_minus_RNI5D5HA_Y;
    wire [7:7] un2_s_rate_count_minus_RNIT7CD9_Y;
    wire [6:6] un2_s_rate_count_minus_RNIO5J98_Y;
    wire [5:5] un2_s_rate_count_minus_RNIM6Q57_Y;
    wire [4:4] un2_s_rate_count_minus_RNINA126_Y;
    wire [3:3] un2_s_rate_count_minus_RNIRH8U4_Y;
    wire [2:2] un2_s_rate_count_minus_RNI2SFQ3_Y;
    wire [1:1] un2_s_rate_count_minus_RNIC9NM2_Y;
    wire [0:0] un2_s_rate_count_minus_RNIPPUI1_Y;
    wire [17:17] s_count_RNIT51DM_Y;
    wire [18:18] s_count_RNO_FCO;
    wire [18:18] s_count_RNO_Y;
    wire [16:16] s_count_RNIGI45L_Y;
    wire [15:15] s_count_RNI408TJ_Y;
    wire [14:14] s_count_RNIPEBLI_Y;
    wire [13:13] s_count_RNIFUEDH_Y;
    wire [12:12] s_count_RNI6FI5G_Y;
    wire [11:11] s_count_RNIU0MTE_Y;
    wire [10:10] s_count_RNINJPLD_Y;
    wire [9:9] s_count_RNIH7TDC_Y;
    wire [8:8] s_count_RNIJBK8B_Y;
    wire [7:7] s_count_RNIMGB3A_Y;
    wire [6:6] s_count_RNIQM2U8_Y;
    wire [5:5] s_count_RNIVTPO7_Y;
    wire [4:4] s_count_RNI56HJ6_Y;
    wire [3:3] s_count_RNICF8E5_Y;
    wire [2:2] s_count_RNIKPV84_Y;
    wire [1:1] s_count_RNIT4N33_Y;
    wire [0:0] s_count_RNI7HEU1_Y;
    wire \FSM_RATE_LIM_PROC.un1_s_count_1 , 
        \FSM_RATE_LIM_PROC.un1_s_count_2 , 
        \FSM_RATE_LIM_PROC.un1_s_count_3 , 
        \FSM_RATE_LIM_PROC.un1_s_count_4 , 
        \FSM_RATE_LIM_PROC.un1_s_count_5 , 
        \FSM_RATE_LIM_PROC.un1_s_count_6 , 
        \FSM_RATE_LIM_PROC.un1_s_count_7 , 
        \FSM_RATE_LIM_PROC.un1_s_count_8 , 
        \FSM_RATE_LIM_PROC.un1_s_count_9 , 
        \FSM_RATE_LIM_PROC.un1_s_count_10 , 
        \FSM_RATE_LIM_PROC.un1_s_count_11 , 
        \FSM_RATE_LIM_PROC.un1_s_count_12 , 
        \FSM_RATE_LIM_PROC.un1_s_count_13 , 
        \FSM_RATE_LIM_PROC.un1_s_count_14 , 
        \FSM_RATE_LIM_PROC.un1_s_count_15 , 
        \FSM_RATE_LIM_PROC.un1_s_count_16 , 
        \FSM_RATE_LIM_PROC.un1_s_count_17 , MSC_net_338, MSC_net_339, 
        MSC_net_340, MSC_net_341, \FSM_RATE_LIM_PROC.s_ramp_out11 , 
        \FSM_RATE_LIM_PROC.un1_s_diff , 
        \FSM_RATE_LIM_PROC.un1_s_count , MSC_net_345, MSC_net_346, 
        MSC_net_347, MSC_net_348, MSC_net_349, 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_0_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_1_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_2_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_3_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_4_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_5_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_6_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_7_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_8_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_9_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_10_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_11_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_12_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_13_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_14_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_15_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_16_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_17_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_0_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_1_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_2_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_3_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_4_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_5_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_6_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_7_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_8_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_9_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_10_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_11_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_12_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_13_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_14_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_15_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_16_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_17_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_Z , MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459, MSC_net_460, 
        MSC_net_461, MSC_net_462, MSC_net_463, MSC_net_464, 
        MSC_net_465, MSC_net_466, MSC_net_467, MSC_net_468, 
        MSC_net_469, MSC_net_470, MSC_net_471, MSC_net_472, 
        MSC_net_473, MSC_net_474, MSC_net_475, MSC_net_476, 
        MSC_net_477, MSC_net_478, MSC_net_479, MSC_net_480, 
        MSC_net_481, MSC_net_482, MSC_net_483, MSC_net_484, 
        MSC_net_485, MSC_net_486, MSC_net_487, MSC_net_488, 
        MSC_net_489, MSC_net_490, MSC_net_491, MSC_net_492, 
        MSC_net_493, MSC_net_494, MSC_net_495, MSC_net_496, 
        MSC_net_497, MSC_net_498, MSC_net_499, MSC_net_500, 
        MSC_net_501, MSC_net_502, MSC_net_503, MSC_net_504, 
        MSC_net_505, MSC_net_506, MSC_net_507, MSC_net_508, 
        MSC_net_509, MSC_net_510, MSC_net_511, MSC_net_512, 
        MSC_net_513, MSC_net_514, MSC_net_515, MSC_net_516, 
        MSC_net_517, \FSM_RATE_LIM_PROC.s_ramp_out11_cry_18_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_18_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_17_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_17_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_16_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_16_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_15_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_15_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_14_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_14_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_13_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_13_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_12_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_12_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_11_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_11_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_10_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_10_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_9_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_9_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_8_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_8_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_7_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_7_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_6_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_6_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_5_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_5_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_4_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_4_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_3_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_3_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_2_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_2_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_1_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_1_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_0_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_0_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_18_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_18_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_17_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_17_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_16_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_16_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_15_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_15_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_14_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_14_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_13_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_13_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_12_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_12_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_11_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_11_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_10_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_10_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_9_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_9_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_8_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_8_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_7_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_7_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_6_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_6_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_5_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_5_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_4_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_4_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_3_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_3_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_2_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_2_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_1_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_1_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_0_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_0_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_18_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_18_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_Y , MSC_net_632, 
        MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        MSC_net_641, MSC_net_642, MSC_net_643, MSC_net_644, 
        MSC_net_645, MSC_net_646, MSC_net_647, MSC_net_648, 
        MSC_net_649, MSC_net_650, MSC_net_651, MSC_net_652, 
        MSC_net_653, MSC_net_654, MSC_net_655, MSC_net_656, 
        MSC_net_657, MSC_net_658, MSC_net_659, MSC_net_660, 
        MSC_net_661, MSC_net_662, MSC_net_663, MSC_net_664, 
        MSC_net_665, MSC_net_666, MSC_net_667, MSC_net_668, 
        MSC_net_669, MSC_net_670, MSC_net_671, MSC_net_672, 
        MSC_net_673, MSC_net_674, MSC_net_675, MSC_net_676, 
        MSC_net_677, MSC_net_678, MSC_net_679, MSC_net_680, 
        MSC_net_681, MSC_net_682, MSC_net_683, MSC_net_684, 
        MSC_net_685, MSC_net_686, MSC_net_687, MSC_net_688, 
        MSC_net_689, MSC_net_690, MSC_net_691, MSC_net_692, 
        MSC_net_693, MSC_net_694, 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_18_RNI9D6F_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_18_RNI9D6F_Y , MSC_net_697, 
        MSC_net_698, MSC_net_699, MSC_net_700, MSC_net_701, 
        MSC_net_702, MSC_net_703, MSC_net_704, MSC_net_705, 
        MSC_net_706, MSC_net_707, MSC_net_708, MSC_net_709, 
        MSC_net_710, MSC_net_711, MSC_net_712, MSC_net_713, 
        MSC_net_714, MSC_net_715, MSC_net_716, MSC_net_717, 
        MSC_net_718, MSC_net_719;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
R2MHj86n31Y1u+xypoUCpzH7pacNFYejUj/6T3jARBQw+4vE+IlJ3Ig4p62VYy17
wO+UoJCvR9nHZQNhUzju4Tkm0OwGvJo35VE3GQlxQFjKhSfGTdhprAOgJ1x2RGS1
iGsOqwqYBW/aEn7SEgnMp3ykj/ljJNZxC/gadgK4dnc=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=98000)
`pragma protect data_block
[encoded data, 96448 characters]
+bk6fPk6BcJPa44ZhQTSqKvqnFVyTR+d1dwIBNOMxQY=

`pragma protect end_protected

endmodule


module mas_adc_scl_44s_18s_2s_1(
       s_product,
       adc_scale_val_i,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       un1_s_mul1_1_axb_0_i_0,
       un1_s_mul1_1_cry_1_S,
       un1_s_mul1_1_cry_2_S,
       un1_s_mul1_1_cry_3_S,
       un1_s_mul1_1_cry_4_S,
       un1_s_mul1_1_cry_5_S,
       un1_s_mul1_1_cry_6_S,
       un1_s_mul1_1_cry_7_S,
       un1_s_mul1_1_cry_8_S,
       un1_s_mul1_1_cry_9_S,
       un1_s_mul1_1_cry_10_S,
       un1_s_mul1_1_cry_11_S,
       un1_s_mul1_1_cry_12_S,
       un1_s_mul1_1_cry_13_S,
       un1_s_mul1_1_cry_14_S,
       un1_s_mul1_1_cry_15_S,
       un1_s_mul1_1_cry_16_S,
       un1_s_mul1_1_s_17_S,
       un1_s_ia_0_sqmuxa_0
    );
output [25:8] s_product;
input  [17:0] adc_scale_val_i;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
input  un1_s_mul1_1_axb_0_i_0;
input  un1_s_mul1_1_cry_1_S;
input  un1_s_mul1_1_cry_2_S;
input  un1_s_mul1_1_cry_3_S;
input  un1_s_mul1_1_cry_4_S;
input  un1_s_mul1_1_cry_5_S;
input  un1_s_mul1_1_cry_6_S;
input  un1_s_mul1_1_cry_7_S;
input  un1_s_mul1_1_cry_8_S;
input  un1_s_mul1_1_cry_9_S;
input  un1_s_mul1_1_cry_10_S;
input  un1_s_mul1_1_cry_11_S;
input  un1_s_mul1_1_cry_12_S;
input  un1_s_mul1_1_cry_13_S;
input  un1_s_mul1_1_cry_14_S;
input  un1_s_mul1_1_cry_15_S;
input  un1_s_mul1_1_cry_16_S;
input  un1_s_mul1_1_s_17_S;
input  un1_s_ia_0_sqmuxa_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [35:0] product_o;
    wire [43:36] product_o_ONC;
    wire MSC_net_148, MSC_net_149, MSC_net_150, MSC_net_151, 
        MSC_net_152, MSC_net_153, MSC_net_154, MSC_net_155, 
        MSC_net_156, MSC_net_157, MSC_net_158, MSC_net_159, 
        MSC_net_160, MSC_net_161, MSC_net_162, MSC_net_163, 
        MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
S/hJsK34zYqAtE6p102SvZYHDdTTpinZ4/DzaKZ1ISf5vU9nHEIxQNS6/DYpnLLG
DfwLgmcRgTUDg/UxdbJdNaNtFFOJyWW6+17ROmaG+tp1mCvt7owzkxA75MCwbyk5
gqNrzCQszARvbL1Voo2N+WOTQSCsJqlFbF2rgsxPdgU=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8540)
`pragma protect data_block
[encoded data, 8384 characters]
aq4Oi+By3aAK+wDLXkNVSg==

`pragma protect end_protected

endmodule


module ADC_SCALING_0s_12s_2s_8192_5_44s_0_2_3_1(
       reset_i,
       sys_clk_i,
       adc_results_rdy_i,
       adc_scale_val_i,
       adc_result_ch0_i,
       adc_result_ch1_i,
       fault_threshold_i,
       done_o,
       calib_done_o,
       over_current_fault_o,
       ia_adc_o,
       ib_adc_o
    );
input  reset_i;
input  sys_clk_i;
input  adc_results_rdy_i;
input  [17:0] adc_scale_val_i;
input  [11:0] adc_result_ch0_i;
input  [11:0] adc_result_ch1_i;
input  [17:0] fault_threshold_i;
output done_o;
output calib_done_o;
output over_current_fault_o;
output [17:0] ia_adc_o;
output [17:0] ib_adc_o;

    wire [11:1] un1_s_mul1_1_m;
    wire [25:8] s_product;
    wire [30:0] s_adc_ch0_offset;
    wire [30:0] s_adc_ch1_offset;
    wire [1:0] s_state;
    wire [1:0] s_state_ns;
    wire [17:0] inf_abs1;
    wire [17:0] inf_abs0;
    wire [13:0] s_calib_cnt;
    wire [12:0] s_calib_cnt_cry;
    wire [13:0] s_calib_cnt_s;
    wire [11:1] un1_s_mul1_0;
    wire [12:0] s_calib_cnt_cry_Y;
    wire [13:13] s_calib_cnt_s_FCO;
    wire [13:13] s_calib_cnt_s_Y;
    wire [0:0] s_calib_cnt_cry_cy_S;
    wire [0:0] s_calib_cnt_cry_cy_Y;
    wire MSC_net_302, MSC_net_303, MSC_net_304, MSC_net_305, 
        MSC_net_306, MSC_net_307, MSC_net_308, MSC_net_309, 
        MSC_net_310, MSC_net_311, MSC_net_312, MSC_net_313, 
        MSC_net_314, MSC_net_315, MSC_net_316, MSC_net_317, 
        MSC_net_318, MSC_net_319, MSC_net_320, MSC_net_321, 
        MSC_net_322, MSC_net_323, MSC_net_324, MSC_net_325, 
        MSC_net_326, MSC_net_327, MSC_net_328, MSC_net_329, 
        MSC_net_330, MSC_net_331, MSC_net_332, MSC_net_333, 
        MSC_net_334, MSC_net_335, MSC_net_336, MSC_net_337, 
        MSC_net_338, MSC_net_339, MSC_net_340, MSC_net_341, 
        MSC_net_342, MSC_net_343, MSC_net_344, MSC_net_345, 
        MSC_net_346, MSC_net_347, MSC_net_348, MSC_net_349, 
        MSC_net_350, MSC_net_351, MSC_net_352, MSC_net_353, 
        MSC_net_354, MSC_net_355, MSC_net_356, MSC_net_357, 
        MSC_net_358, MSC_net_359, MSC_net_360, MSC_net_361, 
        MSC_net_362, MSC_net_363, MSC_net_364, MSC_net_365, 
        MSC_net_366, MSC_net_367, MSC_net_368, MSC_net_369, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1 , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5 , 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Z , 
        MSC_net_414, MSC_net_415, MSC_net_416, MSC_net_417, 
        MSC_net_418, MSC_net_419, MSC_net_420, MSC_net_421, 
        MSC_net_422, MSC_net_423, MSC_net_424, MSC_net_425, 
        MSC_net_426, MSC_net_427, MSC_net_428, MSC_net_429, 
        MSC_net_430, MSC_net_431, MSC_net_432, MSC_net_433, 
        MSC_net_434, MSC_net_435, MSC_net_436, MSC_net_437, 
        MSC_net_438, MSC_net_439, MSC_net_440, MSC_net_441, 
        MSC_net_442, MSC_net_443, MSC_net_444, MSC_net_445, 
        MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, MSC_net_457, 
        MSC_net_458, MSC_net_459, MSC_net_460, MSC_net_461, 
        MSC_net_462, MSC_net_463, MSC_net_464, MSC_net_465, 
        MSC_net_466, MSC_net_467, MSC_net_468, MSC_net_469, 
        MSC_net_470, MSC_net_471, MSC_net_472, MSC_net_473, 
        MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, MSC_net_489, 
        MSC_net_490, MSC_net_491, MSC_net_492, MSC_net_493, 
        MSC_net_494, MSC_net_495, MSC_net_496, MSC_net_497, 
        MSC_net_498, MSC_net_499, MSC_net_500, MSC_net_501, 
        MSC_net_502, MSC_net_503, MSC_net_504, MSC_net_505, 
        MSC_net_506, MSC_net_507, MSC_net_508, MSC_net_509, 
        MSC_net_510, MSC_net_511, MSC_net_512, MSC_net_513, 
        MSC_net_514, MSC_net_515, MSC_net_516, MSC_net_517, 
        MSC_net_518, MSC_net_519, MSC_net_520, MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526, MSC_net_527, MSC_net_528, MSC_net_529, 
        MSC_net_530, MSC_net_531, MSC_net_532, MSC_net_533, 
        MSC_net_534, MSC_net_535, MSC_net_536, MSC_net_537, 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_S , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_Y , 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_0_Y , 
        MSC_net_581, MSC_net_582, MSC_net_583, MSC_net_584, 
        MSC_net_585, MSC_net_586, MSC_net_587, MSC_net_588, 
        MSC_net_589, MSC_net_590, MSC_net_591, MSC_net_592, 
        MSC_net_593, MSC_net_594, MSC_net_595, MSC_net_596, 
        MSC_net_597, MSC_net_598, MSC_net_599, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Y , 
        MSC_net_668, MSC_net_669, MSC_net_670, MSC_net_671, 
        MSC_net_672, MSC_net_673, MSC_net_674, MSC_net_675, 
        MSC_net_676, MSC_net_677, MSC_net_678, MSC_net_679, 
        MSC_net_680, MSC_net_681, MSC_net_682, MSC_net_683, 
        MSC_net_684, MSC_net_685, MSC_net_686, MSC_net_687, 
        MSC_net_688, MSC_net_689, MSC_net_690, MSC_net_691, 
        MSC_net_692, MSC_net_693, MSC_net_694, MSC_net_695, 
        MSC_net_696, MSC_net_697, MSC_net_698, MSC_net_699, 
        MSC_net_700, MSC_net_701, MSC_net_702, MSC_net_703, 
        MSC_net_704, MSC_net_705, MSC_net_706, MSC_net_707, 
        MSC_net_708, MSC_net_709, MSC_net_710, MSC_net_711, 
        MSC_net_712, MSC_net_713, MSC_net_714, MSC_net_715, 
        MSC_net_716, MSC_net_717, MSC_net_718, MSC_net_719, 
        MSC_net_720, MSC_net_721, MSC_net_722, MSC_net_723, 
        MSC_net_724, MSC_net_725, MSC_net_726, MSC_net_727, 
        MSC_net_728, MSC_net_729, MSC_net_730, MSC_net_731, 
        MSC_net_732, MSC_net_733, MSC_net_734, MSC_net_735, 
        MSC_net_736, MSC_net_737, MSC_net_738, MSC_net_739, 
        MSC_net_740, MSC_net_741, MSC_net_742, MSC_net_743, 
        MSC_net_744, MSC_net_745, MSC_net_746, MSC_net_747, 
        MSC_net_748, MSC_net_749, MSC_net_750, MSC_net_751, 
        MSC_net_752, MSC_net_753, MSC_net_754;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
bRzP74ImjMhgF2it2Hbwcubl3kMFLDqEnk2I1MvV0oovXfMZ/Z8BU6YbYf/W1W2z
MSZt2I4vLz+1bPyn7Xj891AZ7oeUtn3yjb9JDRKvth2Td+BilNqpvvNTQbveDUr1
pdi3cHvG+WAx2DEgr4ZdE/oyrZpV4KGfR8oGqxU25H0=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=115680)
`pragma protect data_block
[encoded data, 113856 characters]
vLpr30XS3A37CwdXL0WHmSyyDP8c9dzdGvjwyGS2rMc=

`pragma protect end_protected

endmodule


module mas_bm_be_44s_18s_2s(
       s_mult_result,
       s_mult0_input_6,
       s_mult1_input_6,
       s_addc_input_4,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       N_70_0
    );
output [43:0] s_mult_result;
input  [17:0] s_mult0_input_6;
input  [17:0] s_mult1_input_6;
input  [43:0] s_addc_input_4;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
input  N_70_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire MSC_net_174, MSC_net_175, MSC_net_176;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
AChUFvW9NAa+A/EXbVZcouFGLsNoUVfPmXYuqdb6l58j7mifAb9YI1P3oYKi514E
6cjxUZjHOc523mH2rd8hjMMfv5FQK62YXGN8M66vK9MVTFr014QpEe2q/31hfX/A
bZ/x4qRoWUv6qlPKyLWlGguhlOzP+WbM/nBGX7dbaaI=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=9035)
`pragma protect data_block
[encoded data, 8896 characters]

`pragma protect end_protected

endmodule


module bldc_model_Z2_layer1(
       ealpha_o,
       ebeta_o,
       i_alpha_i,
       s_i_alpha_buf,
       i_beta_i,
       s_i_beta_buf,
       v_alpha_i,
       v_beta_i,
       Ls_by_Ts_pu_i,
       Rs_pu_i,
       reset_i,
       sys_clk_i,
       s_flux_estimator_done,
       start_i
    );
output [17:0] ealpha_o;
output [17:0] ebeta_o;
input  [17:0] i_alpha_i;
input  [17:0] s_i_alpha_buf;
input  [17:0] i_beta_i;
input  [17:0] s_i_beta_buf;
input  [17:0] v_alpha_i;
input  [17:0] v_beta_i;
input  [17:0] Ls_by_Ts_pu_i;
input  [17:0] Rs_pu_i;
input  reset_i;
input  sys_clk_i;
output s_flux_estimator_done;
input  start_i;

    wire [6:0] s_state;
    wire [17:0] s_d_ialpha;
    wire [17:1] s_sum_ialbuf;
    wire [17:0] s_d_ibeta;
    wire [17:1] s_diff_ibetbuf;
    wire [17:0] s_ialpha_res;
    wire [43:0] s_mult_result;
    wire [17:0] s_ibeta_res;
    wire [1:0] s_state_ns;
    wire [17:0] i_beta_i_m;
    wire [17:0] s_mult0_input_6_iv_0;
    wire [43:0] s_addc_input_4;
    wire [17:0] s_mult1_input_6;
    wire [17:0] s_mult0_input_6;
    wire MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, MSC_net_470, 
        MSC_net_471, MSC_net_472, MSC_net_473, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488, MSC_net_489, MSC_net_490, 
        MSC_net_491, MSC_net_492, MSC_net_493, MSC_net_494, 
        MSC_net_495, MSC_net_496, MSC_net_497, MSC_net_498, 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, MSC_net_518, 
        MSC_net_519, MSC_net_520, MSC_net_521, MSC_net_522, 
        MSC_net_523, MSC_net_524, MSC_net_525, MSC_net_526, 
        MSC_net_527, MSC_net_528, MSC_net_529, MSC_net_530, 
        MSC_net_531, MSC_net_532, MSC_net_533, MSC_net_534, 
        MSC_net_535, MSC_net_536, MSC_net_537, MSC_net_538, 
        MSC_net_539, MSC_net_540, MSC_net_541, MSC_net_542, 
        MSC_net_543, MSC_net_544, MSC_net_545, MSC_net_546, 
        MSC_net_547, MSC_net_548, MSC_net_549, MSC_net_550, 
        MSC_net_551, MSC_net_552, MSC_net_553, MSC_net_554, 
        MSC_net_555, MSC_net_556, MSC_net_557, MSC_net_558, 
        MSC_net_559, MSC_net_560, MSC_net_561, MSC_net_562, 
        MSC_net_563, MSC_net_564, MSC_net_565, MSC_net_566, 
        MSC_net_567, MSC_net_568, MSC_net_569, MSC_net_570, 
        MSC_net_571, MSC_net_572, MSC_net_573, MSC_net_574, 
        MSC_net_575, MSC_net_576, MSC_net_577, MSC_net_578, 
        MSC_net_579, MSC_net_580, MSC_net_581, MSC_net_582, 
        MSC_net_583, MSC_net_584, MSC_net_585, MSC_net_586, 
        MSC_net_587, MSC_net_588, MSC_net_589, MSC_net_590, 
        MSC_net_591, MSC_net_592, MSC_net_593, MSC_net_594, 
        MSC_net_595, MSC_net_596, MSC_net_597, MSC_net_598, 
        MSC_net_599, MSC_net_600, MSC_net_601, MSC_net_602, 
        MSC_net_603, MSC_net_604, MSC_net_605, MSC_net_606, 
        MSC_net_607, MSC_net_608, MSC_net_609, MSC_net_610, 
        MSC_net_611, MSC_net_612, MSC_net_613, MSC_net_614, 
        MSC_net_615, MSC_net_616, MSC_net_617, MSC_net_618, 
        MSC_net_619, MSC_net_620, MSC_net_621, MSC_net_622, 
        MSC_net_623, MSC_net_624, MSC_net_625, MSC_net_626, 
        MSC_net_627, MSC_net_628, MSC_net_629, MSC_net_630, 
        MSC_net_631, MSC_net_632, MSC_net_633, MSC_net_634, 
        MSC_net_635, MSC_net_636, MSC_net_637, MSC_net_638, 
        MSC_net_639, MSC_net_640, MSC_net_641, MSC_net_642, 
        MSC_net_643, MSC_net_644, MSC_net_645, MSC_net_646, 
        MSC_net_647, MSC_net_648, MSC_net_649, MSC_net_650, 
        MSC_net_651, MSC_net_652, MSC_net_653, MSC_net_654, 
        MSC_net_655, MSC_net_656, MSC_net_657, MSC_net_658, 
        MSC_net_659, MSC_net_660;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
a21rl3gCTP0etFqu2m+ZGqFNRZ91w5lo6/I6UHWD5lhTNgste7vghwdsdRbk/K/N
dRFCugTwHrsK0P+g3ZAMt2Ey2T3cgCGipsMT+Qx6Cvhb00d4XcdExoktz/kHAgTb
OOb5O4kil6MuLb5ruLmXsAYsXvhYi5k9Cf3qffkvPd4=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=90850)
`pragma protect data_block
[encoded data, 89408 characters]
e3L1RYdqt8s3P02aOtR5PalVOCGzhayDZ2ZYu/12mt0=

`pragma protect end_protected

endmodule


module cordic_rot_be_18s_15s_0_1(
       theta_o_i_0,
       s_flux_q,
       ebeta_filtered_o,
       ealpha_filtered_o,
       reset_i,
       sys_clk_i,
       s_cordic_done,
       s_ebeta_filter_done
    );
input  [17:0] theta_o_i_0;
output [17:0] s_flux_q;
input  [17:0] ebeta_filtered_o;
input  [17:0] ealpha_filtered_o;
input  reset_i;
input  sys_clk_i;
output s_cordic_done;
input  s_ebeta_filter_done;

    wire [17:0] s_theta_i;
    wire [3:0] s_index;
    wire [0:0] s_index_5;
    wire [3:1] s_index_5_iv_i_0;
    wire [17:0] y_o_6;
    wire [17:0] s_theta_c;
    wire [17:0] s_theta_c_9;
    wire [17:0] s_xi_rot;
    wire [17:0] s_xi_rot_6;
    wire [17:0] s_yi_rot;
    wire [17:0] s_yi_rot_6;
    wire [0:0] s_state;
    wire [17:0] un1_s_sum2;
    wire [17:0] un1_s_diff2;
    wire [15:12] un1_s_diff_theta_ns;
    wire [17:17] s_theta_i_RNI9LK9_FCO;
    wire [17:17] s_theta_i_RNI9LK9_S;
    wire [17:17] s_theta_i_RNI9LK9_Y;
    wire [0:0] s_yi_rot_RNIRB121_Y;
    wire [1:1] s_yi_rot_RNIE3EQ1_Y;
    wire [2:2] s_yi_rot_RNI2SQI2_Y;
    wire [3:3] s_yi_rot_RNINL7B3_Y;
    wire [4:4] s_yi_rot_RNIDGK34_Y;
    wire [5:5] s_yi_rot_RNI4C1S4_Y;
    wire [6:6] s_yi_rot_RNIS8EK5_Y;
    wire [7:7] s_yi_rot_RNIL6RC6_Y;
    wire [8:8] s_yi_rot_RNIF5857_Y;
    wire [9:9] s_yi_rot_RNIA5LT7_Y;
    wire [10:10] s_yi_rot_RNIDR2E8_Y;
    wire [11:11] s_yi_rot_RNIHIGU8_Y;
    wire [12:12] s_yi_rot_RNIMAUE9_Y;
    wire [13:13] s_yi_rot_RNIS3CV9_Y;
    wire [14:14] s_yi_rot_RNI3UPFA_Y;
    wire [15:15] s_yi_rot_RNIBP70B_Y;
    wire [17:17] y_o_6_3_RNO_0_FCO;
    wire [17:17] y_o_6_3_RNO_0_Y;
    wire [16:16] s_yi_rot_RNIKLLGB_Y;
    wire [17:17] s_theta_i_RNI9LK9_0_FCO;
    wire [17:17] s_theta_i_RNI9LK9_0_S;
    wire [17:17] s_theta_i_RNI9LK9_0_Y;
    wire [0:0] s_xi_rot_RNIQ35P_Y;
    wire [1:1] s_xi_rot_RNICJL81_Y;
    wire [2:2] s_xi_rot_RNIV36O1_Y;
    wire [3:3] s_xi_rot_RNIJLM72_Y;
    wire [4:4] s_xi_rot_RNI887N2_Y;
    wire [5:5] s_xi_rot_RNIURN63_Y;
    wire [6:6] s_xi_rot_RNILG8M3_Y;
    wire [7:7] s_xi_rot_RNID6P54_Y;
    wire [8:8] s_xi_rot_RNI6T9L4_Y;
    wire [9:9] s_xi_rot_RNI0LQ45_Y;
    wire [10:10] s_xi_rot_RNI224G5_Y;
    wire [11:11] s_xi_rot_RNI5GDR5_Y;
    wire [12:12] s_xi_rot_RNI9VM66_Y;
    wire [13:13] s_xi_rot_RNIEF0I6_Y;
    wire [14:14] s_xi_rot_RNIK0AT6_Y;
    wire [15:15] s_xi_rot_RNIRIJ87_Y;
    wire [17:17] y_o_6_3_RNO_FCO;
    wire [17:17] y_o_6_3_RNO_Y;
    wire [16:16] s_xi_rot_RNI36TJ7_Y;
    wire [15:12] un1_s_diff_theta_bm;
    wire [15:12] un1_s_diff_theta_am;
    wire MSC_net_321, MSC_net_322, MSC_net_323, MSC_net_324, 
        MSC_net_325, MSC_net_326, MSC_net_327, MSC_net_328, 
        MSC_net_329, MSC_net_330, MSC_net_331, MSC_net_332, 
        MSC_net_333, MSC_net_334, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, MSC_net_350, MSC_net_351, MSC_net_352, 
        MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459, MSC_net_460, 
        MSC_net_461, MSC_net_462, MSC_net_463, MSC_net_464, 
        MSC_net_465, MSC_net_466, MSC_net_467, MSC_net_468, 
        MSC_net_469, MSC_net_470, MSC_net_471, MSC_net_472, 
        MSC_net_473, MSC_net_474, MSC_net_475, MSC_net_476, 
        MSC_net_477, MSC_net_478, MSC_net_479, MSC_net_480, 
        MSC_net_481, MSC_net_482, MSC_net_483, MSC_net_484, 
        MSC_net_485, MSC_net_486, MSC_net_487, MSC_net_488, 
        MSC_net_489, MSC_net_490, MSC_net_491, MSC_net_492, 
        MSC_net_493, MSC_net_494, MSC_net_495, MSC_net_496, 
        MSC_net_497, MSC_net_498, MSC_net_499, MSC_net_500, 
        MSC_net_501, MSC_net_502, MSC_net_503, MSC_net_504, 
        MSC_net_505, MSC_net_506, MSC_net_507, MSC_net_508, 
        MSC_net_509, MSC_net_510, MSC_net_511, MSC_net_512, 
        MSC_net_513, MSC_net_514, MSC_net_515, MSC_net_516, 
        MSC_net_517, MSC_net_518, MSC_net_519, MSC_net_520, 
        MSC_net_521, MSC_net_522, MSC_net_523, MSC_net_524, 
        MSC_net_525, MSC_net_526, MSC_net_527, MSC_net_528, 
        MSC_net_529, MSC_net_530, MSC_net_531, MSC_net_532, 
        MSC_net_533, MSC_net_534, MSC_net_535, MSC_net_536, 
        MSC_net_537, MSC_net_538, MSC_net_539, MSC_net_540, 
        MSC_net_541, MSC_net_542, MSC_net_543, MSC_net_544, 
        MSC_net_545, MSC_net_546, MSC_net_547, MSC_net_548, 
        MSC_net_549, MSC_net_550, MSC_net_551, MSC_net_552, 
        MSC_net_553, MSC_net_554, MSC_net_555, MSC_net_556, 
        MSC_net_557, MSC_net_558, MSC_net_559, MSC_net_560, 
        MSC_net_561, MSC_net_562, MSC_net_563, MSC_net_564, 
        MSC_net_565, MSC_net_566, MSC_net_567, MSC_net_568, 
        MSC_net_569, MSC_net_570, MSC_net_571, MSC_net_572, 
        MSC_net_573, MSC_net_574, MSC_net_575, MSC_net_576, 
        MSC_net_577, MSC_net_578, MSC_net_579, MSC_net_580, 
        MSC_net_581, MSC_net_582, MSC_net_583, MSC_net_584, 
        MSC_net_585, MSC_net_586, MSC_net_587, MSC_net_588, 
        MSC_net_589, MSC_net_590, MSC_net_591, MSC_net_592, 
        MSC_net_593, MSC_net_594, MSC_net_595, MSC_net_596, 
        MSC_net_597, MSC_net_598, MSC_net_599, MSC_net_600, 
        MSC_net_601, MSC_net_602, MSC_net_603, MSC_net_604, 
        MSC_net_605, MSC_net_606, MSC_net_607, MSC_net_608, 
        MSC_net_609, MSC_net_610, MSC_net_611, MSC_net_612, 
        MSC_net_613, MSC_net_614, MSC_net_615, MSC_net_616, 
        MSC_net_617, MSC_net_618, MSC_net_619, MSC_net_620, 
        MSC_net_621, MSC_net_622, MSC_net_623, MSC_net_624, 
        MSC_net_625, MSC_net_626, MSC_net_627, MSC_net_628, 
        MSC_net_629, MSC_net_630, MSC_net_631, MSC_net_632, 
        MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        MSC_net_641, MSC_net_642, MSC_net_643, MSC_net_644, 
        MSC_net_645, MSC_net_646, MSC_net_647, MSC_net_648, 
        MSC_net_649, MSC_net_650, MSC_net_651, MSC_net_652, 
        MSC_net_653, MSC_net_654, MSC_net_655, MSC_net_656, 
        MSC_net_657, MSC_net_658, MSC_net_659, MSC_net_660, 
        MSC_net_661, MSC_net_662, MSC_net_663, MSC_net_664, 
        MSC_net_665, MSC_net_666, MSC_net_667, MSC_net_668, 
        MSC_net_669, MSC_net_670, MSC_net_671, MSC_net_672, 
        MSC_net_673, MSC_net_674, MSC_net_675, MSC_net_676, 
        MSC_net_677, MSC_net_678, MSC_net_679, MSC_net_680, 
        MSC_net_681, MSC_net_682, MSC_net_683, MSC_net_684, 
        MSC_net_685, MSC_net_686, MSC_net_687, MSC_net_688, 
        MSC_net_689, MSC_net_690, MSC_net_691, MSC_net_692, 
        MSC_net_693, MSC_net_694, MSC_net_695, MSC_net_696, 
        MSC_net_697, MSC_net_698, MSC_net_699, MSC_net_700, 
        MSC_net_701, MSC_net_702, MSC_net_703, MSC_net_704, 
        MSC_net_705, MSC_net_706, MSC_net_707, MSC_net_708, 
        MSC_net_709, MSC_net_710, MSC_net_711, MSC_net_712, 
        MSC_net_713, MSC_net_714, MSC_net_715, MSC_net_716, 
        MSC_net_717, MSC_net_718, MSC_net_719, MSC_net_720, 
        MSC_net_721, MSC_net_722, MSC_net_723, MSC_net_724, 
        MSC_net_725, MSC_net_726, MSC_net_727, MSC_net_728, 
        MSC_net_729, MSC_net_730, MSC_net_731, MSC_net_732, 
        MSC_net_733, MSC_net_734, MSC_net_735, MSC_net_736, 
        MSC_net_737, MSC_net_738, MSC_net_739, MSC_net_740, 
        MSC_net_741, MSC_net_742, MSC_net_743, MSC_net_744, 
        MSC_net_745, MSC_net_746, MSC_net_747, MSC_net_748, 
        MSC_net_749, MSC_net_750, MSC_net_751, MSC_net_752, 
        MSC_net_753, MSC_net_754, MSC_net_755, MSC_net_756, 
        MSC_net_757, MSC_net_758, MSC_net_759, MSC_net_760, 
        MSC_net_761, MSC_net_762, MSC_net_763, MSC_net_764, 
        MSC_net_765, MSC_net_766, MSC_net_767;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
hfS0jKwQYvF9s4iJiP3u23gI5CX8zmzx0yyz6t9dI6iWuv1byhL2EDYVIuCcfnYY
c88Nid1lEB48STNFmjPJtqRgEGArKJC0rWEHLSHMjOuiq2QnuvDzH8kihkgXgR7v
4isrKHGuRbjqMMfRY7BceOHB8m87h486x6k401MlLXs=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=112970)
`pragma protect data_block
[encoded data, 111232 characters]

`pragma protect end_protected

endmodule


module mas_pi_be_44s_18s_2s(
       s_state,
       s_product,
       s_flux_q,
       s_mult1_input_6,
       s_add_cin_5,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       s_cordic_done,
       s_pout_0_sqmuxa,
       N_94
    );
input  [2:0] s_state;
output [43:0] s_product;
input  [17:0] s_flux_q;
input  [17:0] s_mult1_input_6;
input  [43:0] s_add_cin_5;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
input  s_cordic_done;
output s_pout_0_sqmuxa;
output N_94;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire MSC_net_179, MSC_net_180, MSC_net_181, MSC_net_182;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
mkl5gRHSRfN03h0ifcA96dpgaaUzufg0Pj0kFAsPMwCmvTvab1cIq4yur/xhckot
z0HIF3PBKo5VjnlkJUyz04cVuuD1OBpRCFQTGkPbvMW3KWJAsBmw9HQvGDLoTuyP
5t67l5uIZcvrZcQjlElum9VEcqT9W9Uw9rG0+RHa1gw=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=9035)
`pragma protect data_block
[encoded data, 8896 characters]

`pragma protect end_protected

endmodule


module pi_controller_be_18s_44s_2s_10s_16s_0_1_2_3_4(
       s_omega_pi_acc_in,
       s_angle_pi_acc_out,
       s_pll_pi_out,
       angle_pi_ki_i,
       angle_pi_kp_i,
       s_flux_q,
       reset_i,
       sys_clk_i,
       s_pll_pi_done,
       angle_pi_en_i,
       s_cordic_done
    );
input  [43:0] s_omega_pi_acc_in;
output [43:0] s_angle_pi_acc_out;
output [17:0] s_pll_pi_out;
input  [17:0] angle_pi_ki_i;
input  [17:0] angle_pi_kp_i;
input  [17:0] s_flux_q;
input  reset_i;
input  sys_clk_i;
output s_pll_pi_done;
input  angle_pi_en_i;
input  s_cordic_done;

    wire [43:0] s_acc_in;
    wire [43:0] s_inew;
    wire [43:0] s_product;
    wire [43:10] s_pout;
    wire [17:0] s_i_init_ds;
    wire [4:0] s_state;
    wire [43:0] acc_out_o_5;
    wire [16:0] output_y_o_5_iv_i_0;
    wire [34:1] s_piout;
    wire [16:16] s_inew_RNIA0H21_S;
    wire [16:16] s_inew_RNIA0H21_Y;
    wire [17:17] s_inew_RNIM2252_Y;
    wire [18:18] s_inew_RNI47J73_Y;
    wire [19:19] s_inew_RNIKD4A4_Y;
    wire [20:20] s_inew_RNITDMC5_Y;
    wire [21:21] s_inew_RNI8G8F6_Y;
    wire [22:22] s_inew_RNILKQH7_Y;
    wire [23:23] s_inew_RNI4RCK8_Y;
    wire [24:24] s_inew_RNIL3VM9_Y;
    wire [25:25] s_inew_RNI8EHPA_Y;
    wire [26:26] s_inew_RNIKI4SB_Y;
    wire [27:27] s_inew_RNI2PNUC_Y;
    wire [28:28] s_inew_RNII1B1E_Y;
    wire [29:29] s_inew_RNI4CU3F_Y;
    wire [30:30] s_inew_RNIFGI6G_Y;
    wire [31:31] s_inew_RNISM69H_Y;
    wire [32:32] s_inew_RNIBVQBI_Y;
    wire [33:33] s_inew_RNIS9FEJ_Y;
    wire [28:28] s_pout_RNIFM3HK_Y;
    wire [29:29] s_pout_RNI45OJL_Y;
    wire [30:30] s_pout_RNIIDDMM_Y;
    wire [31:31] s_pout_RNI2O2PN_Y;
    wire [32:32] s_pout_RNIK4ORO_Y;
    wire [33:33] s_pout_RNI8JDUP_Y;
    wire [34:34] s_pout_RNILR31R_Y;
    wire [35:35] s_pout_RNI46Q3S_Y;
    wire [36:36] s_pout_RNILIG6T_Y;
    wire [37:37] s_pout_RNI8179U_Y;
    wire [38:38] s_pout_RNISGTBV_Y;
    wire [39:39] s_pout_RNIH1KE01_Y;
    wire [40:40] s_pout_RNIUABH11_Y;
    wire [41:41] s_pout_RNICL2K21_Y;
    wire [42:42] s_pout_RNIR0QM31_Y;
    wire [43:43] s_pout_RNIRP8S51_FCO;
    wire [43:43] s_pout_RNIRP8S51_Y;
    wire [43:43] s_pout_RNIBDHP41_Y;
    wire [43:0] s_add_cin_5;
    wire [42:16] s_iout;
    wire [43:43] acc_out_o_5_b_A;
    wire [17:0] s_mult1_input_6;
    wire MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, MSC_net_591, 
        MSC_net_592, MSC_net_593, MSC_net_594, MSC_net_595, 
        MSC_net_596, MSC_net_597, MSC_net_598, MSC_net_599, 
        MSC_net_600, MSC_net_601, MSC_net_602, MSC_net_603, 
        MSC_net_604, MSC_net_605, MSC_net_606, MSC_net_607, 
        MSC_net_608, MSC_net_609, MSC_net_610, MSC_net_611, 
        MSC_net_612, MSC_net_613, MSC_net_614, MSC_net_615, 
        MSC_net_616, MSC_net_617, MSC_net_618, MSC_net_619, 
        MSC_net_620, MSC_net_621, MSC_net_622, MSC_net_623, 
        MSC_net_624, MSC_net_625, MSC_net_626, MSC_net_627, 
        MSC_net_628, MSC_net_629, MSC_net_630, MSC_net_631, 
        MSC_net_632, MSC_net_633, MSC_net_634, MSC_net_635, 
        MSC_net_636, MSC_net_637, MSC_net_638, MSC_net_639, 
        MSC_net_640, MSC_net_641, MSC_net_642, MSC_net_643, 
        MSC_net_644, MSC_net_645, MSC_net_646, MSC_net_647, 
        MSC_net_648, MSC_net_649, MSC_net_650, MSC_net_651, 
        MSC_net_652, MSC_net_653, MSC_net_654, MSC_net_655, 
        MSC_net_656, MSC_net_657, MSC_net_658, MSC_net_659, 
        MSC_net_660, MSC_net_661, MSC_net_662, MSC_net_663, 
        MSC_net_664, MSC_net_665, MSC_net_666, MSC_net_667, 
        MSC_net_668, MSC_net_669, MSC_net_670, MSC_net_671, 
        MSC_net_672, MSC_net_673, MSC_net_674, MSC_net_675, 
        MSC_net_676, MSC_net_677, MSC_net_678, MSC_net_679, 
        MSC_net_680, MSC_net_681, MSC_net_682, MSC_net_683, 
        MSC_net_684, MSC_net_685, MSC_net_686, MSC_net_687, 
        MSC_net_688, MSC_net_689, MSC_net_690, MSC_net_691, 
        MSC_net_692, MSC_net_693, MSC_net_694, MSC_net_695, 
        MSC_net_696, MSC_net_697, MSC_net_698, MSC_net_699, 
        MSC_net_700, MSC_net_701, MSC_net_702, MSC_net_703, 
        MSC_net_704, MSC_net_705, MSC_net_706, MSC_net_707, 
        MSC_net_708, MSC_net_709, MSC_net_710, MSC_net_711, 
        MSC_net_712, MSC_net_713, MSC_net_714, MSC_net_715, 
        MSC_net_716, MSC_net_717, MSC_net_718, MSC_net_719, 
        MSC_net_720, MSC_net_721, MSC_net_722, MSC_net_723, 
        MSC_net_724, MSC_net_725, MSC_net_726, MSC_net_727, 
        MSC_net_728, MSC_net_729, MSC_net_730, MSC_net_731, 
        MSC_net_732, MSC_net_733, MSC_net_734, MSC_net_735, 
        MSC_net_736, MSC_net_737, MSC_net_738, MSC_net_739, 
        MSC_net_740, MSC_net_741, MSC_net_742, MSC_net_743, 
        MSC_net_744, MSC_net_745, MSC_net_746;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
mdn7d1PYJYUcPAC6pbgPArbdMQc0I9skgzCYxNL/mk3n+RMgp/nC6QbLplR3NdDV
bx/bW0pOb+bepYZREtjsxsMPGDBbx0K4KJLJoLYJcwGKwqYRJ83PXKDt0jCumSkB
9sfte7pt7rmkINOEcEXuZfU7VRmHt+0d5wVUZ1iP/1s=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=114530)
`pragma protect data_block
[encoded data, 112768 characters]

`pragma protect end_protected

endmodule


module accumulator_be_44s_34s_18s(
       speed_filtered_o,
       s_omega_filter_out_prev,
       s_omega_filter_out_scale,
       s_omega_pi_acc_in,
       s_angle_pi_acc_out,
       s_i_alpha_buf,
       i_alpha_i,
       s_i_beta_buf,
       i_beta_i,
       s_pll_theta_dly,
       theta_o,
       ealpha_filtered_o,
       s_e_alpha_filter_out_prev,
       s_ealpha_filter_out_scale,
       ebeta_filtered_o,
       s_e_beta_filter_out_prev,
       s_ebeta_filter_out_scale,
       reset_i,
       sys_clk_i,
       done_o,
       s_pll_pi_done,
       s_flux_estimator_done,
       s_pll_theta_done_o,
       s_ealpha_filter_done,
       s_ebeta_filter_done
    );
input  [17:0] speed_filtered_o;
output [33:0] s_omega_filter_out_prev;
input  [15:0] s_omega_filter_out_scale;
output [43:0] s_omega_pi_acc_in;
input  [43:0] s_angle_pi_acc_out;
output [17:0] s_i_alpha_buf;
input  [17:0] i_alpha_i;
output [17:0] s_i_beta_buf;
input  [17:0] i_beta_i;
output [17:0] s_pll_theta_dly;
input  [17:0] theta_o;
input  [17:0] ealpha_filtered_o;
output [33:0] s_e_alpha_filter_out_prev;
input  [15:0] s_ealpha_filter_out_scale;
input  [17:0] ebeta_filtered_o;
output [33:0] s_e_beta_filter_out_prev;
input  [15:0] s_ebeta_filter_out_scale;
input  reset_i;
input  sys_clk_i;
input  done_o;
input  s_pll_pi_done;
input  s_flux_estimator_done;
input  s_pll_theta_done_o;
input  s_ealpha_filter_done;
input  s_ebeta_filter_done;

    wire MSC_net_408, MSC_net_409;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
oNQNA4Tp1K3EN3N/DPVCjek1EJibNepkWpg6SguNIsDa41m7mHYj5D3Gb2oP715C
Eh3uITsxts0jSh6eEJdpdM2PuF3AR0BN0Vj01yEsybahwJaqdpcok9dXYyR+3BYS
lLsTtgqBN2ECRzfErVY3S1I1bAh0LAo3Ia8v6pBIKIY=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=67625)
`pragma protect data_block
[encoded data, 66560 characters]
GE5NlH9JLVQgWBNbEn3lPw==

`pragma protect end_protected

endmodule


module mas_pll_44s_18s_2s(
       s_state,
       s_product,
       s_pll_pi_out,
       pll_theta_factor_i,
       s_addc_input,
       s_state_i_0,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       N_71_i_0
    );
input  [0:0] s_state;
output [30:13] s_product;
input  [17:0] s_pll_pi_out;
input  [17:0] pll_theta_factor_i;
input  [30:13] s_addc_input;
input  [0:0] s_state_i_0;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
output N_71_i_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [43:0] product_o;
    wire MSC_net_168, MSC_net_169, MSC_net_170;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
i+DBN6j1GH/PFSe3xhLl03L8zykPG6k5NRbTL1zO4IJXOu7mSp4PUo03jurSfVG5
XQtKGEOcn951EuABSCjqqix1M27Tbesv5iGW25oOiNTl3lmr3zdQxmktU2SzPQvw
jjpFoS++JGe/JBWRfnqDUvwUfQC7UlzGhpRguDU6E5A=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8735)
`pragma protect data_block
[encoded data, 8576 characters]
c7NyjbcUa0lHOfzo1B5WKA==

`pragma protect end_protected

endmodule


module pll_theta_be_18s_44s_2s_13s_0_1(
       theta_o,
       theta_o_i_0,
       s_pll_theta_dly,
       s_pll_pi_out,
       pll_theta_factor_i,
       reset_i,
       sys_clk_i,
       s_pll_theta_done_o,
       s_pll_pi_done
    );
output [17:0] theta_o;
output [17:0] theta_o_i_0;
input  [17:0] s_pll_theta_dly;
input  [17:0] s_pll_pi_out;
input  [17:0] pll_theta_factor_i;
input  reset_i;
input  sys_clk_i;
output s_pll_theta_done_o;
input  s_pll_pi_done;

    wire [0:0] s_state;
    wire [0:0] s_state_i_0;
    wire [30:13] s_product;
    wire [30:13] s_addc_input;
    wire MSC_net_132, MSC_net_133, MSC_net_134, MSC_net_135, 
        MSC_net_136, MSC_net_137, MSC_net_138, MSC_net_139, 
        MSC_net_140;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
VeKIumLQS5MNltglWVZ5QKN8gCjFcDeYmECTrwIJi1hzy5DD/BB2YvozemOijxWM
JeO6c9+iL3cUpBPU07mZLAOQqJYeD/SMyjm0PpitgNVaOVUfKG5PuVUJbgdRPBKT
MXSe5a+lWDBu6qmJu7kpMnX585XX2HRaZfgIdMphpS0=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=17075)
`pragma protect data_block
[encoded data, 16768 characters]
bdVrrscsAizqDI9874b0fJ9peUPIdW0TIJe2wgR0Et0=

`pragma protect end_protected

endmodule


module filter_be_34s_18s_16s_0_1_0(
       ebeta_filtered_o,
       s_ebeta_filter_out_scale,
       s_e_beta_filter_out_prev,
       ebeta_o,
       ebeta_filter_factor_i,
       reset_i,
       sys_clk_i,
       s_ebeta_filter_done,
       m3_2_03_0_0,
       m3_2_03_1_0,
       m4_2_03_3_0,
       m3_2_03_2_0,
       s_ealpha_filter_done
    );
output [17:0] ebeta_filtered_o;
output [15:0] s_ebeta_filter_out_scale;
input  [33:0] s_e_beta_filter_out_prev;
input  [17:0] ebeta_o;
input  [3:0] ebeta_filter_factor_i;
input  reset_i;
input  sys_clk_i;
output s_ebeta_filter_done;
output m3_2_03_0_0;
output m3_2_03_1_0;
output m4_2_03_3_0;
output m3_2_03_2_0;
input  s_ealpha_filter_done;

    wire [32:0] s_filter_incr;
    wire [0:0] s_state_ns;
    wire [0:0] s_state;
    wire MSC_net_133, MSC_net_134, MSC_net_135, MSC_net_136, 
        MSC_net_137, MSC_net_138, MSC_net_139, MSC_net_140, 
        MSC_net_141, MSC_net_142, MSC_net_143, MSC_net_144, 
        MSC_net_145, MSC_net_146, MSC_net_147, MSC_net_148, 
        MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220, 
        MSC_net_221, MSC_net_222, MSC_net_223, MSC_net_224, 
        MSC_net_225, MSC_net_226, MSC_net_227, MSC_net_228, 
        MSC_net_229, MSC_net_230, MSC_net_231, MSC_net_232, 
        MSC_net_233, MSC_net_234, MSC_net_235, MSC_net_236, 
        MSC_net_237, MSC_net_238, MSC_net_239, MSC_net_240, 
        MSC_net_241, MSC_net_242, MSC_net_243, MSC_net_244, 
        MSC_net_245, MSC_net_246, MSC_net_247, MSC_net_248, 
        MSC_net_249, MSC_net_250, MSC_net_251, MSC_net_252, 
        MSC_net_253, MSC_net_254, MSC_net_255, MSC_net_256, 
        MSC_net_257, MSC_net_258, MSC_net_259, MSC_net_260, 
        MSC_net_261, MSC_net_262, MSC_net_263, MSC_net_264, 
        MSC_net_265, MSC_net_266, MSC_net_267, MSC_net_268, 
        MSC_net_269, MSC_net_270, MSC_net_271, MSC_net_272, 
        MSC_net_273, MSC_net_274, MSC_net_275, MSC_net_276, 
        MSC_net_277, MSC_net_278, MSC_net_279, MSC_net_280, 
        MSC_net_281, MSC_net_282, MSC_net_283, MSC_net_284, 
        MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        MSC_net_305, MSC_net_306, MSC_net_307, MSC_net_308, 
        MSC_net_309, MSC_net_310, MSC_net_311, MSC_net_312, 
        MSC_net_313, MSC_net_314, MSC_net_315, MSC_net_316, 
        MSC_net_317, MSC_net_318, MSC_net_319, MSC_net_320, 
        MSC_net_321, MSC_net_322, MSC_net_323, MSC_net_324, 
        MSC_net_325, MSC_net_326, MSC_net_327, MSC_net_328, 
        MSC_net_329, MSC_net_330, MSC_net_331, MSC_net_332, 
        MSC_net_333, MSC_net_334, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, MSC_net_350, MSC_net_351, MSC_net_352, 
        MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459, MSC_net_460, 
        MSC_net_461, MSC_net_462, MSC_net_463, MSC_net_464, 
        MSC_net_465;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
AhNAOqZ4+ocIYF9aEPIDSn/ZqKGnOOy5ktqp2vjv9tNJEURQMjE0DqMUQPBmadkk
7mlFsw2PPmsEfKuW98LyI3H4S1VHKynFk0RwDTITiUyutCmovuBdYV0WiZOTnsT/
j/UdtaHD2HKFfxm/vJR8KXVOhhgejfIKFpBX1XoBl1Q=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=72650)
`pragma protect data_block
[encoded data, 71488 characters]
br30GydJjE4KyW4JTZ6wCfccmTbQv9UV+N0S4CUtLE0=

`pragma protect end_protected

endmodule


module filter_be_34s_18s_16s_0_1(
       ealpha_filtered_o,
       s_ealpha_filter_out_scale,
       s_e_alpha_filter_out_prev,
       ealpha_o,
       ebeta_filter_factor_i,
       reset_i,
       sys_clk_i,
       s_ealpha_filter_done,
       m3_2_03_0_0,
       m3_2_03_1_1,
       m3_2_03_2_0,
       m4_2_03_3_0,
       s_flux_estimator_done
    );
output [17:0] ealpha_filtered_o;
output [15:0] s_ealpha_filter_out_scale;
input  [33:0] s_e_alpha_filter_out_prev;
input  [17:0] ealpha_o;
input  [3:0] ebeta_filter_factor_i;
input  reset_i;
input  sys_clk_i;
output s_ealpha_filter_done;
input  m3_2_03_0_0;
input  m3_2_03_1_1;
input  m3_2_03_2_0;
input  m4_2_03_3_0;
input  s_flux_estimator_done;

    wire [32:0] s_filter_incr;
    wire [0:0] s_state_ns;
    wire [0:0] s_state;
    wire MSC_net_133, MSC_net_134, MSC_net_135, MSC_net_136, 
        MSC_net_137, MSC_net_138, MSC_net_139, MSC_net_140, 
        MSC_net_141, MSC_net_142, MSC_net_143, MSC_net_144, 
        MSC_net_145, MSC_net_146, MSC_net_147, MSC_net_148, 
        MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220, 
        MSC_net_221, MSC_net_222, MSC_net_223, MSC_net_224, 
        MSC_net_225, MSC_net_226, MSC_net_227, MSC_net_228, 
        MSC_net_229, MSC_net_230, MSC_net_231, MSC_net_232, 
        MSC_net_233, MSC_net_234, MSC_net_235, MSC_net_236, 
        MSC_net_237, MSC_net_238, MSC_net_239, MSC_net_240, 
        MSC_net_241, MSC_net_242, MSC_net_243, MSC_net_244, 
        MSC_net_245, MSC_net_246, MSC_net_247, MSC_net_248, 
        MSC_net_249, MSC_net_250, MSC_net_251, MSC_net_252, 
        MSC_net_253, MSC_net_254, MSC_net_255, MSC_net_256, 
        MSC_net_257, MSC_net_258, MSC_net_259, MSC_net_260, 
        MSC_net_261, MSC_net_262, MSC_net_263, MSC_net_264, 
        MSC_net_265, MSC_net_266, MSC_net_267, MSC_net_268, 
        MSC_net_269, MSC_net_270, MSC_net_271, MSC_net_272, 
        MSC_net_273, MSC_net_274, MSC_net_275, MSC_net_276, 
        MSC_net_277, MSC_net_278, MSC_net_279, MSC_net_280, 
        MSC_net_281, MSC_net_282, MSC_net_283, MSC_net_284, 
        MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        MSC_net_305, MSC_net_306, MSC_net_307, MSC_net_308, 
        MSC_net_309, MSC_net_310, MSC_net_311, MSC_net_312, 
        MSC_net_313, MSC_net_314, MSC_net_315, MSC_net_316, 
        MSC_net_317, MSC_net_318, MSC_net_319, MSC_net_320, 
        MSC_net_321, MSC_net_322, MSC_net_323, MSC_net_324, 
        MSC_net_325, MSC_net_326, MSC_net_327, MSC_net_328, 
        MSC_net_329, MSC_net_330, MSC_net_331, MSC_net_332, 
        MSC_net_333, MSC_net_334, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, MSC_net_350, MSC_net_351, MSC_net_352, 
        MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459, MSC_net_460, 
        MSC_net_461, MSC_net_462, MSC_net_463, MSC_net_464;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
Txc1KEjziCOwFXXIhWNnNwCFeJLbuPUyvEZHVaMTY3gz3mktNrMAxi4aIjfmY49R
VNbPYLJBmQqx/p5to4+mKyGBqwsLKCjKz9mt6GJ1DtjvQsJJQUw1kuP0FTTU5UhJ
rSy2ruRSOSP63GBfMpDin3jNIt62+bbzRPGkeC5JjBY=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=71980)
`pragma protect data_block
[encoded data, 70848 characters]
9EBer+5+3bNAvYYQAKUBCg==

`pragma protect end_protected

endmodule


module filter_be_34s_18s_16s_0_1_1(
       speed_filtered_o,
       s_omega_filter_out_scale,
       s_omega_filter_out_prev,
       s_pll_pi_out,
       omega_filter_factor_i,
       reset_i,
       sys_clk_i,
       done_o,
       s_pll_pi_done
    );
output [17:0] speed_filtered_o;
output [15:0] s_omega_filter_out_scale;
input  [33:0] s_omega_filter_out_prev;
input  [17:0] s_pll_pi_out;
input  [3:0] omega_filter_factor_i;
input  reset_i;
input  sys_clk_i;
output done_o;
input  s_pll_pi_done;

    wire [32:0] s_filter_incr;
    wire [0:0] s_state_ns;
    wire [0:0] s_state;
    wire MSC_net_129, MSC_net_130, MSC_net_131, MSC_net_132, 
        MSC_net_133, MSC_net_134, MSC_net_135, MSC_net_136, 
        MSC_net_137, MSC_net_138, MSC_net_139, MSC_net_140, 
        MSC_net_141, MSC_net_142, MSC_net_143, MSC_net_144, 
        MSC_net_145, MSC_net_146, MSC_net_147, MSC_net_148, 
        MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220, 
        MSC_net_221, MSC_net_222, MSC_net_223, MSC_net_224, 
        MSC_net_225, MSC_net_226, MSC_net_227, MSC_net_228, 
        MSC_net_229, MSC_net_230, MSC_net_231, MSC_net_232, 
        MSC_net_233, MSC_net_234, MSC_net_235, MSC_net_236, 
        MSC_net_237, MSC_net_238, MSC_net_239, MSC_net_240, 
        MSC_net_241, MSC_net_242, MSC_net_243, MSC_net_244, 
        MSC_net_245, MSC_net_246, MSC_net_247, MSC_net_248, 
        MSC_net_249, MSC_net_250, MSC_net_251, MSC_net_252, 
        MSC_net_253, MSC_net_254, MSC_net_255, MSC_net_256, 
        MSC_net_257, MSC_net_258, MSC_net_259, MSC_net_260, 
        MSC_net_261, MSC_net_262, MSC_net_263, MSC_net_264, 
        MSC_net_265, MSC_net_266, MSC_net_267, MSC_net_268, 
        MSC_net_269, MSC_net_270, MSC_net_271, MSC_net_272, 
        MSC_net_273, MSC_net_274, MSC_net_275, MSC_net_276, 
        MSC_net_277, MSC_net_278, MSC_net_279, MSC_net_280, 
        MSC_net_281, MSC_net_282, MSC_net_283, MSC_net_284, 
        MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        MSC_net_305, MSC_net_306, MSC_net_307, MSC_net_308, 
        MSC_net_309, MSC_net_310, MSC_net_311, MSC_net_312, 
        MSC_net_313, MSC_net_314, MSC_net_315, MSC_net_316, 
        MSC_net_317, MSC_net_318, MSC_net_319, MSC_net_320, 
        MSC_net_321, MSC_net_322, MSC_net_323, MSC_net_324, 
        MSC_net_325, MSC_net_326, MSC_net_327, MSC_net_328, 
        MSC_net_329, MSC_net_330, MSC_net_331, MSC_net_332, 
        MSC_net_333, MSC_net_334, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, MSC_net_350, MSC_net_351, MSC_net_352, 
        MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459, MSC_net_460, 
        MSC_net_461, MSC_net_462;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
YJq4iGx1QKFfmIzEnxyF4xiRFvRKtGXRN2drWkE9jpSEf6OcyMUD+ivSKnFN2b5J
7jJyX/E+eTTAnpVce70Hl52OkSH4MD7MWazoamJpnDoSGoMDkicYr3YWNifzepIW
hLuj+5S98UJMGoCsMpxiYbG3aflF0Cv3PPLdN+zvVhQ=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=72000)
`pragma protect data_block
[encoded data, 70848 characters]
JbNQn8ZU/2TzekvhO8CGAfEQjXStJF8MmdmhKt2knRk=

`pragma protect end_protected

endmodule


module BLDC_ESTIMATOR_18s_2s_34s_44s(
       reset_i,
       sys_clk_i,
       start_i,
       angle_pi_en_i,
       v_alpha_i,
       v_beta_i,
       i_alpha_i,
       i_beta_i,
       Ls_by_Ts_pu_i,
       Rs_pu_i,
       ealpha_filter_factor_i,
       ebeta_filter_factor_i,
       pll_theta_factor_i,
       angle_pi_ki_i,
       angle_pi_kp_i,
       omega_filter_factor_i,
       done_o,
       theta_o,
       ealpha_o,
       ebeta_o,
       ealpha_filtered_o,
       ebeta_filtered_o,
       pll_pi_out_o,
       speed_filtered_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  angle_pi_en_i;
input  [17:0] v_alpha_i;
input  [17:0] v_beta_i;
input  [17:0] i_alpha_i;
input  [17:0] i_beta_i;
input  [17:0] Ls_by_Ts_pu_i;
input  [17:0] Rs_pu_i;
input  [3:0] ealpha_filter_factor_i;
input  [3:0] ebeta_filter_factor_i;
input  [17:0] pll_theta_factor_i;
input  [17:0] angle_pi_ki_i;
input  [17:0] angle_pi_kp_i;
input  [3:0] omega_filter_factor_i;
output done_o;
output [17:0] theta_o;
output [17:0] ealpha_o;
output [17:0] ebeta_o;
output [17:0] ealpha_filtered_o;
output [17:0] ebeta_filtered_o;
output [17:0] pll_pi_out_o;
output [17:0] speed_filtered_o;

    wire [17:0] s_i_alpha_buf;
    wire [17:0] s_i_beta_buf;
    wire [33:0] s_e_alpha_filter_out_prev;
    wire [15:0] s_ealpha_filter_out_scale;
    wire [33:0] s_e_beta_filter_out_prev;
    wire [15:0] s_ebeta_filter_out_scale;
    wire [17:0] s_flux_q;
    wire [43:0] s_omega_pi_acc_in;
    wire [43:0] s_angle_pi_acc_out;
    wire [17:0] s_pll_theta_dly;
    wire [33:0] s_omega_filter_out_prev;
    wire [15:0] s_omega_filter_out_scale;
    wire [17:0] theta_o_i_0;
    wire MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        \filter_be_inst.m3_2_03_0_0 , \filter_be_inst.m3_2_03_1_0 , 
        \filter_be_inst.m3_2_03_2_0 , \filter_be_inst.m4_2_03_3_0 ;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
Mr0BJcKOEDQKaToEuwuZ0IpMkKhMKHC7ENP1Xz6omJ9kzLJBR+8osAGdpjYSp7tR
6AhwXoGcHmUlgXDQTnyjosEMgJCFMNiBFMSFGJqVmjDBqos2/TyloO7cD7BmEBL+
L3KSBP9iabr+7f8aouc0o+L2PpvHcXftu9P9l17iji4=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=44115)
`pragma protect data_block
[encoded data, 43392 characters]
nH1LOsf/jNIridMGzMf00r1ShFo70dexxLRpxG31+bw=

`pragma protect end_protected

endmodule


module mas_olmng_44s_18s_2s(
       s_product,
       speed_ref_i,
       theta_factor_i,
       s_addc_input,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       s_init_iqpi,
       s_state_79_d
    );
output [30:13] s_product;
input  [17:1] speed_ref_i;
input  [17:0] theta_factor_i;
input  [30:13] s_addc_input;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
input  s_init_iqpi;
input  s_state_79_d;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [43:0] product_o;
    wire MSC_net_166, MSC_net_167, MSC_net_168;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
P81I5VZaHeJquNa2eWXEyXq3O9n5gVO6vWpKsrH6FgEaywIwauh1JesbYo6mwuH0
qF587iAEBy0Qs7Xj8I/y6R7MC/7lE00B7nsVeXvoBgkIIfjxg6MzOabO7h0nrpGe
U1HqAlf7jADuJom0dSSEMOtqetLYe8JgsieszBoI6cQ=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8385)
`pragma protect data_block
[encoded data, 8256 characters]

`pragma protect end_protected

endmodule


module accumulator_olmng_18s(
       s_theta_buff,
       s_theta,
       reset_i,
       sys_clk_i,
       clear_buffer_i,
       s_olmng_done
    );
output [17:0] s_theta_buff;
input  [17:0] s_theta;
input  reset_i;
input  sys_clk_i;
input  clear_buffer_i;
input  s_olmng_done;

    wire [17:0] theta_scl_buff_o_3;
    wire MSC_net_58, MSC_net_59, MSC_net_60;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
MYPMlAHCe+92TxRNobGTuzKZKDP/ffu0a22Ax2S71COt8LXkQCVaNBKCrPzzotSe
1RjPH393TSWC+OFjZsJWNfHdjn0htfjq6dVkMVi0MGKseakiiLISh7rGJHwcPMDU
mDlBpqnYbSmZfgzbhhIsbJmyFQn1KTNqgv9sGQKTp+4=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=9210)
`pragma protect data_block
[encoded data, 9024 characters]
TLXoCWHz7XN9aWOeEj3+3wKlZCJUNNzJrAM7JRGpXJQ=

`pragma protect end_protected

endmodule


module OLMNG_2s_13s_44s_0_2_3(
       reset_i,
       sys_clk_i,
       start_i,
       clear_buffer_i,
       direction_config_i,
       cl_status_i,
       theta_factor_i,
       speed_ref_i,
       dv_i,
       theta_cl_i,
       iq_ref_in_i,
       done_o,
       theta_o,
       init_speedpi_o,
       init_iqpi_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  clear_buffer_i;
input  direction_config_i;
input  cl_status_i;
input  [17:0] theta_factor_i;
input  [17:0] speed_ref_i;
input  [17:0] dv_i;
input  [17:0] theta_cl_i;
input  [17:0] iq_ref_in_i;
output done_o;
output [17:0] theta_o;
output [17:0] init_speedpi_o;
output [17:0] init_iqpi_o;

    wire [30:13] s_addc_input;
    wire [17:0] s_theta_buff;
    wire [17:0] s_theta_ol;
    wire [17:1] s_init_iqpi;
    wire [30:13] \inst.s_product ;
    wire [1:0] s_state;
    wire [0:0] s_state_ns;
    wire [17:0] \THETA_SEL_PROC.s_theta_4 ;
    wire [17:1] init_speedpi_o_7;
    wire MSC_net_278, MSC_net_279, MSC_net_280, MSC_net_281, 
        MSC_net_282, MSC_net_283, MSC_net_284, MSC_net_285, 
        MSC_net_286, MSC_net_287, MSC_net_288, MSC_net_289, 
        MSC_net_290, MSC_net_291, MSC_net_292, MSC_net_293, 
        MSC_net_294, MSC_net_295, MSC_net_296, MSC_net_297, 
        MSC_net_298, MSC_net_299, MSC_net_300, MSC_net_301, 
        MSC_net_302, MSC_net_303, MSC_net_304, MSC_net_305, 
        MSC_net_306, MSC_net_307, MSC_net_308, MSC_net_309, 
        MSC_net_310, MSC_net_311, MSC_net_312, MSC_net_313, 
        MSC_net_314, MSC_net_315, MSC_net_316, MSC_net_317, 
        MSC_net_318, MSC_net_319, MSC_net_320, MSC_net_321, 
        MSC_net_322, MSC_net_323, MSC_net_324, MSC_net_325, 
        MSC_net_326, MSC_net_327, MSC_net_328, MSC_net_329, 
        MSC_net_330, MSC_net_331, MSC_net_332, MSC_net_333, 
        MSC_net_334, MSC_net_335, MSC_net_336, MSC_net_337, 
        MSC_net_338, MSC_net_339, MSC_net_340, MSC_net_341, 
        MSC_net_342, MSC_net_343, MSC_net_344, MSC_net_345, 
        MSC_net_346, MSC_net_347, MSC_net_348, MSC_net_349, 
        MSC_net_350, MSC_net_351, MSC_net_352, MSC_net_353, 
        MSC_net_354, MSC_net_355, MSC_net_356, MSC_net_357, 
        MSC_net_358, MSC_net_359, MSC_net_360, MSC_net_361, 
        MSC_net_362, MSC_net_363, MSC_net_364, MSC_net_365, 
        MSC_net_366, MSC_net_367, MSC_net_368, MSC_net_369, 
        MSC_net_370;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
Y1rQzBbvIja67awzEcDz9xcq/C6434vZhI3ejMjsodudeS7pjntAmmHV8GtFUAsS
FooXyc94wrkL0IcC/d0smlSNS2Splct3Iovhp1QS8CL5v5N/prWbJRFR2uDdT9aa
gGqyGrkWNgQfFm9ecy/ukVnsBcpFz8r8WZk6zgGyJ5I=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=47385)
`pragma protect data_block
[encoded data, 46656 characters]

`pragma protect end_protected

endmodule


module mas_pwm_scl_44s_18s_2s_1(
       s_product,
       s_mult_in0_5,
       pwm_gain_i,
       pwm_period_i,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en
    );
output [33:16] s_product;
input  [17:0] s_mult_in0_5;
input  [17:1] pwm_gain_i;
input  [17:0] pwm_period_i;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [43:0] product_o;
    wire MSC_net_164, MSC_net_165, MSC_net_166;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
UvdS+wr6nqNqC4x8cjze1NuQgV0KfKiZ/YHy7z/nYNYkv9x2BqPM/BwUs3WeMbKA
Oknzf9B0YSWFUtEYg1ozjOpZFdPzulaijhmik4FVqqWNwJXF5AwcwpAjRL3f/PY6
4KeYaulg1dGJ8hUg7h4g+E7C5HIy+tcfb9UD6ZS9u/k=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8280)
`pragma protect data_block
[encoded data, 8128 characters]
+vRkwfVm+mhcO4lW1Mryjg==

`pragma protect end_protected

endmodule


module PWM_SCALING_2s_44s_15s_0_1_2_4_1(
       reset_i,
       sys_clk_i,
       start_i,
       va_i,
       vb_i,
       vc_i,
       pwm_period_i,
       pwm_gain_i,
       Va_o,
       Vb_o,
       Vc_o,
       done_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  [17:0] va_i;
input  [17:0] vb_i;
input  [17:0] vc_i;
input  [17:0] pwm_period_i;
input  [17:0] pwm_gain_i;
output [17:0] Va_o;
output [17:0] Vb_o;
output [17:0] Vc_o;
output done_o;

    wire [33:16] s_product;
    wire [4:0] s_state;
    wire [17:0] \MUL_INP_GEN_PROC.s_mult_in0_5 ;
    wire [1:1] s_state_ns;
    wire [17:0] \MUL_INP_GEN_PROC.s_mult_in0_5_iv_0 ;
    wire MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, MSC_net_213, MSC_net_214, MSC_net_215, 
        MSC_net_216, MSC_net_217, MSC_net_218, MSC_net_219, 
        MSC_net_220, MSC_net_221, MSC_net_222, MSC_net_223, 
        MSC_net_224;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
iVZ4UbonkqP7WFRNmXZ1Wcu/gWJHQXLpro/0pc73oXawQdTzQWiGksv4d0JR7qgA
jSxb/VapKETnfFopwiXdN+RZdqsXYWTSeVzRsiVWEHo2yrqtzXuEE9ncQ9VHzvdD
OXtTZI3qNRaDqduN75FroQqVaTa/4O9mDIl/BcJm1wY=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=30965)
`pragma protect data_block
[encoded data, 30464 characters]
mJAUKgNqU2zFQRSoE4DHNQ==

`pragma protect end_protected

endmodule


module mas_pi_spi_44s_18s_2s_1(
       s_state,
       s_product,
       s_error,
       s_mult1_input_6,
       s_add_cin_5,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       N_77_i_0,
       s_error_axb_0_i_0,
       un1_s_acc_in_0_sqmuxa_0
    );
input  [2:2] s_state;
output [43:0] s_product;
input  [17:1] s_error;
input  [17:0] s_mult1_input_6;
input  [43:0] s_add_cin_5;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
output N_77_i_0;
input  s_error_axb_0_i_0;
input  un1_s_acc_in_0_sqmuxa_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire MSC_net_176, MSC_net_177, MSC_net_178;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
EQGSPFf+TMMmC88KUyoY/9Z9TzVDwf6DxtCpkaUxqNQI1zst4Y9INimFaXkgvBt8
p9yQw8uR60Tslkbea58l6xnG0TCpBTJqIb+ERRMkKfhQ7qxwKTJkLArZlsbTqQ/s
YEjiHlA5TAjjaFGnCLaPCHhyc19lI9G7j+i8e/iQW3Q=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8690)
`pragma protect data_block
[encoded data, 8512 characters]
lvOAIipCdXxLXdk2XHyC0PvxzNLC+at1U66PT8pghaw=

`pragma protect end_protected

endmodule


module pi_controller_spi_18s_44s_2s_10s_16s_0_1_2_4_1(
       s_acc_in_0,
       s_acc_out,
       s_output_y,
       id_pi_act_input_i,
       s_act_input,
       s_pi_sel_i_0,
       s_pi_sel_fast,
       iq_init_i_0,
       iq_init_i_10,
       speed_init_i_0,
       speed_init_i_10,
       iq_pi_ref_input_i,
       speed_pi_ref_input_i,
       speed_pi_kp_i,
       iq_pi_kp_i,
       speed_pi_ki_i,
       iq_pi_ki_i,
       reset_i,
       sys_clk_i,
       s_done,
       s_en,
       N_1498,
       N_1499,
       N_1500,
       N_1501,
       N_1502,
       N_1503,
       N_1504,
       N_1505,
       N_1506,
       N_1507,
       N_1508,
       N_1509,
       N_1510,
       N_1511,
       N_1512,
       N_1513,
       s_pi_sel_1_rep1,
       N_1533,
       N_1514,
       N_1480,
       N_1481,
       N_1482,
       N_1483,
       N_1484,
       N_1485,
       N_1486,
       N_1487,
       N_1488,
       N_1489,
       N_1490,
       N_1491,
       N_1492,
       N_1493,
       N_1494,
       N_1495,
       N_1497,
       N_1496,
       s_pi_sel_0_rep2,
       s_pi_sel_0_rep1,
       output_y_o6_0,
       s_start
    );
input  [43:0] s_acc_in_0;
output [43:0] s_acc_out;
output [17:0] s_output_y;
input  [17:17] id_pi_act_input_i;
input  [16:0] s_act_input;
input  [1:1] s_pi_sel_i_0;
input  [1:0] s_pi_sel_fast;
input  iq_init_i_0;
input  iq_init_i_10;
input  speed_init_i_0;
input  speed_init_i_10;
input  [17:17] iq_pi_ref_input_i;
input  [17:17] speed_pi_ref_input_i;
input  [17:0] speed_pi_kp_i;
input  [17:0] iq_pi_kp_i;
input  [17:0] speed_pi_ki_i;
input  [17:0] iq_pi_ki_i;
input  reset_i;
input  sys_clk_i;
output s_done;
input  s_en;
input  N_1498;
input  N_1499;
input  N_1500;
input  N_1501;
input  N_1502;
input  N_1503;
input  N_1504;
input  N_1505;
input  N_1506;
input  N_1507;
input  N_1508;
input  N_1509;
input  N_1510;
input  N_1511;
input  N_1512;
input  N_1513;
input  s_pi_sel_1_rep1;
input  N_1533;
input  N_1514;
input  N_1480;
input  N_1481;
input  N_1482;
input  N_1483;
input  N_1484;
input  N_1485;
input  N_1486;
input  N_1487;
input  N_1488;
input  N_1489;
input  N_1490;
input  N_1491;
input  N_1492;
input  N_1493;
input  N_1494;
input  N_1495;
input  N_1497;
input  N_1496;
input  s_pi_sel_0_rep2;
input  s_pi_sel_0_rep1;
input  output_y_o6_0;
input  s_start;

    wire [0:0] un1_s_diff_v_RNIME7V_Y;
    wire [16:0] s_piout_i;
    wire [34:1] s_piout;
    wire [43:0] s_acc_in;
    wire [43:0] s_inew;
    wire [43:0] s_product;
    wire [43:10] s_pout;
    wire [17:0] s_i_init_ds;
    wire [4:0] s_state;
    wire [43:0] acc_out_o_5;
    wire [17:1] output_y_o_5;
    wire [1:1] s_state_ns;
    wire [0:0] un1_s_diff_v_RNIME7V_S;
    wire [17:0] s_init;
    wire [1:1] un1_s_diff_v_RNIF0FU1_Y;
    wire [2:2] un1_s_diff_v_RNIBLMT2_Y;
    wire [3:3] un1_s_diff_v_RNIADUS3_Y;
    wire [4:4] un1_s_diff_v_RNI307S4_Y;
    wire [5:5] un1_s_diff_v_RNIVLFR5_Y;
    wire [6:6] un1_s_diff_v_RNIUEOQ6_Y;
    wire [7:7] un1_s_diff_v_RNI0B1Q7_Y;
    wire [8:8] un1_s_diff_v_RNI5AAP8_Y;
    wire [9:9] un1_s_diff_v_RNIDCJO9_Y;
    wire [10:10] un1_s_diff_v_RNIM27KA_Y;
    wire [11:11] un1_s_diff_v_RNI2SQFB_Y;
    wire [12:12] un1_s_diff_v_RNIHOEBC_Y;
    wire [13:13] un1_s_diff_v_RNI3O27D_Y;
    wire [14:14] un1_s_diff_v_RNIFIN2E_Y;
    wire [15:15] un1_s_diff_v_RNIUFCUE_Y;
    wire [16:16] un1_s_diff_v_RNIGG1QF_Y;
    wire [27:27] s_pout_RNI5KMLG_Y;
    wire [28:28] s_pout_RNISPBHH_Y;
    wire [29:29] s_pout_RNIL11DI_Y;
    wire [30:30] s_pout_RNI73N8J_Y;
    wire [31:31] s_pout_RNIR6D4K_Y;
    wire [32:32] s_pout_RNIHC30L_Y;
    wire [33:33] s_pout_RNI9KPRL_Y;
    wire [34:34] s_pout_RNIQLGNM_Y;
    wire [35:35] s_pout_RNIDP7JN_Y;
    wire [36:36] s_pout_RNI2VUEO_Y;
    wire [37:37] s_pout_RNIP6MAP_Y;
    wire [38:38] s_pout_RNIHFD6Q_Y;
    wire [39:39] s_pout_RNIAP42R_Y;
    wire [40:40] s_pout_RNIRRSTR_Y;
    wire [41:41] s_pout_RNIDVKPS_Y;
    wire [42:42] s_pout_RNI04DLT_Y;
    wire [43:43] s_pout_RNI8FTCV_FCO;
    wire [43:43] s_pout_RNI8FTCV_Y;
    wire [43:43] s_pout_RNIK95HU_Y;
    wire [17:1] s_error;
    wire [0:0] s_piout_0;
    wire [17:0] s_mult1_input_6_1_1;
    wire [17:0] s_mult1_input_6;
    wire [43:0] s_add_cin_5;
    wire [42:0] s_iout;
    wire [43:43] acc_out_o_5_b_A;
    wire MSC_net_749, MSC_net_750, MSC_net_751, MSC_net_752, 
        MSC_net_753, MSC_net_754, MSC_net_755, MSC_net_756, 
        MSC_net_757, MSC_net_758, MSC_net_759, MSC_net_760, 
        MSC_net_761, MSC_net_762, MSC_net_763, MSC_net_764, 
        MSC_net_765, MSC_net_766, MSC_net_767, MSC_net_768, 
        MSC_net_769, MSC_net_770, MSC_net_771, MSC_net_772, 
        MSC_net_773, MSC_net_774, MSC_net_775, MSC_net_776, 
        MSC_net_777, MSC_net_778, MSC_net_779, MSC_net_780, 
        MSC_net_781, MSC_net_782, MSC_net_783, MSC_net_784, 
        MSC_net_785, MSC_net_786, MSC_net_787, MSC_net_788, 
        MSC_net_789, MSC_net_790, MSC_net_791, MSC_net_792, 
        MSC_net_793, MSC_net_794, MSC_net_795, MSC_net_796, 
        MSC_net_797, MSC_net_798, MSC_net_799, MSC_net_800, 
        MSC_net_801, MSC_net_802, MSC_net_803, MSC_net_804, 
        MSC_net_805, MSC_net_806, MSC_net_807, MSC_net_808, 
        MSC_net_809, MSC_net_810, MSC_net_811, MSC_net_812, 
        MSC_net_813, MSC_net_814, MSC_net_815, MSC_net_816, 
        MSC_net_817, MSC_net_818, MSC_net_819, MSC_net_820, 
        MSC_net_821, MSC_net_822, MSC_net_823, MSC_net_824, 
        MSC_net_825, MSC_net_826, MSC_net_827, MSC_net_828, 
        MSC_net_829, MSC_net_830, MSC_net_831, MSC_net_832, 
        MSC_net_833, MSC_net_834, MSC_net_835, MSC_net_836, 
        MSC_net_837, MSC_net_838, MSC_net_839, MSC_net_840, 
        MSC_net_841, MSC_net_842, MSC_net_843, MSC_net_844, 
        MSC_net_845, MSC_net_846, MSC_net_847, MSC_net_848, 
        MSC_net_849, MSC_net_850, MSC_net_851, MSC_net_852, 
        MSC_net_853, MSC_net_854, MSC_net_855, MSC_net_856, 
        MSC_net_857, MSC_net_858, MSC_net_859, MSC_net_860, 
        MSC_net_861, MSC_net_862, MSC_net_863, MSC_net_864, 
        MSC_net_865, MSC_net_866, MSC_net_867, MSC_net_868, 
        MSC_net_869, MSC_net_870, MSC_net_871, MSC_net_872, 
        MSC_net_873, MSC_net_874, MSC_net_875, MSC_net_876, 
        MSC_net_877, MSC_net_878, MSC_net_879, MSC_net_880, 
        MSC_net_881, MSC_net_882, MSC_net_883, MSC_net_884, 
        MSC_net_885, MSC_net_886, MSC_net_887, MSC_net_888, 
        MSC_net_889, MSC_net_890, MSC_net_891, MSC_net_892, 
        MSC_net_893, MSC_net_894, MSC_net_895, MSC_net_896, 
        MSC_net_897, MSC_net_898, MSC_net_899, MSC_net_900, 
        MSC_net_901, MSC_net_902, MSC_net_903, MSC_net_904, 
        MSC_net_905, MSC_net_906, MSC_net_907, MSC_net_908, 
        MSC_net_909, MSC_net_910, MSC_net_911, MSC_net_912, 
        MSC_net_913, MSC_net_914, MSC_net_915, MSC_net_916, 
        MSC_net_917, MSC_net_918, MSC_net_919, MSC_net_920, 
        MSC_net_921, MSC_net_922, MSC_net_923, MSC_net_924, 
        MSC_net_925, MSC_net_926, MSC_net_927, MSC_net_928, 
        MSC_net_929, MSC_net_930, MSC_net_931, MSC_net_932, 
        MSC_net_933, MSC_net_934, MSC_net_935, MSC_net_936, 
        MSC_net_937, MSC_net_938, MSC_net_939, MSC_net_940, 
        MSC_net_941, MSC_net_942, MSC_net_943, MSC_net_944, 
        MSC_net_945, MSC_net_946, MSC_net_947, MSC_net_948, 
        MSC_net_949, MSC_net_950, MSC_net_951, MSC_net_952, 
        MSC_net_953, MSC_net_954, MSC_net_955, MSC_net_956, 
        MSC_net_957, MSC_net_958, MSC_net_959, MSC_net_960, 
        MSC_net_961, MSC_net_962, MSC_net_963, MSC_net_964, 
        MSC_net_965, MSC_net_966, MSC_net_967, MSC_net_968, 
        MSC_net_969, MSC_net_970, MSC_net_971, MSC_net_972, 
        MSC_net_973, MSC_net_974, MSC_net_975, MSC_net_976, 
        MSC_net_977, MSC_net_978, MSC_net_979, MSC_net_980, 
        MSC_net_981, MSC_net_982, MSC_net_983, MSC_net_984, 
        MSC_net_985, MSC_net_986, MSC_net_987, MSC_net_988, 
        MSC_net_989, MSC_net_990, MSC_net_991, MSC_net_992, 
        MSC_net_993, MSC_net_994, MSC_net_995, MSC_net_996, 
        MSC_net_997, MSC_net_998, MSC_net_999, MSC_net_1000, 
        MSC_net_1001, MSC_net_1002, MSC_net_1003, MSC_net_1004, 
        MSC_net_1005, MSC_net_1006, MSC_net_1007, MSC_net_1008, 
        MSC_net_1009, MSC_net_1010, MSC_net_1011, MSC_net_1012, 
        MSC_net_1013, MSC_net_1014, MSC_net_1015, MSC_net_1016, 
        MSC_net_1017, MSC_net_1018, MSC_net_1019, MSC_net_1020, 
        MSC_net_1021, MSC_net_1022, MSC_net_1023, MSC_net_1024, 
        MSC_net_1025, MSC_net_1026, MSC_net_1027, MSC_net_1028, 
        MSC_net_1029, MSC_net_1030, MSC_net_1031, MSC_net_1032, 
        MSC_net_1033, MSC_net_1034, MSC_net_1035, MSC_net_1036, 
        MSC_net_1037, MSC_net_1038, MSC_net_1039, MSC_net_1040, 
        MSC_net_1041, MSC_net_1042, MSC_net_1043, MSC_net_1044, 
        MSC_net_1045, MSC_net_1046, MSC_net_1047, MSC_net_1048, 
        MSC_net_1049, MSC_net_1050, MSC_net_1051, MSC_net_1052, 
        MSC_net_1053, MSC_net_1054, MSC_net_1055, MSC_net_1056, 
        MSC_net_1057, MSC_net_1058, MSC_net_1059, MSC_net_1060, 
        MSC_net_1061, MSC_net_1062, MSC_net_1063, MSC_net_1064, 
        MSC_net_1065, MSC_net_1066, MSC_net_1067, MSC_net_1068, 
        MSC_net_1069, MSC_net_1070, MSC_net_1071, MSC_net_1072, 
        MSC_net_1073, MSC_net_1074, MSC_net_1075, MSC_net_1076, 
        MSC_net_1077, MSC_net_1078, MSC_net_1079, MSC_net_1080, 
        MSC_net_1081, MSC_net_1082, MSC_net_1083, MSC_net_1084, 
        MSC_net_1085, MSC_net_1086, MSC_net_1087, MSC_net_1088, 
        MSC_net_1089, MSC_net_1090, MSC_net_1091, MSC_net_1092, 
        MSC_net_1093, MSC_net_1094, MSC_net_1095, MSC_net_1096, 
        MSC_net_1097, MSC_net_1098, MSC_net_1099, MSC_net_1100, 
        MSC_net_1101, MSC_net_1102, MSC_net_1103, MSC_net_1104, 
        MSC_net_1105, MSC_net_1106, MSC_net_1107, MSC_net_1108, 
        MSC_net_1109, MSC_net_1110, MSC_net_1111, MSC_net_1112, 
        MSC_net_1113, MSC_net_1114, MSC_net_1115, MSC_net_1116, 
        MSC_net_1117, MSC_net_1118, MSC_net_1119, MSC_net_1120, 
        MSC_net_1121, MSC_net_1122, MSC_net_1123;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
RFma80J/RHDiE6MeJVtstYZIh9LVys5xa/fwVlMI8e5rW5tJkWQkseKWc1Xan4NW
k9YPQc6Kx7R5AKee732s4GOP5A0kSt3DQSrKt6k4lkJuuhSxhRjJ4gJkpeJk+p/R
g5rQ8dorGAX5sD+bjAKWmAjyLgC92VKusGdnNYpjzmk=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=150890)
`pragma protect data_block
[encoded data, 148544 characters]
chL1Gy4bbv57qIz4jnCcmg==

`pragma protect end_protected

endmodule


module pi_scheduler_spi_18s_44s_1(
       s_pi_sel_i_0,
       speed_pi_output_o,
       iq_pi_output_o,
       id_pi_output_o,
       s_pi_sel_fast,
       s_output_y,
       s_acc_out,
       speed_init_i,
       iq_init_i,
       iq_pi_ref_input_i,
       speed_pi_ref_input_i,
       iq_pi_act_input_i,
       speed_pi_act_input_i,
       s_acc_in,
       id_pi_act_input_i,
       s_act_input,
       reset_i,
       sys_clk_i,
       id_pi_done_o,
       s_done,
       iq_pi_done_o,
       s_start,
       s_pi_sel_1_rep1,
       s_pi_sel_0_rep1,
       s_pi_sel_0_rep2,
       speed_en_i,
       idq_en_i,
       s_en,
       clear_buffer_i,
       speed_pi_start_i,
       iq_pi_start_i,
       output_y_o6_0,
       N_1480,
       N_1481,
       N_1482,
       N_1483,
       N_1484,
       N_1485,
       N_1486,
       N_1487,
       N_1488,
       N_1489,
       N_1490,
       N_1491,
       N_1492,
       N_1493,
       N_1494,
       N_1495,
       N_1496,
       N_1497,
       N_1498,
       N_1499,
       N_1500,
       N_1501,
       N_1502,
       N_1503,
       N_1504,
       N_1505,
       N_1506,
       N_1507,
       N_1508,
       N_1509,
       N_1510,
       N_1511,
       N_1512,
       N_1513,
       N_1514,
       N_1533,
       id_pi_start_i
    );
output [1:1] s_pi_sel_i_0;
output [17:0] speed_pi_output_o;
output [17:0] iq_pi_output_o;
output [17:0] id_pi_output_o;
output [1:0] s_pi_sel_fast;
input  [17:0] s_output_y;
input  [43:0] s_acc_out;
input  [17:0] speed_init_i;
input  [17:0] iq_init_i;
input  [16:0] iq_pi_ref_input_i;
input  [16:0] speed_pi_ref_input_i;
input  [17:0] iq_pi_act_input_i;
input  [17:0] speed_pi_act_input_i;
output [43:0] s_acc_in;
input  [16:0] id_pi_act_input_i;
output [16:0] s_act_input;
input  reset_i;
input  sys_clk_i;
output id_pi_done_o;
input  s_done;
output iq_pi_done_o;
output s_start;
output s_pi_sel_1_rep1;
output s_pi_sel_0_rep1;
output s_pi_sel_0_rep2;
input  speed_en_i;
input  idq_en_i;
output s_en;
input  clear_buffer_i;
input  speed_pi_start_i;
input  iq_pi_start_i;
output output_y_o6_0;
output N_1480;
output N_1481;
output N_1482;
output N_1483;
output N_1484;
output N_1485;
output N_1486;
output N_1487;
output N_1488;
output N_1489;
output N_1490;
output N_1491;
output N_1492;
output N_1493;
output N_1494;
output N_1495;
output N_1496;
output N_1497;
output N_1498;
output N_1499;
output N_1500;
output N_1501;
output N_1502;
output N_1503;
output N_1504;
output N_1505;
output N_1506;
output N_1507;
output N_1508;
output N_1509;
output N_1510;
output N_1511;
output N_1512;
output N_1513;
output N_1514;
output N_1533;
input  id_pi_start_i;

    wire [43:0] s_speed_pi_acc_in;
    wire [43:0] s_speed_pi_acc_in_4;
    wire [1:0] s_pi_sel;
    wire [1:0] s_pi_sel_dly;
    wire [43:0] s_iq_acc_in;
    wire [43:0] s_id_acc_in;
    wire [17:0] speed_pi_output_y_o_5;
    wire MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        MSC_net_558, MSC_net_559, MSC_net_560, MSC_net_561, 
        MSC_net_562, MSC_net_563, MSC_net_564, MSC_net_565, 
        MSC_net_566, MSC_net_567, MSC_net_568, MSC_net_569, 
        MSC_net_570, MSC_net_571, MSC_net_572, MSC_net_573, 
        MSC_net_574, MSC_net_575, MSC_net_576, MSC_net_577, 
        MSC_net_578, MSC_net_579, MSC_net_580, MSC_net_581, 
        MSC_net_582, MSC_net_583, MSC_net_584, MSC_net_585, 
        MSC_net_586, MSC_net_587, MSC_net_588, MSC_net_589, 
        MSC_net_590, MSC_net_591, MSC_net_592, MSC_net_593, 
        MSC_net_594, MSC_net_595, MSC_net_596, MSC_net_597, 
        MSC_net_598, MSC_net_599, MSC_net_600, MSC_net_601, 
        MSC_net_602, MSC_net_603, MSC_net_604, MSC_net_605, 
        MSC_net_606, MSC_net_607, MSC_net_608, MSC_net_609, 
        MSC_net_610, MSC_net_611, MSC_net_612, MSC_net_613, 
        MSC_net_614, MSC_net_615, MSC_net_616, MSC_net_617, 
        MSC_net_618, MSC_net_619, MSC_net_620, MSC_net_621, 
        MSC_net_622, MSC_net_623, MSC_net_624, MSC_net_625, 
        MSC_net_626, MSC_net_627, MSC_net_628, MSC_net_629, 
        MSC_net_630, MSC_net_631, MSC_net_632, MSC_net_633, 
        MSC_net_634;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
FAGo+MkFSR0TMbYpEB8w1HdS8b89FWr0Asn5ZBO6wPgwIipoeRZahArnx8mFX5AU
BD+FD9hBZ+CdhuCxaAoL8rc68nTSK7X+WqmeTuPhdslgVJupTCUxzN4JqHPH64Wx
9H4RECjrMdWSyw+5SmTZG8ShkrQVj6jJC3nK3ZwZE4E=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=110435)
`pragma protect data_block
[encoded data, 108736 characters]

`pragma protect end_protected

endmodule


module SPEED_ID_IQ_PI_2s_44s_1(
       reset_i,
       sys_clk_i,
       clear_buffer_i,
       speed_en_i,
       idq_en_i,
       speed_pi_start_i,
       id_pi_start_i,
       iq_pi_start_i,
       speed_init_i,
       id_init_i,
       iq_init_i,
       speed_pi_ref_input_i,
       speed_pi_act_input_i,
       speed_pi_kp_i,
       speed_pi_ki_i,
       speed_pi_ymax_i,
       speed_pi_ymin_i,
       id_pi_ref_input_i,
       id_pi_act_input_i,
       id_pi_kp_i,
       id_pi_ki_i,
       idq_pi_ymax_i,
       idq_pi_ymin_i,
       iq_pi_ref_input_i,
       iq_pi_act_input_i,
       iq_pi_kp_i,
       iq_pi_ki_i,
       speed_pi_done_o,
       id_pi_done_o,
       iq_pi_done_o,
       speed_pi_output_o,
       id_pi_output_o,
       iq_pi_output_o
    );
input  reset_i;
input  sys_clk_i;
input  clear_buffer_i;
input  speed_en_i;
input  idq_en_i;
input  speed_pi_start_i;
input  id_pi_start_i;
input  iq_pi_start_i;
input  [17:0] speed_init_i;
input  [17:0] id_init_i;
input  [17:0] iq_init_i;
input  [17:0] speed_pi_ref_input_i;
input  [17:0] speed_pi_act_input_i;
input  [17:0] speed_pi_kp_i;
input  [17:0] speed_pi_ki_i;
input  [17:0] speed_pi_ymax_i;
input  [17:0] speed_pi_ymin_i;
input  [17:0] id_pi_ref_input_i;
input  [17:0] id_pi_act_input_i;
input  [17:0] id_pi_kp_i;
input  [17:0] id_pi_ki_i;
input  [17:0] idq_pi_ymax_i;
input  [17:0] idq_pi_ymin_i;
input  [17:0] iq_pi_ref_input_i;
input  [17:0] iq_pi_act_input_i;
input  [17:0] iq_pi_kp_i;
input  [17:0] iq_pi_ki_i;
output speed_pi_done_o;
output id_pi_done_o;
output iq_pi_done_o;
output [17:0] speed_pi_output_o;
output [17:0] id_pi_output_o;
output [17:0] iq_pi_output_o;

    wire [43:0] s_acc_out;
    wire [17:0] s_output_y;
    wire [16:0] s_act_input;
    wire [43:0] s_acc_in;
    wire [1:1] \pi_scheduler_spi_inst.s_pi_sel_i_0 ;
    wire [1:0] \pi_scheduler_spi_inst.s_pi_sel_fast ;
    wire MSC_net_533, MSC_net_534, MSC_net_535, MSC_net_536, 
        \pi_controller_spi_inst.PI_CONT_FSM_PROC.output_y_o6_0 , 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        MSC_net_558, MSC_net_559, MSC_net_560, MSC_net_561, 
        MSC_net_562, MSC_net_563, MSC_net_564, MSC_net_565, 
        MSC_net_566, MSC_net_567, MSC_net_568, MSC_net_569, 
        MSC_net_570, MSC_net_571, MSC_net_572, MSC_net_573, 
        \pi_scheduler_spi_inst.s_pi_sel_1_rep1 , 
        \pi_scheduler_spi_inst.s_pi_sel_0_rep1 , 
        \pi_scheduler_spi_inst.s_pi_sel_0_rep2 ;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
ZGo3QYYxyF6KYrYefYDkxdG+hrPv/lIlTh60UrYa6i7oDeY6Dk/wpM5sg5o6giHB
JDBZC4L5R+cvKgCkSMEoRZ/ebZEZe02XUVovS70lN1rmpIfpEeSgmbggdivaCYFu
vW0AEa/k+8f0mDlNUuAbMTIkg82Z6wYpvnF3I+OIvG0=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=19395)
`pragma protect data_block
[encoded data, 19072 characters]
36uMeGYjRqKV6btdx7ky9Q==

`pragma protect end_protected

endmodule


module cordic_scale_18s_44s_0_1_2_1(
       s_xo_scale,
       s_product_from_mas,
       s_yo_scale,
       s_mul_a_from_cordic,
       s_yo,
       s_xo,
       reset_i,
       sys_clk_i,
       s_done_o,
       s_mas_en_from_cordic,
       s_mas_done_to_cordic,
       s_cordic_done
    );
output [17:0] s_xo_scale;
input  [26:9] s_product_from_mas;
output [17:0] s_yo_scale;
output [17:0] s_mul_a_from_cordic;
input  [17:0] s_yo;
input  [17:0] s_xo;
input  reset_i;
input  sys_clk_i;
output s_done_o;
output s_mas_en_from_cordic;
input  s_mas_done_to_cordic;
input  s_cordic_done;

    wire [1:0] s_state;
    wire MSC_net_116, MSC_net_117, MSC_net_118, MSC_net_119, 
        MSC_net_120, MSC_net_121, MSC_net_122, MSC_net_123, 
        MSC_net_124, MSC_net_125, MSC_net_126, MSC_net_127, 
        MSC_net_128, MSC_net_129, MSC_net_130, MSC_net_131, 
        MSC_net_132, MSC_net_133, MSC_net_134, MSC_net_135, 
        MSC_net_136, MSC_net_137, MSC_net_138, MSC_net_139, 
        MSC_net_140, MSC_net_141, MSC_net_142, MSC_net_143, 
        MSC_net_144;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
RAbjj8HHGAvXti4Fj/hlnynPAj52uCgIX61dW4w6ekXH7VIM40a4uBQrK+omNM6l
sPN0o5xL/E4J0AxO0R/8PeDJQKGBWMtwUqrxULAzyFp/BBDwmFZ3RZWLtQeaBa4v
q9IDB1VFPIdr+zSmRpz25U57xaC0JSQU96USpj9Ln7M=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=22320)
`pragma protect data_block
[encoded data, 21952 characters]
iLC3nbZ0wwYhzE6ImROjOQ==

`pragma protect end_protected

endmodule


module cordic_rot_foc_18s_15s_0_1_1(
       s_theta,
       s_xo,
       s_yo,
       s_yi,
       s_xi,
       reset_i,
       sys_clk_i,
       s_cordic_done,
       start_ipark_i,
       start_park_i
    );
input  [17:0] s_theta;
output [17:0] s_xo;
output [17:0] s_yo;
input  [16:0] s_yi;
input  [16:0] s_xi;
input  reset_i;
input  sys_clk_i;
output s_cordic_done;
input  start_ipark_i;
input  start_park_i;

    wire [3:0] s_index;
    wire [3:1] s_index_5_iv_i_0;
    wire [17:1] s_yi_rot;
    wire [17:0] s_yi_rot_6;
    wire [0:0] s_index_5;
    wire [17:0] s_theta_i;
    wire [17:0] x_o_6;
    wire [17:0] y_o_6;
    wire [17:0] s_theta_c;
    wire [17:0] s_theta_c_9;
    wire [16:0] s_xi_rot;
    wire [17:0] s_xi_rot_6;
    wire [0:0] s_state;
    wire [0:0] s_index_fast;
    wire [0:0] s_index_5_fast;
    wire [0:0] s_index_5_rep1;
    wire [0:0] s_index_5_rep2;
    wire [17:0] un1_s_sum2;
    wire [17:0] un1_s_diff2;
    wire [15:12] un1_s_diff_theta_ns;
    wire [17:1] x_o_3;
    wire [17:17] s_theta_i_RNINO69_FCO;
    wire [17:17] s_theta_i_RNINO69_S;
    wire [17:17] s_theta_i_RNINO69_Y;
    wire [0:0] s_xi_rot_RNI4IUL_Y;
    wire [1:1] s_xi_rot_RNIICM21_Y;
    wire [2:2] s_xi_rot_RNI18EF1_Y;
    wire [3:3] s_xi_rot_RNIH46S1_Y;
    wire [4:4] s_xi_rot_RNI22U82_Y;
    wire [5:5] s_xi_rot_RNIK0ML2_Y;
    wire [6:6] s_xi_rot_RNI70E23_Y;
    wire [7:7] s_xi_rot_RNIR06F3_Y;
    wire [8:8] s_xi_rot_RNIG2UR3_Y;
    wire [9:9] s_xi_rot_RNI65M84_Y;
    wire [10:10] s_xi_rot_RNI4BEM4_Y;
    wire [11:11] s_xi_rot_RNI3I645_Y;
    wire [12:12] s_xi_rot_RNI3QUH5_Y;
    wire [13:13] s_xi_rot_RNI43NV5_Y;
    wire [14:14] s_xi_rot_RNI6DFD6_Y;
    wire [15:15] s_xi_rot_RNI9O7R6_Y;
    wire [17:17] s_xi_rot_RNIIHOM7_FCO;
    wire [17:17] s_xi_rot_RNIIHOM7_Y;
    wire [16:16] s_xi_rot_RNID4097_Y;
    wire [15:12] un1_s_diff_theta_bm;
    wire [15:12] un1_s_diff_theta_am;
    wire MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459, MSC_net_460, 
        MSC_net_461, MSC_net_462, MSC_net_463, MSC_net_464, 
        MSC_net_465, MSC_net_466, MSC_net_467, MSC_net_468, 
        MSC_net_469, MSC_net_470, MSC_net_471, MSC_net_472, 
        MSC_net_473, MSC_net_474, MSC_net_475, MSC_net_476, 
        MSC_net_477, MSC_net_478, MSC_net_479, MSC_net_480, 
        MSC_net_481, MSC_net_482, MSC_net_483, MSC_net_484, 
        MSC_net_485, MSC_net_486, MSC_net_487, MSC_net_488, 
        MSC_net_489, MSC_net_490, MSC_net_491, MSC_net_492, 
        MSC_net_493, MSC_net_494, MSC_net_495, MSC_net_496, 
        MSC_net_497, MSC_net_498, MSC_net_499, MSC_net_500, 
        MSC_net_501, MSC_net_502, MSC_net_503, MSC_net_504, 
        MSC_net_505, MSC_net_506, MSC_net_507, MSC_net_508, 
        MSC_net_509, MSC_net_510, MSC_net_511, MSC_net_512, 
        MSC_net_513, MSC_net_514, MSC_net_515, MSC_net_516, 
        MSC_net_517, MSC_net_518, MSC_net_519, MSC_net_520, 
        MSC_net_521, MSC_net_522, MSC_net_523, MSC_net_524, 
        MSC_net_525, MSC_net_526, MSC_net_527, MSC_net_528, 
        MSC_net_529, MSC_net_530, MSC_net_531, MSC_net_532, 
        MSC_net_533, MSC_net_534, MSC_net_535, MSC_net_536, 
        MSC_net_537, MSC_net_538, MSC_net_539, MSC_net_540, 
        MSC_net_541, MSC_net_542, MSC_net_543, MSC_net_544, 
        MSC_net_545, MSC_net_546, MSC_net_547, MSC_net_548, 
        MSC_net_549, MSC_net_550, MSC_net_551, MSC_net_552, 
        MSC_net_553, MSC_net_554, MSC_net_555, MSC_net_556, 
        MSC_net_557, MSC_net_558, MSC_net_559, MSC_net_560, 
        MSC_net_561, MSC_net_562, MSC_net_563, MSC_net_564, 
        MSC_net_565, MSC_net_566, MSC_net_567, MSC_net_568, 
        MSC_net_569, MSC_net_570, MSC_net_571, MSC_net_572, 
        MSC_net_573, MSC_net_574, MSC_net_575, MSC_net_576, 
        MSC_net_577, MSC_net_578, MSC_net_579, MSC_net_580, 
        MSC_net_581, MSC_net_582, MSC_net_583, MSC_net_584, 
        MSC_net_585, MSC_net_586, MSC_net_587, MSC_net_588, 
        MSC_net_589, MSC_net_590, MSC_net_591, MSC_net_592, 
        MSC_net_593, MSC_net_594, MSC_net_595, MSC_net_596, 
        MSC_net_597, MSC_net_598, MSC_net_599, MSC_net_600, 
        MSC_net_601, MSC_net_602, MSC_net_603, MSC_net_604, 
        MSC_net_605, MSC_net_606, MSC_net_607, MSC_net_608, 
        MSC_net_609, MSC_net_610, MSC_net_611, MSC_net_612, 
        MSC_net_613, MSC_net_614, MSC_net_615, MSC_net_616, 
        MSC_net_617, MSC_net_618, MSC_net_619, MSC_net_620, 
        MSC_net_621, MSC_net_622, MSC_net_623, MSC_net_624, 
        MSC_net_625, MSC_net_626, MSC_net_627, MSC_net_628, 
        MSC_net_629, MSC_net_630, MSC_net_631, MSC_net_632, 
        MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        MSC_net_641, MSC_net_642, MSC_net_643, MSC_net_644, 
        MSC_net_645, MSC_net_646, MSC_net_647, MSC_net_648, 
        MSC_net_649, MSC_net_650, MSC_net_651, MSC_net_652, 
        MSC_net_653, MSC_net_654, MSC_net_655, MSC_net_656, 
        MSC_net_657, MSC_net_658, MSC_net_659, MSC_net_660, 
        MSC_net_661, MSC_net_662, MSC_net_663, MSC_net_664, 
        MSC_net_665, MSC_net_666, MSC_net_667, MSC_net_668, 
        MSC_net_669, MSC_net_670, MSC_net_671, MSC_net_672, 
        MSC_net_673, MSC_net_674, MSC_net_675, MSC_net_676, 
        MSC_net_677, MSC_net_678, MSC_net_679, MSC_net_680, 
        MSC_net_681, MSC_net_682, MSC_net_683, MSC_net_684, 
        MSC_net_685, MSC_net_686, MSC_net_687, MSC_net_688, 
        MSC_net_689, MSC_net_690, MSC_net_691, MSC_net_692, 
        MSC_net_693, MSC_net_694, MSC_net_695, MSC_net_696, 
        MSC_net_697, MSC_net_698, MSC_net_699, MSC_net_700, 
        MSC_net_701, MSC_net_702, MSC_net_703, MSC_net_704, 
        MSC_net_705, MSC_net_706, MSC_net_707, MSC_net_708, 
        MSC_net_709, MSC_net_710, MSC_net_711, MSC_net_712, 
        MSC_net_713, MSC_net_714, MSC_net_715, MSC_net_716, 
        MSC_net_717, MSC_net_718, MSC_net_719, MSC_net_720, 
        MSC_net_721, MSC_net_722, MSC_net_723, MSC_net_724, 
        MSC_net_725, MSC_net_726, MSC_net_727, MSC_net_728, 
        MSC_net_729, MSC_net_730, MSC_net_731, MSC_net_732, 
        MSC_net_733, MSC_net_734, MSC_net_735, MSC_net_736, 
        MSC_net_737, MSC_net_738, MSC_net_739, MSC_net_740, 
        MSC_net_741, MSC_net_742, MSC_net_743, MSC_net_744, 
        MSC_net_745, MSC_net_746, MSC_net_747, MSC_net_748, 
        MSC_net_749, MSC_net_750, MSC_net_751, MSC_net_752, 
        MSC_net_753, MSC_net_754, MSC_net_755, MSC_net_756, 
        MSC_net_757, MSC_net_758, MSC_net_759, MSC_net_760, 
        MSC_net_761, MSC_net_762, MSC_net_763, MSC_net_764, 
        MSC_net_765, MSC_net_766, MSC_net_767, MSC_net_768, 
        MSC_net_769, MSC_net_770, MSC_net_771, MSC_net_772, 
        MSC_net_773, MSC_net_774, MSC_net_775, MSC_net_776, 
        MSC_net_777, MSC_net_778, MSC_net_779, MSC_net_780, 
        MSC_net_781, MSC_net_782, MSC_net_783, MSC_net_784, 
        MSC_net_785, MSC_net_786, MSC_net_787, MSC_net_788, 
        MSC_net_789, MSC_net_790, MSC_net_791, MSC_net_792, 
        MSC_net_793, MSC_net_794, MSC_net_795, MSC_net_796, 
        MSC_net_797, MSC_net_798, MSC_net_799, MSC_net_800, 
        MSC_net_801, MSC_net_802, MSC_net_803, MSC_net_804, 
        MSC_net_805, MSC_net_806, MSC_net_807, MSC_net_808, 
        MSC_net_809, MSC_net_810, MSC_net_811, MSC_net_812, 
        MSC_net_813, MSC_net_814, MSC_net_815, MSC_net_816, 
        MSC_net_817, MSC_net_818, MSC_net_819, MSC_net_820;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
gcmZJH0GziY+QkIhfCW8T02dXm66yZsnQnVoVZXqrhe8R1biF7/bE+gU/CYZnpJ7
6zrntxufBo4bssRBEuE74gw3ROkLGZxJC3P56UhjmmDeKjcOky/I+e/BGv7WFgau
j2Mt+mTupDofoVzUQdt7VujTJ9nnnqG7yV7TUZqJFRw=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=126275)
`pragma protect data_block
[encoded data, 124288 characters]
cR4AjOpLKCevCt7IlDLuBgR8sx1YLrnX3XHG/vgrZMw=

`pragma protect end_protected

endmodule


module cordic_scheduler_foc_18s_15s_44s_1(
       valpha_o,
       vbeta_o,
       id_o,
       iq_o,
       vd_i,
       ialpha_i,
       ibeta_i,
       vq_i,
       theta_i,
       s_product_from_mas,
       s_mul_a_from_cordic,
       start_park_i,
       reset_i,
       sys_clk_i,
       ipark_done_o,
       park_done_o,
       start_ipark_i,
       s_mas_en_from_cordic,
       s_mas_done_to_cordic
    );
output [17:0] valpha_o;
output [17:0] vbeta_o;
output [17:0] id_o;
output [17:0] iq_o;
input  [17:1] vd_i;
input  [17:1] ialpha_i;
input  [17:1] ibeta_i;
input  [17:1] vq_i;
input  [17:0] theta_i;
input  [26:9] s_product_from_mas;
output [17:0] s_mul_a_from_cordic;
input  start_park_i;
input  reset_i;
input  sys_clk_i;
output ipark_done_o;
output park_done_o;
input  start_ipark_i;
output s_mas_en_from_cordic;
input  s_mas_done_to_cordic;

    wire [17:0] s_xo_scale;
    wire [17:0] s_yo_scale;
    wire [16:0] s_xi;
    wire [16:0] s_yi;
    wire [17:0] s_theta;
    wire [17:0] s_xo;
    wire [17:0] s_yo;
    wire MSC_net_326, MSC_net_327, MSC_net_328, MSC_net_329, 
        MSC_net_330, MSC_net_331, MSC_net_332, MSC_net_333, 
        MSC_net_334;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
JoEkt2zSQ5Y4JvierNxnZ51XU6L0gS9JeLda+xyc7lsI4FQLup5NEcfFNy1XhjkG
IRmqeDOPZ/8QbjOst78AEng0M+3790CGsGQzwvPDFsvzcpa0eJ/ZQ3KbfIWBQcdG
TLfmdd46R3ezUPaBSCR98DztlSf0tPt/nF9qIPRaJiE=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=36120)
`pragma protect data_block
[encoded data, 35520 characters]
We+qJrcMvbsjyDmLzQR44qROcYHxv/Fr5LM6CBp7KCA=

`pragma protect end_protected

endmodule


module mas_scheduler_foc_18s_44s_1(
       s_mas_sel,
       s_mul_b_from_clarke,
       s_mul_b_from_iclarke,
       s_mul_b_to_mas_4,
       s_mul_b_to_mas_0,
       s_mul_a_from_cordic,
       s_mul_a_from_clarke,
       va_o,
       s_add_c_to_mas_33,
       s_add_c_to_mas_16,
       s_add_c_to_mas_15,
       s_add_c_to_mas_14,
       s_add_c_to_mas_13,
       s_add_c_to_mas_12,
       s_add_c_to_mas_11,
       s_add_c_to_mas_10,
       s_add_c_to_mas_9,
       s_add_c_to_mas_8,
       s_add_c_to_mas_7,
       s_add_c_to_mas_6,
       s_add_c_to_mas_5,
       s_add_c_to_mas_4,
       s_add_c_to_mas_3,
       s_add_c_to_mas_2,
       s_add_c_to_mas_1,
       s_add_c_to_mas_0,
       s_mul_a_from_iclarke,
       s_mul_a_to_mas,
       reset_i,
       sys_clk_i,
       start_iclarke_i,
       start_clarke_i,
       start_park_i,
       start_ipark_i,
       s_mas_en_from_cordic,
       s_mas_en_from_clarke,
       s_mas_done_from_mas,
       s_mas_done_to_cordic,
       s_mas_en_from_iclarke,
       s_mas_en_to_mas
    );
output [1:0] s_mas_sel;
input  [1:1] s_mul_b_from_clarke;
input  [2:2] s_mul_b_from_iclarke;
output s_mul_b_to_mas_4;
output s_mul_b_to_mas_0;
input  [17:0] s_mul_a_from_cordic;
input  [17:0] s_mul_a_from_clarke;
input  [17:0] va_o;
output s_add_c_to_mas_33;
output s_add_c_to_mas_16;
output s_add_c_to_mas_15;
output s_add_c_to_mas_14;
output s_add_c_to_mas_13;
output s_add_c_to_mas_12;
output s_add_c_to_mas_11;
output s_add_c_to_mas_10;
output s_add_c_to_mas_9;
output s_add_c_to_mas_8;
output s_add_c_to_mas_7;
output s_add_c_to_mas_6;
output s_add_c_to_mas_5;
output s_add_c_to_mas_4;
output s_add_c_to_mas_3;
output s_add_c_to_mas_2;
output s_add_c_to_mas_1;
output s_add_c_to_mas_0;
input  [17:0] s_mul_a_from_iclarke;
output [17:0] s_mul_a_to_mas;
input  reset_i;
input  sys_clk_i;
input  start_iclarke_i;
input  start_clarke_i;
input  start_park_i;
input  start_ipark_i;
input  s_mas_en_from_cordic;
input  s_mas_en_from_clarke;
input  s_mas_done_from_mas;
output s_mas_done_to_cordic;
input  s_mas_en_from_iclarke;
output s_mas_en_to_mas;

    wire MSC_net_126, MSC_net_127, MSC_net_128, MSC_net_129, 
        MSC_net_130, MSC_net_131, MSC_net_132, MSC_net_133, 
        MSC_net_134, MSC_net_135, MSC_net_136, MSC_net_137, 
        MSC_net_138, MSC_net_139, MSC_net_140, MSC_net_141, 
        MSC_net_142, MSC_net_143, MSC_net_144, MSC_net_145, 
        MSC_net_146, MSC_net_147, MSC_net_148, MSC_net_149;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
OQHNdAGezTZNhmFcT5hicJkfSVni2KQvjhmG80utYV+ULQgb7Qmr4DM2lb6+ytMt
QhYD6ERaD2OniLTmvchtnL954uP/mGq8ztn9eI9SHdaOWEQLgA1li9shHUfBnU7a
jXJAD5K8JGSnUymTdQueRu4R9vpZ9M2W6JiWLeXPVe8=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=13975)
`pragma protect data_block
[encoded data, 13760 characters]

`pragma protect end_protected

endmodule


module inverse_clarke_foc_18s_44s_1774_0_1_1(
       s_mul_a_from_iclarke,
       vbeta_i,
       s_product_from_mas,
       va_o,
       valpha_i,
       s_mul_b_from_iclarke,
       vc_o,
       vb_o,
       s_mas_sel,
       reset_i,
       sys_clk_i,
       iclarke_done_o,
       s_mas_en_from_iclarke,
       s_vca_axb_0_i_0,
       start_iclarke_i,
       s_mas_done_from_mas
    );
output [17:0] s_mul_a_from_iclarke;
input  [17:0] vbeta_i;
input  [28:11] s_product_from_mas;
output [17:0] va_o;
input  [17:0] valpha_i;
output [2:2] s_mul_b_from_iclarke;
output [17:0] vc_o;
output [17:1] vb_o;
input  [1:0] s_mas_sel;
input  reset_i;
input  sys_clk_i;
output iclarke_done_o;
output s_mas_en_from_iclarke;
output s_vca_axb_0_i_0;
input  start_iclarke_i;
input  s_mas_done_from_mas;

    wire [17:1] s_vc;
    wire [0:0] s_state;
    wire MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220, 
        MSC_net_221, MSC_net_222, MSC_net_223, MSC_net_224, 
        MSC_net_225, MSC_net_226, MSC_net_227, MSC_net_228, 
        MSC_net_229, MSC_net_230, MSC_net_231, MSC_net_232, 
        MSC_net_233, MSC_net_234;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
XDn/gwUuZ957XIfSS3HhsNGXjRzaABmGllkg996zzk8LQNiLVge5nx8GUV/Q+6f2
HKHu0UnAJv06SvTcRCGxFSotThQrSnnG14BjPb8vclvH9W7i2O6COZntTKypGFya
qLTQTIkhWwcistuav2IfMPZUp4f7HjcAns5mvKG6tVQ=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=27715)
`pragma protect data_block
[encoded data, 27264 characters]
XklVfEC9Frziez4i3B/dsw==

`pragma protect end_protected

endmodule


module clarke_foc_18s_44s_591_0_1_1(
       ialpha_o,
       ia_i,
       ibeta_o,
       s_product_from_mas,
       s_mul_a_from_clarke,
       s_mul_b_from_clarke,
       ib_i,
       s_mas_sel,
       s_mul_b_from_iclarke,
       s_mul_b_to_mas_7,
       s_mul_b_to_mas_0,
       reset_i,
       sys_clk_i,
       s_mas_en_from_clarke,
       clarke_done_o,
       start_clarke_i,
       s_mas_done_from_mas
    );
output [17:0] ialpha_o;
input  [17:0] ia_i;
output [17:0] ibeta_o;
input  [26:9] s_product_from_mas;
output [17:0] s_mul_a_from_clarke;
output [1:1] s_mul_b_from_clarke;
input  [17:0] ib_i;
input  [1:0] s_mas_sel;
input  [2:2] s_mul_b_from_iclarke;
output s_mul_b_to_mas_7;
output s_mul_b_to_mas_0;
input  reset_i;
input  sys_clk_i;
output s_mas_en_from_clarke;
output clarke_done_o;
input  start_clarke_i;
input  s_mas_done_from_mas;

    wire [0:0] s_state;
    wire MSC_net_121, MSC_net_122, MSC_net_123, MSC_net_124, 
        MSC_net_125, MSC_net_126, MSC_net_127, MSC_net_128, 
        MSC_net_129, MSC_net_130, MSC_net_131, MSC_net_132, 
        MSC_net_133, MSC_net_134, MSC_net_135, MSC_net_136, 
        MSC_net_137, MSC_net_138, MSC_net_139, MSC_net_140, 
        MSC_net_141, MSC_net_142, MSC_net_143, MSC_net_144, 
        MSC_net_145, MSC_net_146, MSC_net_147, MSC_net_148, 
        MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
bAcm5bT3cpvVEdZmZKIeDa83w1KqITElld3IW6ih3yCI02GhNCqUHv7Mk19/KPLp
zdOY6sWUBTLbd9Ot50SmTT2naaTC1IE+QK+uK+AbqNZYlbm2e9K947ucxuvF0p//
rcYCVOwdy/rnUnO9KdN4Mrtnn42yTVLPmU2gu4mqAGI=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=23140)
`pragma protect data_block
[encoded data, 22784 characters]

`pragma protect end_protected

endmodule


module mas_foc_44s_18s_2s_1(
       s_product_from_mas,
       s_mul_a_to_mas,
       s_mul_b_to_mas_0,
       s_mul_b_to_mas_9,
       s_mul_b_to_mas_5,
       s_mul_b_to_mas_7,
       s_add_c_to_mas_0,
       s_add_c_to_mas_1,
       s_add_c_to_mas_2,
       s_add_c_to_mas_3,
       s_add_c_to_mas_4,
       s_add_c_to_mas_5,
       s_add_c_to_mas_6,
       s_add_c_to_mas_7,
       s_add_c_to_mas_8,
       s_add_c_to_mas_9,
       s_add_c_to_mas_10,
       s_add_c_to_mas_11,
       s_add_c_to_mas_12,
       s_add_c_to_mas_13,
       s_add_c_to_mas_14,
       s_add_c_to_mas_15,
       s_add_c_to_mas_16,
       s_add_c_to_mas_33,
       s_mas_done_from_mas,
       reset_i,
       sys_clk_i,
       s_mas_en_to_mas
    );
output [28:9] s_product_from_mas;
input  [17:0] s_mul_a_to_mas;
input  s_mul_b_to_mas_0;
input  s_mul_b_to_mas_9;
input  s_mul_b_to_mas_5;
input  s_mul_b_to_mas_7;
input  s_add_c_to_mas_0;
input  s_add_c_to_mas_1;
input  s_add_c_to_mas_2;
input  s_add_c_to_mas_3;
input  s_add_c_to_mas_4;
input  s_add_c_to_mas_5;
input  s_add_c_to_mas_6;
input  s_add_c_to_mas_7;
input  s_add_c_to_mas_8;
input  s_add_c_to_mas_9;
input  s_add_c_to_mas_10;
input  s_add_c_to_mas_11;
input  s_add_c_to_mas_12;
input  s_add_c_to_mas_13;
input  s_add_c_to_mas_14;
input  s_add_c_to_mas_15;
input  s_add_c_to_mas_16;
input  s_add_c_to_mas_33;
output s_mas_done_from_mas;
input  reset_i;
input  sys_clk_i;
input  s_mas_en_to_mas;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [43:0] product_o;
    wire MSC_net_153, MSC_net_154, MSC_net_155;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
j9J2bWOrwPgI2IN4ad1P+DEcAgDIXoVAyLL2jCY+x61PblcuUnIoF8jbrVI+6yt5
EkkQ7bqCrnJMvykMmpMtWo6CSvqmPBh6bSDTn+tGihHeoCMtXhO0Np3AdSTRy3Gt
6q4SwJCAaUE53Xptiho6mRFXs2Y4dSiq005ZEzdTrvA=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8885)
`pragma protect data_block
[encoded data, 8704 characters]
ht96H+xsoxaUyPo973Df0wzlEEO5ozzUfffYx1JP0MA=

`pragma protect end_protected

endmodule


module FOC_TRANSFORMS_2s_44s_1(
       reset_i,
       sys_clk_i,
       start_clarke_i,
       start_park_i,
       start_ipark_i,
       start_iclarke_i,
       ia_i,
       ib_i,
       ialpha_i,
       ibeta_i,
       vd_i,
       vq_i,
       valpha_i,
       vbeta_i,
       theta_i,
       clarke_done_o,
       park_done_o,
       ipark_done_o,
       iclarke_done_o,
       ialpha_o,
       ibeta_o,
       id_o,
       iq_o,
       valpha_o,
       vbeta_o,
       va_o,
       vb_o,
       vc_o
    );
input  reset_i;
input  sys_clk_i;
input  start_clarke_i;
input  start_park_i;
input  start_ipark_i;
input  start_iclarke_i;
input  [17:0] ia_i;
input  [17:0] ib_i;
input  [17:0] ialpha_i;
input  [17:0] ibeta_i;
input  [17:0] vd_i;
input  [17:0] vq_i;
input  [17:0] valpha_i;
input  [17:0] vbeta_i;
input  [17:0] theta_i;
output clarke_done_o;
output park_done_o;
output ipark_done_o;
output iclarke_done_o;
output [17:0] ialpha_o;
output [17:0] ibeta_o;
output [17:0] id_o;
output [17:0] iq_o;
output [17:0] valpha_o;
output [17:0] vbeta_o;
output [17:0] va_o;
output [17:0] vb_o;
output [17:0] vc_o;

    wire [17:0] s_mul_a_from_clarke;
    wire [1:1] s_mul_b_from_clarke;
    wire [17:0] s_mul_a_from_cordic;
    wire [17:0] s_mul_a_from_iclarke;
    wire [2:2] s_mul_b_from_iclarke;
    wire [17:0] s_mul_a_to_mas;
    wire [9:0] s_mul_b_to_mas;
    wire [43:10] s_add_c_to_mas;
    wire [28:9] s_product_from_mas;
    wire [1:0] \MAS_SCHEDULER_INST.s_mas_sel ;
    wire MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
EOizju8x9sXxx0EuaKHtr2eQxRqcc/wECJaVZyQroEghIN727EjFtwgQT6rgKGee
vBYFI4aFOMtrsUp+7T04LIE7oWyh86NXKZcdaRp5f2b5gFx5ZGI6CYNQbFjKbxTD
V+ev88nuSpz2GCpSz9Ba4Jz62keUlQduMsCiKfvftJU=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=20475)
`pragma protect data_block
[encoded data, 20160 characters]

`pragma protect end_protected

endmodule


module PWM3PH_1(
       reset_i,
       sys_clk_i,
       en_pwm_i,
       en_dual_trig_i,
       va_i,
       vb_i,
       vc_i,
       pwm_period_i,
       dead_time_i,
       delay_time_i,
       midmatch_o,
       PWM_AH_o,
       PWM_BH_o,
       PWM_CH_o,
       PWM_AL_o,
       PWM_BL_o,
       PWM_CL_o
    );
input  reset_i;
input  sys_clk_i;
input  en_pwm_i;
input  en_dual_trig_i;
input  [17:0] va_i;
input  [17:0] vb_i;
input  [17:0] vc_i;
input  [17:0] pwm_period_i;
input  [17:0] dead_time_i;
input  [17:0] delay_time_i;
output midmatch_o;
output PWM_AH_o;
output PWM_BH_o;
output PWM_CH_o;
output PWM_AL_o;
output PWM_BL_o;
output PWM_CL_o;

    wire MSC_net_116;
    wire [17:0] s_pwm_counter;
    wire [17:0] s_delay_counter;
    wire [17:1] \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4 ;
    wire [8:0] \PWM_MIDMATCH_GEN_PROC.s_midmatch5_0_data_tmp ;
    wire [16:0] s_pwm_counter_cry;
    wire [17:0] s_pwm_counter_s;
    wire [17:0] s_delay_counter_s;
    wire [16:1] s_delay_counter_cry;
    wire [16:1] s_delay_counter_cry_Y;
    wire [17:17] s_delay_counter_s_FCO;
    wire [17:17] s_delay_counter_s_Y;
    wire [16:0] s_pwm_counter_cry_Y;
    wire [17:17] s_pwm_counter_s_FCO;
    wire [17:17] s_pwm_counter_s_Y;
    wire MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5 , 
        \PWM_OUTPUT_GEN.un1_va_i , \PWM_OUTPUT_GEN.un1_vb_i , 
        \PWM_OUTPUT_GEN.un1_vc_i , MSC_net_309, 
        \PWM_OUTPUT_GEN.PWM_AH_o6 , \PWM_OUTPUT_GEN.PWM_BH_o6 , 
        \PWM_OUTPUT_GEN.PWM_CH_o6 , MSC_net_313, MSC_net_314, 
        MSC_net_315, MSC_net_316, \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_16_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_16_Z , MSC_net_436, MSC_net_437, 
        MSC_net_438, MSC_net_439, MSC_net_440, MSC_net_441, 
        MSC_net_442, MSC_net_443, MSC_net_444, MSC_net_445, 
        MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_5_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_7_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_13_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_15_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_Z , MSC_net_474, 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_15_Z , MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_RNIOO6E5_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_RNIOO6E5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_RNIPKUS4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_RNIPKUS4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_RNI7T6E4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_RNI7T6E4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_RNIT9FV3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_RNIT9FV3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_RNIRQNG3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_RNIRQNG3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_RNIT8VP2_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_RNIT8VP2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_RNI7R632_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_RNI7R632_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_RNIPHEC1_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_RNIPHEC1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_RNIJCML_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_RNIJCML_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_0_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_17_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_17_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_0_Y , MSC_net_759, MSC_net_760, 
        MSC_net_761, MSC_net_762, MSC_net_763, MSC_net_764, 
        MSC_net_765, MSC_net_766, MSC_net_767, MSC_net_768, 
        MSC_net_769, MSC_net_770, MSC_net_771, MSC_net_772, 
        MSC_net_773, MSC_net_774, MSC_net_775, MSC_net_776, 
        MSC_net_777, MSC_net_778, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_s_17_FCO , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_s_17_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_15_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_13_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_11_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_9_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_7_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_Y , MSC_net_799, 
        MSC_net_800, MSC_net_801, MSC_net_802;
    assign PWM_AL_o = MSC_net_116;
    assign PWM_BL_o = MSC_net_116;
    assign PWM_CL_o = MSC_net_116;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
ptDfJ9ZJTCxN6GX/DsnbNLtcSKMITJxQi148kBcWSP8fnmF1NlyTNxB+HLTeTZSy
NnOhiaEBHHtke8DFA6dpgxGpp+o999/d3kQJW3CIVZMfkjL0zM34H+U7Sirea3oT
KKnyZXO1klAwo52XtNJVgeq6kjP3MJKmnJ6jsB0Y9n0=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=115570)
`pragma protect data_block
[encoded data, 113792 characters]

`pragma protect end_protected

endmodule


module 
        work_adc_interface_adc_interface_6_16_12_g_ADC_CONFIG_REG_WIDTHg_ADC_CONFIG_VAL_WIDTHg_ADC_RESULTS_WIDTH_1(
        
       apb3_if_0_adc_control_reg_val_o,
       adc_interface_0_result_ch0_o,
       adc_interface_0_result_ch1_o,
       adc_measurements_0_adc_result_ch2_o,
       adc_measurements_0_adc_result_ch3_o,
       apb3_if_0_adc_channel_ch2_o,
       apb3_if_0_adc_channel_ch0_o,
       apb3_if_0_adc_channel_ch1_o,
       apb3_if_0_adc_channel_ch3_o,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       SEQ_CONTROLLER_1_adc_start_o,
       A0_ADC_SDI_I_c,
       A0_ADC_SDO_O_c,
       A0_ADC_CS_O_c,
       A0_ADC_SCK_O_c,
       adc_interface_0_results_rdy_o
    );
input  [5:0] apb3_if_0_adc_control_reg_val_o;
output [11:0] adc_interface_0_result_ch0_o;
output [11:0] adc_interface_0_result_ch1_o;
output [11:0] adc_measurements_0_adc_result_ch2_o;
output [11:0] adc_measurements_0_adc_result_ch3_o;
input  [15:0] apb3_if_0_adc_channel_ch2_o;
input  [15:0] apb3_if_0_adc_channel_ch0_o;
input  [15:0] apb3_if_0_adc_channel_ch1_o;
input  [15:0] apb3_if_0_adc_channel_ch3_o;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;
input  SEQ_CONTROLLER_1_adc_start_o;
input  A0_ADC_SDI_I_c;
output A0_ADC_SDO_O_c;
output A0_ADC_CS_O_c;
output A0_ADC_SCK_O_c;
output adc_interface_0_results_rdy_o;

    wire [4:0] s_r_sck_count;
    wire [2:0] s_channel_cnt;
    wire [2:0] s_channel_cnt_5;
    wire [2:0] s_r_adc_chnls_4_samp;
    wire [2:0] s_r_sck_sel;
    wire [15:0] s_r_adc_data;
    wire [12:0] s_r_adc_data_4;
    wire [15:0] s_sdo;
    wire [15:0] s_sdo_14;
    wire [4:0] present_state;
    wire [4:4] next_state;
    wire [3:1] present_state_ns;
    wire [4:4] next_state_i_0;
    wire [3:3] s_r_sck_max_count;
    wire [7:0] s_r_clock_count;
    wire [7:0] s_r_clock_count_s;
    wire [6:0] s_r_clock_count_cry;
    wire [6:0] s_r_clock_count_cry_Y;
    wire [7:7] s_r_clock_count_s_FCO;
    wire [7:7] s_r_clock_count_s_Y;
    wire [0:0] s_sdo_14_m3_am;
    wire [0:0] s_sdo_14_m3_bm;
    wire [15:1] s_sdo_14_m3_am_0;
    wire [15:1] s_sdo_14_m3_bm_0;
    wire [15:1] s_sdo_14_m3;
    wire [1:1] present_state_ns_a3_1;
    wire VCC, s_r_sck_count_n2_Z, s_r_sck_counte, GND, 
        s_r_sck_count_n3_Z, s_r_sck_count_n4_Z, N_2167, N_2162_i_0, 
        s_r_sck_count_0_sqmuxa_Z, N_2165_i_0, N_2164_i_0, N_2163_i_0, 
        result_ch1_o_1_sqmuxa, result_ch0_o_0_sqmuxa, 
        result_ch2_o_1_sqmuxa, result_ch3_o_1_sqmuxa_Z, 
        s_sdo_1_sqmuxa_3_i_0, s_start_sig_ext_Z, 
        un13_s_r_adc_results_ready, s_adc_sdi_Z, N_154_i_0, N_173_i_0, 
        s_r_sck_enable_Z, adc_sdo_dly_Z, s_slave_select_2, s_r_sck_Z, 
        s_r_sck_10, s_r_adc_results_ready_1_sqmuxa_1, 
        s_r_clock_count_s_170_FCO, s_r_clock_count_s_170_S, 
        s_r_clock_count_s_170_Y, s_channel_cnt_0_sqmuxa_Z, 
        un13_s_r_sck, s_sdo_14_sm1, s_r_sck_10_7_am_1_1, 
        s_r_sck_10_7_am, s_r_sck_10_7_bm_1_1, s_r_sck_10_7_bm, 
        result_ch3_o_1_sqmuxa_0_Z, un1_s_r_sck, 
        un15_s_r_sck_count_NE_2, un10_s_start_sig_ext_0_a3_2, 
        s_r_sck_count_c2_Z, un15_s_r_sck_count_NE, N_188, 
        un1_s_sdo_2_sqmuxa_tz, s_sdo_3_sqmuxa_Z, 
        un1_s_sdo_1_sqmuxa_1_tz_Z, CO1, un1_s_sdo_0_sqmuxa_Z, 
        un1_s_sdo_1_sqmuxa_1_0, un22_s_r_sck, 
        s_r_adc_results_ready_0_sqmuxa_1, CO0, N_120, N_119, N_118, 
        N_117, N_116;
    
    SLE s_r_sck (.D(s_r_sck_10), .CLK(MC_System_0_FIC_0_CLK), .EN(VCC), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(s_r_sck_Z));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[2]  (.A(
        s_sdo_14_m3[2]), .B(s_sdo[1]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[2]));
    SLE s_r_sck_enable (.D(next_state_i_0[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_sck_enable_Z)
        );
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[10]  (
        .A(s_sdo_14_m3_am_0[10]), .B(s_sdo_14_m3_bm_0[10]), .C(
        s_sdo_14_sm1), .Y(s_sdo_14_m3[10]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[1]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[0]), .Y(s_r_adc_data_4[1]));
    SLE \s_r_adc_data[13]  (.D(N_2165_i_0), .CLK(MC_System_0_FIC_0_CLK)
        , .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_adc_data[13])
        );
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[14]  (
        .A(s_sdo_14_m3_am_0[14]), .B(s_sdo_14_m3_bm_0[14]), .C(
        s_sdo_14_sm1), .Y(s_sdo_14_m3[14]));
    SLE \s_r_adc_data[4]  (.D(s_r_adc_data_4[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[4]));
    SLE s_slave_select (.D(s_slave_select_2), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(A0_ADC_CS_O_c));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[10]  
        (.A(apb3_if_0_adc_channel_ch1_o[10]), .B(
        apb3_if_0_adc_channel_ch3_o[10]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[10]));
    SLE \s_r_adc_chnls_4_samp[0]  (.D(
        apb3_if_0_adc_control_reg_val_o[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_adc_chnls_4_samp[0]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[1]  
        (.A(apb3_if_0_adc_channel_ch1_o[1]), .B(
        apb3_if_0_adc_channel_ch3_o[1]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[1]));
    SLE \s_r_clock_count[4]  (.D(s_r_clock_count_s[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[4]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[3]  
        (.A(apb3_if_0_adc_channel_ch1_o[3]), .B(
        apb3_if_0_adc_channel_ch3_o[3]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[3]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[1]  (.A(
        s_sdo_14_m3_am_0[1]), .B(s_sdo_14_m3_bm_0[1]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[1]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[10]  (.A(
        s_sdo_14_m3[10]), .B(s_sdo[9]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[10]));
    CFG4 #( .INIT(16'h1444) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[1]  (
        .A(present_state[4]), .B(s_channel_cnt[1]), .C(
        s_channel_cnt[0]), .D(s_channel_cnt_0_sqmuxa_Z), .Y(
        s_channel_cnt_5[1]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[1]  (.A(VCC), .B(
        s_r_clock_count[1]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[0]), .S(s_r_clock_count_s[1]), .Y(
        s_r_clock_count_cry_Y[1]), .FCO(s_r_clock_count_cry[1]));
    CFG4 #( .INIT(16'h3437) )  \SCK_GEN_PROC.s_r_sck_10_7_bm_1_1  (.A(
        s_r_clock_count[5]), .B(s_r_sck_sel[2]), .C(s_r_sck_sel[1]), 
        .D(s_r_clock_count[1]), .Y(s_r_sck_10_7_bm_1_1));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[4]  (.A(
        s_sdo_14_m3[4]), .B(s_sdo[3]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[4]));
    SLE \s_sdo[2]  (.D(s_sdo_14[2]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[2]));
    CFG2 #( .INIT(4'hE) )  s_sdo_1_sqmuxa_3_i (.A(un1_s_r_sck), .B(
        A0_ADC_CS_O_c), .Y(s_sdo_1_sqmuxa_3_i_0));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[4]  (.A(VCC), .B(
        s_r_clock_count[4]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[3]), .S(s_r_clock_count_s[4]), .Y(
        s_r_clock_count_cry_Y[4]), .FCO(s_r_clock_count_cry[4]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[7]  (.A(
        s_sdo_14_m3[7]), .B(s_sdo[6]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[7]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[5]  (.A(
        s_sdo_14_m3[5]), .B(s_sdo[4]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[5]));
    SLE \result_ch0_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[4]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[12]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[11]), .Y(
        s_r_adc_data_4[12]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[0]  (.A(VCC), .B(
        s_r_clock_count[0]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_s_170_FCO), .S(s_r_clock_count_s[0]), .Y(
        s_r_clock_count_cry_Y[0]), .FCO(s_r_clock_count_cry[0]));
    SLE \result_ch1_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[8]));
    CFG4 #( .INIT(16'h5755) )  \SS_GEN_PROC.s_slave_select_2  (.A(
        s_start_sig_ext_Z), .B(s_r_sck_count[2]), .C(s_r_sck_count[0]), 
        .D(un10_s_start_sig_ext_0_a3_2), .Y(s_slave_select_2));
    SLE \s_sdo[5]  (.D(s_sdo_14[5]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[5]));
    SLE \result_ch3_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[0]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[9]  (.A(
        s_sdo_14_m3[9]), .B(s_sdo[8]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[9]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[7]  (.A(
        s_sdo_14_m3_am_0[7]), .B(s_sdo_14_m3_bm_0[7]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[7]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[4]  (.A(
        s_sdo_14_m3_am_0[4]), .B(s_sdo_14_m3_bm_0[4]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[4]));
    CFG2 #( .INIT(4'h2) )  un1_s_sdo_0_sqmuxa_tz_1 (.A(
        s_r_adc_chnls_4_samp[1]), .B(s_r_adc_chnls_4_samp[2]), .Y(
        un1_s_sdo_2_sqmuxa_tz));
    SLE \s_r_sck_count[0]  (.D(N_2167), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_r_sck_counte), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_sck_count[0]));
    SLE \s_sdo[0]  (.D(s_sdo_14[0]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[0]));
    CFG2 #( .INIT(4'h4) )  \s_r_adc_data_RNO[13]  (.A(A0_ADC_CS_O_c), 
        .B(s_r_adc_data[12]), .Y(N_2165_i_0));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[12]  (
        .A(s_sdo_14_m3_am_0[12]), .B(s_sdo_14_m3_bm_0[12]), .C(
        s_sdo_14_sm1), .Y(s_sdo_14_m3[12]));
    SLE s_start_sig_ext (.D(SEQ_CONTROLLER_1_adc_start_o), .CLK(
        MC_System_0_FIC_0_CLK), .EN(un13_s_r_adc_results_ready), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_start_sig_ext_Z));
    CFG4 #( .INIT(16'h6A00) )  s_r_sck_count_n2 (.A(s_r_sck_count[2]), 
        .B(s_r_sck_count[1]), .C(s_r_sck_count[0]), .D(
        present_state[1]), .Y(s_r_sck_count_n2_Z));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[3]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[2]), .Y(s_r_adc_data_4[3]));
    SLE \result_ch2_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[3]));
    SLE \s_r_adc_data[6]  (.D(s_r_adc_data_4[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[6]));
    SLE \result_ch1_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[6]));
    SLE s_adc_sdi (.D(A0_ADC_SDI_I_c), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(N_154_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(
        VCC), .SD(GND), .LAT(GND), .Q(s_adc_sdi_Z));
    SLE \result_ch1_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[4]));
    CFG4 #( .INIT(16'h0001) )  un1_s_sdo_0_sqmuxa (.A(
        s_r_adc_chnls_4_samp[2]), .B(s_channel_cnt[1]), .C(
        s_channel_cnt[2]), .D(s_channel_cnt[0]), .Y(
        un1_s_sdo_0_sqmuxa_Z));
    CFG2 #( .INIT(4'hE) )  
        \START_SIG_PROC.un13_s_r_adc_results_ready_0  (.A(
        s_r_adc_results_ready_1_sqmuxa_1), .B(
        SEQ_CONTROLLER_1_adc_start_o), .Y(un13_s_r_adc_results_ready));
    ARI1 #( .INIT(20'h4AA00) )  s_r_clock_count_s_170 (.A(VCC), .B(
        s_r_sck_enable_Z), .C(GND), .D(GND), .FCI(VCC), .S(
        s_r_clock_count_s_170_S), .Y(s_r_clock_count_s_170_Y), .FCO(
        s_r_clock_count_s_170_FCO));
    CFG3 #( .INIT(8'h80) )  s_r_adc_results_ready_0_sqmuxa_1_0_a3 (.A(
        un22_s_r_sck), .B(present_state[0]), .C(un1_s_r_sck), .Y(
        s_r_adc_results_ready_0_sqmuxa_1));
    CFG2 #( .INIT(4'h8) )  s_adc_sdi_RNO (.A(un1_s_r_sck), .B(
        present_state[1]), .Y(N_154_i_0));
    SLE \s_sdo[1]  (.D(s_sdo_14[1]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[1]));
    SLE \present_state[2]  (.D(present_state_ns[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(present_state[2])
        );
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[8]  (.A(
        s_sdo_14_m3[8]), .B(s_sdo[7]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[8]));
    SLE \s_r_clock_count[5]  (.D(s_r_clock_count_s[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[5]));
    SLE \result_ch3_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[3]));
    SLE \s_r_clock_count[2]  (.D(s_r_clock_count_s[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[2]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[13]  (
        .A(apb3_if_0_adc_channel_ch2_o[13]), .B(
        apb3_if_0_adc_channel_ch0_o[13]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[13]));
    CFG4 #( .INIT(16'h28A0) )  s_r_sck_count_n4 (.A(present_state[1]), 
        .B(s_r_sck_count_c2_Z), .C(s_r_sck_count[4]), .D(
        s_r_sck_count[3]), .Y(s_r_sck_count_n4_Z));
    CFG4 #( .INIT(16'hFDFE) )  
        \ADC_RESULTS_PROC.un15_s_r_sck_count_NE_2  (.A(
        s_r_sck_max_count[3]), .B(s_r_sck_count[3]), .C(
        s_r_sck_count[2]), .D(s_r_sck_count[1]), .Y(
        un15_s_r_sck_count_NE_2));
    SLE \s_sdo[15]  (.D(s_sdo_14[15]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[15]));
    SLE \s_sdo[12]  (.D(s_sdo_14[12]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[12]));
    SLE \s_r_clock_count[3]  (.D(s_r_clock_count_s[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[3]));
    SLE \s_r_adc_data[14]  (.D(N_2164_i_0), .CLK(MC_System_0_FIC_0_CLK)
        , .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_adc_data[14])
        );
    SLE results_rdy_o (.D(s_r_adc_results_ready_1_sqmuxa_1), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        adc_interface_0_results_rdy_o));
    SLE \result_ch2_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[2]));
    SLE \s_r_sck_count[4]  (.D(s_r_sck_count_n4_Z), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[4]));
    SLE \result_ch1_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[10]));
    SLE \s_r_adc_data[7]  (.D(s_r_adc_data_4[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[7]));
    SLE \result_ch0_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[2]));
    CFG4 #( .INIT(16'h0020) )  result_ch2_o_1_sqmuxa_0_a3 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(
        result_ch3_o_1_sqmuxa_0_Z), .D(un15_s_r_sck_count_NE), .Y(
        result_ch2_o_1_sqmuxa));
    SLE \s_channel_cnt[0]  (.D(s_channel_cnt_5[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_channel_cnt[0])
        );
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[6]  (.A(
        s_sdo_14_m3_am_0[6]), .B(s_sdo_14_m3_bm_0[6]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[6]));
    SLE \result_ch1_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[5]));
    SLE \s_sdo[11]  (.D(s_sdo_14[11]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[11]));
    SLE \s_r_sck_sel[0]  (.D(apb3_if_0_adc_control_reg_val_o[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_sck_sel[0]));
    CFG2 #( .INIT(4'h2) )  s_r_sck_count_n0_i_a3 (.A(present_state[1]), 
        .B(s_r_sck_count[0]), .Y(N_2167));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[11]  (.A(
        s_sdo_14_m3[11]), .B(s_sdo[10]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[11]));
    SLE \s_r_adc_data[15]  (.D(N_2163_i_0), .CLK(MC_System_0_FIC_0_CLK)
        , .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_adc_data[15])
        );
    CFG4 #( .INIT(16'hFFE7) )  
        \ADC_RESULTS_PROC.un15_s_r_sck_count_NE  (.A(
        s_r_sck_max_count[3]), .B(s_r_sck_count[4]), .C(
        s_r_sck_count[0]), .D(un15_s_r_sck_count_NE_2), .Y(
        un15_s_r_sck_count_NE));
    CFG3 #( .INIT(8'hA4) )  \present_state_ns_i_m4[2]  (.A(
        present_state[3]), .B(present_state[2]), .C(un1_s_r_sck), .Y(
        present_state_ns[2]));
    CFG3 #( .INIT(8'hDC) )  \next_state_0[4]  (.A(
        SEQ_CONTROLLER_1_adc_start_o), .B(
        s_r_adc_results_ready_1_sqmuxa_1), .C(present_state[4]), .Y(
        next_state[4]));
    SLE \s_r_adc_data[5]  (.D(s_r_adc_data_4[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[5]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[1]  (.A(
        apb3_if_0_adc_channel_ch2_o[1]), .B(
        apb3_if_0_adc_channel_ch0_o[1]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[1]));
    SLE \s_r_adc_data[11]  (.D(s_r_adc_data_4[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[11]));
    SLE \s_r_adc_chnls_4_samp[1]  (.D(
        apb3_if_0_adc_control_reg_val_o[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_adc_chnls_4_samp[1]));
    SLE \s_sdo[9]  (.D(s_sdo_14[9]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[9]));
    SLE \result_ch0_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[1]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[3]  (.A(
        apb3_if_0_adc_channel_ch2_o[3]), .B(
        apb3_if_0_adc_channel_ch0_o[3]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[3]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[5]  
        (.A(apb3_if_0_adc_channel_ch1_o[5]), .B(
        apb3_if_0_adc_channel_ch3_o[5]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[5]));
    SLE \s_r_sck_max_count[3]  (.D(VCC), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_r_sck_max_count[3]));
    GND GND_Z (.Y(GND));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[4]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[3]), .Y(s_r_adc_data_4[4]));
    SLE \s_sdo[4]  (.D(s_sdo_14[4]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[4]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[9]  
        (.A(apb3_if_0_adc_channel_ch1_o[9]), .B(
        apb3_if_0_adc_channel_ch3_o[9]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[9]));
    CFG4 #( .INIT(16'h006A) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[2]  (
        .A(s_channel_cnt[2]), .B(CO0), .C(s_channel_cnt[1]), .D(
        present_state[4]), .Y(s_channel_cnt_5[2]));
    VCC VCC_Z (.Y(VCC));
    CFG4 #( .INIT(16'h0800) )  s_channel_cnt_0_sqmuxa (.A(
        present_state[0]), .B(s_r_sck_Z), .C(A0_ADC_SCK_O_c), .D(
        un22_s_r_sck), .Y(s_channel_cnt_0_sqmuxa_Z));
    SLE \s_r_sck_sel[2]  (.D(apb3_if_0_adc_control_reg_val_o[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_sck_sel[2]));
    SLE \s_r_adc_data[10]  (.D(s_r_adc_data_4[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[10]));
    SLE \result_ch0_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[8]));
    SLE \result_ch2_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[5]));
    SLE \result_ch2_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[10]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[10]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[9]), .Y(s_r_adc_data_4[10])
        );
    CFG4 #( .INIT(16'h7555) )  \present_state_ns_o4_RNIN9SS[3]  (.A(
        present_state[1]), .B(s_r_sck_Z), .C(un13_s_r_sck), .D(
        A0_ADC_SCK_O_c), .Y(s_r_sck_counte));
    SLE \result_ch3_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[4]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[13]  (.A(
        s_sdo_14_m3[13]), .B(s_sdo[12]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[13]));
    SLE \result_ch0_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[9]));
    SLE \result_ch3_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[6]));
    SLE sdo_o (.D(adc_sdo_dly_Z), .CLK(MC_System_0_FIC_0_CLK), .EN(VCC)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(A0_ADC_SDO_O_c));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_s[7]  (.A(VCC), .B(
        s_r_clock_count[7]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[6]), .S(s_r_clock_count_s[7]), .Y(
        s_r_clock_count_s_Y[7]), .FCO(s_r_clock_count_s_FCO[7]));
    SLE \result_ch1_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[11]));
    SLE \result_ch0_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[5]));
    SLE \result_ch0_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[0]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[0]  
        (.A(apb3_if_0_adc_channel_ch1_o[0]), .B(
        apb3_if_0_adc_channel_ch3_o[0]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[0]));
    CFG4 #( .INIT(16'hEACC) )  \present_state_ns[3]  (.A(
        present_state[2]), .B(present_state[1]), .C(un13_s_r_sck), .D(
        un1_s_r_sck), .Y(present_state_ns[3]));
    SLE \s_r_adc_data[8]  (.D(s_r_adc_data_4[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[8]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[0]  (
        .A(A0_ADC_CS_O_c), .B(s_adc_sdi_Z), .Y(s_r_adc_data_4[0]));
    SLE \s_r_clock_count[6]  (.D(s_r_clock_count_s[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[6]));
    CFG4 #( .INIT(16'h0080) )  result_ch3_o_1_sqmuxa (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(
        result_ch3_o_1_sqmuxa_0_Z), .D(un15_s_r_sck_count_NE), .Y(
        result_ch3_o_1_sqmuxa_Z));
    CFG4 #( .INIT(16'hFF10) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3s2  (.A(
        s_channel_cnt[2]), .B(s_channel_cnt[0]), .C(
        un1_s_sdo_2_sqmuxa_tz), .D(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_sm1));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[2]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[1]), .Y(s_r_adc_data_4[2]));
    SLE \present_state[0]  (.D(N_173_i_0), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(present_state[0]));
    CFG4 #( .INIT(16'h0040) )  result_ch1_o_1_sqmuxa_0_a3 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(
        result_ch3_o_1_sqmuxa_0_Z), .D(un15_s_r_sck_count_NE), .Y(
        result_ch1_o_1_sqmuxa));
    SLE \result_ch3_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[1]));
    SLE \result_ch2_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[6]));
    SLE \s_r_sck_count[3]  (.D(s_r_sck_count_n3_Z), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[3]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[2]  
        (.A(apb3_if_0_adc_channel_ch1_o[2]), .B(
        apb3_if_0_adc_channel_ch3_o[2]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[2]));
    SLE \s_r_sck_count[1]  (.D(N_2162_i_0), .CLK(MC_System_0_FIC_0_CLK)
        , .EN(s_r_sck_counte), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_sck_count[1]));
    SLE \present_state[3]  (.D(present_state_ns[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(present_state[3])
        );
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[13]  (
        .A(s_sdo_14_m3_am_0[13]), .B(s_sdo_14_m3_bm_0[13]), .C(
        s_sdo_14_sm1), .Y(s_sdo_14_m3[13]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[8]  
        (.A(apb3_if_0_adc_channel_ch1_o[8]), .B(
        apb3_if_0_adc_channel_ch3_o[8]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[8]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[7]  
        (.A(apb3_if_0_adc_channel_ch1_o[7]), .B(
        apb3_if_0_adc_channel_ch3_o[7]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[7]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[7]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[6]), .Y(s_r_adc_data_4[7]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[14]  (.A(
        s_sdo_14_m3[14]), .B(s_sdo[13]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[14]));
    CFG4 #( .INIT(16'h045D) )  \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO1  (
        .A(s_r_adc_chnls_4_samp[1]), .B(s_r_adc_chnls_4_samp[0]), .C(
        s_channel_cnt[0]), .D(s_channel_cnt[1]), .Y(CO1));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[6]  (.A(VCC), .B(
        s_r_clock_count[6]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[5]), .S(s_r_clock_count_s[6]), .Y(
        s_r_clock_count_cry_Y[6]), .FCO(s_r_clock_count_cry[6]));
    SLE \s_channel_cnt[2]  (.D(s_channel_cnt_5[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_channel_cnt[2])
        );
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[4]  
        (.A(apb3_if_0_adc_channel_ch1_o[4]), .B(
        apb3_if_0_adc_channel_ch3_o[4]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[4]));
    SLE \s_sdo[6]  (.D(s_sdo_14[6]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[6]));
    SLE \result_ch0_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[3]));
    SLE \result_ch0_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[7]));
    CFG2 #( .INIT(4'h4) )  \s_r_adc_data_RNO[15]  (.A(A0_ADC_CS_O_c), 
        .B(s_r_adc_data[14]), .Y(N_2163_i_0));
    CFG3 #( .INIT(8'h01) )  \SS_GEN_PROC.un10_s_start_sig_ext_0_a3_2  
        (.A(s_r_sck_count[4]), .B(s_r_sck_count[3]), .C(
        s_r_sck_count[1]), .Y(un10_s_start_sig_ext_0_a3_2));
    SLE \result_ch0_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[6]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[9]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[8]), .Y(s_r_adc_data_4[9]));
    SLE \result_ch3_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[10]));
    CFG4 #( .INIT(16'h0010) )  result_ch0_o_0_sqmuxa_0_a3 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(
        result_ch3_o_1_sqmuxa_0_Z), .D(un15_s_r_sck_count_NE), .Y(
        result_ch0_o_0_sqmuxa));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[6]  
        (.A(apb3_if_0_adc_channel_ch1_o[6]), .B(
        apb3_if_0_adc_channel_ch3_o[6]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[6]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[15]  (.A(
        s_sdo_14_m3[15]), .B(s_sdo[14]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[15]));
    SLE \present_state[1]  (.D(present_state_ns[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(present_state[1])
        );
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[9]  (.A(
        s_sdo_14_m3_am_0[9]), .B(s_sdo_14_m3_bm_0[9]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[9]));
    CFG3 #( .INIT(8'h40) )  \next_state_0_a3_0[4]  (.A(un22_s_r_sck), 
        .B(present_state[0]), .C(un1_s_r_sck), .Y(
        s_r_adc_results_ready_1_sqmuxa_1));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[10]  (
        .A(apb3_if_0_adc_channel_ch2_o[10]), .B(
        apb3_if_0_adc_channel_ch0_o[10]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[10]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[15]  (
        .A(apb3_if_0_adc_channel_ch2_o[15]), .B(
        apb3_if_0_adc_channel_ch0_o[15]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[15]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[15]  
        (.A(apb3_if_0_adc_channel_ch1_o[15]), .B(
        apb3_if_0_adc_channel_ch3_o[15]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[15]));
    SLE \result_ch3_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[5]));
    CFG4 #( .INIT(16'hFFF4) )  \present_state_ns[1]  (.A(un1_s_r_sck), 
        .B(present_state[3]), .C(s_r_adc_results_ready_0_sqmuxa_1), .D(
        N_188), .Y(present_state_ns[1]));
    CFG4 #( .INIT(16'h0400) )  s_sdo_3_sqmuxa (.A(
        s_r_adc_chnls_4_samp[2]), .B(s_r_adc_chnls_4_samp[0]), .C(
        s_channel_cnt[2]), .D(s_r_adc_chnls_4_samp[1]), .Y(
        s_sdo_3_sqmuxa_Z));
    CFG4 #( .INIT(16'hE040) )  \s_sdo_RNO[0]  (.A(s_sdo_14_sm1), .B(
        s_sdo_14_m3_am[0]), .C(A0_ADC_CS_O_c), .D(s_sdo_14_m3_bm[0]), 
        .Y(s_sdo_14[0]));
    SLE \result_ch2_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[4]));
    CFG3 #( .INIT(8'hE2) )  \SCK_GEN_PROC.s_r_sck_10_7_ns  (.A(
        s_r_sck_10_7_am), .B(s_r_sck_sel[0]), .C(s_r_sck_10_7_bm), .Y(
        s_r_sck_10));
    SLE \result_ch2_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[11]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[11]  
        (.A(apb3_if_0_adc_channel_ch1_o[11]), .B(
        apb3_if_0_adc_channel_ch3_o[11]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[11]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[5]  (.A(VCC), .B(
        s_r_clock_count[5]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[4]), .S(s_r_clock_count_s[5]), .Y(
        s_r_clock_count_cry_Y[5]), .FCO(s_r_clock_count_cry[5]));
    SLE \s_sdo[13]  (.D(s_sdo_14[13]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[13]));
    CFG3 #( .INIT(8'h80) )  s_r_sck_count_c2 (.A(s_r_sck_count[2]), .B(
        s_r_sck_count[1]), .C(s_r_sck_count[0]), .Y(s_r_sck_count_c2_Z)
        );
    SLE \result_ch2_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[0]));
    CFG4 #( .INIT(16'h0004) )  \present_state_ns_a3[1]  (.A(
        present_state[1]), .B(present_state_ns_a3_1[1]), .C(
        present_state[3]), .D(present_state[2]), .Y(N_188));
    SLE \s_sdo[7]  (.D(s_sdo_14[7]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[7]));
    CFG3 #( .INIT(8'h28) )  s_r_sck_count_n3 (.A(present_state[1]), .B(
        s_r_sck_count_c2_Z), .C(s_r_sck_count[3]), .Y(
        s_r_sck_count_n3_Z));
    SLE \result_ch3_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[2]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[11]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[10]), .Y(
        s_r_adc_data_4[11]));
    SLE \result_ch3_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[7]));
    SLE \result_ch1_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[1]));
    CFG2 #( .INIT(4'h2) )  \present_state_ns_a3_1[1]  (.A(
        SEQ_CONTROLLER_1_adc_start_o), .B(present_state[0]), .Y(
        present_state_ns_a3_1[1]));
    CFG4 #( .INIT(16'h3437) )  \SCK_GEN_PROC.s_r_sck_10_7_am_1_1  (.A(
        s_r_clock_count[4]), .B(s_r_sck_sel[2]), .C(s_r_sck_sel[1]), 
        .D(s_r_clock_count[0]), .Y(s_r_sck_10_7_am_1_1));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[12]  (
        .A(apb3_if_0_adc_channel_ch2_o[12]), .B(
        apb3_if_0_adc_channel_ch0_o[12]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[12]));
    SLE \result_ch1_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[9]));
    CFG4 #( .INIT(16'h04AC) )  \present_state_RNO[0]  (.A(
        present_state[1]), .B(present_state[0]), .C(un1_s_r_sck), .D(
        un13_s_r_sck), .Y(N_173_i_0));
    SLE \result_ch3_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[9]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[5]  (.A(
        apb3_if_0_adc_channel_ch2_o[5]), .B(
        apb3_if_0_adc_channel_ch0_o[5]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[5]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[12]  (.A(
        s_sdo_14_m3[12]), .B(s_sdo[11]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[12]));
    SLE \present_state[4]  (.D(next_state[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(GND), .SLn(VCC), .SD(GND), .LAT(GND), .Q(present_state[4])
        );
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[15]  (
        .A(s_sdo_14_m3_am_0[15]), .B(s_sdo_14_m3_bm_0[15]), .C(
        s_sdo_14_sm1), .Y(s_sdo_14_m3[15]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[9]  (.A(
        apb3_if_0_adc_channel_ch2_o[9]), .B(
        apb3_if_0_adc_channel_ch0_o[9]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[9]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[11]  (
        .A(s_sdo_14_m3_am_0[11]), .B(s_sdo_14_m3_bm_0[11]), .C(
        s_sdo_14_sm1), .Y(s_sdo_14_m3[11]));
    SLE \result_ch0_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[10]));
    SLE \s_r_adc_data[2]  (.D(s_r_adc_data_4[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[2]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[2]  (.A(
        s_sdo_14_m3_am_0[2]), .B(s_sdo_14_m3_bm_0[2]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[2]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[1]  (.A(
        s_sdo_14_m3[1]), .B(s_sdo[0]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[1]));
    CFG4 #( .INIT(16'h6F06) )  \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO2  (
        .A(s_r_adc_chnls_4_samp[2]), .B(s_r_adc_chnls_4_samp[1]), .C(
        s_channel_cnt[2]), .D(CO1), .Y(un22_s_r_sck));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[2]  (.A(VCC), .B(
        s_r_clock_count[2]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[1]), .S(s_r_clock_count_s[2]), .Y(
        s_r_clock_count_cry_Y[2]), .FCO(s_r_clock_count_cry[2]));
    SLE \s_r_adc_data[12]  (.D(s_r_adc_data_4[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[12]));
    SLE \s_r_adc_data[1]  (.D(s_r_adc_data_4[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[1]));
    CFG4 #( .INIT(16'hB931) )  \SCK_GEN_PROC.s_r_sck_10_7_am  (.A(
        s_r_sck_sel[1]), .B(s_r_sck_10_7_am_1_1), .C(
        s_r_clock_count[6]), .D(s_r_clock_count[2]), .Y(
        s_r_sck_10_7_am));
    SLE \s_sdo[10]  (.D(s_sdo_14[10]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[10]));
    CFG3 #( .INIT(8'h10) )  un1_s_sdo_1_sqmuxa_1 (.A(s_channel_cnt[1]), 
        .B(s_channel_cnt[2]), .C(un1_s_sdo_1_sqmuxa_1_tz_Z), .Y(
        un1_s_sdo_1_sqmuxa_1_0));
    SLE \result_ch2_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[8]));
    CFG2 #( .INIT(4'h2) )  \ADC_FSM_NS_PROC.un1_s_r_sck  (.A(
        A0_ADC_SCK_O_c), .B(s_r_sck_Z), .Y(un1_s_r_sck));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[3]  (.A(VCC), .B(
        s_r_clock_count[3]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[2]), .S(s_r_clock_count_s[3]), .Y(
        s_r_clock_count_cry_Y[3]), .FCO(s_r_clock_count_cry[3]));
    SLE \result_ch3_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[11]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[5]  (.A(
        s_sdo_14_m3_am_0[5]), .B(s_sdo_14_m3_bm_0[5]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[5]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[14]  (
        .A(apb3_if_0_adc_channel_ch2_o[14]), .B(
        apb3_if_0_adc_channel_ch0_o[14]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[14]));
    CFG3 #( .INIT(8'h60) )  \s_r_sck_count_RNO[1]  (.A(
        s_r_sck_count[1]), .B(s_r_sck_count[0]), .C(present_state[1]), 
        .Y(N_2162_i_0));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[3]  (.A(
        s_sdo_14_m3[3]), .B(s_sdo[2]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[3]));
    SLE \s_r_adc_chnls_4_samp[2]  (.D(
        apb3_if_0_adc_control_reg_val_o[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_adc_chnls_4_samp[2]));
    SLE \s_sdo[8]  (.D(s_sdo_14[8]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[8]));
    SLE \result_ch1_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[3]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[8]  (.A(
        s_sdo_14_m3_am_0[8]), .B(s_sdo_14_m3_bm_0[8]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[8]));
    CFG3 #( .INIT(8'h23) )  \next_state_0_i[4]  (.A(
        SEQ_CONTROLLER_1_adc_start_o), .B(
        s_r_adc_results_ready_1_sqmuxa_1), .C(present_state[4]), .Y(
        next_state_i_0[4]));
    CFG3 #( .INIT(8'h14) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[0]  (.A(
        present_state[4]), .B(s_channel_cnt[0]), .C(
        s_channel_cnt_0_sqmuxa_Z), .Y(s_channel_cnt_5[0]));
    SLE \result_ch2_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[9]));
    SLE \result_ch1_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[7]));
    CFG4 #( .INIT(16'h5557) )  \present_state_ns_o4[3]  (.A(
        s_r_sck_count[4]), .B(s_r_sck_count[3]), .C(s_r_sck_count[2]), 
        .D(s_r_sck_count[1]), .Y(un13_s_r_sck));
    SLE \s_r_adc_data[3]  (.D(s_r_adc_data_4[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[3]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[0]  (.A(
        apb3_if_0_adc_channel_ch2_o[0]), .B(
        apb3_if_0_adc_channel_ch0_o[0]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm[0]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[6]  (.A(
        s_sdo_14_m3[6]), .B(s_sdo[5]), .C(A0_ADC_CS_O_c), .Y(
        s_sdo_14[6]));
    CFG4 #( .INIT(16'hB931) )  \SCK_GEN_PROC.s_r_sck_10_7_bm  (.A(
        s_r_sck_sel[1]), .B(s_r_sck_10_7_bm_1_1), .C(
        s_r_clock_count[7]), .D(s_r_clock_count[3]), .Y(
        s_r_sck_10_7_bm));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[13]  
        (.A(apb3_if_0_adc_channel_ch1_o[13]), .B(
        apb3_if_0_adc_channel_ch3_o[13]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[13]));
    SLE \s_sdo[14]  (.D(s_sdo_14[14]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[14]));
    SLE \result_ch2_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[7]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[12]  
        (.A(apb3_if_0_adc_channel_ch1_o[12]), .B(
        apb3_if_0_adc_channel_ch3_o[12]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[12]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[6]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[5]), .Y(s_r_adc_data_4[6]));
    SLE \result_ch1_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[0]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[3]  (.A(
        s_sdo_14_m3_am_0[3]), .B(s_sdo_14_m3_bm_0[3]), .C(s_sdo_14_sm1)
        , .Y(s_sdo_14_m3[3]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[5]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[4]), .Y(s_r_adc_data_4[5]));
    CFG3 #( .INIT(8'h0E) )  un1_s_sdo_1_sqmuxa_1_tz (.A(
        s_r_adc_chnls_4_samp[1]), .B(s_r_adc_chnls_4_samp[0]), .C(
        s_r_adc_chnls_4_samp[2]), .Y(un1_s_sdo_1_sqmuxa_1_tz_Z));
    SLE \s_r_sck_sel[1]  (.D(apb3_if_0_adc_control_reg_val_o[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_sck_sel[1]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[2]  (.A(
        apb3_if_0_adc_channel_ch2_o[2]), .B(
        apb3_if_0_adc_channel_ch0_o[2]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[2]));
    SLE \s_r_adc_data[0]  (.D(s_r_adc_data_4[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[0]));
    SLE \result_ch3_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[8]));
    CFG2 #( .INIT(4'h8) )  \CHANNEL_CNT_PROC.s_channel_cnt_5_RNO[2]  (
        .A(s_channel_cnt_0_sqmuxa_Z), .B(s_channel_cnt[0]), .Y(CO0));
    CFG4 #( .INIT(16'h4000) )  s_r_sck_count_0_sqmuxa (.A(s_r_sck_Z), 
        .B(present_state[1]), .C(A0_ADC_SCK_O_c), .D(un13_s_r_sck), .Y(
        s_r_sck_count_0_sqmuxa_Z));
    SLE \s_r_clock_count[1]  (.D(s_r_clock_count_s[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[1]));
    SLE \s_r_clock_count[0]  (.D(s_r_clock_count_s[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[0]));
    SLE adc_sdo_dly (.D(s_sdo[15]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(adc_sdo_dly_Z));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[8]  (.A(
        apb3_if_0_adc_channel_ch2_o[8]), .B(
        apb3_if_0_adc_channel_ch0_o[8]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[8]));
    CFG2 #( .INIT(4'h1) )  result_ch3_o_1_sqmuxa_0 (.A(
        s_r_adc_data[14]), .B(s_r_adc_data[15]), .Y(
        result_ch3_o_1_sqmuxa_0_Z));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[7]  (.A(
        apb3_if_0_adc_channel_ch2_o[7]), .B(
        apb3_if_0_adc_channel_ch0_o[7]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[7]));
    SLE \s_sdo[3]  (.D(s_sdo_14[3]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[3]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[4]  (.A(
        apb3_if_0_adc_channel_ch2_o[4]), .B(
        apb3_if_0_adc_channel_ch0_o[4]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[4]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[14]  
        (.A(apb3_if_0_adc_channel_ch1_o[14]), .B(
        apb3_if_0_adc_channel_ch3_o[14]), .C(un1_s_sdo_1_sqmuxa_1_0), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am_0[14]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[8]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[7]), .Y(s_r_adc_data_4[8]));
    CFG2 #( .INIT(4'h4) )  \s_r_adc_data_RNO[14]  (.A(A0_ADC_CS_O_c), 
        .B(s_r_adc_data[13]), .Y(N_2164_i_0));
    SLE \s_r_sck_count[2]  (.D(s_r_sck_count_n2_Z), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[2]));
    SLE \result_ch2_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch2_o[1]));
    SLE \s_r_adc_data[9]  (.D(s_r_adc_data_4[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[9]));
    SLE \result_ch1_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[2]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[11]  (
        .A(apb3_if_0_adc_channel_ch2_o[11]), .B(
        apb3_if_0_adc_channel_ch0_o[11]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[11]));
    SLE \s_channel_cnt[1]  (.D(s_channel_cnt_5[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_channel_cnt[1])
        );
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[6]  (.A(
        apb3_if_0_adc_channel_ch2_o[6]), .B(
        apb3_if_0_adc_channel_ch0_o[6]), .C(un1_s_sdo_0_sqmuxa_Z), .Y(
        s_sdo_14_m3_bm_0[6]));
    SLE \result_ch0_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[11]));
    SLE \s_r_clock_count[7]  (.D(s_r_clock_count_s[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[7]));
    SLE sck_o (.D(s_r_sck_Z), .CLK(MC_System_0_FIC_0_CLK), .EN(VCC), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(A0_ADC_SCK_O_c));
    
endmodule


module 
        work_apb3_if_apb3_if_32_12_12_6_18_2_g_APB3_IF_DATA_WIDTHg_CONST_WIDTHg_ADC_OUT_WIDTHg_ADC_CONFIG_REG_WIDTHg_STD_IO_WIDTH(
        
       apb3_if_0_idq_pi_ki_o_0,
       MC_System_0_AMBA_SLAVE_1_PWDATA,
       apb3_if_0_idq_pi_kp_o,
       apb3_if_0_olmng_dv_o,
       apb3_if_0_olmng_iq_ref_in_o,
       apb3_if_0_olmng_theta_factor_o,
       apb3_if_0_pwm_dead_time_val_o,
       apb3_if_0_pwm_delay_time_val_o,
       apb3_if_0_pwm_gain_val_o,
       apb3_if_0_pwm_period_val_o,
       apb3_if_0_rate_limit_rate_cnt_o,
       apb3_if_0_rate_limit_ref_in_o,
       apb3_if_0_rate_limit_slew_cnt_o,
       apb3_if_0_seq_cntl_cl_omega_o,
       apb3_if_0_speed_pi_ki_o,
       apb3_if_0_filter_factor_bemf_o,
       apb3_if_0_auto_restart_no_o,
       apb3_if_0_speed_pi_kp_o,
       apb3_if_0_adc_control_reg_val_o,
       apb3_if_0_seq_cntl_config_o,
       apb3_if_0_filter_factor_omega_o,
       apb3_if_0_adc_channel_ch0_o,
       apb3_if_0_adc_channel_ch1_o,
       apb3_if_0_adc_channel_ch2_o,
       apb3_if_0_adc_channel_ch3_o,
       apb3_if_0_Ls_by_Ts_pu_o,
       apb3_if_0_Rs_pu_o,
       apb3_if_0_adc_oc_thresh_o,
       apb3_if_0_adc_scale_val_o,
       apb3_if_0_angle_ki_o,
       apb3_if_0_angle_kp_o,
       prdata_o_1_0_1_d0,
       prdata_o_1_4,
       ADC_SCALING_1_ib_adc_o,
       ADC_SCALING_1_ia_adc_o,
       FOC_TRANSFORMS_0_iq_o,
       FOC_TRANSFORMS_0_id_o,
       RATE_LIMITER_0_rl_out_o,
       BLDC_ESTIMATOR_1_ealpha_o,
       BLDC_ESTIMATOR_1_theta_o,
       OLMNG_1_theta_o,
       adc_interface_0_result_ch1_o,
       adc_interface_0_result_ch0_o,
       adc_measurements_0_adc_result_ch3_o,
       adc_measurements_0_adc_result_ch2_o,
       prdata_o_1_0_a2_12_0,
       MC_System_0_AMBA_SLAVE_1_PADDR,
       prdata_o_1_0_a2_10_0,
       prdata_o_1_0_a2_7_0,
       BLDC_ESTIMATOR_1_ebeta_filtered_o,
       BLDC_ESTIMATOR_1_ebeta_o,
       BLDC_ESTIMATOR_0_speed_filtered_o,
       FOC_TRANSFORMS_0_valpha_o,
       SPEED_ID_IQ_PI_1_iq_pi_output_o,
       net_189,
       BLDC_ESTIMATOR_1_ealpha_filtered_o,
       SPEED_ID_IQ_PI_1_id_pi_output_o,
       FOC_TRANSFORMS_0_ibeta_o,
       FOC_TRANSFORMS_0_ialpha_o,
       FOC_TRANSFORMS_0_vbeta_o,
       BLDC_ESTIMATOR_1_pll_pi_out_o,
       prdata_o_1_24_3,
       prdata_o_1_3,
       prdata_o_1_0_2,
       prdata_o_1_0_0,
       SEQ_CONTROLLER_1_state_o,
       prdata_o_1_24_2,
       prdata_o_1_12_3,
       prdata_o_1_12_2,
       prdata_o_1_12_1,
       prdata_o_1_2,
       prdata_o_1_0_1_13,
       prdata_o_1_0_1_11,
       prdata_o_1_0_1_12,
       prdata_o_1_0_1_9,
       prdata_o_1_0_1_10,
       prdata_o_1_24_4,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       apb3_if_0_stop_motor_o,
       apb3_if_0_start_motor_o,
       apb3_if_0_fault_clr_o,
       apb3_if_0_direction_config_o,
       N_202,
       N_185,
       N_2791,
       N_2779,
       N_2542,
       N_1508,
       N_1083,
       N_2606,
       N_2585,
       N_1080,
       N_1077,
       N_1014,
       N_176,
       N_1007,
       N_2522,
       N_2532,
       MC_System_0_AMBA_SLAVE_1_PWRITE,
       MC_System_0_AMBA_SLAVE_1_PENABLE,
       N_2787,
       N_2704,
       adc_channel_ch3_o_1_sqmuxa_0_a2_0_0,
       prdata_o190_0_a2_0_out,
       N_172,
       N_2660,
       N_2778,
       N_2784,
       prdata_o200_2,
       N_2470,
       N_2785,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       N_2734,
       N_2661,
       N_2728,
       N_193
    );
output [17:0] apb3_if_0_idq_pi_ki_o_0;
input  [17:0] MC_System_0_AMBA_SLAVE_1_PWDATA;
output [17:0] apb3_if_0_idq_pi_kp_o;
output [17:0] apb3_if_0_olmng_dv_o;
output [17:0] apb3_if_0_olmng_iq_ref_in_o;
output [17:0] apb3_if_0_olmng_theta_factor_o;
output [17:0] apb3_if_0_pwm_dead_time_val_o;
output [17:0] apb3_if_0_pwm_delay_time_val_o;
output [17:1] apb3_if_0_pwm_gain_val_o;
output [17:0] apb3_if_0_pwm_period_val_o;
output [17:0] apb3_if_0_rate_limit_rate_cnt_o;
output [17:0] apb3_if_0_rate_limit_ref_in_o;
output [17:0] apb3_if_0_rate_limit_slew_cnt_o;
output [17:0] apb3_if_0_seq_cntl_cl_omega_o;
output [17:0] apb3_if_0_speed_pi_ki_o;
output [3:0] apb3_if_0_filter_factor_bemf_o;
output [3:0] apb3_if_0_auto_restart_no_o;
output [17:0] apb3_if_0_speed_pi_kp_o;
output [5:0] apb3_if_0_adc_control_reg_val_o;
output [3:0] apb3_if_0_seq_cntl_config_o;
output [3:0] apb3_if_0_filter_factor_omega_o;
output [15:0] apb3_if_0_adc_channel_ch0_o;
output [15:0] apb3_if_0_adc_channel_ch1_o;
output [15:0] apb3_if_0_adc_channel_ch2_o;
output [15:0] apb3_if_0_adc_channel_ch3_o;
output [17:0] apb3_if_0_Ls_by_Ts_pu_o;
output [17:0] apb3_if_0_Rs_pu_o;
output [17:0] apb3_if_0_adc_oc_thresh_o;
output [17:0] apb3_if_0_adc_scale_val_o;
output [17:0] apb3_if_0_angle_ki_o;
output [17:0] apb3_if_0_angle_kp_o;
output prdata_o_1_0_1_d0;
output [2:2] prdata_o_1_4;
input  [17:0] ADC_SCALING_1_ib_adc_o;
input  [17:0] ADC_SCALING_1_ia_adc_o;
input  [17:0] FOC_TRANSFORMS_0_iq_o;
input  [17:0] FOC_TRANSFORMS_0_id_o;
input  [17:0] RATE_LIMITER_0_rl_out_o;
input  [17:0] BLDC_ESTIMATOR_1_ealpha_o;
input  [17:0] BLDC_ESTIMATOR_1_theta_o;
input  [17:0] OLMNG_1_theta_o;
input  [11:0] adc_interface_0_result_ch1_o;
input  [11:0] adc_interface_0_result_ch0_o;
input  [11:0] adc_measurements_0_adc_result_ch3_o;
input  [11:0] adc_measurements_0_adc_result_ch2_o;
output [15:15] prdata_o_1_0_a2_12_0;
input  [11:0] MC_System_0_AMBA_SLAVE_1_PADDR;
output [15:15] prdata_o_1_0_a2_10_0;
output [3:3] prdata_o_1_0_a2_7_0;
input  [17:0] BLDC_ESTIMATOR_1_ebeta_filtered_o;
input  [17:0] BLDC_ESTIMATOR_1_ebeta_o;
input  [17:0] BLDC_ESTIMATOR_0_speed_filtered_o;
input  [17:0] FOC_TRANSFORMS_0_valpha_o;
input  [17:0] SPEED_ID_IQ_PI_1_iq_pi_output_o;
input  [17:0] net_189;
input  [17:0] BLDC_ESTIMATOR_1_ealpha_filtered_o;
input  [17:0] SPEED_ID_IQ_PI_1_id_pi_output_o;
input  [17:0] FOC_TRANSFORMS_0_ibeta_o;
input  [17:0] FOC_TRANSFORMS_0_ialpha_o;
input  [17:0] FOC_TRANSFORMS_0_vbeta_o;
input  [17:0] BLDC_ESTIMATOR_1_pll_pi_out_o;
output [1:1] prdata_o_1_24_3;
output [3:2] prdata_o_1_3;
output [16:12] prdata_o_1_0_2;
output [16:12] prdata_o_1_0_0;
input  [3:0] SEQ_CONTROLLER_1_state_o;
output [1:1] prdata_o_1_24_2;
output [11:4] prdata_o_1_12_3;
output [11:4] prdata_o_1_12_2;
output [11:4] prdata_o_1_12_1;
output [3:2] prdata_o_1_2;
output prdata_o_1_0_1_13;
output prdata_o_1_0_1_11;
output prdata_o_1_0_1_12;
output prdata_o_1_0_1_9;
output prdata_o_1_0_1_10;
output [1:1] prdata_o_1_24_4;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;
output apb3_if_0_stop_motor_o;
output apb3_if_0_start_motor_o;
output apb3_if_0_fault_clr_o;
output apb3_if_0_direction_config_o;
input  N_202;
output N_185;
output N_2791;
output N_2779;
output N_2542;
output N_1508;
output N_1083;
output N_2606;
output N_2585;
output N_1080;
output N_1077;
output N_1014;
output N_176;
output N_1007;
output N_2522;
output N_2532;
input  MC_System_0_AMBA_SLAVE_1_PWRITE;
input  MC_System_0_AMBA_SLAVE_1_PENABLE;
output N_2787;
output N_2704;
input  adc_channel_ch3_o_1_sqmuxa_0_a2_0_0;
input  prdata_o190_0_a2_0_out;
input  N_172;
output N_2660;
output N_2778;
output N_2784;
input  prdata_o200_2;
output N_2470;
output N_2785;
input  MC_System_0_AMBA_SLAVE_0_PSELx;
output N_2734;
output N_2661;
output N_2728;
input  N_193;

    wire [3:3] prdata_o_1_0_1;
    wire [2:2] prdata_o_1_0;
    wire [2:2] prdata_o_1_4_1;
    wire [17:0] prdata_o_1_16_i_m2_bm;
    wire [17:0] prdata_o_1_16_i_m2_am;
    wire [17:0] prdata_o_1_14_i_m2_1_1;
    wire [17:0] prdata_o_1_15_i_m2_1_1;
    wire [11:0] prdata_o_1_13_i_m2_1_1;
    wire [3:3] prdata_o_1_13_i_m2_i_m2_1_1;
    wire [17:0] prdata_o_1_17_i_m2_am;
    wire [17:0] prdata_o_1_17_i_m2_bm;
    wire [3:3] prdata_o_1_17_i_m2_i_m2_am;
    wire [3:3] prdata_o_1_17_i_m2_i_m2_bm;
    wire [15:15] prdata_o_1_0_a2_9_0;
    wire [10:4] prdata_o_1_12_0;
    wire [1:1] prdata_o_1_24_1;
    wire VCC, idq_pi_ki_o_1_sqmuxa, GND, idq_pi_kp_o_1_sqmuxa, 
        olmng_dv_o_1_sqmuxa, olmng_iq_ref_in_o_1_sqmuxa, 
        olmng_theta_factor_o_1_sqmuxa, pwm_dead_time_val_o_1_sqmuxa, 
        pwm_delay_time_val_o_1_sqmuxa, pwm_gain_val_o_1_sqmuxa, 
        pwm_period_val_o_1_sqmuxa, rate_limit_rate_cnt_o_1_sqmuxa, 
        rate_limit_ref_in_o_1_sqmuxa, rate_limit_slew_cnt_o_1_sqmuxa, 
        seq_cntl_cl_omega_o_1_sqmuxa, speed_pi_ki_o_1_sqmuxa, 
        speed_pi_kp_o_1_sqmuxa, filter_factor_omega_o_1_sqmuxa, 
        filter_factor_bemf_o_1_sqmuxa, auto_restart_no_o_1_sqmuxa, 
        adc_channel_ch0_o_1_sqmuxa, adc_control_reg_val_o_1_sqmuxa, 
        seq_cntl_config_o_1_sqmuxa, adc_channel_ch1_o_1_sqmuxa, 
        adc_channel_ch2_o_1_sqmuxa, adc_channel_ch3_o_1_sqmuxa, 
        Ls_by_Ts_pu_o_0_sqmuxa, Rs_pu_o_1_sqmuxa, 
        adc_oc_thresh_o_1_sqmuxa, adc_scale_val_o_1_sqmuxa, 
        angle_ki_o_1_sqmuxa, angle_kp_o_1_sqmuxa, 
        stop_motor_o_1_sqmuxa, start_motor_o_1_sqmuxa, 
        fault_clr_o_1_sqmuxa, direction_config_o_1_sqmuxa, 
        prdata_m2_e_3_0_Z, prdata_m2_e_0_3, N_939_i, prdata_m3_e_0_0_Z, 
        prdata_o_1_12_a2_7_out, prdata_m2_e_0_3_1, N_2775, N_2529, 
        N_1535, N_1534, N_1090, N_1026, N_1025, N_1024, N_2574, N_1510, 
        N_1509, N_1507, N_1506, N_1086, N_1055, N_1054, N_1088, N_1087, 
        N_2528, N_1234, N_2527, N_2562, N_2601, N_2600, N_1027, N_2595, 
        N_2594, N_2536, N_1468, N_1455, N_1084, N_1011, N_1089, N_2561, 
        N_2560, N_1056, N_1085, N_1153, N_1015, N_1091, N_1057, N_1053, 
        N_2541, N_1154, N_1052, N_1012, N_1079, N_1082, N_2584, N_2582, 
        N_2581, N_2580, N_2573, N_2559, N_2558, N_2535, N_1435, N_1416, 
        N_1160, N_1152, N_1081, N_1078, N_1051, N_1050, N_1049, N_1048, 
        N_1047, N_1046, N_1023, N_1022, N_1021, N_1020, N_1013, N_2557, 
        N_2553, N_2579, N_2865, N_1004, N_2534, N_1289, N_1005, N_1159, 
        N_2869, N_1018, N_2801, 
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_0_Z, N_2798, N_1008, 
        N_1030, N_1031, N_1042, N_1043, N_1061, N_1062, N_1063, N_1073, 
        N_1074, N_1075, N_2523, N_1097, N_1146, N_1147, N_1155, N_2531, 
        N_1512, N_1513, N_1514, N_1525, N_1526, N_2550, N_2555, N_2564, 
        N_2570, N_2610, direction_config_o_1_sqmuxa_0_a2_3_1_Z, 
        prdata_m3_e_0_1_Z, prdata_m3_e_0_0_0, N_2759, N_2802, N_2796, 
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_3_Z, N_938, N_942, N_2766, 
        N_2786, N_2794, N_2725, N_2674, N_2671, N_2789, N_2788, N_1094;
    
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[11]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[11]), .Y(
        prdata_o_1_17_i_m2_bm[11]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_24_3_RNO_1[1]  (.A(
        BLDC_ESTIMATOR_1_theta_o[1]), .B(OLMNG_1_theta_o[1]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[1]));
    SLE \idq_pi_ki_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[6]));
    SLE \rate_limit_rate_cnt_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[16]));
    SLE \adc_channel_ch2_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch2_o[14]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[14]  (.A(
        prdata_o_1_16_i_m2_am[14]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[14]), .Y(N_1049));
    SLE \adc_oc_thresh_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[13]));
    SLE \rate_limit_slew_cnt_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[8]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_0_cZ[12]  (.A(N_1063), .B(
        N_1075), .C(N_2778), .D(N_2784), .Y(prdata_o_1_0_0[12]));
    SLE \olmng_theta_factor_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[4]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[15]  (.A(
        prdata_o_1_17_i_m2_am[15]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[15]), .Y(N_1020));
    SLE \adc_channel_ch3_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch3_o[15]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_12_2_RNO[8]  (.A(
        RATE_LIMITER_0_rl_out_o[8]), .B(BLDC_ESTIMATOR_1_ealpha_o[8]), 
        .C(prdata_o_1_15_i_m2_1_1[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_2574));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_12_2_RNO_0[5]  (.A(
        RATE_LIMITER_0_rl_out_o[5]), .B(BLDC_ESTIMATOR_1_ealpha_o[5]), 
        .C(prdata_o_1_15_i_m2_1_1[5]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1534));
    SLE \speed_pi_kp_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[3]));
    SLE \idq_pi_kp_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[14]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[7]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[7]), .Y(prdata_o_1_16_i_m2_am[7]));
    CFG2 #( .INIT(4'h1) )  \prdata_o_1_12_a2_10_2[11]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(N_176));
    SLE \speed_pi_ki_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[3]));
    SLE \olmng_iq_ref_in_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_iq_ref_in_o[11]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_12_1_cZ[4]  (.A(N_1011), .B(
        N_1160), .C(N_2791), .D(N_2779), .Y(prdata_o_1_12_1[4]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[7]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[7]), .Y(N_1043));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_0_2_RNO_1[15]  (.A(
        BLDC_ESTIMATOR_1_theta_o[15]), .B(OLMNG_1_theta_o[15]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[15]));
    SLE \idq_pi_kp_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[12]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_24_3_RNO_0[1]  (.A(
        RATE_LIMITER_0_rl_out_o[1]), .B(BLDC_ESTIMATOR_1_ealpha_o[1]), 
        .C(prdata_o_1_15_i_m2_1_1[1]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_2527));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[12]  (.A(
        prdata_o_1_17_i_m2_am[12]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[12]), .Y(N_1048));
    SLE \adc_channel_ch0_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[3]));
    SLE \angle_ki_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[14]));
    SLE \adc_channel_ch0_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch0_o[15]));
    SLE \angle_ki_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[7]));
    SLE \speed_pi_ki_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[6]));
    SLE \pwm_period_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[10]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[14]  (.A(
        prdata_o_1_17_i_m2_am[14]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[14]), .Y(N_1046));
    SLE \rate_limit_ref_in_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[7]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_12_1_RNO[10]  (.A(
        adc_interface_0_result_ch1_o[10]), .B(
        adc_interface_0_result_ch0_o[10]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[10]), .Y(N_1509));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[6]  (.A(
        prdata_o_1_16_i_m2_am[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[6]), .Y(N_2535));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_12_2_RNO[9]  (.A(
        RATE_LIMITER_0_rl_out_o[9]), .B(BLDC_ESTIMATOR_1_ealpha_o[9]), 
        .C(prdata_o_1_15_i_m2_1_1[9]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_2560));
    SLE \pwm_period_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[6]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_12_1_RNO_0[11]  (.A(
        adc_measurements_0_adc_result_ch3_o[11]), .B(
        adc_measurements_0_adc_result_ch2_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[11]));
    SLE \idq_pi_kp_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[13]));
    SLE \Ls_by_Ts_pu_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[12]));
    CFG4 #( .INIT(16'h2000) )  idq_pi_ki_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(N_2794), .D(N_2798), .Y(
        idq_pi_ki_o_1_sqmuxa));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_12_2_RNO_0[7]  (.A(
        BLDC_ESTIMATOR_1_theta_o[7]), .B(OLMNG_1_theta_o[7]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[7]));
    CFG4 #( .INIT(16'h0400) )  filter_factor_bemf_o_1_sqmuxa_0_a2_1_3 
        (.A(MC_System_0_AMBA_SLAVE_1_PADDR[10]), .B(
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_0_Z), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[0]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), .Y(
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_3_Z));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_12_1_RNO_1[10]  (.A(
        adc_measurements_0_adc_result_ch3_o[10]), .B(
        adc_measurements_0_adc_result_ch2_o[10]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[10]));
    SLE \Ls_by_Ts_pu_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[16]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[6]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[6]), .Y(N_1526));
    SLE \rate_limit_rate_cnt_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[17]));
    CFG2 #( .INIT(4'h6) )  \prdata_o_1_0_x2[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(N_939_i));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_2_cZ[10]  (.A(N_1455), 
        .B(N_1416), .C(N_2785), .D(N_2786), .Y(prdata_o_1_12_2[10]));
    SLE \adc_channel_ch2_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[9]));
    SLE \pwm_delay_time_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[1]));
    SLE \idq_pi_ki_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[15]));
    SLE \speed_pi_kp_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[15]));
    SLE \idq_pi_kp_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[9]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_12_1_RNO[9]  (.A(
        adc_interface_0_result_ch1_o[9]), .B(
        adc_interface_0_result_ch0_o[9]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[9]), .Y(N_2562));
    SLE \idq_pi_kp_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[8]));
    SLE \pwm_dead_time_val_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[9]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_24_1[1]  (.A(N_2541), .B(
        N_2584), .C(N_2791), .D(N_2779), .Y(prdata_o_1_24_1[1]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[17]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[17]), .Y(
        prdata_o_1_17_i_m2_bm[17]));
    CFG4 #( .INIT(16'h0002) )  prdata_m3_e_0_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[1]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .Y(prdata_m3_e_0_0_0));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[4]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[4]), .Y(prdata_o_1_16_i_m2_bm[4]));
    SLE \olmng_iq_ref_in_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[0]));
    SLE \angle_kp_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[4]));
    SLE \rate_limit_slew_cnt_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[5]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_0_cZ[14]  (.A(N_1061), .B(
        N_1073), .C(N_2778), .D(N_2784), .Y(prdata_o_1_0_0[14]));
    CFG4 #( .INIT(16'hAC00) )  \prdata_o_1_0_RNO[3]  (.A(
        FOC_TRANSFORMS_0_vbeta_o[3]), .B(
        BLDC_ESTIMATOR_1_pll_pi_out_o[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(prdata_o_1_12_a2_7_out), 
        .Y(prdata_m2_e_3_0_Z));
    SLE \Rs_pu_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[5]));
    SLE direction_config_o (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(direction_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_direction_config_o));
    CFG2 #( .INIT(4'h8) )  seq_cntl_config_o_1_sqmuxa_0_a2_1_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_185));
    SLE \idq_pi_kp_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[11]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_12_1_cZ[9]  (.A(N_2559), .B(
        N_2562), .C(N_2779), .D(N_2791), .Y(prdata_o_1_12_1[9]));
    SLE \adc_channel_ch3_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch3_o[13]));
    SLE \Ls_by_Ts_pu_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[11]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_0_2_RNO_0[16]  (.A(
        ADC_SCALING_1_ib_adc_o[16]), .B(ADC_SCALING_1_ia_adc_o[16]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[16]), .Y(N_1088));
    SLE \pwm_delay_time_val_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[13]));
    CFG4 #( .INIT(16'hFEEE) )  \prdata_o_1_12_3_cZ[11]  (.A(N_2674), 
        .B(N_2671), .C(N_1089), .D(N_193), .Y(prdata_o_1_12_3[11]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_2_cZ[5]  (.A(N_2579), .B(
        N_1534), .C(N_2786), .D(N_2785), .Y(prdata_o_1_12_2[5]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_0_2_RNO_0[13]  (.A(
        ADC_SCALING_1_ib_adc_o[13]), .B(ADC_SCALING_1_ia_adc_o[13]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[13]), .Y(N_1056));
    SLE \olmng_dv_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[6]));
    SLE \angle_kp_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[2]));
    SLE \angle_ki_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[13]));
    SLE \speed_pi_ki_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[15]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_3_i_m2[3]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[3]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[3]), .Y(N_2869));
    SLE \adc_control_reg_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_control_reg_val_o[3]));
    SLE \adc_channel_ch1_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[7]));
    SLE \filter_factor_omega_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(filter_factor_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_filter_factor_omega_o[3]));
    CFG4 #( .INIT(16'h0800) )  \prdata_o_1_12_a2_6[11]  (.A(N_942), .B(
        N_202), .C(MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        prdata_o_1_12_a2_7_out), .Y(N_2791));
    SLE \adc_channel_ch0_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch0_o[13]));
    SLE \pwm_gain_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[8]));
    SLE \rate_limit_rate_cnt_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[11]));
    SLE \pwm_gain_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[17]));
    SLE \pwm_delay_time_val_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[7]));
    SLE \seq_cntl_cl_omega_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[0]));
    SLE \adc_scale_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[5]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[9]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[9]), .Y(N_2564));
    SLE \rate_limit_rate_cnt_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[8]));
    SLE \adc_channel_ch2_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[5]));
    CFG3 #( .INIT(8'hEA) )  \prdata_o_1_12_3_cZ[10]  (.A(
        prdata_o_1_12_0[10]), .B(N_2536), .C(N_193), .Y(
        prdata_o_1_12_3[10]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_24_1_RNO_0[1]  (.A(
        adc_measurements_0_adc_result_ch3_o[1]), .B(
        adc_measurements_0_adc_result_ch2_o[1]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[1]));
    CFG2 #( .INIT(4'h1) )  prdata_m2_e_3_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(prdata_m3_e_0_0_Z));
    SLE \rate_limit_slew_cnt_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[17]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_12_2_RNO[5]  (.A(N_2557), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(N_2553), .Y(N_2579));
    SLE \olmng_theta_factor_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[16]));
    CFG3 #( .INIT(8'h80) )  adc_scale_val_o_1_sqmuxa_0_a2_0_a2 (.A(
        N_2789), .B(N_2801), .C(N_2766), .Y(adc_scale_val_o_1_sqmuxa));
    SLE \speed_pi_kp_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[17]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[17]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[17]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[17]), .Y(prdata_o_1_16_i_m2_am[17]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_12_3_RNO_0[10]  (.A(
        FOC_TRANSFORMS_0_iq_o[10]), .B(FOC_TRANSFORMS_0_id_o[10]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[10]));
    SLE \pwm_period_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[15]));
    CFG3 #( .INIT(8'h80) )  idq_pi_kp_o_1_sqmuxa_0_a2_2_a2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(N_2801), .C(N_2794), .Y(
        idq_pi_kp_o_1_sqmuxa));
    SLE \pwm_delay_time_val_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[8]));
    CFG4 #( .INIT(16'h0810) )  \prdata_o_1_12_o2[11]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(N_942));
    CFG4 #( .INIT(16'hAC00) )  \prdata_o_1_0_a2_4[17]  (.A(
        FOC_TRANSFORMS_0_ibeta_o[17]), .B(
        FOC_TRANSFORMS_0_ialpha_o[17]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(N_2778), .Y(N_2661));
    SLE \adc_oc_thresh_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[2]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[8]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[8]), .Y(prdata_o_1_16_i_m2_bm[8]));
    SLE \adc_channel_ch3_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[7]));
    CFG3 #( .INIT(8'h02) )  \prdata_o_1_0_a2_12_0_cZ[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .Y(
        prdata_o_1_0_a2_12_0[15]));
    SLE \Rs_pu_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[0]));
    CFG3 #( .INIT(8'hEA) )  \prdata_o_1_12_3_cZ[4]  (.A(
        prdata_o_1_12_0[4]), .B(N_2601), .C(N_193), .Y(
        prdata_o_1_12_3[4]));
    SLE \adc_channel_ch3_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[5]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[0]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[0]), .Y(prdata_o_1_16_i_m2_bm[0]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_0_2_RNO_1[16]  (.A(
        BLDC_ESTIMATOR_1_theta_o[16]), .B(OLMNG_1_theta_o[16]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[16]));
    SLE \filter_factor_omega_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(filter_factor_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_filter_factor_omega_o[1]));
    SLE \pwm_delay_time_val_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[11]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_0_2_RNO_1[13]  (.A(
        BLDC_ESTIMATOR_1_theta_o[13]), .B(OLMNG_1_theta_o[13]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[13]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_24_2_cZ[1]  (.A(N_2581), .B(
        SEQ_CONTROLLER_1_state_o[1]), .C(N_2785), .D(N_2470), .Y(
        prdata_o_1_24_2[1]));
    SLE \seq_cntl_cl_omega_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[10]));
    SLE \pwm_delay_time_val_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[10]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_12_2_RNO_1[4]  (.A(
        BLDC_ESTIMATOR_1_theta_o[4]), .B(OLMNG_1_theta_o[4]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[4]));
    SLE \pwm_delay_time_val_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[15]));
    CFG3 #( .INIT(8'h7F) )  \prdata_o_1_0_1[3]  (.A(N_939_i), .B(N_185)
        , .C(prdata_m3_e_0_0_Z), .Y(prdata_o_1_0_1[3]));
    SLE \speed_pi_ki_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[7]));
    SLE \angle_ki_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[6]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_RNO_0[3]  (.A(
        prdata_m3_e_0_0_Z), .B(prdata_o_1_12_a2_7_out), .C(
        prdata_m2_e_0_3_1), .D(N_2775), .Y(prdata_m2_e_0_3));
    SLE \pwm_gain_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[2]));
    SLE \adc_oc_thresh_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[12]));
    SLE \rate_limit_ref_in_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[9]));
    SLE \angle_ki_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[12]));
    SLE \olmng_iq_ref_in_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_iq_ref_in_o[10]));
    SLE \speed_pi_kp_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[10]));
    SLE \rate_limit_rate_cnt_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[3]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_12_1_cZ[6]  (.A(N_1510), .B(
        N_2535), .C(N_2791), .D(N_2779), .Y(prdata_o_1_12_1[6]));
    VCC VCC_Z (.Y(VCC));
    SLE \olmng_iq_ref_in_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[6]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[0]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[0]), .Y(N_1007));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_2_cZ[7]  (.A(N_1025), .B(
        N_1021), .C(N_2785), .D(N_2786), .Y(prdata_o_1_12_2[7]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[12]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[12]), .Y(
        prdata_o_1_17_i_m2_bm[12]));
    SLE \Rs_pu_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[12]));
    SLE \idq_pi_ki_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[14]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_12_3_RNO[11]  (.A(
        ADC_SCALING_1_ib_adc_o[11]), .B(ADC_SCALING_1_ia_adc_o[11]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[11]), .Y(N_1089));
    SLE \speed_pi_ki_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[17]));
    SLE \pwm_gain_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[15]));
    SLE \seq_cntl_cl_omega_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[7]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_12_1_RNO[5]  (.A(
        adc_interface_0_result_ch1_o[5]), .B(
        adc_interface_0_result_ch0_o[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[5]), .Y(N_1012));
    SLE \filter_factor_bemf_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(filter_factor_bemf_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_filter_factor_bemf_o[1]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_1_cZ[10]  (.A(N_1509), 
        .B(N_2534), .C(N_2779), .D(N_2791), .Y(prdata_o_1_12_1[10]));
    SLE \idq_pi_ki_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[12]));
    SLE \Rs_pu_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[4]));
    SLE \pwm_dead_time_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[5]));
    CFG4 #( .INIT(16'h2000) )  olmng_iq_ref_in_o_1_sqmuxa_0_a2 (.A(
        N_2798), .B(MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(N_2789), .D(
        N_2787), .Y(olmng_iq_ref_in_o_1_sqmuxa));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[7]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[7]), .Y(
        prdata_o_1_17_i_m2_bm[7]));
    SLE \rate_limit_rate_cnt_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[7]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[8]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[8]), .Y(
        prdata_o_1_17_i_m2_am[8]));
    SLE \Rs_pu_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[14]));
    SLE \olmng_dv_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[2]));
    SLE \idq_pi_ki_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[13]));
    SLE \rate_limit_rate_cnt_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[0]));
    SLE \olmng_dv_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[16]));
    SLE \rate_limit_ref_in_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[15]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[16]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[16]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[16]), .Y(N_2523));
    SLE \rate_limit_ref_in_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[5]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_3_i_m2[10]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[10]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[10]), .Y(N_2865));
    SLE \pwm_delay_time_val_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[12]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[15]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[15]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[15]), .Y(
        prdata_o_1_17_i_m2_am[15]));
    SLE \seq_cntl_cl_omega_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[12]));
    CFG4 #( .INIT(16'hAA08) )  \prdata_o_1_0[3]  (.A(N_202), .B(
        prdata_m2_e_3_0_Z), .C(prdata_o_1_0_1[3]), .D(prdata_m2_e_0_3), 
        .Y(prdata_o_1_0_1_d0));
    SLE \rate_limit_rate_cnt_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[13]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[10]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[10]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[10]), .Y(
        prdata_o_1_17_i_m2_am[10]));
    SLE \rate_limit_ref_in_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[4]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[13]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[13]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[13]), .Y(
        prdata_o_1_17_i_m2_am[13]));
    SLE \speed_pi_ki_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[10]));
    CFG3 #( .INIT(8'hEA) )  \prdata_o_1_12_3_cZ[9]  (.A(
        prdata_o_1_12_0[9]), .B(N_2561), .C(N_193), .Y(
        prdata_o_1_12_3[9]));
    SLE \idq_pi_ki_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[9]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_24_4_cZ[1]  (.A(N_1514), .B(
        N_2784), .C(N_2725), .D(prdata_o_1_24_1[1]), .Y(
        prdata_o_1_24_4[1]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_12_1_RNO_0[9]  (.A(
        adc_measurements_0_adc_result_ch3_o[9]), .B(
        adc_measurements_0_adc_result_ch2_o[9]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[9]));
    SLE \Ls_by_Ts_pu_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[9]));
    SLE \angle_kp_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[17]));
    SLE \adc_scale_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[4]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_0_2_RNO[13]  (.A(
        RATE_LIMITER_0_rl_out_o[13]), .B(BLDC_ESTIMATOR_1_ealpha_o[13])
        , .C(prdata_o_1_15_i_m2_1_1[13]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1053));
    SLE \adc_channel_ch0_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[2]));
    SLE \pwm_period_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[7]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[16]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[16]), .Y(
        prdata_o_1_17_i_m2_bm[16]));
    SLE \olmng_theta_factor_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[6]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[14]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[14]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[14]), .Y(prdata_o_1_16_i_m2_bm[14]));
    SLE \Ls_by_Ts_pu_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[1]));
    SLE \adc_channel_ch2_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[0]));
    SLE \rate_limit_ref_in_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[8]));
    SLE \rate_limit_ref_in_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[13]));
    SLE \filter_factor_omega_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(filter_factor_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_filter_factor_omega_o[2]));
    SLE \idq_pi_ki_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[5]));
    SLE \seq_cntl_cl_omega_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[5]));
    SLE \pwm_dead_time_val_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[8]));
    SLE \rate_limit_ref_in_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[16]));
    SLE \adc_channel_ch3_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[4]));
    SLE \olmng_dv_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[5]));
    SLE \adc_oc_thresh_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[7]));
    SLE \olmng_iq_ref_in_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[3]));
    SLE \Ls_by_Ts_pu_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[2]));
    SLE \rate_limit_slew_cnt_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[7]));
    CFG3 #( .INIT(8'h80) )  fault_clr_o_1_sqmuxa_0_a2 (.A(N_2789), .B(
        N_2802), .C(N_2787), .Y(fault_clr_o_1_sqmuxa));
    SLE \adc_channel_ch2_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch2_o[12]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_1[13]  (.A(N_1047), .B(
        N_1050), .C(N_2785), .D(N_2779), .Y(prdata_o_1_0_1_10));
    SLE \auto_restart_no_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(auto_restart_no_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_auto_restart_no_o[2]));
    SLE fault_clr_o (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(fault_clr_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_fault_clr_o));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[0]  (.A(
        prdata_o_1_17_i_m2_am[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[0]), .Y(N_2606));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[6]  (.A(
        prdata_o_1_17_i_m2_am[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[6]), .Y(N_1435));
    SLE \Rs_pu_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[2]));
    SLE \idq_pi_ki_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[11]));
    SLE \pwm_dead_time_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[2]));
    SLE \adc_channel_ch2_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch2_o[11]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_3_cZ[2]  (.A(N_1086), .B(
        N_1090), .C(N_193), .D(N_2786), .Y(prdata_o_1_3[2]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[7]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[7]), .Y(prdata_o_1_16_i_m2_bm[7]));
    CFG4 #( .INIT(16'h8000) )  seq_cntl_config_o_1_sqmuxa_0_a2_1_a2 (
        .A(MC_System_0_AMBA_SLAVE_1_PADDR[3]), .B(N_185), .C(N_2787), 
        .D(N_2788), .Y(seq_cntl_config_o_1_sqmuxa));
    SLE \adc_channel_ch2_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[7]));
    CFG2 #( .INIT(4'h2) )  adc_control_reg_val_o_1_sqmuxa_0_a2_2 (.A(
        N_202), .B(MC_System_0_AMBA_SLAVE_1_PADDR[7]), .Y(N_2766));
    SLE \rate_limit_slew_cnt_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[3]));
    CFG3 #( .INIT(8'h80) )  pwm_dead_time_val_o_1_sqmuxa_0_a2_0_a2 (.A(
        N_2789), .B(N_2802), .C(N_2766), .Y(
        pwm_dead_time_val_o_1_sqmuxa));
    CFG2 #( .INIT(4'h2) )  \prdata_o_1_12_a2_7_s[11]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .Y(prdata_o_1_12_a2_7_out));
    SLE \adc_channel_ch1_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch1_o[14]));
    SLE \rate_limit_slew_cnt_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[0]));
    SLE \adc_channel_ch3_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[8]));
    SLE \rate_limit_slew_cnt_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[16]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_9_i_m2[4]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[4]), .Y(N_1005));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_2_cZ[12]  (.A(N_1054), .B(
        N_1057), .C(N_193), .D(N_2786), .Y(prdata_o_1_0_2[12]));
    SLE \pwm_dead_time_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[1]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_12_3_RNO_0[6]  (.A(
        FOC_TRANSFORMS_0_iq_o[6]), .B(FOC_TRANSFORMS_0_id_o[6]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[6]));
    SLE \seq_cntl_cl_omega_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[11]));
    SLE \Ls_by_Ts_pu_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[8]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_12_2_RNO_0[4]  (.A(N_1289), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(N_1005), .Y(N_1159));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[6]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[6]), .Y(
        prdata_o_1_17_i_m2_am[6]));
    SLE \adc_channel_ch3_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[3]));
    SLE \adc_scale_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[1]));
    CFG4 #( .INIT(16'h0E40) )  \prdata_o_1_0_o2_0[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(N_938));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[14]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[14]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[14]), .Y(N_1073));
    SLE \pwm_gain_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[14]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[8]  (.A(
        prdata_o_1_16_i_m2_am[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[8]), .Y(N_1152));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_12_3_RNO_0[7]  (.A(
        FOC_TRANSFORMS_0_iq_o[7]), .B(FOC_TRANSFORMS_0_id_o[7]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[7]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_3_RNO[2]  (.A(
        RATE_LIMITER_0_rl_out_o[2]), .B(BLDC_ESTIMATOR_1_ealpha_o[2]), 
        .C(prdata_o_1_15_i_m2_1_1[2]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1086));
    SLE \angle_kp_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[8]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[2]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[2]), .Y(N_2531));
    CFG3 #( .INIT(8'hEA) )  \prdata_o_1_12_3_cZ[6]  (.A(
        prdata_o_1_12_0[6]), .B(N_1506), .C(N_193), .Y(
        prdata_o_1_12_3[6]));
    CFG4 #( .INIT(16'h0800) )  \prdata_o_1_0_a2_5[15]  (.A(
        prdata_m3_e_0_0_0), .B(prdata_m3_e_0_1_Z), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(N_2775), .Y(N_2778));
    SLE \Ls_by_Ts_pu_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[0]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_1[12]  (.A(N_1048), .B(
        N_1051), .C(N_2785), .D(N_2779), .Y(prdata_o_1_0_1_9));
    SLE \pwm_delay_time_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[4]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_0[8]  (.A(N_1155), .B(
        N_2610), .C(N_2778), .D(N_2784), .Y(prdata_o_1_12_0[8]));
    SLE \adc_control_reg_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_control_reg_val_o[4]));
    SLE \speed_pi_kp_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[6]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_24_a2_0_RNO[0]  (.A(
        RATE_LIMITER_0_rl_out_o[0]), .B(BLDC_ESTIMATOR_1_ealpha_o[0]), 
        .C(prdata_o_1_15_i_m2_1_1[0]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1234));
    CFG3 #( .INIT(8'h80) )  adc_control_reg_val_o_1_sqmuxa_0_a2 (.A(
        N_2788), .B(N_2801), .C(N_2766), .Y(
        adc_control_reg_val_o_1_sqmuxa));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_24_a2_6[0]  (.A(
        prdata_o200_2), .B(SEQ_CONTROLLER_1_state_o[0]), .C(N_2787), 
        .D(prdata_o_1_0_a2_7_0[3]), .Y(N_2734));
    CFG3 #( .INIT(8'h80) )  direction_config_o_1_sqmuxa_0_a2 (.A(
        N_2788), .B(prdata_o200_2), .C(N_2787), .Y(
        direction_config_o_1_sqmuxa));
    SLE \angle_ki_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[16]));
    CFG4 #( .INIT(16'h8000) )  pwm_delay_time_val_o_1_sqmuxa_0_a2_0_a2 
        (.A(MC_System_0_AMBA_SLAVE_1_PADDR[3]), .B(N_185), .C(N_2766), 
        .D(N_2789), .Y(pwm_delay_time_val_o_1_sqmuxa));
    SLE \pwm_gain_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[11]));
    CFG4 #( .INIT(16'h1000) )  direction_config_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .C(
        direction_config_o_1_sqmuxa_0_a2_3_1_Z), .D(
        MC_System_0_AMBA_SLAVE_0_PSELx), .Y(N_2788));
    SLE \angle_ki_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[11]));
    SLE \rate_limit_ref_in_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[17]));
    SLE \adc_scale_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[13]));
    SLE \rate_limit_slew_cnt_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[6]));
    SLE \rate_limit_slew_cnt_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[15]));
    SLE \seq_cntl_cl_omega_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[8]));
    SLE \adc_oc_thresh_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[4]));
    SLE \rate_limit_ref_in_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[1]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_3_RNO_0[2]  (.A(
        ADC_SCALING_1_ib_adc_o[2]), .B(ADC_SCALING_1_ia_adc_o[2]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[2]), .Y(N_1090));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[9]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[9]), .Y(
        prdata_o_1_17_i_m2_am[9]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_a2_9[15]  (.A(N_938), .B(
        N_202), .C(prdata_o_1_0_a2_9_0[15]), .D(prdata_o_1_12_a2_7_out)
        , .Y(N_2785));
    SLE \adc_channel_ch2_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[6]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[11]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[11]), .Y(prdata_o_1_16_i_m2_am[11]));
    CFG4 #( .INIT(16'h0100) )  \prdata_o_1_0_a2_7_0_cZ[3]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(prdata_o_1_0_a2_7_0[3]));
    SLE \adc_channel_ch1_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[6]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_i_m2_bm[3]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[3]), .Y(
        prdata_o_1_17_i_m2_i_m2_bm[3]));
    SLE \adc_channel_ch0_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[7]));
    SLE \rate_limit_ref_in_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[11]));
    SLE \rate_limit_rate_cnt_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[10]));
    SLE \speed_pi_ki_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[4]));
    SLE \Ls_by_Ts_pu_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[5]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[13]  (.A(
        prdata_o_1_16_i_m2_am[13]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[13]), .Y(N_1050));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[12]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[12]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[12]), .Y(prdata_o_1_16_i_m2_am[12]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_12_1_RNO_0[7]  (.A(
        adc_measurements_0_adc_result_ch3_o[7]), .B(
        adc_measurements_0_adc_result_ch2_o[7]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[7]));
    SLE \Rs_pu_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[1]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[5]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[5]), .Y(N_1147));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_12_3_RNO[8]  (.A(
        ADC_SCALING_1_ib_adc_o[8]), .B(ADC_SCALING_1_ia_adc_o[8]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[8]), .Y(N_1153));
    SLE \auto_restart_no_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(auto_restart_no_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_auto_restart_no_o[1]));
    SLE \adc_channel_ch2_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[1]));
    SLE \adc_scale_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[16]));
    SLE \idq_pi_kp_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[1]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_0[9]  (.A(N_2564), .B(
        N_2570), .C(N_2778), .D(N_2784), .Y(prdata_o_1_12_0[9]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_0_a2_0_RNO[3]  (.A(
        RATE_LIMITER_0_rl_out_o[3]), .B(BLDC_ESTIMATOR_1_ealpha_o[3]), 
        .C(prdata_o_1_15_i_m2_1_1[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_2594));
    SLE stop_motor_o (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(stop_motor_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_stop_motor_o));
    SLE \rate_limit_ref_in_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[2]));
    SLE \adc_channel_ch0_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[8]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[10]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[10]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[10]), .Y(N_1512));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_15_i_m2_1_1[17]  (.A(
        BLDC_ESTIMATOR_1_theta_o[17]), .B(OLMNG_1_theta_o[17]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[17]));
    SLE \adc_channel_ch1_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[3]));
    SLE \olmng_iq_ref_in_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[8]));
    CFG3 #( .INIT(8'h40) )  speed_pi_ki_o_1_sqmuxa_0_a2_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(N_2796), .C(N_2794), .Y(
        speed_pi_ki_o_1_sqmuxa));
    SLE \seq_cntl_config_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_config_o[3]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[1]  (.A(
        prdata_o_1_17_i_m2_am[1]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[1]), .Y(N_2581));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_12_1_cZ[5]  (.A(N_1012), .B(
        N_2582), .C(N_2791), .D(N_2779), .Y(prdata_o_1_12_1[5]));
    SLE \pwm_delay_time_val_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[17]));
    SLE \adc_oc_thresh_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[1]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_0_2_RNO_2[14]  (.A(
        FOC_TRANSFORMS_0_iq_o[14]), .B(FOC_TRANSFORMS_0_id_o[14]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[14]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[15]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[15]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[15]), .Y(prdata_o_1_16_i_m2_bm[15]));
    SLE \adc_channel_ch2_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[2]));
    SLE \seq_cntl_cl_omega_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[16]));
    SLE \adc_oc_thresh_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[5]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_2_cZ[16]  (.A(N_1084), .B(
        N_1088), .C(N_193), .D(N_2786), .Y(prdata_o_1_0_2[16]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[12]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[12]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[12]), .Y(N_1075));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_13_i_m2[0]  (.A(
        adc_interface_0_result_ch1_o[0]), .B(
        adc_interface_0_result_ch0_o[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[0]), .Y(N_2542));
    SLE \adc_channel_ch1_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[8]));
    SLE \adc_channel_ch0_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[5]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[13]  (.A(
        prdata_o_1_17_i_m2_am[13]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[13]), .Y(N_1047));
    SLE \Rs_pu_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[17]));
    SLE \olmng_theta_factor_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[10]));
    SLE \angle_ki_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[15]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_12_2_RNO[7]  (.A(
        RATE_LIMITER_0_rl_out_o[7]), .B(BLDC_ESTIMATOR_1_ealpha_o[7]), 
        .C(prdata_o_1_15_i_m2_1_1[7]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1025));
    SLE \olmng_theta_factor_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[15]));
    SLE \olmng_dv_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[8]));
    SLE \idq_pi_ki_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[1]));
    CFG4 #( .INIT(16'h8000) )  stop_motor_o_1_sqmuxa_0_a2 (.A(N_2787), 
        .B(N_2789), .C(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(N_2775), 
        .Y(stop_motor_o_1_sqmuxa));
    SLE \pwm_dead_time_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[4]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_12_1_RNO[7]  (.A(
        adc_interface_0_result_ch1_o[7]), .B(
        adc_interface_0_result_ch0_o[7]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[7]), .Y(N_2528));
    SLE \angle_ki_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[5]));
    SLE \adc_scale_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[14]));
    SLE \adc_control_reg_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_control_reg_val_o[5]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[0]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[0]), .Y(
        prdata_o_1_17_i_m2_am[0]));
    SLE \adc_scale_val_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[0]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_0_2_RNO_0[12]  (.A(
        ADC_SCALING_1_ib_adc_o[12]), .B(ADC_SCALING_1_ia_adc_o[12]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[12]), .Y(N_1057));
    SLE \Ls_by_Ts_pu_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[15]));
    SLE \angle_kp_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[5]));
    SLE \pwm_period_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[17]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[16]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[16]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[16]), .Y(prdata_o_1_16_i_m2_am[16]));
    SLE \Ls_by_Ts_pu_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[13]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_24_3_cZ[1]  (.A(N_1507), .B(
        N_2527), .C(N_2786), .D(N_193), .Y(prdata_o_1_24_3[1]));
    CFG2 #( .INIT(4'h1) )  \prdata_o_1_0_a2_9_0[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(prdata_o_1_0_a2_9_0[15])
        );
    SLE \olmng_iq_ref_in_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[9]));
    CFG3 #( .INIT(8'h80) )  rate_limit_slew_cnt_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(N_2796), .C(N_2794), .Y(
        rate_limit_slew_cnt_o_1_sqmuxa));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[1]  (.A(
        prdata_o_1_16_i_m2_am[1]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[1]), .Y(N_2584));
    SLE \angle_ki_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[10]));
    SLE \speed_pi_ki_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[9]));
    SLE \Rs_pu_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[10]));
    CFG2 #( .INIT(4'h2) )  idq_pi_ki_o_1_sqmuxa_0_a2_3 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_2798));
    SLE \idq_pi_ki_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[3]));
    CFG3 #( .INIT(8'h80) )  olmng_theta_factor_o_1_sqmuxa_0_a2 (.A(
        N_2788), .B(N_2802), .C(N_2787), .Y(
        olmng_theta_factor_o_1_sqmuxa));
    SLE \adc_oc_thresh_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[0]));
    SLE \pwm_dead_time_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[0]));
    SLE \adc_scale_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[11]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_2_cZ[8]  (.A(N_2574), .B(
        N_2573), .C(N_2785), .D(N_2786), .Y(prdata_o_1_12_2[8]));
    SLE \olmng_iq_ref_in_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_iq_ref_in_o[13]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_12_3_RNO_0[8]  (.A(
        FOC_TRANSFORMS_0_iq_o[8]), .B(FOC_TRANSFORMS_0_id_o[8]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[8]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_0_a2_0_RNO_0[3]  (.A(
        BLDC_ESTIMATOR_1_theta_o[3]), .B(OLMNG_1_theta_o[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[3]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_12_1_RNO_0[5]  (.A(
        adc_measurements_0_adc_result_ch3_o[5]), .B(
        adc_measurements_0_adc_result_ch2_o[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[5]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_2_RNO[3]  (.A(
        adc_interface_0_result_ch1_o[3]), .B(
        adc_interface_0_result_ch0_o[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_i_m2_1_1[3]), .Y(N_1015));
    SLE \Ls_by_Ts_pu_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[3]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_12_2_RNO_0[6]  (.A(
        BLDC_ESTIMATOR_1_theta_o[6]), .B(OLMNG_1_theta_o[6]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[6]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[17]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[17]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[17]), .Y(N_2522));
    SLE \idq_pi_kp_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[6]));
    SLE \olmng_theta_factor_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[11]));
    SLE \pwm_dead_time_val_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[10]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_0_2_RNO_2[15]  (.A(
        FOC_TRANSFORMS_0_iq_o[15]), .B(FOC_TRANSFORMS_0_id_o[15]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[15]));
    SLE \olmng_theta_factor_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[7]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[8]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[8]), .Y(
        prdata_o_1_17_i_m2_bm[8]));
    SLE \idq_pi_kp_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[7]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_12_1_cZ[7]  (.A(N_1023), .B(
        N_2528), .C(N_2779), .D(N_2791), .Y(prdata_o_1_12_1[7]));
    SLE \pwm_dead_time_val_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[13]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_0[7]  (.A(N_1031), .B(
        N_1043), .C(N_2778), .D(N_2784), .Y(prdata_o_1_12_0[7]));
    SLE \adc_channel_ch1_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[4]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_0_2_RNO_1[12]  (.A(
        BLDC_ESTIMATOR_1_theta_o[12]), .B(OLMNG_1_theta_o[12]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[12]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[9]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[9]), .Y(N_2570));
    SLE \olmng_dv_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[4]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[6]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[6]), .Y(prdata_o_1_16_i_m2_am[6]));
    SLE \adc_channel_ch1_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[5]));
    SLE \seq_cntl_cl_omega_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[2]));
    CFG3 #( .INIT(8'h80) )  rate_limit_rate_cnt_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(N_2802), .C(N_2794), .Y(
        rate_limit_rate_cnt_o_1_sqmuxa));
    SLE \adc_oc_thresh_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[15]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_12_2_RNO_1[5]  (.A(
        BLDC_ESTIMATOR_1_theta_o[5]), .B(OLMNG_1_theta_o[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[5]));
    SLE \idq_pi_ki_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[7]));
    SLE \seq_cntl_config_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_config_o[1]));
    SLE \pwm_gain_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[16]));
    SLE \olmng_iq_ref_in_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_iq_ref_in_o[16]));
    SLE \pwm_delay_time_val_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[6]));
    CFG3 #( .INIT(8'h01) )  adc_control_reg_val_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_2801));
    SLE \olmng_iq_ref_in_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[5]));
    CFG4 #( .INIT(16'h0C0A) )  \prdata_o_1_0_RNO_1[3]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[3]), .B(FOC_TRANSFORMS_0_ibeta_o[3]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_m2_e_0_3_1));
    SLE \angle_kp_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[14]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[15]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[15]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[15]), .Y(N_1030));
    SLE \speed_pi_kp_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[9]));
    SLE \speed_pi_ki_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[0]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[9]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[9]), .Y(prdata_o_1_16_i_m2_am[9]));
    SLE \idq_pi_kp_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[16]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[4]  (.A(
        prdata_o_1_16_i_m2_am[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[4]), .Y(N_1160));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_12_3_RNO[6]  (.A(
        ADC_SCALING_1_ib_adc_o[6]), .B(ADC_SCALING_1_ia_adc_o[6]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[6]), .Y(N_1506));
    SLE \olmng_dv_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[9]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[17]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[17]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[17]), .Y(
        prdata_o_1_17_i_m2_am[17]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[1]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[1]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[1]), .Y(N_1514));
    SLE \speed_pi_kp_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[8]));
    SLE \seq_cntl_cl_omega_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[3]));
    SLE \olmng_iq_ref_in_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_iq_ref_in_o[17]));
    SLE \idq_pi_kp_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[17]));
    SLE \speed_pi_ki_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[1]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[0]  (.A(
        prdata_o_1_16_i_m2_am[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[0]), .Y(N_2585));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_12_1_RNO[8]  (.A(
        adc_interface_0_result_ch1_o[8]), .B(
        adc_interface_0_result_ch0_o[8]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[8]), .Y(N_1154));
    SLE \adc_channel_ch3_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch3_o[14]));
    CFG4 #( .INIT(16'h0110) )  \prdata_o_1_0_a2_10_0_cZ[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(
        prdata_o_1_0_a2_10_0[15]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_3_RNO_0[3]  (.A(
        FOC_TRANSFORMS_0_iq_o[3]), .B(FOC_TRANSFORMS_0_id_o[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[3]));
    SLE \Rs_pu_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[8]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[10]  (.A(
        prdata_o_1_17_i_m2_am[10]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[10]), .Y(N_1416));
    SLE \rate_limit_rate_cnt_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[4]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[7]  (.A(
        prdata_o_1_16_i_m2_am[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[7]), .Y(N_1023));
    CFG3 #( .INIT(8'h80) )  pwm_period_val_o_1_sqmuxa_0_a2_2_a2 (.A(
        N_2789), .B(N_2796), .C(N_2766), .Y(pwm_period_val_o_1_sqmuxa));
    CFG3 #( .INIT(8'hEA) )  \prdata_o_1_12_3_cZ[5]  (.A(
        prdata_o_1_12_0[5]), .B(N_1535), .C(N_193), .Y(
        prdata_o_1_12_3[5]));
    SLE \pwm_period_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[1]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[8]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[8]), .Y(N_1155));
    SLE \pwm_dead_time_val_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[6]));
    SLE \seq_cntl_cl_omega_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[15]));
    CFG4 #( .INIT(16'h8000) )  angle_ki_o_1_sqmuxa_0_a2 (.A(
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_3_Z), .B(N_2788), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(N_2775), .Y(
        angle_ki_o_1_sqmuxa));
    SLE \adc_channel_ch1_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch1_o[12]));
    SLE \seq_cntl_cl_omega_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[13]));
    SLE \Ls_by_Ts_pu_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[4]));
    SLE \angle_ki_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[0]));
    SLE \adc_channel_ch0_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch0_o[14]));
    SLE \adc_channel_ch2_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch2_o[10]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[11]  (.A(
        prdata_o_1_16_i_m2_am[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[11]), .Y(N_1082));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_1[15]  (.A(N_1020), .B(
        N_1022), .C(N_2785), .D(N_2779), .Y(prdata_o_1_0_1_12));
    SLE \pwm_gain_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[1]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_2_cZ[3]  (.A(N_1015), .B(
        N_1013), .C(N_2785), .D(N_2791), .Y(prdata_o_1_2[3]));
    SLE \adc_channel_ch1_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch1_o[11]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[6]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[6]), .Y(
        prdata_o_1_17_i_m2_bm[6]));
    SLE \Ls_by_Ts_pu_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[17]));
    SLE \idq_pi_kp_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[5]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[14]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[14]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[14]), .Y(prdata_o_1_16_i_m2_am[14]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_12_2_RNO[11]  (.A(
        RATE_LIMITER_0_rl_out_o[11]), .B(BLDC_ESTIMATOR_1_ealpha_o[11])
        , .C(prdata_o_1_15_i_m2_1_1[11]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1085));
    SLE \pwm_gain_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[7]));
    SLE \adc_channel_ch0_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[1]));
    SLE \olmng_iq_ref_in_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_iq_ref_in_o[15]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[5]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[5]), .Y(prdata_o_1_16_i_m2_am[5]));
    SLE \speed_pi_ki_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[2]));
    SLE \rate_limit_rate_cnt_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[14]));
    SLE \filter_factor_bemf_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(filter_factor_bemf_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_filter_factor_bemf_o[2]));
    CFG2 #( .INIT(4'h2) )  rate_limit_slew_cnt_o_1_sqmuxa_0_a2_0 (.A(
        N_185), .B(MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(N_2796));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_a2_10[15]  (.A(
        prdata_o_1_0_a2_10_0[15]), .B(N_202), .C(
        prdata_o_1_0_a2_12_0[15]), .Y(N_2786));
    CFG4 #( .INIT(16'h2000) )  adc_channel_ch0_o_1_sqmuxa_0_a2_0_a2 (
        .A(N_2798), .B(MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(N_2788), 
        .D(N_2766), .Y(adc_channel_ch0_o_1_sqmuxa));
    SLE \angle_ki_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[3]));
    SLE \adc_channel_ch2_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[8]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_0[5]  (.A(N_1097), .B(
        N_1147), .C(N_2778), .D(N_2784), .Y(prdata_o_1_12_0[5]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_12_2_RNO_0[10]  (.A(
        BLDC_ESTIMATOR_1_theta_o[10]), .B(OLMNG_1_theta_o[10]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[10]));
    CFG3 #( .INIT(8'h08) )  rate_limit_rate_cnt_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_2802));
    CFG3 #( .INIT(8'h80) )  adc_channel_ch3_o_1_sqmuxa_0_a2_0_a2 (.A(
        N_2788), .B(prdata_o200_2), .C(N_2766), .Y(
        adc_channel_ch3_o_1_sqmuxa));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[11]  (.A(
        prdata_o_1_17_i_m2_am[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[11]), .Y(N_1079));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[13]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[13]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[13]), .Y(prdata_o_1_16_i_m2_bm[13]));
    SLE \adc_scale_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[17]));
    SLE \angle_kp_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[13]));
    SLE \speed_pi_kp_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[7]));
    SLE \pwm_gain_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[9]));
    SLE \olmng_theta_factor_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[0]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_12_3_RNO[10]  (.A(
        ADC_SCALING_1_ib_adc_o[10]), .B(ADC_SCALING_1_ia_adc_o[10]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[10]), .Y(N_2536));
    SLE \idq_pi_kp_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[3]));
    CFG4 #( .INIT(16'h4000) )  Rs_pu_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .B(N_2798), .C(
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_3_Z), .D(N_2788), .Y(
        Rs_pu_o_1_sqmuxa));
    SLE \pwm_gain_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[3]));
    SLE \pwm_dead_time_val_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[15]));
    SLE \adc_control_reg_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_control_reg_val_o[1]));
    SLE \adc_oc_thresh_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[9]));
    CFG3 #( .INIT(8'h80) )  start_motor_o_1_sqmuxa_0_a2_1_a2 (.A(
        N_2788), .B(N_2796), .C(N_2787), .Y(start_motor_o_1_sqmuxa));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_0_2_RNO_2[16]  (.A(
        FOC_TRANSFORMS_0_iq_o[16]), .B(FOC_TRANSFORMS_0_id_o[16]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[16]));
    SLE \adc_control_reg_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_control_reg_val_o[2]));
    SLE \rate_limit_slew_cnt_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[13]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_0_2_RNO_2[13]  (.A(
        FOC_TRANSFORMS_0_iq_o[13]), .B(FOC_TRANSFORMS_0_id_o[13]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[13]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_4_RNO[2]  (.A(
        adc_interface_0_result_ch1_o[2]), .B(
        adc_interface_0_result_ch0_o[2]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[2]), .Y(N_2529));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[9]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[9]), .Y(
        prdata_o_1_17_i_m2_bm[9]));
    CFG3 #( .INIT(8'h80) )  filter_factor_omega_o_1_sqmuxa_0_a2_4_a2 (
        .A(filter_factor_bemf_o_1_sqmuxa_0_a2_1_3_Z), .B(N_2796), .C(
        N_2788), .Y(filter_factor_omega_o_1_sqmuxa));
    SLE \adc_scale_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[7]));
    CFG3 #( .INIT(8'hEA) )  \prdata_o_1_12_3_cZ[7]  (.A(
        prdata_o_1_12_0[7]), .B(N_1027), .C(N_193), .Y(
        prdata_o_1_12_3[7]));
    SLE \rate_limit_rate_cnt_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[5]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_3_RNO[3]  (.A(
        ADC_SCALING_1_ib_adc_o[3]), .B(ADC_SCALING_1_ia_adc_o[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[3]), .Y(N_2595));
    SLE \adc_channel_ch2_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch2_o[15]));
    SLE \Rs_pu_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[11]));
    SLE \rate_limit_rate_cnt_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[6]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[14]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[14]), .Y(
        prdata_o_1_17_i_m2_bm[14]));
    SLE \angle_kp_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[0]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[5]  (.A(
        prdata_o_1_16_i_m2_am[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[5]), .Y(N_2582));
    SLE \idq_pi_kp_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[10]));
    SLE \pwm_period_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[16]));
    SLE \olmng_dv_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[12]));
    SLE \angle_ki_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[9]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[6]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[6]), .Y(N_1513));
    SLE \olmng_theta_factor_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[8]));
    SLE \pwm_delay_time_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[0]));
    SLE \pwm_gain_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[4]));
    SLE \olmng_theta_factor_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[12]));
    SLE \pwm_dead_time_val_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[7]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[14]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[14]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[14]), .Y(N_1061));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0[2]  (.A(N_1008), .B(
        N_2531), .C(N_2778), .D(N_2784), .Y(prdata_o_1_0[2]));
    CFG4 #( .INIT(16'h0800) )  angle_kp_o_1_sqmuxa_0_a2 (.A(
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_3_Z), .B(N_2788), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(N_2775), .Y(
        angle_kp_o_1_sqmuxa));
    CFG4 #( .INIT(16'h0200) )  direction_config_o_1_sqmuxa_0_a2_3_1 (
        .A(MC_System_0_AMBA_SLAVE_1_PWRITE), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PENABLE), .Y(
        direction_config_o_1_sqmuxa_0_a2_3_1_Z));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_a2_0[3]  (.A(N_202), .B(
        N_2594), .C(prdata_o_1_0_a2_12_0[15]), .D(
        prdata_o_1_0_a2_10_0[15]), .Y(N_2704));
    SLE \olmng_iq_ref_in_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[1]));
    SLE \Rs_pu_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[6]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[1]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[1]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[1]), .Y(prdata_o_1_16_i_m2_am[1]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[13]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[13]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[13]), .Y(N_1062));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_12_3_RNO_0[9]  (.A(
        FOC_TRANSFORMS_0_iq_o[9]), .B(FOC_TRANSFORMS_0_id_o[9]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[9]));
    SLE \adc_channel_ch3_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[0]));
    SLE \seq_cntl_cl_omega_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[17]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_12_3_RNO_0[11]  (.A(
        FOC_TRANSFORMS_0_iq_o[11]), .B(FOC_TRANSFORMS_0_id_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[11]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_12_1_RNO_0[8]  (.A(
        adc_measurements_0_adc_result_ch3_o[8]), .B(
        adc_measurements_0_adc_result_ch2_o[8]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[8]));
    SLE \pwm_delay_time_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[2]));
    SLE \angle_kp_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[12]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[2]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[2]), .Y(
        prdata_o_1_17_i_m2_am[2]));
    SLE \pwm_dead_time_val_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[14]));
    CFG3 #( .INIT(8'h80) )  Ls_by_Ts_pu_o_0_sqmuxa_0_a2_0_a2 (.A(
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_3_Z), .B(N_2788), .C(
        N_2801), .Y(Ls_by_Ts_pu_o_0_sqmuxa));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_0[4]  (.A(N_2550), .B(
        N_2555), .C(N_2784), .D(N_2778), .Y(prdata_o_1_12_0[4]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[9]  (.A(
        prdata_o_1_16_i_m2_am[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[9]), .Y(N_2559));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_0_2_RNO[14]  (.A(
        RATE_LIMITER_0_rl_out_o[14]), .B(BLDC_ESTIMATOR_1_ealpha_o[14])
        , .C(prdata_o_1_15_i_m2_1_1[14]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1052));
    SLE start_motor_o (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(start_motor_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_start_motor_o));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_2_cZ[13]  (.A(N_1053), .B(
        N_1056), .C(N_193), .D(N_2786), .Y(prdata_o_1_0_2[13]));
    CFG3 #( .INIT(8'hD8) )  \prdata_o_1_12_1_RNO_0[10]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_2865), .C(N_1004), .Y(
        N_2534));
    CFG4 #( .INIT(16'h0001) )  prdata_m3_e_0_1 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[10]), .Y(prdata_m3_e_0_1_Z));
    SLE \filter_factor_bemf_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(filter_factor_bemf_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_filter_factor_bemf_o[3]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[5]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[5]), .Y(N_1097));
    SLE \olmng_theta_factor_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[14]));
    SLE \rate_limit_rate_cnt_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[2]));
    SLE \olmng_theta_factor_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[1]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_i_m2_am[3]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[3]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[3]), .Y(
        prdata_o_1_17_i_m2_i_m2_am[3]));
    SLE \filter_factor_bemf_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(filter_factor_bemf_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_filter_factor_bemf_o[0]));
    SLE \speed_pi_kp_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[14]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[0]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[0]), .Y(
        prdata_o_1_17_i_m2_bm[0]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_12_1_RNO[6]  (.A(
        adc_interface_0_result_ch1_o[6]), .B(
        adc_interface_0_result_ch0_o[6]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[6]), .Y(N_1510));
    SLE \idq_pi_ki_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[4]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_12_3_RNO[7]  (.A(
        ADC_SCALING_1_ib_adc_o[7]), .B(ADC_SCALING_1_ia_adc_o[7]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[7]), .Y(N_1027));
    SLE \idq_pi_ki_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[16]));
    SLE \olmng_iq_ref_in_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[2]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_0_2_RNO[16]  (.A(
        RATE_LIMITER_0_rl_out_o[16]), .B(BLDC_ESTIMATOR_1_ealpha_o[16])
        , .C(prdata_o_1_15_i_m2_1_1[16]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1084));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[1]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[1]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[1]), .Y(
        prdata_o_1_17_i_m2_am[1]));
    SLE \idq_pi_ki_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[17]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_12_1_cZ[11]  (.A(N_1082), 
        .B(N_1091), .C(N_2779), .D(N_2791), .Y(prdata_o_1_12_1[11]));
    SLE \pwm_period_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[4]));
    CFG4 #( .INIT(16'h4F7F) )  \prdata_o_1_4_1[2]  (.A(
        prdata_o_1_16_i_m2_bm[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(N_2779), .D(
        prdata_o_1_16_i_m2_am[2]), .Y(prdata_o_1_4_1[2]));
    SLE \olmng_dv_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[15]));
    SLE \pwm_gain_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[12]));
    SLE \rate_limit_rate_cnt_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[1]));
    SLE \adc_scale_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[6]));
    SLE \adc_scale_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[9]));
    SLE \adc_channel_ch2_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch2_o[13]));
    SLE \rate_limit_slew_cnt_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[12]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_0_cZ[16]  (.A(N_1146), .B(
        N_2523), .C(N_2784), .D(N_2778), .Y(prdata_o_1_0_0[16]));
    SLE \Ls_by_Ts_pu_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[6]));
    CFG3 #( .INIT(8'h80) )  filter_factor_bemf_o_1_sqmuxa_0_a2 (.A(
        prdata_o200_2), .B(filter_factor_bemf_o_1_sqmuxa_0_a2_1_3_Z), 
        .C(N_2788), .Y(filter_factor_bemf_o_1_sqmuxa));
    SLE \Rs_pu_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[9]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_11_i_m2[5]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[5]), .Y(N_2557));
    SLE \rate_limit_ref_in_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[12]));
    SLE \adc_channel_ch3_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[1]));
    SLE \rate_limit_slew_cnt_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[10]));
    SLE \seq_cntl_cl_omega_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[14]));
    SLE \angle_kp_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[1]));
    SLE \pwm_dead_time_val_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[11]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_14_i_m2[0]  (.A(
        ADC_SCALING_1_ib_adc_o[0]), .B(ADC_SCALING_1_ia_adc_o[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[0]), .Y(N_1508));
    SLE \speed_pi_kp_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[1]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[11]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[11]), .Y(
        prdata_o_1_17_i_m2_am[11]));
    SLE \adc_oc_thresh_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[16]));
    CFG3 #( .INIT(8'h08) )  \prdata_o_1_0_a2_11[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_2759));
    SLE \speed_pi_ki_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[14]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[12]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[12]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[12]), .Y(
        prdata_o_1_17_i_m2_am[12]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_12_1_cZ[8]  (.A(N_1152), .B(
        N_1154), .C(N_2779), .D(N_2791), .Y(prdata_o_1_12_1[8]));
    CFG4 #( .INIT(16'hC800) )  \prdata_o_1_0_a2_6[15]  (.A(N_2759), .B(
        prdata_m3_e_0_1_Z), .C(N_2802), .D(prdata_m3_e_0_0_0), .Y(
        N_2779));
    SLE \speed_pi_kp_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[12]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[2]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[2]), .Y(prdata_o_1_16_i_m2_am[2]));
    SLE \auto_restart_no_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(auto_restart_no_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_auto_restart_no_o[0]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_2_RNO_0[3]  (.A(
        adc_measurements_0_adc_result_ch3_o[3]), .B(
        adc_measurements_0_adc_result_ch2_o[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_i_m2_1_1[3]));
    SLE \seq_cntl_config_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_config_o[2]));
    SLE \pwm_delay_time_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[5]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[6]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[6]), .Y(prdata_o_1_16_i_m2_bm[6]));
    SLE \seq_cntl_cl_omega_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[4]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_12_1_RNO[4]  (.A(
        adc_interface_0_result_ch1_o[4]), .B(
        adc_interface_0_result_ch0_o[4]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[4]), .Y(N_1011));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_0_cZ[15]  (.A(N_1030), .B(
        N_1042), .C(N_2778), .D(N_2784), .Y(prdata_o_1_0_0[15]));
    SLE \olmng_dv_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[13]));
    SLE \adc_channel_ch1_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[1]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[11]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[11]), .Y(prdata_o_1_16_i_m2_bm[11]));
    SLE \rate_limit_rate_cnt_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[15]));
    SLE \olmng_theta_factor_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[13]));
    SLE \angle_kp_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[6]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_12_3_RNO[4]  (.A(
        ADC_SCALING_1_ib_adc_o[4]), .B(ADC_SCALING_1_ia_adc_o[4]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[4]), .Y(N_2601));
    CFG2 #( .INIT(4'h1) )  filter_factor_bemf_o_1_sqmuxa_0_a2_1_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[1]), .Y(
        filter_factor_bemf_o_1_sqmuxa_0_a2_1_0_Z));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[8]  (.A(
        prdata_o_1_17_i_m2_am[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[8]), .Y(N_2573));
    SLE \idq_pi_ki_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[8]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_a2_3[17]  (.A(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .B(N_1087), .C(
        prdata_o190_0_a2_0_out), .D(N_172), .Y(N_2660));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[15]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[15]), .Y(
        prdata_o_1_17_i_m2_bm[15]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_12_2_RNO[4]  (.A(
        RATE_LIMITER_0_rl_out_o[4]), .B(BLDC_ESTIMATOR_1_ealpha_o[4]), 
        .C(prdata_o_1_15_i_m2_1_1[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_2600));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_12_1_RNO[11]  (.A(
        adc_interface_0_result_ch1_o[11]), .B(
        adc_interface_0_result_ch0_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[11]), .Y(N_1091));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_1[16]  (.A(N_1078), .B(
        N_1081), .C(N_2785), .D(N_2779), .Y(prdata_o_1_0_1_13));
    SLE \adc_channel_ch0_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[4]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[9]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[9]), .Y(prdata_o_1_16_i_m2_bm[9]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_i_m2_ns[3]  (.A(
        prdata_o_1_17_i_m2_i_m2_am[3]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_i_m2_bm[3]), .Y(N_1013));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_12_1_RNO_0[6]  (.A(
        adc_measurements_0_adc_result_ch3_o[6]), .B(
        adc_measurements_0_adc_result_ch2_o[6]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[6]));
    CFG4 #( .INIT(16'h2000) )  adc_channel_ch1_o_1_sqmuxa_0_a2_0_a2 (
        .A(N_2775), .B(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(N_2788), 
        .D(N_2766), .Y(adc_channel_ch1_o_1_sqmuxa));
    SLE \olmng_theta_factor_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[17]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[17]  (.A(
        prdata_o_1_16_i_m2_am[17]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[17]), .Y(N_1080));
    SLE \olmng_theta_factor_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[5]));
    SLE \idq_pi_kp_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[4]));
    SLE \adc_channel_ch2_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[4]));
    SLE \adc_channel_ch3_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch3_o[12]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_0_a2_3_RNO_0[17]  (.A(
        FOC_TRANSFORMS_0_iq_o[17]), .B(FOC_TRANSFORMS_0_id_o[17]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[17]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_a2_7[3]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .B(prdata_o200_2), .C(
        prdata_o_1_0_a2_7_0[3]), .D(N_202), .Y(N_2470));
    SLE \speed_pi_ki_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[12]));
    SLE \pwm_gain_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[10]));
    SLE \speed_pi_kp_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[13]));
    SLE \idq_pi_ki_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[10]));
    SLE \adc_scale_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[8]));
    SLE \olmng_iq_ref_in_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[4]));
    SLE \adc_channel_ch0_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[0]));
    SLE \adc_channel_ch0_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[6]));
    SLE \adc_channel_ch3_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch3_o[11]));
    SLE \rate_limit_ref_in_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[0]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_14_i_m2_1_1[0]  (.A(
        FOC_TRANSFORMS_0_iq_o[0]), .B(FOC_TRANSFORMS_0_id_o[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[0]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[16]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[16]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[16]), .Y(
        prdata_o_1_17_i_m2_am[16]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_24_3_RNO[1]  (.A(
        ADC_SCALING_1_ib_adc_o[1]), .B(ADC_SCALING_1_ia_adc_o[1]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[1]), .Y(N_1507));
    SLE \angle_kp_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[16]));
    SLE \seq_cntl_cl_omega_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[9]));
    CFG4 #( .INIT(16'hAC00) )  \prdata_o_1_24_a2_5[1]  (.A(
        FOC_TRANSFORMS_0_ibeta_o[1]), .B(FOC_TRANSFORMS_0_ialpha_o[1]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(N_2778), .Y(N_2725));
    SLE \olmng_dv_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[0]));
    SLE \adc_channel_ch0_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch0_o[12]));
    CFG3 #( .INIT(8'h80) )  olmng_dv_o_1_sqmuxa_0_a2_0_a2 (.A(N_2789), 
        .B(N_2801), .C(N_2787), .Y(olmng_dv_o_1_sqmuxa));
    SLE \angle_kp_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[11]));
    SLE \adc_channel_ch2_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch2_o[3]));
    SLE \pwm_dead_time_val_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[16]));
    CFG4 #( .INIT(16'hAC00) )  \prdata_o_1_12_a2_2[11]  (.A(
        FOC_TRANSFORMS_0_vbeta_o[11]), .B(
        BLDC_ESTIMATOR_1_pll_pi_out_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(N_2784), .Y(N_2671));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[17]  (.A(
        prdata_o_1_17_i_m2_am[17]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[17]), .Y(N_1077));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[7]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[7]), .Y(N_1031));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_a2_8[15]  (.A(
        prdata_m3_e_0_0_0), .B(N_939_i), .C(N_185), .D(
        prdata_m3_e_0_1_Z), .Y(N_2784));
    SLE \adc_channel_ch0_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch0_o[11]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_12_3_RNO[9]  (.A(
        ADC_SCALING_1_ib_adc_o[9]), .B(ADC_SCALING_1_ia_adc_o[9]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[9]), .Y(N_2561));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[5]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[5]), .Y(prdata_o_1_16_i_m2_bm[5]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_8_i_m2_i_m2[3]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[3]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[3]), .Y(N_1018));
    SLE \auto_restart_no_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(auto_restart_no_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_auto_restart_no_o[3]));
    SLE \adc_channel_ch1_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch1_o[10]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[17]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[17]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[17]), .Y(prdata_o_1_16_i_m2_bm[17]));
    SLE \seq_cntl_cl_omega_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[1]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[10]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[10]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[10]), .Y(N_1525));
    SLE \rate_limit_slew_cnt_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[9]));
    CFG4 #( .INIT(16'h8000) )  adc_channel_ch2_o_1_sqmuxa_0_a2 (.A(
        N_2775), .B(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(N_2788), .D(
        N_2766), .Y(adc_channel_ch2_o_1_sqmuxa));
    SLE \olmng_dv_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[7]));
    SLE \adc_channel_ch3_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[2]));
    SLE \idq_pi_ki_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[2]));
    SLE \Ls_by_Ts_pu_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[7]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_2_cZ[15]  (.A(N_1024), .B(
        N_1026), .C(N_193), .D(N_2786), .Y(prdata_o_1_0_2[15]));
    SLE \adc_scale_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[2]));
    GND GND_Z (.Y(GND));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[0]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[0]), .Y(N_2532));
    SLE \adc_scale_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[3]));
    SLE \speed_pi_ki_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[13]));
    SLE \adc_channel_ch1_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[0]));
    SLE \seq_cntl_cl_omega_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_cl_omega_o[6]));
    SLE \speed_pi_kp_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[16]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[4]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[4]), .Y(N_2550));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_2_cZ[2]  (.A(N_2580), .B(
        SEQ_CONTROLLER_1_state_o[2]), .C(N_2785), .D(N_2470), .Y(
        prdata_o_1_2[2]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_12_3_RNO_0[5]  (.A(
        FOC_TRANSFORMS_0_iq_o[5]), .B(FOC_TRANSFORMS_0_id_o[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[5]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_2_cZ[4]  (.A(N_2600), .B(
        N_1159), .C(N_2785), .D(N_2786), .Y(prdata_o_1_12_2[4]));
    SLE \olmng_dv_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[10]));
    SLE \adc_oc_thresh_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[3]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_0_cZ[13]  (.A(N_1062), .B(
        N_1074), .C(N_2778), .D(N_2784), .Y(prdata_o_1_0_0[13]));
    SLE \adc_oc_thresh_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[14]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_13_i_m2_1_1[0]  (.A(
        adc_measurements_0_adc_result_ch3_o[0]), .B(
        adc_measurements_0_adc_result_ch2_o[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[0]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_12_2_RNO_0[8]  (.A(
        BLDC_ESTIMATOR_1_theta_o[8]), .B(OLMNG_1_theta_o[8]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[8]));
    SLE \olmng_iq_ref_in_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_iq_ref_in_o[14]));
    SLE \angle_kp_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[9]));
    SLE \idq_pi_ki_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_ki_o_0[0]));
    SLE \pwm_gain_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[6]));
    CFG3 #( .INIT(8'hEA) )  \prdata_o_1_12_3_cZ[8]  (.A(
        prdata_o_1_12_0[8]), .B(N_1153), .C(N_193), .Y(
        prdata_o_1_12_3[8]));
    SLE \rate_limit_slew_cnt_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[2]));
    SLE \pwm_dead_time_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[3]));
    SLE \Rs_pu_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[7]));
    SLE \rate_limit_slew_cnt_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[1]));
    SLE \pwm_gain_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[5]));
    SLE \olmng_theta_factor_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[9]));
    SLE \speed_pi_ki_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[5]));
    SLE \rate_limit_ref_in_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[10]));
    SLE \olmng_theta_factor_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[3]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_12_3_RNO_0[4]  (.A(
        FOC_TRANSFORMS_0_iq_o[4]), .B(FOC_TRANSFORMS_0_id_o[4]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[4]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_12_2_RNO[6]  (.A(
        RATE_LIMITER_0_rl_out_o[6]), .B(BLDC_ESTIMATOR_1_ealpha_o[6]), 
        .C(prdata_o_1_15_i_m2_1_1[6]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1468));
    SLE \angle_kp_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[15]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[2]  (.A(
        prdata_o_1_17_i_m2_am[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[2]), .Y(N_2580));
    SLE \angle_ki_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[17]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_0_2_RNO[15]  (.A(
        RATE_LIMITER_0_rl_out_o[15]), .B(BLDC_ESTIMATOR_1_ealpha_o[15])
        , .C(prdata_o_1_15_i_m2_1_1[15]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1024));
    SLE \idq_pi_kp_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[0]));
    SLE \adc_channel_ch1_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch1_o[15]));
    SLE \Rs_pu_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[3]));
    SLE \pwm_period_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[3]));
    SLE \speed_pi_kp_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[5]));
    SLE \speed_pi_ki_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[8]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[1]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[1]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[1]), .Y(prdata_o_1_16_i_m2_bm[1]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[4]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[4]), .Y(N_2555));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_1[14]  (.A(N_1046), .B(
        N_1049), .C(N_2785), .D(N_2779), .Y(prdata_o_1_0_1_11));
    SLE \olmng_dv_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[11]));
    SLE \pwm_delay_time_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[3]));
    SLE \speed_pi_ki_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[16]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[2]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[2]), .Y(
        prdata_o_1_17_i_m2_bm[2]));
    CFG3 #( .INIT(8'hD8) )  \prdata_o_1_8_i_m2_i_m2_RNIBSG41[3]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_2869), .C(N_1018), .Y(
        N_1014));
    CFG4 #( .INIT(16'h2000) )  adc_oc_thresh_o_1_sqmuxa_0_a2 (.A(
        N_2798), .B(MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(N_2789), .D(
        N_2766), .Y(adc_oc_thresh_o_1_sqmuxa));
    SLE \angle_kp_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[10]));
    SLE \pwm_delay_time_val_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[14]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_9_i_m2[5]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[5]), .Y(N_2553));
    SLE \adc_oc_thresh_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[11]));
    SLE \pwm_period_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[8]));
    CFG4 #( .INIT(16'h2000) )  stop_motor_o_1_sqmuxa_0_a2_3 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .C(
        direction_config_o_1_sqmuxa_0_a2_3_1_Z), .D(
        MC_System_0_AMBA_SLAVE_0_PSELx), .Y(N_2789));
    SLE \idq_pi_kp_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[2]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[15]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[15]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[15]), .Y(N_1042));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_0_2_RNO_2[12]  (.A(
        FOC_TRANSFORMS_0_iq_o[12]), .B(FOC_TRANSFORMS_0_id_o[12]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[12]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_24_a2_0_RNO_0[0]  (.A(
        BLDC_ESTIMATOR_1_theta_o[0]), .B(OLMNG_1_theta_o[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[0]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[2]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[2]), .Y(N_1008));
    SLE \olmng_dv_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[17]));
    SLE \adc_oc_thresh_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[8]));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_24_3_RNO_2[1]  (.A(
        FOC_TRANSFORMS_0_iq_o[1]), .B(FOC_TRANSFORMS_0_id_o[1]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[1]));
    SLE \Rs_pu_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[15]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[14]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[14]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[14]), .Y(
        prdata_o_1_17_i_m2_am[14]));
    SLE \pwm_period_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[12]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_24_a2_0[0]  (.A(N_202), .B(
        N_1234), .C(prdata_o_1_0_a2_12_0[15]), .D(
        prdata_o_1_0_a2_10_0[15]), .Y(N_2728));
    SLE \pwm_dead_time_val_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[12]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_2_cZ[9]  (.A(N_2560), .B(
        N_2558), .C(N_2785), .D(N_2786), .Y(prdata_o_1_12_2[9]));
    SLE \pwm_period_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[2]));
    SLE \rate_limit_slew_cnt_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[4]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_11_i_m2[4]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[4]), .Y(N_1289));
    SLE \adc_channel_ch1_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[9]));
    SLE \angle_kp_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[7]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[13]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[13]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[13]), .Y(N_1074));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[7]  (.A(
        prdata_o_1_17_i_m2_am[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[7]), .Y(N_1021));
    SLE \adc_oc_thresh_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[17]));
    SLE \rate_limit_rate_cnt_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[9]));
    SLE \seq_cntl_config_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_seq_cntl_config_o[0]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_0[10]  (.A(N_1512), .B(
        N_1525), .C(N_2778), .D(N_2784), .Y(prdata_o_1_12_0[10]));
    SLE \angle_ki_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[1]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[8]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[8]), .Y(N_2610));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[12]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[12]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[12]), .Y(prdata_o_1_16_i_m2_bm[12]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[4]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[4]), .Y(prdata_o_1_16_i_m2_am[4]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[1]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[1]), .Y(
        prdata_o_1_17_i_m2_bm[1]));
    SLE \pwm_period_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[13]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_4_RNO_0[2]  (.A(
        adc_measurements_0_adc_result_ch3_o[2]), .B(
        adc_measurements_0_adc_result_ch2_o[2]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[2]));
    SLE \adc_control_reg_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_control_reg_val_o[0]));
    SLE \Ls_by_Ts_pu_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[14]));
    SLE \speed_pi_kp_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[11]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_0_2_RNO[12]  (.A(
        RATE_LIMITER_0_rl_out_o[12]), .B(BLDC_ESTIMATOR_1_ealpha_o[12])
        , .C(prdata_o_1_15_i_m2_1_1[12]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1054));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[13]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[13]), .Y(
        prdata_o_1_17_i_m2_bm[13]));
    CFG2 #( .INIT(4'h8) )  stop_motor_o_1_sqmuxa_0_a2_2 (.A(N_202), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .Y(N_2787));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_12_2_RNO[10]  (.A(
        RATE_LIMITER_0_rl_out_o[10]), .B(BLDC_ESTIMATOR_1_ealpha_o[10])
        , .C(prdata_o_1_15_i_m2_1_1[10]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1455));
    SLE \adc_oc_thresh_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[10]));
    SLE \olmng_iq_ref_in_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_iq_ref_in_o[12]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_8_i_m2[10]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[10]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[10]), .Y(N_1004));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_bm[10]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(net_189[10]), .Y(
        prdata_o_1_17_i_m2_bm[10]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[15]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[15]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[15]), .Y(prdata_o_1_16_i_m2_am[15]));
    SLE \adc_channel_ch1_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch1_o[13]));
    CFG4 #( .INIT(16'h05F3) )  \prdata_o_1_12_1_RNO_0[4]  (.A(
        adc_measurements_0_adc_result_ch3_o[4]), .B(
        adc_measurements_0_adc_result_ch2_o[4]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_13_i_m2_1_1[4]));
    SLE \adc_oc_thresh_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_oc_thresh_o[6]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[13]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[13]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[13]), .Y(prdata_o_1_16_i_m2_am[13]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_12_3_RNO[5]  (.A(
        ADC_SCALING_1_ib_adc_o[5]), .B(ADC_SCALING_1_ia_adc_o[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[5]), .Y(N_1535));
    SLE \pwm_period_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[11]));
    SLE \speed_pi_kp_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[4]));
    SLE \angle_ki_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[8]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[2]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[2]), .Y(prdata_o_1_16_i_m2_bm[2]));
    SLE \rate_limit_ref_in_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[3]));
    SLE \adc_channel_ch0_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch0_o[9]));
    SLE \speed_pi_kp_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[2]));
    SLE \rate_limit_slew_cnt_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[14]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_bm[16]  (.A(
        BLDC_ESTIMATOR_1_ebeta_filtered_o[16]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        BLDC_ESTIMATOR_1_ebeta_o[16]), .Y(prdata_o_1_16_i_m2_bm[16]));
    SLE \adc_scale_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[10]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[16]  (.A(
        prdata_o_1_16_i_m2_am[16]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[16]), .Y(N_1081));
    SLE \pwm_dead_time_val_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_dead_time_val_o[17]));
    SLE \speed_pi_ki_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_ki_o[11]));
    CFG3 #( .INIT(8'h80) )  rate_limit_ref_in_o_1_sqmuxa_0_a2 (.A(
        prdata_o200_2), .B(N_2794), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(
        rate_limit_ref_in_o_1_sqmuxa));
    SLE \rate_limit_slew_cnt_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_slew_cnt_o[11]));
    SLE \olmng_dv_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[1]));
    SLE \idq_pi_kp_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_idq_pi_kp_o[15]));
    SLE \angle_ki_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[4]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_2_cZ[14]  (.A(N_1052), .B(
        N_1055), .C(N_193), .D(N_2786), .Y(prdata_o_1_0_2[14]));
    SLE \olmng_dv_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[14]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_2_cZ[6]  (.A(N_1468), .B(
        N_1435), .C(N_2785), .D(N_2786), .Y(prdata_o_1_12_2[6]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_16_i_m2_am[8]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        FOC_TRANSFORMS_0_valpha_o[8]), .Y(prdata_o_1_16_i_m2_am[8]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_10_i_m2[12]  (.A(
        BLDC_ESTIMATOR_1_pll_pi_out_o[12]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        FOC_TRANSFORMS_0_vbeta_o[12]), .Y(N_1063));
    CFG4 #( .INIT(16'hF8FF) )  \prdata_o_1_4_cZ[2]  (.A(N_2791), .B(
        N_2529), .C(prdata_o_1_0[2]), .D(prdata_o_1_4_1[2]), .Y(
        prdata_o_1_4[2]));
    SLE \rate_limit_ref_in_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[6]));
    SLE \pwm_delay_time_val_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[16]));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_16_i_m2_am[0]  (.A(
        BLDC_ESTIMATOR_0_speed_filtered_o[0]), .B(
        FOC_TRANSFORMS_0_valpha_o[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .Y(
        prdata_o_1_16_i_m2_am[0]));
    CFG4 #( .INIT(16'hC0AF) )  \prdata_o_1_24_1_RNO[1]  (.A(
        adc_interface_0_result_ch1_o[1]), .B(
        adc_interface_0_result_ch0_o[1]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .D(
        prdata_o_1_13_i_m2_1_1[1]), .Y(N_2541));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_0_2_RNO_0[14]  (.A(
        ADC_SCALING_1_ib_adc_o[14]), .B(ADC_SCALING_1_ia_adc_o[14]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[14]), .Y(N_1055));
    SLE \speed_pi_kp_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_speed_pi_kp_o[0]));
    SLE \angle_kp_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_kp_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_kp_o[3]));
    SLE \angle_ki_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(angle_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_angle_ki_o[2]));
    CFG4 #( .INIT(16'h0800) )  seq_cntl_cl_omega_o_1_sqmuxa_0_a2 (.A(
        N_2787), .B(N_2789), .C(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(
        N_2775), .Y(seq_cntl_cl_omega_o_1_sqmuxa));
    CFG3 #( .INIT(8'h80) )  auto_restart_no_o_1_sqmuxa_0_a2_0_a2 (.A(
        N_2789), .B(N_2796), .C(N_2787), .Y(auto_restart_no_o_1_sqmuxa)
        );
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[16]  (.A(
        prdata_o_1_17_i_m2_am[16]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[16]), .Y(N_1078));
    SLE \pwm_period_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[14]));
    SLE \filter_factor_omega_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(filter_factor_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_filter_factor_omega_o[0]));
    SLE \pwm_delay_time_val_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_delay_time_val_o[9]));
    SLE \adc_scale_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[12]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_17_i_m2_ns[9]  (.A(
        prdata_o_1_17_i_m2_am[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_17_i_m2_bm[9]), .Y(N_2558));
    SLE \olmng_theta_factor_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_theta_factor_o[2]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_4_i_m2[16]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[16]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        FOC_TRANSFORMS_0_ibeta_o[16]), .Y(N_1146));
    SLE \pwm_period_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[9]));
    CFG3 #( .INIT(8'h40) )  pwm_gain_val_o_1_sqmuxa_0_a2_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(N_2801), .C(N_2794), .Y(
        pwm_gain_val_o_1_sqmuxa));
    SLE \pwm_period_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[5]));
    CFG4 #( .INIT(16'h8000) )  idq_pi_ki_o_1_sqmuxa_0_a2_2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .B(
        direction_config_o_1_sqmuxa_0_a2_3_1_Z), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(N_2766), .Y(N_2794));
    CFG4 #( .INIT(16'h503F) )  \prdata_o_1_3_RNO_2[2]  (.A(
        FOC_TRANSFORMS_0_iq_o[2]), .B(FOC_TRANSFORMS_0_id_o[2]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_14_i_m2_1_1[2]));
    SLE \adc_channel_ch3_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch3_o[10]));
    CFG2 #( .INIT(4'h2) )  \prdata_o_1_0_a2_15[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_2775));
    CFG3 #( .INIT(8'h08) )  speed_pi_kp_o_1_sqmuxa_0_a2 (.A(
        prdata_o200_2), .B(N_2794), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(speed_pi_kp_o_1_sqmuxa));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_0_2_RNO_1[14]  (.A(
        BLDC_ESTIMATOR_1_theta_o[14]), .B(OLMNG_1_theta_o[14]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[14]));
    SLE \rate_limit_ref_in_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_ref_in_o[14]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_12_2_RNO_0[9]  (.A(
        BLDC_ESTIMATOR_1_theta_o[9]), .B(OLMNG_1_theta_o[9]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[9]));
    CFG3 #( .INIT(8'hB8) )  \prdata_o_1_17_i_m2_am[7]  (.A(
        BLDC_ESTIMATOR_1_ealpha_filtered_o[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[7]), .Y(
        prdata_o_1_17_i_m2_am[7]));
    SLE \Ls_by_Ts_pu_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(Ls_by_Ts_pu_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Ls_by_Ts_pu_o[10]));
    SLE \Rs_pu_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[13]));
    SLE \adc_channel_ch3_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[9]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_12_2_RNO_0[11]  (.A(
        BLDC_ESTIMATOR_1_theta_o[11]), .B(OLMNG_1_theta_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[11]));
    SLE \adc_scale_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_scale_val_o[15]));
    SLE \adc_channel_ch0_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_adc_channel_ch0_o[10]));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[15]  (.A(
        prdata_o_1_16_i_m2_am[15]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[15]), .Y(N_1022));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_0[6]  (.A(N_1513), .B(
        N_1526), .C(N_2778), .D(N_2784), .Y(prdata_o_1_12_0[6]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_3_cZ[3]  (.A(N_2470), .B(
        N_193), .C(SEQ_CONTROLLER_1_state_o[3]), .D(N_2595), .Y(
        prdata_o_1_3[3]));
    SLE \olmng_iq_ref_in_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_olmng_iq_ref_in_o[7]));
    SLE \Rs_pu_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(Rs_pu_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_Rs_pu_o[16]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_0_2_RNO_0[15]  (.A(
        ADC_SCALING_1_ib_adc_o[15]), .B(ADC_SCALING_1_ia_adc_o[15]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[15]), .Y(N_1026));
    SLE \adc_channel_ch3_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch3_o[6]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_12_2_cZ[11]  (.A(N_1085), 
        .B(N_1079), .C(N_2785), .D(N_2786), .Y(prdata_o_1_12_2[11]));
    SLE \pwm_period_val_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_period_val_o[0]));
    SLE \pwm_gain_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_pwm_gain_val_o[13]));
    CFG4 #( .INIT(16'h530F) )  \prdata_o_1_3_RNO_1[2]  (.A(
        BLDC_ESTIMATOR_1_theta_o[2]), .B(OLMNG_1_theta_o[2]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        prdata_o_1_15_i_m2_1_1[2]));
    CFG4 #( .INIT(16'h0FAC) )  \prdata_o_1_15_i_m2[17]  (.A(
        RATE_LIMITER_0_rl_out_o[17]), .B(BLDC_ESTIMATOR_1_ealpha_o[17])
        , .C(prdata_o_1_15_i_m2_1_1[17]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_1083));
    CFG4 #( .INIT(16'hAC00) )  \prdata_o_1_12_a2_5[11]  (.A(
        FOC_TRANSFORMS_0_ibeta_o[11]), .B(
        FOC_TRANSFORMS_0_ialpha_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(N_2778), .Y(N_2674));
    CFG3 #( .INIT(8'hE2) )  \prdata_o_1_16_i_m2_ns[12]  (.A(
        prdata_o_1_16_i_m2_am[12]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(
        prdata_o_1_16_i_m2_bm[12]), .Y(N_1051));
    SLE \adc_channel_ch1_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_adc_channel_ch1_o[2]));
    CFG4 #( .INIT(16'h0CFA) )  \prdata_o_1_0_a2_3_RNO[17]  (.A(
        ADC_SCALING_1_ib_adc_o[17]), .B(ADC_SCALING_1_ia_adc_o[17]), 
        .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        prdata_o_1_14_i_m2_1_1[17]), .Y(N_1087));
    SLE \olmng_dv_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_0_olmng_dv_o[3]));
    SLE \rate_limit_rate_cnt_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_0_rate_limit_rate_cnt_o[12]));
    
endmodule


module Bldc_Axis(
       MC_System_0_AMBA_SLAVE_1_PWDATA,
       prdata_o_1_0,
       prdata_o_1_4,
       prdata_o_1_0_a2_12_0,
       MC_System_0_AMBA_SLAVE_1_PADDR,
       prdata_o_1_0_a2_10_0,
       prdata_o_1_0_a2_7_0,
       prdata_o_1_24_3,
       prdata_o_1_3,
       prdata_o_1_0_2,
       prdata_o_1_0_0,
       prdata_o_1_24_2,
       prdata_o_1_12_3,
       prdata_o_1_12_2,
       prdata_o_1_12_1,
       prdata_o_1_2,
       prdata_o_1_0_1,
       prdata_o_1_24_4,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       A0_PWM_VL_O_c,
       A0_PWM_UH_O_c,
       A0_PWM_VH_O_c,
       A0_PWM_WH_O_c,
       N_202,
       N_185,
       N_2791,
       N_2779,
       N_2542,
       N_1508,
       N_1083,
       N_2606,
       N_2585,
       N_1080,
       N_1077,
       N_1014,
       N_176,
       N_1007,
       N_2522,
       N_2532,
       MC_System_0_AMBA_SLAVE_1_PWRITE,
       MC_System_0_AMBA_SLAVE_1_PENABLE,
       N_2787,
       N_2704,
       adc_channel_ch3_o_1_sqmuxa_0_a2_0_0,
       prdata_o190_0_a2_0_out,
       N_172,
       N_2660,
       N_2778,
       N_2784,
       prdata_o200_2,
       N_2470,
       N_2785,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       N_2734,
       N_2661,
       N_2728,
       N_193,
       A0_ADC_SDI_I_c,
       A0_ADC_SDO_O_c,
       A0_ADC_CS_O_c,
       A0_ADC_SCK_O_c
    );
input  [17:0] MC_System_0_AMBA_SLAVE_1_PWDATA;
output [3:3] prdata_o_1_0;
output [2:2] prdata_o_1_4;
output [15:15] prdata_o_1_0_a2_12_0;
input  [11:0] MC_System_0_AMBA_SLAVE_1_PADDR;
output [15:15] prdata_o_1_0_a2_10_0;
output [3:3] prdata_o_1_0_a2_7_0;
output [1:1] prdata_o_1_24_3;
output [3:2] prdata_o_1_3;
output [16:12] prdata_o_1_0_2;
output [16:12] prdata_o_1_0_0;
output [1:1] prdata_o_1_24_2;
output [11:4] prdata_o_1_12_3;
output [11:4] prdata_o_1_12_2;
output [11:4] prdata_o_1_12_1;
output [3:2] prdata_o_1_2;
output [16:12] prdata_o_1_0_1;
output [1:1] prdata_o_1_24_4;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;
output A0_PWM_VL_O_c;
output A0_PWM_UH_O_c;
output A0_PWM_VH_O_c;
output A0_PWM_WH_O_c;
input  N_202;
output N_185;
output N_2791;
output N_2779;
output N_2542;
output N_1508;
output N_1083;
output N_2606;
output N_2585;
output N_1080;
output N_1077;
output N_1014;
output N_176;
output N_1007;
output N_2522;
output N_2532;
input  MC_System_0_AMBA_SLAVE_1_PWRITE;
input  MC_System_0_AMBA_SLAVE_1_PENABLE;
output N_2787;
output N_2704;
input  adc_channel_ch3_o_1_sqmuxa_0_a2_0_0;
input  prdata_o190_0_a2_0_out;
input  N_172;
output N_2660;
output N_2778;
output N_2784;
input  prdata_o200_2;
output N_2470;
output N_2785;
input  MC_System_0_AMBA_SLAVE_0_PSELx;
output N_2734;
output N_2661;
output N_2728;
input  N_193;
input  A0_ADC_SDI_I_c;
output A0_ADC_SDO_O_c;
output A0_ADC_CS_O_c;
output A0_ADC_SCK_O_c;

    wire [17:0] FOC_TRANSFORMS_0_va_o;
    wire [17:0] FOC_TRANSFORMS_0_vb_o;
    wire [17:0] FOC_TRANSFORMS_0_vc_o;
    wire [17:0] SVM_0_va3h_o;
    wire [17:0] SVM_0_vb3h_o;
    wire [17:0] SVM_0_vc3h_o;
    wire [17:0] OLMNG_0_init_speedpi_o;
    wire [17:0] OLMNG_0_init_iqpi_o;
    wire [17:0] RATE_LIMITER_0_rl_out_o;
    wire [17:0] BLDC_ESTIMATOR_0_speed_filtered_o;
    wire [17:0] apb3_if_0_speed_pi_kp_o;
    wire [17:0] apb3_if_0_speed_pi_ki_o;
    wire [17:0] FOC_TRANSFORMS_0_id_o;
    wire [17:0] apb3_if_0_idq_pi_kp_o;
    wire [17:0] apb3_if_0_idq_pi_ki_o_0;
    wire [17:0] net_189;
    wire [17:0] FOC_TRANSFORMS_0_iq_o;
    wire [17:0] SPEED_ID_IQ_PI_1_id_pi_output_o;
    wire [17:0] SPEED_ID_IQ_PI_1_iq_pi_output_o;
    wire [17:0] apb3_if_0_rate_limit_slew_cnt_o;
    wire [17:0] apb3_if_0_rate_limit_rate_cnt_o;
    wire [17:0] apb3_if_0_rate_limit_ref_in_o;
    wire [17:0] apb3_if_0_pwm_period_val_o;
    wire [17:1] apb3_if_0_pwm_gain_val_o;
    wire [17:0] PWM_SCALING_0_Va_o;
    wire [17:0] PWM_SCALING_0_Vb_o;
    wire [17:0] PWM_SCALING_0_Vc_o;
    wire [17:0] apb3_if_0_pwm_dead_time_val_o;
    wire [17:0] apb3_if_0_pwm_delay_time_val_o;
    wire [17:0] apb3_if_0_olmng_theta_factor_o;
    wire [17:0] apb3_if_0_olmng_dv_o;
    wire [17:0] BLDC_ESTIMATOR_1_theta_o;
    wire [17:0] apb3_if_0_olmng_iq_ref_in_o;
    wire [17:0] OLMNG_1_theta_o;
    wire [17:0] ADC_SCALING_1_ia_adc_o;
    wire [17:0] ADC_SCALING_1_ib_adc_o;
    wire [17:0] FOC_TRANSFORMS_0_ialpha_o;
    wire [17:0] FOC_TRANSFORMS_0_ibeta_o;
    wire [17:0] FOC_TRANSFORMS_0_valpha_o;
    wire [17:0] FOC_TRANSFORMS_0_vbeta_o;
    wire [17:0] apb3_if_0_Ls_by_Ts_pu_o;
    wire [17:0] apb3_if_0_Rs_pu_o;
    wire [3:0] apb3_if_0_filter_factor_bemf_o;
    wire [17:0] apb3_if_0_angle_ki_o;
    wire [17:0] apb3_if_0_angle_kp_o;
    wire [3:0] apb3_if_0_filter_factor_omega_o;
    wire [17:0] BLDC_ESTIMATOR_1_ealpha_o;
    wire [17:0] BLDC_ESTIMATOR_1_ebeta_o;
    wire [17:0] BLDC_ESTIMATOR_1_ealpha_filtered_o;
    wire [17:0] BLDC_ESTIMATOR_1_ebeta_filtered_o;
    wire [17:0] BLDC_ESTIMATOR_1_pll_pi_out_o;
    wire [17:0] apb3_if_0_adc_scale_val_o;
    wire [11:0] adc_interface_0_result_ch0_o;
    wire [11:0] adc_interface_0_result_ch1_o;
    wire [17:0] apb3_if_0_adc_oc_thresh_o;
    wire [3:0] SEQ_CONTROLLER_1_state_o;
    wire [17:0] apb3_if_0_seq_cntl_cl_omega_o;
    wire [3:0] apb3_if_0_seq_cntl_config_o;
    wire [3:0] apb3_if_0_auto_restart_no_o;
    wire [5:0] apb3_if_0_adc_control_reg_val_o;
    wire [15:0] apb3_if_0_adc_channel_ch0_o;
    wire [15:0] apb3_if_0_adc_channel_ch1_o;
    wire [15:0] apb3_if_0_adc_channel_ch2_o;
    wire [15:0] apb3_if_0_adc_channel_ch3_o;
    wire [11:0] adc_measurements_0_adc_result_ch3_o;
    wire [11:0] adc_measurements_0_adc_result_ch2_o;
    wire FOC_TRANSFORMS_0_iclarke_done_o, SVM_0_done_o, 
        A0_PWM_VL_O_c_i_0, SEQ_CONTROLLER_0_cl_status_o, N_894_i_0, 
        RATE_LIMITER_0_rl_done_o, SPEED_ID_IQ_PI_1_iq_pi_done_o, 
        FOC_TRANSFORMS_0_park_done_o, GND, VCC, speed_pi_done_o, 
        SPEED_ID_IQ_PI_1_id_pi_done_o, ADC_SCALING_0_done_o, 
        N_2370_i_0, N_326_i_0, apb3_if_0_direction_config_o, 
        PWM_SCALING_1_done_o, PWM3PH_1_midmatch_o, PWM_AL_o, PWM_BL_o, 
        PWM_CL_o, done_o, FOC_TRANSFORMS_1_clarke_done_o_0, 
        FOC_TRANSFORMS_0_ipark_done_o, N_326, done_o_0, 
        adc_interface_0_results_rdy_o, ADC_SCALING_1_calib_done_o, 
        N_2197_i, SEQ_CONTROLLER_1_adc_start_o, 
        apb3_if_0_start_motor_o, apb3_if_0_fault_clr_o, 
        apb3_if_0_stop_motor_o;
    
    SVM MSC_i_0 (.reset_i(MC_System_0_FIC_0_LOCK), .sys_clk_i(
        MC_System_0_FIC_0_CLK), .start_i(
        FOC_TRANSFORMS_0_iclarke_done_o), .va_i({
        FOC_TRANSFORMS_0_va_o[17], FOC_TRANSFORMS_0_va_o[16], 
        FOC_TRANSFORMS_0_va_o[15], FOC_TRANSFORMS_0_va_o[14], 
        FOC_TRANSFORMS_0_va_o[13], FOC_TRANSFORMS_0_va_o[12], 
        FOC_TRANSFORMS_0_va_o[11], FOC_TRANSFORMS_0_va_o[10], 
        FOC_TRANSFORMS_0_va_o[9], FOC_TRANSFORMS_0_va_o[8], 
        FOC_TRANSFORMS_0_va_o[7], FOC_TRANSFORMS_0_va_o[6], 
        FOC_TRANSFORMS_0_va_o[5], FOC_TRANSFORMS_0_va_o[4], 
        FOC_TRANSFORMS_0_va_o[3], FOC_TRANSFORMS_0_va_o[2], 
        FOC_TRANSFORMS_0_va_o[1], FOC_TRANSFORMS_0_va_o[0]}), .vb_i({
        FOC_TRANSFORMS_0_vb_o[17], FOC_TRANSFORMS_0_vb_o[16], 
        FOC_TRANSFORMS_0_vb_o[15], FOC_TRANSFORMS_0_vb_o[14], 
        FOC_TRANSFORMS_0_vb_o[13], FOC_TRANSFORMS_0_vb_o[12], 
        FOC_TRANSFORMS_0_vb_o[11], FOC_TRANSFORMS_0_vb_o[10], 
        FOC_TRANSFORMS_0_vb_o[9], FOC_TRANSFORMS_0_vb_o[8], 
        FOC_TRANSFORMS_0_vb_o[7], FOC_TRANSFORMS_0_vb_o[6], 
        FOC_TRANSFORMS_0_vb_o[5], FOC_TRANSFORMS_0_vb_o[4], 
        FOC_TRANSFORMS_0_vb_o[3], FOC_TRANSFORMS_0_vb_o[2], 
        FOC_TRANSFORMS_0_vb_o[1], FOC_TRANSFORMS_0_vb_o[0]}), .vc_i({
        FOC_TRANSFORMS_0_vc_o[17], FOC_TRANSFORMS_0_vc_o[16], 
        FOC_TRANSFORMS_0_vc_o[15], FOC_TRANSFORMS_0_vc_o[14], 
        FOC_TRANSFORMS_0_vc_o[13], FOC_TRANSFORMS_0_vc_o[12], 
        FOC_TRANSFORMS_0_vc_o[11], FOC_TRANSFORMS_0_vc_o[10], 
        FOC_TRANSFORMS_0_vc_o[9], FOC_TRANSFORMS_0_vc_o[8], 
        FOC_TRANSFORMS_0_vc_o[7], FOC_TRANSFORMS_0_vc_o[6], 
        FOC_TRANSFORMS_0_vc_o[5], FOC_TRANSFORMS_0_vc_o[4], 
        FOC_TRANSFORMS_0_vc_o[3], FOC_TRANSFORMS_0_vc_o[2], 
        FOC_TRANSFORMS_0_vc_o[1], FOC_TRANSFORMS_0_vc_o[0]}), .va3h_o({
        SVM_0_va3h_o[17], SVM_0_va3h_o[16], SVM_0_va3h_o[15], 
        SVM_0_va3h_o[14], SVM_0_va3h_o[13], SVM_0_va3h_o[12], 
        SVM_0_va3h_o[11], SVM_0_va3h_o[10], SVM_0_va3h_o[9], 
        SVM_0_va3h_o[8], SVM_0_va3h_o[7], SVM_0_va3h_o[6], 
        SVM_0_va3h_o[5], SVM_0_va3h_o[4], SVM_0_va3h_o[3], 
        SVM_0_va3h_o[2], SVM_0_va3h_o[1], SVM_0_va3h_o[0]}), .vb3h_o({
        SVM_0_vb3h_o[17], SVM_0_vb3h_o[16], SVM_0_vb3h_o[15], 
        SVM_0_vb3h_o[14], SVM_0_vb3h_o[13], SVM_0_vb3h_o[12], 
        SVM_0_vb3h_o[11], SVM_0_vb3h_o[10], SVM_0_vb3h_o[9], 
        SVM_0_vb3h_o[8], SVM_0_vb3h_o[7], SVM_0_vb3h_o[6], 
        SVM_0_vb3h_o[5], SVM_0_vb3h_o[4], SVM_0_vb3h_o[3], 
        SVM_0_vb3h_o[2], SVM_0_vb3h_o[1], SVM_0_vb3h_o[0]}), .vc3h_o({
        SVM_0_vc3h_o[17], SVM_0_vc3h_o[16], SVM_0_vc3h_o[15], 
        SVM_0_vc3h_o[14], SVM_0_vc3h_o[13], SVM_0_vc3h_o[12], 
        SVM_0_vc3h_o[11], SVM_0_vc3h_o[10], SVM_0_vc3h_o[9], 
        SVM_0_vc3h_o[8], SVM_0_vc3h_o[7], SVM_0_vc3h_o[6], 
        SVM_0_vc3h_o[5], SVM_0_vc3h_o[4], SVM_0_vc3h_o[3], 
        SVM_0_vc3h_o[2], SVM_0_vc3h_o[1], SVM_0_vc3h_o[0]}), .done_o(
        SVM_0_done_o));
    GND GND_Z (.Y(GND));
    SEQ_CONTROLLER_Z1_layer1_1 SEQ_CONTROLLER_0 (
        .SEQ_CONTROLLER_1_state_o({SEQ_CONTROLLER_1_state_o[3], 
        SEQ_CONTROLLER_1_state_o[2], SEQ_CONTROLLER_1_state_o[1], 
        SEQ_CONTROLLER_1_state_o[0]}), .apb3_if_0_seq_cntl_cl_omega_o({
        apb3_if_0_seq_cntl_cl_omega_o[17], 
        apb3_if_0_seq_cntl_cl_omega_o[16], 
        apb3_if_0_seq_cntl_cl_omega_o[15], 
        apb3_if_0_seq_cntl_cl_omega_o[14], 
        apb3_if_0_seq_cntl_cl_omega_o[13], 
        apb3_if_0_seq_cntl_cl_omega_o[12], 
        apb3_if_0_seq_cntl_cl_omega_o[11], 
        apb3_if_0_seq_cntl_cl_omega_o[10], 
        apb3_if_0_seq_cntl_cl_omega_o[9], 
        apb3_if_0_seq_cntl_cl_omega_o[8], 
        apb3_if_0_seq_cntl_cl_omega_o[7], 
        apb3_if_0_seq_cntl_cl_omega_o[6], 
        apb3_if_0_seq_cntl_cl_omega_o[5], 
        apb3_if_0_seq_cntl_cl_omega_o[4], 
        apb3_if_0_seq_cntl_cl_omega_o[3], 
        apb3_if_0_seq_cntl_cl_omega_o[2], 
        apb3_if_0_seq_cntl_cl_omega_o[1], 
        apb3_if_0_seq_cntl_cl_omega_o[0]}), .RATE_LIMITER_0_rl_out_o({
        RATE_LIMITER_0_rl_out_o[17], RATE_LIMITER_0_rl_out_o[16], 
        RATE_LIMITER_0_rl_out_o[15], RATE_LIMITER_0_rl_out_o[14], 
        RATE_LIMITER_0_rl_out_o[13], RATE_LIMITER_0_rl_out_o[12], 
        RATE_LIMITER_0_rl_out_o[11], RATE_LIMITER_0_rl_out_o[10], 
        RATE_LIMITER_0_rl_out_o[9], RATE_LIMITER_0_rl_out_o[8], 
        RATE_LIMITER_0_rl_out_o[7], RATE_LIMITER_0_rl_out_o[6], 
        RATE_LIMITER_0_rl_out_o[5], RATE_LIMITER_0_rl_out_o[4], 
        RATE_LIMITER_0_rl_out_o[3], RATE_LIMITER_0_rl_out_o[2], 
        RATE_LIMITER_0_rl_out_o[1], RATE_LIMITER_0_rl_out_o[0]}), 
        .SPEED_ID_IQ_PI_1_iq_pi_output_o({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]}), 
        .apb3_if_0_seq_cntl_config_o({apb3_if_0_seq_cntl_config_o[3], 
        apb3_if_0_seq_cntl_config_o[2], apb3_if_0_seq_cntl_config_o[1], 
        apb3_if_0_seq_cntl_config_o[0]}), .apb3_if_0_auto_restart_no_o({
        apb3_if_0_auto_restart_no_o[3], apb3_if_0_auto_restart_no_o[2], 
        apb3_if_0_auto_restart_no_o[1], apb3_if_0_auto_restart_no_o[0]})
        , .MC_System_0_FIC_0_LOCK(MC_System_0_FIC_0_LOCK), 
        .MC_System_0_FIC_0_CLK(MC_System_0_FIC_0_CLK), 
        .SEQ_CONTROLLER_1_adc_start_o(SEQ_CONTROLLER_1_adc_start_o), 
        .SEQ_CONTROLLER_0_cl_status_o(SEQ_CONTROLLER_0_cl_status_o), 
        .apb3_if_0_start_motor_o(apb3_if_0_start_motor_o), 
        .apb3_if_0_fault_clr_o(apb3_if_0_fault_clr_o), 
        .ADC_SCALING_1_calib_done_o(ADC_SCALING_1_calib_done_o), 
        .apb3_if_0_stop_motor_o(apb3_if_0_stop_motor_o), .N_2197_i(
        N_2197_i), .A0_PWM_VL_O_c_i_0(A0_PWM_VL_O_c_i_0), .N_326_i_0(
        N_326_i_0), .PWM_SCALING_1_done_o(PWM_SCALING_1_done_o), 
        .N_2370_i_0(N_2370_i_0), .N_326(N_326), .A0_PWM_VL_O_c(
        A0_PWM_VL_O_c), .N_894_i_0(N_894_i_0), .PWM3PH_1_midmatch_o(
        PWM3PH_1_midmatch_o));
    RATE_LIMITER MSC_i_9 (.reset_i(MC_System_0_FIC_0_LOCK), .sys_clk_i(
        MC_System_0_FIC_0_CLK), .start_i(ADC_SCALING_0_done_o), 
        .soft_stop_i(N_2370_i_0), .reset_rl_i(N_326_i_0), .direction_i(
        apb3_if_0_direction_config_o), .slew_count_i({
        apb3_if_0_rate_limit_slew_cnt_o[17], 
        apb3_if_0_rate_limit_slew_cnt_o[16], 
        apb3_if_0_rate_limit_slew_cnt_o[15], 
        apb3_if_0_rate_limit_slew_cnt_o[14], 
        apb3_if_0_rate_limit_slew_cnt_o[13], 
        apb3_if_0_rate_limit_slew_cnt_o[12], 
        apb3_if_0_rate_limit_slew_cnt_o[11], 
        apb3_if_0_rate_limit_slew_cnt_o[10], 
        apb3_if_0_rate_limit_slew_cnt_o[9], 
        apb3_if_0_rate_limit_slew_cnt_o[8], 
        apb3_if_0_rate_limit_slew_cnt_o[7], 
        apb3_if_0_rate_limit_slew_cnt_o[6], 
        apb3_if_0_rate_limit_slew_cnt_o[5], 
        apb3_if_0_rate_limit_slew_cnt_o[4], 
        apb3_if_0_rate_limit_slew_cnt_o[3], 
        apb3_if_0_rate_limit_slew_cnt_o[2], 
        apb3_if_0_rate_limit_slew_cnt_o[1], 
        apb3_if_0_rate_limit_slew_cnt_o[0]}), .rate_count_i({
        apb3_if_0_rate_limit_rate_cnt_o[17], 
        apb3_if_0_rate_limit_rate_cnt_o[16], 
        apb3_if_0_rate_limit_rate_cnt_o[15], 
        apb3_if_0_rate_limit_rate_cnt_o[14], 
        apb3_if_0_rate_limit_rate_cnt_o[13], 
        apb3_if_0_rate_limit_rate_cnt_o[12], 
        apb3_if_0_rate_limit_rate_cnt_o[11], 
        apb3_if_0_rate_limit_rate_cnt_o[10], 
        apb3_if_0_rate_limit_rate_cnt_o[9], 
        apb3_if_0_rate_limit_rate_cnt_o[8], 
        apb3_if_0_rate_limit_rate_cnt_o[7], 
        apb3_if_0_rate_limit_rate_cnt_o[6], 
        apb3_if_0_rate_limit_rate_cnt_o[5], 
        apb3_if_0_rate_limit_rate_cnt_o[4], 
        apb3_if_0_rate_limit_rate_cnt_o[3], 
        apb3_if_0_rate_limit_rate_cnt_o[2], 
        apb3_if_0_rate_limit_rate_cnt_o[1], 
        apb3_if_0_rate_limit_rate_cnt_o[0]}), .rl_in_i({
        apb3_if_0_rate_limit_ref_in_o[17], 
        apb3_if_0_rate_limit_ref_in_o[16], 
        apb3_if_0_rate_limit_ref_in_o[15], 
        apb3_if_0_rate_limit_ref_in_o[14], 
        apb3_if_0_rate_limit_ref_in_o[13], 
        apb3_if_0_rate_limit_ref_in_o[12], 
        apb3_if_0_rate_limit_ref_in_o[11], 
        apb3_if_0_rate_limit_ref_in_o[10], 
        apb3_if_0_rate_limit_ref_in_o[9], 
        apb3_if_0_rate_limit_ref_in_o[8], 
        apb3_if_0_rate_limit_ref_in_o[7], 
        apb3_if_0_rate_limit_ref_in_o[6], 
        apb3_if_0_rate_limit_ref_in_o[5], 
        apb3_if_0_rate_limit_ref_in_o[4], 
        apb3_if_0_rate_limit_ref_in_o[3], 
        apb3_if_0_rate_limit_ref_in_o[2], 
        apb3_if_0_rate_limit_ref_in_o[1], 
        apb3_if_0_rate_limit_ref_in_o[0]}), .rl_out_o({
        RATE_LIMITER_0_rl_out_o[17], RATE_LIMITER_0_rl_out_o[16], 
        RATE_LIMITER_0_rl_out_o[15], RATE_LIMITER_0_rl_out_o[14], 
        RATE_LIMITER_0_rl_out_o[13], RATE_LIMITER_0_rl_out_o[12], 
        RATE_LIMITER_0_rl_out_o[11], RATE_LIMITER_0_rl_out_o[10], 
        RATE_LIMITER_0_rl_out_o[9], RATE_LIMITER_0_rl_out_o[8], 
        RATE_LIMITER_0_rl_out_o[7], RATE_LIMITER_0_rl_out_o[6], 
        RATE_LIMITER_0_rl_out_o[5], RATE_LIMITER_0_rl_out_o[4], 
        RATE_LIMITER_0_rl_out_o[3], RATE_LIMITER_0_rl_out_o[2], 
        RATE_LIMITER_0_rl_out_o[1], RATE_LIMITER_0_rl_out_o[0]}), 
        .rl_done_o(RATE_LIMITER_0_rl_done_o));
    ADC_SCALING_0s_12s_2s_8192_5_44s_0_2_3_1 MSC_i_14 (.reset_i(
        MC_System_0_FIC_0_LOCK), .sys_clk_i(MC_System_0_FIC_0_CLK), 
        .adc_results_rdy_i(adc_interface_0_results_rdy_o), 
        .adc_scale_val_i({apb3_if_0_adc_scale_val_o[17], 
        apb3_if_0_adc_scale_val_o[16], apb3_if_0_adc_scale_val_o[15], 
        apb3_if_0_adc_scale_val_o[14], apb3_if_0_adc_scale_val_o[13], 
        apb3_if_0_adc_scale_val_o[12], apb3_if_0_adc_scale_val_o[11], 
        apb3_if_0_adc_scale_val_o[10], apb3_if_0_adc_scale_val_o[9], 
        apb3_if_0_adc_scale_val_o[8], apb3_if_0_adc_scale_val_o[7], 
        apb3_if_0_adc_scale_val_o[6], apb3_if_0_adc_scale_val_o[5], 
        apb3_if_0_adc_scale_val_o[4], apb3_if_0_adc_scale_val_o[3], 
        apb3_if_0_adc_scale_val_o[2], apb3_if_0_adc_scale_val_o[1], 
        apb3_if_0_adc_scale_val_o[0]}), .adc_result_ch0_i({
        adc_interface_0_result_ch0_o[11], 
        adc_interface_0_result_ch0_o[10], 
        adc_interface_0_result_ch0_o[9], 
        adc_interface_0_result_ch0_o[8], 
        adc_interface_0_result_ch0_o[7], 
        adc_interface_0_result_ch0_o[6], 
        adc_interface_0_result_ch0_o[5], 
        adc_interface_0_result_ch0_o[4], 
        adc_interface_0_result_ch0_o[3], 
        adc_interface_0_result_ch0_o[2], 
        adc_interface_0_result_ch0_o[1], 
        adc_interface_0_result_ch0_o[0]}), .adc_result_ch1_i({
        adc_interface_0_result_ch1_o[11], 
        adc_interface_0_result_ch1_o[10], 
        adc_interface_0_result_ch1_o[9], 
        adc_interface_0_result_ch1_o[8], 
        adc_interface_0_result_ch1_o[7], 
        adc_interface_0_result_ch1_o[6], 
        adc_interface_0_result_ch1_o[5], 
        adc_interface_0_result_ch1_o[4], 
        adc_interface_0_result_ch1_o[3], 
        adc_interface_0_result_ch1_o[2], 
        adc_interface_0_result_ch1_o[1], 
        adc_interface_0_result_ch1_o[0]}), .fault_threshold_i({
        apb3_if_0_adc_oc_thresh_o[17], apb3_if_0_adc_oc_thresh_o[16], 
        apb3_if_0_adc_oc_thresh_o[15], apb3_if_0_adc_oc_thresh_o[14], 
        apb3_if_0_adc_oc_thresh_o[13], apb3_if_0_adc_oc_thresh_o[12], 
        apb3_if_0_adc_oc_thresh_o[11], apb3_if_0_adc_oc_thresh_o[10], 
        apb3_if_0_adc_oc_thresh_o[9], apb3_if_0_adc_oc_thresh_o[8], 
        apb3_if_0_adc_oc_thresh_o[7], apb3_if_0_adc_oc_thresh_o[6], 
        apb3_if_0_adc_oc_thresh_o[5], apb3_if_0_adc_oc_thresh_o[4], 
        apb3_if_0_adc_oc_thresh_o[3], apb3_if_0_adc_oc_thresh_o[2], 
        apb3_if_0_adc_oc_thresh_o[1], apb3_if_0_adc_oc_thresh_o[0]}), 
        .done_o(ADC_SCALING_0_done_o), .calib_done_o(
        ADC_SCALING_1_calib_done_o), .over_current_fault_o(N_2197_i), 
        .ia_adc_o({ADC_SCALING_1_ia_adc_o[17], 
        ADC_SCALING_1_ia_adc_o[16], ADC_SCALING_1_ia_adc_o[15], 
        ADC_SCALING_1_ia_adc_o[14], ADC_SCALING_1_ia_adc_o[13], 
        ADC_SCALING_1_ia_adc_o[12], ADC_SCALING_1_ia_adc_o[11], 
        ADC_SCALING_1_ia_adc_o[10], ADC_SCALING_1_ia_adc_o[9], 
        ADC_SCALING_1_ia_adc_o[8], ADC_SCALING_1_ia_adc_o[7], 
        ADC_SCALING_1_ia_adc_o[6], ADC_SCALING_1_ia_adc_o[5], 
        ADC_SCALING_1_ia_adc_o[4], ADC_SCALING_1_ia_adc_o[3], 
        ADC_SCALING_1_ia_adc_o[2], ADC_SCALING_1_ia_adc_o[1], 
        ADC_SCALING_1_ia_adc_o[0]}), .ib_adc_o({
        ADC_SCALING_1_ib_adc_o[17], ADC_SCALING_1_ib_adc_o[16], 
        ADC_SCALING_1_ib_adc_o[15], ADC_SCALING_1_ib_adc_o[14], 
        ADC_SCALING_1_ib_adc_o[13], ADC_SCALING_1_ib_adc_o[12], 
        ADC_SCALING_1_ib_adc_o[11], ADC_SCALING_1_ib_adc_o[10], 
        ADC_SCALING_1_ib_adc_o[9], ADC_SCALING_1_ib_adc_o[8], 
        ADC_SCALING_1_ib_adc_o[7], ADC_SCALING_1_ib_adc_o[6], 
        ADC_SCALING_1_ib_adc_o[5], ADC_SCALING_1_ib_adc_o[4], 
        ADC_SCALING_1_ib_adc_o[3], ADC_SCALING_1_ib_adc_o[2], 
        ADC_SCALING_1_ib_adc_o[1], ADC_SCALING_1_ib_adc_o[0]}));
    BLDC_ESTIMATOR_18s_2s_34s_44s MSC_i_20 (.reset_i(
        MC_System_0_FIC_0_LOCK), .sys_clk_i(MC_System_0_FIC_0_CLK), 
        .start_i(FOC_TRANSFORMS_0_ipark_done_o), .angle_pi_en_i(N_326), 
        .v_alpha_i({FOC_TRANSFORMS_0_valpha_o[17], 
        FOC_TRANSFORMS_0_valpha_o[16], FOC_TRANSFORMS_0_valpha_o[15], 
        FOC_TRANSFORMS_0_valpha_o[14], FOC_TRANSFORMS_0_valpha_o[13], 
        FOC_TRANSFORMS_0_valpha_o[12], FOC_TRANSFORMS_0_valpha_o[11], 
        FOC_TRANSFORMS_0_valpha_o[10], FOC_TRANSFORMS_0_valpha_o[9], 
        FOC_TRANSFORMS_0_valpha_o[8], FOC_TRANSFORMS_0_valpha_o[7], 
        FOC_TRANSFORMS_0_valpha_o[6], FOC_TRANSFORMS_0_valpha_o[5], 
        FOC_TRANSFORMS_0_valpha_o[4], FOC_TRANSFORMS_0_valpha_o[3], 
        FOC_TRANSFORMS_0_valpha_o[2], FOC_TRANSFORMS_0_valpha_o[1], 
        FOC_TRANSFORMS_0_valpha_o[0]}), .v_beta_i({
        FOC_TRANSFORMS_0_vbeta_o[17], FOC_TRANSFORMS_0_vbeta_o[16], 
        FOC_TRANSFORMS_0_vbeta_o[15], FOC_TRANSFORMS_0_vbeta_o[14], 
        FOC_TRANSFORMS_0_vbeta_o[13], FOC_TRANSFORMS_0_vbeta_o[12], 
        FOC_TRANSFORMS_0_vbeta_o[11], FOC_TRANSFORMS_0_vbeta_o[10], 
        FOC_TRANSFORMS_0_vbeta_o[9], FOC_TRANSFORMS_0_vbeta_o[8], 
        FOC_TRANSFORMS_0_vbeta_o[7], FOC_TRANSFORMS_0_vbeta_o[6], 
        FOC_TRANSFORMS_0_vbeta_o[5], FOC_TRANSFORMS_0_vbeta_o[4], 
        FOC_TRANSFORMS_0_vbeta_o[3], FOC_TRANSFORMS_0_vbeta_o[2], 
        FOC_TRANSFORMS_0_vbeta_o[1], FOC_TRANSFORMS_0_vbeta_o[0]}), 
        .i_alpha_i({FOC_TRANSFORMS_0_ialpha_o[17], 
        FOC_TRANSFORMS_0_ialpha_o[16], FOC_TRANSFORMS_0_ialpha_o[15], 
        FOC_TRANSFORMS_0_ialpha_o[14], FOC_TRANSFORMS_0_ialpha_o[13], 
        FOC_TRANSFORMS_0_ialpha_o[12], FOC_TRANSFORMS_0_ialpha_o[11], 
        FOC_TRANSFORMS_0_ialpha_o[10], FOC_TRANSFORMS_0_ialpha_o[9], 
        FOC_TRANSFORMS_0_ialpha_o[8], FOC_TRANSFORMS_0_ialpha_o[7], 
        FOC_TRANSFORMS_0_ialpha_o[6], FOC_TRANSFORMS_0_ialpha_o[5], 
        FOC_TRANSFORMS_0_ialpha_o[4], FOC_TRANSFORMS_0_ialpha_o[3], 
        FOC_TRANSFORMS_0_ialpha_o[2], FOC_TRANSFORMS_0_ialpha_o[1], 
        FOC_TRANSFORMS_0_ialpha_o[0]}), .i_beta_i({
        FOC_TRANSFORMS_0_ibeta_o[17], FOC_TRANSFORMS_0_ibeta_o[16], 
        FOC_TRANSFORMS_0_ibeta_o[15], FOC_TRANSFORMS_0_ibeta_o[14], 
        FOC_TRANSFORMS_0_ibeta_o[13], FOC_TRANSFORMS_0_ibeta_o[12], 
        FOC_TRANSFORMS_0_ibeta_o[11], FOC_TRANSFORMS_0_ibeta_o[10], 
        FOC_TRANSFORMS_0_ibeta_o[9], FOC_TRANSFORMS_0_ibeta_o[8], 
        FOC_TRANSFORMS_0_ibeta_o[7], FOC_TRANSFORMS_0_ibeta_o[6], 
        FOC_TRANSFORMS_0_ibeta_o[5], FOC_TRANSFORMS_0_ibeta_o[4], 
        FOC_TRANSFORMS_0_ibeta_o[3], FOC_TRANSFORMS_0_ibeta_o[2], 
        FOC_TRANSFORMS_0_ibeta_o[1], FOC_TRANSFORMS_0_ibeta_o[0]}), 
        .Ls_by_Ts_pu_i({apb3_if_0_Ls_by_Ts_pu_o[17], 
        apb3_if_0_Ls_by_Ts_pu_o[16], apb3_if_0_Ls_by_Ts_pu_o[15], 
        apb3_if_0_Ls_by_Ts_pu_o[14], apb3_if_0_Ls_by_Ts_pu_o[13], 
        apb3_if_0_Ls_by_Ts_pu_o[12], apb3_if_0_Ls_by_Ts_pu_o[11], 
        apb3_if_0_Ls_by_Ts_pu_o[10], apb3_if_0_Ls_by_Ts_pu_o[9], 
        apb3_if_0_Ls_by_Ts_pu_o[8], apb3_if_0_Ls_by_Ts_pu_o[7], 
        apb3_if_0_Ls_by_Ts_pu_o[6], apb3_if_0_Ls_by_Ts_pu_o[5], 
        apb3_if_0_Ls_by_Ts_pu_o[4], apb3_if_0_Ls_by_Ts_pu_o[3], 
        apb3_if_0_Ls_by_Ts_pu_o[2], apb3_if_0_Ls_by_Ts_pu_o[1], 
        apb3_if_0_Ls_by_Ts_pu_o[0]}), .Rs_pu_i({apb3_if_0_Rs_pu_o[17], 
        apb3_if_0_Rs_pu_o[16], apb3_if_0_Rs_pu_o[15], 
        apb3_if_0_Rs_pu_o[14], apb3_if_0_Rs_pu_o[13], 
        apb3_if_0_Rs_pu_o[12], apb3_if_0_Rs_pu_o[11], 
        apb3_if_0_Rs_pu_o[10], apb3_if_0_Rs_pu_o[9], 
        apb3_if_0_Rs_pu_o[8], apb3_if_0_Rs_pu_o[7], 
        apb3_if_0_Rs_pu_o[6], apb3_if_0_Rs_pu_o[5], 
        apb3_if_0_Rs_pu_o[4], apb3_if_0_Rs_pu_o[3], 
        apb3_if_0_Rs_pu_o[2], apb3_if_0_Rs_pu_o[1], 
        apb3_if_0_Rs_pu_o[0]}), .ealpha_filter_factor_i({
        apb3_if_0_filter_factor_bemf_o[3], 
        apb3_if_0_filter_factor_bemf_o[2], 
        apb3_if_0_filter_factor_bemf_o[1], 
        apb3_if_0_filter_factor_bemf_o[0]}), .ebeta_filter_factor_i({
        GND, GND, GND, GND}), .pll_theta_factor_i({
        apb3_if_0_olmng_theta_factor_o[17], 
        apb3_if_0_olmng_theta_factor_o[16], 
        apb3_if_0_olmng_theta_factor_o[15], 
        apb3_if_0_olmng_theta_factor_o[14], 
        apb3_if_0_olmng_theta_factor_o[13], 
        apb3_if_0_olmng_theta_factor_o[12], 
        apb3_if_0_olmng_theta_factor_o[11], 
        apb3_if_0_olmng_theta_factor_o[10], 
        apb3_if_0_olmng_theta_factor_o[9], 
        apb3_if_0_olmng_theta_factor_o[8], 
        apb3_if_0_olmng_theta_factor_o[7], 
        apb3_if_0_olmng_theta_factor_o[6], 
        apb3_if_0_olmng_theta_factor_o[5], 
        apb3_if_0_olmng_theta_factor_o[4], 
        apb3_if_0_olmng_theta_factor_o[3], 
        apb3_if_0_olmng_theta_factor_o[2], 
        apb3_if_0_olmng_theta_factor_o[1], 
        apb3_if_0_olmng_theta_factor_o[0]}), .angle_pi_ki_i({
        apb3_if_0_angle_ki_o[17], apb3_if_0_angle_ki_o[16], 
        apb3_if_0_angle_ki_o[15], apb3_if_0_angle_ki_o[14], 
        apb3_if_0_angle_ki_o[13], apb3_if_0_angle_ki_o[12], 
        apb3_if_0_angle_ki_o[11], apb3_if_0_angle_ki_o[10], 
        apb3_if_0_angle_ki_o[9], apb3_if_0_angle_ki_o[8], 
        apb3_if_0_angle_ki_o[7], apb3_if_0_angle_ki_o[6], 
        apb3_if_0_angle_ki_o[5], apb3_if_0_angle_ki_o[4], 
        apb3_if_0_angle_ki_o[3], apb3_if_0_angle_ki_o[2], 
        apb3_if_0_angle_ki_o[1], apb3_if_0_angle_ki_o[0]}), 
        .angle_pi_kp_i({apb3_if_0_angle_kp_o[17], 
        apb3_if_0_angle_kp_o[16], apb3_if_0_angle_kp_o[15], 
        apb3_if_0_angle_kp_o[14], apb3_if_0_angle_kp_o[13], 
        apb3_if_0_angle_kp_o[12], apb3_if_0_angle_kp_o[11], 
        apb3_if_0_angle_kp_o[10], apb3_if_0_angle_kp_o[9], 
        apb3_if_0_angle_kp_o[8], apb3_if_0_angle_kp_o[7], 
        apb3_if_0_angle_kp_o[6], apb3_if_0_angle_kp_o[5], 
        apb3_if_0_angle_kp_o[4], apb3_if_0_angle_kp_o[3], 
        apb3_if_0_angle_kp_o[2], apb3_if_0_angle_kp_o[1], 
        apb3_if_0_angle_kp_o[0]}), .omega_filter_factor_i({
        apb3_if_0_filter_factor_omega_o[3], 
        apb3_if_0_filter_factor_omega_o[2], 
        apb3_if_0_filter_factor_omega_o[1], 
        apb3_if_0_filter_factor_omega_o[0]}), .done_o(done_o_0), 
        .theta_o({BLDC_ESTIMATOR_1_theta_o[17], 
        BLDC_ESTIMATOR_1_theta_o[16], BLDC_ESTIMATOR_1_theta_o[15], 
        BLDC_ESTIMATOR_1_theta_o[14], BLDC_ESTIMATOR_1_theta_o[13], 
        BLDC_ESTIMATOR_1_theta_o[12], BLDC_ESTIMATOR_1_theta_o[11], 
        BLDC_ESTIMATOR_1_theta_o[10], BLDC_ESTIMATOR_1_theta_o[9], 
        BLDC_ESTIMATOR_1_theta_o[8], BLDC_ESTIMATOR_1_theta_o[7], 
        BLDC_ESTIMATOR_1_theta_o[6], BLDC_ESTIMATOR_1_theta_o[5], 
        BLDC_ESTIMATOR_1_theta_o[4], BLDC_ESTIMATOR_1_theta_o[3], 
        BLDC_ESTIMATOR_1_theta_o[2], BLDC_ESTIMATOR_1_theta_o[1], 
        BLDC_ESTIMATOR_1_theta_o[0]}), .ealpha_o({
        BLDC_ESTIMATOR_1_ealpha_o[17], BLDC_ESTIMATOR_1_ealpha_o[16], 
        BLDC_ESTIMATOR_1_ealpha_o[15], BLDC_ESTIMATOR_1_ealpha_o[14], 
        BLDC_ESTIMATOR_1_ealpha_o[13], BLDC_ESTIMATOR_1_ealpha_o[12], 
        BLDC_ESTIMATOR_1_ealpha_o[11], BLDC_ESTIMATOR_1_ealpha_o[10], 
        BLDC_ESTIMATOR_1_ealpha_o[9], BLDC_ESTIMATOR_1_ealpha_o[8], 
        BLDC_ESTIMATOR_1_ealpha_o[7], BLDC_ESTIMATOR_1_ealpha_o[6], 
        BLDC_ESTIMATOR_1_ealpha_o[5], BLDC_ESTIMATOR_1_ealpha_o[4], 
        BLDC_ESTIMATOR_1_ealpha_o[3], BLDC_ESTIMATOR_1_ealpha_o[2], 
        BLDC_ESTIMATOR_1_ealpha_o[1], BLDC_ESTIMATOR_1_ealpha_o[0]}), 
        .ebeta_o({BLDC_ESTIMATOR_1_ebeta_o[17], 
        BLDC_ESTIMATOR_1_ebeta_o[16], BLDC_ESTIMATOR_1_ebeta_o[15], 
        BLDC_ESTIMATOR_1_ebeta_o[14], BLDC_ESTIMATOR_1_ebeta_o[13], 
        BLDC_ESTIMATOR_1_ebeta_o[12], BLDC_ESTIMATOR_1_ebeta_o[11], 
        BLDC_ESTIMATOR_1_ebeta_o[10], BLDC_ESTIMATOR_1_ebeta_o[9], 
        BLDC_ESTIMATOR_1_ebeta_o[8], BLDC_ESTIMATOR_1_ebeta_o[7], 
        BLDC_ESTIMATOR_1_ebeta_o[6], BLDC_ESTIMATOR_1_ebeta_o[5], 
        BLDC_ESTIMATOR_1_ebeta_o[4], BLDC_ESTIMATOR_1_ebeta_o[3], 
        BLDC_ESTIMATOR_1_ebeta_o[2], BLDC_ESTIMATOR_1_ebeta_o[1], 
        BLDC_ESTIMATOR_1_ebeta_o[0]}), .ealpha_filtered_o({
        BLDC_ESTIMATOR_1_ealpha_filtered_o[17], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[16], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[15], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[14], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[13], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[12], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[11], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[10], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[9], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[8], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[7], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[6], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[5], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[4], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[3], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[2], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[1], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[0]}), .ebeta_filtered_o({
        BLDC_ESTIMATOR_1_ebeta_filtered_o[17], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[16], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[15], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[14], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[13], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[12], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[11], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[10], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[9], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[8], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[7], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[6], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[5], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[4], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[3], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[2], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[1], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[0]}), .pll_pi_out_o({
        BLDC_ESTIMATOR_1_pll_pi_out_o[17], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[16], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[15], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[14], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[13], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[12], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[11], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[10], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[9], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[8], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[7], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[6], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[5], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[4], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[3], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[2], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[1], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[0]}), .speed_filtered_o({
        BLDC_ESTIMATOR_0_speed_filtered_o[17], 
        BLDC_ESTIMATOR_0_speed_filtered_o[16], 
        BLDC_ESTIMATOR_0_speed_filtered_o[15], 
        BLDC_ESTIMATOR_0_speed_filtered_o[14], 
        BLDC_ESTIMATOR_0_speed_filtered_o[13], 
        BLDC_ESTIMATOR_0_speed_filtered_o[12], 
        BLDC_ESTIMATOR_0_speed_filtered_o[11], 
        BLDC_ESTIMATOR_0_speed_filtered_o[10], 
        BLDC_ESTIMATOR_0_speed_filtered_o[9], 
        BLDC_ESTIMATOR_0_speed_filtered_o[8], 
        BLDC_ESTIMATOR_0_speed_filtered_o[7], 
        BLDC_ESTIMATOR_0_speed_filtered_o[6], 
        BLDC_ESTIMATOR_0_speed_filtered_o[5], 
        BLDC_ESTIMATOR_0_speed_filtered_o[4], 
        BLDC_ESTIMATOR_0_speed_filtered_o[3], 
        BLDC_ESTIMATOR_0_speed_filtered_o[2], 
        BLDC_ESTIMATOR_0_speed_filtered_o[1], 
        BLDC_ESTIMATOR_0_speed_filtered_o[0]}));
    OLMNG_2s_13s_44s_0_2_3 MSC_i_11 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FIC_0_CLK), .start_i(
        RATE_LIMITER_0_rl_done_o), .clear_buffer_i(A0_PWM_VL_O_c_i_0), 
        .direction_config_i(apb3_if_0_direction_config_o), 
        .cl_status_i(SEQ_CONTROLLER_0_cl_status_o), .theta_factor_i({
        apb3_if_0_olmng_theta_factor_o[17], 
        apb3_if_0_olmng_theta_factor_o[16], 
        apb3_if_0_olmng_theta_factor_o[15], 
        apb3_if_0_olmng_theta_factor_o[14], 
        apb3_if_0_olmng_theta_factor_o[13], 
        apb3_if_0_olmng_theta_factor_o[12], 
        apb3_if_0_olmng_theta_factor_o[11], 
        apb3_if_0_olmng_theta_factor_o[10], 
        apb3_if_0_olmng_theta_factor_o[9], 
        apb3_if_0_olmng_theta_factor_o[8], 
        apb3_if_0_olmng_theta_factor_o[7], 
        apb3_if_0_olmng_theta_factor_o[6], 
        apb3_if_0_olmng_theta_factor_o[5], 
        apb3_if_0_olmng_theta_factor_o[4], 
        apb3_if_0_olmng_theta_factor_o[3], 
        apb3_if_0_olmng_theta_factor_o[2], 
        apb3_if_0_olmng_theta_factor_o[1], 
        apb3_if_0_olmng_theta_factor_o[0]}), .speed_ref_i({
        RATE_LIMITER_0_rl_out_o[17], RATE_LIMITER_0_rl_out_o[16], 
        RATE_LIMITER_0_rl_out_o[15], RATE_LIMITER_0_rl_out_o[14], 
        RATE_LIMITER_0_rl_out_o[13], RATE_LIMITER_0_rl_out_o[12], 
        RATE_LIMITER_0_rl_out_o[11], RATE_LIMITER_0_rl_out_o[10], 
        RATE_LIMITER_0_rl_out_o[9], RATE_LIMITER_0_rl_out_o[8], 
        RATE_LIMITER_0_rl_out_o[7], RATE_LIMITER_0_rl_out_o[6], 
        RATE_LIMITER_0_rl_out_o[5], RATE_LIMITER_0_rl_out_o[4], 
        RATE_LIMITER_0_rl_out_o[3], RATE_LIMITER_0_rl_out_o[2], 
        RATE_LIMITER_0_rl_out_o[1], RATE_LIMITER_0_rl_out_o[0]}), 
        .dv_i({apb3_if_0_olmng_dv_o[17], apb3_if_0_olmng_dv_o[16], 
        apb3_if_0_olmng_dv_o[15], apb3_if_0_olmng_dv_o[14], 
        apb3_if_0_olmng_dv_o[13], apb3_if_0_olmng_dv_o[12], 
        apb3_if_0_olmng_dv_o[11], apb3_if_0_olmng_dv_o[10], 
        apb3_if_0_olmng_dv_o[9], apb3_if_0_olmng_dv_o[8], 
        apb3_if_0_olmng_dv_o[7], apb3_if_0_olmng_dv_o[6], 
        apb3_if_0_olmng_dv_o[5], apb3_if_0_olmng_dv_o[4], 
        apb3_if_0_olmng_dv_o[3], apb3_if_0_olmng_dv_o[2], 
        apb3_if_0_olmng_dv_o[1], apb3_if_0_olmng_dv_o[0]}), 
        .theta_cl_i({BLDC_ESTIMATOR_1_theta_o[17], 
        BLDC_ESTIMATOR_1_theta_o[16], BLDC_ESTIMATOR_1_theta_o[15], 
        BLDC_ESTIMATOR_1_theta_o[14], BLDC_ESTIMATOR_1_theta_o[13], 
        BLDC_ESTIMATOR_1_theta_o[12], BLDC_ESTIMATOR_1_theta_o[11], 
        BLDC_ESTIMATOR_1_theta_o[10], BLDC_ESTIMATOR_1_theta_o[9], 
        BLDC_ESTIMATOR_1_theta_o[8], BLDC_ESTIMATOR_1_theta_o[7], 
        BLDC_ESTIMATOR_1_theta_o[6], BLDC_ESTIMATOR_1_theta_o[5], 
        BLDC_ESTIMATOR_1_theta_o[4], BLDC_ESTIMATOR_1_theta_o[3], 
        BLDC_ESTIMATOR_1_theta_o[2], BLDC_ESTIMATOR_1_theta_o[1], 
        BLDC_ESTIMATOR_1_theta_o[0]}), .iq_ref_in_i({
        apb3_if_0_olmng_iq_ref_in_o[17], 
        apb3_if_0_olmng_iq_ref_in_o[16], 
        apb3_if_0_olmng_iq_ref_in_o[15], 
        apb3_if_0_olmng_iq_ref_in_o[14], 
        apb3_if_0_olmng_iq_ref_in_o[13], 
        apb3_if_0_olmng_iq_ref_in_o[12], 
        apb3_if_0_olmng_iq_ref_in_o[11], 
        apb3_if_0_olmng_iq_ref_in_o[10], 
        apb3_if_0_olmng_iq_ref_in_o[9], apb3_if_0_olmng_iq_ref_in_o[8], 
        apb3_if_0_olmng_iq_ref_in_o[7], apb3_if_0_olmng_iq_ref_in_o[6], 
        apb3_if_0_olmng_iq_ref_in_o[5], apb3_if_0_olmng_iq_ref_in_o[4], 
        apb3_if_0_olmng_iq_ref_in_o[3], apb3_if_0_olmng_iq_ref_in_o[2], 
        apb3_if_0_olmng_iq_ref_in_o[1], apb3_if_0_olmng_iq_ref_in_o[0]})
        , .done_o(done_o), .theta_o({OLMNG_1_theta_o[17], 
        OLMNG_1_theta_o[16], OLMNG_1_theta_o[15], OLMNG_1_theta_o[14], 
        OLMNG_1_theta_o[13], OLMNG_1_theta_o[12], OLMNG_1_theta_o[11], 
        OLMNG_1_theta_o[10], OLMNG_1_theta_o[9], OLMNG_1_theta_o[8], 
        OLMNG_1_theta_o[7], OLMNG_1_theta_o[6], OLMNG_1_theta_o[5], 
        OLMNG_1_theta_o[4], OLMNG_1_theta_o[3], OLMNG_1_theta_o[2], 
        OLMNG_1_theta_o[1], OLMNG_1_theta_o[0]}), .init_speedpi_o({
        OLMNG_0_init_speedpi_o[17], OLMNG_0_init_speedpi_o[16], 
        OLMNG_0_init_speedpi_o[15], OLMNG_0_init_speedpi_o[14], 
        OLMNG_0_init_speedpi_o[13], OLMNG_0_init_speedpi_o[12], 
        OLMNG_0_init_speedpi_o[11], OLMNG_0_init_speedpi_o[10], 
        OLMNG_0_init_speedpi_o[9], OLMNG_0_init_speedpi_o[8], 
        OLMNG_0_init_speedpi_o[7], OLMNG_0_init_speedpi_o[6], 
        OLMNG_0_init_speedpi_o[5], OLMNG_0_init_speedpi_o[4], 
        OLMNG_0_init_speedpi_o[3], OLMNG_0_init_speedpi_o[2], 
        OLMNG_0_init_speedpi_o[1], OLMNG_0_init_speedpi_o[0]}), 
        .init_iqpi_o({OLMNG_0_init_iqpi_o[17], OLMNG_0_init_iqpi_o[16], 
        OLMNG_0_init_iqpi_o[15], OLMNG_0_init_iqpi_o[14], 
        OLMNG_0_init_iqpi_o[13], OLMNG_0_init_iqpi_o[12], 
        OLMNG_0_init_iqpi_o[11], OLMNG_0_init_iqpi_o[10], 
        OLMNG_0_init_iqpi_o[9], OLMNG_0_init_iqpi_o[8], 
        OLMNG_0_init_iqpi_o[7], OLMNG_0_init_iqpi_o[6], 
        OLMNG_0_init_iqpi_o[5], OLMNG_0_init_iqpi_o[4], 
        OLMNG_0_init_iqpi_o[3], OLMNG_0_init_iqpi_o[2], 
        OLMNG_0_init_iqpi_o[1], OLMNG_0_init_iqpi_o[0]}));
    VCC VCC_Z (.Y(VCC));
    PWM_SCALING_2s_44s_15s_0_1_2_4_1 MSC_i_32 (.reset_i(
        MC_System_0_FIC_0_LOCK), .sys_clk_i(MC_System_0_FIC_0_CLK), 
        .start_i(SVM_0_done_o), .va_i({SVM_0_va3h_o[17], 
        SVM_0_va3h_o[16], SVM_0_va3h_o[15], SVM_0_va3h_o[14], 
        SVM_0_va3h_o[13], SVM_0_va3h_o[12], SVM_0_va3h_o[11], 
        SVM_0_va3h_o[10], SVM_0_va3h_o[9], SVM_0_va3h_o[8], 
        SVM_0_va3h_o[7], SVM_0_va3h_o[6], SVM_0_va3h_o[5], 
        SVM_0_va3h_o[4], SVM_0_va3h_o[3], SVM_0_va3h_o[2], 
        SVM_0_va3h_o[1], SVM_0_va3h_o[0]}), .vb_i({SVM_0_vb3h_o[17], 
        SVM_0_vb3h_o[16], SVM_0_vb3h_o[15], SVM_0_vb3h_o[14], 
        SVM_0_vb3h_o[13], SVM_0_vb3h_o[12], SVM_0_vb3h_o[11], 
        SVM_0_vb3h_o[10], SVM_0_vb3h_o[9], SVM_0_vb3h_o[8], 
        SVM_0_vb3h_o[7], SVM_0_vb3h_o[6], SVM_0_vb3h_o[5], 
        SVM_0_vb3h_o[4], SVM_0_vb3h_o[3], SVM_0_vb3h_o[2], 
        SVM_0_vb3h_o[1], SVM_0_vb3h_o[0]}), .vc_i({SVM_0_vc3h_o[17], 
        SVM_0_vc3h_o[16], SVM_0_vc3h_o[15], SVM_0_vc3h_o[14], 
        SVM_0_vc3h_o[13], SVM_0_vc3h_o[12], SVM_0_vc3h_o[11], 
        SVM_0_vc3h_o[10], SVM_0_vc3h_o[9], SVM_0_vc3h_o[8], 
        SVM_0_vc3h_o[7], SVM_0_vc3h_o[6], SVM_0_vc3h_o[5], 
        SVM_0_vc3h_o[4], SVM_0_vc3h_o[3], SVM_0_vc3h_o[2], 
        SVM_0_vc3h_o[1], SVM_0_vc3h_o[0]}), .pwm_period_i({
        apb3_if_0_pwm_period_val_o[17], apb3_if_0_pwm_period_val_o[16], 
        apb3_if_0_pwm_period_val_o[15], apb3_if_0_pwm_period_val_o[14], 
        apb3_if_0_pwm_period_val_o[13], apb3_if_0_pwm_period_val_o[12], 
        apb3_if_0_pwm_period_val_o[11], apb3_if_0_pwm_period_val_o[10], 
        apb3_if_0_pwm_period_val_o[9], apb3_if_0_pwm_period_val_o[8], 
        apb3_if_0_pwm_period_val_o[7], apb3_if_0_pwm_period_val_o[6], 
        apb3_if_0_pwm_period_val_o[5], apb3_if_0_pwm_period_val_o[4], 
        apb3_if_0_pwm_period_val_o[3], apb3_if_0_pwm_period_val_o[2], 
        apb3_if_0_pwm_period_val_o[1], apb3_if_0_pwm_period_val_o[0]}), 
        .pwm_gain_i({apb3_if_0_pwm_gain_val_o[17], 
        apb3_if_0_pwm_gain_val_o[16], apb3_if_0_pwm_gain_val_o[15], 
        apb3_if_0_pwm_gain_val_o[14], apb3_if_0_pwm_gain_val_o[13], 
        apb3_if_0_pwm_gain_val_o[12], apb3_if_0_pwm_gain_val_o[11], 
        apb3_if_0_pwm_gain_val_o[10], apb3_if_0_pwm_gain_val_o[9], 
        apb3_if_0_pwm_gain_val_o[8], apb3_if_0_pwm_gain_val_o[7], 
        apb3_if_0_pwm_gain_val_o[6], apb3_if_0_pwm_gain_val_o[5], 
        apb3_if_0_pwm_gain_val_o[4], apb3_if_0_pwm_gain_val_o[3], 
        apb3_if_0_pwm_gain_val_o[2], apb3_if_0_pwm_gain_val_o[1], GND})
        , .Va_o({PWM_SCALING_0_Va_o[17], PWM_SCALING_0_Va_o[16], 
        PWM_SCALING_0_Va_o[15], PWM_SCALING_0_Va_o[14], 
        PWM_SCALING_0_Va_o[13], PWM_SCALING_0_Va_o[12], 
        PWM_SCALING_0_Va_o[11], PWM_SCALING_0_Va_o[10], 
        PWM_SCALING_0_Va_o[9], PWM_SCALING_0_Va_o[8], 
        PWM_SCALING_0_Va_o[7], PWM_SCALING_0_Va_o[6], 
        PWM_SCALING_0_Va_o[5], PWM_SCALING_0_Va_o[4], 
        PWM_SCALING_0_Va_o[3], PWM_SCALING_0_Va_o[2], 
        PWM_SCALING_0_Va_o[1], PWM_SCALING_0_Va_o[0]}), .Vb_o({
        PWM_SCALING_0_Vb_o[17], PWM_SCALING_0_Vb_o[16], 
        PWM_SCALING_0_Vb_o[15], PWM_SCALING_0_Vb_o[14], 
        PWM_SCALING_0_Vb_o[13], PWM_SCALING_0_Vb_o[12], 
        PWM_SCALING_0_Vb_o[11], PWM_SCALING_0_Vb_o[10], 
        PWM_SCALING_0_Vb_o[9], PWM_SCALING_0_Vb_o[8], 
        PWM_SCALING_0_Vb_o[7], PWM_SCALING_0_Vb_o[6], 
        PWM_SCALING_0_Vb_o[5], PWM_SCALING_0_Vb_o[4], 
        PWM_SCALING_0_Vb_o[3], PWM_SCALING_0_Vb_o[2], 
        PWM_SCALING_0_Vb_o[1], PWM_SCALING_0_Vb_o[0]}), .Vc_o({
        PWM_SCALING_0_Vc_o[17], PWM_SCALING_0_Vc_o[16], 
        PWM_SCALING_0_Vc_o[15], PWM_SCALING_0_Vc_o[14], 
        PWM_SCALING_0_Vc_o[13], PWM_SCALING_0_Vc_o[12], 
        PWM_SCALING_0_Vc_o[11], PWM_SCALING_0_Vc_o[10], 
        PWM_SCALING_0_Vc_o[9], PWM_SCALING_0_Vc_o[8], 
        PWM_SCALING_0_Vc_o[7], PWM_SCALING_0_Vc_o[6], 
        PWM_SCALING_0_Vc_o[5], PWM_SCALING_0_Vc_o[4], 
        PWM_SCALING_0_Vc_o[3], PWM_SCALING_0_Vc_o[2], 
        PWM_SCALING_0_Vc_o[1], PWM_SCALING_0_Vc_o[0]}), .done_o(
        PWM_SCALING_1_done_o));
    SPEED_ID_IQ_PI_2s_44s_1 MSC_i_16 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FIC_0_CLK), .clear_buffer_i(
        A0_PWM_VL_O_c_i_0), .speed_en_i(SEQ_CONTROLLER_0_cl_status_o), 
        .idq_en_i(N_894_i_0), .speed_pi_start_i(
        RATE_LIMITER_0_rl_done_o), .id_pi_start_i(
        SPEED_ID_IQ_PI_1_iq_pi_done_o), .iq_pi_start_i(
        FOC_TRANSFORMS_0_park_done_o), .speed_init_i({
        OLMNG_0_init_speedpi_o[17], OLMNG_0_init_speedpi_o[16], 
        OLMNG_0_init_speedpi_o[15], OLMNG_0_init_speedpi_o[14], 
        OLMNG_0_init_speedpi_o[13], OLMNG_0_init_speedpi_o[12], 
        OLMNG_0_init_speedpi_o[11], OLMNG_0_init_speedpi_o[10], 
        OLMNG_0_init_speedpi_o[9], OLMNG_0_init_speedpi_o[8], 
        OLMNG_0_init_speedpi_o[7], OLMNG_0_init_speedpi_o[6], 
        OLMNG_0_init_speedpi_o[5], OLMNG_0_init_speedpi_o[4], 
        OLMNG_0_init_speedpi_o[3], OLMNG_0_init_speedpi_o[2], 
        OLMNG_0_init_speedpi_o[1], OLMNG_0_init_speedpi_o[0]}), 
        .id_init_i({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND}), .iq_init_i({
        OLMNG_0_init_iqpi_o[17], OLMNG_0_init_iqpi_o[16], 
        OLMNG_0_init_iqpi_o[15], OLMNG_0_init_iqpi_o[14], 
        OLMNG_0_init_iqpi_o[13], OLMNG_0_init_iqpi_o[12], 
        OLMNG_0_init_iqpi_o[11], OLMNG_0_init_iqpi_o[10], 
        OLMNG_0_init_iqpi_o[9], OLMNG_0_init_iqpi_o[8], 
        OLMNG_0_init_iqpi_o[7], OLMNG_0_init_iqpi_o[6], 
        OLMNG_0_init_iqpi_o[5], OLMNG_0_init_iqpi_o[4], 
        OLMNG_0_init_iqpi_o[3], OLMNG_0_init_iqpi_o[2], 
        OLMNG_0_init_iqpi_o[1], OLMNG_0_init_iqpi_o[0]}), 
        .speed_pi_ref_input_i({RATE_LIMITER_0_rl_out_o[17], 
        RATE_LIMITER_0_rl_out_o[16], RATE_LIMITER_0_rl_out_o[15], 
        RATE_LIMITER_0_rl_out_o[14], RATE_LIMITER_0_rl_out_o[13], 
        RATE_LIMITER_0_rl_out_o[12], RATE_LIMITER_0_rl_out_o[11], 
        RATE_LIMITER_0_rl_out_o[10], RATE_LIMITER_0_rl_out_o[9], 
        RATE_LIMITER_0_rl_out_o[8], RATE_LIMITER_0_rl_out_o[7], 
        RATE_LIMITER_0_rl_out_o[6], RATE_LIMITER_0_rl_out_o[5], 
        RATE_LIMITER_0_rl_out_o[4], RATE_LIMITER_0_rl_out_o[3], 
        RATE_LIMITER_0_rl_out_o[2], RATE_LIMITER_0_rl_out_o[1], 
        RATE_LIMITER_0_rl_out_o[0]}), .speed_pi_act_input_i({
        BLDC_ESTIMATOR_0_speed_filtered_o[17], 
        BLDC_ESTIMATOR_0_speed_filtered_o[16], 
        BLDC_ESTIMATOR_0_speed_filtered_o[15], 
        BLDC_ESTIMATOR_0_speed_filtered_o[14], 
        BLDC_ESTIMATOR_0_speed_filtered_o[13], 
        BLDC_ESTIMATOR_0_speed_filtered_o[12], 
        BLDC_ESTIMATOR_0_speed_filtered_o[11], 
        BLDC_ESTIMATOR_0_speed_filtered_o[10], 
        BLDC_ESTIMATOR_0_speed_filtered_o[9], 
        BLDC_ESTIMATOR_0_speed_filtered_o[8], 
        BLDC_ESTIMATOR_0_speed_filtered_o[7], 
        BLDC_ESTIMATOR_0_speed_filtered_o[6], 
        BLDC_ESTIMATOR_0_speed_filtered_o[5], 
        BLDC_ESTIMATOR_0_speed_filtered_o[4], 
        BLDC_ESTIMATOR_0_speed_filtered_o[3], 
        BLDC_ESTIMATOR_0_speed_filtered_o[2], 
        BLDC_ESTIMATOR_0_speed_filtered_o[1], 
        BLDC_ESTIMATOR_0_speed_filtered_o[0]}), .speed_pi_kp_i({
        apb3_if_0_speed_pi_kp_o[17], apb3_if_0_speed_pi_kp_o[16], 
        apb3_if_0_speed_pi_kp_o[15], apb3_if_0_speed_pi_kp_o[14], 
        apb3_if_0_speed_pi_kp_o[13], apb3_if_0_speed_pi_kp_o[12], 
        apb3_if_0_speed_pi_kp_o[11], apb3_if_0_speed_pi_kp_o[10], 
        apb3_if_0_speed_pi_kp_o[9], apb3_if_0_speed_pi_kp_o[8], 
        apb3_if_0_speed_pi_kp_o[7], apb3_if_0_speed_pi_kp_o[6], 
        apb3_if_0_speed_pi_kp_o[5], apb3_if_0_speed_pi_kp_o[4], 
        apb3_if_0_speed_pi_kp_o[3], apb3_if_0_speed_pi_kp_o[2], 
        apb3_if_0_speed_pi_kp_o[1], apb3_if_0_speed_pi_kp_o[0]}), 
        .speed_pi_ki_i({apb3_if_0_speed_pi_ki_o[17], 
        apb3_if_0_speed_pi_ki_o[16], apb3_if_0_speed_pi_ki_o[15], 
        apb3_if_0_speed_pi_ki_o[14], apb3_if_0_speed_pi_ki_o[13], 
        apb3_if_0_speed_pi_ki_o[12], apb3_if_0_speed_pi_ki_o[11], 
        apb3_if_0_speed_pi_ki_o[10], apb3_if_0_speed_pi_ki_o[9], 
        apb3_if_0_speed_pi_ki_o[8], apb3_if_0_speed_pi_ki_o[7], 
        apb3_if_0_speed_pi_ki_o[6], apb3_if_0_speed_pi_ki_o[5], 
        apb3_if_0_speed_pi_ki_o[4], apb3_if_0_speed_pi_ki_o[3], 
        apb3_if_0_speed_pi_ki_o[2], apb3_if_0_speed_pi_ki_o[1], 
        apb3_if_0_speed_pi_ki_o[0]}), .speed_pi_ymax_i({GND, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC}), .speed_pi_ymin_i({VCC, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        VCC}), .id_pi_ref_input_i({GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .id_pi_act_input_i({FOC_TRANSFORMS_0_id_o[17], 
        FOC_TRANSFORMS_0_id_o[16], FOC_TRANSFORMS_0_id_o[15], 
        FOC_TRANSFORMS_0_id_o[14], FOC_TRANSFORMS_0_id_o[13], 
        FOC_TRANSFORMS_0_id_o[12], FOC_TRANSFORMS_0_id_o[11], 
        FOC_TRANSFORMS_0_id_o[10], FOC_TRANSFORMS_0_id_o[9], 
        FOC_TRANSFORMS_0_id_o[8], FOC_TRANSFORMS_0_id_o[7], 
        FOC_TRANSFORMS_0_id_o[6], FOC_TRANSFORMS_0_id_o[5], 
        FOC_TRANSFORMS_0_id_o[4], FOC_TRANSFORMS_0_id_o[3], 
        FOC_TRANSFORMS_0_id_o[2], FOC_TRANSFORMS_0_id_o[1], 
        FOC_TRANSFORMS_0_id_o[0]}), .id_pi_kp_i({
        apb3_if_0_idq_pi_kp_o[17], apb3_if_0_idq_pi_kp_o[16], 
        apb3_if_0_idq_pi_kp_o[15], apb3_if_0_idq_pi_kp_o[14], 
        apb3_if_0_idq_pi_kp_o[13], apb3_if_0_idq_pi_kp_o[12], 
        apb3_if_0_idq_pi_kp_o[11], apb3_if_0_idq_pi_kp_o[10], 
        apb3_if_0_idq_pi_kp_o[9], apb3_if_0_idq_pi_kp_o[8], 
        apb3_if_0_idq_pi_kp_o[7], apb3_if_0_idq_pi_kp_o[6], 
        apb3_if_0_idq_pi_kp_o[5], apb3_if_0_idq_pi_kp_o[4], 
        apb3_if_0_idq_pi_kp_o[3], apb3_if_0_idq_pi_kp_o[2], 
        apb3_if_0_idq_pi_kp_o[1], apb3_if_0_idq_pi_kp_o[0]}), 
        .id_pi_ki_i({apb3_if_0_idq_pi_ki_o_0[17], 
        apb3_if_0_idq_pi_ki_o_0[16], apb3_if_0_idq_pi_ki_o_0[15], 
        apb3_if_0_idq_pi_ki_o_0[14], apb3_if_0_idq_pi_ki_o_0[13], 
        apb3_if_0_idq_pi_ki_o_0[12], apb3_if_0_idq_pi_ki_o_0[11], 
        apb3_if_0_idq_pi_ki_o_0[10], apb3_if_0_idq_pi_ki_o_0[9], 
        apb3_if_0_idq_pi_ki_o_0[8], apb3_if_0_idq_pi_ki_o_0[7], 
        apb3_if_0_idq_pi_ki_o_0[6], apb3_if_0_idq_pi_ki_o_0[5], 
        apb3_if_0_idq_pi_ki_o_0[4], apb3_if_0_idq_pi_ki_o_0[3], 
        apb3_if_0_idq_pi_ki_o_0[2], apb3_if_0_idq_pi_ki_o_0[1], 
        apb3_if_0_idq_pi_ki_o_0[0]}), .idq_pi_ymax_i({GND, VCC, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND}), .idq_pi_ymin_i({VCC, VCC, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .iq_pi_ref_input_i({net_189[17], net_189[16], net_189[15], 
        net_189[14], net_189[13], net_189[12], net_189[11], 
        net_189[10], net_189[9], net_189[8], net_189[7], net_189[6], 
        net_189[5], net_189[4], net_189[3], net_189[2], net_189[1], 
        net_189[0]}), .iq_pi_act_input_i({FOC_TRANSFORMS_0_iq_o[17], 
        FOC_TRANSFORMS_0_iq_o[16], FOC_TRANSFORMS_0_iq_o[15], 
        FOC_TRANSFORMS_0_iq_o[14], FOC_TRANSFORMS_0_iq_o[13], 
        FOC_TRANSFORMS_0_iq_o[12], FOC_TRANSFORMS_0_iq_o[11], 
        FOC_TRANSFORMS_0_iq_o[10], FOC_TRANSFORMS_0_iq_o[9], 
        FOC_TRANSFORMS_0_iq_o[8], FOC_TRANSFORMS_0_iq_o[7], 
        FOC_TRANSFORMS_0_iq_o[6], FOC_TRANSFORMS_0_iq_o[5], 
        FOC_TRANSFORMS_0_iq_o[4], FOC_TRANSFORMS_0_iq_o[3], 
        FOC_TRANSFORMS_0_iq_o[2], FOC_TRANSFORMS_0_iq_o[1], 
        FOC_TRANSFORMS_0_iq_o[0]}), .iq_pi_kp_i({GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND}), .iq_pi_ki_i({GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .speed_pi_done_o(speed_pi_done_o), .id_pi_done_o(
        SPEED_ID_IQ_PI_1_id_pi_done_o), .iq_pi_done_o(
        SPEED_ID_IQ_PI_1_iq_pi_done_o), .speed_pi_output_o({
        net_189[17], net_189[16], net_189[15], net_189[14], 
        net_189[13], net_189[12], net_189[11], net_189[10], net_189[9], 
        net_189[8], net_189[7], net_189[6], net_189[5], net_189[4], 
        net_189[3], net_189[2], net_189[1], net_189[0]}), 
        .id_pi_output_o({SPEED_ID_IQ_PI_1_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[1], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[0]}), .iq_pi_output_o({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]}));
    FOC_TRANSFORMS_2s_44s_1 MSC_i_1 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FIC_0_CLK), .start_clarke_i(
        ADC_SCALING_0_done_o), .start_park_i(
        FOC_TRANSFORMS_1_clarke_done_o_0), .start_ipark_i(
        SPEED_ID_IQ_PI_1_id_pi_done_o), .start_iclarke_i(
        FOC_TRANSFORMS_0_ipark_done_o), .ia_i({
        ADC_SCALING_1_ia_adc_o[17], ADC_SCALING_1_ia_adc_o[16], 
        ADC_SCALING_1_ia_adc_o[15], ADC_SCALING_1_ia_adc_o[14], 
        ADC_SCALING_1_ia_adc_o[13], ADC_SCALING_1_ia_adc_o[12], 
        ADC_SCALING_1_ia_adc_o[11], ADC_SCALING_1_ia_adc_o[10], 
        ADC_SCALING_1_ia_adc_o[9], ADC_SCALING_1_ia_adc_o[8], 
        ADC_SCALING_1_ia_adc_o[7], ADC_SCALING_1_ia_adc_o[6], 
        ADC_SCALING_1_ia_adc_o[5], ADC_SCALING_1_ia_adc_o[4], 
        ADC_SCALING_1_ia_adc_o[3], ADC_SCALING_1_ia_adc_o[2], 
        ADC_SCALING_1_ia_adc_o[1], ADC_SCALING_1_ia_adc_o[0]}), .ib_i({
        ADC_SCALING_1_ib_adc_o[17], ADC_SCALING_1_ib_adc_o[16], 
        ADC_SCALING_1_ib_adc_o[15], ADC_SCALING_1_ib_adc_o[14], 
        ADC_SCALING_1_ib_adc_o[13], ADC_SCALING_1_ib_adc_o[12], 
        ADC_SCALING_1_ib_adc_o[11], ADC_SCALING_1_ib_adc_o[10], 
        ADC_SCALING_1_ib_adc_o[9], ADC_SCALING_1_ib_adc_o[8], 
        ADC_SCALING_1_ib_adc_o[7], ADC_SCALING_1_ib_adc_o[6], 
        ADC_SCALING_1_ib_adc_o[5], ADC_SCALING_1_ib_adc_o[4], 
        ADC_SCALING_1_ib_adc_o[3], ADC_SCALING_1_ib_adc_o[2], 
        ADC_SCALING_1_ib_adc_o[1], ADC_SCALING_1_ib_adc_o[0]}), 
        .ialpha_i({FOC_TRANSFORMS_0_ialpha_o[17], 
        FOC_TRANSFORMS_0_ialpha_o[16], FOC_TRANSFORMS_0_ialpha_o[15], 
        FOC_TRANSFORMS_0_ialpha_o[14], FOC_TRANSFORMS_0_ialpha_o[13], 
        FOC_TRANSFORMS_0_ialpha_o[12], FOC_TRANSFORMS_0_ialpha_o[11], 
        FOC_TRANSFORMS_0_ialpha_o[10], FOC_TRANSFORMS_0_ialpha_o[9], 
        FOC_TRANSFORMS_0_ialpha_o[8], FOC_TRANSFORMS_0_ialpha_o[7], 
        FOC_TRANSFORMS_0_ialpha_o[6], FOC_TRANSFORMS_0_ialpha_o[5], 
        FOC_TRANSFORMS_0_ialpha_o[4], FOC_TRANSFORMS_0_ialpha_o[3], 
        FOC_TRANSFORMS_0_ialpha_o[2], FOC_TRANSFORMS_0_ialpha_o[1], 
        GND}), .ibeta_i({FOC_TRANSFORMS_0_ibeta_o[17], 
        FOC_TRANSFORMS_0_ibeta_o[16], FOC_TRANSFORMS_0_ibeta_o[15], 
        FOC_TRANSFORMS_0_ibeta_o[14], FOC_TRANSFORMS_0_ibeta_o[13], 
        FOC_TRANSFORMS_0_ibeta_o[12], FOC_TRANSFORMS_0_ibeta_o[11], 
        FOC_TRANSFORMS_0_ibeta_o[10], FOC_TRANSFORMS_0_ibeta_o[9], 
        FOC_TRANSFORMS_0_ibeta_o[8], FOC_TRANSFORMS_0_ibeta_o[7], 
        FOC_TRANSFORMS_0_ibeta_o[6], FOC_TRANSFORMS_0_ibeta_o[5], 
        FOC_TRANSFORMS_0_ibeta_o[4], FOC_TRANSFORMS_0_ibeta_o[3], 
        FOC_TRANSFORMS_0_ibeta_o[2], FOC_TRANSFORMS_0_ibeta_o[1], GND})
        , .vd_i({SPEED_ID_IQ_PI_1_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[1], GND}), .vq_i({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1], GND}), .valpha_i({
        FOC_TRANSFORMS_0_valpha_o[17], FOC_TRANSFORMS_0_valpha_o[16], 
        FOC_TRANSFORMS_0_valpha_o[15], FOC_TRANSFORMS_0_valpha_o[14], 
        FOC_TRANSFORMS_0_valpha_o[13], FOC_TRANSFORMS_0_valpha_o[12], 
        FOC_TRANSFORMS_0_valpha_o[11], FOC_TRANSFORMS_0_valpha_o[10], 
        FOC_TRANSFORMS_0_valpha_o[9], FOC_TRANSFORMS_0_valpha_o[8], 
        FOC_TRANSFORMS_0_valpha_o[7], FOC_TRANSFORMS_0_valpha_o[6], 
        FOC_TRANSFORMS_0_valpha_o[5], FOC_TRANSFORMS_0_valpha_o[4], 
        FOC_TRANSFORMS_0_valpha_o[3], FOC_TRANSFORMS_0_valpha_o[2], 
        FOC_TRANSFORMS_0_valpha_o[1], FOC_TRANSFORMS_0_valpha_o[0]}), 
        .vbeta_i({FOC_TRANSFORMS_0_vbeta_o[17], 
        FOC_TRANSFORMS_0_vbeta_o[16], FOC_TRANSFORMS_0_vbeta_o[15], 
        FOC_TRANSFORMS_0_vbeta_o[14], FOC_TRANSFORMS_0_vbeta_o[13], 
        FOC_TRANSFORMS_0_vbeta_o[12], FOC_TRANSFORMS_0_vbeta_o[11], 
        FOC_TRANSFORMS_0_vbeta_o[10], FOC_TRANSFORMS_0_vbeta_o[9], 
        FOC_TRANSFORMS_0_vbeta_o[8], FOC_TRANSFORMS_0_vbeta_o[7], 
        FOC_TRANSFORMS_0_vbeta_o[6], FOC_TRANSFORMS_0_vbeta_o[5], 
        FOC_TRANSFORMS_0_vbeta_o[4], FOC_TRANSFORMS_0_vbeta_o[3], 
        FOC_TRANSFORMS_0_vbeta_o[2], FOC_TRANSFORMS_0_vbeta_o[1], 
        FOC_TRANSFORMS_0_vbeta_o[0]}), .theta_i({OLMNG_1_theta_o[17], 
        OLMNG_1_theta_o[16], OLMNG_1_theta_o[15], OLMNG_1_theta_o[14], 
        OLMNG_1_theta_o[13], OLMNG_1_theta_o[12], OLMNG_1_theta_o[11], 
        OLMNG_1_theta_o[10], OLMNG_1_theta_o[9], OLMNG_1_theta_o[8], 
        OLMNG_1_theta_o[7], OLMNG_1_theta_o[6], OLMNG_1_theta_o[5], 
        OLMNG_1_theta_o[4], OLMNG_1_theta_o[3], OLMNG_1_theta_o[2], 
        OLMNG_1_theta_o[1], OLMNG_1_theta_o[0]}), .clarke_done_o(
        FOC_TRANSFORMS_1_clarke_done_o_0), .park_done_o(
        FOC_TRANSFORMS_0_park_done_o), .ipark_done_o(
        FOC_TRANSFORMS_0_ipark_done_o), .iclarke_done_o(
        FOC_TRANSFORMS_0_iclarke_done_o), .ialpha_o({
        FOC_TRANSFORMS_0_ialpha_o[17], FOC_TRANSFORMS_0_ialpha_o[16], 
        FOC_TRANSFORMS_0_ialpha_o[15], FOC_TRANSFORMS_0_ialpha_o[14], 
        FOC_TRANSFORMS_0_ialpha_o[13], FOC_TRANSFORMS_0_ialpha_o[12], 
        FOC_TRANSFORMS_0_ialpha_o[11], FOC_TRANSFORMS_0_ialpha_o[10], 
        FOC_TRANSFORMS_0_ialpha_o[9], FOC_TRANSFORMS_0_ialpha_o[8], 
        FOC_TRANSFORMS_0_ialpha_o[7], FOC_TRANSFORMS_0_ialpha_o[6], 
        FOC_TRANSFORMS_0_ialpha_o[5], FOC_TRANSFORMS_0_ialpha_o[4], 
        FOC_TRANSFORMS_0_ialpha_o[3], FOC_TRANSFORMS_0_ialpha_o[2], 
        FOC_TRANSFORMS_0_ialpha_o[1], FOC_TRANSFORMS_0_ialpha_o[0]}), 
        .ibeta_o({FOC_TRANSFORMS_0_ibeta_o[17], 
        FOC_TRANSFORMS_0_ibeta_o[16], FOC_TRANSFORMS_0_ibeta_o[15], 
        FOC_TRANSFORMS_0_ibeta_o[14], FOC_TRANSFORMS_0_ibeta_o[13], 
        FOC_TRANSFORMS_0_ibeta_o[12], FOC_TRANSFORMS_0_ibeta_o[11], 
        FOC_TRANSFORMS_0_ibeta_o[10], FOC_TRANSFORMS_0_ibeta_o[9], 
        FOC_TRANSFORMS_0_ibeta_o[8], FOC_TRANSFORMS_0_ibeta_o[7], 
        FOC_TRANSFORMS_0_ibeta_o[6], FOC_TRANSFORMS_0_ibeta_o[5], 
        FOC_TRANSFORMS_0_ibeta_o[4], FOC_TRANSFORMS_0_ibeta_o[3], 
        FOC_TRANSFORMS_0_ibeta_o[2], FOC_TRANSFORMS_0_ibeta_o[1], 
        FOC_TRANSFORMS_0_ibeta_o[0]}), .id_o({
        FOC_TRANSFORMS_0_id_o[17], FOC_TRANSFORMS_0_id_o[16], 
        FOC_TRANSFORMS_0_id_o[15], FOC_TRANSFORMS_0_id_o[14], 
        FOC_TRANSFORMS_0_id_o[13], FOC_TRANSFORMS_0_id_o[12], 
        FOC_TRANSFORMS_0_id_o[11], FOC_TRANSFORMS_0_id_o[10], 
        FOC_TRANSFORMS_0_id_o[9], FOC_TRANSFORMS_0_id_o[8], 
        FOC_TRANSFORMS_0_id_o[7], FOC_TRANSFORMS_0_id_o[6], 
        FOC_TRANSFORMS_0_id_o[5], FOC_TRANSFORMS_0_id_o[4], 
        FOC_TRANSFORMS_0_id_o[3], FOC_TRANSFORMS_0_id_o[2], 
        FOC_TRANSFORMS_0_id_o[1], FOC_TRANSFORMS_0_id_o[0]}), .iq_o({
        FOC_TRANSFORMS_0_iq_o[17], FOC_TRANSFORMS_0_iq_o[16], 
        FOC_TRANSFORMS_0_iq_o[15], FOC_TRANSFORMS_0_iq_o[14], 
        FOC_TRANSFORMS_0_iq_o[13], FOC_TRANSFORMS_0_iq_o[12], 
        FOC_TRANSFORMS_0_iq_o[11], FOC_TRANSFORMS_0_iq_o[10], 
        FOC_TRANSFORMS_0_iq_o[9], FOC_TRANSFORMS_0_iq_o[8], 
        FOC_TRANSFORMS_0_iq_o[7], FOC_TRANSFORMS_0_iq_o[6], 
        FOC_TRANSFORMS_0_iq_o[5], FOC_TRANSFORMS_0_iq_o[4], 
        FOC_TRANSFORMS_0_iq_o[3], FOC_TRANSFORMS_0_iq_o[2], 
        FOC_TRANSFORMS_0_iq_o[1], FOC_TRANSFORMS_0_iq_o[0]}), 
        .valpha_o({FOC_TRANSFORMS_0_valpha_o[17], 
        FOC_TRANSFORMS_0_valpha_o[16], FOC_TRANSFORMS_0_valpha_o[15], 
        FOC_TRANSFORMS_0_valpha_o[14], FOC_TRANSFORMS_0_valpha_o[13], 
        FOC_TRANSFORMS_0_valpha_o[12], FOC_TRANSFORMS_0_valpha_o[11], 
        FOC_TRANSFORMS_0_valpha_o[10], FOC_TRANSFORMS_0_valpha_o[9], 
        FOC_TRANSFORMS_0_valpha_o[8], FOC_TRANSFORMS_0_valpha_o[7], 
        FOC_TRANSFORMS_0_valpha_o[6], FOC_TRANSFORMS_0_valpha_o[5], 
        FOC_TRANSFORMS_0_valpha_o[4], FOC_TRANSFORMS_0_valpha_o[3], 
        FOC_TRANSFORMS_0_valpha_o[2], FOC_TRANSFORMS_0_valpha_o[1], 
        FOC_TRANSFORMS_0_valpha_o[0]}), .vbeta_o({
        FOC_TRANSFORMS_0_vbeta_o[17], FOC_TRANSFORMS_0_vbeta_o[16], 
        FOC_TRANSFORMS_0_vbeta_o[15], FOC_TRANSFORMS_0_vbeta_o[14], 
        FOC_TRANSFORMS_0_vbeta_o[13], FOC_TRANSFORMS_0_vbeta_o[12], 
        FOC_TRANSFORMS_0_vbeta_o[11], FOC_TRANSFORMS_0_vbeta_o[10], 
        FOC_TRANSFORMS_0_vbeta_o[9], FOC_TRANSFORMS_0_vbeta_o[8], 
        FOC_TRANSFORMS_0_vbeta_o[7], FOC_TRANSFORMS_0_vbeta_o[6], 
        FOC_TRANSFORMS_0_vbeta_o[5], FOC_TRANSFORMS_0_vbeta_o[4], 
        FOC_TRANSFORMS_0_vbeta_o[3], FOC_TRANSFORMS_0_vbeta_o[2], 
        FOC_TRANSFORMS_0_vbeta_o[1], FOC_TRANSFORMS_0_vbeta_o[0]}), 
        .va_o({FOC_TRANSFORMS_0_va_o[17], FOC_TRANSFORMS_0_va_o[16], 
        FOC_TRANSFORMS_0_va_o[15], FOC_TRANSFORMS_0_va_o[14], 
        FOC_TRANSFORMS_0_va_o[13], FOC_TRANSFORMS_0_va_o[12], 
        FOC_TRANSFORMS_0_va_o[11], FOC_TRANSFORMS_0_va_o[10], 
        FOC_TRANSFORMS_0_va_o[9], FOC_TRANSFORMS_0_va_o[8], 
        FOC_TRANSFORMS_0_va_o[7], FOC_TRANSFORMS_0_va_o[6], 
        FOC_TRANSFORMS_0_va_o[5], FOC_TRANSFORMS_0_va_o[4], 
        FOC_TRANSFORMS_0_va_o[3], FOC_TRANSFORMS_0_va_o[2], 
        FOC_TRANSFORMS_0_va_o[1], FOC_TRANSFORMS_0_va_o[0]}), .vb_o({
        FOC_TRANSFORMS_0_vb_o[17], FOC_TRANSFORMS_0_vb_o[16], 
        FOC_TRANSFORMS_0_vb_o[15], FOC_TRANSFORMS_0_vb_o[14], 
        FOC_TRANSFORMS_0_vb_o[13], FOC_TRANSFORMS_0_vb_o[12], 
        FOC_TRANSFORMS_0_vb_o[11], FOC_TRANSFORMS_0_vb_o[10], 
        FOC_TRANSFORMS_0_vb_o[9], FOC_TRANSFORMS_0_vb_o[8], 
        FOC_TRANSFORMS_0_vb_o[7], FOC_TRANSFORMS_0_vb_o[6], 
        FOC_TRANSFORMS_0_vb_o[5], FOC_TRANSFORMS_0_vb_o[4], 
        FOC_TRANSFORMS_0_vb_o[3], FOC_TRANSFORMS_0_vb_o[2], 
        FOC_TRANSFORMS_0_vb_o[1], FOC_TRANSFORMS_0_vb_o[0]}), .vc_o({
        FOC_TRANSFORMS_0_vc_o[17], FOC_TRANSFORMS_0_vc_o[16], 
        FOC_TRANSFORMS_0_vc_o[15], FOC_TRANSFORMS_0_vc_o[14], 
        FOC_TRANSFORMS_0_vc_o[13], FOC_TRANSFORMS_0_vc_o[12], 
        FOC_TRANSFORMS_0_vc_o[11], FOC_TRANSFORMS_0_vc_o[10], 
        FOC_TRANSFORMS_0_vc_o[9], FOC_TRANSFORMS_0_vc_o[8], 
        FOC_TRANSFORMS_0_vc_o[7], FOC_TRANSFORMS_0_vc_o[6], 
        FOC_TRANSFORMS_0_vc_o[5], FOC_TRANSFORMS_0_vc_o[4], 
        FOC_TRANSFORMS_0_vc_o[3], FOC_TRANSFORMS_0_vc_o[2], 
        FOC_TRANSFORMS_0_vc_o[1], FOC_TRANSFORMS_0_vc_o[0]}));
    PWM3PH_1 MSC_i_34 (.reset_i(MC_System_0_FIC_0_LOCK), .sys_clk_i(
        MC_System_0_FIC_0_CLK), .en_pwm_i(A0_PWM_VL_O_c), 
        .en_dual_trig_i(GND), .va_i({PWM_SCALING_0_Va_o[17], 
        PWM_SCALING_0_Va_o[16], PWM_SCALING_0_Va_o[15], 
        PWM_SCALING_0_Va_o[14], PWM_SCALING_0_Va_o[13], 
        PWM_SCALING_0_Va_o[12], PWM_SCALING_0_Va_o[11], 
        PWM_SCALING_0_Va_o[10], PWM_SCALING_0_Va_o[9], 
        PWM_SCALING_0_Va_o[8], PWM_SCALING_0_Va_o[7], 
        PWM_SCALING_0_Va_o[6], PWM_SCALING_0_Va_o[5], 
        PWM_SCALING_0_Va_o[4], PWM_SCALING_0_Va_o[3], 
        PWM_SCALING_0_Va_o[2], PWM_SCALING_0_Va_o[1], 
        PWM_SCALING_0_Va_o[0]}), .vb_i({PWM_SCALING_0_Vb_o[17], 
        PWM_SCALING_0_Vb_o[16], PWM_SCALING_0_Vb_o[15], 
        PWM_SCALING_0_Vb_o[14], PWM_SCALING_0_Vb_o[13], 
        PWM_SCALING_0_Vb_o[12], PWM_SCALING_0_Vb_o[11], 
        PWM_SCALING_0_Vb_o[10], PWM_SCALING_0_Vb_o[9], 
        PWM_SCALING_0_Vb_o[8], PWM_SCALING_0_Vb_o[7], 
        PWM_SCALING_0_Vb_o[6], PWM_SCALING_0_Vb_o[5], 
        PWM_SCALING_0_Vb_o[4], PWM_SCALING_0_Vb_o[3], 
        PWM_SCALING_0_Vb_o[2], PWM_SCALING_0_Vb_o[1], 
        PWM_SCALING_0_Vb_o[0]}), .vc_i({PWM_SCALING_0_Vc_o[17], 
        PWM_SCALING_0_Vc_o[16], PWM_SCALING_0_Vc_o[15], 
        PWM_SCALING_0_Vc_o[14], PWM_SCALING_0_Vc_o[13], 
        PWM_SCALING_0_Vc_o[12], PWM_SCALING_0_Vc_o[11], 
        PWM_SCALING_0_Vc_o[10], PWM_SCALING_0_Vc_o[9], 
        PWM_SCALING_0_Vc_o[8], PWM_SCALING_0_Vc_o[7], 
        PWM_SCALING_0_Vc_o[6], PWM_SCALING_0_Vc_o[5], 
        PWM_SCALING_0_Vc_o[4], PWM_SCALING_0_Vc_o[3], 
        PWM_SCALING_0_Vc_o[2], PWM_SCALING_0_Vc_o[1], 
        PWM_SCALING_0_Vc_o[0]}), .pwm_period_i({
        apb3_if_0_pwm_period_val_o[17], apb3_if_0_pwm_period_val_o[16], 
        apb3_if_0_pwm_period_val_o[15], apb3_if_0_pwm_period_val_o[14], 
        apb3_if_0_pwm_period_val_o[13], apb3_if_0_pwm_period_val_o[12], 
        apb3_if_0_pwm_period_val_o[11], apb3_if_0_pwm_period_val_o[10], 
        apb3_if_0_pwm_period_val_o[9], apb3_if_0_pwm_period_val_o[8], 
        apb3_if_0_pwm_period_val_o[7], apb3_if_0_pwm_period_val_o[6], 
        apb3_if_0_pwm_period_val_o[5], apb3_if_0_pwm_period_val_o[4], 
        apb3_if_0_pwm_period_val_o[3], apb3_if_0_pwm_period_val_o[2], 
        apb3_if_0_pwm_period_val_o[1], apb3_if_0_pwm_period_val_o[0]}), 
        .dead_time_i({apb3_if_0_pwm_dead_time_val_o[17], 
        apb3_if_0_pwm_dead_time_val_o[16], 
        apb3_if_0_pwm_dead_time_val_o[15], 
        apb3_if_0_pwm_dead_time_val_o[14], 
        apb3_if_0_pwm_dead_time_val_o[13], 
        apb3_if_0_pwm_dead_time_val_o[12], 
        apb3_if_0_pwm_dead_time_val_o[11], 
        apb3_if_0_pwm_dead_time_val_o[10], 
        apb3_if_0_pwm_dead_time_val_o[9], 
        apb3_if_0_pwm_dead_time_val_o[8], 
        apb3_if_0_pwm_dead_time_val_o[7], 
        apb3_if_0_pwm_dead_time_val_o[6], 
        apb3_if_0_pwm_dead_time_val_o[5], 
        apb3_if_0_pwm_dead_time_val_o[4], 
        apb3_if_0_pwm_dead_time_val_o[3], 
        apb3_if_0_pwm_dead_time_val_o[2], 
        apb3_if_0_pwm_dead_time_val_o[1], 
        apb3_if_0_pwm_dead_time_val_o[0]}), .delay_time_i({
        apb3_if_0_pwm_delay_time_val_o[17], 
        apb3_if_0_pwm_delay_time_val_o[16], 
        apb3_if_0_pwm_delay_time_val_o[15], 
        apb3_if_0_pwm_delay_time_val_o[14], 
        apb3_if_0_pwm_delay_time_val_o[13], 
        apb3_if_0_pwm_delay_time_val_o[12], 
        apb3_if_0_pwm_delay_time_val_o[11], 
        apb3_if_0_pwm_delay_time_val_o[10], 
        apb3_if_0_pwm_delay_time_val_o[9], 
        apb3_if_0_pwm_delay_time_val_o[8], 
        apb3_if_0_pwm_delay_time_val_o[7], 
        apb3_if_0_pwm_delay_time_val_o[6], 
        apb3_if_0_pwm_delay_time_val_o[5], 
        apb3_if_0_pwm_delay_time_val_o[4], 
        apb3_if_0_pwm_delay_time_val_o[3], 
        apb3_if_0_pwm_delay_time_val_o[2], 
        apb3_if_0_pwm_delay_time_val_o[1], 
        apb3_if_0_pwm_delay_time_val_o[0]}), .midmatch_o(
        PWM3PH_1_midmatch_o), .PWM_AH_o(A0_PWM_UH_O_c), .PWM_BH_o(
        A0_PWM_VH_O_c), .PWM_CH_o(A0_PWM_WH_O_c), .PWM_AL_o(PWM_AL_o), 
        .PWM_BL_o(PWM_BL_o), .PWM_CL_o(PWM_CL_o));
    
        work_adc_interface_adc_interface_6_16_12_g_ADC_CONFIG_REG_WIDTHg_ADC_CONFIG_VAL_WIDTHg_ADC_RESULTS_WIDTH_1 
        adc_interface_0 (.apb3_if_0_adc_control_reg_val_o({
        apb3_if_0_adc_control_reg_val_o[5], 
        apb3_if_0_adc_control_reg_val_o[4], 
        apb3_if_0_adc_control_reg_val_o[3], 
        apb3_if_0_adc_control_reg_val_o[2], 
        apb3_if_0_adc_control_reg_val_o[1], 
        apb3_if_0_adc_control_reg_val_o[0]}), 
        .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[11], 
        adc_interface_0_result_ch0_o[10], 
        adc_interface_0_result_ch0_o[9], 
        adc_interface_0_result_ch0_o[8], 
        adc_interface_0_result_ch0_o[7], 
        adc_interface_0_result_ch0_o[6], 
        adc_interface_0_result_ch0_o[5], 
        adc_interface_0_result_ch0_o[4], 
        adc_interface_0_result_ch0_o[3], 
        adc_interface_0_result_ch0_o[2], 
        adc_interface_0_result_ch0_o[1], 
        adc_interface_0_result_ch0_o[0]}), 
        .adc_interface_0_result_ch1_o({
        adc_interface_0_result_ch1_o[11], 
        adc_interface_0_result_ch1_o[10], 
        adc_interface_0_result_ch1_o[9], 
        adc_interface_0_result_ch1_o[8], 
        adc_interface_0_result_ch1_o[7], 
        adc_interface_0_result_ch1_o[6], 
        adc_interface_0_result_ch1_o[5], 
        adc_interface_0_result_ch1_o[4], 
        adc_interface_0_result_ch1_o[3], 
        adc_interface_0_result_ch1_o[2], 
        adc_interface_0_result_ch1_o[1], 
        adc_interface_0_result_ch1_o[0]}), 
        .adc_measurements_0_adc_result_ch2_o({
        adc_measurements_0_adc_result_ch2_o[11], 
        adc_measurements_0_adc_result_ch2_o[10], 
        adc_measurements_0_adc_result_ch2_o[9], 
        adc_measurements_0_adc_result_ch2_o[8], 
        adc_measurements_0_adc_result_ch2_o[7], 
        adc_measurements_0_adc_result_ch2_o[6], 
        adc_measurements_0_adc_result_ch2_o[5], 
        adc_measurements_0_adc_result_ch2_o[4], 
        adc_measurements_0_adc_result_ch2_o[3], 
        adc_measurements_0_adc_result_ch2_o[2], 
        adc_measurements_0_adc_result_ch2_o[1], 
        adc_measurements_0_adc_result_ch2_o[0]}), 
        .adc_measurements_0_adc_result_ch3_o({
        adc_measurements_0_adc_result_ch3_o[11], 
        adc_measurements_0_adc_result_ch3_o[10], 
        adc_measurements_0_adc_result_ch3_o[9], 
        adc_measurements_0_adc_result_ch3_o[8], 
        adc_measurements_0_adc_result_ch3_o[7], 
        adc_measurements_0_adc_result_ch3_o[6], 
        adc_measurements_0_adc_result_ch3_o[5], 
        adc_measurements_0_adc_result_ch3_o[4], 
        adc_measurements_0_adc_result_ch3_o[3], 
        adc_measurements_0_adc_result_ch3_o[2], 
        adc_measurements_0_adc_result_ch3_o[1], 
        adc_measurements_0_adc_result_ch3_o[0]}), 
        .apb3_if_0_adc_channel_ch2_o({apb3_if_0_adc_channel_ch2_o[15], 
        apb3_if_0_adc_channel_ch2_o[14], 
        apb3_if_0_adc_channel_ch2_o[13], 
        apb3_if_0_adc_channel_ch2_o[12], 
        apb3_if_0_adc_channel_ch2_o[11], 
        apb3_if_0_adc_channel_ch2_o[10], 
        apb3_if_0_adc_channel_ch2_o[9], apb3_if_0_adc_channel_ch2_o[8], 
        apb3_if_0_adc_channel_ch2_o[7], apb3_if_0_adc_channel_ch2_o[6], 
        apb3_if_0_adc_channel_ch2_o[5], apb3_if_0_adc_channel_ch2_o[4], 
        apb3_if_0_adc_channel_ch2_o[3], apb3_if_0_adc_channel_ch2_o[2], 
        apb3_if_0_adc_channel_ch2_o[1], apb3_if_0_adc_channel_ch2_o[0]})
        , .apb3_if_0_adc_channel_ch0_o({
        apb3_if_0_adc_channel_ch0_o[15], 
        apb3_if_0_adc_channel_ch0_o[14], 
        apb3_if_0_adc_channel_ch0_o[13], 
        apb3_if_0_adc_channel_ch0_o[12], 
        apb3_if_0_adc_channel_ch0_o[11], 
        apb3_if_0_adc_channel_ch0_o[10], 
        apb3_if_0_adc_channel_ch0_o[9], apb3_if_0_adc_channel_ch0_o[8], 
        apb3_if_0_adc_channel_ch0_o[7], apb3_if_0_adc_channel_ch0_o[6], 
        apb3_if_0_adc_channel_ch0_o[5], apb3_if_0_adc_channel_ch0_o[4], 
        apb3_if_0_adc_channel_ch0_o[3], apb3_if_0_adc_channel_ch0_o[2], 
        apb3_if_0_adc_channel_ch0_o[1], apb3_if_0_adc_channel_ch0_o[0]})
        , .apb3_if_0_adc_channel_ch1_o({
        apb3_if_0_adc_channel_ch1_o[15], 
        apb3_if_0_adc_channel_ch1_o[14], 
        apb3_if_0_adc_channel_ch1_o[13], 
        apb3_if_0_adc_channel_ch1_o[12], 
        apb3_if_0_adc_channel_ch1_o[11], 
        apb3_if_0_adc_channel_ch1_o[10], 
        apb3_if_0_adc_channel_ch1_o[9], apb3_if_0_adc_channel_ch1_o[8], 
        apb3_if_0_adc_channel_ch1_o[7], apb3_if_0_adc_channel_ch1_o[6], 
        apb3_if_0_adc_channel_ch1_o[5], apb3_if_0_adc_channel_ch1_o[4], 
        apb3_if_0_adc_channel_ch1_o[3], apb3_if_0_adc_channel_ch1_o[2], 
        apb3_if_0_adc_channel_ch1_o[1], apb3_if_0_adc_channel_ch1_o[0]})
        , .apb3_if_0_adc_channel_ch3_o({
        apb3_if_0_adc_channel_ch3_o[15], 
        apb3_if_0_adc_channel_ch3_o[14], 
        apb3_if_0_adc_channel_ch3_o[13], 
        apb3_if_0_adc_channel_ch3_o[12], 
        apb3_if_0_adc_channel_ch3_o[11], 
        apb3_if_0_adc_channel_ch3_o[10], 
        apb3_if_0_adc_channel_ch3_o[9], apb3_if_0_adc_channel_ch3_o[8], 
        apb3_if_0_adc_channel_ch3_o[7], apb3_if_0_adc_channel_ch3_o[6], 
        apb3_if_0_adc_channel_ch3_o[5], apb3_if_0_adc_channel_ch3_o[4], 
        apb3_if_0_adc_channel_ch3_o[3], apb3_if_0_adc_channel_ch3_o[2], 
        apb3_if_0_adc_channel_ch3_o[1], apb3_if_0_adc_channel_ch3_o[0]})
        , .MC_System_0_FIC_0_LOCK(MC_System_0_FIC_0_LOCK), 
        .MC_System_0_FIC_0_CLK(MC_System_0_FIC_0_CLK), 
        .SEQ_CONTROLLER_1_adc_start_o(SEQ_CONTROLLER_1_adc_start_o), 
        .A0_ADC_SDI_I_c(A0_ADC_SDI_I_c), .A0_ADC_SDO_O_c(
        A0_ADC_SDO_O_c), .A0_ADC_CS_O_c(A0_ADC_CS_O_c), 
        .A0_ADC_SCK_O_c(A0_ADC_SCK_O_c), 
        .adc_interface_0_results_rdy_o(adc_interface_0_results_rdy_o));
    
        work_apb3_if_apb3_if_32_12_12_6_18_2_g_APB3_IF_DATA_WIDTHg_CONST_WIDTHg_ADC_OUT_WIDTHg_ADC_CONFIG_REG_WIDTHg_STD_IO_WIDTH 
        apb3_if_0 (.apb3_if_0_idq_pi_ki_o_0({
        apb3_if_0_idq_pi_ki_o_0[17], apb3_if_0_idq_pi_ki_o_0[16], 
        apb3_if_0_idq_pi_ki_o_0[15], apb3_if_0_idq_pi_ki_o_0[14], 
        apb3_if_0_idq_pi_ki_o_0[13], apb3_if_0_idq_pi_ki_o_0[12], 
        apb3_if_0_idq_pi_ki_o_0[11], apb3_if_0_idq_pi_ki_o_0[10], 
        apb3_if_0_idq_pi_ki_o_0[9], apb3_if_0_idq_pi_ki_o_0[8], 
        apb3_if_0_idq_pi_ki_o_0[7], apb3_if_0_idq_pi_ki_o_0[6], 
        apb3_if_0_idq_pi_ki_o_0[5], apb3_if_0_idq_pi_ki_o_0[4], 
        apb3_if_0_idq_pi_ki_o_0[3], apb3_if_0_idq_pi_ki_o_0[2], 
        apb3_if_0_idq_pi_ki_o_0[1], apb3_if_0_idq_pi_ki_o_0[0]}), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA({
        MC_System_0_AMBA_SLAVE_1_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]}), .apb3_if_0_idq_pi_kp_o({
        apb3_if_0_idq_pi_kp_o[17], apb3_if_0_idq_pi_kp_o[16], 
        apb3_if_0_idq_pi_kp_o[15], apb3_if_0_idq_pi_kp_o[14], 
        apb3_if_0_idq_pi_kp_o[13], apb3_if_0_idq_pi_kp_o[12], 
        apb3_if_0_idq_pi_kp_o[11], apb3_if_0_idq_pi_kp_o[10], 
        apb3_if_0_idq_pi_kp_o[9], apb3_if_0_idq_pi_kp_o[8], 
        apb3_if_0_idq_pi_kp_o[7], apb3_if_0_idq_pi_kp_o[6], 
        apb3_if_0_idq_pi_kp_o[5], apb3_if_0_idq_pi_kp_o[4], 
        apb3_if_0_idq_pi_kp_o[3], apb3_if_0_idq_pi_kp_o[2], 
        apb3_if_0_idq_pi_kp_o[1], apb3_if_0_idq_pi_kp_o[0]}), 
        .apb3_if_0_olmng_dv_o({apb3_if_0_olmng_dv_o[17], 
        apb3_if_0_olmng_dv_o[16], apb3_if_0_olmng_dv_o[15], 
        apb3_if_0_olmng_dv_o[14], apb3_if_0_olmng_dv_o[13], 
        apb3_if_0_olmng_dv_o[12], apb3_if_0_olmng_dv_o[11], 
        apb3_if_0_olmng_dv_o[10], apb3_if_0_olmng_dv_o[9], 
        apb3_if_0_olmng_dv_o[8], apb3_if_0_olmng_dv_o[7], 
        apb3_if_0_olmng_dv_o[6], apb3_if_0_olmng_dv_o[5], 
        apb3_if_0_olmng_dv_o[4], apb3_if_0_olmng_dv_o[3], 
        apb3_if_0_olmng_dv_o[2], apb3_if_0_olmng_dv_o[1], 
        apb3_if_0_olmng_dv_o[0]}), .apb3_if_0_olmng_iq_ref_in_o({
        apb3_if_0_olmng_iq_ref_in_o[17], 
        apb3_if_0_olmng_iq_ref_in_o[16], 
        apb3_if_0_olmng_iq_ref_in_o[15], 
        apb3_if_0_olmng_iq_ref_in_o[14], 
        apb3_if_0_olmng_iq_ref_in_o[13], 
        apb3_if_0_olmng_iq_ref_in_o[12], 
        apb3_if_0_olmng_iq_ref_in_o[11], 
        apb3_if_0_olmng_iq_ref_in_o[10], 
        apb3_if_0_olmng_iq_ref_in_o[9], apb3_if_0_olmng_iq_ref_in_o[8], 
        apb3_if_0_olmng_iq_ref_in_o[7], apb3_if_0_olmng_iq_ref_in_o[6], 
        apb3_if_0_olmng_iq_ref_in_o[5], apb3_if_0_olmng_iq_ref_in_o[4], 
        apb3_if_0_olmng_iq_ref_in_o[3], apb3_if_0_olmng_iq_ref_in_o[2], 
        apb3_if_0_olmng_iq_ref_in_o[1], apb3_if_0_olmng_iq_ref_in_o[0]})
        , .apb3_if_0_olmng_theta_factor_o({
        apb3_if_0_olmng_theta_factor_o[17], 
        apb3_if_0_olmng_theta_factor_o[16], 
        apb3_if_0_olmng_theta_factor_o[15], 
        apb3_if_0_olmng_theta_factor_o[14], 
        apb3_if_0_olmng_theta_factor_o[13], 
        apb3_if_0_olmng_theta_factor_o[12], 
        apb3_if_0_olmng_theta_factor_o[11], 
        apb3_if_0_olmng_theta_factor_o[10], 
        apb3_if_0_olmng_theta_factor_o[9], 
        apb3_if_0_olmng_theta_factor_o[8], 
        apb3_if_0_olmng_theta_factor_o[7], 
        apb3_if_0_olmng_theta_factor_o[6], 
        apb3_if_0_olmng_theta_factor_o[5], 
        apb3_if_0_olmng_theta_factor_o[4], 
        apb3_if_0_olmng_theta_factor_o[3], 
        apb3_if_0_olmng_theta_factor_o[2], 
        apb3_if_0_olmng_theta_factor_o[1], 
        apb3_if_0_olmng_theta_factor_o[0]}), 
        .apb3_if_0_pwm_dead_time_val_o({
        apb3_if_0_pwm_dead_time_val_o[17], 
        apb3_if_0_pwm_dead_time_val_o[16], 
        apb3_if_0_pwm_dead_time_val_o[15], 
        apb3_if_0_pwm_dead_time_val_o[14], 
        apb3_if_0_pwm_dead_time_val_o[13], 
        apb3_if_0_pwm_dead_time_val_o[12], 
        apb3_if_0_pwm_dead_time_val_o[11], 
        apb3_if_0_pwm_dead_time_val_o[10], 
        apb3_if_0_pwm_dead_time_val_o[9], 
        apb3_if_0_pwm_dead_time_val_o[8], 
        apb3_if_0_pwm_dead_time_val_o[7], 
        apb3_if_0_pwm_dead_time_val_o[6], 
        apb3_if_0_pwm_dead_time_val_o[5], 
        apb3_if_0_pwm_dead_time_val_o[4], 
        apb3_if_0_pwm_dead_time_val_o[3], 
        apb3_if_0_pwm_dead_time_val_o[2], 
        apb3_if_0_pwm_dead_time_val_o[1], 
        apb3_if_0_pwm_dead_time_val_o[0]}), 
        .apb3_if_0_pwm_delay_time_val_o({
        apb3_if_0_pwm_delay_time_val_o[17], 
        apb3_if_0_pwm_delay_time_val_o[16], 
        apb3_if_0_pwm_delay_time_val_o[15], 
        apb3_if_0_pwm_delay_time_val_o[14], 
        apb3_if_0_pwm_delay_time_val_o[13], 
        apb3_if_0_pwm_delay_time_val_o[12], 
        apb3_if_0_pwm_delay_time_val_o[11], 
        apb3_if_0_pwm_delay_time_val_o[10], 
        apb3_if_0_pwm_delay_time_val_o[9], 
        apb3_if_0_pwm_delay_time_val_o[8], 
        apb3_if_0_pwm_delay_time_val_o[7], 
        apb3_if_0_pwm_delay_time_val_o[6], 
        apb3_if_0_pwm_delay_time_val_o[5], 
        apb3_if_0_pwm_delay_time_val_o[4], 
        apb3_if_0_pwm_delay_time_val_o[3], 
        apb3_if_0_pwm_delay_time_val_o[2], 
        apb3_if_0_pwm_delay_time_val_o[1], 
        apb3_if_0_pwm_delay_time_val_o[0]}), .apb3_if_0_pwm_gain_val_o({
        apb3_if_0_pwm_gain_val_o[17], apb3_if_0_pwm_gain_val_o[16], 
        apb3_if_0_pwm_gain_val_o[15], apb3_if_0_pwm_gain_val_o[14], 
        apb3_if_0_pwm_gain_val_o[13], apb3_if_0_pwm_gain_val_o[12], 
        apb3_if_0_pwm_gain_val_o[11], apb3_if_0_pwm_gain_val_o[10], 
        apb3_if_0_pwm_gain_val_o[9], apb3_if_0_pwm_gain_val_o[8], 
        apb3_if_0_pwm_gain_val_o[7], apb3_if_0_pwm_gain_val_o[6], 
        apb3_if_0_pwm_gain_val_o[5], apb3_if_0_pwm_gain_val_o[4], 
        apb3_if_0_pwm_gain_val_o[3], apb3_if_0_pwm_gain_val_o[2], 
        apb3_if_0_pwm_gain_val_o[1]}), .apb3_if_0_pwm_period_val_o({
        apb3_if_0_pwm_period_val_o[17], apb3_if_0_pwm_period_val_o[16], 
        apb3_if_0_pwm_period_val_o[15], apb3_if_0_pwm_period_val_o[14], 
        apb3_if_0_pwm_period_val_o[13], apb3_if_0_pwm_period_val_o[12], 
        apb3_if_0_pwm_period_val_o[11], apb3_if_0_pwm_period_val_o[10], 
        apb3_if_0_pwm_period_val_o[9], apb3_if_0_pwm_period_val_o[8], 
        apb3_if_0_pwm_period_val_o[7], apb3_if_0_pwm_period_val_o[6], 
        apb3_if_0_pwm_period_val_o[5], apb3_if_0_pwm_period_val_o[4], 
        apb3_if_0_pwm_period_val_o[3], apb3_if_0_pwm_period_val_o[2], 
        apb3_if_0_pwm_period_val_o[1], apb3_if_0_pwm_period_val_o[0]}), 
        .apb3_if_0_rate_limit_rate_cnt_o({
        apb3_if_0_rate_limit_rate_cnt_o[17], 
        apb3_if_0_rate_limit_rate_cnt_o[16], 
        apb3_if_0_rate_limit_rate_cnt_o[15], 
        apb3_if_0_rate_limit_rate_cnt_o[14], 
        apb3_if_0_rate_limit_rate_cnt_o[13], 
        apb3_if_0_rate_limit_rate_cnt_o[12], 
        apb3_if_0_rate_limit_rate_cnt_o[11], 
        apb3_if_0_rate_limit_rate_cnt_o[10], 
        apb3_if_0_rate_limit_rate_cnt_o[9], 
        apb3_if_0_rate_limit_rate_cnt_o[8], 
        apb3_if_0_rate_limit_rate_cnt_o[7], 
        apb3_if_0_rate_limit_rate_cnt_o[6], 
        apb3_if_0_rate_limit_rate_cnt_o[5], 
        apb3_if_0_rate_limit_rate_cnt_o[4], 
        apb3_if_0_rate_limit_rate_cnt_o[3], 
        apb3_if_0_rate_limit_rate_cnt_o[2], 
        apb3_if_0_rate_limit_rate_cnt_o[1], 
        apb3_if_0_rate_limit_rate_cnt_o[0]}), 
        .apb3_if_0_rate_limit_ref_in_o({
        apb3_if_0_rate_limit_ref_in_o[17], 
        apb3_if_0_rate_limit_ref_in_o[16], 
        apb3_if_0_rate_limit_ref_in_o[15], 
        apb3_if_0_rate_limit_ref_in_o[14], 
        apb3_if_0_rate_limit_ref_in_o[13], 
        apb3_if_0_rate_limit_ref_in_o[12], 
        apb3_if_0_rate_limit_ref_in_o[11], 
        apb3_if_0_rate_limit_ref_in_o[10], 
        apb3_if_0_rate_limit_ref_in_o[9], 
        apb3_if_0_rate_limit_ref_in_o[8], 
        apb3_if_0_rate_limit_ref_in_o[7], 
        apb3_if_0_rate_limit_ref_in_o[6], 
        apb3_if_0_rate_limit_ref_in_o[5], 
        apb3_if_0_rate_limit_ref_in_o[4], 
        apb3_if_0_rate_limit_ref_in_o[3], 
        apb3_if_0_rate_limit_ref_in_o[2], 
        apb3_if_0_rate_limit_ref_in_o[1], 
        apb3_if_0_rate_limit_ref_in_o[0]}), 
        .apb3_if_0_rate_limit_slew_cnt_o({
        apb3_if_0_rate_limit_slew_cnt_o[17], 
        apb3_if_0_rate_limit_slew_cnt_o[16], 
        apb3_if_0_rate_limit_slew_cnt_o[15], 
        apb3_if_0_rate_limit_slew_cnt_o[14], 
        apb3_if_0_rate_limit_slew_cnt_o[13], 
        apb3_if_0_rate_limit_slew_cnt_o[12], 
        apb3_if_0_rate_limit_slew_cnt_o[11], 
        apb3_if_0_rate_limit_slew_cnt_o[10], 
        apb3_if_0_rate_limit_slew_cnt_o[9], 
        apb3_if_0_rate_limit_slew_cnt_o[8], 
        apb3_if_0_rate_limit_slew_cnt_o[7], 
        apb3_if_0_rate_limit_slew_cnt_o[6], 
        apb3_if_0_rate_limit_slew_cnt_o[5], 
        apb3_if_0_rate_limit_slew_cnt_o[4], 
        apb3_if_0_rate_limit_slew_cnt_o[3], 
        apb3_if_0_rate_limit_slew_cnt_o[2], 
        apb3_if_0_rate_limit_slew_cnt_o[1], 
        apb3_if_0_rate_limit_slew_cnt_o[0]}), 
        .apb3_if_0_seq_cntl_cl_omega_o({
        apb3_if_0_seq_cntl_cl_omega_o[17], 
        apb3_if_0_seq_cntl_cl_omega_o[16], 
        apb3_if_0_seq_cntl_cl_omega_o[15], 
        apb3_if_0_seq_cntl_cl_omega_o[14], 
        apb3_if_0_seq_cntl_cl_omega_o[13], 
        apb3_if_0_seq_cntl_cl_omega_o[12], 
        apb3_if_0_seq_cntl_cl_omega_o[11], 
        apb3_if_0_seq_cntl_cl_omega_o[10], 
        apb3_if_0_seq_cntl_cl_omega_o[9], 
        apb3_if_0_seq_cntl_cl_omega_o[8], 
        apb3_if_0_seq_cntl_cl_omega_o[7], 
        apb3_if_0_seq_cntl_cl_omega_o[6], 
        apb3_if_0_seq_cntl_cl_omega_o[5], 
        apb3_if_0_seq_cntl_cl_omega_o[4], 
        apb3_if_0_seq_cntl_cl_omega_o[3], 
        apb3_if_0_seq_cntl_cl_omega_o[2], 
        apb3_if_0_seq_cntl_cl_omega_o[1], 
        apb3_if_0_seq_cntl_cl_omega_o[0]}), .apb3_if_0_speed_pi_ki_o({
        apb3_if_0_speed_pi_ki_o[17], apb3_if_0_speed_pi_ki_o[16], 
        apb3_if_0_speed_pi_ki_o[15], apb3_if_0_speed_pi_ki_o[14], 
        apb3_if_0_speed_pi_ki_o[13], apb3_if_0_speed_pi_ki_o[12], 
        apb3_if_0_speed_pi_ki_o[11], apb3_if_0_speed_pi_ki_o[10], 
        apb3_if_0_speed_pi_ki_o[9], apb3_if_0_speed_pi_ki_o[8], 
        apb3_if_0_speed_pi_ki_o[7], apb3_if_0_speed_pi_ki_o[6], 
        apb3_if_0_speed_pi_ki_o[5], apb3_if_0_speed_pi_ki_o[4], 
        apb3_if_0_speed_pi_ki_o[3], apb3_if_0_speed_pi_ki_o[2], 
        apb3_if_0_speed_pi_ki_o[1], apb3_if_0_speed_pi_ki_o[0]}), 
        .apb3_if_0_filter_factor_bemf_o({
        apb3_if_0_filter_factor_bemf_o[3], 
        apb3_if_0_filter_factor_bemf_o[2], 
        apb3_if_0_filter_factor_bemf_o[1], 
        apb3_if_0_filter_factor_bemf_o[0]}), 
        .apb3_if_0_auto_restart_no_o({apb3_if_0_auto_restart_no_o[3], 
        apb3_if_0_auto_restart_no_o[2], apb3_if_0_auto_restart_no_o[1], 
        apb3_if_0_auto_restart_no_o[0]}), .apb3_if_0_speed_pi_kp_o({
        apb3_if_0_speed_pi_kp_o[17], apb3_if_0_speed_pi_kp_o[16], 
        apb3_if_0_speed_pi_kp_o[15], apb3_if_0_speed_pi_kp_o[14], 
        apb3_if_0_speed_pi_kp_o[13], apb3_if_0_speed_pi_kp_o[12], 
        apb3_if_0_speed_pi_kp_o[11], apb3_if_0_speed_pi_kp_o[10], 
        apb3_if_0_speed_pi_kp_o[9], apb3_if_0_speed_pi_kp_o[8], 
        apb3_if_0_speed_pi_kp_o[7], apb3_if_0_speed_pi_kp_o[6], 
        apb3_if_0_speed_pi_kp_o[5], apb3_if_0_speed_pi_kp_o[4], 
        apb3_if_0_speed_pi_kp_o[3], apb3_if_0_speed_pi_kp_o[2], 
        apb3_if_0_speed_pi_kp_o[1], apb3_if_0_speed_pi_kp_o[0]}), 
        .apb3_if_0_adc_control_reg_val_o({
        apb3_if_0_adc_control_reg_val_o[5], 
        apb3_if_0_adc_control_reg_val_o[4], 
        apb3_if_0_adc_control_reg_val_o[3], 
        apb3_if_0_adc_control_reg_val_o[2], 
        apb3_if_0_adc_control_reg_val_o[1], 
        apb3_if_0_adc_control_reg_val_o[0]}), 
        .apb3_if_0_seq_cntl_config_o({apb3_if_0_seq_cntl_config_o[3], 
        apb3_if_0_seq_cntl_config_o[2], apb3_if_0_seq_cntl_config_o[1], 
        apb3_if_0_seq_cntl_config_o[0]}), 
        .apb3_if_0_filter_factor_omega_o({
        apb3_if_0_filter_factor_omega_o[3], 
        apb3_if_0_filter_factor_omega_o[2], 
        apb3_if_0_filter_factor_omega_o[1], 
        apb3_if_0_filter_factor_omega_o[0]}), 
        .apb3_if_0_adc_channel_ch0_o({apb3_if_0_adc_channel_ch0_o[15], 
        apb3_if_0_adc_channel_ch0_o[14], 
        apb3_if_0_adc_channel_ch0_o[13], 
        apb3_if_0_adc_channel_ch0_o[12], 
        apb3_if_0_adc_channel_ch0_o[11], 
        apb3_if_0_adc_channel_ch0_o[10], 
        apb3_if_0_adc_channel_ch0_o[9], apb3_if_0_adc_channel_ch0_o[8], 
        apb3_if_0_adc_channel_ch0_o[7], apb3_if_0_adc_channel_ch0_o[6], 
        apb3_if_0_adc_channel_ch0_o[5], apb3_if_0_adc_channel_ch0_o[4], 
        apb3_if_0_adc_channel_ch0_o[3], apb3_if_0_adc_channel_ch0_o[2], 
        apb3_if_0_adc_channel_ch0_o[1], apb3_if_0_adc_channel_ch0_o[0]})
        , .apb3_if_0_adc_channel_ch1_o({
        apb3_if_0_adc_channel_ch1_o[15], 
        apb3_if_0_adc_channel_ch1_o[14], 
        apb3_if_0_adc_channel_ch1_o[13], 
        apb3_if_0_adc_channel_ch1_o[12], 
        apb3_if_0_adc_channel_ch1_o[11], 
        apb3_if_0_adc_channel_ch1_o[10], 
        apb3_if_0_adc_channel_ch1_o[9], apb3_if_0_adc_channel_ch1_o[8], 
        apb3_if_0_adc_channel_ch1_o[7], apb3_if_0_adc_channel_ch1_o[6], 
        apb3_if_0_adc_channel_ch1_o[5], apb3_if_0_adc_channel_ch1_o[4], 
        apb3_if_0_adc_channel_ch1_o[3], apb3_if_0_adc_channel_ch1_o[2], 
        apb3_if_0_adc_channel_ch1_o[1], apb3_if_0_adc_channel_ch1_o[0]})
        , .apb3_if_0_adc_channel_ch2_o({
        apb3_if_0_adc_channel_ch2_o[15], 
        apb3_if_0_adc_channel_ch2_o[14], 
        apb3_if_0_adc_channel_ch2_o[13], 
        apb3_if_0_adc_channel_ch2_o[12], 
        apb3_if_0_adc_channel_ch2_o[11], 
        apb3_if_0_adc_channel_ch2_o[10], 
        apb3_if_0_adc_channel_ch2_o[9], apb3_if_0_adc_channel_ch2_o[8], 
        apb3_if_0_adc_channel_ch2_o[7], apb3_if_0_adc_channel_ch2_o[6], 
        apb3_if_0_adc_channel_ch2_o[5], apb3_if_0_adc_channel_ch2_o[4], 
        apb3_if_0_adc_channel_ch2_o[3], apb3_if_0_adc_channel_ch2_o[2], 
        apb3_if_0_adc_channel_ch2_o[1], apb3_if_0_adc_channel_ch2_o[0]})
        , .apb3_if_0_adc_channel_ch3_o({
        apb3_if_0_adc_channel_ch3_o[15], 
        apb3_if_0_adc_channel_ch3_o[14], 
        apb3_if_0_adc_channel_ch3_o[13], 
        apb3_if_0_adc_channel_ch3_o[12], 
        apb3_if_0_adc_channel_ch3_o[11], 
        apb3_if_0_adc_channel_ch3_o[10], 
        apb3_if_0_adc_channel_ch3_o[9], apb3_if_0_adc_channel_ch3_o[8], 
        apb3_if_0_adc_channel_ch3_o[7], apb3_if_0_adc_channel_ch3_o[6], 
        apb3_if_0_adc_channel_ch3_o[5], apb3_if_0_adc_channel_ch3_o[4], 
        apb3_if_0_adc_channel_ch3_o[3], apb3_if_0_adc_channel_ch3_o[2], 
        apb3_if_0_adc_channel_ch3_o[1], apb3_if_0_adc_channel_ch3_o[0]})
        , .apb3_if_0_Ls_by_Ts_pu_o({apb3_if_0_Ls_by_Ts_pu_o[17], 
        apb3_if_0_Ls_by_Ts_pu_o[16], apb3_if_0_Ls_by_Ts_pu_o[15], 
        apb3_if_0_Ls_by_Ts_pu_o[14], apb3_if_0_Ls_by_Ts_pu_o[13], 
        apb3_if_0_Ls_by_Ts_pu_o[12], apb3_if_0_Ls_by_Ts_pu_o[11], 
        apb3_if_0_Ls_by_Ts_pu_o[10], apb3_if_0_Ls_by_Ts_pu_o[9], 
        apb3_if_0_Ls_by_Ts_pu_o[8], apb3_if_0_Ls_by_Ts_pu_o[7], 
        apb3_if_0_Ls_by_Ts_pu_o[6], apb3_if_0_Ls_by_Ts_pu_o[5], 
        apb3_if_0_Ls_by_Ts_pu_o[4], apb3_if_0_Ls_by_Ts_pu_o[3], 
        apb3_if_0_Ls_by_Ts_pu_o[2], apb3_if_0_Ls_by_Ts_pu_o[1], 
        apb3_if_0_Ls_by_Ts_pu_o[0]}), .apb3_if_0_Rs_pu_o({
        apb3_if_0_Rs_pu_o[17], apb3_if_0_Rs_pu_o[16], 
        apb3_if_0_Rs_pu_o[15], apb3_if_0_Rs_pu_o[14], 
        apb3_if_0_Rs_pu_o[13], apb3_if_0_Rs_pu_o[12], 
        apb3_if_0_Rs_pu_o[11], apb3_if_0_Rs_pu_o[10], 
        apb3_if_0_Rs_pu_o[9], apb3_if_0_Rs_pu_o[8], 
        apb3_if_0_Rs_pu_o[7], apb3_if_0_Rs_pu_o[6], 
        apb3_if_0_Rs_pu_o[5], apb3_if_0_Rs_pu_o[4], 
        apb3_if_0_Rs_pu_o[3], apb3_if_0_Rs_pu_o[2], 
        apb3_if_0_Rs_pu_o[1], apb3_if_0_Rs_pu_o[0]}), 
        .apb3_if_0_adc_oc_thresh_o({apb3_if_0_adc_oc_thresh_o[17], 
        apb3_if_0_adc_oc_thresh_o[16], apb3_if_0_adc_oc_thresh_o[15], 
        apb3_if_0_adc_oc_thresh_o[14], apb3_if_0_adc_oc_thresh_o[13], 
        apb3_if_0_adc_oc_thresh_o[12], apb3_if_0_adc_oc_thresh_o[11], 
        apb3_if_0_adc_oc_thresh_o[10], apb3_if_0_adc_oc_thresh_o[9], 
        apb3_if_0_adc_oc_thresh_o[8], apb3_if_0_adc_oc_thresh_o[7], 
        apb3_if_0_adc_oc_thresh_o[6], apb3_if_0_adc_oc_thresh_o[5], 
        apb3_if_0_adc_oc_thresh_o[4], apb3_if_0_adc_oc_thresh_o[3], 
        apb3_if_0_adc_oc_thresh_o[2], apb3_if_0_adc_oc_thresh_o[1], 
        apb3_if_0_adc_oc_thresh_o[0]}), .apb3_if_0_adc_scale_val_o({
        apb3_if_0_adc_scale_val_o[17], apb3_if_0_adc_scale_val_o[16], 
        apb3_if_0_adc_scale_val_o[15], apb3_if_0_adc_scale_val_o[14], 
        apb3_if_0_adc_scale_val_o[13], apb3_if_0_adc_scale_val_o[12], 
        apb3_if_0_adc_scale_val_o[11], apb3_if_0_adc_scale_val_o[10], 
        apb3_if_0_adc_scale_val_o[9], apb3_if_0_adc_scale_val_o[8], 
        apb3_if_0_adc_scale_val_o[7], apb3_if_0_adc_scale_val_o[6], 
        apb3_if_0_adc_scale_val_o[5], apb3_if_0_adc_scale_val_o[4], 
        apb3_if_0_adc_scale_val_o[3], apb3_if_0_adc_scale_val_o[2], 
        apb3_if_0_adc_scale_val_o[1], apb3_if_0_adc_scale_val_o[0]}), 
        .apb3_if_0_angle_ki_o({apb3_if_0_angle_ki_o[17], 
        apb3_if_0_angle_ki_o[16], apb3_if_0_angle_ki_o[15], 
        apb3_if_0_angle_ki_o[14], apb3_if_0_angle_ki_o[13], 
        apb3_if_0_angle_ki_o[12], apb3_if_0_angle_ki_o[11], 
        apb3_if_0_angle_ki_o[10], apb3_if_0_angle_ki_o[9], 
        apb3_if_0_angle_ki_o[8], apb3_if_0_angle_ki_o[7], 
        apb3_if_0_angle_ki_o[6], apb3_if_0_angle_ki_o[5], 
        apb3_if_0_angle_ki_o[4], apb3_if_0_angle_ki_o[3], 
        apb3_if_0_angle_ki_o[2], apb3_if_0_angle_ki_o[1], 
        apb3_if_0_angle_ki_o[0]}), .apb3_if_0_angle_kp_o({
        apb3_if_0_angle_kp_o[17], apb3_if_0_angle_kp_o[16], 
        apb3_if_0_angle_kp_o[15], apb3_if_0_angle_kp_o[14], 
        apb3_if_0_angle_kp_o[13], apb3_if_0_angle_kp_o[12], 
        apb3_if_0_angle_kp_o[11], apb3_if_0_angle_kp_o[10], 
        apb3_if_0_angle_kp_o[9], apb3_if_0_angle_kp_o[8], 
        apb3_if_0_angle_kp_o[7], apb3_if_0_angle_kp_o[6], 
        apb3_if_0_angle_kp_o[5], apb3_if_0_angle_kp_o[4], 
        apb3_if_0_angle_kp_o[3], apb3_if_0_angle_kp_o[2], 
        apb3_if_0_angle_kp_o[1], apb3_if_0_angle_kp_o[0]}), 
        .prdata_o_1_0_1_d0(prdata_o_1_0[3]), .prdata_o_1_4({
        prdata_o_1_4[2]}), .ADC_SCALING_1_ib_adc_o({
        ADC_SCALING_1_ib_adc_o[17], ADC_SCALING_1_ib_adc_o[16], 
        ADC_SCALING_1_ib_adc_o[15], ADC_SCALING_1_ib_adc_o[14], 
        ADC_SCALING_1_ib_adc_o[13], ADC_SCALING_1_ib_adc_o[12], 
        ADC_SCALING_1_ib_adc_o[11], ADC_SCALING_1_ib_adc_o[10], 
        ADC_SCALING_1_ib_adc_o[9], ADC_SCALING_1_ib_adc_o[8], 
        ADC_SCALING_1_ib_adc_o[7], ADC_SCALING_1_ib_adc_o[6], 
        ADC_SCALING_1_ib_adc_o[5], ADC_SCALING_1_ib_adc_o[4], 
        ADC_SCALING_1_ib_adc_o[3], ADC_SCALING_1_ib_adc_o[2], 
        ADC_SCALING_1_ib_adc_o[1], ADC_SCALING_1_ib_adc_o[0]}), 
        .ADC_SCALING_1_ia_adc_o({ADC_SCALING_1_ia_adc_o[17], 
        ADC_SCALING_1_ia_adc_o[16], ADC_SCALING_1_ia_adc_o[15], 
        ADC_SCALING_1_ia_adc_o[14], ADC_SCALING_1_ia_adc_o[13], 
        ADC_SCALING_1_ia_adc_o[12], ADC_SCALING_1_ia_adc_o[11], 
        ADC_SCALING_1_ia_adc_o[10], ADC_SCALING_1_ia_adc_o[9], 
        ADC_SCALING_1_ia_adc_o[8], ADC_SCALING_1_ia_adc_o[7], 
        ADC_SCALING_1_ia_adc_o[6], ADC_SCALING_1_ia_adc_o[5], 
        ADC_SCALING_1_ia_adc_o[4], ADC_SCALING_1_ia_adc_o[3], 
        ADC_SCALING_1_ia_adc_o[2], ADC_SCALING_1_ia_adc_o[1], 
        ADC_SCALING_1_ia_adc_o[0]}), .FOC_TRANSFORMS_0_iq_o({
        FOC_TRANSFORMS_0_iq_o[17], FOC_TRANSFORMS_0_iq_o[16], 
        FOC_TRANSFORMS_0_iq_o[15], FOC_TRANSFORMS_0_iq_o[14], 
        FOC_TRANSFORMS_0_iq_o[13], FOC_TRANSFORMS_0_iq_o[12], 
        FOC_TRANSFORMS_0_iq_o[11], FOC_TRANSFORMS_0_iq_o[10], 
        FOC_TRANSFORMS_0_iq_o[9], FOC_TRANSFORMS_0_iq_o[8], 
        FOC_TRANSFORMS_0_iq_o[7], FOC_TRANSFORMS_0_iq_o[6], 
        FOC_TRANSFORMS_0_iq_o[5], FOC_TRANSFORMS_0_iq_o[4], 
        FOC_TRANSFORMS_0_iq_o[3], FOC_TRANSFORMS_0_iq_o[2], 
        FOC_TRANSFORMS_0_iq_o[1], FOC_TRANSFORMS_0_iq_o[0]}), 
        .FOC_TRANSFORMS_0_id_o({FOC_TRANSFORMS_0_id_o[17], 
        FOC_TRANSFORMS_0_id_o[16], FOC_TRANSFORMS_0_id_o[15], 
        FOC_TRANSFORMS_0_id_o[14], FOC_TRANSFORMS_0_id_o[13], 
        FOC_TRANSFORMS_0_id_o[12], FOC_TRANSFORMS_0_id_o[11], 
        FOC_TRANSFORMS_0_id_o[10], FOC_TRANSFORMS_0_id_o[9], 
        FOC_TRANSFORMS_0_id_o[8], FOC_TRANSFORMS_0_id_o[7], 
        FOC_TRANSFORMS_0_id_o[6], FOC_TRANSFORMS_0_id_o[5], 
        FOC_TRANSFORMS_0_id_o[4], FOC_TRANSFORMS_0_id_o[3], 
        FOC_TRANSFORMS_0_id_o[2], FOC_TRANSFORMS_0_id_o[1], 
        FOC_TRANSFORMS_0_id_o[0]}), .RATE_LIMITER_0_rl_out_o({
        RATE_LIMITER_0_rl_out_o[17], RATE_LIMITER_0_rl_out_o[16], 
        RATE_LIMITER_0_rl_out_o[15], RATE_LIMITER_0_rl_out_o[14], 
        RATE_LIMITER_0_rl_out_o[13], RATE_LIMITER_0_rl_out_o[12], 
        RATE_LIMITER_0_rl_out_o[11], RATE_LIMITER_0_rl_out_o[10], 
        RATE_LIMITER_0_rl_out_o[9], RATE_LIMITER_0_rl_out_o[8], 
        RATE_LIMITER_0_rl_out_o[7], RATE_LIMITER_0_rl_out_o[6], 
        RATE_LIMITER_0_rl_out_o[5], RATE_LIMITER_0_rl_out_o[4], 
        RATE_LIMITER_0_rl_out_o[3], RATE_LIMITER_0_rl_out_o[2], 
        RATE_LIMITER_0_rl_out_o[1], RATE_LIMITER_0_rl_out_o[0]}), 
        .BLDC_ESTIMATOR_1_ealpha_o({BLDC_ESTIMATOR_1_ealpha_o[17], 
        BLDC_ESTIMATOR_1_ealpha_o[16], BLDC_ESTIMATOR_1_ealpha_o[15], 
        BLDC_ESTIMATOR_1_ealpha_o[14], BLDC_ESTIMATOR_1_ealpha_o[13], 
        BLDC_ESTIMATOR_1_ealpha_o[12], BLDC_ESTIMATOR_1_ealpha_o[11], 
        BLDC_ESTIMATOR_1_ealpha_o[10], BLDC_ESTIMATOR_1_ealpha_o[9], 
        BLDC_ESTIMATOR_1_ealpha_o[8], BLDC_ESTIMATOR_1_ealpha_o[7], 
        BLDC_ESTIMATOR_1_ealpha_o[6], BLDC_ESTIMATOR_1_ealpha_o[5], 
        BLDC_ESTIMATOR_1_ealpha_o[4], BLDC_ESTIMATOR_1_ealpha_o[3], 
        BLDC_ESTIMATOR_1_ealpha_o[2], BLDC_ESTIMATOR_1_ealpha_o[1], 
        BLDC_ESTIMATOR_1_ealpha_o[0]}), .BLDC_ESTIMATOR_1_theta_o({
        BLDC_ESTIMATOR_1_theta_o[17], BLDC_ESTIMATOR_1_theta_o[16], 
        BLDC_ESTIMATOR_1_theta_o[15], BLDC_ESTIMATOR_1_theta_o[14], 
        BLDC_ESTIMATOR_1_theta_o[13], BLDC_ESTIMATOR_1_theta_o[12], 
        BLDC_ESTIMATOR_1_theta_o[11], BLDC_ESTIMATOR_1_theta_o[10], 
        BLDC_ESTIMATOR_1_theta_o[9], BLDC_ESTIMATOR_1_theta_o[8], 
        BLDC_ESTIMATOR_1_theta_o[7], BLDC_ESTIMATOR_1_theta_o[6], 
        BLDC_ESTIMATOR_1_theta_o[5], BLDC_ESTIMATOR_1_theta_o[4], 
        BLDC_ESTIMATOR_1_theta_o[3], BLDC_ESTIMATOR_1_theta_o[2], 
        BLDC_ESTIMATOR_1_theta_o[1], BLDC_ESTIMATOR_1_theta_o[0]}), 
        .OLMNG_1_theta_o({OLMNG_1_theta_o[17], OLMNG_1_theta_o[16], 
        OLMNG_1_theta_o[15], OLMNG_1_theta_o[14], OLMNG_1_theta_o[13], 
        OLMNG_1_theta_o[12], OLMNG_1_theta_o[11], OLMNG_1_theta_o[10], 
        OLMNG_1_theta_o[9], OLMNG_1_theta_o[8], OLMNG_1_theta_o[7], 
        OLMNG_1_theta_o[6], OLMNG_1_theta_o[5], OLMNG_1_theta_o[4], 
        OLMNG_1_theta_o[3], OLMNG_1_theta_o[2], OLMNG_1_theta_o[1], 
        OLMNG_1_theta_o[0]}), .adc_interface_0_result_ch1_o({
        adc_interface_0_result_ch1_o[11], 
        adc_interface_0_result_ch1_o[10], 
        adc_interface_0_result_ch1_o[9], 
        adc_interface_0_result_ch1_o[8], 
        adc_interface_0_result_ch1_o[7], 
        adc_interface_0_result_ch1_o[6], 
        adc_interface_0_result_ch1_o[5], 
        adc_interface_0_result_ch1_o[4], 
        adc_interface_0_result_ch1_o[3], 
        adc_interface_0_result_ch1_o[2], 
        adc_interface_0_result_ch1_o[1], 
        adc_interface_0_result_ch1_o[0]}), 
        .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[11], 
        adc_interface_0_result_ch0_o[10], 
        adc_interface_0_result_ch0_o[9], 
        adc_interface_0_result_ch0_o[8], 
        adc_interface_0_result_ch0_o[7], 
        adc_interface_0_result_ch0_o[6], 
        adc_interface_0_result_ch0_o[5], 
        adc_interface_0_result_ch0_o[4], 
        adc_interface_0_result_ch0_o[3], 
        adc_interface_0_result_ch0_o[2], 
        adc_interface_0_result_ch0_o[1], 
        adc_interface_0_result_ch0_o[0]}), 
        .adc_measurements_0_adc_result_ch3_o({
        adc_measurements_0_adc_result_ch3_o[11], 
        adc_measurements_0_adc_result_ch3_o[10], 
        adc_measurements_0_adc_result_ch3_o[9], 
        adc_measurements_0_adc_result_ch3_o[8], 
        adc_measurements_0_adc_result_ch3_o[7], 
        adc_measurements_0_adc_result_ch3_o[6], 
        adc_measurements_0_adc_result_ch3_o[5], 
        adc_measurements_0_adc_result_ch3_o[4], 
        adc_measurements_0_adc_result_ch3_o[3], 
        adc_measurements_0_adc_result_ch3_o[2], 
        adc_measurements_0_adc_result_ch3_o[1], 
        adc_measurements_0_adc_result_ch3_o[0]}), 
        .adc_measurements_0_adc_result_ch2_o({
        adc_measurements_0_adc_result_ch2_o[11], 
        adc_measurements_0_adc_result_ch2_o[10], 
        adc_measurements_0_adc_result_ch2_o[9], 
        adc_measurements_0_adc_result_ch2_o[8], 
        adc_measurements_0_adc_result_ch2_o[7], 
        adc_measurements_0_adc_result_ch2_o[6], 
        adc_measurements_0_adc_result_ch2_o[5], 
        adc_measurements_0_adc_result_ch2_o[4], 
        adc_measurements_0_adc_result_ch2_o[3], 
        adc_measurements_0_adc_result_ch2_o[2], 
        adc_measurements_0_adc_result_ch2_o[1], 
        adc_measurements_0_adc_result_ch2_o[0]}), 
        .prdata_o_1_0_a2_12_0({prdata_o_1_0_a2_12_0[15]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR({
        MC_System_0_AMBA_SLAVE_1_PADDR[11], 
        MC_System_0_AMBA_SLAVE_1_PADDR[10], 
        MC_System_0_AMBA_SLAVE_1_PADDR[9], 
        MC_System_0_AMBA_SLAVE_1_PADDR[8], 
        MC_System_0_AMBA_SLAVE_1_PADDR[7], 
        MC_System_0_AMBA_SLAVE_1_PADDR[6], 
        MC_System_0_AMBA_SLAVE_1_PADDR[5], 
        MC_System_0_AMBA_SLAVE_1_PADDR[4], 
        MC_System_0_AMBA_SLAVE_1_PADDR[3], 
        MC_System_0_AMBA_SLAVE_1_PADDR[2], 
        MC_System_0_AMBA_SLAVE_1_PADDR[1], 
        MC_System_0_AMBA_SLAVE_1_PADDR[0]}), .prdata_o_1_0_a2_10_0({
        prdata_o_1_0_a2_10_0[15]}), .prdata_o_1_0_a2_7_0({
        prdata_o_1_0_a2_7_0[3]}), .BLDC_ESTIMATOR_1_ebeta_filtered_o({
        BLDC_ESTIMATOR_1_ebeta_filtered_o[17], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[16], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[15], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[14], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[13], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[12], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[11], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[10], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[9], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[8], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[7], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[6], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[5], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[4], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[3], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[2], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[1], 
        BLDC_ESTIMATOR_1_ebeta_filtered_o[0]}), 
        .BLDC_ESTIMATOR_1_ebeta_o({BLDC_ESTIMATOR_1_ebeta_o[17], 
        BLDC_ESTIMATOR_1_ebeta_o[16], BLDC_ESTIMATOR_1_ebeta_o[15], 
        BLDC_ESTIMATOR_1_ebeta_o[14], BLDC_ESTIMATOR_1_ebeta_o[13], 
        BLDC_ESTIMATOR_1_ebeta_o[12], BLDC_ESTIMATOR_1_ebeta_o[11], 
        BLDC_ESTIMATOR_1_ebeta_o[10], BLDC_ESTIMATOR_1_ebeta_o[9], 
        BLDC_ESTIMATOR_1_ebeta_o[8], BLDC_ESTIMATOR_1_ebeta_o[7], 
        BLDC_ESTIMATOR_1_ebeta_o[6], BLDC_ESTIMATOR_1_ebeta_o[5], 
        BLDC_ESTIMATOR_1_ebeta_o[4], BLDC_ESTIMATOR_1_ebeta_o[3], 
        BLDC_ESTIMATOR_1_ebeta_o[2], BLDC_ESTIMATOR_1_ebeta_o[1], 
        BLDC_ESTIMATOR_1_ebeta_o[0]}), 
        .BLDC_ESTIMATOR_0_speed_filtered_o({
        BLDC_ESTIMATOR_0_speed_filtered_o[17], 
        BLDC_ESTIMATOR_0_speed_filtered_o[16], 
        BLDC_ESTIMATOR_0_speed_filtered_o[15], 
        BLDC_ESTIMATOR_0_speed_filtered_o[14], 
        BLDC_ESTIMATOR_0_speed_filtered_o[13], 
        BLDC_ESTIMATOR_0_speed_filtered_o[12], 
        BLDC_ESTIMATOR_0_speed_filtered_o[11], 
        BLDC_ESTIMATOR_0_speed_filtered_o[10], 
        BLDC_ESTIMATOR_0_speed_filtered_o[9], 
        BLDC_ESTIMATOR_0_speed_filtered_o[8], 
        BLDC_ESTIMATOR_0_speed_filtered_o[7], 
        BLDC_ESTIMATOR_0_speed_filtered_o[6], 
        BLDC_ESTIMATOR_0_speed_filtered_o[5], 
        BLDC_ESTIMATOR_0_speed_filtered_o[4], 
        BLDC_ESTIMATOR_0_speed_filtered_o[3], 
        BLDC_ESTIMATOR_0_speed_filtered_o[2], 
        BLDC_ESTIMATOR_0_speed_filtered_o[1], 
        BLDC_ESTIMATOR_0_speed_filtered_o[0]}), 
        .FOC_TRANSFORMS_0_valpha_o({FOC_TRANSFORMS_0_valpha_o[17], 
        FOC_TRANSFORMS_0_valpha_o[16], FOC_TRANSFORMS_0_valpha_o[15], 
        FOC_TRANSFORMS_0_valpha_o[14], FOC_TRANSFORMS_0_valpha_o[13], 
        FOC_TRANSFORMS_0_valpha_o[12], FOC_TRANSFORMS_0_valpha_o[11], 
        FOC_TRANSFORMS_0_valpha_o[10], FOC_TRANSFORMS_0_valpha_o[9], 
        FOC_TRANSFORMS_0_valpha_o[8], FOC_TRANSFORMS_0_valpha_o[7], 
        FOC_TRANSFORMS_0_valpha_o[6], FOC_TRANSFORMS_0_valpha_o[5], 
        FOC_TRANSFORMS_0_valpha_o[4], FOC_TRANSFORMS_0_valpha_o[3], 
        FOC_TRANSFORMS_0_valpha_o[2], FOC_TRANSFORMS_0_valpha_o[1], 
        FOC_TRANSFORMS_0_valpha_o[0]}), 
        .SPEED_ID_IQ_PI_1_iq_pi_output_o({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[0]}), .net_189({net_189[17], 
        net_189[16], net_189[15], net_189[14], net_189[13], 
        net_189[12], net_189[11], net_189[10], net_189[9], net_189[8], 
        net_189[7], net_189[6], net_189[5], net_189[4], net_189[3], 
        net_189[2], net_189[1], net_189[0]}), 
        .BLDC_ESTIMATOR_1_ealpha_filtered_o({
        BLDC_ESTIMATOR_1_ealpha_filtered_o[17], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[16], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[15], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[14], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[13], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[12], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[11], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[10], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[9], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[8], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[7], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[6], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[5], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[4], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[3], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[2], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[1], 
        BLDC_ESTIMATOR_1_ealpha_filtered_o[0]}), 
        .SPEED_ID_IQ_PI_1_id_pi_output_o({
        SPEED_ID_IQ_PI_1_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[1], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[0]}), 
        .FOC_TRANSFORMS_0_ibeta_o({FOC_TRANSFORMS_0_ibeta_o[17], 
        FOC_TRANSFORMS_0_ibeta_o[16], FOC_TRANSFORMS_0_ibeta_o[15], 
        FOC_TRANSFORMS_0_ibeta_o[14], FOC_TRANSFORMS_0_ibeta_o[13], 
        FOC_TRANSFORMS_0_ibeta_o[12], FOC_TRANSFORMS_0_ibeta_o[11], 
        FOC_TRANSFORMS_0_ibeta_o[10], FOC_TRANSFORMS_0_ibeta_o[9], 
        FOC_TRANSFORMS_0_ibeta_o[8], FOC_TRANSFORMS_0_ibeta_o[7], 
        FOC_TRANSFORMS_0_ibeta_o[6], FOC_TRANSFORMS_0_ibeta_o[5], 
        FOC_TRANSFORMS_0_ibeta_o[4], FOC_TRANSFORMS_0_ibeta_o[3], 
        FOC_TRANSFORMS_0_ibeta_o[2], FOC_TRANSFORMS_0_ibeta_o[1], 
        FOC_TRANSFORMS_0_ibeta_o[0]}), .FOC_TRANSFORMS_0_ialpha_o({
        FOC_TRANSFORMS_0_ialpha_o[17], FOC_TRANSFORMS_0_ialpha_o[16], 
        FOC_TRANSFORMS_0_ialpha_o[15], FOC_TRANSFORMS_0_ialpha_o[14], 
        FOC_TRANSFORMS_0_ialpha_o[13], FOC_TRANSFORMS_0_ialpha_o[12], 
        FOC_TRANSFORMS_0_ialpha_o[11], FOC_TRANSFORMS_0_ialpha_o[10], 
        FOC_TRANSFORMS_0_ialpha_o[9], FOC_TRANSFORMS_0_ialpha_o[8], 
        FOC_TRANSFORMS_0_ialpha_o[7], FOC_TRANSFORMS_0_ialpha_o[6], 
        FOC_TRANSFORMS_0_ialpha_o[5], FOC_TRANSFORMS_0_ialpha_o[4], 
        FOC_TRANSFORMS_0_ialpha_o[3], FOC_TRANSFORMS_0_ialpha_o[2], 
        FOC_TRANSFORMS_0_ialpha_o[1], FOC_TRANSFORMS_0_ialpha_o[0]}), 
        .FOC_TRANSFORMS_0_vbeta_o({FOC_TRANSFORMS_0_vbeta_o[17], 
        FOC_TRANSFORMS_0_vbeta_o[16], FOC_TRANSFORMS_0_vbeta_o[15], 
        FOC_TRANSFORMS_0_vbeta_o[14], FOC_TRANSFORMS_0_vbeta_o[13], 
        FOC_TRANSFORMS_0_vbeta_o[12], FOC_TRANSFORMS_0_vbeta_o[11], 
        FOC_TRANSFORMS_0_vbeta_o[10], FOC_TRANSFORMS_0_vbeta_o[9], 
        FOC_TRANSFORMS_0_vbeta_o[8], FOC_TRANSFORMS_0_vbeta_o[7], 
        FOC_TRANSFORMS_0_vbeta_o[6], FOC_TRANSFORMS_0_vbeta_o[5], 
        FOC_TRANSFORMS_0_vbeta_o[4], FOC_TRANSFORMS_0_vbeta_o[3], 
        FOC_TRANSFORMS_0_vbeta_o[2], FOC_TRANSFORMS_0_vbeta_o[1], 
        FOC_TRANSFORMS_0_vbeta_o[0]}), .BLDC_ESTIMATOR_1_pll_pi_out_o({
        BLDC_ESTIMATOR_1_pll_pi_out_o[17], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[16], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[15], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[14], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[13], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[12], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[11], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[10], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[9], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[8], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[7], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[6], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[5], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[4], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[3], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[2], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[1], 
        BLDC_ESTIMATOR_1_pll_pi_out_o[0]}), .prdata_o_1_24_3({
        prdata_o_1_24_3[1]}), .prdata_o_1_3({prdata_o_1_3[3], 
        prdata_o_1_3[2]}), .prdata_o_1_0_2({prdata_o_1_0_2[16], 
        prdata_o_1_0_2[15], prdata_o_1_0_2[14], prdata_o_1_0_2[13], 
        prdata_o_1_0_2[12]}), .prdata_o_1_0_0({prdata_o_1_0_0[16], 
        prdata_o_1_0_0[15], prdata_o_1_0_0[14], prdata_o_1_0_0[13], 
        prdata_o_1_0_0[12]}), .SEQ_CONTROLLER_1_state_o({
        SEQ_CONTROLLER_1_state_o[3], SEQ_CONTROLLER_1_state_o[2], 
        SEQ_CONTROLLER_1_state_o[1], SEQ_CONTROLLER_1_state_o[0]}), 
        .prdata_o_1_24_2({prdata_o_1_24_2[1]}), .prdata_o_1_12_3({
        prdata_o_1_12_3[11], prdata_o_1_12_3[10], prdata_o_1_12_3[9], 
        prdata_o_1_12_3[8], prdata_o_1_12_3[7], prdata_o_1_12_3[6], 
        prdata_o_1_12_3[5], prdata_o_1_12_3[4]}), .prdata_o_1_12_2({
        prdata_o_1_12_2[11], prdata_o_1_12_2[10], prdata_o_1_12_2[9], 
        prdata_o_1_12_2[8], prdata_o_1_12_2[7], prdata_o_1_12_2[6], 
        prdata_o_1_12_2[5], prdata_o_1_12_2[4]}), .prdata_o_1_12_1({
        prdata_o_1_12_1[11], prdata_o_1_12_1[10], prdata_o_1_12_1[9], 
        prdata_o_1_12_1[8], prdata_o_1_12_1[7], prdata_o_1_12_1[6], 
        prdata_o_1_12_1[5], prdata_o_1_12_1[4]}), .prdata_o_1_2({
        prdata_o_1_2[3], prdata_o_1_2[2]}), .prdata_o_1_0_1_13(
        prdata_o_1_0_1[16]), .prdata_o_1_0_1_11(prdata_o_1_0_1[14]), 
        .prdata_o_1_0_1_12(prdata_o_1_0_1[15]), .prdata_o_1_0_1_9(
        prdata_o_1_0_1[12]), .prdata_o_1_0_1_10(prdata_o_1_0_1[13]), 
        .prdata_o_1_24_4({prdata_o_1_24_4[1]}), 
        .MC_System_0_FIC_0_LOCK(MC_System_0_FIC_0_LOCK), 
        .MC_System_0_FIC_0_CLK(MC_System_0_FIC_0_CLK), 
        .apb3_if_0_stop_motor_o(apb3_if_0_stop_motor_o), 
        .apb3_if_0_start_motor_o(apb3_if_0_start_motor_o), 
        .apb3_if_0_fault_clr_o(apb3_if_0_fault_clr_o), 
        .apb3_if_0_direction_config_o(apb3_if_0_direction_config_o), 
        .N_202(N_202), .N_185(N_185), .N_2791(N_2791), .N_2779(N_2779), 
        .N_2542(N_2542), .N_1508(N_1508), .N_1083(N_1083), .N_2606(
        N_2606), .N_2585(N_2585), .N_1080(N_1080), .N_1077(N_1077), 
        .N_1014(N_1014), .N_176(N_176), .N_1007(N_1007), .N_2522(
        N_2522), .N_2532(N_2532), .MC_System_0_AMBA_SLAVE_1_PWRITE(
        MC_System_0_AMBA_SLAVE_1_PWRITE), 
        .MC_System_0_AMBA_SLAVE_1_PENABLE(
        MC_System_0_AMBA_SLAVE_1_PENABLE), .N_2787(N_2787), .N_2704(
        N_2704), .adc_channel_ch3_o_1_sqmuxa_0_a2_0_0(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .prdata_o190_0_a2_0_out(
        prdata_o190_0_a2_0_out), .N_172(N_172), .N_2660(N_2660), 
        .N_2778(N_2778), .N_2784(N_2784), .prdata_o200_2(prdata_o200_2)
        , .N_2470(N_2470), .N_2785(N_2785), 
        .MC_System_0_AMBA_SLAVE_0_PSELx(MC_System_0_AMBA_SLAVE_0_PSELx)
        , .N_2734(N_2734), .N_2661(N_2661), .N_2728(N_2728), .N_193(
        N_193));
    
endmodule


module mas_pwm_scl_44s_18s_2s_0(
       s_product,
       s_mult_in0_5,
       pwm_gain_i,
       pwm_period_i,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en
    );
output [33:16] s_product;
input  [17:0] s_mult_in0_5;
input  [17:1] pwm_gain_i;
input  [0:0] pwm_period_i;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [43:0] product_o;
    wire MSC_net_147, MSC_net_148, MSC_net_149;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
haNO4w019gstxNlBMxeZMrqtZf+ssCdGRM1T1itrhNsSdh7/0qiAC8R+AT1epjTq
dOqdhWMgs9zMD1ER4Mjj4IEWr8FTHwoEUG5HMumizN+a8ow+5T6llXkfj88rM2VL
4LeF83gwHHgsQJjeTZH2xOxHc4AgzWgaRW1uWzCpRAE=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8235)
`pragma protect data_block
[encoded data, 8064 characters]
IZ6EiQkH/5TuNKBaiG4rr8s6I58C8i17jEnKCF2Ytq8=

`pragma protect end_protected

endmodule


module PWM_SCALING_2s_44s_15s_0_1_2_4_0(
       reset_i,
       sys_clk_i,
       start_i,
       va_i,
       vb_i,
       vc_i,
       pwm_period_i,
       pwm_gain_i,
       Va_o,
       Vb_o,
       Vc_o,
       done_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  [17:0] va_i;
input  [17:0] vb_i;
input  [17:0] vc_i;
input  [17:0] pwm_period_i;
input  [17:0] pwm_gain_i;
output [17:0] Va_o;
output [17:0] Vb_o;
output [17:0] Vc_o;
output done_o;

    wire [17:0] Vc_o_net_1;
    wire [33:16] s_product;
    wire [4:0] s_state;
    wire [17:0] \MUL_INP_GEN_PROC.s_mult_in0_5 ;
    wire [1:1] s_state_ns;
    wire [4:4] s_state_ns_i;
    wire MSC_net_174, MSC_net_175, MSC_net_176, MSC_net_177, 
        MSC_net_178, MSC_net_179, MSC_net_180, MSC_net_181, 
        MSC_net_182, MSC_net_183, MSC_net_184, MSC_net_185, 
        MSC_net_186, MSC_net_187, MSC_net_188, MSC_net_189, 
        MSC_net_190, MSC_net_191, MSC_net_192, MSC_net_193, 
        MSC_net_194, MSC_net_195, MSC_net_196, MSC_net_197, 
        MSC_net_198, MSC_net_199, MSC_net_200, MSC_net_201, 
        MSC_net_202, MSC_net_203, MSC_net_204, MSC_net_205, 
        MSC_net_206;
    assign Vc_o[17] = Vc_o_net_1[0];
    assign Vc_o[16] = Vc_o_net_1[0];
    assign Vc_o[15] = Vc_o_net_1[0];
    assign Vc_o[14] = Vc_o_net_1[0];
    assign Vc_o[13] = Vc_o_net_1[0];
    assign Vc_o[12] = Vc_o_net_1[0];
    assign Vc_o[11] = Vc_o_net_1[0];
    assign Vc_o[10] = Vc_o_net_1[0];
    assign Vc_o[9] = Vc_o_net_1[0];
    assign Vc_o[8] = Vc_o_net_1[0];
    assign Vc_o[7] = Vc_o_net_1[0];
    assign Vc_o[6] = Vc_o_net_1[0];
    assign Vc_o[5] = Vc_o_net_1[0];
    assign Vc_o[4] = Vc_o_net_1[0];
    assign Vc_o[3] = Vc_o_net_1[0];
    assign Vc_o[2] = Vc_o_net_1[0];
    assign Vc_o[1] = Vc_o_net_1[0];
    assign Vc_o[0] = Vc_o_net_1[0];
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
hn5tis+V0HbagfO/baNUpRcKJNIU1/M643NELfqOU9hgmY2gQ/0dJRGfZ2I0z4dh
7XqlwTPXDuz3x0KVZIfyCJiptnRRRTPQuoEHbWr83nD/5eLoqDLJi7TCxt8GCDB7
OGiqRc9LWWe4YuzpUoE/yxHpsNo3u6Pl35byOOmwGGA=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=20910)
`pragma protect data_block
[encoded data, 20544 characters]
yCv4NWjF3LkcXjzpaWeZr3qwNmd7B0hYkHk7LZYwsyY=

`pragma protect end_protected

endmodule


module cordic_rot_foc_18s_15s_0_1_0(
       s_xo,
       s_yo,
       s_yi,
       s_xi,
       reset_i,
       sys_clk_i,
       N_579,
       N_580,
       N_581,
       N_582,
       N_583,
       N_584,
       N_585,
       N_586,
       N_587,
       N_588,
       N_589,
       N_572,
       N_573,
       N_574,
       N_575,
       N_576,
       N_577,
       N_578,
       s_cordic_done,
       start_ipark_i,
       start_park_i,
       s_start_cordic
    );
output [17:0] s_xo;
output [17:0] s_yo;
input  [16:0] s_yi;
input  [16:0] s_xi;
input  reset_i;
input  sys_clk_i;
input  N_579;
input  N_580;
input  N_581;
input  N_582;
input  N_583;
input  N_584;
input  N_585;
input  N_586;
input  N_587;
input  N_588;
input  N_589;
input  N_572;
input  N_573;
input  N_574;
input  N_575;
input  N_576;
input  N_577;
input  N_578;
output s_cordic_done;
input  start_ipark_i;
input  start_park_i;
output s_start_cordic;

    wire [3:0] s_index;
    wire [3:1] s_index_5_iv_i_0;
    wire [17:1] s_yi_rot;
    wire [17:0] s_yi_rot_6;
    wire [0:0] s_index_5;
    wire [17:0] s_theta_i;
    wire [17:0] x_o_6;
    wire [17:0] y_o_6;
    wire [17:0] s_theta_c;
    wire [17:0] s_theta_c_9;
    wire [17:0] s_xi_rot;
    wire [17:0] s_xi_rot_6;
    wire [0:0] s_state;
    wire [0:0] s_index_fast;
    wire [0:0] s_index_5_fast;
    wire [0:0] s_index_5_rep1;
    wire [0:0] s_index_5_rep2;
    wire [17:0] un1_s_sum2;
    wire [17:0] un1_s_diff2;
    wire [15:12] un1_s_diff_theta_ns;
    wire [17:1] x_o_3;
    wire [17:17] s_theta_i_RNINO69_FCO;
    wire [17:17] s_theta_i_RNINO69_S;
    wire [17:17] s_theta_i_RNINO69_Y;
    wire [0:0] s_xi_rot_RNI4IUL_Y;
    wire [1:1] s_xi_rot_RNIICM21_Y;
    wire [2:2] s_xi_rot_RNI18EF1_Y;
    wire [3:3] s_xi_rot_RNIH46S1_Y;
    wire [4:4] s_xi_rot_RNI22U82_Y;
    wire [5:5] s_xi_rot_RNIK0ML2_Y;
    wire [6:6] s_xi_rot_RNI70E23_Y;
    wire [7:7] s_xi_rot_RNIR06F3_Y;
    wire [8:8] s_xi_rot_RNIG2UR3_Y;
    wire [9:9] s_xi_rot_RNI65M84_Y;
    wire [10:10] s_xi_rot_RNI4BEM4_Y;
    wire [11:11] s_xi_rot_RNI3I645_Y;
    wire [12:12] s_xi_rot_RNI3QUH5_Y;
    wire [13:13] s_xi_rot_RNI43NV5_Y;
    wire [14:14] s_xi_rot_RNI6DFD6_Y;
    wire [15:15] s_xi_rot_RNI9O7R6_Y;
    wire [17:17] s_xi_rot_RNIIHOM7_FCO;
    wire [17:17] s_xi_rot_RNIIHOM7_Y;
    wire [16:16] s_xi_rot_RNID4097_Y;
    wire [15:12] un1_s_diff_theta_bm;
    wire [15:12] un1_s_diff_theta_am;
    wire MSC_net_355, MSC_net_356, MSC_net_357, MSC_net_358, 
        MSC_net_359, MSC_net_360, MSC_net_361, MSC_net_362, 
        MSC_net_363, MSC_net_364, MSC_net_365, MSC_net_366, 
        MSC_net_367, MSC_net_368, MSC_net_369, MSC_net_370, 
        MSC_net_371, MSC_net_372, MSC_net_373, MSC_net_374, 
        MSC_net_375, MSC_net_376, MSC_net_377, MSC_net_378, 
        MSC_net_379, MSC_net_380, MSC_net_381, MSC_net_382, 
        MSC_net_383, MSC_net_384, MSC_net_385, MSC_net_386, 
        MSC_net_387, MSC_net_388, MSC_net_389, MSC_net_390, 
        MSC_net_391, MSC_net_392, MSC_net_393, MSC_net_394, 
        MSC_net_395, MSC_net_396, MSC_net_397, MSC_net_398, 
        MSC_net_399, MSC_net_400, MSC_net_401, MSC_net_402, 
        MSC_net_403, MSC_net_404, MSC_net_405, MSC_net_406, 
        MSC_net_407, MSC_net_408, MSC_net_409, MSC_net_410, 
        MSC_net_411, MSC_net_412, MSC_net_413, MSC_net_414, 
        MSC_net_415, MSC_net_416, MSC_net_417, MSC_net_418, 
        MSC_net_419, MSC_net_420, MSC_net_421, MSC_net_422, 
        MSC_net_423, MSC_net_424, MSC_net_425, MSC_net_426, 
        MSC_net_427, MSC_net_428, MSC_net_429, MSC_net_430, 
        MSC_net_431, MSC_net_432, MSC_net_433, MSC_net_434, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, MSC_net_442, 
        MSC_net_443, MSC_net_444, MSC_net_445, MSC_net_446, 
        MSC_net_447, MSC_net_448, MSC_net_449, MSC_net_450, 
        MSC_net_451, MSC_net_452, MSC_net_453, MSC_net_454, 
        MSC_net_455, MSC_net_456, MSC_net_457, MSC_net_458, 
        MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, MSC_net_470, 
        MSC_net_471, MSC_net_472, MSC_net_473, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488, MSC_net_489, MSC_net_490, 
        MSC_net_491, MSC_net_492, MSC_net_493, MSC_net_494, 
        MSC_net_495, MSC_net_496, MSC_net_497, MSC_net_498, 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, MSC_net_518, 
        MSC_net_519, MSC_net_520, MSC_net_521, MSC_net_522, 
        MSC_net_523, MSC_net_524, MSC_net_525, MSC_net_526, 
        MSC_net_527, MSC_net_528, MSC_net_529, MSC_net_530, 
        MSC_net_531, MSC_net_532, MSC_net_533, MSC_net_534, 
        MSC_net_535, MSC_net_536, MSC_net_537, MSC_net_538, 
        MSC_net_539, MSC_net_540, MSC_net_541, MSC_net_542, 
        MSC_net_543, MSC_net_544, MSC_net_545, MSC_net_546, 
        MSC_net_547, MSC_net_548, MSC_net_549, MSC_net_550, 
        MSC_net_551, MSC_net_552, MSC_net_553, MSC_net_554, 
        MSC_net_555, MSC_net_556, MSC_net_557, MSC_net_558, 
        MSC_net_559, MSC_net_560, MSC_net_561, MSC_net_562, 
        MSC_net_563, MSC_net_564, MSC_net_565, MSC_net_566, 
        MSC_net_567, MSC_net_568, MSC_net_569, MSC_net_570, 
        MSC_net_571, MSC_net_572, MSC_net_573, MSC_net_574, 
        MSC_net_575, MSC_net_576, MSC_net_577, MSC_net_578, 
        MSC_net_579, MSC_net_580, MSC_net_581, MSC_net_582, 
        MSC_net_583, MSC_net_584, MSC_net_585, MSC_net_586, 
        MSC_net_587, MSC_net_588, MSC_net_589, MSC_net_590, 
        MSC_net_591, MSC_net_592, MSC_net_593, MSC_net_594, 
        MSC_net_595, MSC_net_596, MSC_net_597, MSC_net_598, 
        MSC_net_599, MSC_net_600, MSC_net_601, MSC_net_602, 
        MSC_net_603, MSC_net_604, MSC_net_605, MSC_net_606, 
        MSC_net_607, MSC_net_608, MSC_net_609, MSC_net_610, 
        MSC_net_611, MSC_net_612, MSC_net_613, MSC_net_614, 
        MSC_net_615, MSC_net_616, MSC_net_617, MSC_net_618, 
        MSC_net_619, MSC_net_620, MSC_net_621, MSC_net_622, 
        MSC_net_623, MSC_net_624, MSC_net_625, MSC_net_626, 
        MSC_net_627, MSC_net_628, MSC_net_629, MSC_net_630, 
        MSC_net_631, MSC_net_632, MSC_net_633, MSC_net_634, 
        MSC_net_635, MSC_net_636, MSC_net_637, MSC_net_638, 
        MSC_net_639, MSC_net_640, MSC_net_641, MSC_net_642, 
        MSC_net_643, MSC_net_644, MSC_net_645, MSC_net_646, 
        MSC_net_647, MSC_net_648, MSC_net_649, MSC_net_650, 
        MSC_net_651, MSC_net_652, MSC_net_653, MSC_net_654, 
        MSC_net_655, MSC_net_656, MSC_net_657, MSC_net_658, 
        MSC_net_659, MSC_net_660, MSC_net_661, MSC_net_662, 
        MSC_net_663, MSC_net_664, MSC_net_665, MSC_net_666, 
        MSC_net_667, MSC_net_668, MSC_net_669, MSC_net_670, 
        MSC_net_671, MSC_net_672, MSC_net_673, MSC_net_674, 
        MSC_net_675, MSC_net_676, MSC_net_677, MSC_net_678, 
        MSC_net_679, MSC_net_680, MSC_net_681, MSC_net_682, 
        MSC_net_683, MSC_net_684, MSC_net_685, MSC_net_686, 
        MSC_net_687, MSC_net_688, MSC_net_689, MSC_net_690, 
        MSC_net_691, MSC_net_692, MSC_net_693, MSC_net_694, 
        MSC_net_695, MSC_net_696, MSC_net_697, MSC_net_698, 
        MSC_net_699, MSC_net_700, MSC_net_701, MSC_net_702, 
        MSC_net_703, MSC_net_704, MSC_net_705, MSC_net_706, 
        MSC_net_707, MSC_net_708, MSC_net_709, MSC_net_710, 
        MSC_net_711, MSC_net_712, MSC_net_713, MSC_net_714, 
        MSC_net_715, MSC_net_716, MSC_net_717, MSC_net_718, 
        MSC_net_719, MSC_net_720, MSC_net_721, MSC_net_722, 
        MSC_net_723, MSC_net_724, MSC_net_725, MSC_net_726, 
        MSC_net_727, MSC_net_728, MSC_net_729, MSC_net_730, 
        MSC_net_731, MSC_net_732, MSC_net_733, MSC_net_734, 
        MSC_net_735, MSC_net_736, MSC_net_737, MSC_net_738, 
        MSC_net_739, MSC_net_740, MSC_net_741, MSC_net_742, 
        MSC_net_743, MSC_net_744, MSC_net_745, MSC_net_746, 
        MSC_net_747, MSC_net_748, MSC_net_749, MSC_net_750, 
        MSC_net_751, MSC_net_752, MSC_net_753, MSC_net_754, 
        MSC_net_755, MSC_net_756, MSC_net_757, MSC_net_758, 
        MSC_net_759, MSC_net_760, MSC_net_761, MSC_net_762, 
        MSC_net_763, MSC_net_764, MSC_net_765, MSC_net_766, 
        MSC_net_767, MSC_net_768, MSC_net_769, MSC_net_770, 
        MSC_net_771, MSC_net_772, MSC_net_773, MSC_net_774, 
        MSC_net_775, MSC_net_776, MSC_net_777, MSC_net_778, 
        MSC_net_779, MSC_net_780, MSC_net_781, MSC_net_782, 
        MSC_net_783, MSC_net_784, MSC_net_785, MSC_net_786, 
        MSC_net_787, MSC_net_788, MSC_net_789, MSC_net_790, 
        MSC_net_791, MSC_net_792, MSC_net_793, MSC_net_794, 
        MSC_net_795, MSC_net_796, MSC_net_797, MSC_net_798, 
        MSC_net_799, MSC_net_800, MSC_net_801, MSC_net_802, 
        MSC_net_803, MSC_net_804, MSC_net_805, MSC_net_806, 
        MSC_net_807, MSC_net_808, MSC_net_809, MSC_net_810, 
        MSC_net_811, MSC_net_812, MSC_net_813, MSC_net_814, 
        MSC_net_815, MSC_net_816, MSC_net_817, MSC_net_818, 
        MSC_net_819, MSC_net_820, MSC_net_821, MSC_net_822, 
        MSC_net_823, MSC_net_824;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
UBToHe8BY6gjCHq+1Q3vDCEhpRsTf51J7CEoDOMVJSFDB+kfF62uBoemgnWOXOEn
jMlXFtdTEZLUjuyDSedegGjNb9E72/M17XQKjf7CoJnAYw92X5hgOymy3fQk1jfq
UiS/F9HhrLxpBhe8dCTQpHPduO0o4tnYXbfF+6GdUvU=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=127010)
`pragma protect data_block
[encoded data, 125056 characters]

`pragma protect end_protected

endmodule


module cordic_scale_18s_44s_0_1_2_0(
       s_xo_scale,
       s_product_from_mas,
       s_yo_scale,
       s_mul_a_from_cordic,
       s_mas_sel,
       s_yo,
       s_xo,
       reset_i,
       sys_clk_i,
       s_done_o,
       s_mas_en_from_cordic,
       N_15,
       s_mas_done_from_mas,
       s_cordic_done
    );
output [17:0] s_xo_scale;
input  [26:9] s_product_from_mas;
output [17:0] s_yo_scale;
output [17:0] s_mul_a_from_cordic;
input  [1:1] s_mas_sel;
input  [17:0] s_yo;
input  [17:0] s_xo;
input  reset_i;
input  sys_clk_i;
output s_done_o;
output s_mas_en_from_cordic;
input  N_15;
input  s_mas_done_from_mas;
input  s_cordic_done;

    wire [1:0] s_state;
    wire [0:0] s_state_ns;
    wire MSC_net_119, MSC_net_120, MSC_net_121, MSC_net_122, 
        MSC_net_123, MSC_net_124, MSC_net_125, MSC_net_126, 
        MSC_net_127, MSC_net_128, MSC_net_129, MSC_net_130, 
        MSC_net_131, MSC_net_132, MSC_net_133, MSC_net_134, 
        MSC_net_135, MSC_net_136, MSC_net_137, MSC_net_138, 
        MSC_net_139, MSC_net_140, MSC_net_141, MSC_net_142, 
        MSC_net_143, MSC_net_144, MSC_net_145, MSC_net_146;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
IPS+hdHc+toDeJqBTAC5UaBljh+onwwaN3UUdIcKGdvuJt8aTXPz629G5vj0UsXM
tzrHdRlxqBt43un1KwLmuT5+df7zupG65yPOnF8r1bMz5YbnALiSVpladm//zhvt
VgZ0zkwjQjZWuG6WRRfyvCnXG1hDdor9cztE5Breh0Q=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=22275)
`pragma protect data_block
[encoded data, 21888 characters]
a6BP9qyo1oQMDXAQlCOBU7UJQ1W6vTGEHf4A/wzvOos=

`pragma protect end_protected

endmodule


module cordic_scheduler_foc_18s_15s_44s_0(
       valpha_o,
       vbeta_o,
       id_o,
       iq_o,
       ialpha_i,
       vd_i,
       ibeta_i,
       vq_i,
       theta_i,
       s_product_from_mas,
       s_mul_a_from_cordic,
       s_mas_sel,
       start_park_i,
       reset_i,
       sys_clk_i,
       s_start_cordic,
       ipark_done_o,
       park_done_o,
       start_ipark_i,
       s_mas_en_from_cordic,
       N_15,
       s_mas_done_from_mas
    );
output [17:0] valpha_o;
output [17:0] vbeta_o;
output [17:0] id_o;
output [17:0] iq_o;
input  [17:1] ialpha_i;
input  [17:1] vd_i;
input  [17:1] ibeta_i;
input  [17:1] vq_i;
input  [17:0] theta_i;
input  [26:9] s_product_from_mas;
output [17:0] s_mul_a_from_cordic;
input  [1:1] s_mas_sel;
input  start_park_i;
input  reset_i;
input  sys_clk_i;
output s_start_cordic;
output ipark_done_o;
output park_done_o;
input  start_ipark_i;
output s_mas_en_from_cordic;
input  N_15;
input  s_mas_done_from_mas;

    wire [17:0] s_xo_scale;
    wire [17:0] s_yo_scale;
    wire [16:0] s_xi;
    wire [16:0] s_yi;
    wire [17:0] s_xo;
    wire [17:0] s_yo;
    wire MSC_net_311, MSC_net_312, MSC_net_313, MSC_net_314, 
        MSC_net_315, MSC_net_316, MSC_net_317, MSC_net_318, 
        MSC_net_319, MSC_net_320, MSC_net_321, MSC_net_322, 
        MSC_net_323, MSC_net_324, MSC_net_325, MSC_net_326, 
        MSC_net_327, MSC_net_328, MSC_net_329, MSC_net_330, 
        MSC_net_331, MSC_net_332, MSC_net_333, MSC_net_334, 
        MSC_net_335, MSC_net_336;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
OkFGkN31mFKc9mnRwMDtiMs4IsDXCJkvOBlzo4q8VoLvdMrVNmTM65jmoTC1Klwk
j5FgreJotOHsE8W/DEPButeOCS49ckFCAt7UsRGo1+rVWs175KwoirAK28nsNNIz
ZQ3rwpyXCsfVEhVoXEj4zWje7awGZFINnYZ/S+6/1Vs=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=35860)
`pragma protect data_block
[encoded data, 35264 characters]
5ocpVS4fmoNriR20T2RxBOFUoNhRzvUnJ0zb1KvCINo=

`pragma protect end_protected

endmodule


module mas_scheduler_foc_18s_44s_0(
       s_mas_sel,
       s_mul_b_from_clarke,
       s_mul_b_to_mas,
       s_mul_a_from_cordic,
       s_mul_a_to_mas,
       reset_i,
       sys_clk_i,
       s_start_cordic,
       s_mas_done_from_mas,
       N_15,
       s_mas_en_from_cordic,
       s_mas_en_to_mas,
       N_17_i_0
    );
output [1:1] s_mas_sel;
input  [1:1] s_mul_b_from_clarke;
output [0:0] s_mul_b_to_mas;
input  [17:0] s_mul_a_from_cordic;
output [17:0] s_mul_a_to_mas;
input  reset_i;
input  sys_clk_i;
input  s_start_cordic;
input  s_mas_done_from_mas;
output N_15;
input  s_mas_en_from_cordic;
output s_mas_en_to_mas;
output N_17_i_0;

    wire MSC_net_47, MSC_net_48;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
XldQW+SUoMBN+tpxQagp0ixpQfSWAkfDCfs5ZegB6PH/5yG6i5204Y+vZFVx4FWJ
tdMyMvcb1KZp7RLaOQcWkiGFanL4BIsmqNymj+TGxR2OoMgrasavvn1szg3wSnUE
dXpk/hCCvE2HYVBLMMjZAc8VTn8A/QgncVHvnn4csPI=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=4270)
`pragma protect data_block
[encoded data, 4160 characters]
aYNZ+VZRvfQ66iFbPciP5nA9yjs0u4bSH5yASVcOY/4=

`pragma protect end_protected

endmodule


module mas_foc_44s_18s_2s_0(
       s_product_from_mas,
       s_mul_a_to_mas,
       s_mul_b_to_mas,
       s_mas_sel,
       s_mas_done_from_mas,
       reset_i,
       sys_clk_i,
       s_mas_en_to_mas,
       N_17_i_0
    );
output [26:9] s_product_from_mas;
input  [17:0] s_mul_a_to_mas;
input  [0:0] s_mul_b_to_mas;
input  [1:1] s_mas_sel;
output s_mas_done_from_mas;
input  reset_i;
input  sys_clk_i;
input  s_mas_en_to_mas;
input  N_17_i_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [28:0] product_o;
    wire [43:29] product_o_ONC;
    wire MSC_net_132, MSC_net_133, MSC_net_134, MSC_net_135, 
        MSC_net_136, MSC_net_137, MSC_net_138, MSC_net_139, 
        MSC_net_140, MSC_net_141, MSC_net_142, MSC_net_143, 
        MSC_net_144, MSC_net_145, MSC_net_146, MSC_net_147, 
        MSC_net_148, MSC_net_149, MSC_net_150, MSC_net_151, 
        MSC_net_152, MSC_net_153, MSC_net_154, MSC_net_155, 
        MSC_net_156, MSC_net_157, MSC_net_158, MSC_net_159, 
        MSC_net_160, MSC_net_161, MSC_net_162, MSC_net_163, 
        MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194, MSC_net_195, 
        MSC_net_196, MSC_net_197, MSC_net_198, MSC_net_199, 
        MSC_net_200, MSC_net_201, MSC_net_202, MSC_net_203, 
        MSC_net_204, MSC_net_205, MSC_net_206, MSC_net_207, 
        MSC_net_208;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
ceTImEc055hHWexpA6utfCzFK1tPS4pfHhUYVAxxjrVwlZDlbu/gaw4PzR5Kr8H2
uTlrRWI4sp34Ot0Khd2iRREo1lUZDUglICIIvcs23LkvZ1UhOuUkRRJkjFEK4QQ4
Y+ssAL7wAKN/2jRSa9fU2+uceckeofjPHfRWzdSW98E=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8540)
`pragma protect data_block
[encoded data, 8384 characters]
+hETWZeH8h6b7zePC1Q0RA==

`pragma protect end_protected

endmodule


module clarke_foc_18s_44s_591_0_1_0(
       s_mul_b_from_clarke,
       reset_i,
       sys_clk_i
    );
output [1:1] s_mul_b_from_clarke;
input  reset_i;
input  sys_clk_i;

    wire MSC_net_3, MSC_net_4, MSC_net_5, MSC_net_6, MSC_net_7, 
        MSC_net_8, MSC_net_9, MSC_net_10, MSC_net_11, MSC_net_12, 
        MSC_net_13, MSC_net_14, MSC_net_15, MSC_net_16, MSC_net_17, 
        MSC_net_18, MSC_net_19, MSC_net_20, MSC_net_21, MSC_net_22, 
        MSC_net_23, MSC_net_24, MSC_net_25, MSC_net_26, MSC_net_27, 
        MSC_net_28, MSC_net_29, MSC_net_30, MSC_net_31, MSC_net_32, 
        MSC_net_33, MSC_net_34, MSC_net_35, MSC_net_36, MSC_net_37, 
        MSC_net_38, MSC_net_39, MSC_net_40, MSC_net_41, MSC_net_42, 
        MSC_net_43;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
mA0QNrQhUcnrQ9FpAOy2PS4vBmeDX+XJo1X/gM3C4wZrYsprGS5I4Y4msezCr6cZ
fJzoFYOJgt9ssGu91BLqV+LGKkenRZyp6Kgw3KyDYMKeSQ46Mx7hV3BjMnsVpqCk
/cYaHKnCszkhIXXW8eK+b2wzNR05Andc52dUr/NV/8k=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=435)
`pragma protect data_block
QwpjnlPiG9ksX+JLEJDuT2Z/3ACcmCSg7So8IRZR9u/GIagYEEzZIkxvXEy5Tu5O
x7BKoNgIUT23YTjDv6Vu51S+YS/PPHc1S4F/OA5RcR1Vl/CO5WnOrHDuf5Mq7aKP
6VSuWo98GTDZRBVr5KiYyoQb9sc7YK97BuFRMfmoxXNrIJ18Tg+HFfo73oNt1uys
i0RRMeKoP8DzWEf/SYWSAKv+hcjAdj+tqdfNcN1Eb7SFytPyLf1CX4txErcTBb/1
ez72ZBI9BCvhHDcP8Or3+9NhLhEEcu9c0WfAOVl7U7nW1Mkf8tWs0v4DETG5lA/k
QTcnVKSgbuOGqbvIFYfyJHEep62q/HF1zLZ0B6gbnIf19wcCWc6hcAk5Dsc6Hczg
Fez/T0SbZVJlTcnBxnDkW2oKiBiWQo7mpolnlNPTpLI=

`pragma protect end_protected

endmodule


module FOC_TRANSFORMS_2s_44s_0(
       reset_i,
       sys_clk_i,
       start_clarke_i,
       start_park_i,
       start_ipark_i,
       start_iclarke_i,
       ia_i,
       ib_i,
       ialpha_i,
       ibeta_i,
       vd_i,
       vq_i,
       valpha_i,
       vbeta_i,
       theta_i,
       clarke_done_o,
       park_done_o,
       ipark_done_o,
       iclarke_done_o,
       ialpha_o,
       ibeta_o,
       id_o,
       iq_o,
       valpha_o,
       vbeta_o,
       va_o,
       vb_o,
       vc_o
    );
input  reset_i;
input  sys_clk_i;
input  start_clarke_i;
input  start_park_i;
input  start_ipark_i;
input  start_iclarke_i;
input  [17:0] ia_i;
input  [17:0] ib_i;
input  [17:0] ialpha_i;
input  [17:0] ibeta_i;
input  [17:0] vd_i;
input  [17:0] vq_i;
input  [17:0] valpha_i;
input  [17:0] vbeta_i;
input  [17:0] theta_i;
output clarke_done_o;
output park_done_o;
output ipark_done_o;
output iclarke_done_o;
output [17:0] ialpha_o;
output [17:0] ibeta_o;
output [17:0] id_o;
output [17:0] iq_o;
output [17:0] valpha_o;
output [17:0] vbeta_o;
output [17:0] va_o;
output [17:0] vb_o;
output [17:0] vc_o;

    wire [17:0] ialpha_o_net_1;
    wire [1:1] s_mul_b_from_clarke;
    wire [17:0] s_mul_a_from_cordic;
    wire [17:0] s_mul_a_to_mas;
    wire [26:9] s_product_from_mas;
    wire [1:1] \MAS_SCHEDULER_INST.s_mas_sel ;
    wire [0:0] s_mul_b_to_mas;
    wire MSC_net_300, MSC_net_301, MSC_net_302, MSC_net_303, 
        MSC_net_304, MSC_net_305, MSC_net_306;
    assign clarke_done_o = ialpha_o_net_1[0];
    assign iclarke_done_o = ialpha_o_net_1[0];
    assign ialpha_o[17] = ialpha_o_net_1[0];
    assign ialpha_o[16] = ialpha_o_net_1[0];
    assign ialpha_o[15] = ialpha_o_net_1[0];
    assign ialpha_o[14] = ialpha_o_net_1[0];
    assign ialpha_o[13] = ialpha_o_net_1[0];
    assign ialpha_o[12] = ialpha_o_net_1[0];
    assign ialpha_o[11] = ialpha_o_net_1[0];
    assign ialpha_o[10] = ialpha_o_net_1[0];
    assign ialpha_o[9] = ialpha_o_net_1[0];
    assign ialpha_o[8] = ialpha_o_net_1[0];
    assign ialpha_o[7] = ialpha_o_net_1[0];
    assign ialpha_o[6] = ialpha_o_net_1[0];
    assign ialpha_o[5] = ialpha_o_net_1[0];
    assign ialpha_o[4] = ialpha_o_net_1[0];
    assign ialpha_o[3] = ialpha_o_net_1[0];
    assign ialpha_o[2] = ialpha_o_net_1[0];
    assign ialpha_o[1] = ialpha_o_net_1[0];
    assign ialpha_o[0] = ialpha_o_net_1[0];
    assign ibeta_o[17] = ialpha_o_net_1[0];
    assign ibeta_o[16] = ialpha_o_net_1[0];
    assign ibeta_o[15] = ialpha_o_net_1[0];
    assign ibeta_o[14] = ialpha_o_net_1[0];
    assign ibeta_o[13] = ialpha_o_net_1[0];
    assign ibeta_o[12] = ialpha_o_net_1[0];
    assign ibeta_o[11] = ialpha_o_net_1[0];
    assign ibeta_o[10] = ialpha_o_net_1[0];
    assign ibeta_o[9] = ialpha_o_net_1[0];
    assign ibeta_o[8] = ialpha_o_net_1[0];
    assign ibeta_o[7] = ialpha_o_net_1[0];
    assign ibeta_o[6] = ialpha_o_net_1[0];
    assign ibeta_o[5] = ialpha_o_net_1[0];
    assign ibeta_o[4] = ialpha_o_net_1[0];
    assign ibeta_o[3] = ialpha_o_net_1[0];
    assign ibeta_o[2] = ialpha_o_net_1[0];
    assign ibeta_o[1] = ialpha_o_net_1[0];
    assign ibeta_o[0] = ialpha_o_net_1[0];
    assign va_o[17] = ialpha_o_net_1[0];
    assign va_o[16] = ialpha_o_net_1[0];
    assign va_o[15] = ialpha_o_net_1[0];
    assign va_o[14] = ialpha_o_net_1[0];
    assign va_o[13] = ialpha_o_net_1[0];
    assign va_o[12] = ialpha_o_net_1[0];
    assign va_o[11] = ialpha_o_net_1[0];
    assign va_o[10] = ialpha_o_net_1[0];
    assign va_o[9] = ialpha_o_net_1[0];
    assign va_o[8] = ialpha_o_net_1[0];
    assign va_o[7] = ialpha_o_net_1[0];
    assign va_o[6] = ialpha_o_net_1[0];
    assign va_o[5] = ialpha_o_net_1[0];
    assign va_o[4] = ialpha_o_net_1[0];
    assign va_o[3] = ialpha_o_net_1[0];
    assign va_o[2] = ialpha_o_net_1[0];
    assign va_o[1] = ialpha_o_net_1[0];
    assign va_o[0] = ialpha_o_net_1[0];
    assign vb_o[17] = ialpha_o_net_1[0];
    assign vb_o[16] = ialpha_o_net_1[0];
    assign vb_o[15] = ialpha_o_net_1[0];
    assign vb_o[14] = ialpha_o_net_1[0];
    assign vb_o[13] = ialpha_o_net_1[0];
    assign vb_o[12] = ialpha_o_net_1[0];
    assign vb_o[11] = ialpha_o_net_1[0];
    assign vb_o[10] = ialpha_o_net_1[0];
    assign vb_o[9] = ialpha_o_net_1[0];
    assign vb_o[8] = ialpha_o_net_1[0];
    assign vb_o[7] = ialpha_o_net_1[0];
    assign vb_o[6] = ialpha_o_net_1[0];
    assign vb_o[5] = ialpha_o_net_1[0];
    assign vb_o[4] = ialpha_o_net_1[0];
    assign vb_o[3] = ialpha_o_net_1[0];
    assign vb_o[2] = ialpha_o_net_1[0];
    assign vb_o[1] = ialpha_o_net_1[0];
    assign vb_o[0] = ialpha_o_net_1[0];
    assign vc_o[17] = ialpha_o_net_1[0];
    assign vc_o[16] = ialpha_o_net_1[0];
    assign vc_o[15] = ialpha_o_net_1[0];
    assign vc_o[14] = ialpha_o_net_1[0];
    assign vc_o[13] = ialpha_o_net_1[0];
    assign vc_o[12] = ialpha_o_net_1[0];
    assign vc_o[11] = ialpha_o_net_1[0];
    assign vc_o[10] = ialpha_o_net_1[0];
    assign vc_o[9] = ialpha_o_net_1[0];
    assign vc_o[8] = ialpha_o_net_1[0];
    assign vc_o[7] = ialpha_o_net_1[0];
    assign vc_o[6] = ialpha_o_net_1[0];
    assign vc_o[5] = ialpha_o_net_1[0];
    assign vc_o[4] = ialpha_o_net_1[0];
    assign vc_o[3] = ialpha_o_net_1[0];
    assign vc_o[2] = ialpha_o_net_1[0];
    assign vc_o[1] = ialpha_o_net_1[0];
    assign vc_o[0] = ialpha_o_net_1[0];
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
XS7S0CZRjWa0xJ4Mcz7jb+kvcFsgsK/F7mfLOGd9aaHAgWHBIHYvywKa6ecpcnt9
AaXoA/ujfXA3UHtqrUCQT8BHpQKSECCQqsFA2tXgBt+y0XLxL3wKn1Y1qoLTkeyD
J/TzFTSZnggcGz58zM+L7kUTsOWd0xtdW4hPBuTyzmw=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8995)
`pragma protect data_block
[encoded data, 8832 characters]
EOTsGrpuBT+ZwzCOuTH3rw==

`pragma protect end_protected

endmodule


module SEQ_CONTROLLER_Z1_layer1_0(
       SEQ_CONTROLLER_1_state_o_0,
       apb3_if_st_0_seq_cntl_config_o,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FAB_CCC_GL1,
       SEQ_CONTROLLER_1_adc_start_o_0,
       apb3_if_st_0_start_motor_o,
       apb3_if_st_0_stop_motor_o,
       ADC_SCALING_0_calib_done_o,
       A1_PWM_WL_O_c_i_0,
       ADC_SCALING_0_over_current_fault_o,
       A1_PWM_WL_O_c,
       N_614_i_0,
       PWM_SCALING_0_done_o,
       PWM3PH_0_midmatch_o
    );
output [3:0] SEQ_CONTROLLER_1_state_o_0;
input  [2:1] apb3_if_st_0_seq_cntl_config_o;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FAB_CCC_GL1;
output SEQ_CONTROLLER_1_adc_start_o_0;
input  apb3_if_st_0_start_motor_o;
input  apb3_if_st_0_stop_motor_o;
input  ADC_SCALING_0_calib_done_o;
output A1_PWM_WL_O_c_i_0;
input  ADC_SCALING_0_over_current_fault_o;
output A1_PWM_WL_O_c;
output N_614_i_0;
input  PWM_SCALING_0_done_o;
input  PWM3PH_0_midmatch_o;

    wire [8:1] s_state;
    wire [12:0] s_adctrig_count;
    wire [12:0] s_adctrig_count_s;
    wire [13:0] s_sensor_calib_count;
    wire [13:0] s_sensor_calib_count_s;
    wire [1:1] s_state_RNIHSUR_S;
    wire [1:1] s_state_RNIHSUR_Y;
    wire [11:0] s_adctrig_count_cry;
    wire [0:0] s_adctrig_count_RNIVH572_Y;
    wire [1:1] s_adctrig_count_RNIE8CI3_Y;
    wire [2:2] s_adctrig_count_RNIUVIT4_Y;
    wire [3:3] s_adctrig_count_RNIFOP86_Y;
    wire [4:4] s_adctrig_count_RNI1I0K7_Y;
    wire [5:5] s_adctrig_count_RNIKC7V8_Y;
    wire [6:6] s_adctrig_count_RNI88EAA_Y;
    wire [7:7] s_adctrig_count_RNIT4LLB_Y;
    wire [8:8] s_adctrig_count_RNIJ2S0D_Y;
    wire [9:9] s_adctrig_count_RNIA13CE_Y;
    wire [10:10] s_adctrig_count_RNI9A2FF_Y;
    wire [12:12] s_adctrig_count_RNO_FCO;
    wire [12:12] s_adctrig_count_RNO_Y;
    wire [11:11] s_adctrig_count_RNI9K1IG_Y;
    wire [13:13] s_sensor_calib_count_RNI1QSJ_S;
    wire [13:13] s_sensor_calib_count_RNI1QSJ_Y;
    wire [12:0] s_sensor_calib_count_cry;
    wire [0:0] s_sensor_calib_count_RNIKU601_Y;
    wire [1:1] s_sensor_calib_count_RNI84HC1_Y;
    wire [2:2] s_sensor_calib_count_RNITARO1_Y;
    wire [3:3] s_sensor_calib_count_RNIJI552_Y;
    wire [4:4] s_sensor_calib_count_RNIARFH2_Y;
    wire [5:5] s_sensor_calib_count_RNI25QT2_Y;
    wire [6:6] s_sensor_calib_count_RNIRF4A3_Y;
    wire [7:7] s_sensor_calib_count_RNILREM3_Y;
    wire [8:8] s_sensor_calib_count_RNIG8P24_Y;
    wire [9:9] s_sensor_calib_count_RNICM3F4_Y;
    wire [10:10] s_sensor_calib_count_RNIG4IL4_Y;
    wire [11:11] s_sensor_calib_count_RNILJ0S4_Y;
    wire [13:13] s_sensor_calib_count_RNO_FCO;
    wire [13:13] s_sensor_calib_count_RNO_Y;
    wire [12:12] s_sensor_calib_count_RNIR3F25_Y;
    wire [2:2] s_state_ns_i_i_a2_i_a2_0_4_7;
    wire [2:2] s_state_ns_i_i_a2_i_a2_0_4_1;
    wire [2:2] s_state_ns_i_i_a2_i_a2_0_4_8;
    wire [1:1] s_state_ns_i_0_2;
    wire [1:1] s_state_ns_i_0_0;
    wire VCC, N_613_i_0, GND, N_611_i_0, N_612_i_0, N_1181_i_0, 
        N_974_i_0, N_58, N_325_i_0, N_1182_i_0, N_72, N_73, 
        adc_start_o_4, s_start_motor_dly_Z, s_fault_clear_sync_Z, 
        N_475_li, s_adctrig_counte, adc_start_o5, 
        s_adctrig_count_cry_cy, s_sensor_calib_count_cry_cy, N_51_4, 
        adc_start_o5_8, adc_start_o5_7, adc_start_o5_1, N_30, N_39, 
        N_53, N_73_2, N_50, N_1187, N_51, un1_s_sensor_calib_count_inv, 
        N_52, N_995, N_975, N_237, N_236, N_235, N_234, N_233, N_232, 
        N_231, N_230, N_229, N_228, N_1;
    
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNITARO1[2]  (.A(
        VCC), .B(s_sensor_calib_count[2]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[1]), .S(s_sensor_calib_count_s[2]), 
        .Y(s_sensor_calib_count_RNITARO1_Y[2]), .FCO(
        s_sensor_calib_count_cry[2]));
    SLE \s_adctrig_count[10]  (.D(s_adctrig_count_s[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[10]));
    CFG3 #( .INIT(8'h08) )  \s_state_ns_i_i_a2_i_a2_0[2]  (.A(
        s_state[2]), .B(N_51_4), .C(s_sensor_calib_count[0]), .Y(N_51));
    CFG3 #( .INIT(8'h31) )  \s_state_ns_i_i_a2_i_a2[2]  (.A(
        apb3_if_st_0_seq_cntl_config_o[1]), .B(s_state[2]), .C(
        s_state_RNIHSUR_Y[1]), .Y(N_50));
    CFG4 #( .INIT(16'hFF08) )  \s_state_ns_i_0_2[1]  (.A(
        ADC_SCALING_0_calib_done_o), .B(s_state[1]), .C(N_53), .D(
        s_state_ns_i_0_0[1]), .Y(s_state_ns_i_0_2[1]));
    SLE \s_state[1]  (.D(N_325_i_0), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_state[1]));
    CFG4 #( .INIT(16'h0001) )  \s_state_ns_i_i_a2_i_a2_0_4_8[2]  (.A(
        s_sensor_calib_count[12]), .B(s_sensor_calib_count[11]), .C(
        s_sensor_calib_count[6]), .D(s_sensor_calib_count[5]), .Y(
        s_state_ns_i_i_a2_i_a2_0_4_8[2]));
    CFG4 #( .INIT(16'h4C5F) )  \s_state_ns_o2_0_a2[6]  (.A(
        apb3_if_st_0_stop_motor_o), .B(PWM_SCALING_0_done_o), .C(N_30), 
        .D(s_state[6]), .Y(N_1187));
    CFG4 #( .INIT(16'h8000) )  \s_state_ns_i_i_a2_i_a2_0_4[2]  (.A(
        s_state_ns_i_i_a2_i_a2_0_4_7[2]), .B(
        s_state_ns_i_i_a2_i_a2_0_4_1[2]), .C(s_sensor_calib_count[13]), 
        .D(s_state_ns_i_i_a2_i_a2_0_4_8[2]), .Y(N_51_4));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIJ2S0D[8]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[8]), .D(GND), 
        .FCI(s_adctrig_count_cry[7]), .S(s_adctrig_count_s[8]), .Y(
        s_adctrig_count_RNIJ2S0D_Y[8]), .FCO(s_adctrig_count_cry[8]));
    SLE \s_sensor_calib_count[1]  (.D(s_sensor_calib_count_s[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[1]));
    SLE \s_sensor_calib_count[5]  (.D(s_sensor_calib_count_s[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[5]));
    CFG4 #( .INIT(16'h7FFF) )  \ADC_START_PROC.adc_start_o5_1  (.A(
        s_adctrig_count[12]), .B(s_adctrig_count[10]), .C(
        s_adctrig_count[9]), .D(s_adctrig_count[8]), .Y(adc_start_o5_1)
        );
    CFG3 #( .INIT(8'h2E) )  \s_state_ns_1_i_m2[8]  (.A(
        ADC_SCALING_0_over_current_fault_o), .B(s_state[8]), .C(
        N_475_li), .Y(N_58));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNI25QT2[5]  (.A(
        VCC), .B(s_sensor_calib_count[5]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[4]), .S(s_sensor_calib_count_s[5]), 
        .Y(s_sensor_calib_count_RNI25QT2_Y[5]), .FCO(
        s_sensor_calib_count_cry[5]));
    SLE \s_sensor_calib_count[7]  (.D(s_sensor_calib_count_s[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[7]));
    SLE \s_adctrig_count[3]  (.D(s_adctrig_count_s[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[3]));
    SLE \state_o[2]  (.D(N_612_i_0), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_state_o_0[2]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIARFH2[4]  (.A(
        VCC), .B(s_sensor_calib_count[4]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[3]), .S(s_sensor_calib_count_s[4]), 
        .Y(s_sensor_calib_count_RNIARFH2_Y[4]), .FCO(
        s_sensor_calib_count_cry[4]));
    ARI1 #( .INIT(20'h42A00) )  \s_adctrig_count_RNIVH572[0]  (.A(VCC), 
        .B(s_adctrig_count[0]), .C(s_state[1]), .D(
        ADC_SCALING_0_calib_done_o), .FCI(s_adctrig_count_cry_cy), .S(
        s_adctrig_count_s[0]), .Y(s_adctrig_count_RNIVH572_Y[0]), .FCO(
        s_adctrig_count_cry[0]));
    SLE \s_adctrig_count[9]  (.D(s_adctrig_count_s[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[9]));
    CFG3 #( .INIT(8'hFE) )  \state_o_RNO[1]  (.A(s_state[6]), .B(
        s_state[2]), .C(s_state[3]), .Y(N_611_i_0));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNO[12]  (.A(VCC), .B(
        s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[12]), .D(GND), .FCI(
        s_adctrig_count_cry[11]), .S(s_adctrig_count_s[12]), .Y(
        s_adctrig_count_RNO_Y[12]), .FCO(s_adctrig_count_RNO_FCO[12]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNI1I0K7[4]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[4]), .D(GND), 
        .FCI(s_adctrig_count_cry[3]), .S(s_adctrig_count_s[4]), .Y(
        s_adctrig_count_RNI1I0K7_Y[4]), .FCO(s_adctrig_count_cry[4]));
    SLE \s_adctrig_count[2]  (.D(s_adctrig_count_s[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[2]));
    CFG4 #( .INIT(16'hF0FD) )  \s_state_ns_i_0_0[1]  (.A(
        apb3_if_st_0_start_motor_o), .B(s_start_motor_dly_Z), .C(N_30), 
        .D(s_state[1]), .Y(s_state_ns_i_0_0[1]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIRF4A3[6]  (.A(
        VCC), .B(s_sensor_calib_count[6]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[5]), .S(s_sensor_calib_count_s[6]), 
        .Y(s_sensor_calib_count_RNIRF4A3_Y[6]), .FCO(
        s_sensor_calib_count_cry[6]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIA13CE[9]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[9]), .D(GND), 
        .FCI(s_adctrig_count_cry[8]), .S(s_adctrig_count_s[9]), .Y(
        s_adctrig_count_RNIA13CE_Y[9]), .FCO(s_adctrig_count_cry[9]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNI88EAA[6]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[6]), .D(GND), 
        .FCI(s_adctrig_count_cry[5]), .S(s_adctrig_count_s[6]), .Y(
        s_adctrig_count_RNI88EAA_Y[6]), .FCO(s_adctrig_count_cry[6]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIE8CI3[1]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[1]), .D(GND), 
        .FCI(s_adctrig_count_cry[0]), .S(s_adctrig_count_s[1]), .Y(
        s_adctrig_count_RNIE8CI3_Y[1]), .FCO(s_adctrig_count_cry[1]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIR3F25[12]  (
        .A(VCC), .B(s_sensor_calib_count[12]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[11]), .S(s_sensor_calib_count_s[12]), 
        .Y(s_sensor_calib_count_RNIR3F25_Y[12]), .FCO(
        s_sensor_calib_count_cry[12]));
    SLE \s_sensor_calib_count[10]  (.D(s_sensor_calib_count_s[10]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[10]));
    SLE s_start_motor_dly (.D(apb3_if_st_0_start_motor_o), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_start_motor_dly_Z));
    SLE \s_sensor_calib_count[11]  (.D(s_sensor_calib_count_s[11]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[11]));
    SLE \s_state[4]  (.D(N_73), .CLK(MC_System_0_FAB_CCC_GL1), .EN(VCC)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(s_state[4]));
    CFG3 #( .INIT(8'h01) )  \s_state_ns_i_0_o2_RNI8BCT_0[1]  (.A(
        s_state[6]), .B(s_state[2]), .C(N_30), .Y(A1_PWM_WL_O_c_i_0));
    SLE \s_adctrig_count[5]  (.D(s_adctrig_count_s[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[5]));
    SLE \state_o[0]  (.D(N_613_i_0), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_state_o_0[0]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIKC7V8[5]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[5]), .D(GND), 
        .FCI(s_adctrig_count_cry[4]), .S(s_adctrig_count_s[5]), .Y(
        s_adctrig_count_RNIKC7V8_Y[5]), .FCO(s_adctrig_count_cry[5]));
    CFG3 #( .INIT(8'h40) )  \s_state_ns_i_1_i_a2[3]  (.A(
        apb3_if_st_0_seq_cntl_config_o[2]), .B(N_73_2), .C(N_52), .Y(
        N_72));
    CFG4 #( .INIT(16'h0080) )  \ADC_START_PROC.adc_start_o5  (.A(
        s_adctrig_count[11]), .B(adc_start_o5_8), .C(adc_start_o5_7), 
        .D(adc_start_o5_1), .Y(adc_start_o5));
    CFG2 #( .INIT(4'h4) )  \s_state_RNO[5]  (.A(N_39), .B(N_30), .Y(
        N_1181_i_0));
    SLE \s_sensor_calib_count[13]  (.D(s_sensor_calib_count_s[13]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[13]));
    CFG2 #( .INIT(4'h2) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_s_sensor_calib_count_inv_0_a2  (
        .A(N_51_4), .B(s_sensor_calib_count[0]), .Y(
        un1_s_sensor_calib_count_inv));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNICM3F4[9]  (.A(
        VCC), .B(s_sensor_calib_count[9]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[8]), .S(s_sensor_calib_count_s[9]), 
        .Y(s_sensor_calib_count_RNICM3F4_Y[9]), .FCO(
        s_sensor_calib_count_cry[9]));
    SLE \s_sensor_calib_count[8]  (.D(s_sensor_calib_count_s[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[8]));
    CFG3 #( .INIT(8'hFE) )  \state_o_RNO[2]  (.A(s_state[4]), .B(
        s_state[5]), .C(s_state[6]), .Y(N_612_i_0));
    CFG4 #( .INIT(16'hECA0) )  \ADC_START_PROC.adc_start_o_4_iv_0  (.A(
        s_state[1]), .B(PWM3PH_0_midmatch_o), .C(adc_start_o5), .D(
        A1_PWM_WL_O_c), .Y(adc_start_o_4));
    SLE \state_o[1]  (.D(N_611_i_0), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_state_o_0[1]));
    SLE \s_state[5]  (.D(N_1181_i_0), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_state[5]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIKU601[0]  (.A(
        VCC), .B(s_sensor_calib_count[0]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry_cy), .S(s_sensor_calib_count_s[0]), 
        .Y(s_sensor_calib_count_RNIKU601_Y[0]), .FCO(
        s_sensor_calib_count_cry[0]));
    SLE \s_state[6]  (.D(N_974_i_0), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_state[6]));
    CFG3 #( .INIT(8'h80) )  \s_state_ns_i_1_i_a2[4]  (.A(
        apb3_if_st_0_seq_cntl_config_o[2]), .B(N_73_2), .C(N_52), .Y(
        N_73));
    SLE adc_start_o (.D(adc_start_o_4), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_adc_start_o_0));
    CFG4 #( .INIT(16'h0001) )  \s_state_ns_i_i_a2_i_a2_0_4_7[2]  (.A(
        s_sensor_calib_count[4]), .B(s_sensor_calib_count[3]), .C(
        s_sensor_calib_count[2]), .D(s_sensor_calib_count[1]), .Y(
        s_state_ns_i_i_a2_i_a2_0_4_7[2]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNILJ0S4[11]  (
        .A(VCC), .B(s_sensor_calib_count[11]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[10]), .S(s_sensor_calib_count_s[11]), 
        .Y(s_sensor_calib_count_RNILJ0S4_Y[11]), .FCO(
        s_sensor_calib_count_cry[11]));
    SLE \s_sensor_calib_count[4]  (.D(s_sensor_calib_count_s[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[4]));
    SLE \s_state[8]  (.D(N_58), .CLK(MC_System_0_FAB_CCC_GL1), .EN(VCC)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(s_state[8]));
    SLE \s_adctrig_count[8]  (.D(s_adctrig_count_s[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[8]));
    SLE \s_sensor_calib_count[2]  (.D(s_sensor_calib_count_s[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[2]));
    CFG4 #( .INIT(16'h0001) )  \s_state_RNO[2]  (.A(N_30), .B(N_39), 
        .C(N_50), .D(N_51), .Y(N_1182_i_0));
    CFG3 #( .INIT(8'hFE) )  \s_state_ns_i_i_a2_i_o2[5]  (.A(s_state[8])
        , .B(s_state[6]), .C(N_53), .Y(N_39));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNI9A2FF[10]  (.A(VCC)
        , .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[10]), .D(GND), 
        .FCI(s_adctrig_count_cry[9]), .S(s_adctrig_count_s[10]), .Y(
        s_adctrig_count_RNI9A2FF_Y[10]), .FCO(s_adctrig_count_cry[10]));
    SLE \s_sensor_calib_count[3]  (.D(s_sensor_calib_count_s[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[3]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIUVIT4[2]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[2]), .D(GND), 
        .FCI(s_adctrig_count_cry[1]), .S(s_adctrig_count_s[2]), .Y(
        s_adctrig_count_RNIUVIT4_Y[2]), .FCO(s_adctrig_count_cry[2]));
    SLE \s_adctrig_count[0]  (.D(s_adctrig_count_s[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[0]));
    CFG3 #( .INIT(8'h01) )  \s_state_RNO[6]  (.A(N_1187), .B(
        ADC_SCALING_0_over_current_fault_o), .C(s_state[8]), .Y(
        N_974_i_0));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNI9K1IG[11]  (.A(VCC)
        , .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[11]), .D(GND), 
        .FCI(s_adctrig_count_cry[10]), .S(s_adctrig_count_s[11]), .Y(
        s_adctrig_count_RNI9K1IG_Y[11]), .FCO(s_adctrig_count_cry[11]));
    SLE s_fault_clear_sync (.D(apb3_if_st_0_stop_motor_o), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_fault_clear_sync_Z));
    SLE \s_sensor_calib_count[0]  (.D(s_sensor_calib_count_s[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[0]));
    ARI1 #( .INIT(20'h47700) )  \s_state_RNIHSUR[1]  (.A(VCC), .B(
        ADC_SCALING_0_calib_done_o), .C(s_state[1]), .D(GND), .FCI(VCC)
        , .S(s_state_RNIHSUR_S[1]), .Y(s_state_RNIHSUR_Y[1]), .FCO(
        s_adctrig_count_cry_cy));
    SLE \s_adctrig_count[1]  (.D(s_adctrig_count_s[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[1]));
    CFG2 #( .INIT(4'hE) )  \s_state_ns_i_o2_4_0_o2_1_o2[5]  (.A(
        apb3_if_st_0_stop_motor_o), .B(
        ADC_SCALING_0_over_current_fault_o), .Y(N_53));
    CFG3 #( .INIT(8'h01) )  \s_state_ns_i_1_i_a2_2[3]  (.A(s_state[6]), 
        .B(N_53), .C(N_30), .Y(N_73_2));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNILREM3[7]  (.A(
        VCC), .B(s_sensor_calib_count[7]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[6]), .S(s_sensor_calib_count_s[7]), 
        .Y(s_sensor_calib_count_RNILREM3_Y[7]), .FCO(
        s_sensor_calib_count_cry[7]));
    SLE \s_sensor_calib_count[9]  (.D(s_sensor_calib_count_s[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[9]));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIFOP86[3]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[3]), .D(GND), 
        .FCI(s_adctrig_count_cry[2]), .S(s_adctrig_count_s[3]), .Y(
        s_adctrig_count_RNIFOP86_Y[3]), .FCO(s_adctrig_count_cry[3]));
    CFG3 #( .INIT(8'hFE) )  \s_state_ns_i_0_o2_RNI8BCT[1]  (.A(
        s_state[6]), .B(s_state[2]), .C(N_30), .Y(A1_PWM_WL_O_c));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIJI552[3]  (.A(
        VCC), .B(s_sensor_calib_count[3]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[2]), .S(s_sensor_calib_count_s[3]), 
        .Y(s_sensor_calib_count_RNIJI552_Y[3]), .FCO(
        s_sensor_calib_count_cry[3]));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIG8P24[8]  (.A(
        VCC), .B(s_sensor_calib_count[8]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[7]), .S(s_sensor_calib_count_s[8]), 
        .Y(s_sensor_calib_count_RNIG8P24_Y[8]), .FCO(
        s_sensor_calib_count_cry[8]));
    GND GND_Z (.Y(GND));
    VCC VCC_Z (.Y(VCC));
    CFG3 #( .INIT(8'h01) )  \s_state_RNO[1]  (.A(N_39), .B(
        s_state_ns_i_0_2[1]), .C(s_state[2]), .Y(N_325_i_0));
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNO[13]  (.A(VCC)
        , .B(s_sensor_calib_count[13]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[12]), .S(s_sensor_calib_count_s[13]), 
        .Y(s_sensor_calib_count_RNO_Y[13]), .FCO(
        s_sensor_calib_count_RNO_FCO[13]));
    SLE \s_sensor_calib_count[6]  (.D(s_sensor_calib_count_s[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[6]));
    CFG4 #( .INIT(16'h0001) )  \s_state_ns_i_i_a2_i_a2_0_4_1[2]  (.A(
        s_sensor_calib_count[10]), .B(s_sensor_calib_count[9]), .C(
        s_sensor_calib_count[8]), .D(s_sensor_calib_count[7]), .Y(
        s_state_ns_i_i_a2_i_a2_0_4_1[2]));
    SLE \s_adctrig_count[12]  (.D(s_adctrig_count_s[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[12]));
    CFG4 #( .INIT(16'hFFFE) )  \state_o_RNO[0]  (.A(s_state[1]), .B(
        s_state[6]), .C(s_state[3]), .D(s_state[5]), .Y(N_613_i_0));
    CFG4 #( .INIT(16'h8000) )  \ADC_START_PROC.adc_start_o5_8  (.A(
        s_adctrig_count[7]), .B(s_adctrig_count[6]), .C(
        s_adctrig_count[5]), .D(s_adctrig_count[4]), .Y(adc_start_o5_8)
        );
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNI84HC1[1]  (.A(
        VCC), .B(s_sensor_calib_count[1]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[0]), .S(s_sensor_calib_count_s[1]), 
        .Y(s_sensor_calib_count_RNI84HC1_Y[1]), .FCO(
        s_sensor_calib_count_cry[1]));
    SLE \s_adctrig_count[7]  (.D(s_adctrig_count_s[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[7]));
    SLE \s_adctrig_count[6]  (.D(s_adctrig_count_s[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[6]));
    CFG3 #( .INIT(8'hFE) )  \s_state_ns_i_0_o2[1]  (.A(s_state[3]), .B(
        s_state[5]), .C(s_state[4]), .Y(N_30));
    SLE \s_adctrig_count[4]  (.D(s_adctrig_count_s[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[4]));
    CFG4 #( .INIT(16'hFFFE) )  \s_state_RNIHCPL1[4]  (.A(s_state[6]), 
        .B(s_state[2]), .C(s_state[4]), .D(s_state[5]), .Y(N_614_i_0));
    ARI1 #( .INIT(20'h44400) )  \s_sensor_calib_count_RNI1QSJ[13]  (.A(
        VCC), .B(s_sensor_calib_count[13]), .C(s_state[2]), .D(GND), 
        .FCI(VCC), .S(s_sensor_calib_count_RNI1QSJ_S[13]), .Y(
        s_sensor_calib_count_RNI1QSJ_Y[13]), .FCO(
        s_sensor_calib_count_cry_cy));
    SLE \state_o[3]  (.D(s_state[8]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(SEQ_CONTROLLER_1_state_o_0[3]));
    CFG4 #( .INIT(16'hFF01) )  \s_state_ns_i_1_i_o2[3]  (.A(
        apb3_if_st_0_seq_cntl_config_o[1]), .B(s_state[2]), .C(
        s_state_RNIHSUR_Y[1]), .D(N_51), .Y(N_52));
    SLE \s_state[3]  (.D(N_72), .CLK(MC_System_0_FAB_CCC_GL1), .EN(VCC)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(s_state[3]));
    CFG4 #( .INIT(16'h8000) )  \ADC_START_PROC.adc_start_o5_7  (.A(
        s_adctrig_count[3]), .B(s_adctrig_count[2]), .C(
        s_adctrig_count[1]), .D(s_adctrig_count[0]), .Y(adc_start_o5_7)
        );
    ARI1 #( .INIT(20'h4AA00) )  \s_sensor_calib_count_RNIG4IL4[10]  (
        .A(VCC), .B(s_sensor_calib_count[10]), .C(GND), .D(GND), .FCI(
        s_sensor_calib_count_cry[9]), .S(s_sensor_calib_count_s[10]), 
        .Y(s_sensor_calib_count_RNIG4IL4_Y[10]), .FCO(
        s_sensor_calib_count_cry[10]));
    SLE s_fault_clear_sync1 (.D(s_fault_clear_sync_Z), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(N_475_li));
    CFG4 #( .INIT(16'h0A0E) )  
        \FSM_SEQ_CONTROLLER_PROC.un1_s_sensor_calib_count_inv_0_a2_RNI72I41  
        (.A(s_state[1]), .B(s_state[2]), .C(N_53), .D(
        un1_s_sensor_calib_count_inv), .Y(s_adctrig_counte));
    ARI1 #( .INIT(20'h48800) )  \s_adctrig_count_RNIT4LLB[7]  (.A(VCC), 
        .B(s_state_RNIHSUR_Y[1]), .C(s_adctrig_count[7]), .D(GND), 
        .FCI(s_adctrig_count_cry[6]), .S(s_adctrig_count_s[7]), .Y(
        s_adctrig_count_RNIT4LLB_Y[7]), .FCO(s_adctrig_count_cry[7]));
    SLE \s_state[2]  (.D(N_1182_i_0), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_state[2]));
    SLE \s_adctrig_count[11]  (.D(s_adctrig_count_s[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_adctrig_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_adctrig_count[11]));
    SLE \s_sensor_calib_count[12]  (.D(s_sensor_calib_count_s[12]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_start_o5), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_sensor_calib_count[12]));
    
endmodule


module mas_adc_scl_44s_18s_2s_0(
       s_product,
       adc_scale_val_i,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       un1_s_mul1_1_axb_0_i_0,
       un1_s_mul1_1_cry_1_S,
       un1_s_mul1_1_cry_2_S,
       un1_s_mul1_1_cry_3_S,
       un1_s_mul1_1_cry_4_S,
       un1_s_mul1_1_cry_5_S,
       un1_s_mul1_1_cry_6_S,
       un1_s_mul1_1_cry_7_S,
       un1_s_mul1_1_cry_8_S,
       un1_s_mul1_1_cry_9_S,
       un1_s_mul1_1_cry_10_S,
       un1_s_mul1_1_cry_11_S,
       un1_s_mul1_1_cry_12_S,
       un1_s_mul1_1_cry_13_S,
       un1_s_mul1_1_cry_14_S,
       un1_s_mul1_1_cry_15_S,
       un1_s_mul1_1_cry_16_S,
       un1_s_mul1_1_s_17_S,
       un1_s_ia_0_sqmuxa_0
    );
output [25:8] s_product;
input  [17:0] adc_scale_val_i;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
input  un1_s_mul1_1_axb_0_i_0;
input  un1_s_mul1_1_cry_1_S;
input  un1_s_mul1_1_cry_2_S;
input  un1_s_mul1_1_cry_3_S;
input  un1_s_mul1_1_cry_4_S;
input  un1_s_mul1_1_cry_5_S;
input  un1_s_mul1_1_cry_6_S;
input  un1_s_mul1_1_cry_7_S;
input  un1_s_mul1_1_cry_8_S;
input  un1_s_mul1_1_cry_9_S;
input  un1_s_mul1_1_cry_10_S;
input  un1_s_mul1_1_cry_11_S;
input  un1_s_mul1_1_cry_12_S;
input  un1_s_mul1_1_cry_13_S;
input  un1_s_mul1_1_cry_14_S;
input  un1_s_mul1_1_cry_15_S;
input  un1_s_mul1_1_cry_16_S;
input  un1_s_mul1_1_s_17_S;
input  un1_s_ia_0_sqmuxa_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [35:0] product_o;
    wire [43:36] product_o_ONC;
    wire MSC_net_148, MSC_net_149, MSC_net_150, MSC_net_151, 
        MSC_net_152, MSC_net_153, MSC_net_154, MSC_net_155, 
        MSC_net_156, MSC_net_157, MSC_net_158, MSC_net_159, 
        MSC_net_160, MSC_net_161, MSC_net_162, MSC_net_163, 
        MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
mCnGzYAC23jCmuaN6i9qKZY+V2+eWi1N6SotmHP6UebgwHwo2HMGNxNQ8x6djaWj
7lCwCXF8ejs4f1cYs0MQ54eh490nPOwGC9hDgrHLGosWlH98fyePuTZml2RUd4j1
X5ITzXdW3j6Z0OQOPNbYrRevW//f8PEitb89GV20mI4=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8540)
`pragma protect data_block
[encoded data, 8384 characters]
oQqxTGYVDqcOhw8OM4DgnA==

`pragma protect end_protected

endmodule


module ADC_SCALING_0s_12s_2s_8192_5_44s_0_2_3_0(
       reset_i,
       sys_clk_i,
       adc_results_rdy_i,
       adc_scale_val_i,
       adc_result_ch0_i,
       adc_result_ch1_i,
       fault_threshold_i,
       done_o,
       calib_done_o,
       over_current_fault_o,
       ia_adc_o,
       ib_adc_o
    );
input  reset_i;
input  sys_clk_i;
input  adc_results_rdy_i;
input  [17:0] adc_scale_val_i;
input  [11:0] adc_result_ch0_i;
input  [11:0] adc_result_ch1_i;
input  [17:0] fault_threshold_i;
output done_o;
output calib_done_o;
output over_current_fault_o;
output [17:0] ia_adc_o;
output [17:0] ib_adc_o;

    wire [11:1] un1_s_mul1_1_m;
    wire [25:8] s_product;
    wire [30:0] s_adc_ch0_offset;
    wire [30:0] s_adc_ch1_offset;
    wire [1:0] s_state;
    wire [1:0] s_state_ns;
    wire [17:0] inf_abs1;
    wire [17:0] inf_abs0;
    wire [13:0] s_calib_cnt;
    wire [12:0] s_calib_cnt_cry;
    wire [13:0] s_calib_cnt_s;
    wire [11:1] un1_s_mul1_0;
    wire [12:0] s_calib_cnt_cry_Y;
    wire [13:13] s_calib_cnt_s_FCO;
    wire [13:13] s_calib_cnt_s_Y;
    wire [0:0] s_calib_cnt_cry_cy_S;
    wire [0:0] s_calib_cnt_cry_cy_Y;
    wire MSC_net_302, MSC_net_303, MSC_net_304, MSC_net_305, 
        MSC_net_306, MSC_net_307, MSC_net_308, MSC_net_309, 
        MSC_net_310, MSC_net_311, MSC_net_312, MSC_net_313, 
        MSC_net_314, MSC_net_315, MSC_net_316, MSC_net_317, 
        MSC_net_318, MSC_net_319, MSC_net_320, MSC_net_321, 
        MSC_net_322, MSC_net_323, MSC_net_324, MSC_net_325, 
        MSC_net_326, MSC_net_327, MSC_net_328, MSC_net_329, 
        MSC_net_330, MSC_net_331, MSC_net_332, MSC_net_333, 
        MSC_net_334, MSC_net_335, MSC_net_336, MSC_net_337, 
        MSC_net_338, MSC_net_339, MSC_net_340, MSC_net_341, 
        MSC_net_342, MSC_net_343, MSC_net_344, MSC_net_345, 
        MSC_net_346, MSC_net_347, MSC_net_348, MSC_net_349, 
        MSC_net_350, MSC_net_351, MSC_net_352, MSC_net_353, 
        MSC_net_354, MSC_net_355, MSC_net_356, MSC_net_357, 
        MSC_net_358, MSC_net_359, MSC_net_360, MSC_net_361, 
        MSC_net_362, MSC_net_363, MSC_net_364, MSC_net_365, 
        MSC_net_366, MSC_net_367, MSC_net_368, MSC_net_369, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1 , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5 , 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Z , 
        MSC_net_414, MSC_net_415, MSC_net_416, MSC_net_417, 
        MSC_net_418, MSC_net_419, MSC_net_420, MSC_net_421, 
        MSC_net_422, MSC_net_423, MSC_net_424, MSC_net_425, 
        MSC_net_426, MSC_net_427, MSC_net_428, MSC_net_429, 
        MSC_net_430, MSC_net_431, MSC_net_432, MSC_net_433, 
        MSC_net_434, MSC_net_435, MSC_net_436, MSC_net_437, 
        MSC_net_438, MSC_net_439, MSC_net_440, MSC_net_441, 
        MSC_net_442, MSC_net_443, MSC_net_444, MSC_net_445, 
        MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, MSC_net_457, 
        MSC_net_458, MSC_net_459, MSC_net_460, MSC_net_461, 
        MSC_net_462, MSC_net_463, MSC_net_464, MSC_net_465, 
        MSC_net_466, MSC_net_467, MSC_net_468, MSC_net_469, 
        MSC_net_470, MSC_net_471, MSC_net_472, MSC_net_473, 
        MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, MSC_net_489, 
        MSC_net_490, MSC_net_491, MSC_net_492, MSC_net_493, 
        MSC_net_494, MSC_net_495, MSC_net_496, MSC_net_497, 
        MSC_net_498, MSC_net_499, MSC_net_500, MSC_net_501, 
        MSC_net_502, MSC_net_503, MSC_net_504, MSC_net_505, 
        MSC_net_506, MSC_net_507, MSC_net_508, MSC_net_509, 
        MSC_net_510, MSC_net_511, MSC_net_512, MSC_net_513, 
        MSC_net_514, MSC_net_515, MSC_net_516, MSC_net_517, 
        MSC_net_518, MSC_net_519, MSC_net_520, MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526, MSC_net_527, MSC_net_528, MSC_net_529, 
        MSC_net_530, MSC_net_531, MSC_net_532, MSC_net_533, 
        MSC_net_534, MSC_net_535, MSC_net_536, MSC_net_537, 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_S , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_Y , 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_0_Y , 
        MSC_net_581, MSC_net_582, MSC_net_583, MSC_net_584, 
        MSC_net_585, MSC_net_586, MSC_net_587, MSC_net_588, 
        MSC_net_589, MSC_net_590, MSC_net_591, MSC_net_592, 
        MSC_net_593, MSC_net_594, MSC_net_595, MSC_net_596, 
        MSC_net_597, MSC_net_598, MSC_net_599, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Y , 
        MSC_net_668, MSC_net_669, MSC_net_670, MSC_net_671, 
        MSC_net_672, MSC_net_673, MSC_net_674, MSC_net_675, 
        MSC_net_676, MSC_net_677, MSC_net_678, MSC_net_679, 
        MSC_net_680, MSC_net_681, MSC_net_682, MSC_net_683, 
        MSC_net_684, MSC_net_685, MSC_net_686, MSC_net_687, 
        MSC_net_688, MSC_net_689, MSC_net_690, MSC_net_691, 
        MSC_net_692, MSC_net_693, MSC_net_694, MSC_net_695, 
        MSC_net_696, MSC_net_697, MSC_net_698, MSC_net_699, 
        MSC_net_700, MSC_net_701, MSC_net_702, MSC_net_703, 
        MSC_net_704, MSC_net_705, MSC_net_706, MSC_net_707, 
        MSC_net_708, MSC_net_709, MSC_net_710, MSC_net_711, 
        MSC_net_712, MSC_net_713, MSC_net_714, MSC_net_715, 
        MSC_net_716, MSC_net_717, MSC_net_718, MSC_net_719, 
        MSC_net_720, MSC_net_721, MSC_net_722, MSC_net_723, 
        MSC_net_724, MSC_net_725, MSC_net_726, MSC_net_727, 
        MSC_net_728, MSC_net_729, MSC_net_730, MSC_net_731, 
        MSC_net_732, MSC_net_733, MSC_net_734, MSC_net_735, 
        MSC_net_736, MSC_net_737, MSC_net_738, MSC_net_739, 
        MSC_net_740, MSC_net_741, MSC_net_742, MSC_net_743, 
        MSC_net_744, MSC_net_745, MSC_net_746, MSC_net_747, 
        MSC_net_748, MSC_net_749, MSC_net_750, MSC_net_751, 
        MSC_net_752, MSC_net_753, MSC_net_754;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
khCuw5fTo7LN5vME/H/dBnJGYrJFhliiqzE0UlR4x0b0HJgRdAYM8czic6VT+i29
0zrTSnCr4YraepLwxnXKzlHT0FCyNkoed+wRYUldVXrdfpdi9cOpPew9KYZb9NoQ
obC1lPe0/bf2VueoUXxHZPLsBYc7oZXEb0eotctR+5c=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=115680)
`pragma protect data_block
[encoded data, 113856 characters]
0xhWv5NaI8Hp4FUVrtPstUG36/9fpN5E4QPq2brCmnk=

`pragma protect end_protected

endmodule


module 
        work_apb3_if_st_apb3_if_st_32_12_6_18_2_g_APB3_IF_DATA_WIDTHg_CONST_WIDTHg_ADC_CONFIG_REG_WIDTHg_STD_IO_WIDTH(
        
       apb3_if_st_0_adc_oc_thresh_o,
       apb3_if_st_0_adc_scale_val_o,
       apb3_if_st_0_id_ref_val_o,
       apb3_if_st_0_idq_pi_ki_o,
       apb3_if_st_0_idq_pi_kp_o,
       apb3_if_st_0_pwm_dead_time_val_o,
       apb3_if_st_0_pwm_delay_time_val_o,
       apb3_if_st_0_pwm_period_val_o,
       apb3_if_st_0_sqmng_dv_o,
       apb3_if_st_0_theta_gen_rate_limit_o,
       MC_System_0_AMBA_SLAVE_1_PWDATA,
       apb3_if_st_0_theta_gen_slew_count_o,
       apb3_if_st_0_theta_gen_cmd_step_no_o_0,
       apb3_if_st_0_adc_control_reg_val_o,
       apb3_if_st_0_seq_cntl_config_o,
       apb3_if_st_0_adc_channel_ch0_o,
       apb3_if_st_0_adc_channel_ch1_o,
       apb3_if_st_0_adc_channel_ch2_o,
       apb3_if_st_0_adc_channel_ch3_o,
       MC_System_0_AMBA_SLAVE_1_PADDR,
       prdata_o_1_0_a2_7_0,
       adc_interface_0_result_ch2_o_11,
       adc_interface_0_result_ch2_o_0,
       adc_interface_0_result_ch2_o_9,
       adc_interface_0_result_ch2_o_6,
       adc_interface_0_result_ch2_o_10,
       adc_interface_0_result_ch2_o_1,
       adc_interface_0_result_ch2_o_5,
       adc_interface_0_result_ch2_o_4,
       adc_interface_0_result_ch2_o_7,
       adc_interface_0_result_ch2_o_3,
       adc_interface_0_result_ch2_o_8,
       adc_measurements_0_adc_result_ch3_o_11,
       adc_measurements_0_adc_result_ch3_o_0,
       adc_measurements_0_adc_result_ch3_o_9,
       adc_measurements_0_adc_result_ch3_o_6,
       adc_measurements_0_adc_result_ch3_o_10,
       adc_measurements_0_adc_result_ch3_o_1,
       adc_measurements_0_adc_result_ch3_o_5,
       adc_measurements_0_adc_result_ch3_o_4,
       adc_measurements_0_adc_result_ch3_o_7,
       adc_measurements_0_adc_result_ch3_o_3,
       adc_measurements_0_adc_result_ch3_o_8,
       prdata_o_1_iv_12_0_2,
       prdata_o_1_iv_12_1,
       STEPPER_THETA_0_theta_output_o,
       SPEED_ID_IQ_PI_1_id_pi_output_o_m,
       SEQ_CONTROLLER_1_state_o_0_3,
       SEQ_CONTROLLER_1_state_o_0_1,
       SEQ_CONTROLLER_1_state_o_0_0,
       SPEED_ID_IQ_PI_1_id_pi_output_o,
       prdata_o_1_iv_9,
       adc_interface_0_result_ch0_o_0,
       adc_interface_0_result_ch0_o_11,
       adc_interface_0_result_ch0_o_1,
       adc_interface_0_result_ch0_o_9,
       adc_interface_0_result_ch0_o_6,
       adc_interface_0_result_ch0_o_10,
       adc_interface_0_result_ch0_o_5,
       adc_interface_0_result_ch0_o_8,
       adc_interface_0_result_ch0_o_4,
       adc_interface_0_result_ch0_o_3,
       adc_interface_0_result_ch0_o_7,
       SPEED_ID_IQ_PI_1_iq_pi_output_o,
       STEPPER_THETA_1_step_count_o_0,
       STEPPER_THETA_1_step_count_o_15,
       STEPPER_THETA_1_step_count_o_14,
       STEPPER_THETA_1_step_count_o_11,
       STEPPER_THETA_1_step_count_o_3,
       STEPPER_THETA_1_step_count_o_7,
       STEPPER_THETA_1_step_count_o_9,
       STEPPER_THETA_1_step_count_o_4,
       STEPPER_THETA_1_step_count_o_5,
       STEPPER_THETA_1_step_count_o_1,
       STEPPER_THETA_1_step_count_o_12,
       STEPPER_THETA_1_step_count_o_10,
       STEPPER_THETA_1_step_count_o_8,
       STEPPER_THETA_1_step_count_o_6,
       STEPPER_THETA_1_step_count_o_16,
       STEPPER_THETA_1_step_count_o_13,
       STEPPER_THETA_1_step_count_o_18,
       STEPPER_THETA_1_step_count_o_19,
       STEPPER_THETA_1_step_count_o_20,
       STEPPER_THETA_1_step_count_o_21,
       STEPPER_THETA_1_step_count_o_22,
       STEPPER_THETA_1_step_count_o_23,
       STEPPER_THETA_1_step_count_o_17,
       ADC_SCALING_0_ib_adc_o_9,
       ADC_SCALING_0_ib_adc_o_13,
       ADC_SCALING_0_ib_adc_o_16,
       ADC_SCALING_0_ib_adc_o_17,
       ADC_SCALING_0_ib_adc_o_11,
       ADC_SCALING_0_ib_adc_o_7,
       ADC_SCALING_0_ib_adc_o_6,
       ADC_SCALING_0_ib_adc_o_3,
       ADC_SCALING_0_ib_adc_o_15,
       ADC_SCALING_0_ib_adc_o_14,
       ADC_SCALING_0_ib_adc_o_12,
       ADC_SCALING_0_ib_adc_o_8,
       ADC_SCALING_0_ib_adc_o_5,
       ADC_SCALING_0_ib_adc_o_10,
       ADC_SCALING_0_ib_adc_o_4,
       ADC_SCALING_0_ib_adc_o_1,
       ADC_SCALING_0_ib_adc_o_0,
       ADC_SCALING_0_ia_adc_o,
       adc_measurements_0_adc_result_ch1_o_9,
       adc_measurements_0_adc_result_ch1_o_0,
       adc_measurements_0_adc_result_ch1_o_11,
       adc_measurements_0_adc_result_ch1_o_6,
       adc_measurements_0_adc_result_ch1_o_8,
       adc_measurements_0_adc_result_ch1_o_4,
       adc_measurements_0_adc_result_ch1_o_10,
       adc_measurements_0_adc_result_ch1_o_5,
       adc_measurements_0_adc_result_ch1_o_1,
       adc_measurements_0_adc_result_ch1_o_3,
       adc_measurements_0_adc_result_ch1_o_7,
       FOC_TRANSFORMS_0_vbeta_o_17,
       FOC_TRANSFORMS_0_vbeta_o_16,
       FOC_TRANSFORMS_0_vbeta_o_13,
       FOC_TRANSFORMS_0_vbeta_o_15,
       FOC_TRANSFORMS_0_vbeta_o_14,
       FOC_TRANSFORMS_0_vbeta_o_12,
       FOC_TRANSFORMS_0_vbeta_o_4,
       FOC_TRANSFORMS_0_vbeta_o_5,
       FOC_TRANSFORMS_0_vbeta_o_8,
       FOC_TRANSFORMS_0_vbeta_o_3,
       FOC_TRANSFORMS_0_vbeta_o_6,
       FOC_TRANSFORMS_0_vbeta_o_9,
       FOC_TRANSFORMS_0_vbeta_o_7,
       FOC_TRANSFORMS_0_vbeta_o_0,
       FOC_TRANSFORMS_0_vbeta_o_1,
       FOC_TRANSFORMS_0_vbeta_o_10,
       FOC_TRANSFORMS_0_vbeta_o_2,
       prdata_o_1_iv_12,
       FOC_TRANSFORMS_1_valpha_o_17,
       FOC_TRANSFORMS_1_valpha_o_16,
       FOC_TRANSFORMS_1_valpha_o_13,
       FOC_TRANSFORMS_1_valpha_o_15,
       FOC_TRANSFORMS_1_valpha_o_14,
       FOC_TRANSFORMS_1_valpha_o_12,
       FOC_TRANSFORMS_1_valpha_o_10,
       FOC_TRANSFORMS_1_valpha_o_2,
       FOC_TRANSFORMS_1_valpha_o_1,
       FOC_TRANSFORMS_1_valpha_o_0,
       FOC_TRANSFORMS_1_valpha_o_3,
       FOC_TRANSFORMS_1_valpha_o_4,
       FOC_TRANSFORMS_1_valpha_o_7,
       FOC_TRANSFORMS_1_valpha_o_5,
       FOC_TRANSFORMS_1_valpha_o_9,
       FOC_TRANSFORMS_1_valpha_o_8,
       FOC_TRANSFORMS_1_valpha_o_6,
       prdata_o_1_0_iv_11,
       FOC_TRANSFORMS_0_iq_o_9,
       FOC_TRANSFORMS_0_iq_o_6,
       FOC_TRANSFORMS_0_iq_o_7,
       FOC_TRANSFORMS_0_iq_o_3,
       FOC_TRANSFORMS_0_iq_o_1,
       FOC_TRANSFORMS_0_iq_o_17,
       FOC_TRANSFORMS_0_iq_o_4,
       FOC_TRANSFORMS_0_iq_o_10,
       FOC_TRANSFORMS_0_iq_o_5,
       FOC_TRANSFORMS_0_iq_o_8,
       FOC_TRANSFORMS_0_iq_o_0,
       FOC_TRANSFORMS_0_iq_o_15,
       FOC_TRANSFORMS_0_iq_o_14,
       FOC_TRANSFORMS_0_iq_o_12,
       FOC_TRANSFORMS_0_iq_o_16,
       FOC_TRANSFORMS_0_iq_o_13,
       prdata_o_1_0_iv_6,
       prdata_o_1_0_iv_7,
       FOC_TRANSFORMS_0_id_o_9,
       FOC_TRANSFORMS_0_id_o_0,
       FOC_TRANSFORMS_0_id_o_7,
       FOC_TRANSFORMS_0_id_o_1,
       FOC_TRANSFORMS_0_id_o_17,
       FOC_TRANSFORMS_0_id_o_6,
       FOC_TRANSFORMS_0_id_o_3,
       FOC_TRANSFORMS_0_id_o_15,
       FOC_TRANSFORMS_0_id_o_16,
       FOC_TRANSFORMS_0_id_o_13,
       FOC_TRANSFORMS_0_id_o_14,
       FOC_TRANSFORMS_0_id_o_12,
       FOC_TRANSFORMS_0_id_o_4,
       FOC_TRANSFORMS_0_id_o_10,
       FOC_TRANSFORMS_0_id_o_5,
       FOC_TRANSFORMS_0_id_o_8,
       prdata_o_1_iv_11_3,
       prdata_o_1_iv_11_1,
       prdata_o_1_iv_11_0,
       prdata_o_1_0_iv_10,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FAB_CCC_GL1,
       apb3_if_st_0_theta_gen_mode_o,
       apb3_if_st_0_stop_motor_o,
       apb3_if_st_0_start_motor_o,
       N_193,
       N_194,
       N_184,
       prdata_o197_0_a2_0_a2_0_out,
       N_185,
       N_174,
       prdata_o201_0_a2_0_0,
       g1,
       g2,
       N_172,
       N_187,
       N_104,
       N_105,
       N_106,
       N_107,
       N_108,
       adc_channel_ch3_o_1_sqmuxa_0_a2_0_0,
       prdata_o195_0_a2_0,
       prdata_o190_0_a2_0_out,
       N_202,
       prdata_o200_2,
       N_176,
       N_201,
       N_179,
       N_233,
       N_2787,
       MC_System_0_AMBA_SLAVE_1_PWRITE,
       MC_System_0_AMBA_SLAVE_1_PSELx,
       MC_System_0_AMBA_SLAVE_1_PENABLE,
       prdata_o191,
       prdata_o190,
       N_2470,
       N_151,
       N_152,
       N_153,
       N_154,
       N_155,
       N_156,
       N_157,
       N_54
    );
output [17:0] apb3_if_st_0_adc_oc_thresh_o;
output [17:0] apb3_if_st_0_adc_scale_val_o;
output [17:0] apb3_if_st_0_id_ref_val_o;
output [17:0] apb3_if_st_0_idq_pi_ki_o;
output [17:0] apb3_if_st_0_idq_pi_kp_o;
output [17:0] apb3_if_st_0_pwm_dead_time_val_o;
output [17:0] apb3_if_st_0_pwm_delay_time_val_o;
output [17:0] apb3_if_st_0_pwm_period_val_o;
output [17:0] apb3_if_st_0_sqmng_dv_o;
output [17:0] apb3_if_st_0_theta_gen_rate_limit_o;
input  [23:0] MC_System_0_AMBA_SLAVE_1_PWDATA;
output [17:0] apb3_if_st_0_theta_gen_slew_count_o;
output [23:0] apb3_if_st_0_theta_gen_cmd_step_no_o_0;
output [5:0] apb3_if_st_0_adc_control_reg_val_o;
output [2:1] apb3_if_st_0_seq_cntl_config_o;
output [15:0] apb3_if_st_0_adc_channel_ch0_o;
output [15:0] apb3_if_st_0_adc_channel_ch1_o;
output [15:0] apb3_if_st_0_adc_channel_ch2_o;
output [15:0] apb3_if_st_0_adc_channel_ch3_o;
input  [11:0] MC_System_0_AMBA_SLAVE_1_PADDR;
input  [3:3] prdata_o_1_0_a2_7_0;
input  adc_interface_0_result_ch2_o_11;
input  adc_interface_0_result_ch2_o_0;
input  adc_interface_0_result_ch2_o_9;
input  adc_interface_0_result_ch2_o_6;
input  adc_interface_0_result_ch2_o_10;
input  adc_interface_0_result_ch2_o_1;
input  adc_interface_0_result_ch2_o_5;
input  adc_interface_0_result_ch2_o_4;
input  adc_interface_0_result_ch2_o_7;
input  adc_interface_0_result_ch2_o_3;
input  adc_interface_0_result_ch2_o_8;
input  adc_measurements_0_adc_result_ch3_o_11;
input  adc_measurements_0_adc_result_ch3_o_0;
input  adc_measurements_0_adc_result_ch3_o_9;
input  adc_measurements_0_adc_result_ch3_o_6;
input  adc_measurements_0_adc_result_ch3_o_10;
input  adc_measurements_0_adc_result_ch3_o_1;
input  adc_measurements_0_adc_result_ch3_o_5;
input  adc_measurements_0_adc_result_ch3_o_4;
input  adc_measurements_0_adc_result_ch3_o_7;
input  adc_measurements_0_adc_result_ch3_o_3;
input  adc_measurements_0_adc_result_ch3_o_8;
output [3:3] prdata_o_1_iv_12_0_2;
output [3:3] prdata_o_1_iv_12_1;
input  [17:0] STEPPER_THETA_0_theta_output_o;
output [0:0] SPEED_ID_IQ_PI_1_id_pi_output_o_m;
input  SEQ_CONTROLLER_1_state_o_0_3;
input  SEQ_CONTROLLER_1_state_o_0_1;
input  SEQ_CONTROLLER_1_state_o_0_0;
input  [17:0] SPEED_ID_IQ_PI_1_id_pi_output_o;
output [0:0] prdata_o_1_iv_9;
input  adc_interface_0_result_ch0_o_0;
input  adc_interface_0_result_ch0_o_11;
input  adc_interface_0_result_ch0_o_1;
input  adc_interface_0_result_ch0_o_9;
input  adc_interface_0_result_ch0_o_6;
input  adc_interface_0_result_ch0_o_10;
input  adc_interface_0_result_ch0_o_5;
input  adc_interface_0_result_ch0_o_8;
input  adc_interface_0_result_ch0_o_4;
input  adc_interface_0_result_ch0_o_3;
input  adc_interface_0_result_ch0_o_7;
input  [17:1] SPEED_ID_IQ_PI_1_iq_pi_output_o;
input  STEPPER_THETA_1_step_count_o_0;
input  STEPPER_THETA_1_step_count_o_15;
input  STEPPER_THETA_1_step_count_o_14;
input  STEPPER_THETA_1_step_count_o_11;
input  STEPPER_THETA_1_step_count_o_3;
input  STEPPER_THETA_1_step_count_o_7;
input  STEPPER_THETA_1_step_count_o_9;
input  STEPPER_THETA_1_step_count_o_4;
input  STEPPER_THETA_1_step_count_o_5;
input  STEPPER_THETA_1_step_count_o_1;
input  STEPPER_THETA_1_step_count_o_12;
input  STEPPER_THETA_1_step_count_o_10;
input  STEPPER_THETA_1_step_count_o_8;
input  STEPPER_THETA_1_step_count_o_6;
input  STEPPER_THETA_1_step_count_o_16;
input  STEPPER_THETA_1_step_count_o_13;
input  STEPPER_THETA_1_step_count_o_18;
input  STEPPER_THETA_1_step_count_o_19;
input  STEPPER_THETA_1_step_count_o_20;
input  STEPPER_THETA_1_step_count_o_21;
input  STEPPER_THETA_1_step_count_o_22;
input  STEPPER_THETA_1_step_count_o_23;
input  STEPPER_THETA_1_step_count_o_17;
input  ADC_SCALING_0_ib_adc_o_9;
input  ADC_SCALING_0_ib_adc_o_13;
input  ADC_SCALING_0_ib_adc_o_16;
input  ADC_SCALING_0_ib_adc_o_17;
input  ADC_SCALING_0_ib_adc_o_11;
input  ADC_SCALING_0_ib_adc_o_7;
input  ADC_SCALING_0_ib_adc_o_6;
input  ADC_SCALING_0_ib_adc_o_3;
input  ADC_SCALING_0_ib_adc_o_15;
input  ADC_SCALING_0_ib_adc_o_14;
input  ADC_SCALING_0_ib_adc_o_12;
input  ADC_SCALING_0_ib_adc_o_8;
input  ADC_SCALING_0_ib_adc_o_5;
input  ADC_SCALING_0_ib_adc_o_10;
input  ADC_SCALING_0_ib_adc_o_4;
input  ADC_SCALING_0_ib_adc_o_1;
input  ADC_SCALING_0_ib_adc_o_0;
input  [17:0] ADC_SCALING_0_ia_adc_o;
input  adc_measurements_0_adc_result_ch1_o_9;
input  adc_measurements_0_adc_result_ch1_o_0;
input  adc_measurements_0_adc_result_ch1_o_11;
input  adc_measurements_0_adc_result_ch1_o_6;
input  adc_measurements_0_adc_result_ch1_o_8;
input  adc_measurements_0_adc_result_ch1_o_4;
input  adc_measurements_0_adc_result_ch1_o_10;
input  adc_measurements_0_adc_result_ch1_o_5;
input  adc_measurements_0_adc_result_ch1_o_1;
input  adc_measurements_0_adc_result_ch1_o_3;
input  adc_measurements_0_adc_result_ch1_o_7;
input  FOC_TRANSFORMS_0_vbeta_o_17;
input  FOC_TRANSFORMS_0_vbeta_o_16;
input  FOC_TRANSFORMS_0_vbeta_o_13;
input  FOC_TRANSFORMS_0_vbeta_o_15;
input  FOC_TRANSFORMS_0_vbeta_o_14;
input  FOC_TRANSFORMS_0_vbeta_o_12;
input  FOC_TRANSFORMS_0_vbeta_o_4;
input  FOC_TRANSFORMS_0_vbeta_o_5;
input  FOC_TRANSFORMS_0_vbeta_o_8;
input  FOC_TRANSFORMS_0_vbeta_o_3;
input  FOC_TRANSFORMS_0_vbeta_o_6;
input  FOC_TRANSFORMS_0_vbeta_o_9;
input  FOC_TRANSFORMS_0_vbeta_o_7;
input  FOC_TRANSFORMS_0_vbeta_o_0;
input  FOC_TRANSFORMS_0_vbeta_o_1;
input  FOC_TRANSFORMS_0_vbeta_o_10;
input  FOC_TRANSFORMS_0_vbeta_o_2;
output [3:1] prdata_o_1_iv_12;
input  FOC_TRANSFORMS_1_valpha_o_17;
input  FOC_TRANSFORMS_1_valpha_o_16;
input  FOC_TRANSFORMS_1_valpha_o_13;
input  FOC_TRANSFORMS_1_valpha_o_15;
input  FOC_TRANSFORMS_1_valpha_o_14;
input  FOC_TRANSFORMS_1_valpha_o_12;
input  FOC_TRANSFORMS_1_valpha_o_10;
input  FOC_TRANSFORMS_1_valpha_o_2;
input  FOC_TRANSFORMS_1_valpha_o_1;
input  FOC_TRANSFORMS_1_valpha_o_0;
input  FOC_TRANSFORMS_1_valpha_o_3;
input  FOC_TRANSFORMS_1_valpha_o_4;
input  FOC_TRANSFORMS_1_valpha_o_7;
input  FOC_TRANSFORMS_1_valpha_o_5;
input  FOC_TRANSFORMS_1_valpha_o_9;
input  FOC_TRANSFORMS_1_valpha_o_8;
input  FOC_TRANSFORMS_1_valpha_o_6;
output [10:4] prdata_o_1_0_iv_11;
input  FOC_TRANSFORMS_0_iq_o_9;
input  FOC_TRANSFORMS_0_iq_o_6;
input  FOC_TRANSFORMS_0_iq_o_7;
input  FOC_TRANSFORMS_0_iq_o_3;
input  FOC_TRANSFORMS_0_iq_o_1;
input  FOC_TRANSFORMS_0_iq_o_17;
input  FOC_TRANSFORMS_0_iq_o_4;
input  FOC_TRANSFORMS_0_iq_o_10;
input  FOC_TRANSFORMS_0_iq_o_5;
input  FOC_TRANSFORMS_0_iq_o_8;
input  FOC_TRANSFORMS_0_iq_o_0;
input  FOC_TRANSFORMS_0_iq_o_15;
input  FOC_TRANSFORMS_0_iq_o_14;
input  FOC_TRANSFORMS_0_iq_o_12;
input  FOC_TRANSFORMS_0_iq_o_16;
input  FOC_TRANSFORMS_0_iq_o_13;
output [16:12] prdata_o_1_0_iv_6;
output [16:12] prdata_o_1_0_iv_7;
input  FOC_TRANSFORMS_0_id_o_9;
input  FOC_TRANSFORMS_0_id_o_0;
input  FOC_TRANSFORMS_0_id_o_7;
input  FOC_TRANSFORMS_0_id_o_1;
input  FOC_TRANSFORMS_0_id_o_17;
input  FOC_TRANSFORMS_0_id_o_6;
input  FOC_TRANSFORMS_0_id_o_3;
input  FOC_TRANSFORMS_0_id_o_15;
input  FOC_TRANSFORMS_0_id_o_16;
input  FOC_TRANSFORMS_0_id_o_13;
input  FOC_TRANSFORMS_0_id_o_14;
input  FOC_TRANSFORMS_0_id_o_12;
input  FOC_TRANSFORMS_0_id_o_4;
input  FOC_TRANSFORMS_0_id_o_10;
input  FOC_TRANSFORMS_0_id_o_5;
input  FOC_TRANSFORMS_0_id_o_8;
output prdata_o_1_iv_11_3;
output prdata_o_1_iv_11_1;
output prdata_o_1_iv_11_0;
output [10:4] prdata_o_1_0_iv_10;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FAB_CCC_GL1;
output apb3_if_st_0_theta_gen_mode_o;
output apb3_if_st_0_stop_motor_o;
output apb3_if_st_0_start_motor_o;
output N_193;
output N_194;
output N_184;
output prdata_o197_0_a2_0_a2_0_out;
input  N_185;
output N_174;
output prdata_o201_0_a2_0_0;
output g1;
output g2;
output N_172;
output N_187;
output N_104;
output N_105;
output N_106;
output N_107;
output N_108;
output adc_channel_ch3_o_1_sqmuxa_0_a2_0_0;
output prdata_o195_0_a2_0;
output prdata_o190_0_a2_0_out;
output N_202;
output prdata_o200_2;
input  N_176;
output N_201;
output N_179;
output N_233;
input  N_2787;
input  MC_System_0_AMBA_SLAVE_1_PWRITE;
input  MC_System_0_AMBA_SLAVE_1_PSELx;
input  MC_System_0_AMBA_SLAVE_1_PENABLE;
output prdata_o191;
output prdata_o190;
input  N_2470;
output N_151;
output N_152;
output N_153;
output N_154;
output N_155;
output N_156;
output N_157;
output N_54;

    wire [9:9] prdata_o_1_0_iv_10_1;
    wire [10:4] prdata_o_1_0_iv_10_3;
    wire [9:9] prdata_o_1_0_iv_10_4_1;
    wire [9:6] ADC_SCALING_0_ia_adc_o_m;
    wire [10:4] prdata_o_1_0_iv_10_0;
    wire [9:6] FOC_TRANSFORMS_0_iq_o_m_0;
    wire [9:7] prdata_o_1_0_iv_1_tz;
    wire [0:0] prdata_o_1_iv_11_4;
    wire [1:0] prdata_o_1_iv_11_3_Z;
    wire [9:9] prdata_o_1_0_iv_10_1_1;
    wire [16:1] SPEED_ID_IQ_PI_1_iq_pi_output_o_m;
    wire [16:12] prdata_o_1_0_iv_6_0;
    wire [16:13] prdata_o_1_0_iv_7_1_0;
    wire [15:12] ADC_SCALING_0_ia_adc_o_m_0;
    wire [18:18] prdata_o_1_0_iv_0_a2_0_0;
    wire [3:3] prdata_o_1_iv_11_2_tz;
    wire [3:3] prdata_o_1_iv_4_tz;
    wire [0:0] prdata_o_1_iv_0_tz;
    wire [9:6] prdata_o_1_0_iv_0_tz;
    wire [3:3] SEQ_CONTROLLER_1_state_o_0_m_0;
    wire [1:1] STEPPER_THETA_0_theta_output_o_m_1;
    wire [10:4] prdata_o_1_0_iv_0_0;
    wire [1:1] STEPPER_THETA_1_step_count_o_m_1;
    wire [12:6] prdata_o_1_0_iv_1;
    wire [10:4] prdata_o_1_0_iv_1_0;
    wire [3:1] prdata_o_1_iv_0_0;
    wire [10:10] prdata_o_1_0_iv_10_2_RNO;
    wire [1:1] prdata_o_1_iv_11_4_tz;
    wire [18:18] prdata_o_1_0_iv_0_0_o2_3_tz;
    wire [18:18] prdata_o_1_0_iv_0_0_o2_2_a0_1;
    wire [10:4] prdata_o_1_0_iv_10_1_tz_0;
    wire [3:3] prdata_o_1_iv_12_0_0;
    wire [3:3] prdata_o_1_iv_5_a0;
    wire [18:18] prdata_o_1_0_iv_0_0_o2_4;
    wire [3:1] prdata_o_1_iv_11_0_Z;
    wire [3:1] prdata_o_1_iv_11_1_Z;
    wire [6:6] prdata_o_1_0_iv_10_1_tz;
    wire [1:1] SEQ_CONTROLLER_1_state_o_0_m;
    wire [15:1] ADC_SCALING_0_ib_adc_o_m;
    wire [3:3] prdata_o_1_iv_5;
    wire [16:13] prdata_o_1_0_iv_0;
    wire [18:18] prdata_o_1_0_iv_0_0_o2_0;
    wire [18:18] prdata_o_1_0_iv_0_0_o2_2_1;
    wire [0:0] prdata_o_1_iv_11_2;
    wire [3:3] prdata_o_1_iv_11_2_0;
    wire [10:4] prdata_o_1_0_iv_10_2;
    wire [16:12] prdata_o_1_0_iv_7_1;
    wire [16:12] prdata_o_1_0_iv_7_0;
    wire [10:4] prdata_o_1_0_iv_11_0;
    wire [3:1] prdata_o_1_iv_12_0;
    wire [3:3] FOC_TRANSFORMS_0_id_o_m;
    wire [7:7] adc_interface_0_result_ch0_o_m;
    wire [0:0] prdata_o_1_iv_11_5;
    wire [7:7] prdata_o_1_0_iv_10_5;
    wire [1:1] prdata_o_1_iv_11_4_0;
    wire VCC, adc_oc_thresh_o_1_sqmuxa, GND, adc_scale_val_o_1_sqmuxa, 
        id_ref_val_o_1_sqmuxa, idq_pi_ki_o_1_sqmuxa, 
        idq_pi_kp_o_0_sqmuxa, pwm_dead_time_val_o_1_sqmuxa, 
        pwm_delay_time_val_o_1_sqmuxa, pwm_period_val_o_1_sqmuxa, 
        sqmng_dv_o_1_sqmuxa, theta_gen_rate_limit_o_1_sqmuxa, 
        theta_gen_slew_count_o_1_sqmuxa, 
        theta_gen_cmd_step_no_o_1_sqmuxa, adc_channel_ch0_o_1_sqmuxa, 
        adc_control_reg_val_o_1_sqmuxa, seq_cntl_config_o_1_sqmuxa, 
        adc_channel_ch1_o_1_sqmuxa, adc_channel_ch2_o_1_sqmuxa, 
        adc_channel_ch3_o_1_sqmuxa, theta_gen_mode_o_1_sqmuxa, 
        stop_motor_o_1_sqmuxa, start_motor_o_1_sqmuxa, prdata_o197, 
        prdata_o_1_iv_11_3_N_5L8_Z, prdata_o_1_iv_11_3_N_7L12_1_Z, 
        prdata_o_1_iv_11_3_N_7L12_Z, prdata_o_1_iv_11_3_N_6L10_1_Z, 
        prdata_o_1_iv_11_3_N_6L10_Z, N_180, 
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_1_Z, g2_0_Z, N_177, N_181, 
        N_171, ADC_m1_e_1_0, prdata_m6_0, N_183, N_231, prdata_N_8_0, 
        prdata_N_8, N_99, idq_pi_kp_o_0_sqmuxa_0_a2_0_1, 
        prdata_m2_i_a3_1_0, ADC_m3_e_2_1, ADC_m1_0_a2_2_1, 
        FOC_TRANSFORMS_0_id_o_m_out_0, prdata_o197_0_a2_0_a2_0, 
        prdata_o196_0_a2_0_a2_0, N_205, N_198, prdata_m6_1, 
        prdata_m2_e_0, ADC_m1_e_1_2, FOC_m2_0_a2_1, SPEED_m1_0_a2_3_1, 
        adc_m1_0_a2_1, FOC_m1_0_a2_1, prdata_m6_4, adc_m2_0_a2_1, 
        adc_m1_0_a2_1_1, adc_N_5_mux_5, adc_N_5_mux_3, adc_N_5_mux, 
        adc_m1_0_a2_4_1, adc_m1_0_a2_0_1, adc_m1_0_a2_7_1, 
        adc_m1_0_a2_6_1, FOC_N_5_mux, adc_m2_0_a2_0_0, N_204, N_178, 
        N_232, N_182, N_226, N_1322, N_1321;
    
    CFG4 #( .INIT(16'hFFF2) )  \prdata_o_1_iv_11_3[0]  (.A(N_174), .B(
        prdata_o_1_iv_11_3_N_6L10_Z), .C(prdata_o_1_iv_11_3_N_7L12_Z), 
        .D(prdata_o_1_iv_11_4[0]), .Y(prdata_o_1_iv_11_3_Z[0]));
    SLE \idq_pi_kp_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[11]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_7_cZ[12]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_12), .C(
        prdata_o_1_0_iv_7_0[12]), .D(prdata_o_1_0_iv_7_1[12]), .Y(
        prdata_o_1_0_iv_7[12]));
    SLE \pwm_dead_time_val_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[6]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_9_cZ[0]  (.A(
        FOC_TRANSFORMS_1_valpha_o_0), .B(FOC_TRANSFORMS_0_vbeta_o_0), 
        .C(prdata_o_1_iv_12_1[3]), .D(prdata_o_1_iv_12_0_2[3]), .Y(
        prdata_o_1_iv_9[0]));
    SLE \adc_channel_ch1_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[3]));
    SLE \adc_scale_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[12]));
    SLE \theta_gen_rate_limit_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[14]));
    CFG3 #( .INIT(8'h80) )  id_ref_val_o_1_sqmuxa_0_a2 (.A(N_232), .B(
        N_204), .C(N_176), .Y(id_ref_val_o_1_sqmuxa));
    SLE \idq_pi_ki_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[8]));
    SLE \theta_gen_cmd_step_no_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[9]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_iv_0_0_0[3]  (.A(N_172), .B(
        prdata_o197_0_a2_0_a2_0_out), .C(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .Y(N_179));
    CFG3 #( .INIT(8'h80) )  adc_channel_ch2_o_1_sqmuxa_0_a2 (.A(N_205), 
        .B(N_182), .C(N_174), .Y(adc_channel_ch2_o_1_sqmuxa));
    SLE \pwm_delay_time_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[0]));
    SLE \pwm_dead_time_val_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[8]));
    SLE \idq_pi_kp_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[6]));
    SLE \theta_gen_rate_limit_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[11]));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_0_iv_1_0[10]  (.A(
        adc_interface_0_result_ch2_o_10), .B(
        adc_measurements_0_adc_result_ch3_o_10), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1_0[10])
        );
    CFG4 #( .INIT(16'hC888) )  \prdata_o_1_0_iv_10_3[7]  (.A(
        FOC_N_5_mux), .B(N_174), .C(ADC_m3_e_2_1), .D(N_177), .Y(
        prdata_o_1_0_iv_10_3[7]));
    SLE \adc_oc_thresh_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[17]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_6_0_RNO[12]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12]), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_183), .Y(SPEED_m1_0_a2_3_1));
    SLE \adc_channel_ch0_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[12]));
    SLE \pwm_dead_time_val_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[16]));
    CFG4 #( .INIT(16'hFFBF) )  \prdata_o_1_0_iv_10_cZ[9]  (.A(
        prdata_o_1_0_iv_10_1[9]), .B(prdata_o_1_0_iv_10_3[9]), .C(
        prdata_o_1_0_iv_10_4_1[9]), .D(ADC_SCALING_0_ia_adc_o_m[9]), 
        .Y(prdata_o_1_0_iv_10[9]));
    SLE \theta_gen_slew_count_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[5]));
    SLE \theta_gen_rate_limit_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[1]));
    SLE \adc_oc_thresh_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[9]));
    SLE \adc_channel_ch1_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[8]));
    SLE \id_ref_val_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[0]));
    CFG4 #( .INIT(16'h0080) )  adc_channel_ch1_o_1_sqmuxa_0_a2 (.A(
        N_205), .B(N_178), .C(N_174), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        adc_channel_ch1_o_1_sqmuxa));
    SLE \pwm_period_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[4]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_0_iv_11_cZ[8]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[8]), .B(
        FOC_TRANSFORMS_1_valpha_o_8), .C(prdata_o_1_0_iv_11_0[8]), .D(
        prdata_o_1_iv_12_1[3]), .Y(prdata_o_1_0_iv_11[8]));
    CFG2 #( .INIT(4'h4) )  \prdata_o_1_0_iv_7_1_RNO[14]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        ADC_SCALING_0_ia_adc_o[14]), .Y(prdata_o_1_0_iv_7_1_0[14]));
    CFG4 #( .INIT(16'hF888) )  \prdata_o_1_0_iv_10_0[6]  (.A(N_174), 
        .B(prdata_o_1_0_iv_10_1_tz[6]), .C(prdata_o_1_0_iv_0_tz[6]), 
        .D(N_233), .Y(prdata_o_1_0_iv_10_0[6]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_iv_11_RNO[1]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_1), .Y(ADC_SCALING_0_ib_adc_o_m[1]));
    SLE \pwm_period_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[9]));
    SLE \adc_oc_thresh_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[5]));
    CFG4 #( .INIT(16'h553F) )  prdata_o_1_iv_11_3_N_7L12_1 (.A(
        STEPPER_THETA_0_theta_output_o[0]), .B(
        STEPPER_THETA_1_step_count_o_0), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_iv_11_3_N_7L12_1_Z));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_10_1_tz[6]  (.A(
        ADC_m1_0_a2_2_1), .B(N_177), .C(adc_m2_0_a2_1), .D(
        adc_m1_0_a2_1_1), .Y(prdata_o_1_0_iv_10_1_tz[6]));
    SLE \adc_scale_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[11]));
    SLE \theta_gen_cmd_step_no_o[21]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[21]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[21]));
    SLE \id_ref_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[2]));
    CFG2 #( .INIT(4'h8) )  
        \READ_DECODE_PROC.prdata_o197_0_a2_0_a2_0_s  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(
        prdata_o197_0_a2_0_a2_0_out));
    SLE \pwm_delay_time_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[1]));
    SLE \adc_scale_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[10]));
    SLE \id_ref_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[14]));
    SLE \theta_gen_slew_count_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[1]));
    SLE \id_ref_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[5]));
    SLE \pwm_delay_time_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[4]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_2_RNO[4]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_interface_0_result_ch0_o_4), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_180), .Y(adc_N_5_mux));
    CFG4 #( .INIT(16'h8000) )  \READ_DECODE_PROC.prdata_o190_0_a2  (.A(
        N_172), .B(adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .C(
        prdata_o190_0_a2_0_out), .D(N_180), .Y(prdata_o190));
    SLE \theta_gen_cmd_step_no_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[6]));
    SLE \idq_pi_kp_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[0]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_iv_11_2[0]  (.A(
        prdata_o_1_iv_0_tz[0]), .B(SEQ_CONTROLLER_1_state_o_0_0), .C(
        N_2470), .D(N_233), .Y(prdata_o_1_iv_11_2[0]));
    CFG3 #( .INIT(8'h40) )  \prdata_o_1_0_iv_10_RNO[6]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ia_adc_o[6]), .Y(ADC_SCALING_0_ia_adc_o_m[6]));
    SLE \adc_channel_ch1_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[15]));
    CFG4 #( .INIT(16'h0800) )  
        theta_gen_slew_count_o_1_sqmuxa_0_a2_0_RNIV8JE1 (.A(N_177), .B(
        N_174), .C(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(g2_0_Z), .Y(
        g2));
    SLE \theta_gen_rate_limit_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[13]));
    SLE \adc_channel_ch3_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[13]));
    SLE \adc_channel_ch0_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[8]));
    SLE \theta_gen_cmd_step_no_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[12]));
    CFG2 #( .INIT(4'h4) )  adc_scale_val_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .B(N_183), .Y(N_198));
    CFG3 #( .INIT(8'hCA) )  \prdata_o_1_iv_11_2_tz[3]  (.A(
        STEPPER_THETA_1_step_count_o_3), .B(
        STEPPER_THETA_0_theta_output_o[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_iv_11_2_tz[3]));
    CFG4 #( .INIT(16'h0001) )  adc_channel_ch3_o_1_sqmuxa_0_a2_0_1 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[10]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .Y(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_iv_11[1]  (.A(N_193), .B(
        prdata_o_1_iv_11_4_tz[1]), .C(prdata_o_1_iv_11_4_0[1]), .D(
        ADC_SCALING_0_ib_adc_o_m[1]), .Y(prdata_o_1_iv_11_1));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_7_0[14]  (.A(
        FOC_TRANSFORMS_1_valpha_o_14), .B(FOC_TRANSFORMS_0_vbeta_o_14), 
        .C(prdata_o_1_iv_12_1[3]), .D(prdata_o_1_iv_12_0_2[3]), .Y(
        prdata_o_1_0_iv_7_0[14]));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_0_iv_1_0[5]  (.A(
        adc_interface_0_result_ch2_o_5), .B(
        adc_measurements_0_adc_result_ch3_o_5), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1_0[5]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_11_RNO[7]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[7]));
    SLE \adc_scale_val_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[0]));
    SLE \adc_channel_ch3_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[10]));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o197_0_a2_0_a2  (.A(N_172), .B(
        prdata_o197_0_a2_0_a2_0), .C(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .D(
        prdata_o197_0_a2_0_a2_0_out), .Y(prdata_o197));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_tz_RNO_0[6]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_measurements_0_adc_result_ch1_o_6), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_185), .Y(adc_m2_0_a2_1));
    SLE \pwm_dead_time_val_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[15]));
    SLE \pwm_dead_time_val_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[11]));
    SLE \pwm_delay_time_val_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[14]));
    CFG4 #( .INIT(16'h0080) )  adc_scale_val_o_1_sqmuxa_0_a2 (.A(N_198)
        , .B(N_178), .C(N_174), .D(MC_System_0_AMBA_SLAVE_1_PADDR[2]), 
        .Y(adc_scale_val_o_1_sqmuxa));
    SLE \theta_gen_cmd_step_no_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[2]));
    CFG4 #( .INIT(16'h8000) )  seq_cntl_config_o_1_sqmuxa_0_a2_1 (.A(
        N_202), .B(N_182), .C(N_171), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .Y(N_226));
    CFG4 #( .INIT(16'hFFC8) )  \prdata_o_1_0_iv_10_2[10]  (.A(
        prdata_o_1_0_iv_10_2_RNO[10]), .B(N_174), .C(
        prdata_o_1_0_iv_10_1_tz_0[10]), .D(prdata_o_1_0_iv_10_0[10]), 
        .Y(prdata_o_1_0_iv_10_2[10]));
    SLE \adc_channel_ch3_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[6]));
    CFG4 #( .INIT(16'hF800) )  \prdata_o_1_iv_11_4_0_RNO[1]  (.A(
        prdata_m2_i_a3_1_0), .B(prdata_o196_0_a2_0_a2_0), .C(
        adc_m2_0_a2_0_0), .D(N_174), .Y(prdata_o_1_iv_11_3_Z[1]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_11_0[6]  (.A(
        SPEED_ID_IQ_PI_1_id_pi_output_o[6]), .B(
        FOC_TRANSFORMS_0_vbeta_o_6), .C(prdata_o_1_iv_12_0_0[3]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_0_iv_11_0[6]));
    CFG3 #( .INIT(8'h80) )  stop_motor_o_1_sqmuxa_0_a2 (.A(N_226), .B(
        N_183), .C(MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(
        stop_motor_o_1_sqmuxa));
    SLE \adc_channel_ch0_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[3]));
    SLE \theta_gen_cmd_step_no_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[5]));
    CFG4 #( .INIT(16'h0010) )  \READ_DECODE_PROC.prdata_o201_0_a2_1  (
        .A(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(N_184));
    CFG3 #( .INIT(8'h80) )  adc_channel_ch0_o_1_sqmuxa_0_a2 (.A(N_182), 
        .B(N_177), .C(N_174), .Y(adc_channel_ch0_o_1_sqmuxa));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_11[3]  (.A(
        prdata_o_1_iv_5[3]), .B(FOC_TRANSFORMS_0_id_o_m[3]), .C(
        prdata_o_1_iv_11_2_0[3]), .D(prdata_o_1_iv_11_1_Z[3]), .Y(
        prdata_o_1_iv_11_3));
    CFG4 #( .INIT(16'h0001) )  \READ_DECODE_PROC.prdata_o200_0_a2_3  (
        .A(MC_System_0_AMBA_SLAVE_1_PADDR[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[1]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[10]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), .Y(N_202));
    CFG4 #( .INIT(16'h153F) )  prdata_o_1_iv_11_3_N_6L10_1 (.A(
        adc_interface_0_result_ch0_o_0), .B(
        adc_measurements_0_adc_result_ch1_o_0), .C(N_185), .D(N_180), 
        .Y(prdata_o_1_iv_11_3_N_6L10_1_Z));
    CFG4 #( .INIT(16'hECCC) )  \prdata_o_1_0_iv_6_0[15]  (.A(
        prdata_o201_0_a2_0_0), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[15]), .C(prdata_N_8_0), .D(
        N_184), .Y(prdata_o_1_0_iv_6_0[15]));
    SLE \idq_pi_kp_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[3]));
    SLE \idq_pi_ki_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[6]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_0_iv_11_cZ[7]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[7]), .B(
        FOC_TRANSFORMS_1_valpha_o_7), .C(prdata_o_1_0_iv_11_0[7]), .D(
        prdata_o_1_iv_12_1[3]), .Y(prdata_o_1_0_iv_11[7]));
    CFG4 #( .INIT(16'h135F) )  \prdata_o_1_0_iv_10_4_1[9]  (.A(
        prdata_o_1_0_iv_1_tz[9]), .B(
        adc_measurements_0_adc_result_ch1_o_9), .C(N_194), .D(
        prdata_o197), .Y(prdata_o_1_0_iv_10_4_1[9]));
    CFG4 #( .INIT(16'h80C0) )  \prdata_o_1_0_iv_0_0_a2[18]  (.A(
        STEPPER_THETA_0_theta_output_o[17]), .B(
        STEPPER_THETA_1_step_count_o_18), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_151));
    CFG3 #( .INIT(8'h01) )  idq_pi_kp_o_0_sqmuxa_0_a2_1 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[0]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[1]), .Y(N_172));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_11_0_RNO[3]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        FOC_TRANSFORMS_0_iq_o_3), .C(N_185), .D(N_176), .Y(
        FOC_m1_0_a2_1));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_0_iv_1_0[7]  (.A(
        adc_interface_0_result_ch2_o_7), .B(
        adc_measurements_0_adc_result_ch3_o_7), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1_0[7]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_RNO[7]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        adc_interface_0_result_ch0_o_7), .D(prdata_o196_0_a2_0_a2_0), 
        .Y(adc_interface_0_result_ch0_o_m[7]));
    CFG3 #( .INIT(8'hCA) )  \prdata_o_1_0_iv_6_RNO_0[15]  (.A(
        STEPPER_THETA_1_step_count_o_15), .B(
        STEPPER_THETA_0_theta_output_o[15]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_N_8_0));
    CFG4 #( .INIT(16'h80C0) )  \prdata_o_1_0_iv_0_0_a2[22]  (.A(
        STEPPER_THETA_0_theta_output_o[17]), .B(
        STEPPER_THETA_1_step_count_o_22), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_155));
    CFG4 #( .INIT(16'h0080) )  theta_gen_mode_o_1_sqmuxa_0_a2_1 (.A(
        N_181), .B(N_172), .C(MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .Y(N_204));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_iv_11_0_RNO[1]  (.A(N_184), .B(
        STEPPER_THETA_0_theta_output_o[1]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        STEPPER_THETA_0_theta_output_o_m_1[1]));
    CFG3 #( .INIT(8'h02) )  \READ_DECODE_PROC.prdata_o200_0_a2_2_0  (
        .A(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o200_2));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_11_0[5]  (.A(
        SPEED_ID_IQ_PI_1_id_pi_output_o[5]), .B(
        FOC_TRANSFORMS_0_vbeta_o_5), .C(prdata_o_1_iv_12_0_0[3]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_0_iv_11_0[5]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_0_0_o2_3_tz[18]  (.A(
        FOC_TRANSFORMS_0_iq_o_17), .B(FOC_TRANSFORMS_0_id_o_17), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_0_iv_0_0_o2_3_tz[18]));
    CFG4 #( .INIT(16'hC480) )  \prdata_o_1_iv_11_5[0]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_0), .D(ADC_SCALING_0_ia_adc_o[0]), .Y(
        prdata_o_1_iv_11_5[0]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_11_0[9]  (.A(
        SPEED_ID_IQ_PI_1_id_pi_output_o[9]), .B(
        FOC_TRANSFORMS_0_vbeta_o_9), .C(prdata_o_1_iv_12_0_0[3]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_0_iv_11_0[9]));
    CFG3 #( .INIT(8'hCA) )  \prdata_o_1_0_iv_6_RNO_0[14]  (.A(
        STEPPER_THETA_1_step_count_o_14), .B(
        STEPPER_THETA_0_theta_output_o[14]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_N_8));
    SLE \idq_pi_ki_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[3]));
    SLE \theta_gen_rate_limit_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[16]));
    CFG4 #( .INIT(16'hCC80) )  \prdata_o_1_0_iv_10_2[6]  (.A(N_180), 
        .B(N_193), .C(FOC_TRANSFORMS_0_id_o_6), .D(
        FOC_TRANSFORMS_0_iq_o_m_0[6]), .Y(prdata_o_1_0_iv_10_2[6]));
    SLE \idq_pi_ki_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[0]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_1_tz_0_RNO[8]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_measurements_0_adc_result_ch1_o_8), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_185), .Y(adc_m1_0_a2_4_1));
    CFG4 #( .INIT(16'hECCC) )  \prdata_o_1_0_iv_0_0_o2_0[18]  (.A(
        prdata_o201_0_a2_0_0), .B(prdata_o_1_0_iv_0_0_o2_4[18]), .C(
        prdata_o_1_0_iv_0_a2_0_0[18]), .D(N_184), .Y(
        prdata_o_1_0_iv_0_0_o2_0[18]));
    SLE \adc_channel_ch3_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[15]));
    CFG4 #( .INIT(16'h00AC) )  \prdata_o_1_0_iv_10_1[9]  (.A(N_187), 
        .B(N_193), .C(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .D(
        prdata_o_1_0_iv_10_1_1[9]), .Y(prdata_o_1_0_iv_10_1[9]));
    SLE \pwm_delay_time_val_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[7]));
    CFG4 #( .INIT(16'h0080) )  adc_control_reg_val_o_1_sqmuxa_0_a2 (.A(
        N_178), .B(N_177), .C(N_174), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        adc_control_reg_val_o_1_sqmuxa));
    SLE \adc_channel_ch0_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[4]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_iv_10_RNO_0[7]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        ADC_SCALING_0_ib_adc_o_7), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(ADC_m3_e_2_1));
    SLE \pwm_period_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14])
        , .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[14]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_0[16]  (.A(
        STEPPER_THETA_0_theta_output_o[16]), .B(
        STEPPER_THETA_1_step_count_o_16), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_0[16]));
    SLE \pwm_dead_time_val_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[7]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_7_1[14]  (.A(N_187), 
        .B(prdata_o_1_iv_12_0_0[3]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[14]), .D(
        prdata_o_1_0_iv_7_1_0[14]), .Y(prdata_o_1_0_iv_7_1[14]));
    SLE \adc_channel_ch3_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[8]));
    SLE \theta_gen_rate_limit_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[15]));
    SLE \theta_gen_cmd_step_no_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[13]));
    CFG4 #( .INIT(16'h2000) )  seq_cntl_config_o_1_sqmuxa_0_a2 (.A(
        N_226), .B(MC_System_0_AMBA_SLAVE_1_PADDR[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(
        seq_cntl_config_o_1_sqmuxa));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_0[4]  (.A(
        STEPPER_THETA_0_theta_output_o[4]), .B(
        STEPPER_THETA_1_step_count_o_4), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_0_0[4]));
    SLE \adc_oc_thresh_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[12]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_10_0[10]  (.A(
        prdata_o_1_0_iv_1_0[10]), .B(prdata_o_1_0_iv_0_0[10]), .C(
        prdata_o201_0_a2_0_0), .D(N_201), .Y(prdata_o_1_0_iv_10_0[10]));
    SLE \pwm_dead_time_val_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[9]));
    SLE \pwm_dead_time_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[1]));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_0_iv_0_0_m2[18]  (.A(
        ADC_SCALING_0_ib_adc_o_17), .B(ADC_SCALING_0_ia_adc_o[17]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_99));
    CFG4 #( .INIT(16'h80C0) )  \prdata_o_1_0_iv_0_0_a2[20]  (.A(
        STEPPER_THETA_0_theta_output_o[17]), .B(
        STEPPER_THETA_1_step_count_o_20), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_153));
    CFG4 #( .INIT(16'h135F) )  \prdata_o_1_iv_5_a0[3]  (.A(
        adc_measurements_0_adc_result_ch1_o_3), .B(
        adc_interface_0_result_ch0_o_3), .C(prdata_o197_0_a2_0_a2_0), 
        .D(prdata_o196_0_a2_0_a2_0), .Y(prdata_o_1_iv_5_a0[3]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_0_iv_11_cZ[6]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[6]), .B(
        FOC_TRANSFORMS_1_valpha_o_6), .C(prdata_o_1_0_iv_11_0[6]), .D(
        prdata_o_1_iv_12_1[3]), .Y(prdata_o_1_0_iv_11[6]));
    CFG3 #( .INIT(8'h08) )  \prdata_o_1_iv_0[3]  (.A(N_174), .B(
        prdata_o197_0_a2_0_a2_0_out), .C(prdata_o_1_iv_5_a0[3]), .Y(
        prdata_o_1_iv_5[3]));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_0_iv_0_tz[9]  (.A(
        adc_measurements_0_adc_result_ch3_o_9), .B(
        adc_interface_0_result_ch2_o_9), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_0_tz[9])
        );
    SLE \adc_oc_thresh_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[10]));
    SLE \theta_gen_slew_count_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[10]));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_0_iv_0_m2_1[11]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11]), .B(
        SPEED_ID_IQ_PI_1_id_pi_output_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_106));
    CFG4 #( .INIT(16'hFEEE) )  \prdata_o_1_0_iv_0_0_o2[18]  (.A(
        prdata_o_1_0_iv_0_0_o2_2_1[18]), .B(
        prdata_o_1_0_iv_0_0_o2_0[18]), .C(
        prdata_o_1_0_iv_0_0_o2_3_tz[18]), .D(N_193), .Y(N_54));
    SLE \theta_gen_slew_count_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[2]));
    CFG3 #( .INIT(8'h10) )  theta_gen_mode_o_1_sqmuxa_0_a2_2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(N_205));
    SLE \adc_channel_ch1_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[12]));
    SLE \theta_gen_slew_count_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[3]));
    SLE \adc_channel_ch0_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[2]));
    SLE \theta_gen_rate_limit_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[7]));
    SLE \theta_gen_rate_limit_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[12]));
    CFG4 #( .INIT(16'h8000) )  \READ_DECODE_PROC.prdata_o201_0_a2_0  (
        .A(N_171), .B(N_184), .C(N_172), .D(N_181), .Y(N_194));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_iv_10_1_tz_RNO[6]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        ADC_SCALING_0_ib_adc_o_6), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(ADC_m1_0_a2_2_1));
    CFG3 #( .INIT(8'hEC) )  \prdata_o_1_0_iv_10_5[7]  (.A(prdata_o197), 
        .B(ADC_SCALING_0_ia_adc_o_m[7]), .C(
        adc_measurements_0_adc_result_ch1_o_7), .Y(
        prdata_o_1_0_iv_10_5[7]));
    SLE \adc_channel_ch0_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[6]));
    SLE \adc_scale_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[13]));
    SLE \adc_oc_thresh_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[16]));
    SLE \idq_pi_kp_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[4]));
    SLE \theta_gen_cmd_step_no_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[1]));
    CFG2 #( .INIT(4'h8) )  pwm_delay_time_val_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .Y(N_231));
    SLE \theta_gen_slew_count_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[11]));
    SLE \theta_gen_slew_count_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[0]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_0[10]  (.A(
        STEPPER_THETA_0_theta_output_o[10]), .B(
        STEPPER_THETA_1_step_count_o_10), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_0_0[10])
        );
    SLE \theta_gen_slew_count_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[15]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_10_0[8]  (.A(
        prdata_o_1_0_iv_1_0[8]), .B(prdata_o_1_0_iv_0_0[8]), .C(
        prdata_o201_0_a2_0_0), .D(N_201), .Y(prdata_o_1_0_iv_10_0[8]));
    SLE \adc_oc_thresh_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[8]));
    SLE \sqmng_dv_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[15]));
    CFG3 #( .INIT(8'h7F) )  prdata_o_1_iv_11_3_N_5L8 (.A(N_181), .B(
        N_171), .C(N_172), .Y(prdata_o_1_iv_11_3_N_5L8_Z));
    CFG4 #( .INIT(16'hC480) )  \prdata_o_1_0_iv_10_3[10]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_10), .D(ADC_SCALING_0_ia_adc_o[10]), .Y(
        prdata_o_1_0_iv_10_3[10]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_1_tz_0_RNO[5]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_measurements_0_adc_result_ch1_o_5), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_185), .Y(adc_m1_0_a2_6_1));
    SLE \sqmng_dv_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[8]));
    SLE \adc_channel_ch2_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[3]));
    SLE \theta_gen_slew_count_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[14]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_11_RNO[5]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[5]));
    CFG4 #( .INIT(16'hFF80) )  \prdata_o_1_0_iv_10_1_tz_0[5]  (.A(
        FOC_TRANSFORMS_0_iq_o_5), .B(prdata_o190_0_a2_0_out), .C(N_185)
        , .D(adc_m1_0_a2_6_1), .Y(prdata_o_1_0_iv_10_1_tz_0[5]));
    SLE \adc_oc_thresh_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[1]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_11_2_0[3]  (.A(
        prdata_o_1_iv_11_2_tz[3]), .B(prdata_o_1_iv_4_tz[3]), .C(N_194)
        , .D(N_187), .Y(prdata_o_1_iv_11_2_0[3]));
    SLE \sqmng_dv_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[1]));
    SLE \pwm_dead_time_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[2]));
    CFG2 #( .INIT(4'h4) )  \prdata_o_1_0_iv_7_1_RNO[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        ADC_SCALING_0_ia_adc_o[15]), .Y(ADC_SCALING_0_ia_adc_o_m_0[15])
        );
    SLE \theta_gen_rate_limit_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[8]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_12_RNO[3]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[3]));
    SLE \theta_gen_cmd_step_no_o[19]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[19]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[19]));
    SLE \pwm_delay_time_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[3]));
    CFG4 #( .INIT(16'h1000) )  \prdata_o_1_iv_11_1_RNO_0[1]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(ADC_m1_e_1_0), .D(N_176)
        , .Y(ADC_m1_e_1_2));
    CFG4 #( .INIT(16'h0004) )  idq_pi_kp_o_0_sqmuxa_0_a2_0_2 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[10]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .Y(
        idq_pi_kp_o_0_sqmuxa_0_a2_0_1));
    SLE \adc_channel_ch1_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[1]));
    SLE \theta_gen_cmd_step_no_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[10]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_6_0_RNO[14]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[14]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_11_0[8]  (.A(
        SPEED_ID_IQ_PI_1_id_pi_output_o[8]), .B(
        FOC_TRANSFORMS_0_vbeta_o_8), .C(prdata_o_1_iv_12_0_0[3]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_0_iv_11_0[8]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_0_o2_0_RNO_1[18]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(N_172), .D(N_171), .Y(
        prdata_m6_4));
    SLE \adc_control_reg_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_control_reg_val_o[3]));
    CFG2 #( .INIT(4'h4) )  \prdata_o_1_0_iv_7_1_RNO[13]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        ADC_SCALING_0_ia_adc_o[13]), .Y(prdata_o_1_0_iv_7_1_0[13]));
    SLE \id_ref_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[13]));
    CFG2 #( .INIT(4'h2) )  stop_motor_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_183));
    CFG3 #( .INIT(8'h40) )  \prdata_o_1_0_iv_10_5_RNO[7]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ia_adc_o[7]), .Y(ADC_SCALING_0_ia_adc_o_m[7]));
    SLE \adc_channel_ch2_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[11]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_iv_6_RNO[14]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_14), .Y(ADC_SCALING_0_ib_adc_o_m[14]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_11_RNO[6]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[6]));
    SLE \id_ref_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[4]));
    SLE \adc_scale_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[8]));
    CFG3 #( .INIT(8'h80) )  theta_gen_rate_limit_o_1_sqmuxa_0_a2 (.A(
        N_204), .B(N_182), .C(N_177), .Y(
        theta_gen_rate_limit_o_1_sqmuxa));
    CFG3 #( .INIT(8'h08) )  \prdata_o_1_iv_11_4_RNO[0]  (.A(
        FOC_TRANSFORMS_0_id_o_0), .B(MC_System_0_AMBA_SLAVE_1_PADDR[4])
        , .C(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        FOC_TRANSFORMS_0_id_o_m_out_0));
    SLE \adc_channel_ch2_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[6]));
    SLE \adc_channel_ch0_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[1]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_12_0[3]  (.A(
        SPEED_ID_IQ_PI_1_id_pi_output_o[3]), .B(
        FOC_TRANSFORMS_0_vbeta_o_3), .C(prdata_o_1_iv_12_0_0[3]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_iv_12_0[3]));
    CFG4 #( .INIT(16'h80C0) )  \prdata_o_1_0_iv_0_0_a2[21]  (.A(
        STEPPER_THETA_0_theta_output_o[17]), .B(
        STEPPER_THETA_1_step_count_o_21), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_154));
    SLE \adc_oc_thresh_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[2]));
    CFG3 #( .INIT(8'h40) )  \prdata_o_1_0_iv_10_RNO[9]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ia_adc_o[9]), .Y(ADC_SCALING_0_ia_adc_o_m[9]));
    CFG3 #( .INIT(8'h80) )  adc_channel_ch3_o_1_sqmuxa_0_a2 (.A(N_232), 
        .B(N_176), .C(N_174), .Y(adc_channel_ch3_o_1_sqmuxa));
    SLE \pwm_dead_time_val_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[10]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_7_cZ[13]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_13), .C(
        prdata_o_1_0_iv_7_0[13]), .D(prdata_o_1_0_iv_7_1[13]), .Y(
        prdata_o_1_0_iv_7[13]));
    SLE \adc_channel_ch1_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[7]));
    SLE \adc_channel_ch3_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[12]));
    SLE \pwm_period_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13])
        , .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[13]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_0_RNO[9]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_interface_0_result_ch0_o_9), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_180), .Y(adc_m1_0_a2_1));
    SLE \adc_oc_thresh_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[6]));
    SLE \adc_channel_ch3_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[9]));
    SLE \theta_gen_cmd_step_no_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[7]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_11_0[4]  (.A(
        SPEED_ID_IQ_PI_1_id_pi_output_o[4]), .B(
        FOC_TRANSFORMS_0_vbeta_o_4), .C(prdata_o_1_iv_12_0_0[3]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_0_iv_11_0[4]));
    CFG4 #( .INIT(16'hFF80) )  \prdata_o_1_0_iv_10_1_tz_0[4]  (.A(
        FOC_TRANSFORMS_0_iq_o_4), .B(prdata_o190_0_a2_0_out), .C(N_185)
        , .D(adc_m1_0_a2_0_1), .Y(prdata_o_1_0_iv_10_1_tz_0[4]));
    SLE \id_ref_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[11]));
    SLE \adc_channel_ch1_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[9]));
    CFG3 #( .INIT(8'h10) )  \READ_DECODE_PROC.prdata_o190_0_a2_0_s  (
        .A(MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .Y(prdata_o190_0_a2_0_out)
        );
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_11_4_RNO_0[1]  (.A(
        prdata_o200_2), .B(SEQ_CONTROLLER_1_state_o_0_1), .C(N_2787), 
        .D(prdata_o_1_0_a2_7_0[3]), .Y(SEQ_CONTROLLER_1_state_o_0_m[1])
        );
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_0_iv_1_0[4]  (.A(
        adc_interface_0_result_ch2_o_4), .B(
        adc_measurements_0_adc_result_ch3_o_4), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1_0[4]));
    SLE \adc_channel_ch0_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[11]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_1_tz_0_RNO[4]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_measurements_0_adc_result_ch1_o_4), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_185), .Y(adc_m1_0_a2_0_1));
    SLE \adc_channel_ch2_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[8]));
    CFG4 #( .INIT(16'hECCC) )  \prdata_o_1_0_iv_6_0[14]  (.A(
        prdata_o201_0_a2_0_0), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[14]), .C(prdata_N_8), .D(
        N_184), .Y(prdata_o_1_0_iv_6_0[14]));
    CFG4 #( .INIT(16'h0080) )  theta_gen_mode_o_1_sqmuxa_0_a2_3 (.A(
        MC_System_0_AMBA_SLAVE_1_PWRITE), .B(
        MC_System_0_AMBA_SLAVE_1_PSELx), .C(
        MC_System_0_AMBA_SLAVE_1_PENABLE), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .Y(N_178));
    CFG3 #( .INIT(8'hCA) )  \prdata_o_1_0_iv_0_m2_0[11]  (.A(
        STEPPER_THETA_1_step_count_o_11), .B(
        STEPPER_THETA_0_theta_output_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_105));
    CFG4 #( .INIT(16'hF8F0) )  \prdata_o_1_0_iv_6_RNO[16]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        ADC_SCALING_0_ib_adc_o_16), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[16]), .D(N_187), .Y(
        prdata_o_1_0_iv_6_0[16]));
    SLE \adc_channel_ch3_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[4]));
    SLE \adc_oc_thresh_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[15]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_11_0[3]  (.A(
        FOC_m1_0_a2_1), .B(prdata_o_1_iv_0_0[3]), .C(N_174), .D(N_201), 
        .Y(prdata_o_1_iv_11_0_Z[3]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_11_RNO[10]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[10]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_2_RNO[8]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_interface_0_result_ch0_o_8), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_180), .Y(adc_N_5_mux_3));
    SLE \theta_gen_rate_limit_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[17]));
    SLE \adc_scale_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[1]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_12_RNO[2]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[2]));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_iv_0_tz[0]  (.A(
        adc_measurements_0_adc_result_ch3_o_0), .B(
        adc_interface_0_result_ch2_o_0), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_iv_0_tz[0]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_11_0[10]  (.A(
        FOC_TRANSFORMS_1_valpha_o_10), .B(
        SPEED_ID_IQ_PI_1_id_pi_output_o[10]), .C(prdata_o_1_iv_12_1[3])
        , .D(prdata_o_1_iv_12_0_0[3]), .Y(prdata_o_1_0_iv_11_0[10]));
    SLE \adc_channel_ch2_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[4]));
    SLE \pwm_delay_time_val_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[6]));
    SLE \id_ref_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[1]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_0_iv_11_cZ[4]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[4]), .B(
        FOC_TRANSFORMS_1_valpha_o_4), .C(prdata_o_1_0_iv_11_0[4]), .D(
        prdata_o_1_iv_12_1[3]), .Y(prdata_o_1_0_iv_11[4]));
    SLE \adc_channel_ch0_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[7]));
    CFG3 #( .INIT(8'h08) )  \READ_DECODE_PROC.prdata_o195_0_a2_0  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(prdata_o195_0_a2_0));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o201_0_a2_0_0_RNIGM521  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        STEPPER_THETA_0_theta_output_o[2]), .C(prdata_o201_0_a2_0_0), 
        .D(N_184), .Y(g1));
    GND GND_Z (.Y(GND));
    SLE \pwm_delay_time_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[2]));
    SLE \pwm_dead_time_val_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[14]));
    CFG3 #( .INIT(8'hCA) )  \prdata_o_1_0_iv_1_tz[7]  (.A(
        STEPPER_THETA_1_step_count_o_7), .B(
        STEPPER_THETA_0_theta_output_o[7]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1_tz[7])
        );
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_7_cZ[16]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_16), .C(
        prdata_o_1_0_iv_7_0[16]), .D(prdata_o_1_0_iv_7_1[16]), .Y(
        prdata_o_1_0_iv_7[16]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_6_RNO_0[16]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[16]));
    SLE \theta_gen_cmd_step_no_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[15]));
    VCC VCC_Z (.Y(VCC));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_6_RNO_0[13]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[13]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_0[5]  (.A(
        STEPPER_THETA_0_theta_output_o[5]), .B(
        STEPPER_THETA_1_step_count_o_5), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_0_0[5]));
    SLE \theta_gen_cmd_step_no_o[22]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[22]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[22]));
    SLE \theta_gen_cmd_step_no_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[0]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_12_0[2]  (.A(
        FOC_TRANSFORMS_1_valpha_o_2), .B(
        SPEED_ID_IQ_PI_1_id_pi_output_o[2]), .C(prdata_o_1_iv_12_1[3]), 
        .D(prdata_o_1_iv_12_0_0[3]), .Y(prdata_o_1_iv_12_0[2]));
    SLE \idq_pi_ki_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[17]));
    SLE \adc_scale_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[15]));
    SLE \adc_channel_ch2_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[14]));
    SLE \theta_gen_slew_count_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[8]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_11_RNO[4]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[4]));
    SLE \theta_gen_slew_count_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[12]));
    SLE \pwm_delay_time_val_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[8]));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_0_iv_2_1_m3_i_m2[11]  (.A(
        adc_measurements_0_adc_result_ch1_o_11), .B(
        adc_interface_0_result_ch0_o_11), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_108));
    SLE \theta_gen_cmd_step_no_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[14]));
    CFG4 #( .INIT(16'hFFC8) )  \prdata_o_1_0_iv_10_2[5]  (.A(
        adc_N_5_mux_5), .B(N_174), .C(prdata_o_1_0_iv_10_1_tz_0[5]), 
        .D(prdata_o_1_0_iv_10_0[5]), .Y(prdata_o_1_0_iv_10_2[5]));
    SLE \theta_gen_rate_limit_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[4]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_10_cZ[8]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_8), .C(
        prdata_o_1_0_iv_10_2[8]), .D(prdata_o_1_0_iv_10_3[8]), .Y(
        prdata_o_1_0_iv_10[8]));
    SLE \id_ref_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[17]));
    SLE \adc_channel_ch0_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[0]));
    SLE \adc_channel_ch1_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[4]));
    SLE start_motor_o (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(start_motor_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_start_motor_o));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_iv_11_1[1]  (.A(
        STEPPER_THETA_1_step_count_o_m_1[1]), .B(ADC_m1_e_1_2), .C(
        N_174), .D(prdata_o201_0_a2_0_0), .Y(prdata_o_1_iv_11_1_Z[1]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_7_0[13]  (.A(
        FOC_TRANSFORMS_1_valpha_o_13), .B(FOC_TRANSFORMS_0_vbeta_o_13), 
        .C(prdata_o_1_iv_12_1[3]), .D(prdata_o_1_iv_12_0_2[3]), .Y(
        prdata_o_1_0_iv_7_0[13]));
    SLE \id_ref_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[6]));
    SLE \adc_scale_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[16]));
    SLE \adc_oc_thresh_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[0]));
    CFG4 #( .INIT(16'h1000) )  \prdata_o_1_0_iv_0_0_o2_0_RNO[18]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[10]), .C(prdata_m6_1), .D(
        prdata_m6_4), .Y(prdata_o_1_0_iv_0_0_o2_4[18]));
    SLE \pwm_period_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[6]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_iv_11_4_tz[1]  (.A(
        FOC_TRANSFORMS_0_iq_o_1), .B(FOC_TRANSFORMS_0_id_o_1), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_iv_11_4_tz[1]));
    SLE theta_gen_mode_o (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_mode_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_theta_gen_mode_o));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_iv_4_tz[3]  (.A(
        ADC_SCALING_0_ib_adc_o_3), .B(ADC_SCALING_0_ia_adc_o[3]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_iv_4_tz[3]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_2_RNO[5]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_interface_0_result_ch0_o_5), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_180), .Y(adc_N_5_mux_5));
    SLE \pwm_dead_time_val_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[12]));
    CFG4 #( .INIT(16'hC888) )  \prdata_o_1_0_iv_0_0_o2_2_1[18]  (.A(
        prdata_o_1_0_iv_0_0_o2_2_a0_1[18]), .B(N_174), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(prdata_m2_e_0), .Y(
        prdata_o_1_0_iv_0_0_o2_2_1[18]));
    CFG4 #( .INIT(16'h2000) )  stop_motor_o_1_sqmuxa_0_a2_0_RNII12F1 (
        .A(N_183), .B(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(N_174), 
        .D(prdata_o197_0_a2_0_a2_0_out), .Y(prdata_o_1_iv_12_0_0[3]));
    SLE \pwm_period_val_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[0]));
    CFG4 #( .INIT(16'h8000) )  pwm_dead_time_val_o_1_sqmuxa_0_a2 (.A(
        N_232), .B(N_174), .C(MC_System_0_AMBA_SLAVE_1_PADDR[5]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(
        pwm_dead_time_val_o_1_sqmuxa));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_11_4_0[1]  (.A(
        prdata_o_1_iv_11_3_Z[1]), .B(SEQ_CONTROLLER_1_state_o_0_m[1]), 
        .C(prdata_o_1_iv_11_1_Z[1]), .D(prdata_o_1_iv_11_0_Z[1]), .Y(
        prdata_o_1_iv_11_4_0[1]));
    SLE \adc_scale_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[4]));
    SLE \adc_channel_ch0_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[14]));
    CFG4 #( .INIT(16'h80C0) )  \prdata_o_1_0_iv_0_0_a2[23]  (.A(
        STEPPER_THETA_0_theta_output_o[17]), .B(
        STEPPER_THETA_1_step_count_o_23), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_156));
    SLE \idq_pi_kp_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[17]));
    SLE \sqmng_dv_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[6]));
    CFG3 #( .INIT(8'h01) )  theta_gen_slew_count_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_177));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_6_cZ[13]  (.A(
        FOC_TRANSFORMS_0_iq_o_13), .B(prdata_o191), .C(
        prdata_o_1_0_iv_0[13]), .D(prdata_o_1_0_iv_6_0[13]), .Y(
        prdata_o_1_0_iv_6[13]));
    SLE \idq_pi_ki_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[1]));
    CFG4 #( .INIT(16'h0001) )  adc_channel_ch3_o_1_sqmuxa_0_a2_0_0_c (
        .A(MC_System_0_AMBA_SLAVE_1_PADDR[0]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[1]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .Y(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_1_Z));
    SLE \seq_cntl_config_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_seq_cntl_config_o[1]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_0_iv_11_cZ[5]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[5]), .B(
        FOC_TRANSFORMS_1_valpha_o_5), .C(prdata_o_1_0_iv_11_0[5]), .D(
        prdata_o_1_iv_12_1[3]), .Y(prdata_o_1_0_iv_11[5]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_0[8]  (.A(
        STEPPER_THETA_0_theta_output_o[8]), .B(
        STEPPER_THETA_1_step_count_o_8), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_0_0[8]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_10_cZ[10]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_10), .C(
        prdata_o_1_0_iv_10_2[10]), .D(prdata_o_1_0_iv_10_3[10]), .Y(
        prdata_o_1_0_iv_10[10]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_11_RNO[8]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[8]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_iv_12_cZ[2]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[2]), .B(
        FOC_TRANSFORMS_0_vbeta_o_2), .C(prdata_o_1_iv_12_0[2]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_iv_12[2]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_12_0[1]  (.A(
        FOC_TRANSFORMS_1_valpha_o_1), .B(
        SPEED_ID_IQ_PI_1_id_pi_output_o[1]), .C(prdata_o_1_iv_12_1[3]), 
        .D(prdata_o_1_iv_12_0_0[3]), .Y(prdata_o_1_iv_12_0[1]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_tz_RNO_1[6]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_interface_0_result_ch0_o_6), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_180), .Y(adc_m1_0_a2_1_1));
    CFG4 #( .INIT(16'h8000) )  
        theta_gen_slew_count_o_1_sqmuxa_0_a2_0_RNIB9D11 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(N_177), .C(N_172), .D(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .Y(N_187));
    CFG4 #( .INIT(16'h80C0) )  \prdata_o_1_0_iv_0_0_a2[17]  (.A(
        STEPPER_THETA_0_theta_output_o[17]), .B(
        STEPPER_THETA_1_step_count_o_17), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_157));
    CFG4 #( .INIT(16'h2000) )  
        \READ_DECODE_PROC.prdata_o197_0_a2_0_a2_0_s_RNIOQL91  (.A(
        N_185), .B(MC_System_0_AMBA_SLAVE_1_PADDR[5]), .C(N_174), .D(
        prdata_o197_0_a2_0_a2_0_out), .Y(prdata_o_1_iv_12_0_2[3]));
    SLE \adc_channel_ch0_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[5]));
    CFG2 #( .INIT(4'h8) )  sqmng_dv_o_1_sqmuxa_0_a2 (.A(N_198), .B(
        N_226), .Y(sqmng_dv_o_1_sqmuxa));
    SLE \pwm_period_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15])
        , .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[15]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_1[12]  (.A(
        STEPPER_THETA_0_theta_output_o[12]), .B(
        STEPPER_THETA_1_step_count_o_12), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1[12]));
    SLE \adc_channel_ch1_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[2]));
    SLE \idq_pi_ki_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[15]));
    SLE \pwm_delay_time_val_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[13]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_10_0[9]  (.A(
        prdata_o_1_0_iv_0_tz[9]), .B(adc_m1_0_a2_1), .C(N_233), .D(
        N_174), .Y(prdata_o_1_0_iv_10_0[9]));
    SLE \seq_cntl_config_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_seq_cntl_config_o[2]));
    SLE \theta_gen_rate_limit_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[9]));
    SLE \pwm_delay_time_val_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[15]));
    CFG4 #( .INIT(16'h80C0) )  \prdata_o_1_0_iv_0_0_a2[19]  (.A(
        STEPPER_THETA_0_theta_output_o[17]), .B(
        STEPPER_THETA_1_step_count_o_19), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_152));
    SLE \idq_pi_kp_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[8]));
    SLE \pwm_period_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17])
        , .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[17]));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_iv_0_0[3]  (.A(
        adc_interface_0_result_ch2_o_3), .B(
        adc_measurements_0_adc_result_ch3_o_3), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_iv_0_0[3]));
    SLE \adc_channel_ch3_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[2]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_1[6]  (.A(
        STEPPER_THETA_0_theta_output_o[6]), .B(
        STEPPER_THETA_1_step_count_o_6), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1[6]));
    CFG4 #( .INIT(16'hC480) )  \prdata_o_1_0_iv_10_3[4]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_4), .D(ADC_SCALING_0_ia_adc_o[4]), .Y(
        prdata_o_1_0_iv_10_3[4]));
    SLE \theta_gen_cmd_step_no_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[3]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_12_RNO[1]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[1]));
    CFG4 #( .INIT(16'hA0C0) )  \prdata_o_1_0_iv_0[13]  (.A(
        STEPPER_THETA_0_theta_output_o[13]), .B(
        STEPPER_THETA_1_step_count_o_13), .C(N_194), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_0[13]));
    SLE \adc_control_reg_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_control_reg_val_o[0]));
    CFG3 #( .INIT(8'hFE) )  \prdata_o_1_iv_11[0]  (.A(
        prdata_o_1_iv_11_3_Z[0]), .B(prdata_o_1_iv_11_2[0]), .C(
        prdata_o_1_iv_11_5[0]), .Y(prdata_o_1_iv_11_0));
    SLE \theta_gen_cmd_step_no_o[23]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[23]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[23]));
    CFG4 #( .INIT(16'h8000) )  \READ_DECODE_PROC.prdata_o191_0_a2  (.A(
        N_172), .B(prdata_o190_0_a2_0_out), .C(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .D(N_185), .Y(
        prdata_o191));
    SLE \theta_gen_slew_count_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[9]));
    CFG3 #( .INIT(8'hFE) )  \prdata_o_1_0_iv_10_cZ[7]  (.A(
        adc_interface_0_result_ch0_o_m[7]), .B(prdata_o_1_0_iv_10_2[7])
        , .C(prdata_o_1_0_iv_10_5[7]), .Y(prdata_o_1_0_iv_10[7]));
    SLE \adc_control_reg_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_control_reg_val_o[5]));
    CFG2 #( .INIT(4'h8) )  g2_0 (.A(MC_System_0_AMBA_SLAVE_1_PADDR[11])
        , .B(ADC_SCALING_0_ia_adc_o[2]), .Y(g2_0_Z));
    SLE \pwm_dead_time_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[5]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_6_0_RNO[15]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[15]));
    CFG4 #( .INIT(16'hC480) )  \prdata_o_1_0_iv_10_3[8]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_8), .D(ADC_SCALING_0_ia_adc_o[8]), .Y(
        prdata_o_1_0_iv_10_3[8]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_3_RNO[7]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        FOC_TRANSFORMS_0_id_o_7), .C(N_180), .D(N_176), .Y(FOC_N_5_mux)
        );
    SLE \adc_channel_ch2_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[1]));
    SLE \adc_channel_ch1_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[11]));
    SLE \theta_gen_rate_limit_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[6]));
    SLE \pwm_delay_time_val_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[10]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_7_1[13]  (.A(N_187), 
        .B(prdata_o_1_iv_12_0_0[3]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[13]), .D(
        prdata_o_1_0_iv_7_1_0[13]), .Y(prdata_o_1_0_iv_7_1[13]));
    SLE \adc_control_reg_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_control_reg_val_o[1]));
    SLE \pwm_period_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10])
        , .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[10]));
    SLE \idq_pi_kp_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[15]));
    SLE \idq_pi_ki_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[14]));
    CFG4 #( .INIT(16'hFF80) )  \prdata_o_1_0_iv_10_1_tz_0[8]  (.A(
        FOC_TRANSFORMS_0_iq_o_8), .B(prdata_o190_0_a2_0_out), .C(N_185)
        , .D(adc_m1_0_a2_4_1), .Y(prdata_o_1_0_iv_10_1_tz_0[8]));
    CFG4 #( .INIT(16'hFF80) )  \prdata_o_1_0_iv_10_1_tz_0[10]  (.A(
        FOC_TRANSFORMS_0_iq_o_10), .B(prdata_o190_0_a2_0_out), .C(
        N_185), .D(adc_m1_0_a2_7_1), .Y(prdata_o_1_0_iv_10_1_tz_0[10]));
    SLE \id_ref_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[10]));
    SLE \adc_channel_ch2_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[2]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_11_RNO[3]  (.A(N_180), 
        .B(N_174), .C(FOC_TRANSFORMS_0_id_o_3), .D(
        prdata_o190_0_a2_0_out), .Y(FOC_TRANSFORMS_0_id_o_m[3]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_0_iv_11_cZ[9]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[9]), .B(
        FOC_TRANSFORMS_1_valpha_o_9), .C(prdata_o_1_0_iv_11_0[9]), .D(
        prdata_o_1_iv_12_1[3]), .Y(prdata_o_1_0_iv_11[9]));
    SLE \idq_pi_ki_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[13]));
    SLE \pwm_dead_time_val_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[17]));
    SLE \adc_scale_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[3]));
    CFG4 #( .INIT(16'h0080) )  idq_pi_kp_o_0_sqmuxa_0_a2 (.A(N_201), 
        .B(N_198), .C(N_178), .D(MC_System_0_AMBA_SLAVE_1_PADDR[2]), 
        .Y(idq_pi_kp_o_0_sqmuxa));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_iv_10_2_RNO[6]  (.A(
        FOC_TRANSFORMS_0_iq_o_6), .B(MC_System_0_AMBA_SLAVE_1_PADDR[4])
        , .C(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        FOC_TRANSFORMS_0_iq_o_m_0[6]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_0_iv_11_cZ[10]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[10]), .B(
        FOC_TRANSFORMS_0_vbeta_o_10), .C(prdata_o_1_0_iv_11_0[10]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_0_iv_11[10]));
    CFG4 #( .INIT(16'h4000) )  \prdata_o_1_0_iv_0_0_o2_2_a0_1[18]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .C(N_99), .D(N_176), .Y(
        prdata_o_1_0_iv_0_0_o2_2_a0_1[18]));
    SLE \pwm_period_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[3]));
    CFG4 #( .INIT(16'h0080) )  theta_gen_slew_count_o_1_sqmuxa_0_a2 (
        .A(N_204), .B(N_178), .C(N_177), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        theta_gen_slew_count_o_1_sqmuxa));
    SLE \theta_gen_slew_count_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[16]));
    SLE \sqmng_dv_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[14]));
    SLE \adc_channel_ch2_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[9]));
    SLE \theta_gen_slew_count_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[17]));
    CFG3 #( .INIT(8'h08) )  \prdata_o_1_iv_11_1_RNO[1]  (.A(N_184), .B(
        STEPPER_THETA_1_step_count_o_1), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        STEPPER_THETA_1_step_count_o_m_1[1]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_7_0[12]  (.A(
        FOC_TRANSFORMS_1_valpha_o_12), .B(FOC_TRANSFORMS_0_vbeta_o_12), 
        .C(prdata_o_1_iv_12_1[3]), .D(prdata_o_1_iv_12_0_2[3]), .Y(
        prdata_o_1_0_iv_7_0[12]));
    SLE \adc_scale_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[5]));
    SLE \theta_gen_slew_count_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[7]));
    CFG2 #( .INIT(4'h8) )  \prdata_o_1_iv_11_1_RNO_1[1]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        ADC_SCALING_0_ia_adc_o[1]), .Y(ADC_m1_e_1_0));
    CFG3 #( .INIT(8'h13) )  \prdata_o_1_0_iv_10_2[9]  (.A(N_193), .B(
        prdata_o_1_0_iv_10_0[9]), .C(FOC_TRANSFORMS_0_iq_o_m_0[9]), .Y(
        prdata_o_1_0_iv_10_3[9]));
    CFG2 #( .INIT(4'h8) )  \prdata_o_1_iv_11_1_RNO[3]  (.A(
        prdata_o_1_0_a2_7_0[3]), .B(SEQ_CONTROLLER_1_state_o_0_3), .Y(
        SEQ_CONTROLLER_1_state_o_0_m_0[3]));
    SLE \idq_pi_kp_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[14]));
    SLE \sqmng_dv_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[5]));
    SLE \adc_scale_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[2]));
    CFG3 #( .INIT(8'h40) )  \READ_DECODE_PROC.prdata_o196_0_a2_0_a2_0  
        (.A(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(prdata_o196_0_a2_0_a2_0)
        );
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_iv_10_2_RNO[9]  (.A(
        FOC_TRANSFORMS_0_iq_o_9), .B(MC_System_0_AMBA_SLAVE_1_PADDR[4])
        , .C(MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        FOC_TRANSFORMS_0_iq_o_m_0[9]));
    SLE \idq_pi_kp_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[13]));
    SLE \adc_channel_ch3_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[5]));
    SLE \adc_channel_ch3_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[1]));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_0_iv_10_cZ[6]  (.A(
        prdata_o_1_0_iv_1[6]), .B(ADC_SCALING_0_ia_adc_o_m[6]), .C(
        prdata_o_1_0_iv_10_2[6]), .D(prdata_o_1_0_iv_10_0[6]), .Y(
        prdata_o_1_0_iv_10[6]));
    SLE \adc_channel_ch3_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[7]));
    SLE \sqmng_dv_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[13]));
    SLE \pwm_period_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12])
        , .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[12]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_11_4_RNO_2[1]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_measurements_0_adc_result_ch1_o_1), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_185), .Y(adc_m2_0_a2_0_0));
    CFG4 #( .INIT(16'h0080) )  pwm_period_val_o_1_sqmuxa_0_a2 (.A(
        N_231), .B(N_182), .C(N_174), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(
        pwm_period_val_o_1_sqmuxa));
    SLE \adc_oc_thresh_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[14]));
    SLE \pwm_delay_time_val_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[11]));
    SLE \theta_gen_cmd_step_no_o[20]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[20]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[20]));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o201_0_a2_3  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[10]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[9]), .Y(N_181));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_10_0[7]  (.A(
        FOC_m2_0_a2_1), .B(prdata_o_1_0_iv_1_0[7]), .C(N_174), .D(
        N_201), .Y(prdata_o_1_0_iv_10_0[7]));
    SLE \adc_channel_ch2_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[7]));
    SLE \theta_gen_cmd_step_no_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[11]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_1_tz_0_RNO[10]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_measurements_0_adc_result_ch1_o_10), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_185), .Y(adc_m1_0_a2_7_1));
    CFG4 #( .INIT(16'hFFC8) )  \prdata_o_1_0_iv_10_2[4]  (.A(
        adc_N_5_mux), .B(N_174), .C(prdata_o_1_0_iv_10_1_tz_0[4]), .D(
        prdata_o_1_0_iv_10_0[4]), .Y(prdata_o_1_0_iv_10_2[4]));
    CFG4 #( .INIT(16'h335F) )  \prdata_o_1_0_iv_10_1_1[9]  (.A(
        FOC_TRANSFORMS_0_id_o_9), .B(ADC_SCALING_0_ib_adc_o_9), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        prdata_o_1_0_iv_10_1_1[9]));
    SLE \id_ref_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[3]));
    SLE \adc_control_reg_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_control_reg_val_o[2]));
    SLE \adc_channel_ch3_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[0]));
    CFG4 #( .INIT(16'h0080) )  theta_gen_cmd_step_no_o_1_sqmuxa_0_a2 (
        .A(N_205), .B(N_204), .C(N_178), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(
        theta_gen_cmd_step_no_o_1_sqmuxa));
    SLE \idq_pi_ki_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[16]));
    SLE \adc_channel_ch3_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[11]));
    SLE \theta_gen_rate_limit_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[10]));
    SLE \theta_gen_cmd_step_no_o[18]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[18]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[18]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_11_0[1]  (.A(
        prdata_o_1_iv_0_0[1]), .B(
        STEPPER_THETA_0_theta_output_o_m_1[1]), .C(N_201), .D(
        prdata_o201_0_a2_0_0), .Y(prdata_o_1_iv_11_0_Z[1]));
    SLE \adc_oc_thresh_o[13]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[13]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[13]));
    SLE \adc_channel_ch0_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[9]));
    SLE \adc_channel_ch2_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[13]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_iv_6_RNO[15]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_15), .Y(ADC_SCALING_0_ib_adc_o_m[15]));
    CFG2 #( .INIT(4'h4) )  \READ_DECODE_PROC.prdata_o200_0_a2_0  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(N_180));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_0_iv_1_0[8]  (.A(
        adc_interface_0_result_ch2_o_8), .B(
        adc_measurements_0_adc_result_ch3_o_8), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1_0[8]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_10_0[4]  (.A(
        prdata_o_1_0_iv_1_0[4]), .B(prdata_o_1_0_iv_0_0[4]), .C(
        prdata_o201_0_a2_0_0), .D(N_201), .Y(prdata_o_1_0_iv_10_0[4]));
    SLE \adc_channel_ch2_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[10]));
    CFG4 #( .INIT(16'hFFC8) )  \prdata_o_1_0_iv_10_2[8]  (.A(
        adc_N_5_mux_3), .B(N_174), .C(prdata_o_1_0_iv_10_1_tz_0[8]), 
        .D(prdata_o_1_0_iv_10_0[8]), .Y(prdata_o_1_0_iv_10_2[8]));
    CFG2 #( .INIT(4'h4) )  \prdata_o_1_0_iv_0_o2_0_RNO_2[18]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .Y(prdata_m6_0));
    SLE \adc_channel_ch1_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[14]));
    CFG3 #( .INIT(8'hCA) )  \prdata_o_1_0_iv_1_tz[9]  (.A(
        STEPPER_THETA_1_step_count_o_9), .B(
        STEPPER_THETA_0_theta_output_o[9]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_1_tz[9])
        );
    SLE \idq_pi_kp_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[7]));
    SLE \idq_pi_ki_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[4]));
    SLE \theta_gen_rate_limit_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[0]));
    SLE \theta_gen_rate_limit_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[3]));
    CFG4 #( .INIT(16'hCC80) )  \prdata_o_1_iv_11_4[0]  (.A(N_185), .B(
        N_193), .C(FOC_TRANSFORMS_0_iq_o_0), .D(
        FOC_TRANSFORMS_0_id_o_m_out_0), .Y(prdata_o_1_iv_11_4[0]));
    SLE \idq_pi_kp_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[5]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_7_cZ[14]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_14), .C(
        prdata_o_1_0_iv_7_0[14]), .D(prdata_o_1_0_iv_7_1[14]), .Y(
        prdata_o_1_0_iv_7[14]));
    CFG2 #( .INIT(4'h1) )  adc_channel_ch3_o_1_sqmuxa_0_a2_5 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .Y(N_171));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_0_iv_0_tz[6]  (.A(
        adc_measurements_0_adc_result_ch3_o_6), .B(
        adc_interface_0_result_ch2_o_6), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_0_iv_0_tz[6])
        );
    SLE \pwm_period_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[2]));
    CFG4 #( .INIT(16'hFEEE) )  \prdata_o_1_0_iv_6_cZ[15]  (.A(
        ADC_SCALING_0_ib_adc_o_m[15]), .B(prdata_o_1_0_iv_6_0[15]), .C(
        FOC_TRANSFORMS_0_iq_o_15), .D(prdata_o191), .Y(
        prdata_o_1_0_iv_6[15]));
    SLE \adc_scale_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[17]));
    SLE \theta_gen_slew_count_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[6]));
    SLE \pwm_period_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[7]));
    CFG2 #( .INIT(4'h4) )  \prdata_o_1_0_iv_7_1_RNO[12]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        ADC_SCALING_0_ia_adc_o[12]), .Y(ADC_SCALING_0_ia_adc_o_m_0[12])
        );
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_7_1[12]  (.A(N_187), 
        .B(prdata_o_1_iv_12_0_0[3]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[12]), .D(
        ADC_SCALING_0_ia_adc_o_m_0[12]), .Y(prdata_o_1_0_iv_7_1[12]));
    CFG3 #( .INIT(8'h80) )  start_motor_o_1_sqmuxa_0_a2 (.A(N_226), .B(
        N_176), .C(MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(
        start_motor_o_1_sqmuxa));
    SLE \idq_pi_kp_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[16]));
    SLE \adc_channel_ch0_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[13]));
    SLE \idq_pi_kp_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[9]));
    SLE stop_motor_o (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(stop_motor_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_stop_motor_o));
    SLE \adc_oc_thresh_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[7]));
    SLE \adc_channel_ch2_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[5]));
    SLE \theta_gen_rate_limit_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[5]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_0_RNO[7]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        FOC_TRANSFORMS_0_iq_o_7), .C(N_185), .D(N_176), .Y(
        FOC_m2_0_a2_1));
    SLE \adc_oc_thresh_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[4]));
    CFG3 #( .INIT(8'h80) )  
        \READ_DECODE_PROC.prdata_o197_0_a2_0_a2_0_0  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[4]), .Y(prdata_o197_0_a2_0_a2_0)
        );
    SLE \pwm_delay_time_val_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[16]));
    SLE \idq_pi_ki_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[12]));
    SLE \adc_channel_ch0_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[10]));
    SLE \pwm_period_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[5]));
    CFG4 #( .INIT(16'h2000) )  
        \READ_DECODE_PROC.prdata_o200_0_a2_0_RNIS6PD1  (.A(N_180), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .C(N_174), .D(
        prdata_o197_0_a2_0_a2_0_out), .Y(prdata_o_1_iv_12_1[3]));
    SLE \sqmng_dv_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[3]));
    SLE \pwm_period_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11])
        , .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[11]));
    SLE \theta_gen_slew_count_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[13]));
    SLE \pwm_dead_time_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[3]));
    CFG2 #( .INIT(4'h8) )  theta_gen_mode_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_178), .Y(N_182));
    CFG3 #( .INIT(8'h80) )  adc_oc_thresh_o_1_sqmuxa_0_a2 (.A(N_198), 
        .B(N_182), .C(N_174), .Y(adc_oc_thresh_o_1_sqmuxa));
    SLE \theta_gen_cmd_step_no_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[16]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[16]));
    SLE \pwm_delay_time_val_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[17]));
    CFG3 #( .INIT(8'hF7) )  prdata_o_1_iv_11_3_N_6L10 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        prdata_o197_0_a2_0_a2_0_out), .C(prdata_o_1_iv_11_3_N_6L10_1_Z)
        , .Y(prdata_o_1_iv_11_3_N_6L10_Z));
    SLE \pwm_dead_time_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[4]));
    SLE \id_ref_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[12]));
    SLE \id_ref_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[8]));
    CFG4 #( .INIT(16'hF8F0) )  \prdata_o_1_0_iv_6_RNO[13]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        ADC_SCALING_0_ib_adc_o_13), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[13]), .D(N_187), .Y(
        prdata_o_1_0_iv_6_0[13]));
    SLE \adc_channel_ch1_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[6]));
    SLE \sqmng_dv_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[10]));
    SLE \pwm_period_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[1]));
    SLE \idq_pi_ki_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[2]));
    SLE \idq_pi_ki_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[9]));
    SLE \adc_oc_thresh_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[11]));
    SLE \adc_channel_ch3_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[3]));
    SLE \theta_gen_slew_count_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_slew_count_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_slew_count_o[4]));
    SLE \sqmng_dv_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[9]));
    SLE \id_ref_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[9]));
    SLE \sqmng_dv_o[4]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[4]));
    CFG2 #( .INIT(4'h8) )  stop_motor_o_1_sqmuxa_0_a2_0_RNIDP1S1 (.A(
        prdata_o_1_iv_12_0_0[3]), .B(
        SPEED_ID_IQ_PI_1_id_pi_output_o[0]), .Y(
        SPEED_ID_IQ_PI_1_id_pi_output_o_m[0]));
    SLE \adc_channel_ch2_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[15]));
    SLE \pwm_delay_time_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[5]));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_0_iv_2_m3_0_i_m2[11]  (.A(
        adc_measurements_0_adc_result_ch3_o_11), .B(
        adc_interface_0_result_ch2_o_11), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_107));
    SLE \idq_pi_kp_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[12]));
    SLE \sqmng_dv_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[11]));
    CFG4 #( .INIT(16'h00D1) )  prdata_o_1_iv_11_3_N_7L12 (.A(
        prdata_o_1_iv_11_3_N_5L8_Z), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .C(N_194), .D(
        prdata_o_1_iv_11_3_N_7L12_1_Z), .Y(prdata_o_1_iv_11_3_N_7L12_Z)
        );
    CFG4 #( .INIT(16'h8000) )  \READ_DECODE_PROC.prdata_o190_0_a2_0  (
        .A(MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(N_176), .C(N_172), 
        .D(adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .Y(N_193));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_iv_0[1]  (.A(
        adc_interface_0_result_ch2_o_1), .B(
        adc_measurements_0_adc_result_ch3_o_1), .C(N_184), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_o_1_iv_0_0[1]));
    CFG3 #( .INIT(8'h80) )  idq_pi_ki_o_1_sqmuxa_0_a2 (.A(N_201), .B(
        N_198), .C(N_182), .Y(idq_pi_ki_o_1_sqmuxa));
    SLE \adc_channel_ch3_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch3_o[14]));
    CFG2 #( .INIT(4'h4) )  \prdata_o_1_0_iv_7_1_RNO[16]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        ADC_SCALING_0_ia_adc_o[16]), .Y(prdata_o_1_0_iv_7_1_0[16]));
    SLE \id_ref_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[15]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[15]));
    SLE \pwm_period_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[8]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[8]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_7_0[16]  (.A(
        FOC_TRANSFORMS_1_valpha_o_16), .B(FOC_TRANSFORMS_0_vbeta_o_16), 
        .C(prdata_o_1_iv_12_1[3]), .D(prdata_o_1_iv_12_0_2[3]), .Y(
        prdata_o_1_0_iv_7_0[16]));
    CFG4 #( .INIT(16'h0004) )  idq_pi_kp_o_0_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[0]), .B(
        idq_pi_kp_o_0_sqmuxa_0_a2_0_1), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[1]), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[7]), .Y(N_201));
    CFG4 #( .INIT(16'hECCC) )  \prdata_o_1_iv_11_1[3]  (.A(N_2787), .B(
        prdata_o_1_iv_11_0_Z[3]), .C(prdata_o200_2), .D(
        SEQ_CONTROLLER_1_state_o_0_m_0[3]), .Y(prdata_o_1_iv_11_1_Z[3])
        );
    CFG2 #( .INIT(4'h8) )  \prdata_o_1_0_iv_0_a2_0_0[18]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(
        STEPPER_THETA_0_theta_output_o[17]), .Y(
        prdata_o_1_0_iv_0_a2_0_0[18]));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_0_iv_0_0_o2_2_1_RNO[18]  (
        .A(SPEED_ID_IQ_PI_1_id_pi_output_o[17]), .B(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17]), .C(N_183), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(prdata_m2_e_0));
    SLE \adc_control_reg_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_control_reg_val_o[4]));
    SLE \idq_pi_ki_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[7]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_iv_12_cZ[3]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[3]), .B(
        FOC_TRANSFORMS_1_valpha_o_3), .C(prdata_o_1_iv_12_0[3]), .D(
        prdata_o_1_iv_12_1[3]), .Y(prdata_o_1_iv_12[3]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_10_cZ[4]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_4), .C(
        prdata_o_1_0_iv_10_2[4]), .D(prdata_o_1_0_iv_10_3[4]), .Y(
        prdata_o_1_0_iv_10[4]));
    CFG3 #( .INIT(8'h80) )  \READ_DECODE_PROC.prdata_o199_0_a2_0_a2_0  
        (.A(N_184), .B(N_172), .C(idq_pi_kp_o_0_sqmuxa_0_a2_0_1), .Y(
        N_233));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_iv_11_4_RNO_1[1]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[11]), .B(
        adc_interface_0_result_ch0_o_1), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(prdata_m2_i_a3_1_0));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_6_cZ[16]  (.A(
        FOC_TRANSFORMS_0_iq_o_16), .B(prdata_o191), .C(
        prdata_o_1_0_iv_0[16]), .D(prdata_o_1_0_iv_6_0[16]), .Y(
        prdata_o_1_0_iv_6[16]));
    CFG3 #( .INIT(8'hAC) )  \prdata_o_1_0_iv_0_m2[11]  (.A(
        ADC_SCALING_0_ib_adc_o_11), .B(ADC_SCALING_0_ia_adc_o[11]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .Y(N_104));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_7_0[15]  (.A(
        FOC_TRANSFORMS_1_valpha_o_15), .B(FOC_TRANSFORMS_0_vbeta_o_15), 
        .C(prdata_o_1_iv_12_1[3]), .D(prdata_o_1_iv_12_0_2[3]), .Y(
        prdata_o_1_0_iv_7_0[15]));
    CFG4 #( .INIT(16'hFEEE) )  \prdata_o_1_0_iv_6_cZ[12]  (.A(
        prdata_o_1_0_iv_6_0[12]), .B(ADC_SCALING_0_ib_adc_o_m[12]), .C(
        FOC_TRANSFORMS_0_iq_o_12), .D(prdata_o191), .Y(
        prdata_o_1_0_iv_6[12]));
    SLE \adc_channel_ch2_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[0]));
    SLE \id_ref_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[7]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_11_RNO[9]  (.A(
        prdata_o197_0_a2_0_a2_0_out), .B(N_174), .C(
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9]), .D(prdata_o195_0_a2_0), 
        .Y(SPEED_ID_IQ_PI_1_iq_pi_output_o_m[9]));
    SLE \adc_channel_ch0_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch0_o[15]));
    SLE \pwm_delay_time_val_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[9]));
    CFG4 #( .INIT(16'hFEEE) )  \prdata_o_1_0_iv_6_cZ[14]  (.A(
        ADC_SCALING_0_ib_adc_o_m[14]), .B(prdata_o_1_0_iv_6_0[14]), .C(
        FOC_TRANSFORMS_0_iq_o_14), .D(prdata_o191), .Y(
        prdata_o_1_0_iv_6[14]));
    SLE \adc_oc_thresh_o[3]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_oc_thresh_o[3]));
    SLE \adc_channel_ch1_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[5]));
    SLE \pwm_delay_time_val_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_delay_time_val_o[12]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_10_2_RNO[10]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[5]), .B(
        adc_interface_0_result_ch0_o_10), .C(
        prdata_o197_0_a2_0_a2_0_out), .D(N_180), .Y(
        prdata_o_1_0_iv_10_2_RNO[10]));
    SLE \idq_pi_ki_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[10]));
    SLE \sqmng_dv_o[17]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[17]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[17]));
    CFG2 #( .INIT(4'h8) )  adc_channel_ch3_o_1_sqmuxa_0_a2_2 (.A(N_178)
        , .B(N_180), .Y(N_232));
    CFG4 #( .INIT(16'h8000) )  pwm_delay_time_val_o_1_sqmuxa_0_a2 (.A(
        N_231), .B(N_182), .C(N_174), .D(
        MC_System_0_AMBA_SLAVE_1_PADDR[3]), .Y(
        pwm_delay_time_val_o_1_sqmuxa));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_10_2[7]  (.A(
        prdata_o_1_0_iv_1_tz[7]), .B(N_194), .C(
        prdata_o_1_0_iv_10_3[7]), .D(prdata_o_1_0_iv_10_0[7]), .Y(
        prdata_o_1_0_iv_10_2[7]));
    CFG4 #( .INIT(16'h0100) )  adc_channel_ch3_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[6]), .B(
        MC_System_0_AMBA_SLAVE_1_PADDR[10]), .C(
        MC_System_0_AMBA_SLAVE_1_PADDR[8]), .D(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_1_Z), .Y(N_174));
    SLE \id_ref_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(id_ref_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_id_ref_val_o[16]));
    SLE \adc_scale_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[6]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[6]));
    SLE \pwm_dead_time_val_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[13]));
    SLE \sqmng_dv_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[16]));
    SLE \pwm_period_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[16])
        , .CLK(MC_System_0_FAB_CCC_GL1), .EN(pwm_period_val_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_period_val_o[16]));
    SLE \idq_pi_kp_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[2]));
    SLE \idq_pi_kp_o[1]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[1]));
    CFG3 #( .INIT(8'h80) )  theta_gen_mode_o_1_sqmuxa_0_a2 (.A(N_205), 
        .B(N_204), .C(N_182), .Y(theta_gen_mode_o_1_sqmuxa));
    SLE \theta_gen_cmd_step_no_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[8]));
    SLE \sqmng_dv_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[0]));
    CFG4 #( .INIT(16'hC840) )  \prdata_o_1_0_iv_0_o2_0_RNO_0[18]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(prdata_m6_0), .C(
        FOC_TRANSFORMS_1_valpha_o_17), .D(FOC_TRANSFORMS_0_vbeta_o_17), 
        .Y(prdata_m6_1));
    CFG3 #( .INIT(8'h80) )  \READ_DECODE_PROC.prdata_o201_0_a2_0_0  (
        .A(N_181), .B(N_171), .C(N_172), .Y(prdata_o201_0_a2_0_0));
    SLE \adc_scale_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[14]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[14]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_6_0[12]  (.A(
        prdata_o_1_0_iv_1[12]), .B(SPEED_m1_0_a2_3_1), .C(N_174), .D(
        prdata_o201_0_a2_0_0), .Y(prdata_o_1_0_iv_6_0[12]));
    SLE \pwm_dead_time_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_pwm_dead_time_val_o[0]));
    SLE \idq_pi_kp_o[10]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[10]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_kp_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_kp_o[10]));
    SLE \idq_pi_ki_o[5]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[5]));
    SLE \idq_pi_ki_o[11]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[11]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_idq_pi_ki_o[11]));
    SLE \sqmng_dv_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[7]));
    SLE \sqmng_dv_o[12]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[12]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[12]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_10_cZ[5]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_5), .C(
        prdata_o_1_0_iv_10_2[5]), .D(prdata_o_1_0_iv_10_3[5]), .Y(
        prdata_o_1_0_iv_10[5]));
    SLE \theta_gen_cmd_step_no_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[17]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[17]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_iv_12_cZ[1]  (.A(
        SPEED_ID_IQ_PI_1_iq_pi_output_o_m[1]), .B(
        FOC_TRANSFORMS_0_vbeta_o_1), .C(prdata_o_1_iv_12_0[1]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_iv_12[1]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_7_1[16]  (.A(N_187), 
        .B(prdata_o_1_iv_12_0_0[3]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[16]), .D(
        prdata_o_1_0_iv_7_1_0[16]), .Y(prdata_o_1_0_iv_7_1[16]));
    CFG4 #( .INIT(16'hC480) )  \prdata_o_1_0_iv_10_3[5]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_5), .D(ADC_SCALING_0_ia_adc_o[5]), .Y(
        prdata_o_1_0_iv_10_3[5]));
    SLE \theta_gen_cmd_step_no_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_cmd_step_no_o_1_sqmuxa)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_cmd_step_no_o_0[4]));
    SLE \theta_gen_rate_limit_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(theta_gen_rate_limit_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_theta_gen_rate_limit_o[2]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_11_0[7]  (.A(
        SPEED_ID_IQ_PI_1_id_pi_output_o[7]), .B(
        FOC_TRANSFORMS_0_vbeta_o_7), .C(prdata_o_1_iv_12_0_0[3]), .D(
        prdata_o_1_iv_12_0_2[3]), .Y(prdata_o_1_0_iv_11_0[7]));
    SLE \adc_channel_ch1_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[13]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_7_1[15]  (.A(N_187), 
        .B(prdata_o_1_iv_12_0_0[3]), .C(
        SPEED_ID_IQ_PI_1_id_pi_output_o[15]), .D(
        ADC_SCALING_0_ia_adc_o_m_0[15]), .Y(prdata_o_1_0_iv_7_1[15]));
    SLE \adc_scale_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[9]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[9]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_iv_6_RNO[12]  (.A(
        MC_System_0_AMBA_SLAVE_1_PADDR[2]), .B(N_187), .C(
        ADC_SCALING_0_ib_adc_o_12), .Y(ADC_SCALING_0_ib_adc_o_m[12]));
    SLE \sqmng_dv_o[2]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(sqmng_dv_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_if_st_0_sqmng_dv_o[2]));
    SLE \adc_channel_ch2_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch2_o[12]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_10_0[5]  (.A(
        prdata_o_1_0_iv_1_0[5]), .B(prdata_o_1_0_iv_0_0[5]), .C(
        prdata_o201_0_a2_0_0), .D(N_201), .Y(prdata_o_1_0_iv_10_0[5]));
    SLE \adc_scale_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[7]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_scale_val_o[7]));
    SLE \adc_channel_ch1_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_1_PWDATA[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[10]));
    SLE \adc_channel_ch1_o[0]  (.D(MC_System_0_AMBA_SLAVE_1_PWDATA[0]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_if_st_0_adc_channel_ch1_o[0]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_7_cZ[15]  (.A(
        prdata_o190), .B(FOC_TRANSFORMS_0_id_o_15), .C(
        prdata_o_1_0_iv_7_0[15]), .D(prdata_o_1_0_iv_7_1[15]), .Y(
        prdata_o_1_0_iv_7[15]));
    
endmodule


module accumulator_st_18s(
       s_stepcnt_buff,
       s_theta_out_buff_17,
       s_theta_out_buff_0,
       s_theta_out_buff_1,
       s_theta_out_buff_2,
       s_theta_out_buff_3,
       s_theta_out_buff_4,
       s_theta_out_buff_5,
       s_theta_out_buff_6,
       s_theta_out_buff_7,
       s_theta_out_buff_8,
       s_theta_out_buff_9,
       s_count_buff,
       s_count_4,
       rate_limit_i,
       s_theta_output,
       s_step_cnt,
       s_count,
       reset_i,
       sys_clk_i,
       un1_s_count_buff_cry_17_RNIIOFJ_Y,
       s_count_4_cry_0_cy,
       s_count_4_cry_16,
       N_158,
       un1_cmd_step_no_i_1_i_0,
       s_theta_output14,
       s_theta_output_6_0_cry_9,
       N_159,
       N_160,
       N_161,
       N_162,
       N_163,
       s_theta_output_6_0_cry_16,
       N_164,
       clear_buffer_i
    );
output [23:0] s_stepcnt_buff;
output s_theta_out_buff_17;
output s_theta_out_buff_0;
output s_theta_out_buff_1;
output s_theta_out_buff_2;
output s_theta_out_buff_3;
output s_theta_out_buff_4;
output s_theta_out_buff_5;
output s_theta_out_buff_6;
output s_theta_out_buff_7;
output s_theta_out_buff_8;
output s_theta_out_buff_9;
output [17:0] s_count_buff;
output [16:0] s_count_4;
input  [16:10] rate_limit_i;
input  [17:0] s_theta_output;
input  [23:0] s_step_cnt;
input  [17:0] s_count;
input  reset_i;
input  sys_clk_i;
input  un1_s_count_buff_cry_17_RNIIOFJ_Y;
input  s_count_4_cry_0_cy;
output s_count_4_cry_16;
output N_158;
input  un1_cmd_step_no_i_1_i_0;
input  s_theta_output14;
input  s_theta_output_6_0_cry_9;
output N_159;
output N_160;
output N_161;
output N_162;
output N_163;
output s_theta_output_6_0_cry_16;
output N_164;
input  clear_buffer_i;

    wire [23:0] step_count_buff_o_3;
    wire [16:10] s_theta_out_buff;
    wire [17:0] theta_output_buff_o_3;
    wire [17:0] count_buff_o_3;
    wire [0:0] count_buff_o_RNIH1LE1_Y;
    wire [1:1] count_buff_o_RNIHBQ92_Y;
    wire [2:2] count_buff_o_RNIIMV43_Y;
    wire [3:3] count_buff_o_RNIK2504_Y;
    wire [4:4] count_buff_o_RNINFAR4_Y;
    wire [5:5] count_buff_o_RNIRTFM5_Y;
    wire [6:6] count_buff_o_RNI0DLH6_Y;
    wire [7:7] count_buff_o_RNI6TQC7_Y;
    wire [8:8] count_buff_o_RNIDE088_Y;
    wire [9:9] count_buff_o_RNIL0639_Y;
    wire [10:10] count_buff_o_RNI5DR3A_Y;
    wire [11:11] count_buff_o_RNIMQG4B_Y;
    wire [12:12] count_buff_o_RNI8965C_Y;
    wire [13:13] count_buff_o_RNIROR5D_Y;
    wire [14:14] count_buff_o_RNIF9H6E_Y;
    wire [15:15] count_buff_o_RNI4R67F_Y;
    wire [16:16] count_buff_o_RNIQDS7G_Y;
    wire [10:10] theta_output_buff_o_RNIOGUVB_Y;
    wire [11:11] theta_output_buff_o_RNIK5P3D_Y;
    wire [12:12] theta_output_buff_o_RNIISJ7E_Y;
    wire [13:13] theta_output_buff_o_RNIILEBF_Y;
    wire [14:14] theta_output_buff_o_RNIKG9FG_Y;
    wire [15:15] theta_output_buff_o_RNIOD4JH_Y;
    wire [16:16] theta_output_buff_o_RNIUCVMI_Y;
    wire MSC_net_245, MSC_net_246, MSC_net_247, MSC_net_248, 
        MSC_net_249, MSC_net_250, MSC_net_251, MSC_net_252, 
        MSC_net_253, MSC_net_254, MSC_net_255, MSC_net_256, 
        MSC_net_257, MSC_net_258, MSC_net_259, MSC_net_260, 
        MSC_net_261, MSC_net_262, MSC_net_263, MSC_net_264, 
        MSC_net_265, MSC_net_266, MSC_net_267, MSC_net_268;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
Alu930LH4wSgiF+L2u3KeheGN7T3g8pTM//6johMh4ZJN/jXNfaqfkuXuIU+g4a+
1gbtJIW7baIffm2hnnuyV1m8dU6qy6l8rBrf8PCcDsZtWh7AUMQQlwPZC0NHKZoO
oNrOWyLWYyMJI/iKyxzL/ty5aGw4txa9JCROr2eT3mE=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=40390)
`pragma protect data_block
[encoded data, 39744 characters]
S8e7q/LYa2EcwYyHkgwFwA==

`pragma protect end_protected

endmodule


module STEPPER_THETA(
       reset_i,
       sys_clk_i,
       enable_i,
       mode_i,
       clear_buffer_i,
       slew_cnt_i,
       rate_limit_i,
       cmd_step_no_i,
       theta_output_o,
       step_count_o
    );
input  reset_i;
input  sys_clk_i;
input  enable_i;
input  mode_i;
input  clear_buffer_i;
input  [17:0] slew_cnt_i;
input  [17:0] rate_limit_i;
input  [23:0] cmd_step_no_i;
output [17:0] theta_output_o;
output [23:0] step_count_o;

    wire [1:1] un1_s_theta_output18_1_0;
    wire [17:0] s_count;
    wire [17:0] s_theta_out_buff;
    wire [17:0] s_count_buff;
    wire [23:0] s_stepcnt_buff;
    wire [6:0] s_count_1us;
    wire [23:1] \THETA_STEP_COUNT_PROC.s_step_cnt_8 ;
    wire [17:0] \THETA_STEP_COUNT_PROC.s_theta_output_6 ;
    wire [11:0] \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_data_tmp ;
    wire [5:0] s_count_1us_cry;
    wire [6:0] s_count_1us_s;
    wire [17:0] \THETA_STEP_COUNT_PROC.s_count_4 ;
    wire [17:17] \THETA_STEP_COUNT_PROC.s_theta_output_6_RNO_FCO ;
    wire [17:17] \THETA_STEP_COUNT_PROC.s_theta_output_6_RNO_Y ;
    wire [9:9] rate_limit_i_RNIUT3SA_Y;
    wire [8:8] rate_limit_i_RNIK9QQ9_Y;
    wire [7:7] rate_limit_i_RNICNGP8_Y;
    wire [6:6] rate_limit_i_RNI677O7_Y;
    wire [5:5] rate_limit_i_RNI2PTM6_Y;
    wire [4:4] rate_limit_i_RNI0DKL5_Y;
    wire [3:3] rate_limit_i_RNI03BK4_Y;
    wire [2:2] rate_limit_i_RNI2R1J3_Y;
    wire [1:1] rate_limit_i_RNI6LOH2_Y;
    wire [0:0] rate_limit_i_RNICHFG1_Y;
    wire [17:17] s_count_RNO_FCO;
    wire [17:17] s_count_RNO_Y;
    wire [5:5] s_count_1us_RNIOANTA_Y;
    wire [6:6] s_count_1us_RNO_FCO;
    wire [6:6] s_count_1us_RNO_Y;
    wire [4:4] s_count_1us_RNIN9S99_Y;
    wire [3:3] s_count_1us_RNIN91M7_Y;
    wire [2:2] s_count_1us_RNIOA626_Y;
    wire [1:1] s_count_1us_RNIQCBE4_Y;
    wire [0:0] s_count_1us_RNITFGQ2_Y;
    wire MSC_net_299, MSC_net_300, MSC_net_301, 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff , 
        \THETA_STEP_COUNT_PROC.s_theta_output14 , 
        \THETA_STEP_COUNT_PROC.un1_clear_buffer_i_3_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_0_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_1_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_2_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_3_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_4_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_5_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_6_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_7_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_8_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_9_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_10_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_11_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_12_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_13_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_14_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_15_Z , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_16_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_0_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_1_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_2_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_3_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_4_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_5_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_6_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_7_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_8_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_9_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_10_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_11_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_12_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_13_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_14_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_15_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_16_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_17_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_18_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_19_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_20_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_21_Z , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_22_Z , 
        \COUNT_1US_PROC.s_count_1us9lt6 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_0 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_1 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_2 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_3 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_4 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_5 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_6 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_7 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_8 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_9 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_10 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_11 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_12 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_13 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_14 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_15 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_16 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_17 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_18 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_19 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_20 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_21 , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_22 , 
        \THETA_STEP_COUNT_PROC.s_count_4_cry_16 , MSC_net_370, 
        MSC_net_371, MSC_net_372, MSC_net_373, MSC_net_374, 
        MSC_net_375, MSC_net_376, MSC_net_377, MSC_net_378, 
        MSC_net_379, MSC_net_380, MSC_net_381, MSC_net_382, 
        MSC_net_383, MSC_net_384, MSC_net_385, MSC_net_386, 
        MSC_net_387, \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_0 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_1 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_2 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_3 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_4 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_5 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_6 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_7 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_8 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_9 , 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_16 , MSC_net_399, 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_1_i_0 , MSC_net_401, 
        \THETA_STEP_COUNT_PROC.s_theta_output_6_0_cry_0_0_cy , 
        \THETA_STEP_COUNT_PROC.s_count_4_cry_0_cy , MSC_net_404, 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_45_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_45_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_63_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_63_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_57_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_57_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_69_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_69_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_21_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_21_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_39_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_39_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_33_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_33_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_51_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_51_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_27_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_27_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_15_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_15_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_9_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_9_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_1_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_1_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_17_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_17_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_16_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_16_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_15_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_15_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_14_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_14_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_13_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_13_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_12_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_12_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_11_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_11_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_10_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_10_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_9_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_9_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_8_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_8_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_7_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_7_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_6_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_6_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_5_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_5_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_4_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_4_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_3_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_3_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_2_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_2_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_1_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_1_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_0_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_0_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_23_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_23_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_22_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_22_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_21_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_21_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_20_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_20_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_19_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_19_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_18_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_18_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_17_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_17_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_16_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_16_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_15_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_15_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_14_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_14_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_13_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_13_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_12_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_12_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_11_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_11_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_10_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_10_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_9_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_9_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_8_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_8_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_7_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_7_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_6_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_6_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_5_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_5_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_4_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_4_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_3_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_3_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_2_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_2_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_1_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_1_Y , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_0_S , 
        \THETA_STEP_COUNT_PROC.s_theta_output14_cry_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_22_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_s_23_FCO , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_s_23_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_21_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_20_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_19_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_18_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_17_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_16_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_15_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_14_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_13_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_12_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_11_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_10_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_9_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_8_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_7_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_6_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_5_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_4_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_3_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_2_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_1_0_Y , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_0_0_S , 
        \THETA_STEP_COUNT_PROC.s_step_cnt_8_cry_0_0_Y , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_45_RNIKF6F_S , 
        \THETA_STEP_COUNT_PROC.un1_cmd_step_no_i_0_I_45_RNIKF6F_Y , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_17_RNIIOFJ_S , 
        \THETA_STEP_COUNT_PROC.un1_s_count_buff_cry_17_RNIIOFJ_Y , 
        MSC_net_543, MSC_net_544;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
HiuqTvXFdrWC+nbyMldwdJy10gFyn0CsoouSNRJWSpVgEEtb0XLJa6lsIQsMib1V
VWlLIZJcC1GpbITd9AJaRyBcN7XIYq0xe19B+RzZBvtK5f3YP/0aYF/yUNo0h8ch
Yx452JWgDZoiZslqWHZ8wtqyrzgoJJeFGqG4tT3qnaI=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=95185)
`pragma protect data_block
[encoded data, 93696 characters]
/NLvVOteXSBJ9gjOyEnovw==

`pragma protect end_protected

endmodule


module mas_pi_spi_44s_18s_2s_0(
       s_state,
       s_product,
       s_error,
       s_mult1_input_6,
       s_add_cin_5,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       N_124,
       s_error_axb_0_i_0,
       N_122_i_0
    );
input  [2:2] s_state;
output [43:0] s_product;
input  [17:1] s_error;
input  [17:0] s_mult1_input_6;
input  [43:0] s_add_cin_5;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
output N_124;
input  s_error_axb_0_i_0;
input  N_122_i_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire MSC_net_176, MSC_net_177, MSC_net_178;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
H7jTiLu9QePjX3mrfihHHBOCRjCLjtNDYMUTPhOecDXHHJ430R2pTbjJ1mX//oA3
PrwN0ZOSV1/Sy/BNYon3mcRzyUONAGXF5dbqoC0Qozw5sb1qPP0ENXozwreVfAF5
VjP+2MMrciL96ERl9x3dfSA7hLvurNRR3eCAjJ8wI50=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8560)
`pragma protect data_block
[encoded data, 8384 characters]
CvTtwlECIcYEOVdxw0gRKaANSe9MeAdQpGn2hAn2tMY=

`pragma protect end_protected

endmodule


module pi_controller_spi_18s_44s_2s_10s_16s_0_1_2_4_0(
       s_acc_in_0,
       s_acc_out,
       s_output_y,
       id_pi_ref_input_i,
       s_pi_sel,
       id_init_i,
       s_pi_sel_fast,
       iq_pi_kp_i,
       iq_pi_ki_i,
       reset_i,
       sys_clk_i,
       s_done,
       s_en,
       s_pi_sel_1_rep2,
       N_1328,
       s_pi_sel_0_rep1,
       N_1329,
       N_1330,
       N_1331,
       N_1332,
       N_1333,
       N_1334,
       N_1335,
       N_1336,
       N_1337,
       N_1338,
       N_1339,
       N_1340,
       N_1341,
       N_1342,
       N_1343,
       N_1345,
       N_1344,
       s_start,
       s_pi_sel_1_rep1,
       output_y_o6_18
    );
input  [43:0] s_acc_in_0;
output [43:0] s_acc_out;
output [17:0] s_output_y;
input  [17:0] id_pi_ref_input_i;
input  [1:1] s_pi_sel;
input  [17:0] id_init_i;
input  [1:1] s_pi_sel_fast;
input  [17:0] iq_pi_kp_i;
input  [17:0] iq_pi_ki_i;
input  reset_i;
input  sys_clk_i;
output s_done;
input  s_en;
input  s_pi_sel_1_rep2;
input  N_1328;
input  s_pi_sel_0_rep1;
input  N_1329;
input  N_1330;
input  N_1331;
input  N_1332;
input  N_1333;
input  N_1334;
input  N_1335;
input  N_1336;
input  N_1337;
input  N_1338;
input  N_1339;
input  N_1340;
input  N_1341;
input  N_1342;
input  N_1343;
input  N_1345;
input  N_1344;
input  s_start;
input  s_pi_sel_1_rep1;
input  output_y_o6_18;

    wire [34:1] s_piout;
    wire [33:16] s_piout_i;
    wire [43:0] s_acc_in;
    wire [43:0] s_inew;
    wire [43:0] s_product;
    wire [43:10] s_pout;
    wire [17:0] s_i_init_ds;
    wire [4:0] s_state;
    wire [43:0] acc_out_o_5;
    wire [17:0] output_y_o_5;
    wire [0:0] un1_s_diff_v_RNIME7V_S;
    wire [0:0] un1_s_diff_v_RNIME7V_Y;
    wire [17:0] s_init;
    wire [1:1] un1_s_diff_v_RNIF0FU1_Y;
    wire [2:2] un1_s_diff_v_RNIBLMT2_Y;
    wire [3:3] un1_s_diff_v_RNIADUS3_Y;
    wire [4:4] un1_s_diff_v_RNI307S4_Y;
    wire [5:5] un1_s_diff_v_RNIVLFR5_Y;
    wire [6:6] un1_s_diff_v_RNIUEOQ6_Y;
    wire [7:7] un1_s_diff_v_RNI0B1Q7_Y;
    wire [8:8] un1_s_diff_v_RNI5AAP8_Y;
    wire [9:9] un1_s_diff_v_RNIDCJO9_Y;
    wire [10:10] un1_s_diff_v_RNIM27KA_Y;
    wire [11:11] un1_s_diff_v_RNI2SQFB_Y;
    wire [12:12] un1_s_diff_v_RNIHOEBC_Y;
    wire [13:13] un1_s_diff_v_RNI3O27D_Y;
    wire [14:14] un1_s_diff_v_RNIFIN2E_Y;
    wire [15:15] un1_s_diff_v_RNIUFCUE_Y;
    wire [16:16] un1_s_diff_v_RNIGG1QF_Y;
    wire [27:27] s_pout_RNI5KMLG_Y;
    wire [28:28] s_pout_RNISPBHH_Y;
    wire [29:29] s_pout_RNIL11DI_Y;
    wire [30:30] s_pout_RNI73N8J_Y;
    wire [31:31] s_pout_RNIR6D4K_Y;
    wire [32:32] s_pout_RNIHC30L_Y;
    wire [33:33] s_pout_RNI9KPRL_Y;
    wire [34:34] s_pout_RNIQLGNM_Y;
    wire [35:35] s_pout_RNIDP7JN_Y;
    wire [36:36] s_pout_RNI2VUEO_Y;
    wire [37:37] s_pout_RNIP6MAP_Y;
    wire [38:38] s_pout_RNIHFD6Q_Y;
    wire [39:39] s_pout_RNIAP42R_Y;
    wire [40:40] s_pout_RNIRRSTR_Y;
    wire [41:41] s_pout_RNIDVKPS_Y;
    wire [42:42] s_pout_RNI04DLT_Y;
    wire [43:43] s_pout_RNI8FTCV_FCO;
    wire [43:43] s_pout_RNI8FTCV_Y;
    wire [43:43] s_pout_RNIK95HU_Y;
    wire [17:1] s_error;
    wire [43:0] s_add_cin_5;
    wire [42:0] s_iout;
    wire [43:43] acc_out_o_5_b_A;
    wire [17:0] s_mult1_input_6;
    wire MSC_net_688, MSC_net_689, MSC_net_690, MSC_net_691, 
        MSC_net_692, MSC_net_693, MSC_net_694, MSC_net_695, 
        MSC_net_696, MSC_net_697, MSC_net_698, MSC_net_699, 
        MSC_net_700, MSC_net_701, MSC_net_702, MSC_net_703, 
        MSC_net_704, MSC_net_705, MSC_net_706, MSC_net_707, 
        MSC_net_708, MSC_net_709, MSC_net_710, MSC_net_711, 
        MSC_net_712, MSC_net_713, MSC_net_714, MSC_net_715, 
        MSC_net_716, MSC_net_717, MSC_net_718, MSC_net_719, 
        MSC_net_720, MSC_net_721, MSC_net_722, MSC_net_723, 
        MSC_net_724, MSC_net_725, MSC_net_726, MSC_net_727, 
        MSC_net_728, MSC_net_729, MSC_net_730, MSC_net_731, 
        MSC_net_732, MSC_net_733, MSC_net_734, MSC_net_735, 
        MSC_net_736, MSC_net_737, MSC_net_738, MSC_net_739, 
        MSC_net_740, MSC_net_741, MSC_net_742, MSC_net_743, 
        MSC_net_744, MSC_net_745, MSC_net_746, MSC_net_747, 
        MSC_net_748, MSC_net_749, MSC_net_750, MSC_net_751, 
        MSC_net_752, MSC_net_753, MSC_net_754, MSC_net_755, 
        MSC_net_756, MSC_net_757, MSC_net_758, MSC_net_759, 
        MSC_net_760, MSC_net_761, MSC_net_762, MSC_net_763, 
        MSC_net_764, MSC_net_765, MSC_net_766, MSC_net_767, 
        MSC_net_768, MSC_net_769, MSC_net_770, MSC_net_771, 
        MSC_net_772, MSC_net_773, MSC_net_774, MSC_net_775, 
        MSC_net_776, MSC_net_777, MSC_net_778, MSC_net_779, 
        MSC_net_780, MSC_net_781, MSC_net_782, MSC_net_783, 
        MSC_net_784, MSC_net_785, MSC_net_786, MSC_net_787, 
        MSC_net_788, MSC_net_789, MSC_net_790, MSC_net_791, 
        MSC_net_792, MSC_net_793, MSC_net_794, MSC_net_795, 
        MSC_net_796, MSC_net_797, MSC_net_798, MSC_net_799, 
        MSC_net_800, MSC_net_801, MSC_net_802, MSC_net_803, 
        MSC_net_804, MSC_net_805, MSC_net_806, MSC_net_807, 
        MSC_net_808, MSC_net_809, MSC_net_810, MSC_net_811, 
        MSC_net_812, MSC_net_813, MSC_net_814, MSC_net_815, 
        MSC_net_816, MSC_net_817, MSC_net_818, MSC_net_819, 
        MSC_net_820, MSC_net_821, MSC_net_822, MSC_net_823, 
        MSC_net_824, MSC_net_825, MSC_net_826, MSC_net_827, 
        MSC_net_828, MSC_net_829, MSC_net_830, MSC_net_831, 
        MSC_net_832, MSC_net_833, MSC_net_834, MSC_net_835, 
        MSC_net_836, MSC_net_837, MSC_net_838, MSC_net_839, 
        MSC_net_840, MSC_net_841, MSC_net_842, MSC_net_843, 
        MSC_net_844, MSC_net_845, MSC_net_846, MSC_net_847, 
        MSC_net_848, MSC_net_849, MSC_net_850, MSC_net_851, 
        MSC_net_852, MSC_net_853, MSC_net_854, MSC_net_855, 
        MSC_net_856, MSC_net_857, MSC_net_858, MSC_net_859, 
        MSC_net_860, MSC_net_861, MSC_net_862, MSC_net_863, 
        MSC_net_864, MSC_net_865, MSC_net_866, MSC_net_867, 
        MSC_net_868, MSC_net_869, MSC_net_870, MSC_net_871, 
        MSC_net_872, MSC_net_873, MSC_net_874, MSC_net_875, 
        MSC_net_876, MSC_net_877, MSC_net_878, MSC_net_879, 
        MSC_net_880, MSC_net_881, MSC_net_882, MSC_net_883, 
        MSC_net_884, MSC_net_885, MSC_net_886, MSC_net_887, 
        MSC_net_888, MSC_net_889, MSC_net_890, MSC_net_891, 
        MSC_net_892, MSC_net_893, MSC_net_894, MSC_net_895, 
        MSC_net_896, MSC_net_897, MSC_net_898, MSC_net_899, 
        MSC_net_900, MSC_net_901, MSC_net_902, MSC_net_903, 
        MSC_net_904, MSC_net_905, MSC_net_906, MSC_net_907, 
        MSC_net_908, MSC_net_909, MSC_net_910, MSC_net_911, 
        MSC_net_912, MSC_net_913, MSC_net_914, MSC_net_915, 
        MSC_net_916, MSC_net_917, MSC_net_918, MSC_net_919, 
        MSC_net_920, MSC_net_921, MSC_net_922, MSC_net_923, 
        MSC_net_924, MSC_net_925, MSC_net_926, MSC_net_927, 
        MSC_net_928, MSC_net_929, MSC_net_930, MSC_net_931, 
        MSC_net_932, MSC_net_933, MSC_net_934, MSC_net_935, 
        MSC_net_936, MSC_net_937, MSC_net_938, MSC_net_939, 
        MSC_net_940, MSC_net_941, MSC_net_942, MSC_net_943, 
        MSC_net_944, MSC_net_945, MSC_net_946, MSC_net_947, 
        MSC_net_948, MSC_net_949, MSC_net_950, MSC_net_951, 
        MSC_net_952, MSC_net_953, MSC_net_954, MSC_net_955, 
        MSC_net_956, MSC_net_957, MSC_net_958, MSC_net_959, 
        MSC_net_960, MSC_net_961, MSC_net_962, MSC_net_963, 
        MSC_net_964, MSC_net_965, MSC_net_966, MSC_net_967, 
        MSC_net_968, MSC_net_969, MSC_net_970, MSC_net_971, 
        MSC_net_972, MSC_net_973, MSC_net_974, MSC_net_975, 
        MSC_net_976, MSC_net_977, MSC_net_978, MSC_net_979, 
        MSC_net_980, MSC_net_981, MSC_net_982, MSC_net_983, 
        MSC_net_984, MSC_net_985, MSC_net_986, MSC_net_987, 
        MSC_net_988, MSC_net_989, MSC_net_990, MSC_net_991, 
        MSC_net_992, MSC_net_993, MSC_net_994, MSC_net_995, 
        MSC_net_996, MSC_net_997, MSC_net_998, MSC_net_999, 
        MSC_net_1000, MSC_net_1001, MSC_net_1002, MSC_net_1003, 
        MSC_net_1004, MSC_net_1005, MSC_net_1006, MSC_net_1007, 
        MSC_net_1008, MSC_net_1009, MSC_net_1010, MSC_net_1011, 
        MSC_net_1012, MSC_net_1013, MSC_net_1014, MSC_net_1015, 
        MSC_net_1016, MSC_net_1017, MSC_net_1018, MSC_net_1019, 
        MSC_net_1020, MSC_net_1021, MSC_net_1022, MSC_net_1023, 
        MSC_net_1024, MSC_net_1025, MSC_net_1026, MSC_net_1027, 
        MSC_net_1028, MSC_net_1029, MSC_net_1030, MSC_net_1031, 
        MSC_net_1032, MSC_net_1033, MSC_net_1034, MSC_net_1035, 
        MSC_net_1036, MSC_net_1037, MSC_net_1038, MSC_net_1039, 
        MSC_net_1040, MSC_net_1041, MSC_net_1042, MSC_net_1043, 
        MSC_net_1044, MSC_net_1045, MSC_net_1046, MSC_net_1047, 
        MSC_net_1048, MSC_net_1049, MSC_net_1050, MSC_net_1051, 
        MSC_net_1052, MSC_net_1053, MSC_net_1054, MSC_net_1055, 
        MSC_net_1056, MSC_net_1057, MSC_net_1058, MSC_net_1059, 
        MSC_net_1060, MSC_net_1061, MSC_net_1062;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
EJXwKxj+ttkS54wV5NhdsqYIz5kP3hjcxrnV5QxWi/+qLm2yPbRTy7jYAbnGkhnC
/kypTI4Chb2IWDl50V9SbDYulSBE9HEZmJWllPoizDjoYAfEyz+NdErUEJEVvp/R
ZpgPpeTDZF+pAu64vZMIABUh/pJ/lMfhGCnm/aZOXVw=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=142220)
`pragma protect data_block
[encoded data, 140032 characters]

`pragma protect end_protected

endmodule


module pi_scheduler_spi_18s_44s_0(
       s_pi_sel_1,
       iq_pi_output_o,
       id_pi_output_o,
       s_pi_sel_fast_1,
       s_output_y,
       s_acc_out,
       id_pi_act_input_i,
       iq_pi_act_input_i,
       s_acc_in,
       iq_pi_start_i,
       reset_i,
       sys_clk_i,
       id_pi_done_o,
       s_done,
       iq_pi_done_o,
       s_start,
       s_pi_sel_1_rep1,
       s_pi_sel_1_rep2,
       s_pi_sel_0_rep1,
       clear_buffer_i,
       output_y_o6_18,
       id_pi_start_i,
       N_1328,
       N_1329,
       N_1330,
       N_1331,
       N_1332,
       N_1333,
       N_1334,
       N_1335,
       N_1336,
       N_1337,
       N_1338,
       N_1339,
       N_1340,
       N_1341,
       N_1342,
       N_1343,
       N_1344,
       N_1345,
       idq_en_i,
       s_en
    );
output s_pi_sel_1;
output [17:0] iq_pi_output_o;
output [17:0] id_pi_output_o;
output s_pi_sel_fast_1;
input  [17:0] s_output_y;
input  [43:0] s_acc_out;
input  [17:0] id_pi_act_input_i;
input  [17:0] iq_pi_act_input_i;
output [43:0] s_acc_in;
input  iq_pi_start_i;
input  reset_i;
input  sys_clk_i;
output id_pi_done_o;
input  s_done;
output iq_pi_done_o;
output s_start;
output s_pi_sel_1_rep1;
output s_pi_sel_1_rep2;
output s_pi_sel_0_rep1;
input  clear_buffer_i;
output output_y_o6_18;
input  id_pi_start_i;
output N_1328;
output N_1329;
output N_1330;
output N_1331;
output N_1332;
output N_1333;
output N_1334;
output N_1335;
output N_1336;
output N_1337;
output N_1338;
output N_1339;
output N_1340;
output N_1341;
output N_1342;
output N_1343;
output N_1344;
output N_1345;
input  idq_en_i;
output s_en;

    wire [0:0] s_pi_sel;
    wire [1:0] s_pi_sel_dly;
    wire [43:0] s_speed_pi_acc_in;
    wire [43:0] s_speed_pi_acc_in_4;
    wire [43:0] s_iq_acc_in;
    wire [43:0] s_id_acc_in;
    wire [17:0] speed_pi_output_y_o_5;
    wire [0:0] s_pi_sel_fast;
    wire MSC_net_411, MSC_net_412, MSC_net_413, MSC_net_414, 
        MSC_net_415, MSC_net_416, MSC_net_417, MSC_net_418, 
        MSC_net_419, MSC_net_420, MSC_net_421, MSC_net_422, 
        MSC_net_423, MSC_net_424, MSC_net_425, MSC_net_426, 
        MSC_net_427, MSC_net_428, MSC_net_429, MSC_net_430, 
        MSC_net_431, MSC_net_432, MSC_net_433, MSC_net_434, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, MSC_net_442, 
        MSC_net_443, MSC_net_444, MSC_net_445, MSC_net_446, 
        MSC_net_447, MSC_net_448, MSC_net_449, MSC_net_450, 
        MSC_net_451, MSC_net_452, MSC_net_453, MSC_net_454, 
        MSC_net_455, MSC_net_456, MSC_net_457, MSC_net_458, 
        MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, MSC_net_470, 
        MSC_net_471, MSC_net_472, MSC_net_473, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
cD3x28XPjPKYsl2jsnFNv8b0T1Wjqjh2CExSiYxRIFq4Pj6dWJKGt8g8T1nDOx3W
u3MQScRI6eNkqJ75WU7vSYLdjNw0VRDA3CQ71/1+xTxSOgDHpy91ZLOWvbXkhI+i
Tyylh3hvhm0dyjqxFDhyA9duDMxHpuf2hBbakLqF/9Y=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=93255)
`pragma protect data_block
[encoded data, 91776 characters]
UJ4rZORdMeI+5pZ59bpDXeOUncygB82ZLgoNV8OXojY=

`pragma protect end_protected

endmodule


module SPEED_ID_IQ_PI_2s_44s_0(
       reset_i,
       sys_clk_i,
       clear_buffer_i,
       speed_en_i,
       idq_en_i,
       speed_pi_start_i,
       id_pi_start_i,
       iq_pi_start_i,
       speed_init_i,
       id_init_i,
       iq_init_i,
       speed_pi_ref_input_i,
       speed_pi_act_input_i,
       speed_pi_kp_i,
       speed_pi_ki_i,
       speed_pi_ymax_i,
       speed_pi_ymin_i,
       id_pi_ref_input_i,
       id_pi_act_input_i,
       id_pi_kp_i,
       id_pi_ki_i,
       idq_pi_ymax_i,
       idq_pi_ymin_i,
       iq_pi_ref_input_i,
       iq_pi_act_input_i,
       iq_pi_kp_i,
       iq_pi_ki_i,
       speed_pi_done_o,
       id_pi_done_o,
       iq_pi_done_o,
       speed_pi_output_o,
       id_pi_output_o,
       iq_pi_output_o
    );
input  reset_i;
input  sys_clk_i;
input  clear_buffer_i;
input  speed_en_i;
input  idq_en_i;
input  speed_pi_start_i;
input  id_pi_start_i;
input  iq_pi_start_i;
input  [17:0] speed_init_i;
input  [17:0] id_init_i;
input  [17:0] iq_init_i;
input  [17:0] speed_pi_ref_input_i;
input  [17:0] speed_pi_act_input_i;
input  [17:0] speed_pi_kp_i;
input  [17:0] speed_pi_ki_i;
input  [17:0] speed_pi_ymax_i;
input  [17:0] speed_pi_ymin_i;
input  [17:0] id_pi_ref_input_i;
input  [17:0] id_pi_act_input_i;
input  [17:0] id_pi_kp_i;
input  [17:0] id_pi_ki_i;
input  [17:0] idq_pi_ymax_i;
input  [17:0] idq_pi_ymin_i;
input  [17:0] iq_pi_ref_input_i;
input  [17:0] iq_pi_act_input_i;
input  [17:0] iq_pi_kp_i;
input  [17:0] iq_pi_ki_i;
output speed_pi_done_o;
output id_pi_done_o;
output iq_pi_done_o;
output [17:0] speed_pi_output_o;
output [17:0] id_pi_output_o;
output [17:0] iq_pi_output_o;

    wire [17:0] speed_pi_output_o_net_1;
    wire [43:0] s_acc_out;
    wire [17:0] s_output_y;
    wire [1:1] \pi_scheduler_spi_inst.s_pi_sel ;
    wire [43:0] s_acc_in;
    wire [1:1] \pi_scheduler_spi_inst.s_pi_sel_fast ;
    wire MSC_net_497, MSC_net_498, MSC_net_499, MSC_net_500, 
        \pi_controller_spi_inst.PI_CONT_FSM_PROC.output_y_o6_18 , 
        MSC_net_502, MSC_net_503, MSC_net_504, MSC_net_505, 
        MSC_net_506, MSC_net_507, MSC_net_508, MSC_net_509, 
        MSC_net_510, MSC_net_511, MSC_net_512, MSC_net_513, 
        MSC_net_514, MSC_net_515, MSC_net_516, MSC_net_517, 
        MSC_net_518, MSC_net_519, 
        \pi_scheduler_spi_inst.s_pi_sel_1_rep1 , 
        \pi_scheduler_spi_inst.s_pi_sel_1_rep2 , 
        \pi_scheduler_spi_inst.s_pi_sel_0_rep1 ;
    assign speed_pi_done_o = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[17] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[16] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[15] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[14] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[13] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[12] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[11] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[10] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[9] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[8] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[7] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[6] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[5] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[4] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[3] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[2] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[1] = speed_pi_output_o_net_1[0];
    assign speed_pi_output_o[0] = speed_pi_output_o_net_1[0];
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
MEhF8+h7S1MtIv7X/S1C20jKPixG9fFRHu2vcCArbrKIBAfgaG/QPL8Z+ML5QwHi
j8+9TA3Ja8vLYWofSzoHFNe30bWFvp2s90AJuxrj76a6JKvDX+GcwbFjLtLTI7HU
3DIuy19vb1CB3gJRflVb4zAWgnp11CHln/cREHHZcEU=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=12805)
`pragma protect data_block
[encoded data, 12608 characters]

`pragma protect end_protected

endmodule


module PWM3PH_0(
       reset_i,
       sys_clk_i,
       en_pwm_i,
       en_dual_trig_i,
       va_i,
       vb_i,
       vc_i,
       pwm_period_i,
       dead_time_i,
       delay_time_i,
       midmatch_o,
       PWM_AH_o,
       PWM_BH_o,
       PWM_CH_o,
       PWM_AL_o,
       PWM_BL_o,
       PWM_CL_o
    );
input  reset_i;
input  sys_clk_i;
input  en_pwm_i;
input  en_dual_trig_i;
input  [17:0] va_i;
input  [17:0] vb_i;
input  [17:0] vc_i;
input  [17:0] pwm_period_i;
input  [17:0] dead_time_i;
input  [17:0] delay_time_i;
output midmatch_o;
output PWM_AH_o;
output PWM_BH_o;
output PWM_CH_o;
output PWM_AL_o;
output PWM_BL_o;
output PWM_CL_o;

    wire MSC_net_117;
    wire [17:0] s_pwm_counter;
    wire [17:0] s_delay_counter;
    wire [17:1] \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4 ;
    wire [8:0] \PWM_MIDMATCH_GEN_PROC.s_midmatch5_0_data_tmp ;
    wire [16:0] s_pwm_counter_cry;
    wire [17:0] s_pwm_counter_s;
    wire [17:0] s_delay_counter_s;
    wire [16:1] s_delay_counter_cry;
    wire [16:1] s_delay_counter_cry_Y;
    wire [17:17] s_delay_counter_s_FCO;
    wire [17:17] s_delay_counter_s_Y;
    wire [0:0] va_i_i;
    wire [0:0] vb_i_i;
    wire [16:0] s_pwm_counter_cry_Y;
    wire [17:17] s_pwm_counter_s_FCO;
    wire [17:17] s_pwm_counter_s_Y;
    wire MSC_net_288, MSC_net_289, MSC_net_290, MSC_net_291, 
        MSC_net_292, MSC_net_293, MSC_net_294, MSC_net_295, 
        MSC_net_296, MSC_net_297, MSC_net_298, MSC_net_299, 
        MSC_net_300, MSC_net_301, MSC_net_302, MSC_net_303, 
        MSC_net_304, MSC_net_305, MSC_net_306, MSC_net_307, 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5 , 
        \PWM_OUTPUT_GEN.un1_va_i , \PWM_OUTPUT_GEN.PWM_AL_o6 , 
        \PWM_OUTPUT_GEN.un1_vb_i , \PWM_OUTPUT_GEN.PWM_BL_o6 , 
        MSC_net_313, \PWM_OUTPUT_GEN.PWM_AH_o6 , 
        \PWM_OUTPUT_GEN.PWM_BH_o6 , \PWM_OUTPUT_GEN.un1_va_i_1 , 
        \PWM_OUTPUT_GEN.un1_vb_i_1 , MSC_net_318, MSC_net_319, 
        MSC_net_320, \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_16_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_16_Z , MSC_net_474, MSC_net_475, 
        MSC_net_476, MSC_net_477, MSC_net_478, 
        \PWM_OUTPUT_GEN.un1_va_i_1_1 , \PWM_OUTPUT_GEN.un1_va_i_1_2 , 
        \PWM_OUTPUT_GEN.un1_va_i_1_3 , \PWM_OUTPUT_GEN.un1_va_i_1_4 , 
        \PWM_OUTPUT_GEN.un1_va_i_1_5 , \PWM_OUTPUT_GEN.un1_va_i_1_6 , 
        \PWM_OUTPUT_GEN.un1_va_i_1_7 , \PWM_OUTPUT_GEN.un1_va_i_1_8 , 
        \PWM_OUTPUT_GEN.un1_va_i_1_9 , \PWM_OUTPUT_GEN.un1_va_i_1_10 , 
        \PWM_OUTPUT_GEN.un1_va_i_1_11 , \PWM_OUTPUT_GEN.un1_va_i_1_12 , 
        \PWM_OUTPUT_GEN.un1_va_i_1_13 , \PWM_OUTPUT_GEN.un1_va_i_1_14 , 
        \PWM_OUTPUT_GEN.un1_va_i_1_15 , \PWM_OUTPUT_GEN.un1_va_i_1_16 , 
        \PWM_OUTPUT_GEN.un1_va_i_1_17 , MSC_net_496, MSC_net_497, 
        MSC_net_498, MSC_net_499, MSC_net_500, MSC_net_501, 
        MSC_net_502, MSC_net_503, MSC_net_504, MSC_net_505, 
        MSC_net_506, MSC_net_507, MSC_net_508, MSC_net_509, 
        MSC_net_510, MSC_net_511, MSC_net_512, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_5_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_7_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_13_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_15_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_Z , MSC_net_530, 
        MSC_net_531, MSC_net_532, MSC_net_533, MSC_net_534, 
        MSC_net_535, MSC_net_536, MSC_net_537, MSC_net_538, 
        MSC_net_539, MSC_net_540, MSC_net_541, MSC_net_542, 
        MSC_net_543, MSC_net_544, MSC_net_545, MSC_net_546, 
        MSC_net_547, \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_15_Z , MSC_net_554, 
        MSC_net_555, MSC_net_556, MSC_net_557, MSC_net_558, 
        MSC_net_559, MSC_net_560, MSC_net_561, MSC_net_562, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_RNIOO6E5_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_RNIOO6E5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_RNIPKUS4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_RNIPKUS4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_RNI7T6E4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_RNI7T6E4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_RNIT9FV3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_RNIT9FV3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_RNIRQNG3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_RNIRQNG3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_RNIT8VP2_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_RNIT8VP2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_RNI7R632_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_RNI7R632_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_RNIPHEC1_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_RNIPHEC1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_RNIJCML_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_RNIJCML_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_va_i_1_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_1_cry_0_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_17_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_17_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_AL_o6_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_BL_o6_cry_0_Y , MSC_net_905, MSC_net_906, 
        MSC_net_907, MSC_net_908, MSC_net_909, MSC_net_910, 
        MSC_net_911, MSC_net_912, MSC_net_913, MSC_net_914, 
        MSC_net_915, MSC_net_916, MSC_net_917, MSC_net_918, 
        MSC_net_919, MSC_net_920, MSC_net_921, MSC_net_922, 
        MSC_net_923, MSC_net_924, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_s_17_FCO , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_s_17_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_15_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_13_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_11_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_9_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_7_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_Y , MSC_net_945, 
        MSC_net_946, MSC_net_947, MSC_net_948, MSC_net_949, 
        MSC_net_950, MSC_net_951, MSC_net_952, MSC_net_953, 
        MSC_net_954, MSC_net_955, MSC_net_956, MSC_net_957, 
        MSC_net_958, MSC_net_959, MSC_net_960, MSC_net_961, 
        MSC_net_962, MSC_net_963, MSC_net_964, MSC_net_965, 
        MSC_net_966, MSC_net_967, MSC_net_968;
    assign PWM_CH_o = MSC_net_117;
    assign PWM_CL_o = MSC_net_117;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
Hb+0OpQVnlNgGkvEmyr9YRMTUP8eAsH2MwJs2Bd0+Kb0TATrfpekiImBgBkKUzqe
KLkMXXBJk9OYbAyOdJFqme31b6Y9wzeKhKZibHFYu2id73d00SC1kw2Hrt47Jypm
2+f0hTH8FYsGhURK7rD9pGO6+EIFIzkeLR0oTAyUqUw=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=140965)
`pragma protect data_block
[encoded data, 138752 characters]
rgzLfNsE8W+8ziEDcqEaj8fhPZRJkMWYxSPymzSYfjw=

`pragma protect end_protected

endmodule


module 
        work_adc_interface_adc_interface_6_16_12_g_ADC_CONFIG_REG_WIDTHg_ADC_CONFIG_VAL_WIDTHg_ADC_RESULTS_WIDTH_0(
        
       apb3_if_st_0_adc_control_reg_val_o,
       adc_interface_0_result_ch0_o,
       adc_measurements_0_adc_result_ch1_o,
       adc_interface_0_result_ch2_o,
       adc_measurements_0_adc_result_ch3_o,
       apb3_if_st_0_adc_channel_ch2_o,
       apb3_if_st_0_adc_channel_ch0_o,
       apb3_if_st_0_adc_channel_ch1_o,
       apb3_if_st_0_adc_channel_ch3_o,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FAB_CCC_GL1,
       SEQ_CONTROLLER_1_adc_start_o_0,
       A1_ADC_SDI_I_c,
       A1_ADC_SDO_O_c,
       A1_ADC_CS_O_c,
       A1_ADC_SCK_O_c,
       adc_interface_0_results_rdy_o
    );
input  [5:0] apb3_if_st_0_adc_control_reg_val_o;
output [11:0] adc_interface_0_result_ch0_o;
output [11:0] adc_measurements_0_adc_result_ch1_o;
output [11:0] adc_interface_0_result_ch2_o;
output [11:0] adc_measurements_0_adc_result_ch3_o;
input  [15:0] apb3_if_st_0_adc_channel_ch2_o;
input  [15:0] apb3_if_st_0_adc_channel_ch0_o;
input  [15:0] apb3_if_st_0_adc_channel_ch1_o;
input  [15:0] apb3_if_st_0_adc_channel_ch3_o;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FAB_CCC_GL1;
input  SEQ_CONTROLLER_1_adc_start_o_0;
input  A1_ADC_SDI_I_c;
output A1_ADC_SDO_O_c;
output A1_ADC_CS_O_c;
output A1_ADC_SCK_O_c;
output adc_interface_0_results_rdy_o;

    wire [4:0] s_r_sck_count;
    wire [2:0] s_channel_cnt;
    wire [2:0] s_channel_cnt_5;
    wire [2:0] s_r_adc_chnls_4_samp;
    wire [2:0] s_r_sck_sel;
    wire [15:0] s_r_adc_data;
    wire [15:0] s_r_adc_data_4;
    wire [15:0] s_sdo;
    wire [15:0] s_sdo_14;
    wire [4:0] present_state;
    wire [4:4] next_state;
    wire [3:1] present_state_ns;
    wire [4:4] next_state_i_0;
    wire [3:3] s_r_sck_max_count;
    wire [7:0] s_r_clock_count;
    wire [7:0] s_r_clock_count_s;
    wire [6:0] s_r_clock_count_cry;
    wire [6:0] s_r_clock_count_cry_Y_0;
    wire [7:7] s_r_clock_count_s_FCO_0;
    wire [7:7] s_r_clock_count_s_Y_0;
    wire [1:1] present_state_ns_0_1;
    wire [1:1] present_state_ns_0;
    wire [15:1] s_sdo_14_m3_am;
    wire [15:1] s_sdo_14_m3_bm;
    wire [15:1] s_sdo_14_m3;
    wire [0:0] s_channel_cnt_RNIRCFS;
    wire [0:0] s_sdo_14_m1;
    wire [0:0] s_sdo_14_m2;
    wire VCC, s_r_sck_count_n2_Z, s_r_sck_counte, GND, 
        s_r_sck_count_n3_Z, s_r_sck_count_n4_Z, N_1148_i_0, 
        s_r_sck_count_n1_Z, s_r_sck_count_0_sqmuxa_Z, 
        result_ch1_o_1_sqmuxa, result_ch0_o_0_sqmuxa, 
        result_ch2_o_1_sqmuxa, result_ch3_o_1_sqmuxa, 
        s_sdo_1_sqmuxa_3_i_0, s_start_sig_ext_Z, 
        un13_s_r_adc_results_ready, s_adc_sdi_Z, N_154_i_0, N_277_i_0, 
        N_173_i_0, s_r_sck_enable_Z, adc_sdo_dly_Z, s_slave_select_2, 
        s_r_sck_Z, s_r_sck_10, s_r_adc_results_ready_1_sqmuxa_1, 
        s_r_clock_count_s_171_FCO, s_r_clock_count_s_171_S, 
        s_r_clock_count_s_171_Y, un13_s_r_sck, un1_s_r_sck, 
        s_r_sck_10_7_am_1_1, s_r_sck_10_7_am_0, s_r_sck_10_7_bm_1_1, 
        s_r_sck_10_7_bm_0, s_sdo_14_sm1, un1_s_sdo_1_sqmuxa_1_0_Z, 
        s_channel_cnt_0_sqmuxa_1_Z, result_ch3_o_1_sqmuxa_0_a2_0_3_Z, 
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z, un10_s_start_sig_ext_0_a3_2, 
        s_r_sck_count_c2_Z, un1_s_sdo_2_sqmuxa_tz, s_sdo_3_sqmuxa_Z, 
        N_1197, CO1, un1_s_sdo_1_sqmuxa_1_Z, un22_s_r_sck, CO0, N_120, 
        N_119, N_118, N_117, N_116;
    
    SLE s_r_sck (.D(s_r_sck_10), .CLK(MC_System_0_FAB_CCC_GL1), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(s_r_sck_Z));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[2]  (.A(
        s_sdo_14_m3[2]), .B(s_sdo[1]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[2]));
    SLE s_r_sck_enable (.D(next_state_i_0[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_enable_Z));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[10]  (
        .A(s_sdo_14_sm1), .B(s_sdo_14_m3_am[10]), .C(
        s_sdo_14_m3_bm[10]), .Y(s_sdo_14_m3[10]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[1]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[0]), .Y(s_r_adc_data_4[1]));
    SLE \s_r_adc_data[13]  (.D(s_r_adc_data_4[13]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[13]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[14]  (
        .A(s_sdo_14_sm1), .B(s_sdo_14_m3_am[14]), .C(
        s_sdo_14_m3_bm[14]), .Y(s_sdo_14_m3[14]));
    SLE \s_r_adc_data[4]  (.D(s_r_adc_data_4[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[4]));
    SLE s_slave_select (.D(s_slave_select_2), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(A1_ADC_CS_O_c));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[10]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[10]), .B(
        apb3_if_st_0_adc_channel_ch3_o[10]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[10]));
    SLE \s_r_adc_chnls_4_samp[0]  (.D(
        apb3_if_st_0_adc_control_reg_val_o[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_chnls_4_samp[0]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[1]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[1]), .B(
        apb3_if_st_0_adc_channel_ch3_o[1]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[1]));
    SLE \s_r_clock_count[4]  (.D(s_r_clock_count_s[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_clock_count[4]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[3]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[3]), .B(
        apb3_if_st_0_adc_channel_ch3_o[3]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[3]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[1]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[1]), .C(s_sdo_14_m3_bm[1]), 
        .Y(s_sdo_14_m3[1]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[10]  (.A(
        s_sdo_14_m3[10]), .B(s_sdo[9]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[10]));
    CFG3 #( .INIT(8'h12) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[1]  (.A(
        s_channel_cnt[1]), .B(present_state[4]), .C(CO0), .Y(
        s_channel_cnt_5[1]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[1]  (.A(VCC), .B(
        s_r_clock_count[1]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[0]), .S(s_r_clock_count_s[1]), .Y(
        s_r_clock_count_cry_Y_0[1]), .FCO(s_r_clock_count_cry[1]));
    CFG4 #( .INIT(16'h3437) )  \SCK_GEN_PROC.s_r_sck_10_7_bm_1_1  (.A(
        s_r_clock_count[5]), .B(s_r_sck_sel[2]), .C(s_r_sck_sel[1]), 
        .D(s_r_clock_count[1]), .Y(s_r_sck_10_7_bm_1_1));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[4]  (.A(
        s_sdo_14_m3[4]), .B(s_sdo[3]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[4]));
    SLE \s_sdo[2]  (.D(s_sdo_14[2]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[2]));
    CFG2 #( .INIT(4'hE) )  s_sdo_1_sqmuxa_3_i (.A(un1_s_r_sck), .B(
        A1_ADC_CS_O_c), .Y(s_sdo_1_sqmuxa_3_i_0));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[4]  (.A(VCC), .B(
        s_r_clock_count[4]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[3]), .S(s_r_clock_count_s[4]), .Y(
        s_r_clock_count_cry_Y_0[4]), .FCO(s_r_clock_count_cry[4]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[7]  (.A(
        s_sdo_14_m3[7]), .B(s_sdo[6]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[7]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[5]  (.A(
        s_sdo_14_m3[5]), .B(s_sdo[4]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[5]));
    SLE \result_ch0_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[4]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[12]  
        (.A(A1_ADC_CS_O_c), .B(s_r_adc_data[11]), .Y(
        s_r_adc_data_4[12]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[0]  (.A(VCC), .B(
        s_r_clock_count[0]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_s_171_FCO), .S(s_r_clock_count_s[0]), .Y(
        s_r_clock_count_cry_Y_0[0]), .FCO(s_r_clock_count_cry[0]));
    SLE \result_ch1_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[8]));
    CFG4 #( .INIT(16'h5755) )  \SS_GEN_PROC.s_slave_select_2  (.A(
        s_start_sig_ext_Z), .B(s_r_sck_count[4]), .C(s_r_sck_count[2]), 
        .D(un10_s_start_sig_ext_0_a3_2), .Y(s_slave_select_2));
    SLE \s_sdo[5]  (.D(s_sdo_14[5]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[5]));
    SLE \result_ch3_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[0]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[9]  (.A(
        s_sdo_14_m3[9]), .B(s_sdo[8]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[9]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[7]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[7]), .C(s_sdo_14_m3_bm[7]), 
        .Y(s_sdo_14_m3[7]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[4]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[4]), .C(s_sdo_14_m3_bm[4]), 
        .Y(s_sdo_14_m3[4]));
    CFG2 #( .INIT(4'h2) )  un1_s_sdo_0_sqmuxa_tz_1 (.A(
        s_r_adc_chnls_4_samp[1]), .B(s_r_adc_chnls_4_samp[2]), .Y(
        un1_s_sdo_2_sqmuxa_tz));
    SLE \s_r_sck_count[0]  (.D(N_1148_i_0), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[0]));
    SLE \s_sdo[0]  (.D(s_sdo_14[0]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[0]));
    CFG3 #( .INIT(8'h10) )  \present_state_ns_0_1[1]  (.A(N_277_i_0), 
        .B(present_state[2]), .C(SEQ_CONTROLLER_1_adc_start_o_0), .Y(
        present_state_ns_0_1[1]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[12]  (
        .A(s_sdo_14_sm1), .B(s_sdo_14_m3_am[12]), .C(
        s_sdo_14_m3_bm[12]), .Y(s_sdo_14_m3[12]));
    SLE s_start_sig_ext (.D(SEQ_CONTROLLER_1_adc_start_o_0), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(un13_s_r_adc_results_ready), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(s_start_sig_ext_Z));
    CFG4 #( .INIT(16'h6A00) )  s_r_sck_count_n2 (.A(s_r_sck_count[2]), 
        .B(s_r_sck_count[1]), .C(s_r_sck_count[0]), .D(N_277_i_0), .Y(
        s_r_sck_count_n2_Z));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[3]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[2]), .Y(s_r_adc_data_4[3]));
    SLE \result_ch2_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[3]));
    SLE \s_r_adc_data[6]  (.D(s_r_adc_data_4[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[6]));
    SLE \result_ch1_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[6]));
    SLE s_adc_sdi (.D(A1_ADC_SDI_I_c), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(N_154_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(
        VCC), .SD(GND), .LAT(GND), .Q(s_adc_sdi_Z));
    SLE \result_ch1_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[4]));
    CFG2 #( .INIT(4'hE) )  
        \START_SIG_PROC.un13_s_r_adc_results_ready_0  (.A(
        s_r_adc_results_ready_1_sqmuxa_1), .B(
        SEQ_CONTROLLER_1_adc_start_o_0), .Y(un13_s_r_adc_results_ready)
        );
    CFG2 #( .INIT(4'h8) )  s_adc_sdi_RNO (.A(un1_s_r_sck), .B(
        N_277_i_0), .Y(N_154_i_0));
    SLE \s_sdo[1]  (.D(s_sdo_14[1]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[1]));
    SLE \present_state[2]  (.D(present_state_ns[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(present_state[2]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[8]  (.A(
        s_sdo_14_m3[8]), .B(s_sdo[7]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[8]));
    SLE \s_r_clock_count[5]  (.D(s_r_clock_count_s[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_clock_count[5]));
    SLE \result_ch3_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[3]));
    SLE \s_r_clock_count[2]  (.D(s_r_clock_count_s[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_clock_count[2]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[13]  (
        .A(apb3_if_st_0_adc_channel_ch2_o[13]), .B(
        apb3_if_st_0_adc_channel_ch0_o[13]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[13]));
    CFG4 #( .INIT(16'h28A0) )  s_r_sck_count_n4 (.A(N_277_i_0), .B(
        s_r_sck_count_c2_Z), .C(s_r_sck_count[4]), .D(s_r_sck_count[3])
        , .Y(s_r_sck_count_n4_Z));
    SLE \s_sdo[15]  (.D(s_sdo_14[15]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[15]));
    SLE \s_sdo[12]  (.D(s_sdo_14[12]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[12]));
    SLE \s_r_clock_count[3]  (.D(s_r_clock_count_s[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_clock_count[3]));
    SLE \s_r_adc_data[14]  (.D(s_r_adc_data_4[14]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[14]));
    SLE results_rdy_o (.D(s_r_adc_results_ready_1_sqmuxa_1), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_results_rdy_o));
    SLE \result_ch2_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[2]));
    SLE \s_r_sck_count[4]  (.D(s_r_sck_count_n4_Z), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[4]));
    SLE \result_ch1_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[10]));
    SLE \s_r_adc_data[7]  (.D(s_r_adc_data_4[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[7]));
    SLE \result_ch0_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[2]));
    SLE \s_channel_cnt[0]  (.D(s_channel_cnt_5[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_channel_cnt[0]));
    CFG3 #( .INIT(8'h20) )  result_ch2_o_1_sqmuxa_0_a2 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(N_1197), .Y(
        result_ch2_o_1_sqmuxa));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[6]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[6]), .C(s_sdo_14_m3_bm[6]), 
        .Y(s_sdo_14_m3[6]));
    SLE \result_ch1_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[5]));
    CFG4 #( .INIT(16'h88C0) )  \DATA_TRANSMIT_PROC.s_sdo_14[0]  (.A(
        s_sdo_14_m2[0]), .B(A1_ADC_CS_O_c), .C(s_sdo_14_m1[0]), .D(
        s_sdo_14_sm1), .Y(s_sdo_14[0]));
    SLE \s_sdo[11]  (.D(s_sdo_14[11]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[11]));
    SLE \s_r_sck_sel[0]  (.D(apb3_if_st_0_adc_control_reg_val_o[3]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_sel[0]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[11]  (.A(
        s_sdo_14_m3[11]), .B(s_sdo[10]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[11]));
    SLE \s_r_adc_data[15]  (.D(s_r_adc_data_4[15]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[15]));
    CFG3 #( .INIT(8'hA4) )  \present_state_ns_i_m4[2]  (.A(
        present_state[3]), .B(present_state[2]), .C(un1_s_r_sck), .Y(
        present_state_ns[2]));
    CFG3 #( .INIT(8'hDC) )  \next_state_0[4]  (.A(
        SEQ_CONTROLLER_1_adc_start_o_0), .B(
        s_r_adc_results_ready_1_sqmuxa_1), .C(present_state[4]), .Y(
        next_state[4]));
    SLE \s_r_adc_data[5]  (.D(s_r_adc_data_4[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[5]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[1]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[1]), .B(
        apb3_if_st_0_adc_channel_ch0_o[1]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[1]));
    SLE \s_r_adc_data[11]  (.D(s_r_adc_data_4[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[11]));
    SLE \s_r_adc_chnls_4_samp[1]  (.D(
        apb3_if_st_0_adc_control_reg_val_o[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_chnls_4_samp[1]));
    SLE \s_sdo[9]  (.D(s_sdo_14[9]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[9]));
    SLE \result_ch0_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[1]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[3]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[3]), .B(
        apb3_if_st_0_adc_channel_ch0_o[3]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[3]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[5]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[5]), .B(
        apb3_if_st_0_adc_channel_ch3_o[5]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[5]));
    CFG2 #( .INIT(4'h2) )  \s_r_sck_count_RNO[0]  (.A(N_277_i_0), .B(
        s_r_sck_count[0]), .Y(N_1148_i_0));
    SLE \s_r_sck_max_count[3]  (.D(VCC), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_r_sck_max_count[3]));
    GND GND_Z (.Y(GND));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[4]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[3]), .Y(s_r_adc_data_4[4]));
    SLE \s_sdo[4]  (.D(s_sdo_14[4]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[4]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[9]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[9]), .B(
        apb3_if_st_0_adc_channel_ch3_o[9]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[9]));
    CFG4 #( .INIT(16'h006A) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[2]  (
        .A(s_channel_cnt[2]), .B(CO0), .C(s_channel_cnt[1]), .D(
        present_state[4]), .Y(s_channel_cnt_5[2]));
    CFG4 #( .INIT(16'h0401) )  result_ch3_o_1_sqmuxa_0_a2_0_2 (.A(
        s_r_adc_data[15]), .B(s_r_sck_max_count[3]), .C(
        s_r_adc_data[14]), .D(s_r_sck_count[4]), .Y(
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z));
    VCC VCC_Z (.Y(VCC));
    SLE \s_r_sck_sel[2]  (.D(apb3_if_st_0_adc_control_reg_val_o[5]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_sel[2]));
    SLE \s_r_adc_data[10]  (.D(s_r_adc_data_4[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[10]));
    SLE \result_ch0_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[8]));
    CFG4 #( .INIT(16'h7555) )  \present_state_ns_o4_RNIF7191[3]  (.A(
        N_277_i_0), .B(s_r_sck_Z), .C(un13_s_r_sck), .D(A1_ADC_SCK_O_c)
        , .Y(s_r_sck_counte));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[15]  
        (.A(A1_ADC_CS_O_c), .B(s_r_adc_data[14]), .Y(
        s_r_adc_data_4[15]));
    SLE \result_ch2_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[5]));
    SLE \result_ch2_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[10]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[10]  
        (.A(A1_ADC_CS_O_c), .B(s_r_adc_data[9]), .Y(s_r_adc_data_4[10])
        );
    SLE \result_ch3_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[4]));
    CFG3 #( .INIT(8'h40) )  result_ch1_o_1_sqmuxa_0_a2 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(N_1197), .Y(
        result_ch1_o_1_sqmuxa));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[13]  (.A(
        s_sdo_14_m3[13]), .B(s_sdo[12]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[13]));
    SLE \result_ch0_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[9]));
    SLE \result_ch3_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[6]));
    SLE sdo_o (.D(adc_sdo_dly_Z), .CLK(MC_System_0_FAB_CCC_GL1), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(A1_ADC_SDO_O_c));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_s[7]  (.A(VCC), .B(
        s_r_clock_count[7]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[6]), .S(s_r_clock_count_s[7]), .Y(
        s_r_clock_count_s_Y_0[7]), .FCO(s_r_clock_count_s_FCO_0[7]));
    SLE \result_ch1_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[11]));
    SLE \result_ch0_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[5]));
    SLE \result_ch0_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[0]));
    CFG4 #( .INIT(16'h0001) )  \s_channel_cnt_RNIRCFS[0]  (.A(
        s_channel_cnt[1]), .B(s_r_adc_chnls_4_samp[2]), .C(
        s_channel_cnt[2]), .D(s_channel_cnt[0]), .Y(
        s_channel_cnt_RNIRCFS[0]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m1[0]  (.A(
        apb3_if_st_0_adc_channel_ch1_o[0]), .B(
        apb3_if_st_0_adc_channel_ch3_o[0]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m1[0]));
    ARI1 #( .INIT(20'h4AA00) )  s_r_clock_count_s_171 (.A(VCC), .B(
        s_r_sck_enable_Z), .C(GND), .D(GND), .FCI(VCC), .S(
        s_r_clock_count_s_171_S), .Y(s_r_clock_count_s_171_Y), .FCO(
        s_r_clock_count_s_171_FCO));
    CFG4 #( .INIT(16'hEACC) )  \present_state_ns[3]  (.A(
        present_state[2]), .B(N_277_i_0), .C(un13_s_r_sck), .D(
        un1_s_r_sck), .Y(present_state_ns[3]));
    SLE \s_r_adc_data[8]  (.D(s_r_adc_data_4[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[8]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[0]  (
        .A(A1_ADC_CS_O_c), .B(s_adc_sdi_Z), .Y(s_r_adc_data_4[0]));
    SLE \s_r_clock_count[6]  (.D(s_r_clock_count_s[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_clock_count[6]));
    CFG4 #( .INIT(16'hF1F0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3s2  (.A(
        s_channel_cnt[2]), .B(s_channel_cnt[0]), .C(
        s_channel_cnt_RNIRCFS[0]), .D(un1_s_sdo_2_sqmuxa_tz), .Y(
        s_sdo_14_sm1));
    CFG3 #( .INIT(8'h80) )  result_ch3_o_1_sqmuxa_0_a2 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(N_1197), .Y(
        result_ch3_o_1_sqmuxa));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[2]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[1]), .Y(s_r_adc_data_4[2]));
    SLE \present_state[0]  (.D(N_173_i_0), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(present_state[0]));
    SLE \result_ch3_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[1]));
    SLE \result_ch2_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[6]));
    SLE \s_r_sck_count[3]  (.D(s_r_sck_count_n3_Z), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[3]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[2]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[2]), .B(
        apb3_if_st_0_adc_channel_ch3_o[2]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[2]));
    SLE \s_r_sck_count[1]  (.D(s_r_sck_count_n1_Z), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[1]));
    SLE \present_state[3]  (.D(present_state_ns[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(present_state[3]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[13]  (
        .A(s_sdo_14_sm1), .B(s_sdo_14_m3_am[13]), .C(
        s_sdo_14_m3_bm[13]), .Y(s_sdo_14_m3[13]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[8]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[8]), .B(
        apb3_if_st_0_adc_channel_ch3_o[8]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[8]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[7]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[7]), .B(
        apb3_if_st_0_adc_channel_ch3_o[7]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[7]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[7]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[6]), .Y(s_r_adc_data_4[7]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[14]  (.A(
        s_sdo_14_m3[14]), .B(s_sdo[13]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[14]));
    CFG4 #( .INIT(16'h045D) )  \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO1  (
        .A(s_r_adc_chnls_4_samp[1]), .B(s_r_adc_chnls_4_samp[0]), .C(
        s_channel_cnt[0]), .D(s_channel_cnt[1]), .Y(CO1));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[6]  (.A(VCC), .B(
        s_r_clock_count[6]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[5]), .S(s_r_clock_count_s[6]), .Y(
        s_r_clock_count_cry_Y_0[6]), .FCO(s_r_clock_count_cry[6]));
    SLE \s_channel_cnt[2]  (.D(s_channel_cnt_5[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_channel_cnt[2]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[4]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[4]), .B(
        apb3_if_st_0_adc_channel_ch3_o[4]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[4]));
    SLE \s_sdo[6]  (.D(s_sdo_14[6]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[6]));
    SLE \result_ch0_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[3]));
    SLE \result_ch0_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[7]));
    CFG3 #( .INIT(8'h01) )  \SS_GEN_PROC.un10_s_start_sig_ext_0_a3_2  
        (.A(s_r_sck_count[3]), .B(s_r_sck_count[1]), .C(
        s_r_sck_count[0]), .Y(un10_s_start_sig_ext_0_a3_2));
    SLE \result_ch0_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[6]));
    CFG4 #( .INIT(16'h303A) )  \present_state_ns_0[1]  (.A(
        present_state_ns_0_1[1]), .B(un1_s_r_sck), .C(present_state[3])
        , .D(present_state[0]), .Y(present_state_ns_0[1]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[9]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[8]), .Y(s_r_adc_data_4[9]));
    SLE \result_ch3_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[10]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m2[0]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[0]), .B(
        apb3_if_st_0_adc_channel_ch0_o[0]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m2[0]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[6]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[6]), .B(
        apb3_if_st_0_adc_channel_ch3_o[6]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[6]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[15]  (.A(
        s_sdo_14_m3[15]), .B(s_sdo[14]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[15]));
    SLE \present_state[1]  (.D(present_state_ns[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(N_277_i_0));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[9]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[9]), .C(s_sdo_14_m3_bm[9]), 
        .Y(s_sdo_14_m3[9]));
    CFG3 #( .INIT(8'h20) )  s_channel_cnt_0_sqmuxa_1 (.A(s_r_sck_Z), 
        .B(A1_ADC_SCK_O_c), .C(present_state[0]), .Y(
        s_channel_cnt_0_sqmuxa_1_Z));
    CFG3 #( .INIT(8'h40) )  \next_state_0_a3_0[4]  (.A(un22_s_r_sck), 
        .B(present_state[0]), .C(un1_s_r_sck), .Y(
        s_r_adc_results_ready_1_sqmuxa_1));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[10]  (
        .A(apb3_if_st_0_adc_channel_ch2_o[10]), .B(
        apb3_if_st_0_adc_channel_ch0_o[10]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[10]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[15]  (
        .A(apb3_if_st_0_adc_channel_ch2_o[15]), .B(
        apb3_if_st_0_adc_channel_ch0_o[15]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[15]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[15]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[15]), .B(
        apb3_if_st_0_adc_channel_ch3_o[15]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[15]));
    SLE \result_ch3_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[5]));
    CFG4 #( .INIT(16'hF8F0) )  \present_state_ns[1]  (.A(un1_s_r_sck), 
        .B(present_state[0]), .C(present_state_ns_0[1]), .D(
        un22_s_r_sck), .Y(present_state_ns[1]));
    CFG4 #( .INIT(16'h0400) )  s_sdo_3_sqmuxa (.A(
        s_r_adc_chnls_4_samp[2]), .B(s_r_adc_chnls_4_samp[0]), .C(
        s_channel_cnt[2]), .D(s_r_adc_chnls_4_samp[1]), .Y(
        s_sdo_3_sqmuxa_Z));
    SLE \result_ch2_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[4]));
    CFG3 #( .INIT(8'hD8) )  \SCK_GEN_PROC.s_r_sck_10_7_ns  (.A(
        s_r_sck_sel[0]), .B(s_r_sck_10_7_bm_0), .C(s_r_sck_10_7_am_0), 
        .Y(s_r_sck_10));
    SLE \result_ch2_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[11]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[11]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[11]), .B(
        apb3_if_st_0_adc_channel_ch3_o[11]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[11]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[5]  (.A(VCC), .B(
        s_r_clock_count[5]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[4]), .S(s_r_clock_count_s[5]), .Y(
        s_r_clock_count_cry_Y_0[5]), .FCO(s_r_clock_count_cry[5]));
    SLE \s_sdo[13]  (.D(s_sdo_14[13]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[13]));
    CFG3 #( .INIT(8'h80) )  s_r_sck_count_c2 (.A(s_r_sck_count[2]), .B(
        s_r_sck_count[1]), .C(s_r_sck_count[0]), .Y(s_r_sck_count_c2_Z)
        );
    SLE \result_ch2_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[0]));
    SLE \s_sdo[7]  (.D(s_sdo_14[7]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[7]));
    CFG3 #( .INIT(8'h28) )  s_r_sck_count_n3 (.A(N_277_i_0), .B(
        s_r_sck_count_c2_Z), .C(s_r_sck_count[3]), .Y(
        s_r_sck_count_n3_Z));
    SLE \result_ch3_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[2]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[11]  
        (.A(A1_ADC_CS_O_c), .B(s_r_adc_data[10]), .Y(
        s_r_adc_data_4[11]));
    CFG3 #( .INIT(8'h18) )  result_ch3_o_1_sqmuxa_0_a2_0_3 (.A(
        s_r_sck_max_count[3]), .B(s_r_sck_count[1]), .C(
        s_r_sck_count[0]), .Y(result_ch3_o_1_sqmuxa_0_a2_0_3_Z));
    SLE \result_ch3_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[7]));
    SLE \result_ch1_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[1]));
    CFG4 #( .INIT(16'h3437) )  \SCK_GEN_PROC.s_r_sck_10_7_am_1_1  (.A(
        s_r_clock_count[4]), .B(s_r_sck_sel[2]), .C(s_r_sck_sel[1]), 
        .D(s_r_clock_count[0]), .Y(s_r_sck_10_7_am_1_1));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[12]  (
        .A(apb3_if_st_0_adc_channel_ch2_o[12]), .B(
        apb3_if_st_0_adc_channel_ch0_o[12]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[12]));
    SLE \result_ch1_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[9]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[14]  
        (.A(A1_ADC_CS_O_c), .B(s_r_adc_data[13]), .Y(
        s_r_adc_data_4[14]));
    CFG4 #( .INIT(16'h0C2A) )  \present_state_RNO[0]  (.A(
        present_state[0]), .B(N_277_i_0), .C(un13_s_r_sck), .D(
        un1_s_r_sck), .Y(N_173_i_0));
    SLE \result_ch3_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[9]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[5]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[5]), .B(
        apb3_if_st_0_adc_channel_ch0_o[5]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[5]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[12]  (.A(
        s_sdo_14_m3[12]), .B(s_sdo[11]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[12]));
    SLE \present_state[4]  (.D(next_state[4]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(GND), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(present_state[4]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[15]  (
        .A(s_sdo_14_sm1), .B(s_sdo_14_m3_am[15]), .C(
        s_sdo_14_m3_bm[15]), .Y(s_sdo_14_m3[15]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[9]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[9]), .B(
        apb3_if_st_0_adc_channel_ch0_o[9]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[9]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[11]  (
        .A(s_sdo_14_sm1), .B(s_sdo_14_m3_am[11]), .C(
        s_sdo_14_m3_bm[11]), .Y(s_sdo_14_m3[11]));
    SLE \result_ch0_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[10]));
    CFG3 #( .INIT(8'h60) )  s_r_sck_count_n1 (.A(s_r_sck_count[1]), .B(
        s_r_sck_count[0]), .C(N_277_i_0), .Y(s_r_sck_count_n1_Z));
    SLE \s_r_adc_data[2]  (.D(s_r_adc_data_4[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[2]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[2]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[2]), .C(s_sdo_14_m3_bm[2]), 
        .Y(s_sdo_14_m3[2]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[1]  (.A(
        s_sdo_14_m3[1]), .B(s_sdo[0]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[1]));
    CFG4 #( .INIT(16'h6F06) )  \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO2  (
        .A(s_r_adc_chnls_4_samp[2]), .B(s_r_adc_chnls_4_samp[1]), .C(
        s_channel_cnt[2]), .D(CO1), .Y(un22_s_r_sck));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[2]  (.A(VCC), .B(
        s_r_clock_count[2]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[1]), .S(s_r_clock_count_s[2]), .Y(
        s_r_clock_count_cry_Y_0[2]), .FCO(s_r_clock_count_cry[2]));
    SLE \s_r_adc_data[12]  (.D(s_r_adc_data_4[12]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[12]));
    SLE \s_r_adc_data[1]  (.D(s_r_adc_data_4[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[1]));
    CFG4 #( .INIT(16'hB931) )  \SCK_GEN_PROC.s_r_sck_10_7_am  (.A(
        s_r_sck_sel[1]), .B(s_r_sck_10_7_am_1_1), .C(
        s_r_clock_count[6]), .D(s_r_clock_count[2]), .Y(
        s_r_sck_10_7_am_0));
    SLE \s_sdo[10]  (.D(s_sdo_14[10]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[10]));
    CFG3 #( .INIT(8'h10) )  result_ch0_o_0_sqmuxa_0_a2 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(N_1197), .Y(
        result_ch0_o_0_sqmuxa));
    CFG4 #( .INIT(16'h3200) )  un1_s_sdo_1_sqmuxa_1 (.A(
        s_r_adc_chnls_4_samp[0]), .B(s_r_adc_chnls_4_samp[2]), .C(
        s_r_adc_chnls_4_samp[1]), .D(un1_s_sdo_1_sqmuxa_1_0_Z), .Y(
        un1_s_sdo_1_sqmuxa_1_Z));
    SLE \result_ch2_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[8]));
    CFG2 #( .INIT(4'h2) )  \ADC_FSM_NS_PROC.un1_s_r_sck  (.A(
        A1_ADC_SCK_O_c), .B(s_r_sck_Z), .Y(un1_s_r_sck));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[3]  (.A(VCC), .B(
        s_r_clock_count[3]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[2]), .S(s_r_clock_count_s[3]), .Y(
        s_r_clock_count_cry_Y_0[3]), .FCO(s_r_clock_count_cry[3]));
    SLE \result_ch3_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[11]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[5]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[5]), .C(s_sdo_14_m3_bm[5]), 
        .Y(s_sdo_14_m3[5]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[14]  (
        .A(apb3_if_st_0_adc_channel_ch2_o[14]), .B(
        apb3_if_st_0_adc_channel_ch0_o[14]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[14]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[3]  (.A(
        s_sdo_14_m3[3]), .B(s_sdo[2]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[3]));
    SLE \s_r_adc_chnls_4_samp[2]  (.D(
        apb3_if_st_0_adc_control_reg_val_o[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_chnls_4_samp[2]));
    SLE \s_sdo[8]  (.D(s_sdo_14[8]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[8]));
    SLE \result_ch1_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[3]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[8]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[8]), .C(s_sdo_14_m3_bm[8]), 
        .Y(s_sdo_14_m3[8]));
    CFG3 #( .INIT(8'h23) )  \next_state_0_i[4]  (.A(
        SEQ_CONTROLLER_1_adc_start_o_0), .B(
        s_r_adc_results_ready_1_sqmuxa_1), .C(present_state[4]), .Y(
        next_state_i_0[4]));
    CFG4 #( .INIT(16'h0078) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[0]  (
        .A(s_channel_cnt_0_sqmuxa_1_Z), .B(un22_s_r_sck), .C(
        s_channel_cnt[0]), .D(present_state[4]), .Y(s_channel_cnt_5[0])
        );
    SLE \result_ch2_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[9]));
    SLE \result_ch1_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[7]));
    CFG4 #( .INIT(16'h5557) )  \present_state_ns_o4[3]  (.A(
        s_r_sck_count[4]), .B(s_r_sck_count[3]), .C(s_r_sck_count[2]), 
        .D(s_r_sck_count[1]), .Y(un13_s_r_sck));
    CFG4 #( .INIT(16'h1000) )  result_ch3_o_1_sqmuxa_0_a2_0 (.A(
        s_r_sck_count[3]), .B(s_r_sck_count[2]), .C(
        result_ch3_o_1_sqmuxa_0_a2_0_3_Z), .D(
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z), .Y(N_1197));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[13]  
        (.A(A1_ADC_CS_O_c), .B(s_r_adc_data[12]), .Y(
        s_r_adc_data_4[13]));
    SLE \s_r_adc_data[3]  (.D(s_r_adc_data_4[3]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[3]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14[6]  (.A(
        s_sdo_14_m3[6]), .B(s_sdo[5]), .C(A1_ADC_CS_O_c), .Y(
        s_sdo_14[6]));
    CFG4 #( .INIT(16'hB931) )  \SCK_GEN_PROC.s_r_sck_10_7_bm  (.A(
        s_r_sck_sel[1]), .B(s_r_sck_10_7_bm_1_1), .C(
        s_r_clock_count[7]), .D(s_r_clock_count[3]), .Y(
        s_r_sck_10_7_bm_0));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[13]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[13]), .B(
        apb3_if_st_0_adc_channel_ch3_o[13]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[13]));
    SLE \s_sdo[14]  (.D(s_sdo_14[14]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[14]));
    SLE \result_ch2_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[7]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[12]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[12]), .B(
        apb3_if_st_0_adc_channel_ch3_o[12]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[12]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[6]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[5]), .Y(s_r_adc_data_4[6]));
    SLE \result_ch1_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[0]));
    CFG3 #( .INIT(8'hE4) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_ns[3]  (.A(
        s_sdo_14_sm1), .B(s_sdo_14_m3_am[3]), .C(s_sdo_14_m3_bm[3]), 
        .Y(s_sdo_14_m3[3]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[5]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[4]), .Y(s_r_adc_data_4[5]));
    SLE \s_r_sck_sel[1]  (.D(apb3_if_st_0_adc_control_reg_val_o[4]), 
        .CLK(MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_sel[1]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[2]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[2]), .B(
        apb3_if_st_0_adc_channel_ch0_o[2]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[2]));
    SLE \s_r_adc_data[0]  (.D(s_r_adc_data_4[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[0]));
    SLE \result_ch3_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch3_o[8]));
    CFG4 #( .INIT(16'h4000) )  s_r_sck_count_0_sqmuxa (.A(s_r_sck_Z), 
        .B(N_277_i_0), .C(A1_ADC_SCK_O_c), .D(un13_s_r_sck), .Y(
        s_r_sck_count_0_sqmuxa_Z));
    SLE \s_r_clock_count[1]  (.D(s_r_clock_count_s[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_clock_count[1]));
    SLE \s_r_clock_count[0]  (.D(s_r_clock_count_s[0]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_clock_count[0]));
    SLE adc_sdo_dly (.D(s_sdo[15]), .CLK(MC_System_0_FAB_CCC_GL1), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(adc_sdo_dly_Z));
    CFG3 #( .INIT(8'h80) )  s_channel_cnt_0_sqmuxa_1_RNIKES32 (.A(
        s_channel_cnt_0_sqmuxa_1_Z), .B(un22_s_r_sck), .C(
        s_channel_cnt[0]), .Y(CO0));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[8]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[8]), .B(
        apb3_if_st_0_adc_channel_ch0_o[8]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[8]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[7]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[7]), .B(
        apb3_if_st_0_adc_channel_ch0_o[7]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[7]));
    SLE \s_sdo[3]  (.D(s_sdo_14[3]), .CLK(MC_System_0_FAB_CCC_GL1), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[3]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[4]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[4]), .B(
        apb3_if_st_0_adc_channel_ch0_o[4]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[4]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_am[14]  
        (.A(apb3_if_st_0_adc_channel_ch1_o[14]), .B(
        apb3_if_st_0_adc_channel_ch3_o[14]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_m3_am[14]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[8]  (
        .A(A1_ADC_CS_O_c), .B(s_r_adc_data[7]), .Y(s_r_adc_data_4[8]));
    CFG2 #( .INIT(4'h1) )  un1_s_sdo_1_sqmuxa_1_0 (.A(s_channel_cnt[2])
        , .B(s_channel_cnt[1]), .Y(un1_s_sdo_1_sqmuxa_1_0_Z));
    SLE \s_r_sck_count[2]  (.D(s_r_sck_count_n2_Z), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[2]));
    SLE \result_ch2_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[1]));
    SLE \s_r_adc_data[9]  (.D(s_r_adc_data_4[9]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[9]));
    SLE \result_ch1_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_measurements_0_adc_result_ch1_o[2]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[11]  (
        .A(apb3_if_st_0_adc_channel_ch2_o[11]), .B(
        apb3_if_st_0_adc_channel_ch0_o[11]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[11]));
    SLE \s_channel_cnt[1]  (.D(s_channel_cnt_5[1]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_channel_cnt[1]));
    CFG3 #( .INIT(8'hCA) )  \DATA_TRANSMIT_PROC.s_sdo_14_m3_bm[6]  (.A(
        apb3_if_st_0_adc_channel_ch2_o[6]), .B(
        apb3_if_st_0_adc_channel_ch0_o[6]), .C(
        s_channel_cnt_RNIRCFS[0]), .Y(s_sdo_14_m3_bm[6]));
    SLE \result_ch0_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[11]));
    SLE \s_r_clock_count[7]  (.D(s_r_clock_count_s[7]), .CLK(
        MC_System_0_FAB_CCC_GL1), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_clock_count[7]));
    SLE sck_o (.D(s_r_sck_Z), .CLK(MC_System_0_FAB_CCC_GL1), .EN(VCC), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(A1_ADC_SCK_O_c));
    
endmodule


module Stepper_Axis(
       STEPPER_THETA_1_step_count_o_2,
       FOC_TRANSFORMS_0_id_o_2,
       FOC_TRANSFORMS_0_id_o_11,
       FOC_TRANSFORMS_0_iq_o_2,
       FOC_TRANSFORMS_0_iq_o_11,
       SPEED_ID_IQ_PI_1_iq_pi_output_o_0,
       FOC_TRANSFORMS_1_valpha_o_11,
       FOC_TRANSFORMS_0_vbeta_o_11,
       ADC_SCALING_0_ib_adc_o_2,
       adc_interface_0_result_ch0_o_2,
       adc_interface_0_result_ch2_o_2,
       SEQ_CONTROLLER_1_state_o_0_2,
       MC_System_0_AMBA_SLAVE_1_PWDATA,
       MC_System_0_AMBA_SLAVE_1_PADDR,
       prdata_o_1_0_a2_7_0,
       prdata_o_1_iv_12_0_2,
       prdata_o_1_iv_12_1,
       SPEED_ID_IQ_PI_1_id_pi_output_o_m,
       prdata_o_1_iv_9,
       prdata_o_1_iv_12,
       prdata_o_1_0_iv_11,
       prdata_o_1_0_iv_6,
       prdata_o_1_0_iv_7,
       prdata_o_1_iv_11_3,
       prdata_o_1_iv_11_1,
       prdata_o_1_iv_11_0,
       prdata_o_1_0_iv_10,
       adc_measurements_0_adc_result_ch1_o_2,
       adc_measurements_0_adc_result_ch3_o_2,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FAB_CCC_GL1,
       A1_PWM_WL_O_c,
       A1_PWM_UH_O_c,
       A1_PWM_VH_O_c,
       A1_PWM_UL_O_c,
       A1_PWM_VL_O_c,
       N_193,
       N_194,
       N_184,
       prdata_o197_0_a2_0_a2_0_out,
       N_185,
       N_174,
       prdata_o201_0_a2_0_0,
       g1,
       g2,
       N_172,
       N_187,
       N_104,
       N_105,
       N_106,
       N_107,
       N_108,
       adc_channel_ch3_o_1_sqmuxa_0_a2_0_0,
       prdata_o195_0_a2_0,
       prdata_o190_0_a2_0_out,
       N_202,
       prdata_o200_2,
       N_176,
       N_201,
       N_179,
       N_233,
       N_2787,
       MC_System_0_AMBA_SLAVE_1_PWRITE,
       MC_System_0_AMBA_SLAVE_1_PSELx,
       MC_System_0_AMBA_SLAVE_1_PENABLE,
       prdata_o191,
       prdata_o190,
       N_2470,
       N_151,
       N_152,
       N_153,
       N_154,
       N_155,
       N_156,
       N_157,
       N_54,
       A1_ADC_SDI_I_c,
       A1_ADC_SDO_O_c,
       A1_ADC_CS_O_c,
       A1_ADC_SCK_O_c
    );
output STEPPER_THETA_1_step_count_o_2;
output FOC_TRANSFORMS_0_id_o_2;
output FOC_TRANSFORMS_0_id_o_11;
output FOC_TRANSFORMS_0_iq_o_2;
output FOC_TRANSFORMS_0_iq_o_11;
output SPEED_ID_IQ_PI_1_iq_pi_output_o_0;
output FOC_TRANSFORMS_1_valpha_o_11;
output FOC_TRANSFORMS_0_vbeta_o_11;
output ADC_SCALING_0_ib_adc_o_2;
output adc_interface_0_result_ch0_o_2;
output adc_interface_0_result_ch2_o_2;
output SEQ_CONTROLLER_1_state_o_0_2;
input  [23:0] MC_System_0_AMBA_SLAVE_1_PWDATA;
input  [11:0] MC_System_0_AMBA_SLAVE_1_PADDR;
input  [3:3] prdata_o_1_0_a2_7_0;
output [3:3] prdata_o_1_iv_12_0_2;
output [3:3] prdata_o_1_iv_12_1;
output [0:0] SPEED_ID_IQ_PI_1_id_pi_output_o_m;
output [0:0] prdata_o_1_iv_9;
output [3:1] prdata_o_1_iv_12;
output [10:4] prdata_o_1_0_iv_11;
output [16:12] prdata_o_1_0_iv_6;
output [16:12] prdata_o_1_0_iv_7;
output prdata_o_1_iv_11_3;
output prdata_o_1_iv_11_1;
output prdata_o_1_iv_11_0;
output [10:4] prdata_o_1_0_iv_10;
output adc_measurements_0_adc_result_ch1_o_2;
output adc_measurements_0_adc_result_ch3_o_2;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FAB_CCC_GL1;
output A1_PWM_WL_O_c;
output A1_PWM_UH_O_c;
output A1_PWM_VH_O_c;
output A1_PWM_UL_O_c;
output A1_PWM_VL_O_c;
output N_193;
output N_194;
output N_184;
output prdata_o197_0_a2_0_a2_0_out;
input  N_185;
output N_174;
output prdata_o201_0_a2_0_0;
output g1;
output g2;
output N_172;
output N_187;
output N_104;
output N_105;
output N_106;
output N_107;
output N_108;
output adc_channel_ch3_o_1_sqmuxa_0_a2_0_0;
output prdata_o195_0_a2_0;
output prdata_o190_0_a2_0_out;
output N_202;
output prdata_o200_2;
input  N_176;
output N_201;
output N_179;
output N_233;
input  N_2787;
input  MC_System_0_AMBA_SLAVE_1_PWRITE;
input  MC_System_0_AMBA_SLAVE_1_PSELx;
input  MC_System_0_AMBA_SLAVE_1_PENABLE;
output prdata_o191;
output prdata_o190;
input  N_2470;
output N_151;
output N_152;
output N_153;
output N_154;
output N_155;
output N_156;
output N_157;
output N_54;
input  A1_ADC_SDI_I_c;
output A1_ADC_SDO_O_c;
output A1_ADC_CS_O_c;
output A1_ADC_SCK_O_c;

    wire [17:0] apb3_if_st_0_theta_gen_slew_count_o;
    wire [17:0] apb3_if_st_0_theta_gen_rate_limit_o;
    wire [23:0] apb3_if_st_0_theta_gen_cmd_step_no_o_0;
    wire [17:0] STEPPER_THETA_0_theta_output_o;
    wire [23:0] STEPPER_THETA_1_step_count_o;
    wire [17:0] apb3_if_st_0_sqmng_dv_o;
    wire [17:0] apb3_if_st_0_id_ref_val_o;
    wire [17:0] FOC_TRANSFORMS_0_id_o;
    wire [17:0] apb3_if_st_0_idq_pi_kp_o;
    wire [17:0] apb3_if_st_0_idq_pi_ki_o;
    wire [17:0] FOC_TRANSFORMS_0_iq_o;
    wire [17:0] speed_pi_output_o;
    wire [17:0] SPEED_ID_IQ_PI_1_id_pi_output_o;
    wire [17:1] SPEED_ID_IQ_PI_1_iq_pi_output_o;
    wire [17:0] FOC_TRANSFORMS_1_valpha_o;
    wire [17:0] FOC_TRANSFORMS_0_vbeta_o;
    wire [17:0] apb3_if_st_0_pwm_period_val_o;
    wire [17:0] PWM_SCALING_0_Va_o;
    wire [17:0] PWM_SCALING_0_Vb_o;
    wire [17:0] Vc_o;
    wire [17:0] apb3_if_st_0_pwm_dead_time_val_o;
    wire [17:0] apb3_if_st_0_pwm_delay_time_val_o;
    wire [17:0] ADC_SCALING_0_ia_adc_o;
    wire [17:0] ADC_SCALING_0_ib_adc_o;
    wire [17:0] ialpha_o;
    wire [17:0] ibeta_o;
    wire [17:0] va_o;
    wire [17:0] vb_o;
    wire [17:0] vc_o;
    wire [17:0] apb3_if_st_0_adc_scale_val_o;
    wire [11:0] adc_interface_0_result_ch0_o;
    wire [11:0] adc_interface_0_result_ch2_o;
    wire [17:0] apb3_if_st_0_adc_oc_thresh_o;
    wire [3:0] SEQ_CONTROLLER_1_state_o_0;
    wire [2:1] apb3_if_st_0_seq_cntl_config_o;
    wire [5:0] apb3_if_st_0_adc_control_reg_val_o;
    wire [15:0] apb3_if_st_0_adc_channel_ch0_o;
    wire [15:0] apb3_if_st_0_adc_channel_ch1_o;
    wire [15:0] apb3_if_st_0_adc_channel_ch2_o;
    wire [15:0] apb3_if_st_0_adc_channel_ch3_o;
    wire [11:0] adc_measurements_0_adc_result_ch3_o;
    wire [11:0] adc_measurements_0_adc_result_ch1_o;
    wire ADC_SCALING_0_calib_done_o, apb3_if_st_0_theta_gen_mode_o, 
        A1_PWM_WL_O_c_i_0, GND, N_614_i_0, 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, FOC_TRANSFORMS_0_park_done_o, 
        VCC, speed_pi_done_o_0, SPEED_ID_IQ_PI_1_id_pi_done_o, 
        FOC_TRANSFORMS_1_ipark_done_o, PWM_SCALING_0_done_o, 
        PWM3PH_0_midmatch_o, PWM_CH_o, PWM_CL_o_0, 
        ADC_SCALING_0_done_o, clarke_done_o, iclarke_done_o, 
        adc_interface_0_results_rdy_o, 
        ADC_SCALING_0_over_current_fault_o, 
        SEQ_CONTROLLER_1_adc_start_o_0, apb3_if_st_0_start_motor_o, 
        apb3_if_st_0_stop_motor_o;
    
    PWM_SCALING_2s_44s_15s_0_1_2_4_0 MSC_i_50 (.reset_i(
        MC_System_0_FIC_0_LOCK), .sys_clk_i(MC_System_0_FAB_CCC_GL1), 
        .start_i(FOC_TRANSFORMS_1_ipark_done_o), .va_i({
        FOC_TRANSFORMS_1_valpha_o[17], FOC_TRANSFORMS_1_valpha_o[16], 
        FOC_TRANSFORMS_1_valpha_o[15], FOC_TRANSFORMS_1_valpha_o[14], 
        FOC_TRANSFORMS_1_valpha_o[13], FOC_TRANSFORMS_1_valpha_o[12], 
        FOC_TRANSFORMS_1_valpha_o_11, FOC_TRANSFORMS_1_valpha_o[10], 
        FOC_TRANSFORMS_1_valpha_o[9], FOC_TRANSFORMS_1_valpha_o[8], 
        FOC_TRANSFORMS_1_valpha_o[7], FOC_TRANSFORMS_1_valpha_o[6], 
        FOC_TRANSFORMS_1_valpha_o[5], FOC_TRANSFORMS_1_valpha_o[4], 
        FOC_TRANSFORMS_1_valpha_o[3], FOC_TRANSFORMS_1_valpha_o[2], 
        FOC_TRANSFORMS_1_valpha_o[1], FOC_TRANSFORMS_1_valpha_o[0]}), 
        .vb_i({FOC_TRANSFORMS_0_vbeta_o[17], 
        FOC_TRANSFORMS_0_vbeta_o[16], FOC_TRANSFORMS_0_vbeta_o[15], 
        FOC_TRANSFORMS_0_vbeta_o[14], FOC_TRANSFORMS_0_vbeta_o[13], 
        FOC_TRANSFORMS_0_vbeta_o[12], FOC_TRANSFORMS_0_vbeta_o_11, 
        FOC_TRANSFORMS_0_vbeta_o[10], FOC_TRANSFORMS_0_vbeta_o[9], 
        FOC_TRANSFORMS_0_vbeta_o[8], FOC_TRANSFORMS_0_vbeta_o[7], 
        FOC_TRANSFORMS_0_vbeta_o[6], FOC_TRANSFORMS_0_vbeta_o[5], 
        FOC_TRANSFORMS_0_vbeta_o[4], FOC_TRANSFORMS_0_vbeta_o[3], 
        FOC_TRANSFORMS_0_vbeta_o[2], FOC_TRANSFORMS_0_vbeta_o[1], 
        FOC_TRANSFORMS_0_vbeta_o[0]}), .vc_i({GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND}), .pwm_period_i({apb3_if_st_0_pwm_period_val_o[17], 
        apb3_if_st_0_pwm_period_val_o[16], 
        apb3_if_st_0_pwm_period_val_o[15], 
        apb3_if_st_0_pwm_period_val_o[14], 
        apb3_if_st_0_pwm_period_val_o[13], 
        apb3_if_st_0_pwm_period_val_o[12], 
        apb3_if_st_0_pwm_period_val_o[11], 
        apb3_if_st_0_pwm_period_val_o[10], 
        apb3_if_st_0_pwm_period_val_o[9], 
        apb3_if_st_0_pwm_period_val_o[8], 
        apb3_if_st_0_pwm_period_val_o[7], 
        apb3_if_st_0_pwm_period_val_o[6], 
        apb3_if_st_0_pwm_period_val_o[5], 
        apb3_if_st_0_pwm_period_val_o[4], 
        apb3_if_st_0_pwm_period_val_o[3], 
        apb3_if_st_0_pwm_period_val_o[2], 
        apb3_if_st_0_pwm_period_val_o[1], 
        apb3_if_st_0_pwm_period_val_o[0]}), .pwm_gain_i({GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND}), .Va_o({PWM_SCALING_0_Va_o[17], 
        PWM_SCALING_0_Va_o[16], PWM_SCALING_0_Va_o[15], 
        PWM_SCALING_0_Va_o[14], PWM_SCALING_0_Va_o[13], 
        PWM_SCALING_0_Va_o[12], PWM_SCALING_0_Va_o[11], 
        PWM_SCALING_0_Va_o[10], PWM_SCALING_0_Va_o[9], 
        PWM_SCALING_0_Va_o[8], PWM_SCALING_0_Va_o[7], 
        PWM_SCALING_0_Va_o[6], PWM_SCALING_0_Va_o[5], 
        PWM_SCALING_0_Va_o[4], PWM_SCALING_0_Va_o[3], 
        PWM_SCALING_0_Va_o[2], PWM_SCALING_0_Va_o[1], 
        PWM_SCALING_0_Va_o[0]}), .Vb_o({PWM_SCALING_0_Vb_o[17], 
        PWM_SCALING_0_Vb_o[16], PWM_SCALING_0_Vb_o[15], 
        PWM_SCALING_0_Vb_o[14], PWM_SCALING_0_Vb_o[13], 
        PWM_SCALING_0_Vb_o[12], PWM_SCALING_0_Vb_o[11], 
        PWM_SCALING_0_Vb_o[10], PWM_SCALING_0_Vb_o[9], 
        PWM_SCALING_0_Vb_o[8], PWM_SCALING_0_Vb_o[7], 
        PWM_SCALING_0_Vb_o[6], PWM_SCALING_0_Vb_o[5], 
        PWM_SCALING_0_Vb_o[4], PWM_SCALING_0_Vb_o[3], 
        PWM_SCALING_0_Vb_o[2], PWM_SCALING_0_Vb_o[1], 
        PWM_SCALING_0_Vb_o[0]}), .Vc_o({Vc_o[17], Vc_o[16], Vc_o[15], 
        Vc_o[14], Vc_o[13], Vc_o[12], Vc_o[11], Vc_o[10], Vc_o[9], 
        Vc_o[8], Vc_o[7], Vc_o[6], Vc_o[5], Vc_o[4], Vc_o[3], Vc_o[2], 
        Vc_o[1], Vc_o[0]}), .done_o(PWM_SCALING_0_done_o));
    GND GND_Z (.Y(GND));
    FOC_TRANSFORMS_2s_44s_0 MSC_i_35 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FAB_CCC_GL1), .start_clarke_i(GND), 
        .start_park_i(ADC_SCALING_0_done_o), .start_ipark_i(
        SPEED_ID_IQ_PI_1_id_pi_done_o), .start_iclarke_i(GND), .ia_i({
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND}), .ib_i({GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND}), .ialpha_i({ADC_SCALING_0_ia_adc_o[17], 
        ADC_SCALING_0_ia_adc_o[16], ADC_SCALING_0_ia_adc_o[15], 
        ADC_SCALING_0_ia_adc_o[14], ADC_SCALING_0_ia_adc_o[13], 
        ADC_SCALING_0_ia_adc_o[12], ADC_SCALING_0_ia_adc_o[11], 
        ADC_SCALING_0_ia_adc_o[10], ADC_SCALING_0_ia_adc_o[9], 
        ADC_SCALING_0_ia_adc_o[8], ADC_SCALING_0_ia_adc_o[7], 
        ADC_SCALING_0_ia_adc_o[6], ADC_SCALING_0_ia_adc_o[5], 
        ADC_SCALING_0_ia_adc_o[4], ADC_SCALING_0_ia_adc_o[3], 
        ADC_SCALING_0_ia_adc_o[2], ADC_SCALING_0_ia_adc_o[1], GND}), 
        .ibeta_i({ADC_SCALING_0_ib_adc_o[17], 
        ADC_SCALING_0_ib_adc_o[16], ADC_SCALING_0_ib_adc_o[15], 
        ADC_SCALING_0_ib_adc_o[14], ADC_SCALING_0_ib_adc_o[13], 
        ADC_SCALING_0_ib_adc_o[12], ADC_SCALING_0_ib_adc_o[11], 
        ADC_SCALING_0_ib_adc_o[10], ADC_SCALING_0_ib_adc_o[9], 
        ADC_SCALING_0_ib_adc_o[8], ADC_SCALING_0_ib_adc_o[7], 
        ADC_SCALING_0_ib_adc_o[6], ADC_SCALING_0_ib_adc_o[5], 
        ADC_SCALING_0_ib_adc_o[4], ADC_SCALING_0_ib_adc_o[3], 
        ADC_SCALING_0_ib_adc_o_2, ADC_SCALING_0_ib_adc_o[1], GND}), 
        .vd_i({SPEED_ID_IQ_PI_1_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[1], GND}), .vq_i({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1], GND}), .valpha_i({GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND}), .vbeta_i({GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .theta_i({STEPPER_THETA_0_theta_output_o[17], 
        STEPPER_THETA_0_theta_output_o[16], 
        STEPPER_THETA_0_theta_output_o[15], 
        STEPPER_THETA_0_theta_output_o[14], 
        STEPPER_THETA_0_theta_output_o[13], 
        STEPPER_THETA_0_theta_output_o[12], 
        STEPPER_THETA_0_theta_output_o[11], 
        STEPPER_THETA_0_theta_output_o[10], 
        STEPPER_THETA_0_theta_output_o[9], 
        STEPPER_THETA_0_theta_output_o[8], 
        STEPPER_THETA_0_theta_output_o[7], 
        STEPPER_THETA_0_theta_output_o[6], 
        STEPPER_THETA_0_theta_output_o[5], 
        STEPPER_THETA_0_theta_output_o[4], 
        STEPPER_THETA_0_theta_output_o[3], 
        STEPPER_THETA_0_theta_output_o[2], 
        STEPPER_THETA_0_theta_output_o[1], 
        STEPPER_THETA_0_theta_output_o[0]}), .clarke_done_o(
        clarke_done_o), .park_done_o(FOC_TRANSFORMS_0_park_done_o), 
        .ipark_done_o(FOC_TRANSFORMS_1_ipark_done_o), .iclarke_done_o(
        iclarke_done_o), .ialpha_o({ialpha_o[17], ialpha_o[16], 
        ialpha_o[15], ialpha_o[14], ialpha_o[13], ialpha_o[12], 
        ialpha_o[11], ialpha_o[10], ialpha_o[9], ialpha_o[8], 
        ialpha_o[7], ialpha_o[6], ialpha_o[5], ialpha_o[4], 
        ialpha_o[3], ialpha_o[2], ialpha_o[1], ialpha_o[0]}), .ibeta_o({
        ibeta_o[17], ibeta_o[16], ibeta_o[15], ibeta_o[14], 
        ibeta_o[13], ibeta_o[12], ibeta_o[11], ibeta_o[10], ibeta_o[9], 
        ibeta_o[8], ibeta_o[7], ibeta_o[6], ibeta_o[5], ibeta_o[4], 
        ibeta_o[3], ibeta_o[2], ibeta_o[1], ibeta_o[0]}), .id_o({
        FOC_TRANSFORMS_0_id_o[17], FOC_TRANSFORMS_0_id_o[16], 
        FOC_TRANSFORMS_0_id_o[15], FOC_TRANSFORMS_0_id_o[14], 
        FOC_TRANSFORMS_0_id_o[13], FOC_TRANSFORMS_0_id_o[12], 
        FOC_TRANSFORMS_0_id_o_11, FOC_TRANSFORMS_0_id_o[10], 
        FOC_TRANSFORMS_0_id_o[9], FOC_TRANSFORMS_0_id_o[8], 
        FOC_TRANSFORMS_0_id_o[7], FOC_TRANSFORMS_0_id_o[6], 
        FOC_TRANSFORMS_0_id_o[5], FOC_TRANSFORMS_0_id_o[4], 
        FOC_TRANSFORMS_0_id_o[3], FOC_TRANSFORMS_0_id_o_2, 
        FOC_TRANSFORMS_0_id_o[1], FOC_TRANSFORMS_0_id_o[0]}), .iq_o({
        FOC_TRANSFORMS_0_iq_o[17], FOC_TRANSFORMS_0_iq_o[16], 
        FOC_TRANSFORMS_0_iq_o[15], FOC_TRANSFORMS_0_iq_o[14], 
        FOC_TRANSFORMS_0_iq_o[13], FOC_TRANSFORMS_0_iq_o[12], 
        FOC_TRANSFORMS_0_iq_o_11, FOC_TRANSFORMS_0_iq_o[10], 
        FOC_TRANSFORMS_0_iq_o[9], FOC_TRANSFORMS_0_iq_o[8], 
        FOC_TRANSFORMS_0_iq_o[7], FOC_TRANSFORMS_0_iq_o[6], 
        FOC_TRANSFORMS_0_iq_o[5], FOC_TRANSFORMS_0_iq_o[4], 
        FOC_TRANSFORMS_0_iq_o[3], FOC_TRANSFORMS_0_iq_o_2, 
        FOC_TRANSFORMS_0_iq_o[1], FOC_TRANSFORMS_0_iq_o[0]}), 
        .valpha_o({FOC_TRANSFORMS_1_valpha_o[17], 
        FOC_TRANSFORMS_1_valpha_o[16], FOC_TRANSFORMS_1_valpha_o[15], 
        FOC_TRANSFORMS_1_valpha_o[14], FOC_TRANSFORMS_1_valpha_o[13], 
        FOC_TRANSFORMS_1_valpha_o[12], FOC_TRANSFORMS_1_valpha_o_11, 
        FOC_TRANSFORMS_1_valpha_o[10], FOC_TRANSFORMS_1_valpha_o[9], 
        FOC_TRANSFORMS_1_valpha_o[8], FOC_TRANSFORMS_1_valpha_o[7], 
        FOC_TRANSFORMS_1_valpha_o[6], FOC_TRANSFORMS_1_valpha_o[5], 
        FOC_TRANSFORMS_1_valpha_o[4], FOC_TRANSFORMS_1_valpha_o[3], 
        FOC_TRANSFORMS_1_valpha_o[2], FOC_TRANSFORMS_1_valpha_o[1], 
        FOC_TRANSFORMS_1_valpha_o[0]}), .vbeta_o({
        FOC_TRANSFORMS_0_vbeta_o[17], FOC_TRANSFORMS_0_vbeta_o[16], 
        FOC_TRANSFORMS_0_vbeta_o[15], FOC_TRANSFORMS_0_vbeta_o[14], 
        FOC_TRANSFORMS_0_vbeta_o[13], FOC_TRANSFORMS_0_vbeta_o[12], 
        FOC_TRANSFORMS_0_vbeta_o_11, FOC_TRANSFORMS_0_vbeta_o[10], 
        FOC_TRANSFORMS_0_vbeta_o[9], FOC_TRANSFORMS_0_vbeta_o[8], 
        FOC_TRANSFORMS_0_vbeta_o[7], FOC_TRANSFORMS_0_vbeta_o[6], 
        FOC_TRANSFORMS_0_vbeta_o[5], FOC_TRANSFORMS_0_vbeta_o[4], 
        FOC_TRANSFORMS_0_vbeta_o[3], FOC_TRANSFORMS_0_vbeta_o[2], 
        FOC_TRANSFORMS_0_vbeta_o[1], FOC_TRANSFORMS_0_vbeta_o[0]}), 
        .va_o({va_o[17], va_o[16], va_o[15], va_o[14], va_o[13], 
        va_o[12], va_o[11], va_o[10], va_o[9], va_o[8], va_o[7], 
        va_o[6], va_o[5], va_o[4], va_o[3], va_o[2], va_o[1], va_o[0]})
        , .vb_o({vb_o[17], vb_o[16], vb_o[15], vb_o[14], vb_o[13], 
        vb_o[12], vb_o[11], vb_o[10], vb_o[9], vb_o[8], vb_o[7], 
        vb_o[6], vb_o[5], vb_o[4], vb_o[3], vb_o[2], vb_o[1], vb_o[0]})
        , .vc_o({vc_o[17], vc_o[16], vc_o[15], vc_o[14], vc_o[13], 
        vc_o[12], vc_o[11], vc_o[10], vc_o[9], vc_o[8], vc_o[7], 
        vc_o[6], vc_o[5], vc_o[4], vc_o[3], vc_o[2], vc_o[1], vc_o[0]})
        );
    SEQ_CONTROLLER_Z1_layer1_0 SEQ_CONTROLLER_0 (
        .SEQ_CONTROLLER_1_state_o_0({SEQ_CONTROLLER_1_state_o_0[3], 
        SEQ_CONTROLLER_1_state_o_0_2, SEQ_CONTROLLER_1_state_o_0[1], 
        SEQ_CONTROLLER_1_state_o_0[0]}), 
        .apb3_if_st_0_seq_cntl_config_o({
        apb3_if_st_0_seq_cntl_config_o[2], 
        apb3_if_st_0_seq_cntl_config_o[1]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FAB_CCC_GL1(
        MC_System_0_FAB_CCC_GL1), .SEQ_CONTROLLER_1_adc_start_o_0(
        SEQ_CONTROLLER_1_adc_start_o_0), .apb3_if_st_0_start_motor_o(
        apb3_if_st_0_start_motor_o), .apb3_if_st_0_stop_motor_o(
        apb3_if_st_0_stop_motor_o), .ADC_SCALING_0_calib_done_o(
        ADC_SCALING_0_calib_done_o), .A1_PWM_WL_O_c_i_0(
        A1_PWM_WL_O_c_i_0), .ADC_SCALING_0_over_current_fault_o(
        ADC_SCALING_0_over_current_fault_o), .A1_PWM_WL_O_c(
        A1_PWM_WL_O_c), .N_614_i_0(N_614_i_0), .PWM_SCALING_0_done_o(
        PWM_SCALING_0_done_o), .PWM3PH_0_midmatch_o(
        PWM3PH_0_midmatch_o));
    ADC_SCALING_0s_12s_2s_8192_5_44s_0_2_3_0 MSC_i_42 (.reset_i(
        MC_System_0_FIC_0_LOCK), .sys_clk_i(MC_System_0_FAB_CCC_GL1), 
        .adc_results_rdy_i(adc_interface_0_results_rdy_o), 
        .adc_scale_val_i({apb3_if_st_0_adc_scale_val_o[17], 
        apb3_if_st_0_adc_scale_val_o[16], 
        apb3_if_st_0_adc_scale_val_o[15], 
        apb3_if_st_0_adc_scale_val_o[14], 
        apb3_if_st_0_adc_scale_val_o[13], 
        apb3_if_st_0_adc_scale_val_o[12], 
        apb3_if_st_0_adc_scale_val_o[11], 
        apb3_if_st_0_adc_scale_val_o[10], 
        apb3_if_st_0_adc_scale_val_o[9], 
        apb3_if_st_0_adc_scale_val_o[8], 
        apb3_if_st_0_adc_scale_val_o[7], 
        apb3_if_st_0_adc_scale_val_o[6], 
        apb3_if_st_0_adc_scale_val_o[5], 
        apb3_if_st_0_adc_scale_val_o[4], 
        apb3_if_st_0_adc_scale_val_o[3], 
        apb3_if_st_0_adc_scale_val_o[2], 
        apb3_if_st_0_adc_scale_val_o[1], 
        apb3_if_st_0_adc_scale_val_o[0]}), .adc_result_ch0_i({
        adc_interface_0_result_ch0_o[11], 
        adc_interface_0_result_ch0_o[10], 
        adc_interface_0_result_ch0_o[9], 
        adc_interface_0_result_ch0_o[8], 
        adc_interface_0_result_ch0_o[7], 
        adc_interface_0_result_ch0_o[6], 
        adc_interface_0_result_ch0_o[5], 
        adc_interface_0_result_ch0_o[4], 
        adc_interface_0_result_ch0_o[3], 
        adc_interface_0_result_ch0_o_2, 
        adc_interface_0_result_ch0_o[1], 
        adc_interface_0_result_ch0_o[0]}), .adc_result_ch1_i({
        adc_interface_0_result_ch2_o[11], 
        adc_interface_0_result_ch2_o[10], 
        adc_interface_0_result_ch2_o[9], 
        adc_interface_0_result_ch2_o[8], 
        adc_interface_0_result_ch2_o[7], 
        adc_interface_0_result_ch2_o[6], 
        adc_interface_0_result_ch2_o[5], 
        adc_interface_0_result_ch2_o[4], 
        adc_interface_0_result_ch2_o[3], 
        adc_interface_0_result_ch2_o_2, 
        adc_interface_0_result_ch2_o[1], 
        adc_interface_0_result_ch2_o[0]}), .fault_threshold_i({
        apb3_if_st_0_adc_oc_thresh_o[17], 
        apb3_if_st_0_adc_oc_thresh_o[16], 
        apb3_if_st_0_adc_oc_thresh_o[15], 
        apb3_if_st_0_adc_oc_thresh_o[14], 
        apb3_if_st_0_adc_oc_thresh_o[13], 
        apb3_if_st_0_adc_oc_thresh_o[12], 
        apb3_if_st_0_adc_oc_thresh_o[11], 
        apb3_if_st_0_adc_oc_thresh_o[10], 
        apb3_if_st_0_adc_oc_thresh_o[9], 
        apb3_if_st_0_adc_oc_thresh_o[8], 
        apb3_if_st_0_adc_oc_thresh_o[7], 
        apb3_if_st_0_adc_oc_thresh_o[6], 
        apb3_if_st_0_adc_oc_thresh_o[5], 
        apb3_if_st_0_adc_oc_thresh_o[4], 
        apb3_if_st_0_adc_oc_thresh_o[3], 
        apb3_if_st_0_adc_oc_thresh_o[2], 
        apb3_if_st_0_adc_oc_thresh_o[1], 
        apb3_if_st_0_adc_oc_thresh_o[0]}), .done_o(
        ADC_SCALING_0_done_o), .calib_done_o(
        ADC_SCALING_0_calib_done_o), .over_current_fault_o(
        ADC_SCALING_0_over_current_fault_o), .ia_adc_o({
        ADC_SCALING_0_ia_adc_o[17], ADC_SCALING_0_ia_adc_o[16], 
        ADC_SCALING_0_ia_adc_o[15], ADC_SCALING_0_ia_adc_o[14], 
        ADC_SCALING_0_ia_adc_o[13], ADC_SCALING_0_ia_adc_o[12], 
        ADC_SCALING_0_ia_adc_o[11], ADC_SCALING_0_ia_adc_o[10], 
        ADC_SCALING_0_ia_adc_o[9], ADC_SCALING_0_ia_adc_o[8], 
        ADC_SCALING_0_ia_adc_o[7], ADC_SCALING_0_ia_adc_o[6], 
        ADC_SCALING_0_ia_adc_o[5], ADC_SCALING_0_ia_adc_o[4], 
        ADC_SCALING_0_ia_adc_o[3], ADC_SCALING_0_ia_adc_o[2], 
        ADC_SCALING_0_ia_adc_o[1], ADC_SCALING_0_ia_adc_o[0]}), 
        .ib_adc_o({ADC_SCALING_0_ib_adc_o[17], 
        ADC_SCALING_0_ib_adc_o[16], ADC_SCALING_0_ib_adc_o[15], 
        ADC_SCALING_0_ib_adc_o[14], ADC_SCALING_0_ib_adc_o[13], 
        ADC_SCALING_0_ib_adc_o[12], ADC_SCALING_0_ib_adc_o[11], 
        ADC_SCALING_0_ib_adc_o[10], ADC_SCALING_0_ib_adc_o[9], 
        ADC_SCALING_0_ib_adc_o[8], ADC_SCALING_0_ib_adc_o[7], 
        ADC_SCALING_0_ib_adc_o[6], ADC_SCALING_0_ib_adc_o[5], 
        ADC_SCALING_0_ib_adc_o[4], ADC_SCALING_0_ib_adc_o[3], 
        ADC_SCALING_0_ib_adc_o_2, ADC_SCALING_0_ib_adc_o[1], 
        ADC_SCALING_0_ib_adc_o[0]}));
    
        work_apb3_if_st_apb3_if_st_32_12_6_18_2_g_APB3_IF_DATA_WIDTHg_CONST_WIDTHg_ADC_CONFIG_REG_WIDTHg_STD_IO_WIDTH 
        apb3_if_st_0 (.apb3_if_st_0_adc_oc_thresh_o({
        apb3_if_st_0_adc_oc_thresh_o[17], 
        apb3_if_st_0_adc_oc_thresh_o[16], 
        apb3_if_st_0_adc_oc_thresh_o[15], 
        apb3_if_st_0_adc_oc_thresh_o[14], 
        apb3_if_st_0_adc_oc_thresh_o[13], 
        apb3_if_st_0_adc_oc_thresh_o[12], 
        apb3_if_st_0_adc_oc_thresh_o[11], 
        apb3_if_st_0_adc_oc_thresh_o[10], 
        apb3_if_st_0_adc_oc_thresh_o[9], 
        apb3_if_st_0_adc_oc_thresh_o[8], 
        apb3_if_st_0_adc_oc_thresh_o[7], 
        apb3_if_st_0_adc_oc_thresh_o[6], 
        apb3_if_st_0_adc_oc_thresh_o[5], 
        apb3_if_st_0_adc_oc_thresh_o[4], 
        apb3_if_st_0_adc_oc_thresh_o[3], 
        apb3_if_st_0_adc_oc_thresh_o[2], 
        apb3_if_st_0_adc_oc_thresh_o[1], 
        apb3_if_st_0_adc_oc_thresh_o[0]}), 
        .apb3_if_st_0_adc_scale_val_o({
        apb3_if_st_0_adc_scale_val_o[17], 
        apb3_if_st_0_adc_scale_val_o[16], 
        apb3_if_st_0_adc_scale_val_o[15], 
        apb3_if_st_0_adc_scale_val_o[14], 
        apb3_if_st_0_adc_scale_val_o[13], 
        apb3_if_st_0_adc_scale_val_o[12], 
        apb3_if_st_0_adc_scale_val_o[11], 
        apb3_if_st_0_adc_scale_val_o[10], 
        apb3_if_st_0_adc_scale_val_o[9], 
        apb3_if_st_0_adc_scale_val_o[8], 
        apb3_if_st_0_adc_scale_val_o[7], 
        apb3_if_st_0_adc_scale_val_o[6], 
        apb3_if_st_0_adc_scale_val_o[5], 
        apb3_if_st_0_adc_scale_val_o[4], 
        apb3_if_st_0_adc_scale_val_o[3], 
        apb3_if_st_0_adc_scale_val_o[2], 
        apb3_if_st_0_adc_scale_val_o[1], 
        apb3_if_st_0_adc_scale_val_o[0]}), .apb3_if_st_0_id_ref_val_o({
        apb3_if_st_0_id_ref_val_o[17], apb3_if_st_0_id_ref_val_o[16], 
        apb3_if_st_0_id_ref_val_o[15], apb3_if_st_0_id_ref_val_o[14], 
        apb3_if_st_0_id_ref_val_o[13], apb3_if_st_0_id_ref_val_o[12], 
        apb3_if_st_0_id_ref_val_o[11], apb3_if_st_0_id_ref_val_o[10], 
        apb3_if_st_0_id_ref_val_o[9], apb3_if_st_0_id_ref_val_o[8], 
        apb3_if_st_0_id_ref_val_o[7], apb3_if_st_0_id_ref_val_o[6], 
        apb3_if_st_0_id_ref_val_o[5], apb3_if_st_0_id_ref_val_o[4], 
        apb3_if_st_0_id_ref_val_o[3], apb3_if_st_0_id_ref_val_o[2], 
        apb3_if_st_0_id_ref_val_o[1], apb3_if_st_0_id_ref_val_o[0]}), 
        .apb3_if_st_0_idq_pi_ki_o({apb3_if_st_0_idq_pi_ki_o[17], 
        apb3_if_st_0_idq_pi_ki_o[16], apb3_if_st_0_idq_pi_ki_o[15], 
        apb3_if_st_0_idq_pi_ki_o[14], apb3_if_st_0_idq_pi_ki_o[13], 
        apb3_if_st_0_idq_pi_ki_o[12], apb3_if_st_0_idq_pi_ki_o[11], 
        apb3_if_st_0_idq_pi_ki_o[10], apb3_if_st_0_idq_pi_ki_o[9], 
        apb3_if_st_0_idq_pi_ki_o[8], apb3_if_st_0_idq_pi_ki_o[7], 
        apb3_if_st_0_idq_pi_ki_o[6], apb3_if_st_0_idq_pi_ki_o[5], 
        apb3_if_st_0_idq_pi_ki_o[4], apb3_if_st_0_idq_pi_ki_o[3], 
        apb3_if_st_0_idq_pi_ki_o[2], apb3_if_st_0_idq_pi_ki_o[1], 
        apb3_if_st_0_idq_pi_ki_o[0]}), .apb3_if_st_0_idq_pi_kp_o({
        apb3_if_st_0_idq_pi_kp_o[17], apb3_if_st_0_idq_pi_kp_o[16], 
        apb3_if_st_0_idq_pi_kp_o[15], apb3_if_st_0_idq_pi_kp_o[14], 
        apb3_if_st_0_idq_pi_kp_o[13], apb3_if_st_0_idq_pi_kp_o[12], 
        apb3_if_st_0_idq_pi_kp_o[11], apb3_if_st_0_idq_pi_kp_o[10], 
        apb3_if_st_0_idq_pi_kp_o[9], apb3_if_st_0_idq_pi_kp_o[8], 
        apb3_if_st_0_idq_pi_kp_o[7], apb3_if_st_0_idq_pi_kp_o[6], 
        apb3_if_st_0_idq_pi_kp_o[5], apb3_if_st_0_idq_pi_kp_o[4], 
        apb3_if_st_0_idq_pi_kp_o[3], apb3_if_st_0_idq_pi_kp_o[2], 
        apb3_if_st_0_idq_pi_kp_o[1], apb3_if_st_0_idq_pi_kp_o[0]}), 
        .apb3_if_st_0_pwm_dead_time_val_o({
        apb3_if_st_0_pwm_dead_time_val_o[17], 
        apb3_if_st_0_pwm_dead_time_val_o[16], 
        apb3_if_st_0_pwm_dead_time_val_o[15], 
        apb3_if_st_0_pwm_dead_time_val_o[14], 
        apb3_if_st_0_pwm_dead_time_val_o[13], 
        apb3_if_st_0_pwm_dead_time_val_o[12], 
        apb3_if_st_0_pwm_dead_time_val_o[11], 
        apb3_if_st_0_pwm_dead_time_val_o[10], 
        apb3_if_st_0_pwm_dead_time_val_o[9], 
        apb3_if_st_0_pwm_dead_time_val_o[8], 
        apb3_if_st_0_pwm_dead_time_val_o[7], 
        apb3_if_st_0_pwm_dead_time_val_o[6], 
        apb3_if_st_0_pwm_dead_time_val_o[5], 
        apb3_if_st_0_pwm_dead_time_val_o[4], 
        apb3_if_st_0_pwm_dead_time_val_o[3], 
        apb3_if_st_0_pwm_dead_time_val_o[2], 
        apb3_if_st_0_pwm_dead_time_val_o[1], 
        apb3_if_st_0_pwm_dead_time_val_o[0]}), 
        .apb3_if_st_0_pwm_delay_time_val_o({
        apb3_if_st_0_pwm_delay_time_val_o[17], 
        apb3_if_st_0_pwm_delay_time_val_o[16], 
        apb3_if_st_0_pwm_delay_time_val_o[15], 
        apb3_if_st_0_pwm_delay_time_val_o[14], 
        apb3_if_st_0_pwm_delay_time_val_o[13], 
        apb3_if_st_0_pwm_delay_time_val_o[12], 
        apb3_if_st_0_pwm_delay_time_val_o[11], 
        apb3_if_st_0_pwm_delay_time_val_o[10], 
        apb3_if_st_0_pwm_delay_time_val_o[9], 
        apb3_if_st_0_pwm_delay_time_val_o[8], 
        apb3_if_st_0_pwm_delay_time_val_o[7], 
        apb3_if_st_0_pwm_delay_time_val_o[6], 
        apb3_if_st_0_pwm_delay_time_val_o[5], 
        apb3_if_st_0_pwm_delay_time_val_o[4], 
        apb3_if_st_0_pwm_delay_time_val_o[3], 
        apb3_if_st_0_pwm_delay_time_val_o[2], 
        apb3_if_st_0_pwm_delay_time_val_o[1], 
        apb3_if_st_0_pwm_delay_time_val_o[0]}), 
        .apb3_if_st_0_pwm_period_val_o({
        apb3_if_st_0_pwm_period_val_o[17], 
        apb3_if_st_0_pwm_period_val_o[16], 
        apb3_if_st_0_pwm_period_val_o[15], 
        apb3_if_st_0_pwm_period_val_o[14], 
        apb3_if_st_0_pwm_period_val_o[13], 
        apb3_if_st_0_pwm_period_val_o[12], 
        apb3_if_st_0_pwm_period_val_o[11], 
        apb3_if_st_0_pwm_period_val_o[10], 
        apb3_if_st_0_pwm_period_val_o[9], 
        apb3_if_st_0_pwm_period_val_o[8], 
        apb3_if_st_0_pwm_period_val_o[7], 
        apb3_if_st_0_pwm_period_val_o[6], 
        apb3_if_st_0_pwm_period_val_o[5], 
        apb3_if_st_0_pwm_period_val_o[4], 
        apb3_if_st_0_pwm_period_val_o[3], 
        apb3_if_st_0_pwm_period_val_o[2], 
        apb3_if_st_0_pwm_period_val_o[1], 
        apb3_if_st_0_pwm_period_val_o[0]}), .apb3_if_st_0_sqmng_dv_o({
        apb3_if_st_0_sqmng_dv_o[17], apb3_if_st_0_sqmng_dv_o[16], 
        apb3_if_st_0_sqmng_dv_o[15], apb3_if_st_0_sqmng_dv_o[14], 
        apb3_if_st_0_sqmng_dv_o[13], apb3_if_st_0_sqmng_dv_o[12], 
        apb3_if_st_0_sqmng_dv_o[11], apb3_if_st_0_sqmng_dv_o[10], 
        apb3_if_st_0_sqmng_dv_o[9], apb3_if_st_0_sqmng_dv_o[8], 
        apb3_if_st_0_sqmng_dv_o[7], apb3_if_st_0_sqmng_dv_o[6], 
        apb3_if_st_0_sqmng_dv_o[5], apb3_if_st_0_sqmng_dv_o[4], 
        apb3_if_st_0_sqmng_dv_o[3], apb3_if_st_0_sqmng_dv_o[2], 
        apb3_if_st_0_sqmng_dv_o[1], apb3_if_st_0_sqmng_dv_o[0]}), 
        .apb3_if_st_0_theta_gen_rate_limit_o({
        apb3_if_st_0_theta_gen_rate_limit_o[17], 
        apb3_if_st_0_theta_gen_rate_limit_o[16], 
        apb3_if_st_0_theta_gen_rate_limit_o[15], 
        apb3_if_st_0_theta_gen_rate_limit_o[14], 
        apb3_if_st_0_theta_gen_rate_limit_o[13], 
        apb3_if_st_0_theta_gen_rate_limit_o[12], 
        apb3_if_st_0_theta_gen_rate_limit_o[11], 
        apb3_if_st_0_theta_gen_rate_limit_o[10], 
        apb3_if_st_0_theta_gen_rate_limit_o[9], 
        apb3_if_st_0_theta_gen_rate_limit_o[8], 
        apb3_if_st_0_theta_gen_rate_limit_o[7], 
        apb3_if_st_0_theta_gen_rate_limit_o[6], 
        apb3_if_st_0_theta_gen_rate_limit_o[5], 
        apb3_if_st_0_theta_gen_rate_limit_o[4], 
        apb3_if_st_0_theta_gen_rate_limit_o[3], 
        apb3_if_st_0_theta_gen_rate_limit_o[2], 
        apb3_if_st_0_theta_gen_rate_limit_o[1], 
        apb3_if_st_0_theta_gen_rate_limit_o[0]}), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA({
        MC_System_0_AMBA_SLAVE_1_PWDATA[23], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[22], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[21], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[20], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[19], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[18], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]}), 
        .apb3_if_st_0_theta_gen_slew_count_o({
        apb3_if_st_0_theta_gen_slew_count_o[17], 
        apb3_if_st_0_theta_gen_slew_count_o[16], 
        apb3_if_st_0_theta_gen_slew_count_o[15], 
        apb3_if_st_0_theta_gen_slew_count_o[14], 
        apb3_if_st_0_theta_gen_slew_count_o[13], 
        apb3_if_st_0_theta_gen_slew_count_o[12], 
        apb3_if_st_0_theta_gen_slew_count_o[11], 
        apb3_if_st_0_theta_gen_slew_count_o[10], 
        apb3_if_st_0_theta_gen_slew_count_o[9], 
        apb3_if_st_0_theta_gen_slew_count_o[8], 
        apb3_if_st_0_theta_gen_slew_count_o[7], 
        apb3_if_st_0_theta_gen_slew_count_o[6], 
        apb3_if_st_0_theta_gen_slew_count_o[5], 
        apb3_if_st_0_theta_gen_slew_count_o[4], 
        apb3_if_st_0_theta_gen_slew_count_o[3], 
        apb3_if_st_0_theta_gen_slew_count_o[2], 
        apb3_if_st_0_theta_gen_slew_count_o[1], 
        apb3_if_st_0_theta_gen_slew_count_o[0]}), 
        .apb3_if_st_0_theta_gen_cmd_step_no_o_0({
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[23], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[22], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[21], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[20], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[19], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[18], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[17], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[16], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[15], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[14], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[13], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[12], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[11], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[10], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[9], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[8], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[7], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[6], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[5], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[4], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[3], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[2], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[1], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[0]}), 
        .apb3_if_st_0_adc_control_reg_val_o({
        apb3_if_st_0_adc_control_reg_val_o[5], 
        apb3_if_st_0_adc_control_reg_val_o[4], 
        apb3_if_st_0_adc_control_reg_val_o[3], 
        apb3_if_st_0_adc_control_reg_val_o[2], 
        apb3_if_st_0_adc_control_reg_val_o[1], 
        apb3_if_st_0_adc_control_reg_val_o[0]}), 
        .apb3_if_st_0_seq_cntl_config_o({
        apb3_if_st_0_seq_cntl_config_o[2], 
        apb3_if_st_0_seq_cntl_config_o[1]}), 
        .apb3_if_st_0_adc_channel_ch0_o({
        apb3_if_st_0_adc_channel_ch0_o[15], 
        apb3_if_st_0_adc_channel_ch0_o[14], 
        apb3_if_st_0_adc_channel_ch0_o[13], 
        apb3_if_st_0_adc_channel_ch0_o[12], 
        apb3_if_st_0_adc_channel_ch0_o[11], 
        apb3_if_st_0_adc_channel_ch0_o[10], 
        apb3_if_st_0_adc_channel_ch0_o[9], 
        apb3_if_st_0_adc_channel_ch0_o[8], 
        apb3_if_st_0_adc_channel_ch0_o[7], 
        apb3_if_st_0_adc_channel_ch0_o[6], 
        apb3_if_st_0_adc_channel_ch0_o[5], 
        apb3_if_st_0_adc_channel_ch0_o[4], 
        apb3_if_st_0_adc_channel_ch0_o[3], 
        apb3_if_st_0_adc_channel_ch0_o[2], 
        apb3_if_st_0_adc_channel_ch0_o[1], 
        apb3_if_st_0_adc_channel_ch0_o[0]}), 
        .apb3_if_st_0_adc_channel_ch1_o({
        apb3_if_st_0_adc_channel_ch1_o[15], 
        apb3_if_st_0_adc_channel_ch1_o[14], 
        apb3_if_st_0_adc_channel_ch1_o[13], 
        apb3_if_st_0_adc_channel_ch1_o[12], 
        apb3_if_st_0_adc_channel_ch1_o[11], 
        apb3_if_st_0_adc_channel_ch1_o[10], 
        apb3_if_st_0_adc_channel_ch1_o[9], 
        apb3_if_st_0_adc_channel_ch1_o[8], 
        apb3_if_st_0_adc_channel_ch1_o[7], 
        apb3_if_st_0_adc_channel_ch1_o[6], 
        apb3_if_st_0_adc_channel_ch1_o[5], 
        apb3_if_st_0_adc_channel_ch1_o[4], 
        apb3_if_st_0_adc_channel_ch1_o[3], 
        apb3_if_st_0_adc_channel_ch1_o[2], 
        apb3_if_st_0_adc_channel_ch1_o[1], 
        apb3_if_st_0_adc_channel_ch1_o[0]}), 
        .apb3_if_st_0_adc_channel_ch2_o({
        apb3_if_st_0_adc_channel_ch2_o[15], 
        apb3_if_st_0_adc_channel_ch2_o[14], 
        apb3_if_st_0_adc_channel_ch2_o[13], 
        apb3_if_st_0_adc_channel_ch2_o[12], 
        apb3_if_st_0_adc_channel_ch2_o[11], 
        apb3_if_st_0_adc_channel_ch2_o[10], 
        apb3_if_st_0_adc_channel_ch2_o[9], 
        apb3_if_st_0_adc_channel_ch2_o[8], 
        apb3_if_st_0_adc_channel_ch2_o[7], 
        apb3_if_st_0_adc_channel_ch2_o[6], 
        apb3_if_st_0_adc_channel_ch2_o[5], 
        apb3_if_st_0_adc_channel_ch2_o[4], 
        apb3_if_st_0_adc_channel_ch2_o[3], 
        apb3_if_st_0_adc_channel_ch2_o[2], 
        apb3_if_st_0_adc_channel_ch2_o[1], 
        apb3_if_st_0_adc_channel_ch2_o[0]}), 
        .apb3_if_st_0_adc_channel_ch3_o({
        apb3_if_st_0_adc_channel_ch3_o[15], 
        apb3_if_st_0_adc_channel_ch3_o[14], 
        apb3_if_st_0_adc_channel_ch3_o[13], 
        apb3_if_st_0_adc_channel_ch3_o[12], 
        apb3_if_st_0_adc_channel_ch3_o[11], 
        apb3_if_st_0_adc_channel_ch3_o[10], 
        apb3_if_st_0_adc_channel_ch3_o[9], 
        apb3_if_st_0_adc_channel_ch3_o[8], 
        apb3_if_st_0_adc_channel_ch3_o[7], 
        apb3_if_st_0_adc_channel_ch3_o[6], 
        apb3_if_st_0_adc_channel_ch3_o[5], 
        apb3_if_st_0_adc_channel_ch3_o[4], 
        apb3_if_st_0_adc_channel_ch3_o[3], 
        apb3_if_st_0_adc_channel_ch3_o[2], 
        apb3_if_st_0_adc_channel_ch3_o[1], 
        apb3_if_st_0_adc_channel_ch3_o[0]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR({
        MC_System_0_AMBA_SLAVE_1_PADDR[11], 
        MC_System_0_AMBA_SLAVE_1_PADDR[10], 
        MC_System_0_AMBA_SLAVE_1_PADDR[9], 
        MC_System_0_AMBA_SLAVE_1_PADDR[8], 
        MC_System_0_AMBA_SLAVE_1_PADDR[7], 
        MC_System_0_AMBA_SLAVE_1_PADDR[6], 
        MC_System_0_AMBA_SLAVE_1_PADDR[5], 
        MC_System_0_AMBA_SLAVE_1_PADDR[4], 
        MC_System_0_AMBA_SLAVE_1_PADDR[3], 
        MC_System_0_AMBA_SLAVE_1_PADDR[2], 
        MC_System_0_AMBA_SLAVE_1_PADDR[1], 
        MC_System_0_AMBA_SLAVE_1_PADDR[0]}), .prdata_o_1_0_a2_7_0({
        prdata_o_1_0_a2_7_0[3]}), .adc_interface_0_result_ch2_o_11(
        adc_interface_0_result_ch2_o[11]), 
        .adc_interface_0_result_ch2_o_0(
        adc_interface_0_result_ch2_o[0]), 
        .adc_interface_0_result_ch2_o_9(
        adc_interface_0_result_ch2_o[9]), 
        .adc_interface_0_result_ch2_o_6(
        adc_interface_0_result_ch2_o[6]), 
        .adc_interface_0_result_ch2_o_10(
        adc_interface_0_result_ch2_o[10]), 
        .adc_interface_0_result_ch2_o_1(
        adc_interface_0_result_ch2_o[1]), 
        .adc_interface_0_result_ch2_o_5(
        adc_interface_0_result_ch2_o[5]), 
        .adc_interface_0_result_ch2_o_4(
        adc_interface_0_result_ch2_o[4]), 
        .adc_interface_0_result_ch2_o_7(
        adc_interface_0_result_ch2_o[7]), 
        .adc_interface_0_result_ch2_o_3(
        adc_interface_0_result_ch2_o[3]), 
        .adc_interface_0_result_ch2_o_8(
        adc_interface_0_result_ch2_o[8]), 
        .adc_measurements_0_adc_result_ch3_o_11(
        adc_measurements_0_adc_result_ch3_o[11]), 
        .adc_measurements_0_adc_result_ch3_o_0(
        adc_measurements_0_adc_result_ch3_o[0]), 
        .adc_measurements_0_adc_result_ch3_o_9(
        adc_measurements_0_adc_result_ch3_o[9]), 
        .adc_measurements_0_adc_result_ch3_o_6(
        adc_measurements_0_adc_result_ch3_o[6]), 
        .adc_measurements_0_adc_result_ch3_o_10(
        adc_measurements_0_adc_result_ch3_o[10]), 
        .adc_measurements_0_adc_result_ch3_o_1(
        adc_measurements_0_adc_result_ch3_o[1]), 
        .adc_measurements_0_adc_result_ch3_o_5(
        adc_measurements_0_adc_result_ch3_o[5]), 
        .adc_measurements_0_adc_result_ch3_o_4(
        adc_measurements_0_adc_result_ch3_o[4]), 
        .adc_measurements_0_adc_result_ch3_o_7(
        adc_measurements_0_adc_result_ch3_o[7]), 
        .adc_measurements_0_adc_result_ch3_o_3(
        adc_measurements_0_adc_result_ch3_o[3]), 
        .adc_measurements_0_adc_result_ch3_o_8(
        adc_measurements_0_adc_result_ch3_o[8]), .prdata_o_1_iv_12_0_2({
        prdata_o_1_iv_12_0_2[3]}), .prdata_o_1_iv_12_1({
        prdata_o_1_iv_12_1[3]}), .STEPPER_THETA_0_theta_output_o({
        STEPPER_THETA_0_theta_output_o[17], 
        STEPPER_THETA_0_theta_output_o[16], 
        STEPPER_THETA_0_theta_output_o[15], 
        STEPPER_THETA_0_theta_output_o[14], 
        STEPPER_THETA_0_theta_output_o[13], 
        STEPPER_THETA_0_theta_output_o[12], 
        STEPPER_THETA_0_theta_output_o[11], 
        STEPPER_THETA_0_theta_output_o[10], 
        STEPPER_THETA_0_theta_output_o[9], 
        STEPPER_THETA_0_theta_output_o[8], 
        STEPPER_THETA_0_theta_output_o[7], 
        STEPPER_THETA_0_theta_output_o[6], 
        STEPPER_THETA_0_theta_output_o[5], 
        STEPPER_THETA_0_theta_output_o[4], 
        STEPPER_THETA_0_theta_output_o[3], 
        STEPPER_THETA_0_theta_output_o[2], 
        STEPPER_THETA_0_theta_output_o[1], 
        STEPPER_THETA_0_theta_output_o[0]}), 
        .SPEED_ID_IQ_PI_1_id_pi_output_o_m({
        SPEED_ID_IQ_PI_1_id_pi_output_o_m[0]}), 
        .SEQ_CONTROLLER_1_state_o_0_3(SEQ_CONTROLLER_1_state_o_0[3]), 
        .SEQ_CONTROLLER_1_state_o_0_1(SEQ_CONTROLLER_1_state_o_0[1]), 
        .SEQ_CONTROLLER_1_state_o_0_0(SEQ_CONTROLLER_1_state_o_0[0]), 
        .SPEED_ID_IQ_PI_1_id_pi_output_o({
        SPEED_ID_IQ_PI_1_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[1], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[0]}), .prdata_o_1_iv_9({
        prdata_o_1_iv_9[0]}), .adc_interface_0_result_ch0_o_0(
        adc_interface_0_result_ch0_o[0]), 
        .adc_interface_0_result_ch0_o_11(
        adc_interface_0_result_ch0_o[11]), 
        .adc_interface_0_result_ch0_o_1(
        adc_interface_0_result_ch0_o[1]), 
        .adc_interface_0_result_ch0_o_9(
        adc_interface_0_result_ch0_o[9]), 
        .adc_interface_0_result_ch0_o_6(
        adc_interface_0_result_ch0_o[6]), 
        .adc_interface_0_result_ch0_o_10(
        adc_interface_0_result_ch0_o[10]), 
        .adc_interface_0_result_ch0_o_5(
        adc_interface_0_result_ch0_o[5]), 
        .adc_interface_0_result_ch0_o_8(
        adc_interface_0_result_ch0_o[8]), 
        .adc_interface_0_result_ch0_o_4(
        adc_interface_0_result_ch0_o[4]), 
        .adc_interface_0_result_ch0_o_3(
        adc_interface_0_result_ch0_o[3]), 
        .adc_interface_0_result_ch0_o_7(
        adc_interface_0_result_ch0_o[7]), 
        .SPEED_ID_IQ_PI_1_iq_pi_output_o({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1]}), 
        .STEPPER_THETA_1_step_count_o_0(
        STEPPER_THETA_1_step_count_o[0]), 
        .STEPPER_THETA_1_step_count_o_15(
        STEPPER_THETA_1_step_count_o[15]), 
        .STEPPER_THETA_1_step_count_o_14(
        STEPPER_THETA_1_step_count_o[14]), 
        .STEPPER_THETA_1_step_count_o_11(
        STEPPER_THETA_1_step_count_o[11]), 
        .STEPPER_THETA_1_step_count_o_3(
        STEPPER_THETA_1_step_count_o[3]), 
        .STEPPER_THETA_1_step_count_o_7(
        STEPPER_THETA_1_step_count_o[7]), 
        .STEPPER_THETA_1_step_count_o_9(
        STEPPER_THETA_1_step_count_o[9]), 
        .STEPPER_THETA_1_step_count_o_4(
        STEPPER_THETA_1_step_count_o[4]), 
        .STEPPER_THETA_1_step_count_o_5(
        STEPPER_THETA_1_step_count_o[5]), 
        .STEPPER_THETA_1_step_count_o_1(
        STEPPER_THETA_1_step_count_o[1]), 
        .STEPPER_THETA_1_step_count_o_12(
        STEPPER_THETA_1_step_count_o[12]), 
        .STEPPER_THETA_1_step_count_o_10(
        STEPPER_THETA_1_step_count_o[10]), 
        .STEPPER_THETA_1_step_count_o_8(
        STEPPER_THETA_1_step_count_o[8]), 
        .STEPPER_THETA_1_step_count_o_6(
        STEPPER_THETA_1_step_count_o[6]), 
        .STEPPER_THETA_1_step_count_o_16(
        STEPPER_THETA_1_step_count_o[16]), 
        .STEPPER_THETA_1_step_count_o_13(
        STEPPER_THETA_1_step_count_o[13]), 
        .STEPPER_THETA_1_step_count_o_18(
        STEPPER_THETA_1_step_count_o[18]), 
        .STEPPER_THETA_1_step_count_o_19(
        STEPPER_THETA_1_step_count_o[19]), 
        .STEPPER_THETA_1_step_count_o_20(
        STEPPER_THETA_1_step_count_o[20]), 
        .STEPPER_THETA_1_step_count_o_21(
        STEPPER_THETA_1_step_count_o[21]), 
        .STEPPER_THETA_1_step_count_o_22(
        STEPPER_THETA_1_step_count_o[22]), 
        .STEPPER_THETA_1_step_count_o_23(
        STEPPER_THETA_1_step_count_o[23]), 
        .STEPPER_THETA_1_step_count_o_17(
        STEPPER_THETA_1_step_count_o[17]), .ADC_SCALING_0_ib_adc_o_9(
        ADC_SCALING_0_ib_adc_o[9]), .ADC_SCALING_0_ib_adc_o_13(
        ADC_SCALING_0_ib_adc_o[13]), .ADC_SCALING_0_ib_adc_o_16(
        ADC_SCALING_0_ib_adc_o[16]), .ADC_SCALING_0_ib_adc_o_17(
        ADC_SCALING_0_ib_adc_o[17]), .ADC_SCALING_0_ib_adc_o_11(
        ADC_SCALING_0_ib_adc_o[11]), .ADC_SCALING_0_ib_adc_o_7(
        ADC_SCALING_0_ib_adc_o[7]), .ADC_SCALING_0_ib_adc_o_6(
        ADC_SCALING_0_ib_adc_o[6]), .ADC_SCALING_0_ib_adc_o_3(
        ADC_SCALING_0_ib_adc_o[3]), .ADC_SCALING_0_ib_adc_o_15(
        ADC_SCALING_0_ib_adc_o[15]), .ADC_SCALING_0_ib_adc_o_14(
        ADC_SCALING_0_ib_adc_o[14]), .ADC_SCALING_0_ib_adc_o_12(
        ADC_SCALING_0_ib_adc_o[12]), .ADC_SCALING_0_ib_adc_o_8(
        ADC_SCALING_0_ib_adc_o[8]), .ADC_SCALING_0_ib_adc_o_5(
        ADC_SCALING_0_ib_adc_o[5]), .ADC_SCALING_0_ib_adc_o_10(
        ADC_SCALING_0_ib_adc_o[10]), .ADC_SCALING_0_ib_adc_o_4(
        ADC_SCALING_0_ib_adc_o[4]), .ADC_SCALING_0_ib_adc_o_1(
        ADC_SCALING_0_ib_adc_o[1]), .ADC_SCALING_0_ib_adc_o_0(
        ADC_SCALING_0_ib_adc_o[0]), .ADC_SCALING_0_ia_adc_o({
        ADC_SCALING_0_ia_adc_o[17], ADC_SCALING_0_ia_adc_o[16], 
        ADC_SCALING_0_ia_adc_o[15], ADC_SCALING_0_ia_adc_o[14], 
        ADC_SCALING_0_ia_adc_o[13], ADC_SCALING_0_ia_adc_o[12], 
        ADC_SCALING_0_ia_adc_o[11], ADC_SCALING_0_ia_adc_o[10], 
        ADC_SCALING_0_ia_adc_o[9], ADC_SCALING_0_ia_adc_o[8], 
        ADC_SCALING_0_ia_adc_o[7], ADC_SCALING_0_ia_adc_o[6], 
        ADC_SCALING_0_ia_adc_o[5], ADC_SCALING_0_ia_adc_o[4], 
        ADC_SCALING_0_ia_adc_o[3], ADC_SCALING_0_ia_adc_o[2], 
        ADC_SCALING_0_ia_adc_o[1], ADC_SCALING_0_ia_adc_o[0]}), 
        .adc_measurements_0_adc_result_ch1_o_9(
        adc_measurements_0_adc_result_ch1_o[9]), 
        .adc_measurements_0_adc_result_ch1_o_0(
        adc_measurements_0_adc_result_ch1_o[0]), 
        .adc_measurements_0_adc_result_ch1_o_11(
        adc_measurements_0_adc_result_ch1_o[11]), 
        .adc_measurements_0_adc_result_ch1_o_6(
        adc_measurements_0_adc_result_ch1_o[6]), 
        .adc_measurements_0_adc_result_ch1_o_8(
        adc_measurements_0_adc_result_ch1_o[8]), 
        .adc_measurements_0_adc_result_ch1_o_4(
        adc_measurements_0_adc_result_ch1_o[4]), 
        .adc_measurements_0_adc_result_ch1_o_10(
        adc_measurements_0_adc_result_ch1_o[10]), 
        .adc_measurements_0_adc_result_ch1_o_5(
        adc_measurements_0_adc_result_ch1_o[5]), 
        .adc_measurements_0_adc_result_ch1_o_1(
        adc_measurements_0_adc_result_ch1_o[1]), 
        .adc_measurements_0_adc_result_ch1_o_3(
        adc_measurements_0_adc_result_ch1_o[3]), 
        .adc_measurements_0_adc_result_ch1_o_7(
        adc_measurements_0_adc_result_ch1_o[7]), 
        .FOC_TRANSFORMS_0_vbeta_o_17(FOC_TRANSFORMS_0_vbeta_o[17]), 
        .FOC_TRANSFORMS_0_vbeta_o_16(FOC_TRANSFORMS_0_vbeta_o[16]), 
        .FOC_TRANSFORMS_0_vbeta_o_13(FOC_TRANSFORMS_0_vbeta_o[13]), 
        .FOC_TRANSFORMS_0_vbeta_o_15(FOC_TRANSFORMS_0_vbeta_o[15]), 
        .FOC_TRANSFORMS_0_vbeta_o_14(FOC_TRANSFORMS_0_vbeta_o[14]), 
        .FOC_TRANSFORMS_0_vbeta_o_12(FOC_TRANSFORMS_0_vbeta_o[12]), 
        .FOC_TRANSFORMS_0_vbeta_o_4(FOC_TRANSFORMS_0_vbeta_o[4]), 
        .FOC_TRANSFORMS_0_vbeta_o_5(FOC_TRANSFORMS_0_vbeta_o[5]), 
        .FOC_TRANSFORMS_0_vbeta_o_8(FOC_TRANSFORMS_0_vbeta_o[8]), 
        .FOC_TRANSFORMS_0_vbeta_o_3(FOC_TRANSFORMS_0_vbeta_o[3]), 
        .FOC_TRANSFORMS_0_vbeta_o_6(FOC_TRANSFORMS_0_vbeta_o[6]), 
        .FOC_TRANSFORMS_0_vbeta_o_9(FOC_TRANSFORMS_0_vbeta_o[9]), 
        .FOC_TRANSFORMS_0_vbeta_o_7(FOC_TRANSFORMS_0_vbeta_o[7]), 
        .FOC_TRANSFORMS_0_vbeta_o_0(FOC_TRANSFORMS_0_vbeta_o[0]), 
        .FOC_TRANSFORMS_0_vbeta_o_1(FOC_TRANSFORMS_0_vbeta_o[1]), 
        .FOC_TRANSFORMS_0_vbeta_o_10(FOC_TRANSFORMS_0_vbeta_o[10]), 
        .FOC_TRANSFORMS_0_vbeta_o_2(FOC_TRANSFORMS_0_vbeta_o[2]), 
        .prdata_o_1_iv_12({prdata_o_1_iv_12[3], prdata_o_1_iv_12[2], 
        prdata_o_1_iv_12[1]}), .FOC_TRANSFORMS_1_valpha_o_17(
        FOC_TRANSFORMS_1_valpha_o[17]), .FOC_TRANSFORMS_1_valpha_o_16(
        FOC_TRANSFORMS_1_valpha_o[16]), .FOC_TRANSFORMS_1_valpha_o_13(
        FOC_TRANSFORMS_1_valpha_o[13]), .FOC_TRANSFORMS_1_valpha_o_15(
        FOC_TRANSFORMS_1_valpha_o[15]), .FOC_TRANSFORMS_1_valpha_o_14(
        FOC_TRANSFORMS_1_valpha_o[14]), .FOC_TRANSFORMS_1_valpha_o_12(
        FOC_TRANSFORMS_1_valpha_o[12]), .FOC_TRANSFORMS_1_valpha_o_10(
        FOC_TRANSFORMS_1_valpha_o[10]), .FOC_TRANSFORMS_1_valpha_o_2(
        FOC_TRANSFORMS_1_valpha_o[2]), .FOC_TRANSFORMS_1_valpha_o_1(
        FOC_TRANSFORMS_1_valpha_o[1]), .FOC_TRANSFORMS_1_valpha_o_0(
        FOC_TRANSFORMS_1_valpha_o[0]), .FOC_TRANSFORMS_1_valpha_o_3(
        FOC_TRANSFORMS_1_valpha_o[3]), .FOC_TRANSFORMS_1_valpha_o_4(
        FOC_TRANSFORMS_1_valpha_o[4]), .FOC_TRANSFORMS_1_valpha_o_7(
        FOC_TRANSFORMS_1_valpha_o[7]), .FOC_TRANSFORMS_1_valpha_o_5(
        FOC_TRANSFORMS_1_valpha_o[5]), .FOC_TRANSFORMS_1_valpha_o_9(
        FOC_TRANSFORMS_1_valpha_o[9]), .FOC_TRANSFORMS_1_valpha_o_8(
        FOC_TRANSFORMS_1_valpha_o[8]), .FOC_TRANSFORMS_1_valpha_o_6(
        FOC_TRANSFORMS_1_valpha_o[6]), .prdata_o_1_0_iv_11({
        prdata_o_1_0_iv_11[10], prdata_o_1_0_iv_11[9], 
        prdata_o_1_0_iv_11[8], prdata_o_1_0_iv_11[7], 
        prdata_o_1_0_iv_11[6], prdata_o_1_0_iv_11[5], 
        prdata_o_1_0_iv_11[4]}), .FOC_TRANSFORMS_0_iq_o_9(
        FOC_TRANSFORMS_0_iq_o[9]), .FOC_TRANSFORMS_0_iq_o_6(
        FOC_TRANSFORMS_0_iq_o[6]), .FOC_TRANSFORMS_0_iq_o_7(
        FOC_TRANSFORMS_0_iq_o[7]), .FOC_TRANSFORMS_0_iq_o_3(
        FOC_TRANSFORMS_0_iq_o[3]), .FOC_TRANSFORMS_0_iq_o_1(
        FOC_TRANSFORMS_0_iq_o[1]), .FOC_TRANSFORMS_0_iq_o_17(
        FOC_TRANSFORMS_0_iq_o[17]), .FOC_TRANSFORMS_0_iq_o_4(
        FOC_TRANSFORMS_0_iq_o[4]), .FOC_TRANSFORMS_0_iq_o_10(
        FOC_TRANSFORMS_0_iq_o[10]), .FOC_TRANSFORMS_0_iq_o_5(
        FOC_TRANSFORMS_0_iq_o[5]), .FOC_TRANSFORMS_0_iq_o_8(
        FOC_TRANSFORMS_0_iq_o[8]), .FOC_TRANSFORMS_0_iq_o_0(
        FOC_TRANSFORMS_0_iq_o[0]), .FOC_TRANSFORMS_0_iq_o_15(
        FOC_TRANSFORMS_0_iq_o[15]), .FOC_TRANSFORMS_0_iq_o_14(
        FOC_TRANSFORMS_0_iq_o[14]), .FOC_TRANSFORMS_0_iq_o_12(
        FOC_TRANSFORMS_0_iq_o[12]), .FOC_TRANSFORMS_0_iq_o_16(
        FOC_TRANSFORMS_0_iq_o[16]), .FOC_TRANSFORMS_0_iq_o_13(
        FOC_TRANSFORMS_0_iq_o[13]), .prdata_o_1_0_iv_6({
        prdata_o_1_0_iv_6[16], prdata_o_1_0_iv_6[15], 
        prdata_o_1_0_iv_6[14], prdata_o_1_0_iv_6[13], 
        prdata_o_1_0_iv_6[12]}), .prdata_o_1_0_iv_7({
        prdata_o_1_0_iv_7[16], prdata_o_1_0_iv_7[15], 
        prdata_o_1_0_iv_7[14], prdata_o_1_0_iv_7[13], 
        prdata_o_1_0_iv_7[12]}), .FOC_TRANSFORMS_0_id_o_9(
        FOC_TRANSFORMS_0_id_o[9]), .FOC_TRANSFORMS_0_id_o_0(
        FOC_TRANSFORMS_0_id_o[0]), .FOC_TRANSFORMS_0_id_o_7(
        FOC_TRANSFORMS_0_id_o[7]), .FOC_TRANSFORMS_0_id_o_1(
        FOC_TRANSFORMS_0_id_o[1]), .FOC_TRANSFORMS_0_id_o_17(
        FOC_TRANSFORMS_0_id_o[17]), .FOC_TRANSFORMS_0_id_o_6(
        FOC_TRANSFORMS_0_id_o[6]), .FOC_TRANSFORMS_0_id_o_3(
        FOC_TRANSFORMS_0_id_o[3]), .FOC_TRANSFORMS_0_id_o_15(
        FOC_TRANSFORMS_0_id_o[15]), .FOC_TRANSFORMS_0_id_o_16(
        FOC_TRANSFORMS_0_id_o[16]), .FOC_TRANSFORMS_0_id_o_13(
        FOC_TRANSFORMS_0_id_o[13]), .FOC_TRANSFORMS_0_id_o_14(
        FOC_TRANSFORMS_0_id_o[14]), .FOC_TRANSFORMS_0_id_o_12(
        FOC_TRANSFORMS_0_id_o[12]), .FOC_TRANSFORMS_0_id_o_4(
        FOC_TRANSFORMS_0_id_o[4]), .FOC_TRANSFORMS_0_id_o_10(
        FOC_TRANSFORMS_0_id_o[10]), .FOC_TRANSFORMS_0_id_o_5(
        FOC_TRANSFORMS_0_id_o[5]), .FOC_TRANSFORMS_0_id_o_8(
        FOC_TRANSFORMS_0_id_o[8]), .prdata_o_1_iv_11_3(
        prdata_o_1_iv_11_3), .prdata_o_1_iv_11_1(prdata_o_1_iv_11_1), 
        .prdata_o_1_iv_11_0(prdata_o_1_iv_11_0), .prdata_o_1_0_iv_10({
        prdata_o_1_0_iv_10[10], prdata_o_1_0_iv_10[9], 
        prdata_o_1_0_iv_10[8], prdata_o_1_0_iv_10[7], 
        prdata_o_1_0_iv_10[6], prdata_o_1_0_iv_10[5], 
        prdata_o_1_0_iv_10[4]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FAB_CCC_GL1(
        MC_System_0_FAB_CCC_GL1), .apb3_if_st_0_theta_gen_mode_o(
        apb3_if_st_0_theta_gen_mode_o), .apb3_if_st_0_stop_motor_o(
        apb3_if_st_0_stop_motor_o), .apb3_if_st_0_start_motor_o(
        apb3_if_st_0_start_motor_o), .N_193(N_193), .N_194(N_194), 
        .N_184(N_184), .prdata_o197_0_a2_0_a2_0_out(
        prdata_o197_0_a2_0_a2_0_out), .N_185(N_185), .N_174(N_174), 
        .prdata_o201_0_a2_0_0(prdata_o201_0_a2_0_0), .g1(g1), .g2(g2), 
        .N_172(N_172), .N_187(N_187), .N_104(N_104), .N_105(N_105), 
        .N_106(N_106), .N_107(N_107), .N_108(N_108), 
        .adc_channel_ch3_o_1_sqmuxa_0_a2_0_0(
        adc_channel_ch3_o_1_sqmuxa_0_a2_0_0), .prdata_o195_0_a2_0(
        prdata_o195_0_a2_0), .prdata_o190_0_a2_0_out(
        prdata_o190_0_a2_0_out), .N_202(N_202), .prdata_o200_2(
        prdata_o200_2), .N_176(N_176), .N_201(N_201), .N_179(N_179), 
        .N_233(N_233), .N_2787(N_2787), 
        .MC_System_0_AMBA_SLAVE_1_PWRITE(
        MC_System_0_AMBA_SLAVE_1_PWRITE), 
        .MC_System_0_AMBA_SLAVE_1_PSELx(MC_System_0_AMBA_SLAVE_1_PSELx)
        , .MC_System_0_AMBA_SLAVE_1_PENABLE(
        MC_System_0_AMBA_SLAVE_1_PENABLE), .prdata_o191(prdata_o191), 
        .prdata_o190(prdata_o190), .N_2470(N_2470), .N_151(N_151), 
        .N_152(N_152), .N_153(N_153), .N_154(N_154), .N_155(N_155), 
        .N_156(N_156), .N_157(N_157), .N_54(N_54));
    STEPPER_THETA MSC_i_44 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FAB_CCC_GL1), .enable_i(
        ADC_SCALING_0_calib_done_o), .mode_i(
        apb3_if_st_0_theta_gen_mode_o), .clear_buffer_i(
        A1_PWM_WL_O_c_i_0), .slew_cnt_i({
        apb3_if_st_0_theta_gen_slew_count_o[17], 
        apb3_if_st_0_theta_gen_slew_count_o[16], 
        apb3_if_st_0_theta_gen_slew_count_o[15], 
        apb3_if_st_0_theta_gen_slew_count_o[14], 
        apb3_if_st_0_theta_gen_slew_count_o[13], 
        apb3_if_st_0_theta_gen_slew_count_o[12], 
        apb3_if_st_0_theta_gen_slew_count_o[11], 
        apb3_if_st_0_theta_gen_slew_count_o[10], 
        apb3_if_st_0_theta_gen_slew_count_o[9], 
        apb3_if_st_0_theta_gen_slew_count_o[8], 
        apb3_if_st_0_theta_gen_slew_count_o[7], 
        apb3_if_st_0_theta_gen_slew_count_o[6], 
        apb3_if_st_0_theta_gen_slew_count_o[5], 
        apb3_if_st_0_theta_gen_slew_count_o[4], 
        apb3_if_st_0_theta_gen_slew_count_o[3], 
        apb3_if_st_0_theta_gen_slew_count_o[2], 
        apb3_if_st_0_theta_gen_slew_count_o[1], 
        apb3_if_st_0_theta_gen_slew_count_o[0]}), .rate_limit_i({
        apb3_if_st_0_theta_gen_rate_limit_o[17], 
        apb3_if_st_0_theta_gen_rate_limit_o[16], 
        apb3_if_st_0_theta_gen_rate_limit_o[15], 
        apb3_if_st_0_theta_gen_rate_limit_o[14], 
        apb3_if_st_0_theta_gen_rate_limit_o[13], 
        apb3_if_st_0_theta_gen_rate_limit_o[12], 
        apb3_if_st_0_theta_gen_rate_limit_o[11], 
        apb3_if_st_0_theta_gen_rate_limit_o[10], 
        apb3_if_st_0_theta_gen_rate_limit_o[9], 
        apb3_if_st_0_theta_gen_rate_limit_o[8], 
        apb3_if_st_0_theta_gen_rate_limit_o[7], 
        apb3_if_st_0_theta_gen_rate_limit_o[6], 
        apb3_if_st_0_theta_gen_rate_limit_o[5], 
        apb3_if_st_0_theta_gen_rate_limit_o[4], 
        apb3_if_st_0_theta_gen_rate_limit_o[3], 
        apb3_if_st_0_theta_gen_rate_limit_o[2], 
        apb3_if_st_0_theta_gen_rate_limit_o[1], 
        apb3_if_st_0_theta_gen_rate_limit_o[0]}), .cmd_step_no_i({
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[23], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[22], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[21], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[20], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[19], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[18], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[17], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[16], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[15], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[14], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[13], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[12], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[11], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[10], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[9], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[8], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[7], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[6], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[5], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[4], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[3], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[2], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[1], 
        apb3_if_st_0_theta_gen_cmd_step_no_o_0[0]}), .theta_output_o({
        STEPPER_THETA_0_theta_output_o[17], 
        STEPPER_THETA_0_theta_output_o[16], 
        STEPPER_THETA_0_theta_output_o[15], 
        STEPPER_THETA_0_theta_output_o[14], 
        STEPPER_THETA_0_theta_output_o[13], 
        STEPPER_THETA_0_theta_output_o[12], 
        STEPPER_THETA_0_theta_output_o[11], 
        STEPPER_THETA_0_theta_output_o[10], 
        STEPPER_THETA_0_theta_output_o[9], 
        STEPPER_THETA_0_theta_output_o[8], 
        STEPPER_THETA_0_theta_output_o[7], 
        STEPPER_THETA_0_theta_output_o[6], 
        STEPPER_THETA_0_theta_output_o[5], 
        STEPPER_THETA_0_theta_output_o[4], 
        STEPPER_THETA_0_theta_output_o[3], 
        STEPPER_THETA_0_theta_output_o[2], 
        STEPPER_THETA_0_theta_output_o[1], 
        STEPPER_THETA_0_theta_output_o[0]}), .step_count_o({
        STEPPER_THETA_1_step_count_o[23], 
        STEPPER_THETA_1_step_count_o[22], 
        STEPPER_THETA_1_step_count_o[21], 
        STEPPER_THETA_1_step_count_o[20], 
        STEPPER_THETA_1_step_count_o[19], 
        STEPPER_THETA_1_step_count_o[18], 
        STEPPER_THETA_1_step_count_o[17], 
        STEPPER_THETA_1_step_count_o[16], 
        STEPPER_THETA_1_step_count_o[15], 
        STEPPER_THETA_1_step_count_o[14], 
        STEPPER_THETA_1_step_count_o[13], 
        STEPPER_THETA_1_step_count_o[12], 
        STEPPER_THETA_1_step_count_o[11], 
        STEPPER_THETA_1_step_count_o[10], 
        STEPPER_THETA_1_step_count_o[9], 
        STEPPER_THETA_1_step_count_o[8], 
        STEPPER_THETA_1_step_count_o[7], 
        STEPPER_THETA_1_step_count_o[6], 
        STEPPER_THETA_1_step_count_o[5], 
        STEPPER_THETA_1_step_count_o[4], 
        STEPPER_THETA_1_step_count_o[3], 
        STEPPER_THETA_1_step_count_o_2, 
        STEPPER_THETA_1_step_count_o[1], 
        STEPPER_THETA_1_step_count_o[0]}));
    VCC VCC_Z (.Y(VCC));
    SPEED_ID_IQ_PI_2s_44s_0 MSC_i_46 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FAB_CCC_GL1), .clear_buffer_i(
        A1_PWM_WL_O_c_i_0), .speed_en_i(GND), .idq_en_i(N_614_i_0), 
        .speed_pi_start_i(GND), .id_pi_start_i(
        SPEED_ID_IQ_PI_1_iq_pi_done_o), .iq_pi_start_i(
        FOC_TRANSFORMS_0_park_done_o), .speed_init_i({GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND}), .id_init_i({apb3_if_st_0_sqmng_dv_o[17], 
        apb3_if_st_0_sqmng_dv_o[16], apb3_if_st_0_sqmng_dv_o[15], 
        apb3_if_st_0_sqmng_dv_o[14], apb3_if_st_0_sqmng_dv_o[13], 
        apb3_if_st_0_sqmng_dv_o[12], apb3_if_st_0_sqmng_dv_o[11], 
        apb3_if_st_0_sqmng_dv_o[10], apb3_if_st_0_sqmng_dv_o[9], 
        apb3_if_st_0_sqmng_dv_o[8], apb3_if_st_0_sqmng_dv_o[7], 
        apb3_if_st_0_sqmng_dv_o[6], apb3_if_st_0_sqmng_dv_o[5], 
        apb3_if_st_0_sqmng_dv_o[4], apb3_if_st_0_sqmng_dv_o[3], 
        apb3_if_st_0_sqmng_dv_o[2], apb3_if_st_0_sqmng_dv_o[1], 
        apb3_if_st_0_sqmng_dv_o[0]}), .iq_init_i({GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND}), .speed_pi_ref_input_i({GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND}), .speed_pi_act_input_i({GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .speed_pi_kp_i({GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND}), .speed_pi_ki_i({
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND}), .speed_pi_ymax_i({GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND}), .speed_pi_ymin_i({GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND}), .id_pi_ref_input_i({apb3_if_st_0_id_ref_val_o[17], 
        apb3_if_st_0_id_ref_val_o[16], apb3_if_st_0_id_ref_val_o[15], 
        apb3_if_st_0_id_ref_val_o[14], apb3_if_st_0_id_ref_val_o[13], 
        apb3_if_st_0_id_ref_val_o[12], apb3_if_st_0_id_ref_val_o[11], 
        apb3_if_st_0_id_ref_val_o[10], apb3_if_st_0_id_ref_val_o[9], 
        apb3_if_st_0_id_ref_val_o[8], apb3_if_st_0_id_ref_val_o[7], 
        apb3_if_st_0_id_ref_val_o[6], apb3_if_st_0_id_ref_val_o[5], 
        apb3_if_st_0_id_ref_val_o[4], apb3_if_st_0_id_ref_val_o[3], 
        apb3_if_st_0_id_ref_val_o[2], apb3_if_st_0_id_ref_val_o[1], 
        apb3_if_st_0_id_ref_val_o[0]}), .id_pi_act_input_i({
        FOC_TRANSFORMS_0_id_o[17], FOC_TRANSFORMS_0_id_o[16], 
        FOC_TRANSFORMS_0_id_o[15], FOC_TRANSFORMS_0_id_o[14], 
        FOC_TRANSFORMS_0_id_o[13], FOC_TRANSFORMS_0_id_o[12], 
        FOC_TRANSFORMS_0_id_o_11, FOC_TRANSFORMS_0_id_o[10], 
        FOC_TRANSFORMS_0_id_o[9], FOC_TRANSFORMS_0_id_o[8], 
        FOC_TRANSFORMS_0_id_o[7], FOC_TRANSFORMS_0_id_o[6], 
        FOC_TRANSFORMS_0_id_o[5], FOC_TRANSFORMS_0_id_o[4], 
        FOC_TRANSFORMS_0_id_o[3], FOC_TRANSFORMS_0_id_o_2, 
        FOC_TRANSFORMS_0_id_o[1], FOC_TRANSFORMS_0_id_o[0]}), 
        .id_pi_kp_i({apb3_if_st_0_idq_pi_kp_o[17], 
        apb3_if_st_0_idq_pi_kp_o[16], apb3_if_st_0_idq_pi_kp_o[15], 
        apb3_if_st_0_idq_pi_kp_o[14], apb3_if_st_0_idq_pi_kp_o[13], 
        apb3_if_st_0_idq_pi_kp_o[12], apb3_if_st_0_idq_pi_kp_o[11], 
        apb3_if_st_0_idq_pi_kp_o[10], apb3_if_st_0_idq_pi_kp_o[9], 
        apb3_if_st_0_idq_pi_kp_o[8], apb3_if_st_0_idq_pi_kp_o[7], 
        apb3_if_st_0_idq_pi_kp_o[6], apb3_if_st_0_idq_pi_kp_o[5], 
        apb3_if_st_0_idq_pi_kp_o[4], apb3_if_st_0_idq_pi_kp_o[3], 
        apb3_if_st_0_idq_pi_kp_o[2], apb3_if_st_0_idq_pi_kp_o[1], 
        apb3_if_st_0_idq_pi_kp_o[0]}), .id_pi_ki_i({
        apb3_if_st_0_idq_pi_ki_o[17], apb3_if_st_0_idq_pi_ki_o[16], 
        apb3_if_st_0_idq_pi_ki_o[15], apb3_if_st_0_idq_pi_ki_o[14], 
        apb3_if_st_0_idq_pi_ki_o[13], apb3_if_st_0_idq_pi_ki_o[12], 
        apb3_if_st_0_idq_pi_ki_o[11], apb3_if_st_0_idq_pi_ki_o[10], 
        apb3_if_st_0_idq_pi_ki_o[9], apb3_if_st_0_idq_pi_ki_o[8], 
        apb3_if_st_0_idq_pi_ki_o[7], apb3_if_st_0_idq_pi_ki_o[6], 
        apb3_if_st_0_idq_pi_ki_o[5], apb3_if_st_0_idq_pi_ki_o[4], 
        apb3_if_st_0_idq_pi_ki_o[3], apb3_if_st_0_idq_pi_ki_o[2], 
        apb3_if_st_0_idq_pi_ki_o[1], apb3_if_st_0_idq_pi_ki_o[0]}), 
        .idq_pi_ymax_i({GND, VCC, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND}), .idq_pi_ymin_i({
        VCC, VCC, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND}), .iq_pi_ref_input_i({GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND}), .iq_pi_act_input_i({
        FOC_TRANSFORMS_0_iq_o[17], FOC_TRANSFORMS_0_iq_o[16], 
        FOC_TRANSFORMS_0_iq_o[15], FOC_TRANSFORMS_0_iq_o[14], 
        FOC_TRANSFORMS_0_iq_o[13], FOC_TRANSFORMS_0_iq_o[12], 
        FOC_TRANSFORMS_0_iq_o_11, FOC_TRANSFORMS_0_iq_o[10], 
        FOC_TRANSFORMS_0_iq_o[9], FOC_TRANSFORMS_0_iq_o[8], 
        FOC_TRANSFORMS_0_iq_o[7], FOC_TRANSFORMS_0_iq_o[6], 
        FOC_TRANSFORMS_0_iq_o[5], FOC_TRANSFORMS_0_iq_o[4], 
        FOC_TRANSFORMS_0_iq_o[3], FOC_TRANSFORMS_0_iq_o_2, 
        FOC_TRANSFORMS_0_iq_o[1], FOC_TRANSFORMS_0_iq_o[0]}), 
        .iq_pi_kp_i({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND}), .iq_pi_ki_i({GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND}), .speed_pi_done_o(speed_pi_done_o_0), 
        .id_pi_done_o(SPEED_ID_IQ_PI_1_id_pi_done_o), .iq_pi_done_o(
        SPEED_ID_IQ_PI_1_iq_pi_done_o), .speed_pi_output_o({
        speed_pi_output_o[17], speed_pi_output_o[16], 
        speed_pi_output_o[15], speed_pi_output_o[14], 
        speed_pi_output_o[13], speed_pi_output_o[12], 
        speed_pi_output_o[11], speed_pi_output_o[10], 
        speed_pi_output_o[9], speed_pi_output_o[8], 
        speed_pi_output_o[7], speed_pi_output_o[6], 
        speed_pi_output_o[5], speed_pi_output_o[4], 
        speed_pi_output_o[3], speed_pi_output_o[2], 
        speed_pi_output_o[1], speed_pi_output_o[0]}), .id_pi_output_o({
        SPEED_ID_IQ_PI_1_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[1], 
        SPEED_ID_IQ_PI_1_id_pi_output_o[0]}), .iq_pi_output_o({
        SPEED_ID_IQ_PI_1_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[9], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o[1], 
        SPEED_ID_IQ_PI_1_iq_pi_output_o_0}));
    PWM3PH_0 MSC_i_52 (.reset_i(MC_System_0_FIC_0_LOCK), .sys_clk_i(
        MC_System_0_FAB_CCC_GL1), .en_pwm_i(A1_PWM_WL_O_c), 
        .en_dual_trig_i(GND), .va_i({PWM_SCALING_0_Va_o[17], 
        PWM_SCALING_0_Va_o[16], PWM_SCALING_0_Va_o[15], 
        PWM_SCALING_0_Va_o[14], PWM_SCALING_0_Va_o[13], 
        PWM_SCALING_0_Va_o[12], PWM_SCALING_0_Va_o[11], 
        PWM_SCALING_0_Va_o[10], PWM_SCALING_0_Va_o[9], 
        PWM_SCALING_0_Va_o[8], PWM_SCALING_0_Va_o[7], 
        PWM_SCALING_0_Va_o[6], PWM_SCALING_0_Va_o[5], 
        PWM_SCALING_0_Va_o[4], PWM_SCALING_0_Va_o[3], 
        PWM_SCALING_0_Va_o[2], PWM_SCALING_0_Va_o[1], 
        PWM_SCALING_0_Va_o[0]}), .vb_i({PWM_SCALING_0_Vb_o[17], 
        PWM_SCALING_0_Vb_o[16], PWM_SCALING_0_Vb_o[15], 
        PWM_SCALING_0_Vb_o[14], PWM_SCALING_0_Vb_o[13], 
        PWM_SCALING_0_Vb_o[12], PWM_SCALING_0_Vb_o[11], 
        PWM_SCALING_0_Vb_o[10], PWM_SCALING_0_Vb_o[9], 
        PWM_SCALING_0_Vb_o[8], PWM_SCALING_0_Vb_o[7], 
        PWM_SCALING_0_Vb_o[6], PWM_SCALING_0_Vb_o[5], 
        PWM_SCALING_0_Vb_o[4], PWM_SCALING_0_Vb_o[3], 
        PWM_SCALING_0_Vb_o[2], PWM_SCALING_0_Vb_o[1], 
        PWM_SCALING_0_Vb_o[0]}), .vc_i({GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .pwm_period_i({apb3_if_st_0_pwm_period_val_o[17], 
        apb3_if_st_0_pwm_period_val_o[16], 
        apb3_if_st_0_pwm_period_val_o[15], 
        apb3_if_st_0_pwm_period_val_o[14], 
        apb3_if_st_0_pwm_period_val_o[13], 
        apb3_if_st_0_pwm_period_val_o[12], 
        apb3_if_st_0_pwm_period_val_o[11], 
        apb3_if_st_0_pwm_period_val_o[10], 
        apb3_if_st_0_pwm_period_val_o[9], 
        apb3_if_st_0_pwm_period_val_o[8], 
        apb3_if_st_0_pwm_period_val_o[7], 
        apb3_if_st_0_pwm_period_val_o[6], 
        apb3_if_st_0_pwm_period_val_o[5], 
        apb3_if_st_0_pwm_period_val_o[4], 
        apb3_if_st_0_pwm_period_val_o[3], 
        apb3_if_st_0_pwm_period_val_o[2], 
        apb3_if_st_0_pwm_period_val_o[1], 
        apb3_if_st_0_pwm_period_val_o[0]}), .dead_time_i({
        apb3_if_st_0_pwm_dead_time_val_o[17], 
        apb3_if_st_0_pwm_dead_time_val_o[16], 
        apb3_if_st_0_pwm_dead_time_val_o[15], 
        apb3_if_st_0_pwm_dead_time_val_o[14], 
        apb3_if_st_0_pwm_dead_time_val_o[13], 
        apb3_if_st_0_pwm_dead_time_val_o[12], 
        apb3_if_st_0_pwm_dead_time_val_o[11], 
        apb3_if_st_0_pwm_dead_time_val_o[10], 
        apb3_if_st_0_pwm_dead_time_val_o[9], 
        apb3_if_st_0_pwm_dead_time_val_o[8], 
        apb3_if_st_0_pwm_dead_time_val_o[7], 
        apb3_if_st_0_pwm_dead_time_val_o[6], 
        apb3_if_st_0_pwm_dead_time_val_o[5], 
        apb3_if_st_0_pwm_dead_time_val_o[4], 
        apb3_if_st_0_pwm_dead_time_val_o[3], 
        apb3_if_st_0_pwm_dead_time_val_o[2], 
        apb3_if_st_0_pwm_dead_time_val_o[1], 
        apb3_if_st_0_pwm_dead_time_val_o[0]}), .delay_time_i({
        apb3_if_st_0_pwm_delay_time_val_o[17], 
        apb3_if_st_0_pwm_delay_time_val_o[16], 
        apb3_if_st_0_pwm_delay_time_val_o[15], 
        apb3_if_st_0_pwm_delay_time_val_o[14], 
        apb3_if_st_0_pwm_delay_time_val_o[13], 
        apb3_if_st_0_pwm_delay_time_val_o[12], 
        apb3_if_st_0_pwm_delay_time_val_o[11], 
        apb3_if_st_0_pwm_delay_time_val_o[10], 
        apb3_if_st_0_pwm_delay_time_val_o[9], 
        apb3_if_st_0_pwm_delay_time_val_o[8], 
        apb3_if_st_0_pwm_delay_time_val_o[7], 
        apb3_if_st_0_pwm_delay_time_val_o[6], 
        apb3_if_st_0_pwm_delay_time_val_o[5], 
        apb3_if_st_0_pwm_delay_time_val_o[4], 
        apb3_if_st_0_pwm_delay_time_val_o[3], 
        apb3_if_st_0_pwm_delay_time_val_o[2], 
        apb3_if_st_0_pwm_delay_time_val_o[1], 
        apb3_if_st_0_pwm_delay_time_val_o[0]}), .midmatch_o(
        PWM3PH_0_midmatch_o), .PWM_AH_o(A1_PWM_UH_O_c), .PWM_BH_o(
        A1_PWM_VH_O_c), .PWM_CH_o(PWM_CH_o), .PWM_AL_o(A1_PWM_UL_O_c), 
        .PWM_BL_o(A1_PWM_VL_O_c), .PWM_CL_o(PWM_CL_o_0));
    
        work_adc_interface_adc_interface_6_16_12_g_ADC_CONFIG_REG_WIDTHg_ADC_CONFIG_VAL_WIDTHg_ADC_RESULTS_WIDTH_0 
        adc_interface_0 (.apb3_if_st_0_adc_control_reg_val_o({
        apb3_if_st_0_adc_control_reg_val_o[5], 
        apb3_if_st_0_adc_control_reg_val_o[4], 
        apb3_if_st_0_adc_control_reg_val_o[3], 
        apb3_if_st_0_adc_control_reg_val_o[2], 
        apb3_if_st_0_adc_control_reg_val_o[1], 
        apb3_if_st_0_adc_control_reg_val_o[0]}), 
        .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[11], 
        adc_interface_0_result_ch0_o[10], 
        adc_interface_0_result_ch0_o[9], 
        adc_interface_0_result_ch0_o[8], 
        adc_interface_0_result_ch0_o[7], 
        adc_interface_0_result_ch0_o[6], 
        adc_interface_0_result_ch0_o[5], 
        adc_interface_0_result_ch0_o[4], 
        adc_interface_0_result_ch0_o[3], 
        adc_interface_0_result_ch0_o_2, 
        adc_interface_0_result_ch0_o[1], 
        adc_interface_0_result_ch0_o[0]}), 
        .adc_measurements_0_adc_result_ch1_o({
        adc_measurements_0_adc_result_ch1_o[11], 
        adc_measurements_0_adc_result_ch1_o[10], 
        adc_measurements_0_adc_result_ch1_o[9], 
        adc_measurements_0_adc_result_ch1_o[8], 
        adc_measurements_0_adc_result_ch1_o[7], 
        adc_measurements_0_adc_result_ch1_o[6], 
        adc_measurements_0_adc_result_ch1_o[5], 
        adc_measurements_0_adc_result_ch1_o[4], 
        adc_measurements_0_adc_result_ch1_o[3], 
        adc_measurements_0_adc_result_ch1_o_2, 
        adc_measurements_0_adc_result_ch1_o[1], 
        adc_measurements_0_adc_result_ch1_o[0]}), 
        .adc_interface_0_result_ch2_o({
        adc_interface_0_result_ch2_o[11], 
        adc_interface_0_result_ch2_o[10], 
        adc_interface_0_result_ch2_o[9], 
        adc_interface_0_result_ch2_o[8], 
        adc_interface_0_result_ch2_o[7], 
        adc_interface_0_result_ch2_o[6], 
        adc_interface_0_result_ch2_o[5], 
        adc_interface_0_result_ch2_o[4], 
        adc_interface_0_result_ch2_o[3], 
        adc_interface_0_result_ch2_o_2, 
        adc_interface_0_result_ch2_o[1], 
        adc_interface_0_result_ch2_o[0]}), 
        .adc_measurements_0_adc_result_ch3_o({
        adc_measurements_0_adc_result_ch3_o[11], 
        adc_measurements_0_adc_result_ch3_o[10], 
        adc_measurements_0_adc_result_ch3_o[9], 
        adc_measurements_0_adc_result_ch3_o[8], 
        adc_measurements_0_adc_result_ch3_o[7], 
        adc_measurements_0_adc_result_ch3_o[6], 
        adc_measurements_0_adc_result_ch3_o[5], 
        adc_measurements_0_adc_result_ch3_o[4], 
        adc_measurements_0_adc_result_ch3_o[3], 
        adc_measurements_0_adc_result_ch3_o_2, 
        adc_measurements_0_adc_result_ch3_o[1], 
        adc_measurements_0_adc_result_ch3_o[0]}), 
        .apb3_if_st_0_adc_channel_ch2_o({
        apb3_if_st_0_adc_channel_ch2_o[15], 
        apb3_if_st_0_adc_channel_ch2_o[14], 
        apb3_if_st_0_adc_channel_ch2_o[13], 
        apb3_if_st_0_adc_channel_ch2_o[12], 
        apb3_if_st_0_adc_channel_ch2_o[11], 
        apb3_if_st_0_adc_channel_ch2_o[10], 
        apb3_if_st_0_adc_channel_ch2_o[9], 
        apb3_if_st_0_adc_channel_ch2_o[8], 
        apb3_if_st_0_adc_channel_ch2_o[7], 
        apb3_if_st_0_adc_channel_ch2_o[6], 
        apb3_if_st_0_adc_channel_ch2_o[5], 
        apb3_if_st_0_adc_channel_ch2_o[4], 
        apb3_if_st_0_adc_channel_ch2_o[3], 
        apb3_if_st_0_adc_channel_ch2_o[2], 
        apb3_if_st_0_adc_channel_ch2_o[1], 
        apb3_if_st_0_adc_channel_ch2_o[0]}), 
        .apb3_if_st_0_adc_channel_ch0_o({
        apb3_if_st_0_adc_channel_ch0_o[15], 
        apb3_if_st_0_adc_channel_ch0_o[14], 
        apb3_if_st_0_adc_channel_ch0_o[13], 
        apb3_if_st_0_adc_channel_ch0_o[12], 
        apb3_if_st_0_adc_channel_ch0_o[11], 
        apb3_if_st_0_adc_channel_ch0_o[10], 
        apb3_if_st_0_adc_channel_ch0_o[9], 
        apb3_if_st_0_adc_channel_ch0_o[8], 
        apb3_if_st_0_adc_channel_ch0_o[7], 
        apb3_if_st_0_adc_channel_ch0_o[6], 
        apb3_if_st_0_adc_channel_ch0_o[5], 
        apb3_if_st_0_adc_channel_ch0_o[4], 
        apb3_if_st_0_adc_channel_ch0_o[3], 
        apb3_if_st_0_adc_channel_ch0_o[2], 
        apb3_if_st_0_adc_channel_ch0_o[1], 
        apb3_if_st_0_adc_channel_ch0_o[0]}), 
        .apb3_if_st_0_adc_channel_ch1_o({
        apb3_if_st_0_adc_channel_ch1_o[15], 
        apb3_if_st_0_adc_channel_ch1_o[14], 
        apb3_if_st_0_adc_channel_ch1_o[13], 
        apb3_if_st_0_adc_channel_ch1_o[12], 
        apb3_if_st_0_adc_channel_ch1_o[11], 
        apb3_if_st_0_adc_channel_ch1_o[10], 
        apb3_if_st_0_adc_channel_ch1_o[9], 
        apb3_if_st_0_adc_channel_ch1_o[8], 
        apb3_if_st_0_adc_channel_ch1_o[7], 
        apb3_if_st_0_adc_channel_ch1_o[6], 
        apb3_if_st_0_adc_channel_ch1_o[5], 
        apb3_if_st_0_adc_channel_ch1_o[4], 
        apb3_if_st_0_adc_channel_ch1_o[3], 
        apb3_if_st_0_adc_channel_ch1_o[2], 
        apb3_if_st_0_adc_channel_ch1_o[1], 
        apb3_if_st_0_adc_channel_ch1_o[0]}), 
        .apb3_if_st_0_adc_channel_ch3_o({
        apb3_if_st_0_adc_channel_ch3_o[15], 
        apb3_if_st_0_adc_channel_ch3_o[14], 
        apb3_if_st_0_adc_channel_ch3_o[13], 
        apb3_if_st_0_adc_channel_ch3_o[12], 
        apb3_if_st_0_adc_channel_ch3_o[11], 
        apb3_if_st_0_adc_channel_ch3_o[10], 
        apb3_if_st_0_adc_channel_ch3_o[9], 
        apb3_if_st_0_adc_channel_ch3_o[8], 
        apb3_if_st_0_adc_channel_ch3_o[7], 
        apb3_if_st_0_adc_channel_ch3_o[6], 
        apb3_if_st_0_adc_channel_ch3_o[5], 
        apb3_if_st_0_adc_channel_ch3_o[4], 
        apb3_if_st_0_adc_channel_ch3_o[3], 
        apb3_if_st_0_adc_channel_ch3_o[2], 
        apb3_if_st_0_adc_channel_ch3_o[1], 
        apb3_if_st_0_adc_channel_ch3_o[0]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FAB_CCC_GL1(
        MC_System_0_FAB_CCC_GL1), .SEQ_CONTROLLER_1_adc_start_o_0(
        SEQ_CONTROLLER_1_adc_start_o_0), .A1_ADC_SDI_I_c(
        A1_ADC_SDI_I_c), .A1_ADC_SDO_O_c(A1_ADC_SDO_O_c), 
        .A1_ADC_CS_O_c(A1_ADC_CS_O_c), .A1_ADC_SCK_O_c(A1_ADC_SCK_O_c), 
        .adc_interface_0_results_rdy_o(adc_interface_0_results_rdy_o));
    
endmodule


module MC_System_top(
       A0_ADC_SDI_I,
       A1_ADC_SDI_I,
       DEVRST_N,
       USB_ULPI_DIR,
       USB_ULPI_NXT,
       USB_ULPI_XCLK,
       A0_ADC_CS_O,
       A0_ADC_SCK_O,
       A0_ADC_SDO_O,
       A0_PWM_UH_O,
       A0_PWM_UL_O,
       A0_PWM_VH_O,
       A0_PWM_VL_O,
       A0_PWM_WH_O,
       A0_PWM_WL_O,
       A0_RUNNING_LED,
       A1_ADC_CS_O,
       A1_ADC_SCK_O,
       A1_ADC_SDO_O,
       A1_PWM_UH_O,
       A1_PWM_UL_O,
       A1_PWM_VH_O,
       A1_PWM_VL_O,
       A1_PWM_WH_O,
       A1_PWM_WL_O,
       A1_RUNNING_LED,
       GPIO_0_M2F,
       USB_ULPI_STP,
       USB_ULPI_DATA
    );
input  A0_ADC_SDI_I;
input  A1_ADC_SDI_I;
input  DEVRST_N;
input  USB_ULPI_DIR;
input  USB_ULPI_NXT;
input  USB_ULPI_XCLK;
output A0_ADC_CS_O;
output A0_ADC_SCK_O;
output A0_ADC_SDO_O;
output A0_PWM_UH_O;
output A0_PWM_UL_O;
output A0_PWM_VH_O;
output A0_PWM_VL_O;
output A0_PWM_WH_O;
output A0_PWM_WL_O;
output A0_RUNNING_LED;
output A1_ADC_CS_O;
output A1_ADC_SCK_O;
output A1_ADC_SDO_O;
output A1_PWM_UH_O;
output A1_PWM_UL_O;
output A1_PWM_VH_O;
output A1_PWM_VL_O;
output A1_PWM_WH_O;
output A1_PWM_WL_O;
output A1_RUNNING_LED;
output GPIO_0_M2F;
output USB_ULPI_STP;
inout  [7:0] USB_ULPI_DATA;

    wire [11:0] MC_System_0_AMBA_SLAVE_1_PADDR;
    wire [23:0] MC_System_0_AMBA_SLAVE_1_PWDATA;
    wire [2:2] \Stepper_Axis_0.adc_interface_0_result_ch0_o ;
    wire [2:2] \Stepper_Axis_0.adc_interface_0_result_ch2_o ;
    wire [2:2] \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o ;
    wire [0:0] \Stepper_Axis_0.SPEED_ID_IQ_PI_1_iq_pi_output_o ;
    wire [11:2] \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o ;
    wire [11:2] \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o ;
    wire [11:11] \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o ;
    wire [11:11] \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o ;
    wire [2:2] \Stepper_Axis_0.SEQ_CONTROLLER_1_state_o_0 ;
    wire [2:2] \Stepper_Axis_0.STEPPER_THETA_1_step_count_o ;
    wire [2:2] \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o ;
    wire [2:2] \Stepper_Axis_0.adc_measurements_0_adc_result_ch3_o ;
    wire [3:3] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12_1 ;
    wire [3:3] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12_0_2 ;
    wire [0:0] \Stepper_Axis_0.SPEED_ID_IQ_PI_1_id_pi_output_o_m ;
    wire [3:3] \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_7_0 ;
    wire [15:15] \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_10_0 ;
    wire [16:12] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 ;
    wire [16:12] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 ;
    wire [10:4] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 ;
    wire [10:4] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 ;
    wire [0:0] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9 ;
    wire [3:0] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11 ;
    wire [3:1] \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12 ;
    wire [3:3] \Bldc_Axis_0.apb3_if_0.prdata_o_1_0 ;
    wire [15:15] \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_12_0 ;
    wire [16:12] \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 ;
    wire [16:12] \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 ;
    wire [16:12] \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 ;
    wire [3:2] \Bldc_Axis_0.apb3_if_0.prdata_o_1_2 ;
    wire [3:2] \Bldc_Axis_0.apb3_if_0.prdata_o_1_3 ;
    wire [11:4] \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 ;
    wire [11:4] \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 ;
    wire [11:4] \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 ;
    wire [1:1] \Bldc_Axis_0.apb3_if_0.prdata_o_1_24_2 ;
    wire [1:1] \Bldc_Axis_0.apb3_if_0.prdata_o_1_24_3 ;
    wire [1:1] \Bldc_Axis_0.apb3_if_0.prdata_o_1_24_4 ;
    wire [2:2] \Bldc_Axis_0.apb3_if_0.prdata_o_1_4 ;
    wire MC_System_0_AMBA_SLAVE_1_PENABLE, 
        MC_System_0_AMBA_SLAVE_1_PWRITE, MC_System_0_FAB_CCC_GL1, 
        MC_System_0_FIC_0_CLK, VCC, GND, MC_System_0_FIC_0_LOCK, 
        A0_ADC_SDI_I_c, A1_ADC_SDI_I_c, A0_ADC_CS_O_c, A0_ADC_SCK_O_c, 
        A0_ADC_SDO_O_c, A0_PWM_UH_O_c, A0_PWM_VH_O_c, A0_PWM_VL_O_c, 
        A0_PWM_WH_O_c, A1_ADC_CS_O_c, A1_ADC_SCK_O_c, A1_ADC_SDO_O_c, 
        A1_PWM_UH_O_c, A1_PWM_UL_O_c, A1_PWM_VH_O_c, A1_PWM_VL_O_c, 
        A1_PWM_WL_O_c, GPIO_0_M2F_c, 
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o200_2 , 
        \Stepper_Axis_0.N_108 , \Stepper_Axis_0.N_107 , 
        \Stepper_Axis_0.N_106 , \Stepper_Axis_0.N_105 , 
        \Stepper_Axis_0.N_104 , \Stepper_Axis_0.N_185 , 
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o190 , 
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o191 , 
        \Stepper_Axis_0.N_233 , \Stepper_Axis_0.N_187 , 
        \Stepper_Axis_0.N_194 , \Bldc_Axis_0.N_2791 , 
        \Bldc_Axis_0.N_2779 , \Bldc_Axis_0.N_2784 , 
        \Bldc_Axis_0.N_2785 , \Bldc_Axis_0.N_2778 , 
        MC_System_0_AMBA_SLAVE_1_PSELx, MC_System_0_AMBA_SLAVE_0_PSELx, 
        \Stepper_Axis_0.N_54 , \Stepper_Axis_0.N_157 , 
        \Stepper_Axis_0.N_156 , \Stepper_Axis_0.N_155 , 
        \Stepper_Axis_0.N_154 , \Stepper_Axis_0.N_153 , 
        \Stepper_Axis_0.N_152 , \Stepper_Axis_0.N_151 , 
        \Stepper_Axis_0.N_202 , \Stepper_Axis_0.N_172 , 
        \Bldc_Axis_0.N_2787 , \Stepper_Axis_0.N_176 , 
        \Stepper_Axis_0.N_201 , \Stepper_Axis_0.N_174 , 
        \Bldc_Axis_0.N_2660 , \Bldc_Axis_0.N_2661 , 
        \Bldc_Axis_0.N_2704 , \Bldc_Axis_0.N_2734 , 
        \Bldc_Axis_0.N_2728 , \Bldc_Axis_0.N_2606 , 
        \Bldc_Axis_0.N_2585 , \Bldc_Axis_0.N_2542 , 
        \Bldc_Axis_0.N_1508 , \Bldc_Axis_0.N_2532 , 
        \Bldc_Axis_0.N_2522 , \Bldc_Axis_0.N_1083 , 
        \Bldc_Axis_0.N_1080 , \Bldc_Axis_0.N_1077 , 
        \Bldc_Axis_0.N_1014 , \Bldc_Axis_0.N_1007 , 
        \Bldc_Axis_0.N_2470 , \Stepper_Axis_0.N_184 , 
        \Stepper_Axis_0.N_193 , 
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o201_0_a2_0_0 , 
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o197_0_a2_0_a2_0_out , 
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o190_0_a2_0_out , 
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o195_0_a2_0 , 
        \Stepper_Axis_0.N_179 , 
        \Stepper_Axis_0.apb3_if_st_0.adc_channel_ch3_o_1_sqmuxa_0_a2_0_0 , 
        \Stepper_Axis_0.apb3_if_st_0.g1 , 
        \Stepper_Axis_0.apb3_if_st_0.g2 ;
    
    GND GND_Z (.Y(GND));
    OUTBUF #( .IOSTD("") )  A1_PWM_UL_O_obuf (.D(A1_PWM_UL_O_c), .PAD(
        A1_PWM_UL_O));
    INBUF #( .IOSTD("") )  A1_ADC_SDI_I_ibuf (.PAD(A1_ADC_SDI_I), .Y(
        A1_ADC_SDI_I_c));
    OUTBUF #( .IOSTD("") )  A0_PWM_VH_O_obuf (.D(A0_PWM_VH_O_c), .PAD(
        A0_PWM_VH_O));
    OUTBUF #( .IOSTD("") )  A0_PWM_UH_O_obuf (.D(A0_PWM_UH_O_c), .PAD(
        A0_PWM_UH_O));
    OUTBUF #( .IOSTD("") )  A1_PWM_VH_O_obuf (.D(A1_PWM_VH_O_c), .PAD(
        A1_PWM_VH_O));
    OUTBUF #( .IOSTD("") )  A0_PWM_WL_O_obuf (.D(A0_PWM_VL_O_c), .PAD(
        A0_PWM_WL_O));
    VCC VCC_Z (.Y(VCC));
    MC_System MC_System_0 (.prdata_o_1_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0 [3]}), 
        .ADC_SCALING_0_ib_adc_o({
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o [2]}), 
        .STEPPER_THETA_1_step_count_o({
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o [2]}), 
        .adc_interface_0_result_ch0_o({
        \Stepper_Axis_0.adc_interface_0_result_ch0_o [2]}), 
        .adc_interface_0_result_ch2_o({
        \Stepper_Axis_0.adc_interface_0_result_ch2_o [2]}), 
        .adc_measurements_0_adc_result_ch3_o({
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch3_o [2]}), 
        .adc_measurements_0_adc_result_ch1_o({
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o [2]}), 
        .SEQ_CONTROLLER_1_state_o_0({
        \Stepper_Axis_0.SEQ_CONTROLLER_1_state_o_0 [2]}), 
        .prdata_o_1_0_a2_12_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_12_0 [15]}), 
        .prdata_o_1_0_a2_10_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_10_0 [15]}), 
        .FOC_TRANSFORMS_1_valpha_o({
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o [11]}), 
        .prdata_o_1_iv_12_1({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12_1 [3]}), 
        .FOC_TRANSFORMS_0_vbeta_o({
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o [11]}), 
        .prdata_o_1_iv_12_0_2({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12_0_2 [3]}), 
        .SPEED_ID_IQ_PI_1_iq_pi_output_o({
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_iq_pi_output_o [0]}), 
        .FOC_TRANSFORMS_0_iq_o_0(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o [2]), 
        .FOC_TRANSFORMS_0_iq_o_9(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o [11]), 
        .FOC_TRANSFORMS_0_id_o_0(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o [2]), 
        .FOC_TRANSFORMS_0_id_o_9(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o [11]), .prdata_o_1_iv_9({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9 [0]}), 
        .SPEED_ID_IQ_PI_1_id_pi_output_o_m({
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_id_pi_output_o_m [0]}), 
        .prdata_o_1_0_1({\Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [16], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [15], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [14], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [13], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [12]}), .prdata_o_1_0_2({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [16], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [15], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [14], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [13], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [12]}), .prdata_o_1_0_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [16], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [15], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [14], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [13], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [12]}), .prdata_o_1_3({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3 [3], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3 [2]}), .prdata_o_1_4({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_4 [2]}), .prdata_o_1_2({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2 [3], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2 [2]}), .prdata_o_1_24_3({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_24_3 [1]}), .prdata_o_1_24_4({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_24_4 [1]}), .prdata_o_1_24_2({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_24_2 [1]}), .prdata_o_1_12_2({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [11], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [10], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [9], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [8], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [7], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [6], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [5], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [4]}), .prdata_o_1_12_3({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [11], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [10], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [9], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [8], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [7], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [6], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [5], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [4]}), .prdata_o_1_12_1({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [11], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [10], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [9], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [8], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [7], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [6], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [5], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [4]}), 
        .prdata_o_1_0_iv_6({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [16], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [15], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [14], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [13], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [12]}), 
        .prdata_o_1_0_iv_7({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [16], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [15], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [14], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [13], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [12]}), 
        .prdata_o_1_0_iv_10({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [10], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [9], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [8], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [7], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [6], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [5], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [4]}), 
        .prdata_o_1_0_iv_11({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [10], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [9], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [8], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [7], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [6], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [5], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [4]}), 
        .prdata_o_1_iv_11_0(
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11 [0]), 
        .prdata_o_1_iv_11_1(
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11 [1]), 
        .prdata_o_1_iv_11_3(
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11 [3]), 
        .prdata_o_1_iv_12({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12 [3], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12 [2], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12 [1]}), 
        .USB_ULPI_DATA({USB_ULPI_DATA[7], USB_ULPI_DATA[6], 
        USB_ULPI_DATA[5], USB_ULPI_DATA[4], USB_ULPI_DATA[3], 
        USB_ULPI_DATA[2], USB_ULPI_DATA[1], USB_ULPI_DATA[0]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR({
        MC_System_0_AMBA_SLAVE_1_PADDR[11], 
        MC_System_0_AMBA_SLAVE_1_PADDR[10], 
        MC_System_0_AMBA_SLAVE_1_PADDR[9], 
        MC_System_0_AMBA_SLAVE_1_PADDR[8], 
        MC_System_0_AMBA_SLAVE_1_PADDR[7], 
        MC_System_0_AMBA_SLAVE_1_PADDR[6], 
        MC_System_0_AMBA_SLAVE_1_PADDR[5], 
        MC_System_0_AMBA_SLAVE_1_PADDR[4], 
        MC_System_0_AMBA_SLAVE_1_PADDR[3], 
        MC_System_0_AMBA_SLAVE_1_PADDR[2], 
        MC_System_0_AMBA_SLAVE_1_PADDR[1], 
        MC_System_0_AMBA_SLAVE_1_PADDR[0]}), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA({
        MC_System_0_AMBA_SLAVE_1_PWDATA[23], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[22], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[21], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[20], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[19], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[18], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FIC_0_CLK(
        MC_System_0_FIC_0_CLK), .MC_System_0_FAB_CCC_GL1(
        MC_System_0_FAB_CCC_GL1), .MC_System_0_AMBA_SLAVE_0_PSELx(
        MC_System_0_AMBA_SLAVE_0_PSELx), 
        .MC_System_0_AMBA_SLAVE_1_PSELx(MC_System_0_AMBA_SLAVE_1_PSELx)
        , .N_2661(\Bldc_Axis_0.N_2661 ), .N_1077(\Bldc_Axis_0.N_1077 ), 
        .N_2660(\Bldc_Axis_0.N_2660 ), .N_2785(\Bldc_Axis_0.N_2785 ), 
        .N_1014(\Bldc_Axis_0.N_1014 ), .N_2779(\Bldc_Axis_0.N_2779 ), 
        .N_2704(\Bldc_Axis_0.N_2704 ), .N_184(\Stepper_Axis_0.N_184 ), 
        .adc_channel_ch3_o_1_sqmuxa_0_a2_0_0(
        \Stepper_Axis_0.apb3_if_st_0.adc_channel_ch3_o_1_sqmuxa_0_a2_0_0 )
        , .N_172(\Stepper_Axis_0.N_172 ), .N_174(
        \Stepper_Axis_0.N_174 ), .prdata_o197_0_a2_0_a2_0_out(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o197_0_a2_0_a2_0_out )
        , .prdata_o201_0_a2_0_0(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o201_0_a2_0_0 )
        , .N_201(\Stepper_Axis_0.N_201 ), .N_193(
        \Stepper_Axis_0.N_193 ), .N_187(\Stepper_Axis_0.N_187 ), 
        .N_2470(\Bldc_Axis_0.N_2470 ), .g2(
        \Stepper_Axis_0.apb3_if_st_0.g2 ), .g1(
        \Stepper_Axis_0.apb3_if_st_0.g1 ), .N_106(
        \Stepper_Axis_0.N_106 ), .N_108(\Stepper_Axis_0.N_108 ), 
        .N_202(\Stepper_Axis_0.N_202 ), .N_1083(\Bldc_Axis_0.N_1083 ), 
        .N_104(\Stepper_Axis_0.N_104 ), .N_179(\Stepper_Axis_0.N_179 ), 
        .N_107(\Stepper_Axis_0.N_107 ), .N_105(\Stepper_Axis_0.N_105 ), 
        .N_233(\Stepper_Axis_0.N_233 ), .N_194(\Stepper_Axis_0.N_194 ), 
        .N_1080(\Bldc_Axis_0.N_1080 ), .N_2522(\Bldc_Axis_0.N_2522 ), 
        .N_2784(\Bldc_Axis_0.N_2784 ), .N_1007(\Bldc_Axis_0.N_1007 ), 
        .N_2532(\Bldc_Axis_0.N_2532 ), .N_2778(\Bldc_Axis_0.N_2778 ), 
        .prdata_o195_0_a2_0(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o195_0_a2_0 )
        , .prdata_o191(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o191 ), 
        .N_1508(\Bldc_Axis_0.N_1508 ), .N_2542(\Bldc_Axis_0.N_2542 ), 
        .N_2791(\Bldc_Axis_0.N_2791 ), .N_2734(\Bldc_Axis_0.N_2734 ), 
        .N_2585(\Bldc_Axis_0.N_2585 ), .prdata_o190(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o190 ), 
        .N_2606(\Bldc_Axis_0.N_2606 ), .N_2728(\Bldc_Axis_0.N_2728 ), 
        .N_54(\Stepper_Axis_0.N_54 ), .N_157(\Stepper_Axis_0.N_157 ), 
        .N_151(\Stepper_Axis_0.N_151 ), .N_152(\Stepper_Axis_0.N_152 ), 
        .N_153(\Stepper_Axis_0.N_153 ), .N_154(\Stepper_Axis_0.N_154 ), 
        .N_155(\Stepper_Axis_0.N_155 ), .N_156(\Stepper_Axis_0.N_156 ), 
        .USB_ULPI_XCLK(USB_ULPI_XCLK), .USB_ULPI_STP(USB_ULPI_STP), 
        .USB_ULPI_NXT(USB_ULPI_NXT), .USB_ULPI_DIR(USB_ULPI_DIR), 
        .MC_System_0_AMBA_SLAVE_1_PENABLE(
        MC_System_0_AMBA_SLAVE_1_PENABLE), 
        .MC_System_0_AMBA_SLAVE_1_PWRITE(
        MC_System_0_AMBA_SLAVE_1_PWRITE), .GPIO_0_M2F_c(GPIO_0_M2F_c));
    OUTBUF #( .IOSTD("") )  A1_PWM_WH_O_obuf (.D(A1_PWM_WL_O_c), .PAD(
        A1_PWM_WH_O));
    OUTBUF #( .IOSTD("") )  A1_PWM_UH_O_obuf (.D(A1_PWM_UH_O_c), .PAD(
        A1_PWM_UH_O));
    OUTBUF #( .IOSTD("") )  A1_ADC_SDO_O_obuf (.D(A1_ADC_SDO_O_c), 
        .PAD(A1_ADC_SDO_O));
    OUTBUF #( .IOSTD("") )  A0_ADC_SCK_O_obuf (.D(A0_ADC_SCK_O_c), 
        .PAD(A0_ADC_SCK_O));
    Bldc_Axis Bldc_Axis_0 (.MC_System_0_AMBA_SLAVE_1_PWDATA({
        MC_System_0_AMBA_SLAVE_1_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]}), .prdata_o_1_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0 [3]}), .prdata_o_1_4({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_4 [2]}), 
        .prdata_o_1_0_a2_12_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_12_0 [15]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR({
        MC_System_0_AMBA_SLAVE_1_PADDR[11], 
        MC_System_0_AMBA_SLAVE_1_PADDR[10], 
        MC_System_0_AMBA_SLAVE_1_PADDR[9], 
        MC_System_0_AMBA_SLAVE_1_PADDR[8], 
        MC_System_0_AMBA_SLAVE_1_PADDR[7], 
        MC_System_0_AMBA_SLAVE_1_PADDR[6], 
        MC_System_0_AMBA_SLAVE_1_PADDR[5], 
        MC_System_0_AMBA_SLAVE_1_PADDR[4], 
        MC_System_0_AMBA_SLAVE_1_PADDR[3], 
        MC_System_0_AMBA_SLAVE_1_PADDR[2], 
        MC_System_0_AMBA_SLAVE_1_PADDR[1], 
        MC_System_0_AMBA_SLAVE_1_PADDR[0]}), .prdata_o_1_0_a2_10_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_10_0 [15]}), 
        .prdata_o_1_0_a2_7_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_7_0 [3]}), 
        .prdata_o_1_24_3({\Bldc_Axis_0.apb3_if_0.prdata_o_1_24_3 [1]}), 
        .prdata_o_1_3({\Bldc_Axis_0.apb3_if_0.prdata_o_1_3 [3], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_3 [2]}), .prdata_o_1_0_2({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [16], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [15], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [14], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [13], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_2 [12]}), .prdata_o_1_0_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [16], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [15], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [14], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [13], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0 [12]}), .prdata_o_1_24_2({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_24_2 [1]}), .prdata_o_1_12_3({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [11], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [10], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [9], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [8], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [7], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [6], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [5], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_3 [4]}), .prdata_o_1_12_2({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [11], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [10], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [9], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [8], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [7], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [6], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [5], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_2 [4]}), .prdata_o_1_12_1({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [11], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [10], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [9], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [8], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [7], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [6], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [5], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_12_1 [4]}), .prdata_o_1_2({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2 [3], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_2 [2]}), .prdata_o_1_0_1({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [16], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [15], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [14], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [13], 
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1 [12]}), .prdata_o_1_24_4({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_24_4 [1]}), 
        .MC_System_0_FIC_0_LOCK(MC_System_0_FIC_0_LOCK), 
        .MC_System_0_FIC_0_CLK(MC_System_0_FIC_0_CLK), .A0_PWM_VL_O_c(
        A0_PWM_VL_O_c), .A0_PWM_UH_O_c(A0_PWM_UH_O_c), .A0_PWM_VH_O_c(
        A0_PWM_VH_O_c), .A0_PWM_WH_O_c(A0_PWM_WH_O_c), .N_202(
        \Stepper_Axis_0.N_202 ), .N_185(\Stepper_Axis_0.N_185 ), 
        .N_2791(\Bldc_Axis_0.N_2791 ), .N_2779(\Bldc_Axis_0.N_2779 ), 
        .N_2542(\Bldc_Axis_0.N_2542 ), .N_1508(\Bldc_Axis_0.N_1508 ), 
        .N_1083(\Bldc_Axis_0.N_1083 ), .N_2606(\Bldc_Axis_0.N_2606 ), 
        .N_2585(\Bldc_Axis_0.N_2585 ), .N_1080(\Bldc_Axis_0.N_1080 ), 
        .N_1077(\Bldc_Axis_0.N_1077 ), .N_1014(\Bldc_Axis_0.N_1014 ), 
        .N_176(\Stepper_Axis_0.N_176 ), .N_1007(\Bldc_Axis_0.N_1007 ), 
        .N_2522(\Bldc_Axis_0.N_2522 ), .N_2532(\Bldc_Axis_0.N_2532 ), 
        .MC_System_0_AMBA_SLAVE_1_PWRITE(
        MC_System_0_AMBA_SLAVE_1_PWRITE), 
        .MC_System_0_AMBA_SLAVE_1_PENABLE(
        MC_System_0_AMBA_SLAVE_1_PENABLE), .N_2787(
        \Bldc_Axis_0.N_2787 ), .N_2704(\Bldc_Axis_0.N_2704 ), 
        .adc_channel_ch3_o_1_sqmuxa_0_a2_0_0(
        \Stepper_Axis_0.apb3_if_st_0.adc_channel_ch3_o_1_sqmuxa_0_a2_0_0 )
        , .prdata_o190_0_a2_0_out(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o190_0_a2_0_out )
        , .N_172(\Stepper_Axis_0.N_172 ), .N_2660(\Bldc_Axis_0.N_2660 )
        , .N_2778(\Bldc_Axis_0.N_2778 ), .N_2784(\Bldc_Axis_0.N_2784 ), 
        .prdata_o200_2(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o200_2 ), 
        .N_2470(\Bldc_Axis_0.N_2470 ), .N_2785(\Bldc_Axis_0.N_2785 ), 
        .MC_System_0_AMBA_SLAVE_0_PSELx(MC_System_0_AMBA_SLAVE_0_PSELx)
        , .N_2734(\Bldc_Axis_0.N_2734 ), .N_2661(\Bldc_Axis_0.N_2661 ), 
        .N_2728(\Bldc_Axis_0.N_2728 ), .N_193(\Stepper_Axis_0.N_193 ), 
        .A0_ADC_SDI_I_c(A0_ADC_SDI_I_c), .A0_ADC_SDO_O_c(
        A0_ADC_SDO_O_c), .A0_ADC_CS_O_c(A0_ADC_CS_O_c), 
        .A0_ADC_SCK_O_c(A0_ADC_SCK_O_c));
    Stepper_Axis Stepper_Axis_0 (.STEPPER_THETA_1_step_count_o_2(
        \Stepper_Axis_0.STEPPER_THETA_1_step_count_o [2]), 
        .FOC_TRANSFORMS_0_id_o_2(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o [2]), 
        .FOC_TRANSFORMS_0_id_o_11(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_id_o [11]), 
        .FOC_TRANSFORMS_0_iq_o_2(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o [2]), 
        .FOC_TRANSFORMS_0_iq_o_11(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_iq_o [11]), 
        .SPEED_ID_IQ_PI_1_iq_pi_output_o_0(
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_iq_pi_output_o [0]), 
        .FOC_TRANSFORMS_1_valpha_o_11(
        \Stepper_Axis_0.FOC_TRANSFORMS_1_valpha_o [11]), 
        .FOC_TRANSFORMS_0_vbeta_o_11(
        \Stepper_Axis_0.FOC_TRANSFORMS_0_vbeta_o [11]), 
        .ADC_SCALING_0_ib_adc_o_2(
        \Stepper_Axis_0.ADC_SCALING_0_ib_adc_o [2]), 
        .adc_interface_0_result_ch0_o_2(
        \Stepper_Axis_0.adc_interface_0_result_ch0_o [2]), 
        .adc_interface_0_result_ch2_o_2(
        \Stepper_Axis_0.adc_interface_0_result_ch2_o [2]), 
        .SEQ_CONTROLLER_1_state_o_0_2(
        \Stepper_Axis_0.SEQ_CONTROLLER_1_state_o_0 [2]), 
        .MC_System_0_AMBA_SLAVE_1_PWDATA({
        MC_System_0_AMBA_SLAVE_1_PWDATA[23], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[22], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[21], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[20], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[19], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[18], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_1_PWDATA[0]}), 
        .MC_System_0_AMBA_SLAVE_1_PADDR({
        MC_System_0_AMBA_SLAVE_1_PADDR[11], 
        MC_System_0_AMBA_SLAVE_1_PADDR[10], 
        MC_System_0_AMBA_SLAVE_1_PADDR[9], 
        MC_System_0_AMBA_SLAVE_1_PADDR[8], 
        MC_System_0_AMBA_SLAVE_1_PADDR[7], 
        MC_System_0_AMBA_SLAVE_1_PADDR[6], 
        MC_System_0_AMBA_SLAVE_1_PADDR[5], 
        MC_System_0_AMBA_SLAVE_1_PADDR[4], 
        MC_System_0_AMBA_SLAVE_1_PADDR[3], 
        MC_System_0_AMBA_SLAVE_1_PADDR[2], 
        MC_System_0_AMBA_SLAVE_1_PADDR[1], 
        MC_System_0_AMBA_SLAVE_1_PADDR[0]}), .prdata_o_1_0_a2_7_0({
        \Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_7_0 [3]}), 
        .prdata_o_1_iv_12_0_2({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12_0_2 [3]}), 
        .prdata_o_1_iv_12_1({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12_1 [3]}), 
        .SPEED_ID_IQ_PI_1_id_pi_output_o_m({
        \Stepper_Axis_0.SPEED_ID_IQ_PI_1_id_pi_output_o_m [0]}), 
        .prdata_o_1_iv_9({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_9 [0]}), 
        .prdata_o_1_iv_12({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12 [3], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12 [2], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_12 [1]}), 
        .prdata_o_1_0_iv_11({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [10], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [9], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [8], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [7], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [6], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [5], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_11 [4]}), 
        .prdata_o_1_0_iv_6({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [16], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [15], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [14], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [13], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_6 [12]}), 
        .prdata_o_1_0_iv_7({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [16], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [15], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [14], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [13], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_7 [12]}), 
        .prdata_o_1_iv_11_3(
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11 [3]), 
        .prdata_o_1_iv_11_1(
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11 [1]), 
        .prdata_o_1_iv_11_0(
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11 [0]), 
        .prdata_o_1_0_iv_10({
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [10], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [9], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [8], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [7], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [6], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [5], 
        \Stepper_Axis_0.apb3_if_st_0.prdata_o_1_0_iv_10 [4]}), 
        .adc_measurements_0_adc_result_ch1_o_2(
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch1_o [2]), 
        .adc_measurements_0_adc_result_ch3_o_2(
        \Stepper_Axis_0.adc_measurements_0_adc_result_ch3_o [2]), 
        .MC_System_0_FIC_0_LOCK(MC_System_0_FIC_0_LOCK), 
        .MC_System_0_FAB_CCC_GL1(MC_System_0_FAB_CCC_GL1), 
        .A1_PWM_WL_O_c(A1_PWM_WL_O_c), .A1_PWM_UH_O_c(A1_PWM_UH_O_c), 
        .A1_PWM_VH_O_c(A1_PWM_VH_O_c), .A1_PWM_UL_O_c(A1_PWM_UL_O_c), 
        .A1_PWM_VL_O_c(A1_PWM_VL_O_c), .N_193(\Stepper_Axis_0.N_193 ), 
        .N_194(\Stepper_Axis_0.N_194 ), .N_184(\Stepper_Axis_0.N_184 ), 
        .prdata_o197_0_a2_0_a2_0_out(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o197_0_a2_0_a2_0_out )
        , .N_185(\Stepper_Axis_0.N_185 ), .N_174(
        \Stepper_Axis_0.N_174 ), .prdata_o201_0_a2_0_0(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o201_0_a2_0_0 )
        , .g1(\Stepper_Axis_0.apb3_if_st_0.g1 ), .g2(
        \Stepper_Axis_0.apb3_if_st_0.g2 ), .N_172(
        \Stepper_Axis_0.N_172 ), .N_187(\Stepper_Axis_0.N_187 ), 
        .N_104(\Stepper_Axis_0.N_104 ), .N_105(\Stepper_Axis_0.N_105 ), 
        .N_106(\Stepper_Axis_0.N_106 ), .N_107(\Stepper_Axis_0.N_107 ), 
        .N_108(\Stepper_Axis_0.N_108 ), 
        .adc_channel_ch3_o_1_sqmuxa_0_a2_0_0(
        \Stepper_Axis_0.apb3_if_st_0.adc_channel_ch3_o_1_sqmuxa_0_a2_0_0 )
        , .prdata_o195_0_a2_0(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o195_0_a2_0 )
        , .prdata_o190_0_a2_0_out(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o190_0_a2_0_out )
        , .N_202(\Stepper_Axis_0.N_202 ), .prdata_o200_2(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o200_2 ), 
        .N_176(\Stepper_Axis_0.N_176 ), .N_201(\Stepper_Axis_0.N_201 ), 
        .N_179(\Stepper_Axis_0.N_179 ), .N_233(\Stepper_Axis_0.N_233 ), 
        .N_2787(\Bldc_Axis_0.N_2787 ), 
        .MC_System_0_AMBA_SLAVE_1_PWRITE(
        MC_System_0_AMBA_SLAVE_1_PWRITE), 
        .MC_System_0_AMBA_SLAVE_1_PSELx(MC_System_0_AMBA_SLAVE_1_PSELx)
        , .MC_System_0_AMBA_SLAVE_1_PENABLE(
        MC_System_0_AMBA_SLAVE_1_PENABLE), .prdata_o191(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o191 ), 
        .prdata_o190(
        \Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC.prdata_o190 ), 
        .N_2470(\Bldc_Axis_0.N_2470 ), .N_151(\Stepper_Axis_0.N_151 ), 
        .N_152(\Stepper_Axis_0.N_152 ), .N_153(\Stepper_Axis_0.N_153 ), 
        .N_154(\Stepper_Axis_0.N_154 ), .N_155(\Stepper_Axis_0.N_155 ), 
        .N_156(\Stepper_Axis_0.N_156 ), .N_157(\Stepper_Axis_0.N_157 ), 
        .N_54(\Stepper_Axis_0.N_54 ), .A1_ADC_SDI_I_c(A1_ADC_SDI_I_c), 
        .A1_ADC_SDO_O_c(A1_ADC_SDO_O_c), .A1_ADC_CS_O_c(A1_ADC_CS_O_c), 
        .A1_ADC_SCK_O_c(A1_ADC_SCK_O_c));
    OUTBUF #( .IOSTD("") )  A0_PWM_WH_O_obuf (.D(A0_PWM_WH_O_c), .PAD(
        A0_PWM_WH_O));
    OUTBUF #( .IOSTD("") )  A0_PWM_VL_O_obuf (.D(A0_PWM_VL_O_c), .PAD(
        A0_PWM_VL_O));
    OUTBUF #( .IOSTD("") )  A0_PWM_UL_O_obuf (.D(A0_PWM_VL_O_c), .PAD(
        A0_PWM_UL_O));
    OUTBUF #( .IOSTD("") )  A1_PWM_VL_O_obuf (.D(A1_PWM_VL_O_c), .PAD(
        A1_PWM_VL_O));
    OUTBUF #( .IOSTD("") )  A0_ADC_SDO_O_obuf (.D(A0_ADC_SDO_O_c), 
        .PAD(A0_ADC_SDO_O));
    OUTBUF #( .IOSTD("") )  GPIO_0_M2F_obuf (.D(GPIO_0_M2F_c), .PAD(
        GPIO_0_M2F));
    OUTBUF #( .IOSTD("") )  A0_ADC_CS_O_obuf (.D(A0_ADC_CS_O_c), .PAD(
        A0_ADC_CS_O));
    OUTBUF #( .IOSTD("") )  A1_RUNNING_LED_obuf (.D(A1_PWM_VL_O_c), 
        .PAD(A1_RUNNING_LED));
    OUTBUF #( .IOSTD("") )  A1_ADC_CS_O_obuf (.D(A1_ADC_CS_O_c), .PAD(
        A1_ADC_CS_O));
    OUTBUF #( .IOSTD("") )  A1_PWM_WL_O_obuf (.D(A1_PWM_WL_O_c), .PAD(
        A1_PWM_WL_O));
    OUTBUF #( .IOSTD("") )  A1_ADC_SCK_O_obuf (.D(A1_ADC_SCK_O_c), 
        .PAD(A1_ADC_SCK_O));
    OUTBUF #( .IOSTD("") )  A0_RUNNING_LED_obuf (.D(A0_PWM_VL_O_c), 
        .PAD(A0_RUNNING_LED));
    INBUF #( .IOSTD("") )  A0_ADC_SDI_I_ibuf (.PAD(A0_ADC_SDI_I), .Y(
        A0_ADC_SDI_I_c));
    
endmodule
