Timing Report Max Delay Analysis

SmartTime Version Libero SoC v11.8 SP1
Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)
Date: Wed Oct 04 15:15:46 2017


Design: MC_System_top
Family: SmartFusion2
Die: M2S010
Package: 484 FBGA
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0                       
Period (ns):                9.727                                                                           
Frequency (MHz):            102.807                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -0.899                                                                          
External Hold (ns):         1.038                                                                           
Min Clock-To-Out (ns):      4.843                                                                           
Max Clock-To-Out (ns):      12.357                                                                          

Clock Domain:               MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1                       
Period (ns):                7.786                                                                           
Frequency (MHz):            128.436                                                                         
Required Period (ns):       10.000                                                                          
Required Frequency (MHz):   100.000                                                                         
External Setup (ns):        -0.739                                                                          
External Hold (ns):         0.932                                                                           
Min Clock-To-Out (ns):      5.367                                                                           
Max Clock-To-Out (ns):      9.513                                                                           

Clock Domain:               MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT                     
Period (ns):                N/A                                                                             
Frequency (MHz):            N/A                                                                             
Required Period (ns):       20.000                                                                          
Required Frequency (MHz):   50.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

                            Input to Output                                                                 
Min Delay (ns):             N/A                                                                             
Max Delay (ns):             N/A                                                                             

END SUMMARY
-----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:EN
  Delay (ns):                  9.140                                                                           
  Slack (ns):                  0.273                                                                           
  Arrival (ns):                13.630                                                                          
  Required (ns):               13.903                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.727                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[9]:EN
  Delay (ns):                  9.139                                                                           
  Slack (ns):                  0.283                                                                           
  Arrival (ns):                13.629                                                                          
  Required (ns):               13.912                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.717                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_ki_o[8]:EN
  Delay (ns):                  9.139                                                                           
  Slack (ns):                  0.283                                                                           
  Arrival (ns):                13.629                                                                          
  Required (ns):               13.912                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.717                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_kp_o[9]:EN
  Delay (ns):                  8.949                                                                           
  Slack (ns):                  0.464                                                                           
  Arrival (ns):                13.439                                                                          
  Required (ns):               13.903                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.536                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Bldc_Axis_0/apb3_if_0/angle_kp_o[10]:EN
  Delay (ns):                  8.949                                                                           
  Slack (ns):                  0.464                                                                           
  Arrival (ns):                13.439                                                                          
  Required (ns):               13.903                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         9.536                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:EN
  data required time                             13.903    
  data arrival time                          -   13.630    
  slack                                          0.273     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.349          cell: ADLIB:MSS_010_IP
  5.839                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[14] (f)
               +     0.829          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[14]
  6.668                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:A (f)
               +     0.099          cell: ADLIB:CFG2
  6.767                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:Y (r)
               +     0.522          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/AMBA_SLAVE_0_PSELS0_i_2
  7.289                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[0]:D (r)
               +     0.074          cell: ADLIB:CFG4
  7.363                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[0]:Y (r)
               +     1.791          net: MC_System_0_AMBA_SLAVE_0_PSELx
  9.154                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:B (r)
               +     0.270          cell: ADLIB:CFG4
  9.424                        Bldc_Axis_0/apb3_if_0/direction_config_o_1_sqmuxa_0_a2_0:Y (r)
               +     0.836          net: Bldc_Axis_0/apb3_if_0/N_1807
  10.260                       Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:D (r)
               +     0.158          cell: ADLIB:CFG4
  10.418                       Bldc_Axis_0/apb3_if_0/filter_factor_omega_o_1_sqmuxa_0_a2_1:Y (r)
               +     0.734          net: Bldc_Axis_0/apb3_if_0/N_1819
  11.152                       Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa_0_a2:A (r)
               +     0.158          cell: ADLIB:CFG3
  11.310                       Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa_0_a2:Y (r)
               +     2.320          net: Bldc_Axis_0/apb3_if_0/angle_ki_o_1_sqmuxa
  13.630                       Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:EN (r)
                                    
  13.630                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn (f)
               +     0.288          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth
  13.435                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB26:An (f)
               +     0.251          cell: ADLIB:RGB
  13.686                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB26:YL (r)
               +     0.471          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB26_rgbl_net_1
  14.157                       Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.903                       Bldc_Axis_0/apb3_if_0/angle_ki_o[10]:EN
                                    
  13.903                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A0_ADC_SDI_I
  To:                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  2.994                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                2.994                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.165                                                                           
  External Setup (ns):         -0.899                                                                          


Expanded Path 1
  From: A0_ADC_SDI_I
  To: Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   2.994     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A0_ADC_SDI_I (f)
               +     0.000          net: A0_ADC_SDI_I
  0.000                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A0_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.392          net: A0_ADC_SDI_I_ibuf/U0/YIN1
  1.792                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.159          cell: ADLIB:IOINFF_BYPASS
  1.951                        A0_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     1.043          net: A0_ADC_SDI_I_c
  2.994                        Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  2.994                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.160          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.273          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YR (r)
               +     0.491          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbr_net_1
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.165          Library setup time: ADLIB:SLE
  N/C                          Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Bldc_Axis_0/MSC_i_11/s_state[8]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  8.185                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                12.357                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           12.357                                                                          

Path 2
  From:                        Bldc_Axis_0/MSC_i_11/s_state[0]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  7.991                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                12.144                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           12.144                                                                          

Path 3
  From:                        Bldc_Axis_0/MSC_i_11/s_state[7]:CLK
  To:                          A0_RUNNING_LED
  Delay (ns):                  7.782                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.952                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.952                                                                          

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_STP
  Delay (ns):                  6.768                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.258                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.258                                                                          

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          USB_ULPI_DATA[0]
  Delay (ns):                  6.758                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.248                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.248                                                                          


Expanded Path 1
  From: Bldc_Axis_0/MSC_i_11/s_state[8]:CLK
  To: A0_RUNNING_LED
  data required time                             N/C       
  data arrival time                          -   12.357    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.274          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.420                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13:An (f)
               +     0.251          cell: ADLIB:RGB
  3.671                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13:YL (r)
               +     0.501          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB13_rgbl_net_1
  4.172                        Bldc_Axis_0/MSC_i_11/s_state[8]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.259                        Bldc_Axis_0/MSC_i_11/s_state[8]:Q (r)
               +     0.807          net: Bldc_Axis_0/MSC_i_11/MSC_net_83
  5.066                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:B (r)
               +     0.143          cell: ADLIB:CFG2
  5.209                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un101_s_state_i_a2_0_a3:Y (f)
               +     0.237          net: Bldc_Axis_0/MSC_i_11/MSC_net_285
  5.446                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.533                        Bldc_Axis_0/MSC_i_11/ADC_START_PROC.un103_s_state_i_a3_0_a2:Y (f)
               +     3.091          net: A0_PWM_UL_O_c
  8.624                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  8.954                        A0_RUNNING_LED_obuf/U0/U_IOOUTFF:Y (f)
               +     0.701          net: A0_RUNNING_LED_obuf/U0/DOUT
  9.655                        A0_RUNNING_LED_obuf/U0/U_IOPAD:D (f)
               +     2.702          cell: ADLIB:IOPAD_TRI
  12.357                       A0_RUNNING_LED_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A0_RUNNING_LED
  12.357                       A0_RUNNING_LED (f)
                                    
  12.357                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A0_RUNNING_LED (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

Path 1
  From:                        Stepper_Axis_0/MSC_i_45/s_theta_output[4]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[4]
  Delay (ns):                  5.446                                                                           
  Slack (ns):                  4.463                                                                           
  Arrival (ns):                9.644                                                                           
  Required (ns):               14.107                                                                          
  Setup (ns):                  0.377                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_45/s_theta_output[17]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[22]
  Delay (ns):                  5.552                                                                           
  Slack (ns):                  4.476                                                                           
  Arrival (ns):                9.744                                                                           
  Required (ns):               14.220                                                                          
  Setup (ns):                  0.264                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_45/s_theta_output[9]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[9]
  Delay (ns):                  5.459                                                                           
  Slack (ns):                  4.508                                                                           
  Arrival (ns):                9.669                                                                           
  Required (ns):               14.177                                                                          
  Setup (ns):                  0.307                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_45/s_step_cnt[4]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[4]
  Delay (ns):                  5.215                                                                           
  Slack (ns):                  4.711                                                                           
  Arrival (ns):                9.396                                                                           
  Required (ns):               14.107                                                                          
  Setup (ns):                  0.377                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_43/s_ia[4]:CLK
  To:                          MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[4]
  Delay (ns):                  5.192                                                                           
  Slack (ns):                  4.720                                                                           
  Arrival (ns):                9.387                                                                           
  Required (ns):               14.107                                                                          
  Setup (ns):                  0.377                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_45/s_theta_output[4]:CLK
  To: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[4]
  data required time                             14.107    
  data arrival time                          -   9.644     
  slack                                          4.463     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.287          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.434                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9:An (f)
               +     0.251          cell: ADLIB:RGB
  3.685                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9:YL (r)
               +     0.513          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB9_rgbl_net_1
  4.198                        Stepper_Axis_0/MSC_i_45/s_theta_output[4]:CLK (r)
               +     0.092          cell: ADLIB:SLE
  4.290                        Stepper_Axis_0/MSC_i_45/s_theta_output[4]:Q (r)
               +     1.591          net: Stepper_Axis_0/STEPPER_THETA_0_theta_output_o[4]
  5.881                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8_RNO_0[4]:C (r)
               +     0.270          cell: ADLIB:CFG4
  6.151                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8_RNO_0[4]:Y (r)
               +     0.225          net: Stepper_Axis_0/apb3_if_st_0/STEPPER_THETA_0_theta_output_o_m_out
  6.376                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8[4]:D (r)
               +     0.158          cell: ADLIB:CFG4
  6.534                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8[4]:Y (r)
               +     0.631          net: Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_8[4]
  7.165                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_7[4]:C (r)
               +     0.158          cell: ADLIB:CFG3
  7.323                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_7[4]:Y (r)
               +     0.651          net: Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv_7_Z[4]
  7.974                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv[4]:D (r)
               +     0.074          cell: ADLIB:CFG4
  8.048                        Stepper_Axis_0/apb3_if_st_0/prdata_o_1_0_iv[4]:Y (r)
               +     0.222          net: MC_System_0_AMBA_SLAVE_1_PRDATA[4]
  8.270                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA[4]:A (r)
               +     0.158          cell: ADLIB:CFG4
  8.428                        MC_System_0/MC_System_sb_0/CoreAPB3_0/u_mux_p_to_b3/PRDATA[4]:Y (r)
               +     0.787          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]
  9.215                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_6:A (r)
               +     0.194          cell: ADLIB:IP_INTERFACE
  9.409                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_6:IPA (r)
               +     0.235          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[4]
  9.644                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[4] (r)
                                    
  9.644                        data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  13.146                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  13.430                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  13.680                       MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  14.065                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  14.274                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.210          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  14.484                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               -     0.377          Library setup time: ADLIB:MSS_010_IP
  14.107                       MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_RDATA[4]
                                    
  14.107                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

SET Register to Register

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:D
  Delay (ns):                  7.537                                                                           
  Slack (ns):                  2.214                                                                           
  Arrival (ns):                11.707                                                                          
  Required (ns):               13.921                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.786                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[11]:D
  Delay (ns):                  7.539                                                                           
  Slack (ns):                  2.219                                                                           
  Arrival (ns):                11.709                                                                          
  Required (ns):               13.928                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.781                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[14]:D
  Delay (ns):                  7.538                                                                           
  Slack (ns):                  2.220                                                                           
  Arrival (ns):                11.708                                                                          
  Required (ns):               13.928                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.780                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[12]:D
  Delay (ns):                  7.538                                                                           
  Slack (ns):                  2.220                                                                           
  Arrival (ns):                11.708                                                                          
  Required (ns):               13.928                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.780                                                                           

Path 5
  From:                        Stepper_Axis_0/MSC_i_42/s_state[4]:CLK
  To:                          Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:D
  Delay (ns):                  7.500                                                                           
  Slack (ns):                  2.239                                                                           
  Arrival (ns):                11.682                                                                          
  Required (ns):               13.921                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.761                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/s_state[2]:CLK
  To: Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:D
  data required time                             13.921    
  data arrival time                          -   11.707    
  slack                                          2.214     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.436                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:An (f)
               +     0.250          cell: ADLIB:RGB
  3.686                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:YR (r)
               +     0.484          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13_rgbr_net_1
  4.170                        Stepper_Axis_0/MSC_i_42/s_state[2]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.257                        Stepper_Axis_0/MSC_i_42/s_state[2]:Q (r)
               +     0.351          net: Stepper_Axis_0/MSC_i_42/MSC_net_86
  4.608                        Stepper_Axis_0/MSC_i_42/s_state_RNIRILT[4]:D (r)
               +     0.202          cell: ADLIB:CFG4
  4.810                        Stepper_Axis_0/MSC_i_42/s_state_RNIRILT[4]:Y (r)
               +     0.877          net: Stepper_Axis_0/SEQ_CONTROLLER_1_en_idq_pi_o
  5.687                        Stepper_Axis_0/MSC_i_47/MSC_i_50/en_o:B (r)
               +     0.074          cell: ADLIB:CFG3
  5.761                        Stepper_Axis_0/MSC_i_47/MSC_i_50/en_o:Y (r)
               +     0.754          net: Stepper_Axis_0/MSC_i_47/MSC_net_516
  6.515                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]:B (r)
               +     0.209          cell: ADLIB:ARI1_CC
  6.724                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]:UB (r)
               +     0.000          net: NET_CC_CONFIG6728
  6.724                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_0:UB[0] (r)
               +     0.701          cell: ADLIB:CC_CONFIG
  7.425                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_0:CO (f)
               +     0.000          net: CI_TO_CO6725
  7.425                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:CI (f)
               +     0.233          cell: ADLIB:CC_CONFIG
  7.658                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_inew_RNIH2E71[16]_CC_1:CC[4] (f)
               +     0.000          net: NET_CC_CONFIG6777
  7.658                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIRMTSL[26]:CC (f)
               +     0.073          cell: ADLIB:ARI1_CC
  7.731                        Stepper_Axis_0/MSC_i_47/MSC_i_48/s_pout_RNIRMTSL[26]:S (f)
               +     0.618          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_240
  8.349                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_16_RNO:A (f)
               +     0.099          cell: ADLIB:CFG1
  8.448                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_16_RNO:Y (r)
               +     0.659          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_273
  9.107                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_16:A (r)
               +     0.134          cell: ADLIB:ARI1_CC
  9.241                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_16:P (f)
               +     0.000          net: NET_CC_CONFIG927
  9.241                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:P[0] (f)
               +     0.573          cell: ADLIB:CC_CONFIG
  9.814                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_0:CO (r)
               +     0.000          net: CI_TO_CO926
  9.814                        Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CI (r)
               +     0.292          cell: ADLIB:CC_CONFIG
  10.106                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_16_CC_1:CC[7] (r)
               +     0.000          net: NET_CC_CONFIG986
  10.106                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CC (r)
               +     0.066          cell: ADLIB:FCEND_BUFF_CC
  10.172                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC_un10_s_piout_cry_34_FCINST1:CO (r)
               +     0.884          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_945
  11.056                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:B (r)
               +     0.100          cell: ADLIB:CFG2
  11.156                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.un10_s_piout_cry_34_RNIO6SB:Y (f)
               +     0.379          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_1054
  11.535                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[7]:B (f)
               +     0.099          cell: ADLIB:CFG4
  11.634                       Stepper_Axis_0/MSC_i_47/MSC_i_48/PI_CONT_FSM_PROC.acc_out_o_2[7]:Y (r)
               +     0.073          net: Stepper_Axis_0/MSC_i_47/MSC_i_48/MSC_net_675
  11.707                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:D (r)
                                    
  11.707                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.292          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.439                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB22:An (f)
               +     0.250          cell: ADLIB:RGB
  13.689                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB22:YR (r)
               +     0.486          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB22_rgbr_net_1
  14.175                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  13.921                       Stepper_Axis_0/MSC_i_47/MSC_i_48/acc_out_o[7]:D
                                    
  13.921                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A1_ADC_SDI_I
  To:                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  Delay (ns):                  3.146                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                3.146                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.174                                                                           
  External Setup (ns):         -0.739                                                                          


Expanded Path 1
  From: A1_ADC_SDI_I
  To: Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D
  data required time                             N/C       
  data arrival time                          -   3.146     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        A1_ADC_SDI_I (f)
               +     0.000          net: A1_ADC_SDI_I
  0.000                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD (f)
               +     1.400          cell: ADLIB:IOPAD_IN
  1.400                        A1_ADC_SDI_I_ibuf/U0/U_IOPAD:Y (f)
               +     0.112          net: A1_ADC_SDI_I_ibuf/U0/YIN1
  1.512                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:A (f)
               +     0.141          cell: ADLIB:IOINFF_BYPASS
  1.653                        A1_ADC_SDI_I_ibuf/U0/U_IOINFF:Y (f)
               +     1.493          net: A1_ADC_SDI_I_c
  3.146                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D (f)
                                    
  3.146                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.700          Clock generation
  N/C                          
               +     0.191          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.161          cell: ADLIB:GB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.280          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB14:An (f)
               +     0.243          cell: ADLIB:RGB
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB14:YR (r)
               +     0.484          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB14_rgbr_net_1
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK (r)
               -     0.174          Library setup time: ADLIB:SLE
  N/C                          Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  5.326                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.513                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.513                                                                           

Path 2
  From:                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  5.323                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.510                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.510                                                                           

Path 3
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WL_O
  Delay (ns):                  5.116                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.291                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.291                                                                           

Path 4
  From:                        Stepper_Axis_0/MSC_i_42/s_state[8]:CLK
  To:                          A1_PWM_WH_O
  Delay (ns):                  5.113                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.288                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.288                                                                           

Path 5
  From:                        Stepper_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sck:CLK
  To:                          A1_ADC_SCK_O
  Delay (ns):                  5.073                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.251                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.251                                                                           


Expanded Path 1
  From: Stepper_Axis_0/MSC_i_42/s_state[0]:CLK
  To: A1_PWM_WL_O
  data required time                             N/C       
  data arrival time                          -   9.513     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  3.147                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.289          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  3.436                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:An (f)
               +     0.250          cell: ADLIB:RGB
  3.686                        MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13:YR (r)
               +     0.501          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB13_rgbr_net_1
  4.187                        Stepper_Axis_0/MSC_i_42/s_state[0]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  4.274                        Stepper_Axis_0/MSC_i_42/s_state[0]:Q (r)
               +     0.686          net: Stepper_Axis_0/MSC_i_42/MSC_net_88
  4.960                        Stepper_Axis_0/MSC_i_42/s_state_RNIUPQE[8]:A (r)
               +     0.143          cell: ADLIB:CFG2
  5.103                        Stepper_Axis_0/MSC_i_42/s_state_RNIUPQE[8]:Y (f)
               +     0.236          net: Stepper_Axis_0/MSC_i_42/MSC_net_255
  5.339                        Stepper_Axis_0/MSC_i_42/ADC_START_PROC.un103_s_state_i_a2_0_a2_0_a2:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.426                        Stepper_Axis_0/MSC_i_42/ADC_START_PROC.un103_s_state_i_a2_0_a2_0_a2:Y (f)
               +     1.975          net: A1_PWM_WH_O_c
  7.401                        A1_PWM_WL_O_obuf/U0/U_IOOUTFF:A (f)
               +     0.330          cell: ADLIB:IOOUTFF_BYPASS
  7.731                        A1_PWM_WL_O_obuf/U0/U_IOOUTFF:Y (f)
               +     0.096          net: A1_PWM_WL_O_obuf/U0/DOUT
  7.827                        A1_PWM_WL_O_obuf/U0/U_IOPAD:D (f)
               +     1.686          cell: ADLIB:IOPAD_TRI
  9.513                        A1_PWM_WL_O_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: A1_PWM_WL_O
  9.513                        A1_PWM_WL_O (f)
                                    
  9.513                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  N/C                          MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  N/C                          
                                    
  N/C                          A1_PWM_WL_O (f)


END SET Clock to Output

----------------------------------------------------

SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

Path 1
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[1]:EN
  Delay (ns):                  8.237                                                                           
  Slack (ns):                  1.132                                                                           
  Arrival (ns):                12.727                                                                          
  Required (ns):               13.859                                                                          
  Setup (ns):                  0.308                                                                           

Path 2
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[15]:EN
  Delay (ns):                  8.237                                                                           
  Slack (ns):                  1.132                                                                           
  Arrival (ns):                12.727                                                                          
  Required (ns):               13.859                                                                          
  Setup (ns):                  0.308                                                                           

Path 3
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[16]:EN
  Delay (ns):                  8.237                                                                           
  Slack (ns):                  1.132                                                                           
  Arrival (ns):                12.727                                                                          
  Required (ns):               13.859                                                                          
  Setup (ns):                  0.308                                                                           

Path 4
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[17]:EN
  Delay (ns):                  8.237                                                                           
  Slack (ns):                  1.132                                                                           
  Arrival (ns):                12.727                                                                          
  Required (ns):               13.859                                                                          
  Setup (ns):                  0.308                                                                           

Path 5
  From:                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To:                          Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[14]:EN
  Delay (ns):                  8.237                                                                           
  Slack (ns):                  1.143                                                                           
  Arrival (ns):                12.727                                                                          
  Required (ns):               13.870                                                                          
  Setup (ns):                  0.308                                                                           


Expanded Path 1
  From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE
  To: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[1]:EN
  data required time                             13.859    
  data arrival time                          -   12.727    
  slack                                          1.132     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     2.784          Clock generation
  2.784                        
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_net
  2.981                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An (r)
               +     0.165          cell: ADLIB:GB
  3.146                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn (f)
               +     0.284          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn
  3.430                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.250          cell: ADLIB:RGB
  3.680                        MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.385          net: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR
  4.065                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  4.274                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB (r)
               +     0.216          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  4.490                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE (r)
               +     1.350          cell: ADLIB:MSS_010_IP
  5.840                        MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[14] (r)
               +     0.828          net: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[14]
  6.668                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:A (r)
               +     0.100          cell: ADLIB:CFG2
  6.768                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw_2[0]:Y (f)
               +     0.437          net: MC_System_0/MC_System_sb_0/CoreAPB3_0/AMBA_SLAVE_0_PSELS0_i_2
  7.205                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:D (f)
               +     0.087          cell: ADLIB:CFG4
  7.292                        MC_System_0/MC_System_sb_0/CoreAPB3_0/iPSELS_raw[1]:Y (f)
               +     0.883          net: MC_System_0_AMBA_SLAVE_1_PSELx
  8.175                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:B (f)
               +     0.164          cell: ADLIB:CFG4
  8.339                        Stepper_Axis_0/apb3_if_st_0/adc_oc_thresh_o_1_sqmuxa_1:Y (f)
               +     0.665          net: Stepper_Axis_0/apb3_if_st_0/sqmng_dv_o_1_sqmuxa_1
  9.004                        Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7:C (f)
               +     0.087          cell: ADLIB:CFG3
  9.091                        Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7:Y (f)
               +     0.690          net: Stepper_Axis_0/apb3_if_st_0/idq_pi_kp_o_0_sqmuxa_7_Z
  9.781                        Stepper_Axis_0/apb3_if_st_0/adc_scale_val_o_1_sqmuxa_0:B (f)
               +     0.087          cell: ADLIB:CFG2
  9.868                        Stepper_Axis_0/apb3_if_st_0/adc_scale_val_o_1_sqmuxa_0:Y (f)
               +     0.233          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_0
  10.101                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2:D (f)
               +     0.209          cell: ADLIB:CFG4
  10.310                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2:Y (f)
               +     0.300          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_2_Z
  10.610                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa:D (f)
               +     0.287          cell: ADLIB:CFG4
  10.897                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa:Y (f)
               +     1.830          net: Stepper_Axis_0/apb3_if_st_0/id_ref_val_o_1_sqmuxa_Z
  12.727                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[1]:EN (f)
                                    
  12.727                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1
               +     0.000          Clock source
  10.000                       MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 (r)
               +     2.784          Clock generation
  12.784                       
               +     0.197          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_net
  12.981                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:An (r)
               +     0.166          cell: ADLIB:GB
  13.147                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST:YSn (f)
               +     0.291          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_YNn_GSouth
  13.438                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB16:An (f)
               +     0.250          cell: ADLIB:RGB
  13.688                       MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB16:YR (r)
               +     0.479          net: MC_System_0/MC_System_sb_0/CCC_0/GL1_INST/U0_RGB1_RGB16_rgbr_net_1
  14.167                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[1]:CLK (r)
               -     0.308          Library setup time: ADLIB:SLE
  13.859                       Stepper_Axis_0/apb3_if_st_0/id_ref_val_o[1]:EN
                                    
  13.859                       data required time


END SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

No Path 

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path 

END SET Input to Output

----------------------------------------------------

Path set User Sets

