----------------------------------------------------------------------
-- Created by SmartDesign Tue Nov 14 17:35:36 2017
-- Version: v11.8 SP2 11.8.2.4
----------------------------------------------------------------------

----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library smartfusion2;
use smartfusion2.all;
library ADC_SCALING_LIB;
use ADC_SCALING_LIB.all;
library SINC3_FILTER_LIB;
use SINC3_FILTER_LIB.all;
----------------------------------------------------------------------
-- Bldc_Axis entity declaration
----------------------------------------------------------------------
entity Bldc_Axis is
    -- Port list
    port(
        -- Inputs
        adc_sdi_i    : in  std_logic;
        clk_adc_i    : in  std_logic;
        data_adc_COS : in  std_logic;
        data_adc_SIN : in  std_logic;
        paddr_i_0    : in  std_logic_vector(31 downto 0);
        penable_i_0  : in  std_logic;
        psel_i_0     : in  std_logic;
        pwdata_i_0   : in  std_logic_vector(31 downto 0);
        pwrite_i_0   : in  std_logic;
        reset_i      : in  std_logic;
        sys_clk_i    : in  std_logic;
        -- Outputs
        adc_cs_o     : out std_logic;
        adc_sck_o    : out std_logic;
        adc_sdo_o    : out std_logic;
        hf_signal_o  : out std_logic;
        prdata_o_0   : out std_logic_vector(31 downto 0);
        pready_o_0   : out std_logic;
        pslverr_o_0  : out std_logic;
        pwm_uh       : out std_logic;
        pwm_ul       : out std_logic;
        pwm_vh       : out std_logic;
        pwm_vl       : out std_logic;
        pwm_wh       : out std_logic;
        pwm_wl       : out std_logic
        );
end Bldc_Axis;
----------------------------------------------------------------------
-- Bldc_Axis architecture body
----------------------------------------------------------------------
architecture RTL of Bldc_Axis is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- adc_interface_795x
component adc_interface_795x
    -- Port list
    port(
        -- Inputs
        channels_to_sample_i : in  std_logic_vector(15 downto 0);
        reset_i              : in  std_logic;
        sdi_i                : in  std_logic;
        start_i              : in  std_logic;
        sys_clk_i            : in  std_logic;
        -- Outputs
        cs_o                 : out std_logic;
        done_o               : out std_logic;
        result_ch0_o         : out std_logic_vector(11 downto 0);
        result_ch10_o        : out std_logic_vector(11 downto 0);
        result_ch11_o        : out std_logic_vector(11 downto 0);
        result_ch12_o        : out std_logic_vector(11 downto 0);
        result_ch13_o        : out std_logic_vector(11 downto 0);
        result_ch14_o        : out std_logic_vector(11 downto 0);
        result_ch15_o        : out std_logic_vector(11 downto 0);
        result_ch1_o         : out std_logic_vector(11 downto 0);
        result_ch2_o         : out std_logic_vector(11 downto 0);
        result_ch3_o         : out std_logic_vector(11 downto 0);
        result_ch4_o         : out std_logic_vector(11 downto 0);
        result_ch5_o         : out std_logic_vector(11 downto 0);
        result_ch6_o         : out std_logic_vector(11 downto 0);
        result_ch7_o         : out std_logic_vector(11 downto 0);
        result_ch8_o         : out std_logic_vector(11 downto 0);
        result_ch9_o         : out std_logic_vector(11 downto 0);
        sck_o                : out std_logic;
        sdo_o                : out std_logic
        );
end component;
-- ADC_SCALING   -   Microsemi:SolutionCore:ADC_SCALING:4.2.0
component ADC_SCALING
    generic( 
        g_ADC_RESULTS_WIDTH : integer := 12 ;
        g_DEBUG             : integer := 0 ;
        g_NO_MCYCLE_PATH    : integer := 2 ;
        g_SIGNED            : integer := 0 
        );
    -- Port list
    port(
        -- Inputs
        adc_result_ch0_i     : in  std_logic_vector(11 downto 0);
        adc_result_ch1_i     : in  std_logic_vector(11 downto 0);
        adc_results_rdy_i    : in  std_logic;
        adc_scale_val_i      : in  std_logic_vector(17 downto 0);
        fault_threshold_i    : in  std_logic_vector(17 downto 0);
        reset_i              : in  std_logic;
        sys_clk_i            : in  std_logic;
        -- Outputs
        calib_done_o         : out std_logic;
        done_o               : out std_logic;
        ia_adc_o             : out std_logic_vector(17 downto 0);
        ib_adc_o             : out std_logic_vector(17 downto 0);
        over_current_fault_o : out std_logic
        );
end component;
-- apb3_if
-- using entity instantiation for component apb3_if
-- FOC_TRANSFORMS   -   Microsemi:SolutionCore:FOC_TRANSFORMS:4.1.1
component FOC_TRANSFORMS
    generic( 
        g_NO_MCYCLE_PATH : integer := 2 
        );
    -- Port list
    port(
        -- Inputs
        ia_i            : in  std_logic_vector(17 downto 0);
        ialpha_i        : in  std_logic_vector(17 downto 0);
        ib_i            : in  std_logic_vector(17 downto 0);
        ibeta_i         : in  std_logic_vector(17 downto 0);
        reset_i         : in  std_logic;
        start_clarke_i  : in  std_logic;
        start_iclarke_i : in  std_logic;
        start_ipark_i   : in  std_logic;
        start_park_i    : in  std_logic;
        sys_clk_i       : in  std_logic;
        theta_i         : in  std_logic_vector(17 downto 0);
        valpha_i        : in  std_logic_vector(17 downto 0);
        vbeta_i         : in  std_logic_vector(17 downto 0);
        vd_i            : in  std_logic_vector(17 downto 0);
        vq_i            : in  std_logic_vector(17 downto 0);
        -- Outputs
        clarke_done_o   : out std_logic;
        ialpha_o        : out std_logic_vector(17 downto 0);
        ibeta_o         : out std_logic_vector(17 downto 0);
        iclarke_done_o  : out std_logic;
        id_o            : out std_logic_vector(17 downto 0);
        ipark_done_o    : out std_logic;
        iq_o            : out std_logic_vector(17 downto 0);
        park_done_o     : out std_logic;
        va_o            : out std_logic_vector(17 downto 0);
        valpha_o        : out std_logic_vector(17 downto 0);
        vb_o            : out std_logic_vector(17 downto 0);
        vbeta_o         : out std_logic_vector(17 downto 0);
        vc_o            : out std_logic_vector(17 downto 0)
        );
end component;
-- OLMNG   -   Microsemi:SolutionCore:OLMNG:4.1.1
component OLMNG
    generic( 
        g_NO_MCYCLE_PATH : integer := 2 
        );
    -- Port list
    port(
        -- Inputs
        cl_status_i        : in  std_logic;
        clear_buffer_i     : in  std_logic;
        direction_config_i : in  std_logic;
        dv_i               : in  std_logic_vector(17 downto 0);
        iq_ref_in_i        : in  std_logic_vector(17 downto 0);
        reset_i            : in  std_logic;
        speed_ref_i        : in  std_logic_vector(17 downto 0);
        start_i            : in  std_logic;
        sys_clk_i          : in  std_logic;
        theta_cl_i         : in  std_logic_vector(17 downto 0);
        theta_factor_i     : in  std_logic_vector(17 downto 0);
        -- Outputs
        done_o             : out std_logic;
        init_iqpi_o        : out std_logic_vector(17 downto 0);
        init_speedpi_o     : out std_logic_vector(17 downto 0);
        theta_o            : out std_logic_vector(17 downto 0)
        );
end component;
-- PWM3PH   -   Microsemi:SolutionCore:PWM3PH:4.1.2
component PWM3PH
    -- Port list
    port(
        -- Inputs
        dead_time_i    : in  std_logic_vector(17 downto 0);
        delay_time_i   : in  std_logic_vector(17 downto 0);
        en_dual_trig_i : in  std_logic;
        en_pwm_i       : in  std_logic;
        pwm_period_i   : in  std_logic_vector(17 downto 0);
        reset_i        : in  std_logic;
        sys_clk_i      : in  std_logic;
        va_i           : in  std_logic_vector(17 downto 0);
        vb_i           : in  std_logic_vector(17 downto 0);
        vc_i           : in  std_logic_vector(17 downto 0);
        -- Outputs
        PWM_AH_o       : out std_logic;
        PWM_AL_o       : out std_logic;
        PWM_BH_o       : out std_logic;
        PWM_BL_o       : out std_logic;
        PWM_CH_o       : out std_logic;
        PWM_CL_o       : out std_logic;
        midmatch_o     : out std_logic
        );
end component;
-- PWM_SCALING   -   Microsemi:SolutionCore:PWM_SCALING:4.1.0
component PWM_SCALING
    generic( 
        g_NO_MCYCLE_PATH : integer := 2 
        );
    -- Port list
    port(
        -- Inputs
        pwm_gain_i   : in  std_logic_vector(17 downto 0);
        pwm_period_i : in  std_logic_vector(17 downto 0);
        reset_i      : in  std_logic;
        start_i      : in  std_logic;
        sys_clk_i    : in  std_logic;
        va_i         : in  std_logic_vector(17 downto 0);
        vb_i         : in  std_logic_vector(17 downto 0);
        vc_i         : in  std_logic_vector(17 downto 0);
        -- Outputs
        Va_o         : out std_logic_vector(17 downto 0);
        Vb_o         : out std_logic_vector(17 downto 0);
        Vc_o         : out std_logic_vector(17 downto 0);
        done_o       : out std_logic
        );
end component;
-- RATE_LIMITER   -   Microsemi:SolutionCore:RATE_LIMITER:4.1.0
component RATE_LIMITER
    -- Port list
    port(
        -- Inputs
        direction_i  : in  std_logic;
        rate_count_i : in  std_logic_vector(17 downto 0);
        reset_i      : in  std_logic;
        reset_rl_i   : in  std_logic;
        rl_in_i      : in  std_logic_vector(17 downto 0);
        slew_count_i : in  std_logic_vector(17 downto 0);
        soft_stop_i  : in  std_logic;
        start_i      : in  std_logic;
        sys_clk_i    : in  std_logic;
        -- Outputs
        rl_done_o    : out std_logic;
        rl_out_o     : out std_logic_vector(17 downto 0)
        );
end component;
-- RESOLVER_INTERFACE   -   Microsemi:SolutionCore:RESOLVER_INTERFACE:4.2.0
component RESOLVER_INTERFACE
    generic( 
        g_NO_MCYCLE_PATH : integer := 2 
        );
    -- Port list
    port(
        -- Inputs
        ac_filter_factor_i : in  std_logic_vector(3 downto 0);
        calib_angle_i      : in  std_logic;
        clear_buffer_i     : in  std_logic;
        cos_i              : in  std_logic_vector(17 downto 0);
        dc_filter_factor_i : in  std_logic_vector(3 downto 0);
        hf_sig_period_i    : in  std_logic_vector(17 downto 0);
        pll_pi_ki_i        : in  std_logic_vector(17 downto 0);
        pll_pi_kp_i        : in  std_logic_vector(17 downto 0);
        pp_ratio_i         : in  std_logic_vector(3 downto 0);
        reset_i            : in  std_logic;
        sin_i              : in  std_logic_vector(17 downto 0);
        sys_clk_i          : in  std_logic;
        theta_factor_i     : in  std_logic_vector(17 downto 0);
        -- Outputs
        hf_signal_o        : out std_logic;
        speed_o            : out std_logic_vector(17 downto 0);
        theta_o            : out std_logic_vector(17 downto 0)
        );
end component;
-- SEQ_CONTROLLER   -   Microsemi:SolutionCore:SEQ_CONTROLLER:4.1.1
component SEQ_CONTROLLER
    generic( 
        g_DEBUG : integer := 0 
        );
    -- Port list
    port(
        -- Inputs
        calib_done_i    : in  std_logic;
        config_reg_i    : in  std_logic_vector(3 downto 0);
        fault_clear_i   : in  std_logic;
        fault_i         : in  std_logic;
        foc_done_i      : in  std_logic;
        max_ar_i        : in  std_logic_vector(3 downto 0);
        pwm_midmatch_i  : in  std_logic;
        reset_i         : in  std_logic;
        speed_cl_i      : in  std_logic_vector(17 downto 0);
        speed_ref_i     : in  std_logic_vector(17 downto 0);
        start_motor_i   : in  std_logic;
        stop_motor_i    : in  std_logic;
        sys_clk_i       : in  std_logic;
        vq_i            : in  std_logic_vector(17 downto 0);
        -- Outputs
        adc_start_o     : out std_logic;
        cl_status_o     : out std_logic;
        en_idq_pi_o     : out std_logic;
        en_pwm_o        : out std_logic;
        motor_stopped_o : out std_logic;
        reset_rl_o      : out std_logic;
        sensor_reset_o  : out std_logic;
        soft_stop_o     : out std_logic;
        state_o         : out std_logic_vector(3 downto 0)
        );
end component;
-- SINC3_FILTER   -   Microsemi:SolutionCore:SINC3_FILTER:4.2.0
component SINC3_FILTER
    generic( 
        g_BIPOLAR           : integer := 0 ;
        g_DECIMATION_FACTOR : integer := 6 ;
        g_NEGATE_OUTPUT     : integer := 0 ;
        g_STD_IO_WIDTH      : integer := 18 
        );
    -- Port list
    port(
        -- Inputs
        clk_adc_i  : in  std_logic;
        data_adc_i : in  std_logic;
        hold_i     : in  std_logic;
        reset_i    : in  std_logic;
        -- Outputs
        clk_dec_o  : out std_logic;
        data_o     : out std_logic_vector(17 downto 0)
        );
end component;
-- SPEED_ID_IQ_PI   -   Microsemi:SolutionCore:SPEED_ID_IQ_PI:4.1.0
component SPEED_ID_IQ_PI
    generic( 
        g_NO_MCYCLE_PATH : integer := 2 
        );
    -- Port list
    port(
        -- Inputs
        clear_buffer_i       : in  std_logic;
        id_init_i            : in  std_logic_vector(17 downto 0);
        id_pi_act_input_i    : in  std_logic_vector(17 downto 0);
        id_pi_ki_i           : in  std_logic_vector(17 downto 0);
        id_pi_kp_i           : in  std_logic_vector(17 downto 0);
        id_pi_ref_input_i    : in  std_logic_vector(17 downto 0);
        id_pi_start_i        : in  std_logic;
        idq_en_i             : in  std_logic;
        idq_pi_ymax_i        : in  std_logic_vector(17 downto 0);
        idq_pi_ymin_i        : in  std_logic_vector(17 downto 0);
        iq_init_i            : in  std_logic_vector(17 downto 0);
        iq_pi_act_input_i    : in  std_logic_vector(17 downto 0);
        iq_pi_ki_i           : in  std_logic_vector(17 downto 0);
        iq_pi_kp_i           : in  std_logic_vector(17 downto 0);
        iq_pi_ref_input_i    : in  std_logic_vector(17 downto 0);
        iq_pi_start_i        : in  std_logic;
        reset_i              : in  std_logic;
        speed_en_i           : in  std_logic;
        speed_init_i         : in  std_logic_vector(17 downto 0);
        speed_pi_act_input_i : in  std_logic_vector(17 downto 0);
        speed_pi_ki_i        : in  std_logic_vector(17 downto 0);
        speed_pi_kp_i        : in  std_logic_vector(17 downto 0);
        speed_pi_ref_input_i : in  std_logic_vector(17 downto 0);
        speed_pi_start_i     : in  std_logic;
        speed_pi_ymax_i      : in  std_logic_vector(17 downto 0);
        speed_pi_ymin_i      : in  std_logic_vector(17 downto 0);
        sys_clk_i            : in  std_logic;
        -- Outputs
        id_pi_done_o         : out std_logic;
        id_pi_output_o       : out std_logic_vector(17 downto 0);
        iq_pi_done_o         : out std_logic;
        iq_pi_output_o       : out std_logic_vector(17 downto 0);
        speed_pi_done_o      : out std_logic;
        speed_pi_output_o    : out std_logic_vector(17 downto 0)
        );
end component;
-- SVM   -   Microsemi:SolutionCore:SVM:4.1.0
component SVM
    -- Port list
    port(
        -- Inputs
        reset_i   : in  std_logic;
        start_i   : in  std_logic;
        sys_clk_i : in  std_logic;
        va_i      : in  std_logic_vector(17 downto 0);
        vb_i      : in  std_logic_vector(17 downto 0);
        vc_i      : in  std_logic_vector(17 downto 0);
        -- Outputs
        done_o    : out std_logic;
        va3h_o    : out std_logic_vector(17 downto 0);
        vb3h_o    : out std_logic_vector(17 downto 0);
        vc3h_o    : out std_logic_vector(17 downto 0)
        );
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal adc_cs_o_0                         : std_logic;
signal adc_interface_795x_0_done_o        : std_logic;
signal adc_interface_795x_0_result_ch0_o  : std_logic_vector(11 downto 0);
signal adc_interface_795x_0_result_ch1_o  : std_logic_vector(11 downto 0);
signal adc_interface_795x_0_result_ch2_o  : std_logic_vector(11 downto 0);
signal adc_interface_795x_0_result_ch3_o  : std_logic_vector(11 downto 0);
signal ADC_SCALING_0_done_o               : std_logic;
signal ADC_SCALING_1_calib_done_o         : std_logic;
signal ADC_SCALING_1_ia_adc_o             : std_logic_vector(17 downto 0);
signal ADC_SCALING_1_ib_adc_o             : std_logic_vector(17 downto 0);
signal ADC_SCALING_1_over_current_fault_o : std_logic;
signal adc_sck_o_0                        : std_logic;
signal adc_sdo_o_0                        : std_logic;
signal apb3_if_0_ac_filter_factor_o       : std_logic_vector(3 downto 0);
signal apb3_if_0_adc_oc_thresh_o          : std_logic_vector(17 downto 0);
signal apb3_if_0_adc_scale_val_o          : std_logic_vector(17 downto 0);
signal apb3_if_0_auto_restart_no_o        : std_logic_vector(3 downto 0);
signal apb3_if_0_dc_filter_factor_o       : std_logic_vector(3 downto 0);
signal apb3_if_0_direction_config_o       : std_logic;
signal apb3_if_0_fault_clr_o              : std_logic;
signal apb3_if_0_hf_sig_period_o          : std_logic_vector(17 downto 0);
signal apb3_if_0_idq_pi_ki_o_0            : std_logic_vector(17 downto 0);
signal apb3_if_0_idq_pi_kp_o              : std_logic_vector(17 downto 0);
signal apb3_if_0_olmng_dv_o               : std_logic_vector(17 downto 0);
signal apb3_if_0_olmng_iq_ref_in_o        : std_logic_vector(17 downto 0);
signal apb3_if_0_olmng_theta_factor_o     : std_logic_vector(17 downto 0);
signal apb3_if_0_pll_pi_ki_o              : std_logic_vector(17 downto 0);
signal apb3_if_0_pll_pi_kp_o              : std_logic_vector(17 downto 0);
signal apb3_if_0_pp_ratio_o               : std_logic_vector(3 downto 0);
signal apb3_if_0_pwm_dead_time_val_o      : std_logic_vector(17 downto 0);
signal apb3_if_0_pwm_delay_time_val_o     : std_logic_vector(17 downto 0);
signal apb3_if_0_pwm_gain_val_o           : std_logic_vector(17 downto 0);
signal apb3_if_0_pwm_period_val_o         : std_logic_vector(17 downto 0);
signal apb3_if_0_rate_limit_rate_cnt_o    : std_logic_vector(17 downto 0);
signal apb3_if_0_rate_limit_ref_in_o      : std_logic_vector(17 downto 0);
signal apb3_if_0_rate_limit_slew_cnt_o    : std_logic_vector(17 downto 0);
signal apb3_if_0_seq_cntl_cl_omega_o      : std_logic_vector(17 downto 0);
signal apb3_if_0_seq_cntl_config_o        : std_logic_vector(3 downto 0);
signal apb3_if_0_speed_pi_ki_o            : std_logic_vector(17 downto 0);
signal apb3_if_0_speed_pi_kp_o            : std_logic_vector(17 downto 0);
signal apb3_if_0_start_motor_o            : std_logic;
signal apb3_if_0_stop_motor_o             : std_logic;
signal apb3_if_0_theta_factor_o           : std_logic_vector(17 downto 0);
signal BLDC_APB_IF_PRDATA                 : std_logic_vector(31 downto 0);
signal BLDC_APB_IF_PREADY                 : std_logic;
signal BLDC_APB_IF_PSLVERR                : std_logic;
signal FOC_TRANSFORMS_0_ialpha_o          : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_0_ibeta_o           : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_0_iclarke_done_o    : std_logic;
signal FOC_TRANSFORMS_0_id_o              : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_0_ipark_done_o      : std_logic;
signal FOC_TRANSFORMS_0_iq_o              : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_0_park_done_o       : std_logic;
signal FOC_TRANSFORMS_0_va_o              : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_0_valpha_o          : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_0_vb_o              : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_0_vbeta_o           : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_0_vc_o              : std_logic_vector(17 downto 0);
signal FOC_TRANSFORMS_1_clarke_done_o_0   : std_logic;
signal hf_signal_o_net_0                  : std_logic;
signal net_189                            : std_logic_vector(17 downto 0);
signal net_230                            : std_logic_vector(17 downto 0);
signal net_231                            : std_logic_vector(17 downto 0);
signal OLMNG_0_init_iqpi_o                : std_logic_vector(17 downto 0);
signal OLMNG_0_init_speedpi_o             : std_logic_vector(17 downto 0);
signal OLMNG_1_theta_o                    : std_logic_vector(17 downto 0);
signal PWM3PH_0_midmatch_o                : std_logic;
signal PWM_SCALING_0_Va_o                 : std_logic_vector(17 downto 0);
signal PWM_SCALING_0_Vb_o                 : std_logic_vector(17 downto 0);
signal PWM_SCALING_0_Vc_o                 : std_logic_vector(17 downto 0);
signal PWM_SCALING_1_done_o               : std_logic;
signal pwm_uh_0                           : std_logic;
signal pwm_vh_0                           : std_logic;
signal pwm_wh_0                           : std_logic;
signal pwm_wl_net_0                       : std_logic;
signal RATE_LIMITER_0_rl_done_o           : std_logic;
signal RATE_LIMITER_0_rl_out_o            : std_logic_vector(17 downto 0);
signal SEQ_CONTROLLER_0_adc_start_o       : std_logic;
signal SEQ_CONTROLLER_0_cl_status_o       : std_logic;
signal SEQ_CONTROLLER_0_en_idq_pi_o       : std_logic;
signal SEQ_CONTROLLER_0_motor_stopped_o   : std_logic;
signal SEQ_CONTROLLER_0_reset_rl_o        : std_logic;
signal SEQ_CONTROLLER_0_sensor_reset_o    : std_logic;
signal SEQ_CONTROLLER_0_soft_stop_o       : std_logic;
signal SEQ_CONTROLLER_1_state_o           : std_logic_vector(3 downto 0);
signal SINC3_FILTER_0_data_o              : std_logic_vector(17 downto 0);
signal SINC3_FILTER_2_data_o              : std_logic_vector(17 downto 0);
signal SPEED_ID_IQ_PI_1_id_pi_done_o      : std_logic;
signal SPEED_ID_IQ_PI_1_id_pi_output_o    : std_logic_vector(17 downto 0);
signal SPEED_ID_IQ_PI_1_iq_pi_done_o      : std_logic;
signal SPEED_ID_IQ_PI_1_iq_pi_output_o    : std_logic_vector(17 downto 0);
signal SVM_0_done_o                       : std_logic;
signal SVM_0_va3h_o                       : std_logic_vector(17 downto 0);
signal SVM_0_vb3h_o                       : std_logic_vector(17 downto 0);
signal SVM_0_vc3h_o                       : std_logic_vector(17 downto 0);
signal pwm_wl_net_1                       : std_logic;
signal pwm_uh_0_net_0                     : std_logic;
signal pwm_wl_net_2                       : std_logic;
signal pwm_vh_0_net_0                     : std_logic;
signal pwm_wl_net_3                       : std_logic;
signal pwm_wh_0_net_0                     : std_logic;
signal adc_sdo_o_0_net_0                  : std_logic;
signal adc_sck_o_0_net_0                  : std_logic;
signal adc_cs_o_0_net_0                   : std_logic;
signal hf_signal_o_net_1                  : std_logic;
signal BLDC_APB_IF_PREADY_net_0           : std_logic;
signal BLDC_APB_IF_PSLVERR_net_0          : std_logic;
signal BLDC_APB_IF_PRDATA_net_0           : std_logic_vector(31 downto 0);
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal channels_to_sample_i_const_net_0   : std_logic_vector(15 downto 0);
signal ealpha_i_const_net_0               : std_logic_vector(17 downto 0);
signal ebeta_i_const_net_0                : std_logic_vector(17 downto 0);
signal ealpha_filter_out_i_const_net_0    : std_logic_vector(17 downto 0);
signal ebeta_filter_out_i_const_net_0     : std_logic_vector(17 downto 0);
signal GND_net                            : std_logic;
signal id_init_i_const_net_0              : std_logic_vector(17 downto 0);
signal speed_pi_ymax_i_const_net_0        : std_logic_vector(17 downto 0);
signal speed_pi_ymin_i_const_net_0        : std_logic_vector(17 downto 0);
signal id_pi_ref_input_i_const_net_0      : std_logic_vector(17 downto 0);
signal idq_pi_ymax_i_const_net_0          : std_logic_vector(17 downto 0);
signal idq_pi_ymin_i_const_net_0          : std_logic_vector(17 downto 0);

begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
 channels_to_sample_i_const_net_0 <= B"0000000000000011";
 ealpha_i_const_net_0             <= B"000000000000000000";
 ebeta_i_const_net_0              <= B"000000000000000000";
 ealpha_filter_out_i_const_net_0  <= B"000000000000000000";
 ebeta_filter_out_i_const_net_0   <= B"000000000000000000";
 GND_net                          <= '0';
 id_init_i_const_net_0            <= B"000000000000000000";
 speed_pi_ymax_i_const_net_0      <= B"011111111111111111";
 speed_pi_ymin_i_const_net_0      <= B"100000000000000001";
 id_pi_ref_input_i_const_net_0    <= B"000000000000000000";
 idq_pi_ymax_i_const_net_0        <= B"010000000000000000";
 idq_pi_ymin_i_const_net_0        <= B"110000000000000000";
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
 pwm_wl_net_1              <= pwm_wl_net_0;
 pwm_wl                    <= pwm_wl_net_1;
 pwm_uh_0_net_0            <= pwm_uh_0;
 pwm_uh                    <= pwm_uh_0_net_0;
 pwm_wl_net_2              <= pwm_wl_net_0;
 pwm_ul                    <= pwm_wl_net_2;
 pwm_vh_0_net_0            <= pwm_vh_0;
 pwm_vh                    <= pwm_vh_0_net_0;
 pwm_wl_net_3              <= pwm_wl_net_0;
 pwm_vl                    <= pwm_wl_net_3;
 pwm_wh_0_net_0            <= pwm_wh_0;
 pwm_wh                    <= pwm_wh_0_net_0;
 adc_sdo_o_0_net_0         <= adc_sdo_o_0;
 adc_sdo_o                 <= adc_sdo_o_0_net_0;
 adc_sck_o_0_net_0         <= adc_sck_o_0;
 adc_sck_o                 <= adc_sck_o_0_net_0;
 adc_cs_o_0_net_0          <= adc_cs_o_0;
 adc_cs_o                  <= adc_cs_o_0_net_0;
 hf_signal_o_net_1         <= hf_signal_o_net_0;
 hf_signal_o               <= hf_signal_o_net_1;
 BLDC_APB_IF_PREADY_net_0  <= BLDC_APB_IF_PREADY;
 pready_o_0                <= BLDC_APB_IF_PREADY_net_0;
 BLDC_APB_IF_PSLVERR_net_0 <= BLDC_APB_IF_PSLVERR;
 pslverr_o_0               <= BLDC_APB_IF_PSLVERR_net_0;
 BLDC_APB_IF_PRDATA_net_0  <= BLDC_APB_IF_PRDATA;
 prdata_o_0(31 downto 0)   <= BLDC_APB_IF_PRDATA_net_0;
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- adc_interface_795x_0
adc_interface_795x_0 : adc_interface_795x
    port map( 
        -- Inputs
        reset_i              => reset_i,
        sys_clk_i            => sys_clk_i,
        start_i              => SEQ_CONTROLLER_0_adc_start_o,
        sdi_i                => adc_sdi_i,
        channels_to_sample_i => channels_to_sample_i_const_net_0,
        -- Outputs
        sdo_o                => adc_sdo_o_0,
        cs_o                 => adc_cs_o_0,
        sck_o                => adc_sck_o_0,
        done_o               => adc_interface_795x_0_done_o,
        result_ch0_o         => adc_interface_795x_0_result_ch0_o,
        result_ch1_o         => adc_interface_795x_0_result_ch1_o,
        result_ch2_o         => adc_interface_795x_0_result_ch2_o,
        result_ch3_o         => adc_interface_795x_0_result_ch3_o,
        result_ch4_o         => OPEN,
        result_ch5_o         => OPEN,
        result_ch6_o         => OPEN,
        result_ch7_o         => OPEN,
        result_ch8_o         => OPEN,
        result_ch9_o         => OPEN,
        result_ch10_o        => OPEN,
        result_ch11_o        => OPEN,
        result_ch12_o        => OPEN,
        result_ch13_o        => OPEN,
        result_ch14_o        => OPEN,
        result_ch15_o        => OPEN 
        );
-- ADC_SCALING_0   -   Microsemi:SolutionCore:ADC_SCALING:4.2.0
ADC_SCALING_0 : ADC_SCALING
    generic map( 
        g_ADC_RESULTS_WIDTH => ( 12 ),
        g_DEBUG             => ( 0 ),
        g_NO_MCYCLE_PATH    => ( 2 ),
        g_SIGNED            => ( 0 )
        )
    port map( 
        -- Inputs
        reset_i              => reset_i,
        sys_clk_i            => sys_clk_i,
        adc_results_rdy_i    => adc_interface_795x_0_done_o,
        adc_scale_val_i      => apb3_if_0_adc_scale_val_o,
        adc_result_ch0_i     => adc_interface_795x_0_result_ch0_o,
        adc_result_ch1_i     => adc_interface_795x_0_result_ch1_o,
        fault_threshold_i    => apb3_if_0_adc_oc_thresh_o,
        -- Outputs
        done_o               => ADC_SCALING_0_done_o,
        calib_done_o         => ADC_SCALING_1_calib_done_o,
        over_current_fault_o => ADC_SCALING_1_over_current_fault_o,
        ia_adc_o             => ADC_SCALING_1_ia_adc_o,
        ib_adc_o             => ADC_SCALING_1_ib_adc_o 
        );
-- apb3_if_0
apb3_if_0 : entity work.apb3_if
    generic map( 
        g_ADC_OUT_WIDTH      => ( 12 ),
        g_APB3_IF_DATA_WIDTH => ( 32 ),
        g_CONST_WIDTH        => ( 12 ),
        g_STD_IO_WIDTH       => ( 18 )
        )
    port map( 
        -- Inputs
        preset_i              => reset_i,
        pclk_i                => sys_clk_i,
        psel_i                => psel_i_0,
        pwrite_i              => pwrite_i_0,
        penable_i             => penable_i_0,
        paddr_i               => paddr_i_0,
        pwdata_i              => pwdata_i_0,
        ia_i                  => ADC_SCALING_1_ia_adc_o,
        ib_i                  => ADC_SCALING_1_ib_adc_o,
        ialpha_i              => FOC_TRANSFORMS_0_ialpha_o,
        ibeta_i               => FOC_TRANSFORMS_0_ibeta_o,
        id_i                  => FOC_TRANSFORMS_0_id_o,
        iq_i                  => FOC_TRANSFORMS_0_iq_o,
        valpha_i              => FOC_TRANSFORMS_0_valpha_o,
        vbeta_i               => FOC_TRANSFORMS_0_vbeta_o,
        rl_out_i              => RATE_LIMITER_0_rl_out_o,
        speed_pi_out_i        => net_189,
        id_pi_out_i           => SPEED_ID_IQ_PI_1_id_pi_output_o,
        iq_pi_out_i           => SPEED_ID_IQ_PI_1_iq_pi_output_o,
        ealpha_i              => ealpha_i_const_net_0,
        ebeta_i               => ebeta_i_const_net_0,
        ealpha_filter_out_i   => ealpha_filter_out_i_const_net_0,
        ebeta_filter_out_i    => ebeta_filter_out_i_const_net_0,
        pll_theta_i           => net_231,
        theta_i               => OLMNG_1_theta_o,
        omega_filter_out_i    => net_230,
        adc_ch0_val_i         => adc_interface_795x_0_result_ch0_o,
        adc_ch1_val_i         => adc_interface_795x_0_result_ch1_o,
        adc_ch2_val_i         => adc_interface_795x_0_result_ch2_o,
        adc_ch3_val_i         => adc_interface_795x_0_result_ch3_o,
        fsm_state_val_i       => SEQ_CONTROLLER_1_state_o,
        -- Outputs
        pready_o              => BLDC_APB_IF_PREADY,
        pslverr_o             => BLDC_APB_IF_PSLVERR,
        start_motor_o         => apb3_if_0_start_motor_o,
        stop_motor_o          => apb3_if_0_stop_motor_o,
        direction_config_o    => apb3_if_0_direction_config_o,
        fault_clr_o           => apb3_if_0_fault_clr_o,
        prdata_o              => BLDC_APB_IF_PRDATA,
        speed_pi_kp_o         => apb3_if_0_speed_pi_kp_o,
        speed_pi_ki_o         => apb3_if_0_speed_pi_ki_o,
        idq_pi_kp_o           => apb3_if_0_idq_pi_kp_o,
        idq_pi_ki_o           => apb3_if_0_idq_pi_ki_o_0,
        Ls_by_Ts_pu_o         => OPEN,
        Rs_pu_o               => OPEN,
        angle_kp_o            => OPEN,
        angle_ki_o            => OPEN,
        rate_limit_ref_in_o   => apb3_if_0_rate_limit_ref_in_o,
        rate_limit_slew_cnt_o => apb3_if_0_rate_limit_slew_cnt_o,
        rate_limit_rate_cnt_o => apb3_if_0_rate_limit_rate_cnt_o,
        olmng_theta_factor_o  => apb3_if_0_olmng_theta_factor_o,
        olmng_dv_o            => apb3_if_0_olmng_dv_o,
        olmng_iq_ref_in_o     => apb3_if_0_olmng_iq_ref_in_o,
        seq_cntl_cl_omega_o   => apb3_if_0_seq_cntl_cl_omega_o,
        adc_scale_val_o       => apb3_if_0_adc_scale_val_o,
        adc_oc_thresh_o       => apb3_if_0_adc_oc_thresh_o,
        pwm_period_val_o      => apb3_if_0_pwm_period_val_o,
        pwm_dead_time_val_o   => apb3_if_0_pwm_dead_time_val_o,
        pwm_delay_time_val_o  => apb3_if_0_pwm_delay_time_val_o,
        pwm_gain_val_o        => apb3_if_0_pwm_gain_val_o,
        pll_pi_kp_o           => apb3_if_0_pll_pi_kp_o,
        pll_pi_ki_o           => apb3_if_0_pll_pi_ki_o,
        theta_factor_o        => apb3_if_0_theta_factor_o,
        hf_sig_period_o       => apb3_if_0_hf_sig_period_o,
        dc_filter_factor_o    => apb3_if_0_dc_filter_factor_o,
        ac_filter_factor_o    => apb3_if_0_ac_filter_factor_o,
        pp_ratio_o            => apb3_if_0_pp_ratio_o,
        auto_restart_no_o     => apb3_if_0_auto_restart_no_o,
        filter_factor_bemf_o  => OPEN,
        filter_factor_omega_o => OPEN,
        seq_cntl_config_o     => apb3_if_0_seq_cntl_config_o 
        );
-- FOC_TRANSFORMS_0   -   Microsemi:SolutionCore:FOC_TRANSFORMS:4.1.1
FOC_TRANSFORMS_0 : FOC_TRANSFORMS
    generic map( 
        g_NO_MCYCLE_PATH => ( 2 )
        )
    port map( 
        -- Inputs
        reset_i         => reset_i,
        sys_clk_i       => sys_clk_i,
        start_clarke_i  => ADC_SCALING_0_done_o,
        start_park_i    => FOC_TRANSFORMS_1_clarke_done_o_0,
        start_ipark_i   => SPEED_ID_IQ_PI_1_id_pi_done_o,
        start_iclarke_i => FOC_TRANSFORMS_0_ipark_done_o,
        ia_i            => ADC_SCALING_1_ia_adc_o,
        ib_i            => ADC_SCALING_1_ib_adc_o,
        ialpha_i        => FOC_TRANSFORMS_0_ialpha_o,
        ibeta_i         => FOC_TRANSFORMS_0_ibeta_o,
        vd_i            => SPEED_ID_IQ_PI_1_id_pi_output_o,
        vq_i            => SPEED_ID_IQ_PI_1_iq_pi_output_o,
        valpha_i        => FOC_TRANSFORMS_0_valpha_o,
        vbeta_i         => FOC_TRANSFORMS_0_vbeta_o,
        theta_i         => OLMNG_1_theta_o,
        -- Outputs
        clarke_done_o   => FOC_TRANSFORMS_1_clarke_done_o_0,
        park_done_o     => FOC_TRANSFORMS_0_park_done_o,
        ipark_done_o    => FOC_TRANSFORMS_0_ipark_done_o,
        iclarke_done_o  => FOC_TRANSFORMS_0_iclarke_done_o,
        ialpha_o        => FOC_TRANSFORMS_0_ialpha_o,
        ibeta_o         => FOC_TRANSFORMS_0_ibeta_o,
        id_o            => FOC_TRANSFORMS_0_id_o,
        iq_o            => FOC_TRANSFORMS_0_iq_o,
        valpha_o        => FOC_TRANSFORMS_0_valpha_o,
        vbeta_o         => FOC_TRANSFORMS_0_vbeta_o,
        va_o            => FOC_TRANSFORMS_0_va_o,
        vb_o            => FOC_TRANSFORMS_0_vb_o,
        vc_o            => FOC_TRANSFORMS_0_vc_o 
        );
-- OLMNG_0   -   Microsemi:SolutionCore:OLMNG:4.1.1
OLMNG_0 : OLMNG
    generic map( 
        g_NO_MCYCLE_PATH => ( 2 )
        )
    port map( 
        -- Inputs
        reset_i            => reset_i,
        sys_clk_i          => sys_clk_i,
        start_i            => RATE_LIMITER_0_rl_done_o,
        clear_buffer_i     => SEQ_CONTROLLER_0_motor_stopped_o,
        direction_config_i => apb3_if_0_direction_config_o,
        cl_status_i        => SEQ_CONTROLLER_0_cl_status_o,
        theta_factor_i     => apb3_if_0_olmng_theta_factor_o,
        speed_ref_i        => RATE_LIMITER_0_rl_out_o,
        dv_i               => apb3_if_0_olmng_dv_o,
        theta_cl_i         => net_231,
        iq_ref_in_i        => apb3_if_0_olmng_iq_ref_in_o,
        -- Outputs
        done_o             => OPEN,
        theta_o            => OLMNG_1_theta_o,
        init_speedpi_o     => OLMNG_0_init_speedpi_o,
        init_iqpi_o        => OLMNG_0_init_iqpi_o 
        );
-- PWM3PH_0   -   Microsemi:SolutionCore:PWM3PH:4.1.2
PWM3PH_0 : PWM3PH
    port map( 
        -- Inputs
        reset_i        => reset_i,
        sys_clk_i      => sys_clk_i,
        en_pwm_i       => pwm_wl_net_0,
        en_dual_trig_i => GND_net,
        va_i           => PWM_SCALING_0_Va_o,
        vb_i           => PWM_SCALING_0_Vb_o,
        vc_i           => PWM_SCALING_0_Vc_o,
        pwm_period_i   => apb3_if_0_pwm_period_val_o,
        dead_time_i    => apb3_if_0_pwm_dead_time_val_o,
        delay_time_i   => apb3_if_0_pwm_delay_time_val_o,
        -- Outputs
        midmatch_o     => PWM3PH_0_midmatch_o,
        PWM_AH_o       => pwm_uh_0,
        PWM_BH_o       => pwm_vh_0,
        PWM_CH_o       => pwm_wh_0,
        PWM_AL_o       => OPEN,
        PWM_BL_o       => OPEN,
        PWM_CL_o       => OPEN 
        );
-- PWM_SCALING_0   -   Microsemi:SolutionCore:PWM_SCALING:4.1.0
PWM_SCALING_0 : PWM_SCALING
    generic map( 
        g_NO_MCYCLE_PATH => ( 2 )
        )
    port map( 
        -- Inputs
        reset_i      => reset_i,
        sys_clk_i    => sys_clk_i,
        start_i      => SVM_0_done_o,
        va_i         => SVM_0_va3h_o,
        vb_i         => SVM_0_vb3h_o,
        vc_i         => SVM_0_vc3h_o,
        pwm_period_i => apb3_if_0_pwm_period_val_o,
        pwm_gain_i   => apb3_if_0_pwm_gain_val_o,
        -- Outputs
        done_o       => PWM_SCALING_1_done_o,
        Va_o         => PWM_SCALING_0_Va_o,
        Vb_o         => PWM_SCALING_0_Vb_o,
        Vc_o         => PWM_SCALING_0_Vc_o 
        );
-- RATE_LIMITER_0   -   Microsemi:SolutionCore:RATE_LIMITER:4.1.0
RATE_LIMITER_0 : RATE_LIMITER
    port map( 
        -- Inputs
        reset_i      => reset_i,
        sys_clk_i    => sys_clk_i,
        start_i      => ADC_SCALING_0_done_o,
        soft_stop_i  => SEQ_CONTROLLER_0_soft_stop_o,
        reset_rl_i   => SEQ_CONTROLLER_0_reset_rl_o,
        direction_i  => apb3_if_0_direction_config_o,
        slew_count_i => apb3_if_0_rate_limit_slew_cnt_o,
        rate_count_i => apb3_if_0_rate_limit_rate_cnt_o,
        rl_in_i      => apb3_if_0_rate_limit_ref_in_o,
        -- Outputs
        rl_done_o    => RATE_LIMITER_0_rl_done_o,
        rl_out_o     => RATE_LIMITER_0_rl_out_o 
        );
-- RESOLVER_INTERFACE_0   -   Microsemi:SolutionCore:RESOLVER_INTERFACE:4.2.0
RESOLVER_INTERFACE_0 : RESOLVER_INTERFACE
    generic map( 
        g_NO_MCYCLE_PATH => ( 2 )
        )
    port map( 
        -- Inputs
        reset_i            => reset_i,
        sys_clk_i          => sys_clk_i,
        clear_buffer_i     => SEQ_CONTROLLER_0_motor_stopped_o,
        calib_angle_i      => SEQ_CONTROLLER_0_sensor_reset_o,
        cos_i              => SINC3_FILTER_2_data_o,
        sin_i              => SINC3_FILTER_0_data_o,
        pll_pi_kp_i        => apb3_if_0_pll_pi_kp_o,
        pll_pi_ki_i        => apb3_if_0_pll_pi_ki_o,
        dc_filter_factor_i => apb3_if_0_dc_filter_factor_o,
        ac_filter_factor_i => apb3_if_0_ac_filter_factor_o,
        theta_factor_i     => apb3_if_0_theta_factor_o,
        hf_sig_period_i    => apb3_if_0_hf_sig_period_o,
        pp_ratio_i         => apb3_if_0_pp_ratio_o,
        -- Outputs
        hf_signal_o        => hf_signal_o_net_0,
        theta_o            => net_231,
        speed_o            => net_230 
        );
-- SEQ_CONTROLLER_0   -   Microsemi:SolutionCore:SEQ_CONTROLLER:4.1.1
SEQ_CONTROLLER_0 : SEQ_CONTROLLER
    generic map( 
        g_DEBUG => ( 0 )
        )
    port map( 
        -- Inputs
        reset_i         => reset_i,
        sys_clk_i       => sys_clk_i,
        fault_i         => ADC_SCALING_1_over_current_fault_o,
        start_motor_i   => apb3_if_0_start_motor_o,
        stop_motor_i    => apb3_if_0_stop_motor_o,
        fault_clear_i   => apb3_if_0_fault_clr_o,
        calib_done_i    => ADC_SCALING_1_calib_done_o,
        pwm_midmatch_i  => PWM3PH_0_midmatch_o,
        foc_done_i      => PWM_SCALING_1_done_o,
        speed_ref_i     => RATE_LIMITER_0_rl_out_o,
        speed_cl_i      => apb3_if_0_seq_cntl_cl_omega_o,
        vq_i            => SPEED_ID_IQ_PI_1_iq_pi_output_o,
        max_ar_i        => apb3_if_0_auto_restart_no_o,
        config_reg_i    => apb3_if_0_seq_cntl_config_o,
        -- Outputs
        adc_start_o     => SEQ_CONTROLLER_0_adc_start_o,
        cl_status_o     => SEQ_CONTROLLER_0_cl_status_o,
        en_idq_pi_o     => SEQ_CONTROLLER_0_en_idq_pi_o,
        en_pwm_o        => pwm_wl_net_0,
        motor_stopped_o => SEQ_CONTROLLER_0_motor_stopped_o,
        reset_rl_o      => SEQ_CONTROLLER_0_reset_rl_o,
        soft_stop_o     => SEQ_CONTROLLER_0_soft_stop_o,
        sensor_reset_o  => SEQ_CONTROLLER_0_sensor_reset_o,
        state_o         => SEQ_CONTROLLER_1_state_o 
        );
-- SINC3_FILTER_0   -   Microsemi:SolutionCore:SINC3_FILTER:4.2.0
SINC3_FILTER_0 : SINC3_FILTER
    generic map( 
        g_BIPOLAR           => ( 0 ),
        g_DECIMATION_FACTOR => ( 6 ),
        g_NEGATE_OUTPUT     => ( 0 ),
        g_STD_IO_WIDTH      => ( 18 )
        )
    port map( 
        -- Inputs
        reset_i    => reset_i,
        clk_adc_i  => clk_adc_i,
        data_adc_i => data_adc_SIN,
        hold_i     => GND_net,
        -- Outputs
        clk_dec_o  => OPEN,
        data_o     => SINC3_FILTER_0_data_o 
        );
-- SINC3_FILTER_2   -   Microsemi:SolutionCore:SINC3_FILTER:4.2.0
SINC3_FILTER_2 : SINC3_FILTER
    generic map( 
        g_BIPOLAR           => ( 0 ),
        g_DECIMATION_FACTOR => ( 6 ),
        g_NEGATE_OUTPUT     => ( 0 ),
        g_STD_IO_WIDTH      => ( 18 )
        )
    port map( 
        -- Inputs
        reset_i    => reset_i,
        clk_adc_i  => clk_adc_i,
        data_adc_i => data_adc_COS,
        hold_i     => GND_net,
        -- Outputs
        clk_dec_o  => OPEN,
        data_o     => SINC3_FILTER_2_data_o 
        );
-- SPEED_ID_IQ_PI_0   -   Microsemi:SolutionCore:SPEED_ID_IQ_PI:4.1.0
SPEED_ID_IQ_PI_0 : SPEED_ID_IQ_PI
    generic map( 
        g_NO_MCYCLE_PATH => ( 2 )
        )
    port map( 
        -- Inputs
        reset_i              => reset_i,
        sys_clk_i            => sys_clk_i,
        clear_buffer_i       => SEQ_CONTROLLER_0_motor_stopped_o,
        speed_en_i           => SEQ_CONTROLLER_0_cl_status_o,
        idq_en_i             => SEQ_CONTROLLER_0_en_idq_pi_o,
        speed_pi_start_i     => RATE_LIMITER_0_rl_done_o,
        id_pi_start_i        => SPEED_ID_IQ_PI_1_iq_pi_done_o,
        iq_pi_start_i        => FOC_TRANSFORMS_0_park_done_o,
        speed_init_i         => OLMNG_0_init_speedpi_o,
        id_init_i            => id_init_i_const_net_0,
        iq_init_i            => OLMNG_0_init_iqpi_o,
        speed_pi_ref_input_i => RATE_LIMITER_0_rl_out_o,
        speed_pi_act_input_i => net_230,
        speed_pi_kp_i        => apb3_if_0_speed_pi_kp_o,
        speed_pi_ki_i        => apb3_if_0_speed_pi_ki_o,
        speed_pi_ymax_i      => speed_pi_ymax_i_const_net_0,
        speed_pi_ymin_i      => speed_pi_ymin_i_const_net_0,
        id_pi_ref_input_i    => id_pi_ref_input_i_const_net_0,
        id_pi_act_input_i    => FOC_TRANSFORMS_0_id_o,
        id_pi_kp_i           => apb3_if_0_idq_pi_kp_o,
        id_pi_ki_i           => apb3_if_0_idq_pi_ki_o_0,
        idq_pi_ymax_i        => idq_pi_ymax_i_const_net_0,
        idq_pi_ymin_i        => idq_pi_ymin_i_const_net_0,
        iq_pi_ref_input_i    => net_189,
        iq_pi_act_input_i    => FOC_TRANSFORMS_0_iq_o,
        iq_pi_kp_i           => apb3_if_0_idq_pi_kp_o,
        iq_pi_ki_i           => apb3_if_0_idq_pi_ki_o_0,
        -- Outputs
        speed_pi_done_o      => OPEN,
        id_pi_done_o         => SPEED_ID_IQ_PI_1_id_pi_done_o,
        iq_pi_done_o         => SPEED_ID_IQ_PI_1_iq_pi_done_o,
        speed_pi_output_o    => net_189,
        id_pi_output_o       => SPEED_ID_IQ_PI_1_id_pi_output_o,
        iq_pi_output_o       => SPEED_ID_IQ_PI_1_iq_pi_output_o 
        );
-- SVM_0   -   Microsemi:SolutionCore:SVM:4.1.0
SVM_0 : SVM
    port map( 
        -- Inputs
        reset_i   => reset_i,
        sys_clk_i => sys_clk_i,
        start_i   => FOC_TRANSFORMS_0_iclarke_done_o,
        va_i      => FOC_TRANSFORMS_0_va_o,
        vb_i      => FOC_TRANSFORMS_0_vb_o,
        vc_i      => FOC_TRANSFORMS_0_vc_o,
        -- Outputs
        done_o    => SVM_0_done_o,
        va3h_o    => SVM_0_va3h_o,
        vb3h_o    => SVM_0_vb3h_o,
        vc3h_o    => SVM_0_vc3h_o 
        );

end RTL;
