# Synopsys Constraint Checker(syntax only), version map201609actrcp1, Build 005R, built Jan 25 2017
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

# Written on Wed Nov 29 15:53:55 2017


##### DESIGN INFO #######################################################

Top View:                "MC_System_top"
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

Start                                              Requested     Requested     Clock        Clock                   Clock
Clock                                              Frequency     Period        Type         Group                   Load 
-------------------------------------------------------------------------------------------------------------------------
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     3404 
MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_1     436  
System                                             100.0 MHz     10.000        system       system_clkgroup         0    
=========================================================================================================================
