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    Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)

    @W:MO171 : coreresetp.vhd(703) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(719) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(735) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(751) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(703) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(719) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(735) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(751) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(703) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(719) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(735) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(751) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(781) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(781) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.vhd(1331) | Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation
    @W:BN132 : coreresetp.vhd(936) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif3_spll_lock_q1,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.CONFIG2_DONE_q1
    @W:BN132 : coreresetp.vhd(922) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.CONFIG2_DONE_q1,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.CONFIG1_DONE_q1
    @W:BN132 : coreresetp.vhd(922) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.CONFIG2_DONE_clk_base,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif3_spll_lock_q2
    @W:BN132 : coreresetp.vhd(908) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.CONFIG1_DONE_clk_base,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif3_spll_lock_q2
    @W:BN132 : coreresetp.vhd(894) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1
    @W:BN132 : coreresetp.vhd(883) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1
    @W:BN132 : coreresetp.vhd(872) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.vhd(850) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.vhd(883) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_areset_n_rcosc
    @W:BN132 : coreresetp.vhd(894) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_areset_n_rcosc

    Available hyper_sources - for debug and ip models
    	None Found

    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[43:0] of view:PrimLib.dffre(prim) in hierarchy view:work.mas_adc_scl_work_mc_system_top_rtl_0layer0(mas_adc_scl) because there are no references to its outputs
    @N:FA239 : foc_transforms.vhd(1894) | ROM un5_s_theta_c[11:0] mapped in logic.
    @N:FA239 : foc_transforms.vhd(1894) | ROM un5_s_theta_c[11:0] mapped in logic.
    @N:MO106 : foc_transforms.vhd(1894) | Found ROM, 'un5_s_theta_c[11:0]', 16 words by 12 bits
    @N:FA239 : coreapb3.vhd(648) | ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
    @N:FA239 : coreapb3.vhd(648) | ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
    @N:MO106 : coreapb3.vhd(648) | Found ROM, 'CoreAPB3_0.iPSELS_raw_5[1:0]', 16 words by 2 bits
    @N:BN362 : sinc3_filter.v(119) | Removing sequential instance sinc3_filter_0.s_dec_count[5:0] of view:PrimLib.dffr(prim) in hierarchy view:work.Bldc_Axis(rtl) because there are no references to its outputs
    @N:BN362 : sinc3_filter.v(119) | Removing sequential instance sinc3_filter_0.s_clk_dec of view:PrimLib.dffr(prim) in hierarchy view:work.Bldc_Axis(rtl) because there are no references to its outputs

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 146MB)

    @N: : sinc3_filter.v(90) | Found counter in view:work.Bldc_Axis(rtl) inst sinc3_filter_0.s_acc1[23:0]
    @N: : sinc3_filter.v(119) | Found counter in view:work.Bldc_Axis(rtl) inst sinc3_filter_1.s_dec_count[5:0]
    @N: : sinc3_filter.v(90) | Found counter in view:work.Bldc_Axis(rtl) inst sinc3_filter_1.s_acc1[23:0]
    @N: : pwm3ph.vhd(138) | Found updn counter in view:work.Bldc_Axis(rtl) inst PWM3PH_0.s_pwm_counter[17:0]
    @N: : pwm3ph.vhd(138) | Found counter in view:work.Bldc_Axis(rtl) inst PWM3PH_0.s_delay_counter[17:0]
    @N:BN362 : apb3_if.vhd(556) | Removing sequential instance apb3_if_0.pwm_gain_val_o[0] of view:PrimLib.dffr(prim) in hierarchy view:work.Bldc_Axis(rtl) because there are no references to its outputs
    @N:MF179 :  | Found 18 bit by 18 bit '==' comparator, 'PWM3PH_0.PWM_MIDMATCH_GEN_PROC\.op_eq\.un6_en_pwm_i'
    Encoding state machine present_state[0:4] (view:work.adc_interface_6_16_12(adc_interface))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    @N: : adc_interface.vhd(492) | Found counter in view:work.adc_interface_6_16_12(adc_interface) inst s_r_sck_count[4:0]
    @N: : adc_interface.vhd(440) | Found counter in view:work.adc_interface_6_16_12(adc_interface) inst s_r_clock_count[7:0]
    Encoding state machine s_state[0:3] (view:work.ADC_SCALING_0_12_18_32_2(adc_scaling))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    @N:MO225 : adc_scaling.vhd(225) | No possible illegal states for state machine s_state[0:3],safe FSM implementation is disabled
    @N: : adc_scaling.vhd(200) | Found counter in view:work.ADC_SCALING_0_12_18_32_2(adc_scaling) inst s_calib_cnt[13:0]
    @N:FX404 : adc_scaling.vhd(188) | Found addmux in view:work.ADC_SCALING_0_12_18_32_2(adc_scaling) inst inf_abs1[17:0] from inf_abs1_a_1[17:0]
    @N:FX404 : adc_scaling.vhd(187) | Found addmux in view:work.ADC_SCALING_0_12_18_32_2(adc_scaling) inst inf_abs0[17:0] from inf_abs0_a_0[17:0]
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[0] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[1] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[2] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[3] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[4] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[5] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[6] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[7] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[26] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[27] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[28] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[29] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[30] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[31] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[32] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[33] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[34] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:BN362 : adc_scaling.vhd(508) | Removing sequential instance product_o[35] of view:PrimLib.dffr(prim) in hierarchy view:VhdlGenLib.syn_mac(preserved) because there are no references to its outputs
    @N:FX404 : foc_transforms.vhd(1866) | Found addmux in view:work.cordic_rot_foc_18_15(cordic_rot_foc) inst FSM_CORDIC_ROT_PROC\.s_yi_rot_7[17:0] from un1_s_yi_rot[17:0]
    @N:FX404 : foc_transforms.vhd(1866) | Found addmux in view:work.cordic_rot_foc_18_15(cordic_rot_foc) inst FSM_CORDIC_ROT_PROC\.s_xi_rot_7[17:0] from un1_s_xi_rot[17:0]
    @N:FX404 : foc_transforms.vhd(1866) | Found addmux in view:work.cordic_rot_foc_18_15(cordic_rot_foc) inst FSM_CORDIC_ROT_PROC\.s_theta_c_9[17:0] from un1_s_theta_c_4[17:0]
    Encoding state machine s_state[0:2] (view:work.cordic_scale_18_44(cordic_scale))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine s_state[0:2] (view:work.OLMNG_18_2(olmng))
    original code -> new code
       00 -> 00
       10 -> 01
       11 -> 10
    @N:FX404 : olmng.vhd(289) | Found addmux in view:work.OLMNG_18_2(olmng) inst init_speedpi_o_5[18:1] from un4_init_speedpi_o[17:0]
    Encoding state machine s_state[0:4] (view:work.PWM_SCALING_18_2(pwm_scaling))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    Encoding state machine s_ramp_present_state[0:2] (view:work.RATE_LIMITER_18(rate_limiter))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    @N: : rate_limiter.vhd(154) | Found counter in view:work.RATE_LIMITER_18(rate_limiter) inst s_count[18:0]
    @N:FX404 : rate_limiter.vhd(132) | Found addmux in view:work.RATE_LIMITER_18(rate_limiter) inst s_rl_in[18:1] from un7_s_rl_in[17:0]
    Encoding state machine s_state[0:8] (view:work.SEQ_CONTROLLER_0_18(seq_controller))
    original code -> new code
       000000001 -> 000000001
       000000010 -> 000000010
       000000100 -> 000000100
       000001000 -> 000001000
       000010000 -> 000010000
       000100000 -> 000100000
       001000000 -> 001000000
       010000000 -> 010000000
       100000000 -> 100000000
    @N: : seq_controller.vhd(294) | Found counter in view:work.SEQ_CONTROLLER_0_18(seq_controller) inst s_adctrig_count[12:0]
    @N: : seq_controller.vhd(510) | Found counter in view:work.SEQ_CONTROLLER_0_18(seq_controller) inst s_sensor_calib_count[13:0]
    @N:FX404 : seq_controller.vhd(197) | Found addmux in view:work.SEQ_CONTROLLER_0_18(seq_controller) inst inf_abs1[17:0] from inf_abs1_a_1[17:0]
    @N:FX404 : seq_controller.vhd(195) | Found addmux in view:work.SEQ_CONTROLLER_0_18(seq_controller) inst inf_abs0[17:0] from inf_abs0_a_0[17:0]
    Encoding state machine s_state[0:4] (view:work.pi_controller_spi_18_44_2(pi_controller_spi))
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    @N:FX404 :  | Found addmux in view:work.pi_controller_spi_18_44_2(pi_controller_spi) inst s_piout[34:0] from un5_s_piout\.un5_s_piout_1[44:10]
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[18] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[19] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[20] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[21] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[22] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[23] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[24] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[25] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[26] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[27] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[28] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[29] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[30] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[31] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[32] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[33] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    @N:BN362 : speed_id_iq_pi.vhd(1011) | Removing sequential instance output_y_o_1[34] of view:PrimLib.dffr(prim) in hierarchy view:work.pi_controller_spi_18_44_2(pi_controller_spi) because there are no references to its outputs
    Encoding state machine s_state[0:2] (view:work.SVM_18(svm))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine sm0_state[0:6] (view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.INIT_DONE_int in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_state[0] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs

    Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 175MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 178MB)

    @N:BN114 : mc_system_sb.vhd(681) | Removing instance MC_System_0.MC_System_sb_0.SYSRESET_POR of black_box view:ACG4.SYSRESET(PRIM) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1519) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.ddr_settled in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(577) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_q1 in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(565) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.RESET_N_M2F_q1 in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(553) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.POWER_ON_RESET_N_q1 in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.ddr_settled_q1 in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(936) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif3_spll_lock_q2 in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(908) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.CONFIG1_DONE_q1 in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(861) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(608) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.MSS_HPMS_READY_int in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(850) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_areset_n_rcosc in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(770) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_areset_n_q1 in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(770) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_areset_n_clk_base in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(577) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(565) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.RESET_N_M2F_clk_base in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(553) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.POWER_ON_RESET_N_clk_base in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.ddr_settled_clk_base in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_state[1] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_state[2] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_state[3] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_state[4] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_state[5] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm0_state[6] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(593) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.mss_ready_state in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(593) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.mss_ready_select in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 168MB peak: 182MB)

    @N:FX404 : rate_limiter.vhd(161) | Found addmux in view:work.MC_System_top(rtl) inst Bldc_Axis_0.RATE_LIMITER_0.s_ramp_out_8_0[17:0] from Bldc_Axis_0.RATE_LIMITER_0.un1_s_ref_val_buf[17:0]
    @N:FX404 : foc_transforms.vhd(1932) | Found addmux in view:work.MC_System_top(rtl) inst Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.OUTPUT_PROC\.x_o_5_1[17:0] from Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.OUTPUT_PROC\.y_o_4[17:0]

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 170MB peak: 182MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 186MB peak: 187MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 185MB peak: 187MB)

    Finished preparing to map (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 186MB peak: 187MB)

    Finished technology mapping (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 245MB peak: 249MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:12s		    -3.38ns		3495 /      2398
       2		0h:00m:12s		    -3.26ns		3276 /      2398
    @N:FX271 : speed_id_iq_pi.vhd(629) | Instance "Bldc_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.s_pi_sel[1]" with 64 loads replicated 1 times to improve timing
    @N:FX271 : speed_id_iq_pi.vhd(629) | Instance "Bldc_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.s_pi_sel[0]" with 101 loads replicated 3 times to improve timing
    Timing driven replication report
    Added 4 Registers via timing driven replication
    Added 4 LUTs via timing driven replication

    @N:FX271 : seq_controller.vhd(294) | Instance "Bldc_Axis_0.SEQ_CONTROLLER_0.s_state[2]" with 29 loads replicated 1 times to improve timing
    @N:FX271 : speed_id_iq_pi.vhd(747) | Instance "Bldc_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.iq_pi_output_y_o[17]" with 7 loads replicated 1 times to improve timing
    @N:FX271 : foc_transforms.vhd(1856) | Instance "Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[0]" with 60 loads replicated 3 times to improve timing
    Timing driven replication report
    Added 5 Registers via timing driven replication
    Added 4 LUTs via timing driven replication

       3		0h:00m:14s		    -1.31ns		3297 /      2407

       4		0h:00m:14s		    -1.31ns		3297 /      2407
    @N:FP130 :  | Promoting Net N_2 on CLKINT  I_5
    @N:FP130 :  | Promoting Net MC_System_0_FIC_0_LOCK on CLKINT  I_1019

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 252MB peak: 254MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 254MB peak: 254MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    2 non-gated/non-generated clock tree(s) driving 2418 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =============================================================== Non-Gated/Non-Generated Clocks ===============================================================
    Clock Tree ID     Driving Element                               Drive Element Type     Fanout     Sample Instance
    --------------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        MC_System_0.MC_System_sb_0.CCC_0.GL0_INST     CLKINT                 1988       MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST
    ClockId0002        MC_System_0.MC_System_sb_0.CCC_0.GL2_INST     CLKINT                 430        Bldc_Axis_0.sinc3_filter_0.s_diff3[15]
    ==============================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Start Writing Netlists (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 205MB peak: 255MB)

    Writing Analyst data base E:\Webrelease\RS\SK1ABLRS10_5_1\synthesis\synwork\MC_System_top_1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 241MB peak: 255MB)

    Writing Verilog Simulation files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 238MB peak: 255MB)

    Start final timing analysis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 238MB peak: 255MB)

    @W:MT246 : mc_system_sb_ccc_0_fccc.vhd(115) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : bldc_axis.vhd(812) | Blackbox RESOLVER_INTERFACE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock MC_System_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.FABOSC_0.RCOSC_25_50MHZ_CCC"

    @W:MT420 :  | Found inferred clock MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.CCC_0.GL2_net"

    @W:MT420 :  | Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.CCC_0.GL0_net"

    @S |##### START OF TIMING REPORT #####[
    # Timing Report written on Thu Aug 25 10:43:36 2016
    #

    Top view:               MC_System_top
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):    E:\Webrelease\RS\SK1ABLRS10_5_1\constraint\MS_MC_System_top_compile.sdc

    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.064

                                                                    Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                                                  Frequency     Frequency     Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     99.4 MHz      10.000        10.064        -0.064     inferred     Inferred_clkgroup_0
    MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock                  100.0 MHz     191.7 MHz     10.000        5.217         2.391      inferred     Inferred_clkgroup_2
    MC_System_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     NA            10.000        NA            NA         inferred     Inferred_clkgroup_1
    System                                                          100.0 MHz     434.2 MHz     10.000        2.303         7.697      system       system_clkgroup
    ===================================================================================================================================================================
    @N:MT582 :  | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
    @W:MT548 : ms_mc_system_top_compile.sdc(3) | Source for clock MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT not found in netlist. Run the constraint checker to verify if constraints are applied correctly.
    @W:MT548 : ms_mc_system_top_compile.sdc(6) | Source for clock MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.
    @W:MT548 : ms_mc_system_top_compile.sdc(11) | Source for clock MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.

    Clock Relationships
    *******************

    Clocks                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                        Ending                                          |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                          System                                          |  10.000      7.697   |  No paths    -      |  No paths    -      |  No paths    -
    System                                          MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      2.646   |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  System                                          |  10.000      8.926   |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      -0.064  |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  System                                          |  10.000      8.934   |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  |  10.000      7.486   |  10.000      7.372  |  No paths    -      |  5.000       2.391
    =======================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                     Starting                                                                                                                 Arrival
    Instance                                                         Reference                                          Type        Pin                Net                                    Time        Slack
                                                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[10]     MC_System_0_AMBA_SLAVE_0_PADDR[10]     3.357       -0.064
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[9]      MC_System_0_AMBA_SLAVE_0_PADDR[9]      3.175       0.059
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[8]      MC_System_0_AMBA_SLAVE_0_PADDR[8]      3.354       0.113
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[11]     MC_System_0_AMBA_SLAVE_0_PADDR[11]     3.057       0.133
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[7]      MC_System_0_AMBA_SLAVE_0_PADDR[7]      3.055       0.188
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[2]      MC_System_0_AMBA_SLAVE_0_PADDR[2]      3.040       0.259
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[1]      MC_System_0_AMBA_SLAVE_0_PADDR[1]      3.058       0.269
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[0]      MC_System_0_AMBA_SLAVE_0_PADDR[0]      3.112       0.290
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[6]      MC_System_0_AMBA_SLAVE_0_PADDR[6]      3.185       0.317
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[3]      MC_System_0_AMBA_SLAVE_0_PADDR[3]      3.040       0.333
    ============================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                     Starting                                                                                                                                  Required
    Instance                                                         Reference                                          Type        Pin                 Net                                                    Time         Slack
                                                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        -0.064
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[2]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]      9.706        0.075
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        0.178
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[9]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]      9.594        0.182
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[11]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]     9.650        0.218
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        0.242
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[6]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]      9.651        0.362
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        0.378
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[13]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]     9.640        0.387
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[16]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]     9.647        0.423
    ==============================================================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.316
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.684

        - Propagation time:                      9.748
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.064

        Number of logic level(s):                6
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[1]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                  Pin                Pin               Arrival     No. of
    Name                                                                Type        Name               Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -
    MC_System_0_AMBA_SLAVE_0_PADDR[10]                                  Net         -                  -       0.985     -           6
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5_sx_1                            CFG4        C                  In      -         4.342       -
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5_sx_1                            CFG4        Y                  Out     0.177     4.518       -
    prdata_m1_e_5_sx_1                                                  Net         -                  -       0.483     -           1
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5                                 CFG4        D                  In      -         5.001       -
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5                                 CFG4        Y                  Out     0.284     5.285       -
    prdata_N_3_mux_0                                                    Net         -                  -       0.893     -           28
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_10_0_a2[9]                  CFG3        C                  In      -         6.178       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_10_0_a2[9]                  CFG3        Y                  Out     0.182     6.361       -
    N_377                                                               Net         -                  -       0.722     -           9
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_4[1]                           CFG4        D                  In      -         7.082       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_4[1]                           CFG4        Y                  Out     0.250     7.332       -
    prdata_o_1_0_0_4[1]                                                 Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[1]     CFG4        C                  In      -         7.816       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[1]     CFG4        Y                  Out     0.194     8.010       -
    PRDATA_1[1]                                                         Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]       CFG4        D                  In      -         8.493       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]       CFG4        Y                  Out     0.284     8.777       -
    MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]                   Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_RDATA[1]     In      -         9.748       -
    ===========================================================================================================================================
    Total path delay (propagation time + setup) of 10.064 is 5.044(50.1%) logic and 5.021(49.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      10.000
        - Setup time:                            0.316
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.684

        - Propagation time:                      9.625
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 0.059

        Number of logic level(s):                6
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[9]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[1]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                  Pin                Pin               Arrival     No. of
    Name                                                                Type        Name               Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_ADDR[9]      Out     3.175     3.175       -
    MC_System_0_AMBA_SLAVE_0_PADDR[9]                                   Net         -                  -       0.985     -           6
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5_sx_1                            CFG4        D                  In      -         4.160       -
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5_sx_1                            CFG4        Y                  Out     0.236     4.396       -
    prdata_m1_e_5_sx_1                                                  Net         -                  -       0.483     -           1
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5                                 CFG4        D                  In      -         4.879       -
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5                                 CFG4        Y                  Out     0.284     5.163       -
    prdata_N_3_mux_0                                                    Net         -                  -       0.893     -           28
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_10_0_a2[9]                  CFG3        C                  In      -         6.056       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_10_0_a2[9]                  CFG3        Y                  Out     0.182     6.238       -
    N_377                                                               Net         -                  -       0.722     -           9
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_4[1]                           CFG4        D                  In      -         6.960       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_4[1]                           CFG4        Y                  Out     0.250     7.210       -
    prdata_o_1_0_0_4[1]                                                 Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[1]     CFG4        C                  In      -         7.693       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[1]     CFG4        Y                  Out     0.194     7.887       -
    PRDATA_1[1]                                                         Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]       CFG4        D                  In      -         8.370       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]       CFG4        Y                  Out     0.284     8.654       -
    MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]                   Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_RDATA[1]     In      -         9.625       -
    ===========================================================================================================================================
    Total path delay (propagation time + setup) of 9.941 is 4.921(49.5%) logic and 5.021(50.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      10.000
        - Setup time:                            0.294
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.706

        - Propagation time:                      9.620
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 0.086

        Number of logic level(s):                6
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                Pin                Pin               Arrival     No. of
    Name                                                              Type        Name               Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -
    MC_System_0_AMBA_SLAVE_0_PADDR[10]                                Net         -                  -       0.985     -           6
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5_sx_1                          CFG4        C                  In      -         4.342       -
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5_sx_1                          CFG4        Y                  Out     0.177     4.518       -
    prdata_m1_e_5_sx_1                                                Net         -                  -       0.483     -           1
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5                               CFG4        D                  In      -         5.001       -
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5                               CFG4        Y                  Out     0.284     5.285       -
    prdata_N_3_mux_0                                                  Net         -                  -       0.893     -           28
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_1_a2_2_o2_0[8]              CFG4        C                  In      -         6.178       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_1_a2_2_o2_0[8]              CFG4        Y                  Out     0.194     6.372       -
    N_3750                                                            Net         -                  -       0.749     -           11
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_1_a2_2_a2[8]                CFG3        C                  In      -         7.121       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_1_a2_2_a2[8]                CFG3        Y                  Out     0.177     7.298       -
    N_271                                                             Net         -                  -       0.548     -           2
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_6[2]                           CFG4        B                  In      -         7.846       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_6[2]                           CFG4        Y                  Out     0.143     7.989       -
    prdata_o_1_0_6[2]                                                 Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[2]     CFG4        C                  In      -         8.472       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[2]     CFG4        Y                  Out     0.177     8.649       -
    MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]                 Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_RDATA[2]     In      -         9.620       -
    =========================================================================================================================================
    Total path delay (propagation time + setup) of 9.914 is 4.802(48.4%) logic and 5.112(51.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      10.000
        - Setup time:                            0.316
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.684

        - Propagation time:                      9.571
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 0.113

        Number of logic level(s):                6
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[8]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[1]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                   Pin                Pin               Arrival     No. of
    Name                                                                 Type        Name               Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST         MSS_010     F_HM0_ADDR[8]      Out     3.354     3.354       -
    MC_System_0_AMBA_SLAVE_0_PADDR[8]                                    Net         -                  -       0.999     -           44
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_6_a2_0_a2_0_sx[7]              CFG3        C                  In      -         4.353       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_6_a2_0_a2_0_sx[7]              CFG3        Y                  Out     0.177     4.530       -
    prdata_o_1_0_a2_6_a2_0_a2_0_sx[7]                                    Net         -                  -       0.483     -           1
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_6_a2_0_a2_0_sx_RNI29JO3[7]     CFG4        D                  In      -         5.013       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_6_a2_0_a2_0_sx_RNI29JO3[7]     CFG4        Y                  Out     0.284     5.297       -
    N_374                                                                Net         -                  -       0.793     -           15
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_5[1]                         CFG4        D                  In      -         6.090       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_5[1]                         CFG4        Y                  Out     0.250     6.340       -
    N_998                                                                Net         -                  -       0.483     -           1
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_2[1]                            CFG4        D                  In      -         6.823       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_2[1]                            CFG4        Y                  Out     0.250     7.074       -
    prdata_o_1_0_0_2[1]                                                  Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[1]      CFG4        D                  In      -         7.557       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[1]      CFG4        Y                  Out     0.276     7.833       -
    PRDATA_1[1]                                                          Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]        CFG4        D                  In      -         8.316       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]        CFG4        Y                  Out     0.284     8.600       -
    MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]                    Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST         MSS_010     F_HM0_RDATA[1]     In      -         9.571       -
    ============================================================================================================================================
    Total path delay (propagation time + setup) of 9.887 is 5.191(52.5%) logic and 4.697(47.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      10.000
        - Setup time:                            0.316
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.684

        - Propagation time:                      9.551
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 0.133

        Number of logic level(s):                6
        Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[11]
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[1]
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                  Pin                Pin               Arrival     No. of
    Name                                                                Type        Name               Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_ADDR[11]     Out     3.057     3.057       -
    MC_System_0_AMBA_SLAVE_0_PADDR[11]                                  Net         -                  -       0.985     -           6
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5_0                               CFG2        B                  In      -         4.042       -
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5_0                               CFG2        Y                  Out     0.143     4.184       -
    prdata_m1_e_5_0                                                     Net         -                  -       0.722     -           9
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5                                 CFG4        C                  In      -         4.906       -
    Bldc_Axis_0.apb3_if_0.prdata_m1_e_5                                 CFG4        Y                  Out     0.182     5.088       -
    prdata_N_3_mux_0                                                    Net         -                  -       0.893     -           28
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_10_0_a2[9]                  CFG3        C                  In      -         5.981       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_10_0_a2[9]                  CFG3        Y                  Out     0.182     6.164       -
    N_377                                                               Net         -                  -       0.722     -           9
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_4[1]                           CFG4        D                  In      -         6.885       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_4[1]                           CFG4        Y                  Out     0.250     7.136       -
    prdata_o_1_0_0_4[1]                                                 Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[1]     CFG4        C                  In      -         7.619       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[1]     CFG4        Y                  Out     0.194     7.813       -
    PRDATA_1[1]                                                         Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]       CFG4        D                  In      -         8.296       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[1]       CFG4        Y                  Out     0.284     8.580       -
    MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]                   Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_RDATA[1]     In      -         9.551       -
    ===========================================================================================================================================
    Total path delay (propagation time + setup) of 9.867 is 4.608(46.7%) logic and 5.259(53.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                 Starting                                                                              Arrival
    Instance                                     Reference                                          Type     Pin     Net               Time        Slack
                                                 Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------
    Bldc_Axis_0.sinc3_filter_1.s_clk_dec         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_clk_dec         0.094       2.391
    Bldc_Axis_0.sinc3_filter_0.s_acc3[0]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[0]         0.094       2.442
    Bldc_Axis_0.sinc3_filter_1.s_acc3[0]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[0]         0.094       2.442
    Bldc_Axis_0.sinc3_filter_1.s_acc3[1]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[1]         0.094       2.501
    Bldc_Axis_0.sinc3_filter_0.s_acc3[1]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[1]         0.094       2.501
    Bldc_Axis_0.sinc3_filter_1.s_acc3[2]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[2]         0.094       2.515
    Bldc_Axis_0.sinc3_filter_0.s_acc3[2]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[2]         0.094       2.515
    Bldc_Axis_0.sinc3_filter_1.s_acc3[3]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[3]         0.094       2.529
    Bldc_Axis_0.sinc3_filter_0.s_acc3[3]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[3]         0.094       2.529
    Bldc_Axis_0.sinc3_filter_0.s_clk_dec_dly     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_clk_dec_dly     0.076       2.538
    ====================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                              Starting                                                                             Required
    Instance                                  Reference                                          Type     Pin     Net              Time         Slack
                                              Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------
    Bldc_Axis_0.sinc3_filter_0.s_diff1[0]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_1.s_diff1[0]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_1.s_diff1[1]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_0.s_diff1[1]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_1.s_diff1[2]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_0.s_diff1[2]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_1.s_diff1[3]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_0.s_diff1[3]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_1.s_diff1[4]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    Bldc_Axis_0.sinc3_filter_0.s_diff1[4]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      EN      s_clk_dec_re     4.707        2.391
    =================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.293
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.707

        - Propagation time:                      2.315
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 2.391

        Number of logic level(s):                1
        Starting point:                          Bldc_Axis_0.sinc3_filter_1.s_clk_dec / Q
        Ending point:                            Bldc_Axis_0.sinc3_filter_0.s_diff1[0] / EN
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock [falling] on pin CLK
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK

    Instance / Net                                       Pin      Pin               Arrival     No. of
    Name                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------
    Bldc_Axis_0.sinc3_filter_1.s_clk_dec        SLE      Q        Out     0.094     0.094       -
    s_clk_dec                                   Net      -        -       0.686     -           2
    Bldc_Axis_0.sinc3_filter_0.s_clk_dec_re     CFG2     A        In      -         0.780       -
    Bldc_Axis_0.sinc3_filter_0.s_clk_dec_re     CFG2     Y        Out     0.076     0.856       -
    s_clk_dec_re                                Net      -        -       1.459     -           276
    Bldc_Axis_0.sinc3_filter_0.s_diff1[0]       SLE      EN       In      -         2.315       -
    ======================================================================================================
    Total path delay (propagation time + setup) of 2.609 is 0.463(17.8%) logic and 2.145(82.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                  Starting                                                                                  Arrival
    Instance                                      Reference     Type                   Pin             Net                                  Time        Slack
                                                  Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.CCC_0.CCC_INST     System        CCC                    LOCK            LOCK                                 0.000       2.646
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     theta_o[7]      RESOLVER_INTERFACE_1_theta_o[7]      0.000       4.490
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     theta_o[3]      RESOLVER_INTERFACE_1_theta_o[3]      0.000       4.793
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     theta_o[6]      RESOLVER_INTERFACE_1_theta_o[6]      0.000       4.990
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     speed_o[17]     RESOLVER_INTERFACE_1_speed_o[17]     0.000       5.090
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     speed_o[7]      RESOLVER_INTERFACE_1_speed_o[7]      0.000       5.156
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     speed_o[11]     RESOLVER_INTERFACE_1_speed_o[11]     0.000       5.367
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     speed_o[1]      RESOLVER_INTERFACE_1_speed_o[1]      0.000       5.402
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     theta_o[1]      RESOLVER_INTERFACE_1_theta_o[1]      0.000       5.444
    Bldc_Axis_0.RESOLVER_INTERFACE_1              System        RESOLVER_INTERFACE     theta_o[5]      RESOLVER_INTERFACE_1_theta_o[5]      0.000       5.476
    =========================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                     Starting                                                                                             Required
    Instance                                                         Reference     Type        Pin                 Net                                                    Time         Slack
                                                                     Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        2.646
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        2.740
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[15]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[15]     9.695        2.768
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[12]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[12]     9.698        2.771
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[13]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]     9.640        3.141
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[16]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]     9.647        3.148
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        3.378
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[2]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]      9.706        3.473
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[8]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[8]      9.668        3.494
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[11]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]     9.650        3.515
    ========================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.517
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.483

        - Propagation time:                      6.837
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 2.646

        Number of logic level(s):                7
        Starting point:                          MC_System_0.MC_System_sb_0.CCC_0.CCC_INST / LOCK
        Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
        The start point is clocked by            System [rising]
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                    Pin                Pin               Arrival     No. of
    Name                                                                  Type        Name               Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                             CCC         LOCK               Out     0.000     0.000       -
    LOCK                                                                  Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                     CLKINT      A                  In      -         0.971       -
    MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                     CLKINT      Y                  Out     0.337     1.308       -
    MC_System_0_FIC_0_LOCK                                                Net         -                  -       0.995     -           2442
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_35[9]                         CFG4        C                  In      -         2.303       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_35[9]                         CFG4        Y                  Out     0.177     2.480       -
    N_1068                                                                Net         -                  -       0.548     -           2
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_35_RNI123O1[9]                CFG4        B                  In      -         3.028       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_35_RNI123O1[9]                CFG4        Y                  Out     0.143     3.171       -
    prdata_o_1_0_0_a2_35_RNI123O1[9]                                      Net         -                  -       0.622     -           4
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_8_7_sx_sx[3]                     CFG4        A                  In      -         3.793       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_8_7_sx_sx[3]                     CFG4        Y                  Out     0.067     3.860       -
    prdata_o_1_0_0_8_7_sx_sx[3]                                           Net         -                  -       0.483     -           1
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_8_2_RNIJ8OT4[3]                  CFG4        B                  In      -         4.343       -
    Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_8_2_RNIJ8OT4[3]                  CFG4        Y                  Out     0.143     4.486       -
    prdata_o_1_0_0_8_7_sx[3]                                              Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_0_1[3]     CFG4        D                  In      -         4.969       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_0_1[3]     CFG4        Y                  Out     0.284     5.253       -
    PRDATA_0_1[3]                                                         Net         -                  -       0.483     -           1
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_0[3]       CFG4        B                  In      -         5.736       -
    MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_0[3]       CFG4        Y                  Out     0.129     5.865       -
    MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]                     Net         -                  -       0.971     -           1
    MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST          MSS_010     F_HM0_RDATA[3]     In      -         6.837       -
    =============================================================================================================================================
    Total path delay (propagation time + setup) of 7.354 is 1.796(24.4%) logic and 5.557(75.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Finished final timing analysis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 238MB peak: 255MB)

    Finished timing report (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 238MB peak: 255MB)

    ---------------------------------------
    Resource Usage Report for MC_System_top

    Mapping to part: m2s010fbga484-1
    Cell usage:
    CCC             1 use
    CLKINT          3 uses
    MSS_010         1 use
    RCOSC_25_50MHZ  1 use
    RESOLVER_INTERFACE  1 use
    CFG1           13 uses
    CFG2           350 uses
    CFG3           693 uses
    CFG4           777 uses

    Carry primitives used for arithmetic functions:
    ARI1           1440 uses

    Sequential Cells:
    SLE            2407 uses

    DSP Blocks:    5
     MACC:         4 MultAdds
     MACC:         1 Mult

    I/O ports: 29
    I/O primitives: 28
    BIBUF          8 uses
    INBUF          6 uses
    OUTBUF         13 uses
    TRIBUFF        1 use

    Global Clock Buffers: 3

    Total LUTs:    3273

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
    MACC     Interface Logic : SLEs = 180; LUTs = 180;

    Total number of SLEs after P&R:  2407 + 0 + 0 + 180 = 2587;
    Total number of LUTs after P&R:  3273 + 0 + 0 + 180 = 3453;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 63MB peak: 255MB)

    Process took 0h:00m:18s realtime, 0h:00m:18s cputime
    # Thu Aug 25 10:43:36 2016

    ###########################################################]

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