Project Status Summary Page

Project Settings
Project Name | MC_System_top_syn | Implementation Name | synthesis
Top Module | work.MC_System_top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 118 | 71 | 0 | - | 00m:08s | - | 29-11-2017 15:53:52
(premap) | Complete | 91 | 17 | 0 | 0m:02s | 0m:02s | 170MB | 29-11-2017 15:53:56
(fpga_mapper) | Complete | 9 | 27 | 0 | 0m:20s | 0m:21s | 256MB | 29-11-2017 15:54:18
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 29-11-2017 15:53:54

Area Summary
Carry Cells | 2151 | Sequential Cells | 3469
DSP Blocks (MACC) (dsp_used) | 7 | I/O Cells | 28
Global Clock Buffers | 3 | LUTs (total_luts) | 5042

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 105.4 MHz | 0.513
MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock | 100.0 MHz | 380.5 MHz | 7.372
System | 100.0 MHz | 1029.4 MHz | 9.029

Optimizations Summary
Combined Clock Conversion | 0 / 2 |  |