KEY LIBERO "11.8"
KEY CAPTURE "11.8.2.4"
KEY DEFAULT_IMPORT_LOC "E:\Hotline_Cases\IP_cases\2012\493642-863181735\Mir_429\component\Actel\DirectCore\CORE429\3.1.103\rtl\vhdl\core"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "0"
KEY HDLTechnology "VHDL"
KEY VERILOGMODE "VERILOG2001"
KEY VHDLMODE "VHDL2008"
KEY UseConstraintFlowTechnology "FALSE"
KEY VendorTechnology_Family "SmartFusion2"
KEY VendorTechnology_Die "PA4M1000_N"
KEY VendorTechnology_Package "fg484"
KEY VendorTechnology_Speed "-1"
KEY VendorTechnology_DieVoltage "1.2"
KEY VendorTechnology_PART_RANGE "COM"
KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE "100_MS"
KEY VendorTechnology_IO_DEFT_STD "LVCMOS25"
KEY VendorTechnology_OPCONR ""
KEY VendorTechnology_PLL_SUPPLY "PLL_SUPPLY_25"
KEY VendorTechnology_RAD_EXPOSURE ""
KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
KEY VendorTechnology_RESTRICTPROBEPINS "1"
KEY VendorTechnology_RESTRICTSPIPINS "0"
KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE "0"
KEY VendorTechnology_TARGETDEVICESFORMIGRATION "M2S010;"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
KEY VendorTechnology_VCCI_1.2_VOLTR "COM"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLRS10\LiberoProject\SK1ABLRS10\SK1ABLRS10_5_1"
KEY ProjectDescription ""
KEY Pa4PeripheralNewSeq "GOOD"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "MC_System_top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
CURREV=2
ENDLIST
LIST LIBRARIES
COREAHBLITE_LIB
COREAPB3_LIB
ADC_SCALING_LIB
SINC3_FILTER_LIB
ENDLIST
LIST LIBRARY_COREAHBLITE_LIB
ALIAS=..\component\Actel\DirectCore\CoreAHBLite\5.0.100\mti\user_vhdl\COREAHBLITE_LIB
COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST LIBRARY_COREAPB3_LIB
ALIAS=COREAPB3_LIB
COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST LIBRARY_ADC_SCALING_LIB
ALIAS=ADC_SCALING_LIB
COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST LIBRARY_SINC3_FILTER_LIB
ALIAS=SINC3_FILTER_LIB
COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST FileManager
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf,actgen_cxf"
STATE="utd"
TIME="1451992831"
SIZE="3259"
PARENT="<project>\component\work\MC_System_sb\MC_System_sb.cxf"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.vhd,tb_hdl"
STATE="utd"
TIME="1451992831"
SIZE="2013"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\mti\scripts\wave_user.do,do"
STATE="utd"
TIME="1450167328"
SIZE="912"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="4009"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="9540"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="2074"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="12455"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="82848"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="45675"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="12780"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="23829"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\components.vhd,hdl"
STATE="utd"
TIME="1450167329"
SIZE="6172"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd,hdl"
STATE="utd"
TIME="1450167329"
SIZE="78851"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_iaddr_reg.vhd,hdl"
STATE="utd"
TIME="1450167329"
SIZE="5757"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd,hdl"
STATE="utd"
TIME="1450167329"
SIZE="9523"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
STATE="utd"
TIME="1450167328"
SIZE="28895"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
MODULE_UNDER_TEST="testbench"
SIMULATION_TIME="-all"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreResetP\7.0.104\CoreResetP.cxf,actgen_cxf"
STATE="utd"
TIME="1451992831"
SIZE="582"
PARENT="<project>\component\work\MC_System_sb\MC_System_sb.cxf"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd,hdl"
STATE="utd"
TIME="1450167329"
SIZE="75039"
PARENT="<project>\component\Actel\DirectCore\CoreResetP\7.0.104\CoreResetP.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp_pcie_hotreset.vhd,hdl"
STATE="utd"
TIME="1450167329"
SIZE="9297"
PARENT="<project>\component\Actel\DirectCore\CoreResetP\7.0.104\CoreResetP.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SgCore\FCCC\2.0.200\FCCC.cxf,actgen_cxf"
STATE="utd"
TIME="1451992831"
SIZE="241"
PARENT="<project>\component\work\MC_System_sb\MC_System_sb.cxf"
ENDFILE
VALUE "<project>\component\Actel\SgCore\OSC\1.0.105\OSC.cxf,actgen_cxf"
STATE="utd"
TIME="1451992833"
SIZE="682"
PARENT="<project>\component\work\MC_System_sb\MC_System_sb.cxf"
ENDFILE
VALUE "<project>\component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd,hdl"
STATE="utd"
TIME="1450167330"
SIZE="2164"
PARENT="<project>\component\Actel\SgCore\OSC\1.0.105\OSC.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SgCore\OSC\1.0.105\osc_comps_pre.vhd,hdl"
STATE="utd"
TIME="1450167330"
SIZE="2108"
PARENT="<project>\component\Actel\SgCore\OSC\1.0.105\OSC.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="PRECISION_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS\1.1.400\MSS.cxf,actgen_cxf"
STATE="utd"
TIME="1451992826"
SIZE="526"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CCC\1.0.100\MSS_CCC.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="253"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CC\1.0.100\MSS_CC.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="252"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CFGM\1.1.100\MSS_CFGM.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="254"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CM3\1.0.200\MSS_CM3.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="253"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_DDRB\1.0.200\MSS_DDRB.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="254"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_EDAC\1.0.101\MSS_EDAC.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="254"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_ENVM\1.0.101\MSS_ENVM.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="254"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_FIC32\1.0.100\MSS_FIC32.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="255"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_GPIO\1.0.100\MSS_GPIO.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="254"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_INTR\1.0.100\MSS_INTR.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="254"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_RESET\1.0.100\MSS_RESET.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="255"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_SECURITY\1.0.100\MSS_SECURITY.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="258"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_SWITCH\1.0.101\MSS_SWITCH.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="256"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_USB\1.0.101\MSS_USB.cxf,actgen_cxf"
STATE="utd"
TIME="1451992822"
SIZE="253"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\ADC_SCALING.cxf,actgen_cxf"
STATE="utd"
TIME="1510661130"
SIZE="910"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\coreparameters.vhd,tb_hdl"
STATE="utd"
TIME="1510661130"
SIZE="726"
PARENT="<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\ADC_SCALING.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Encrypted\adc_scaling.vhd,hdl"
STATE="utd"
TIME="1510661130"
SIZE="35505"
LIBRARY="ADC_SCALING_LIB"
PARENT="<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\ADC_SCALING.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Test\adc_scaling_tb.vhd,tb_hdl"
STATE="utd"
TIME="1510661130"
SIZE="38940"
PARENT="<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\ADC_SCALING.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Test\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1510661130"
SIZE="42824"
PARENT="<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\ADC_SCALING.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Encrypted\FOC_Transforms.vhd,hdl"
STATE="utd"
TIME="1510661130"
SIZE="124351"
PARENT="<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\FOC_TRANSFORMS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\FOC_TRANSFORMS.cxf,actgen_cxf"
STATE="utd"
TIME="1510661130"
SIZE="783"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Test\foc_transforms_tb.vhd,tb_hdl"
STATE="utd"
TIME="1510661130"
SIZE="56452"
PARENT="<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\FOC_TRANSFORMS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Test\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1510661130"
SIZE="42760"
PARENT="<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\FOC_TRANSFORMS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Encrypted\olmng.vhd,hdl"
STATE="utd"
TIME="1510661131"
SIZE="39622"
PARENT="<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\OLMNG.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\OLMNG.cxf,actgen_cxf"
STATE="utd"
TIME="1510661131"
SIZE="756"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\olmng_tb.vhd,tb_hdl"
STATE="utd"
TIME="1510661131"
SIZE="29280"
PARENT="<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\OLMNG.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1510661131"
SIZE="42760"
PARENT="<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\OLMNG.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\Encrypted\PWM3ph.vhd,hdl"
STATE="utd"
TIME="1503903395"
SIZE="15726"
PARENT="<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\PWM3PH.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\PWM3PH.cxf,actgen_cxf"
STATE="utd"
TIME="1510661132"
SIZE="771"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\Stimulus\pwm3ph_tb.vhd,tb_hdl"
STATE="utd"
TIME="1503903394"
SIZE="49238"
PARENT="<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\PWM3PH.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\Stimulus\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1503903394"
SIZE="42760"
PARENT="<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\PWM3PH.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Encrypted\pwm_scaling.vhd,hdl"
STATE="utd"
TIME="1503901117"
SIZE="28692"
PARENT="<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\PWM_SCALING.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\PWM_SCALING.cxf,actgen_cxf"
STATE="utd"
TIME="1510661132"
SIZE="774"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Test\pwm_scaling_tb.vhd,tb_hdl"
STATE="utd"
TIME="1503901117"
SIZE="26440"
PARENT="<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\PWM_SCALING.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Test\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1503901117"
SIZE="42760"
PARENT="<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\PWM_SCALING.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Encrypted\rate_limiter.vhd,hdl"
STATE="utd"
TIME="1503901118"
SIZE="22929"
PARENT="<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\RATE_LIMITER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\RATE_LIMITER.cxf,actgen_cxf"
STATE="utd"
TIME="1510661133"
SIZE="777"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\rate_limiter_tb.vhd,tb_hdl"
STATE="utd"
TIME="1503901118"
SIZE="54422"
PARENT="<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\RATE_LIMITER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1503901118"
SIZE="42760"
PARENT="<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\RATE_LIMITER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Encrypted\resolver_interface.vhd,hdl"
STATE="utd"
TIME="1510661134"
SIZE="120476"
PARENT="<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\RESOLVER_INTERFACE.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\RESOLVER_INTERFACE.cxf,actgen_cxf"
STATE="utd"
TIME="1510661134"
SIZE="711"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Test\resolver_interface_tb.vhd,tb_hdl"
STATE="utd"
TIME="1510661134"
SIZE="8794"
PARENT="<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\RESOLVER_INTERFACE.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Encrypted\seq_controller.vhd,hdl"
STATE="utd"
TIME="1510661134"
SIZE="28302"
PARENT="<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\SEQ_CONTROLLER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\SEQ_CONTROLLER.cxf,actgen_cxf"
STATE="utd"
TIME="1510661134"
SIZE="789"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Test\seq_controller_tb.vhd,tb_hdl"
STATE="utd"
TIME="1510661134"
SIZE="33867"
PARENT="<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\SEQ_CONTROLLER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Test\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1510661134"
SIZE="42760"
PARENT="<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\SEQ_CONTROLLER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\coreparameters.vhd,tb_hdl"
STATE="utd"
TIME="1510661135"
SIZE="734"
PARENT="<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\SINC3_FILTER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Encrypted\sinc3_filter.vhd,hdl"
STATE="utd"
TIME="1510661135"
SIZE="17563"
LIBRARY="SINC3_FILTER_LIB"
PARENT="<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\SINC3_FILTER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\SINC3_FILTER.cxf,actgen_cxf"
STATE="utd"
TIME="1510661135"
SIZE="828"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Test\sinc3_filter_tb.vhd,tb_hdl"
STATE="utd"
TIME="1510661134"
SIZE="7442"
PARENT="<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\SINC3_FILTER.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Encrypted\speed_id_iq_pi.vhd,hdl"
STATE="utd"
TIME="1503901118"
SIZE="85841"
PARENT="<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\SPEED_ID_IQ_PI.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\SPEED_ID_IQ_PI.cxf,actgen_cxf"
STATE="utd"
TIME="1510661135"
SIZE="791"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Stimulus\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1503901118"
SIZE="42760"
PARENT="<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\SPEED_ID_IQ_PI.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Stimulus\speed_id_iq_pi_tb.vhd,tb_hdl"
STATE="utd"
TIME="1503901118"
SIZE="32840"
PARENT="<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\SPEED_ID_IQ_PI.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Encrypted\svm.vhd,hdl"
STATE="utd"
TIME="1503901118"
SIZE="13264"
PARENT="<project>\component\Microsemi\SolutionCore\SVM\4.1.0\SVM.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\SVM.cxf,actgen_cxf"
STATE="utd"
TIME="1510661136"
SIZE="750"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\sim_pkg.vhd,tb_hdl"
STATE="utd"
TIME="1503901118"
SIZE="42760"
PARENT="<project>\component\Microsemi\SolutionCore\SVM\4.1.0\SVM.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\svm_tb.vhd,tb_hdl"
STATE="utd"
TIME="1503901118"
SIZE="23439"
PARENT="<project>\component\Microsemi\SolutionCore\SVM\4.1.0\SVM.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\Bldc_Axis\Bldc_Axis.cxf,actgen_cxf"
STATE="utd"
TIME="1510661141"
SIZE="9960"
ENDFILE
VALUE "<project>\component\work\Bldc_Axis\Bldc_Axis.vhd,hdl"
STATE="utd"
TIME="1510661136"
SIZE="45596"
PARENT="<project>\component\work\Bldc_Axis\Bldc_Axis.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf"
STATE="utd"
TIME="1425967493"
SIZE="1892"
ENDFILE
VALUE "<project>\component\work\MC_System\MC_System.cxf,actgen_cxf"
STATE="utd"
TIME="1479727520"
SIZE="9777"
ENDFILE
VALUE "<project>\component\work\MC_System\MC_System.vhd,hdl"
STATE="utd"
TIME="1479727519"
SIZE="11007"
PARENT="<project>\component\work\MC_System\MC_System.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MC_System\subsystem.bfm,sim"
STATE="utd"
TIME="1425966375"
SIZE="851"
ENDFILE
VALUE "<project>\component\work\MC_System_sb\CCC_0\MC_System_sb_CCC_0_FCCC.cxf,actgen_cxf"
STATE="utd"
TIME="1451992831"
SIZE="704"
PARENT="<project>\component\work\MC_System_sb\MC_System_sb.cxf"
ENDFILE
VALUE "<project>\component\work\MC_System_sb\CCC_0\MC_System_sb_CCC_0_FCCC.vhd,hdl"
STATE="utd"
TIME="1451992831"
SIZE="5838"
PARENT="<project>\component\work\MC_System_sb\CCC_0\MC_System_sb_CCC_0_FCCC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.cxf,actgen_cxf"
STATE="utd"
TIME="1451992833"
SIZE="472"
PARENT="<project>\component\work\MC_System_sb\MC_System_sb.cxf"
ENDFILE
VALUE "<project>\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd,hdl"
STATE="utd"
TIME="1451992833"
SIZE="1582"
PARENT="<project>\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MC_System_sb\MC_System_sb.cxf,actgen_cxf"
STATE="utd"
TIME="1451992835"
SIZE="13412"
ENDFILE
VALUE "<project>\component\work\MC_System_sb\MC_System_sb.vhd,hdl"
STATE="utd"
TIME="1451992833"
SIZE="37034"
PARENT="<project>\component\work\MC_System_sb\MC_System_sb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MC_System_sb_MSS\CM3_compile_bfm.tcl,sim"
STATE="utd"
TIME="1451992826"
SIZE="500"
ENDFILE
VALUE "<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf,actgen_cxf"
STATE="utd"
TIME="1451992827"
SIZE="17053"
ENDFILE
VALUE "<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.vhd,hdl"
STATE="utd"
TIME="1451992826"
SIZE="90297"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS_pre.vhd,hdl"
STATE="utd"
TIME="1451992826"
SIZE="70098"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="PRECISION_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS_syn.vhd,hdl"
STATE="utd"
TIME="1451992826"
SIZE="70093"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\MC_System_sb_MSS\test.bfm,sim"
STATE="utd"
TIME="1451992826"
SIZE="734"
ENDFILE
VALUE "<project>\component\work\MC_System_sb_MSS\user.bfm,sim"
STATE="utd"
TIME="1451992826"
SIZE="555"
ENDFILE
VALUE "<project>\component\work\MC_System_top\MC_System_top.cxf,actgen_cxf"
STATE="utd"
TIME="1510661148"
SIZE="6210"
ENDFILE
VALUE "<project>\component\work\MC_System_top\MC_System_top.vhd,hdl"
STATE="utd"
TIME="1510661145"
SIZE="12415"
PARENT="<project>\component\work\MC_System_top\MC_System_top.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\Stepper_Axis\Stepper_Axis.cxf,actgen_cxf"
STATE="utd"
TIME="1444719813"
SIZE="8187"
ENDFILE
VALUE "<project>\component\work\Stepper_Axis\Stepper_Axis.vhd,hdl"
STATE="utd"
TIME="1444719811"
SIZE="34909"
PARENT="<project>\component\work\Stepper_Axis\Stepper_Axis.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\constraint\io\MC_System_top.io.pdc,io_pdc"
STATE="utd"
TIME="1511945012"
SIZE="2704"
ENDFILE
VALUE "<project>\constraint\MS_MC_System_top_compile.sdc,sdc"
STATE="utd"
TIME="1511947799"
SIZE="4262"
ENDFILE
VALUE "<project>\designer\impl2\MC_System_top.ide_des,ide_des"
STATE="utd"
TIME="1511950984"
SIZE="547"
ENDFILE
VALUE "<project>\designer\impl2\MC_System_top_1.ide_des,ide_des"
STATE="utd"
TIME="1445942978"
SIZE="372"
ENDFILE
VALUE "<project>\designer\impl2\XTLOSC_FAB.ide_des,ide_des"
STATE="utd"
TIME="1451976603"
SIZE="226"
ENDFILE
VALUE "<project>\hdl\adc_interface_795x.vhd,hdl"
STATE="utd"
TIME="1507807684"
SIZE="28699"
ENDFILE
VALUE "<project>\hdl\apb3_if.vhd,hdl"
STATE="utd"
TIME="1508133304"
SIZE="45087"
ENDFILE
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
STATE="utd"
TIME="1450167328"
SIZE="1229"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
ENDFILE
VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim"
STATE="utd"
TIME="1451992826"
SIZE="500"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
STATE="utd"
TIME="1427446517"
SIZE="8016"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
ENDFILE
VALUE "<project>\simulation\peripheral_init.bfm,sim"
STATE="utd"
TIME="1450167300"
SIZE="8450"
PARENT="<project>\component\Actel\SmartFusion2MSS\MSS\1.1.400\MSS.cxf"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1510661146"
SIZE="824"
PARENT="<project>\component\work\MC_System\MC_System.cxf"
PARENT="<project>\component\work\MC_System_top\MC_System_top.cxf"
ENDFILE
VALUE "<project>\simulation\test.bfm,sim"
STATE="utd"
TIME="1451992826"
SIZE="734"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\simulation\user.bfm,sim"
STATE="utd"
TIME="1437632209"
SIZE="555"
PARENT="<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.cxf"
ENDFILE
VALUE "<project>\synthesis\MC_System_top_1.so,so"
STATE="utd"
TIME="1511951058"
SIZE="296"
ENDFILE
VALUE "<project>\synthesis\MC_System_top_1.vm,syn_vm"
STATE="utd"
TIME="1511951056"
SIZE="3026823"
ENDFILE
VALUE "<project>\synthesis\MC_System_top_1_vm.sdc,syn_sdc"
STATE="utd"
TIME="1511951057"
SIZE="1423"
ENDFILE
VALUE "<project>\synthesis\MC_System_top_syn.prj,prj"
STATE="utd"
TIME="1512105317"
SIZE="7488"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "FOC_TRANSFORMS::work"
FILE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Encrypted\FOC_Transforms.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Test\foc_transforms_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST "MC_System::work"
FILE "<project>\component\work\MC_System\MC_System.vhd,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST PinReports
VALUE "<project>\designer\MC_System\MC_System_pinrpt_name.rpt,log"
VALUE "<project>\designer\MC_System\MC_System_pinrpt_number.rpt,log"
VALUE "<project>\designer\MC_System\MC_System_bankrpt.rpt,log"
VALUE "<project>\designer\MC_System\MC_System_ioff.xml,log"
ENDLIST
ENDLIST
LIST "MC_System_sb::work"
FILE "<project>\component\work\MC_System_sb\MC_System_sb.vhd,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "MC_System_sb_MSS::work"
FILE "<project>\component\work\MC_System_sb_MSS\MC_System_sb_MSS.vhd,hdl"
LIST Other_Association
VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST "MC_System_top::work"
FILE "<project>\component\work\MC_System_top\MC_System_top.vhd,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSYNTHESIS(<project>\synthesis\MC_System_top_1.vm,syn_vm)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\designer\impl1\MC_System_top_fp\MC_System_top.pro,pro"
VALUE "<project>\synthesis\MC_System_top.vm,syn_vm"
VALUE "<project>\synthesis\MC_System_top.edn,syn_edn"
VALUE "<project>\synthesis\MC_System_top_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\MC_System_top.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\MC_System_top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\MC_System_top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\MC_System_top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\MC_System_top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\MC_System_top_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\MC_System_top.adb,adb"
VALUE "<project>\designer\impl1\MC_System_top.fdb,fdb"
VALUE "<project>\designer\impl1\MC_System_top.pdb,pdb"
VALUE "<project>\designer\impl1\MC_System_top.stp,stp"
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSYNTHESIS(<project>\synthesis\MC_System_top_1.vm,syn_vm)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\MC_System_top.edn,syn_edn"
VALUE "<project>\synthesis\MC_System_top.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\MC_System_top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\MC_System_top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\MC_System_top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\MC_System_top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\MC_System_top_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl2\MC_System_top.adb,adb"
VALUE "<project>\designer\impl2\MC_System_top.fdb,fdb"
VALUE "<project>\designer\impl2\MC_System_top.pdb,pdb"
VALUE "<project>\designer\impl2\MC_System_top.stp,stp"
VALUE "<project>\designer\impl2\MC_System_top_fp\MC_System_top.pro,pro"
VALUE "<project>\synthesis\MC_System_top_1.vm,syn_vm"
VALUE "<project>\synthesis\MC_System_top_1_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST PinReports
VALUE "<project>\designer\MC_System_top\MC_System_top_pinrpt_name.rpt,log"
VALUE "<project>\designer\MC_System_top\MC_System_top_pinrpt_number.rpt,log"
VALUE "<project>\designer\MC_System_top\MC_System_top_bankrpt.rpt,log"
VALUE "<project>\designer\MC_System_top\MC_System_top_ioff.xml,log"
ENDLIST
ENDLIST
LIST "OLMNG::work"
FILE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Encrypted\olmng.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\olmng_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\olmng_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "PWM3PH::work"
FILE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\Encrypted\PWM3ph.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\Stimulus\pwm3ph_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\Stimulus\sim_pkg.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST "PWM_SCALING::work"
FILE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Encrypted\pwm_scaling.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Test\pwm_scaling_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST "RATE_LIMITER::work"
FILE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Encrypted\rate_limiter.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\rate_limiter_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\rate_limiter_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "RESOLVER_INTERFACE::work"
FILE "<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Encrypted\resolver_interface.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Test\resolver_interface_tb.vhd,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Test\resolver_interface_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "SEQ_CONTROLLER::work"
FILE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Encrypted\seq_controller.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Test\seq_controller_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST "SPEED_ID_IQ_PI::work"
FILE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Encrypted\speed_id_iq_pi.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Stimulus\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Stimulus\speed_id_iq_pi_tb.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST "STEPPER_THETA::work"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\STEPPER_THETA\3.0.2\Stimulus\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\STEPPER_THETA\3.0.2\Stimulus\stepper_theta_tb.vhd,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Microsemi\SolutionCore\STEPPER_THETA\3.0.2\Stimulus\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\STEPPER_THETA\3.0.2\Stimulus\stepper_theta_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "SVM::work"
FILE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Encrypted\svm.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\svm_tb.vhd,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\svm_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "ADC_SCALING::ADC_SCALING_LIB"
FILE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Encrypted\adc_scaling.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Test\adc_scaling_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST "sinc3_filter::SINC3_FILTER_LIB"
FILE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Encrypted\sinc3_filter.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Test\sinc3_filter_tb.vhd,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Test\sinc3_filter_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST STEPPER_THETA
VALUE "<project>\component\Microsemi\SolutionCore\STEPPER_THETA\3.0.2\Stimulus\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\STEPPER_THETA\3.0.2\Stimulus\stepper_theta_tb.vhd,tb_hdl"
ENDLIST
LIST OLMNG
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\olmng_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST RATE_LIMITER
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\rate_limiter_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST RESOLVER_INTERFACE
VALUE "<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Test\resolver_interface_tb.vhd,tb_hdl"
ENDLIST
LIST SVM
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\svm_tb.vhd,tb_hdl"
ENDLIST
LIST sinc3_filter
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Test\sinc3_filter_tb.vhd,tb_hdl"
ENDLIST
LIST MC_System_sb
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST FOC_TRANSFORMS
VALUE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Test\foc_transforms_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST PWM3PH
VALUE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\Stimulus\pwm3ph_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\PWM3PH\4.1.2\Stimulus\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST PWM_SCALING
VALUE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Test\pwm_scaling_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST SEQ_CONTROLLER
VALUE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Test\seq_controller_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST SPEED_ID_IQ_PI
VALUE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Stimulus\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Stimulus\speed_id_iq_pi_tb.vhd,tb_hdl"
ENDLIST
LIST STEPPER_THETA
VALUE "<project>\component\Microsemi\SolutionCore\STEPPER_THETA\3.0.2\Stimulus\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\STEPPER_THETA\3.0.2\Stimulus\stepper_theta_tb.vhd,tb_hdl"
ENDLIST
LIST ADC_SCALING
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Test\adc_scaling_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST MC_System_top
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST OLMNG
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\olmng_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST RATE_LIMITER
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\rate_limiter_tb.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\sim_pkg.vhd,tb_hdl"
ENDLIST
LIST RESOLVER_INTERFACE
VALUE "<project>\component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Test\resolver_interface_tb.vhd,tb_hdl"
ENDLIST
LIST SVM
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\sim_pkg.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SVM\4.1.0\Test\svm_tb.vhd,tb_hdl"
ENDLIST
LIST sinc3_filter
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Test\sinc3_filter_tb.vhd,tb_hdl"
ENDLIST
LIST MC_System
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST MC_System_sb
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST MC_System_sb_MSS
VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1fs
VsimOpt=
EntityName=svm_tb
TopInstanceName=<top>_0
DoFileName=C:/MS_MC_single_axis_NB_050_484/simulation/test.do
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
TimeUnit=1
TimeUnitBase=ns
Precision=100
PrecisionBase=ps
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=TRUE
EnableDesignSeparationOn=FALSE
EnableSETMitigationOn=FALSE
DisplayFanoutLimit=10
AbortFlowOnPDCErrorsOn=TRUE
AbortFlowOnSDCErrorsOn=TRUE
InstantiateInSmartDesign=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Synplify Pro ME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\bin\synplify_pro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSim ME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="F:\Microsemi\Libero_SoC_v11.8\Modelsim\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FPExpress"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="F:\Microsemi\Libero_SoC_v11.8\Designer\bin\FPExpress.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Identify Debugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="F:\Microsemi\Libero_SoC_v11.8\Identify\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "MC_System_sb::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "MC_System_top::work"
LIST Impl1
ideSYNTHESIS(<project>\synthesis\MC_System_top_1.vm,syn_vm)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\designer\impl1\MC_System_top_fp\MC_System_top.pro,pro"
VALUE "<project>\synthesis\MC_System_top.vm,syn_vm"
VALUE "<project>\synthesis\MC_System_top.edn,syn_edn"
VALUE "<project>\synthesis\MC_System_top_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\MC_System_top.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\MC_System_top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\MC_System_top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\MC_System_top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\MC_System_top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\MC_System_top_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\MC_System_top.adb,adb"
VALUE "<project>\designer\impl1\MC_System_top.fdb,fdb"
VALUE "<project>\designer\impl1\MC_System_top.pdb,pdb"
VALUE "<project>\designer\impl1\MC_System_top.stp,stp"
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSYNTHESIS(<project>\synthesis\MC_System_top_1.vm,syn_vm)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\MC_System_top.edn,syn_edn"
VALUE "<project>\synthesis\MC_System_top.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\MC_System_top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\MC_System_top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\MC_System_top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\MC_System_top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\MC_System_top_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl2\MC_System_top.adb,adb"
VALUE "<project>\designer\impl2\MC_System_top.fdb,fdb"
VALUE "<project>\designer\impl2\MC_System_top.pdb,pdb"
VALUE "<project>\designer\impl2\MC_System_top.stp,stp"
VALUE "<project>\designer\impl2\MC_System_top_fp\MC_System_top.pro,pro"
VALUE "<project>\synthesis\MC_System_top_1.vm,syn_vm"
VALUE "<project>\synthesis\MC_System_top_1_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "OLMNG::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "RATE_LIMITER::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "RESOLVER_INTERFACE::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "STEPPER_THETA::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "SVM::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "sinc3_filter::SINC3_FILTER_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Export Bitstream:MC_System_top_exportBitstream.log
StartPage;StartPage;0
SmartDesign;MC_System;0
SmartDesign;Bldc_Axis;0
ACTIVEVIEW;MC_System
ENDLIST
LIST ModuleSubBlockList
LIST "adc_interface::work","","FALSE","FALSE"
ENDLIST
LIST "adc_interface_795x::work","hdl\adc_interface_795x.vhd","FALSE","FALSE"
SUBBLOCK "spi_engine::work","hdl\adc_interface_795x.vhd","FALSE","FALSE"
ENDLIST
LIST "ADC_SCALING::work","","FALSE","FALSE"
ENDLIST
LIST "apb3_if::work","hdl\apb3_if.vhd","FALSE","FALSE"
ENDLIST
LIST "apb3_if_st::work","","FALSE","FALSE"
ENDLIST
LIST "Bldc_Axis::work","component\work\Bldc_Axis\Bldc_Axis.vhd","TRUE","FALSE"
SUBBLOCK "FOC_TRANSFORMS::work","component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Encrypted\FOC_Transforms.vhd","FALSE","FALSE"
SUBBLOCK "OLMNG::work","component\Microsemi\SolutionCore\OLMNG\4.1.1\Encrypted\olmng.vhd","FALSE","FALSE"
SUBBLOCK "PWM3PH::work","component\Microsemi\SolutionCore\PWM3PH\4.1.2\Encrypted\PWM3ph.vhd","FALSE","FALSE"
SUBBLOCK "PWM_SCALING::work","component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Encrypted\pwm_scaling.vhd","FALSE","FALSE"
SUBBLOCK "RATE_LIMITER::work","component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Encrypted\rate_limiter.vhd","FALSE","FALSE"
SUBBLOCK "RESOLVER_INTERFACE::work","component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Encrypted\resolver_interface.vhd","FALSE","FALSE"
SUBBLOCK "SEQ_CONTROLLER::work","component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Encrypted\seq_controller.vhd","FALSE","FALSE"
SUBBLOCK "SPEED_ID_IQ_PI::work","component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Encrypted\speed_id_iq_pi.vhd","FALSE","FALSE"
SUBBLOCK "SVM::work","component\Microsemi\SolutionCore\SVM\4.1.0\Encrypted\svm.vhd","FALSE","FALSE"
SUBBLOCK "adc_interface_795x::work","hdl\adc_interface_795x.vhd","FALSE","FALSE"
SUBBLOCK "apb3_if::work","hdl\apb3_if.vhd","FALSE","FALSE"
SUBBLOCK "ADC_SCALING::ADC_SCALING_LIB","component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Encrypted\adc_scaling.vhd","FALSE","FALSE"
SUBBLOCK "sinc3_filter::SINC3_FILTER_LIB","component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Encrypted\sinc3_filter.vhd","FALSE","FALSE"
ENDLIST
LIST "CoreResetP::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd","FALSE","FALSE"
SUBBLOCK "coreresetp_pcie_hotreset::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp_pcie_hotreset.vhd","FALSE","FALSE"
ENDLIST
LIST "coreresetp_pcie_hotreset::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp_pcie_hotreset.vhd","FALSE","FALSE"
ENDLIST
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
SUBBLOCK "SmartFusion2_CMSIS::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_GPIO_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_HPDMA_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_NVM_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_System_Services_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_Timer_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_USB_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "FOC_TRANSFORMS::work","component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Encrypted\FOC_Transforms.vhd","FALSE","FALSE"
ENDLIST
LIST "MC_System::work","component\work\MC_System\MC_System.vhd","TRUE","FALSE"
SUBBLOCK "MC_System_sb::work","component\work\MC_System_sb\MC_System_sb.vhd","TRUE","FALSE"
ENDLIST
LIST "MC_System_sb::work","component\work\MC_System_sb\MC_System_sb.vhd","TRUE","FALSE"
SUBBLOCK "CoreResetP::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd","FALSE","FALSE"
SUBBLOCK "MC_System_sb_CCC_0_FCCC::work","component\work\MC_System_sb\CCC_0\MC_System_sb_CCC_0_FCCC.vhd","FALSE","FALSE"
SUBBLOCK "MC_System_sb_FABOSC_0_OSC::work","component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd","FALSE","FALSE"
SUBBLOCK "MC_System_sb_MSS::work","component\work\MC_System_sb_MSS\MC_System_sb_MSS.vhd","TRUE","FALSE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB::components","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd","FALSE","FALSE"
ENDLIST
LIST "MC_System_sb_CCC_0_FCCC::work","component\work\MC_System_sb\CCC_0\MC_System_sb_CCC_0_FCCC.vhd","FALSE","FALSE"
ENDLIST
LIST "MC_System_sb_FABOSC_0_OSC::work","component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "MC_System_sb_MSS::work","component\work\MC_System_sb_MSS\MC_System_sb_MSS.vhd","TRUE","FALSE"
SUBBLOCK "MSS_010::work","component\work\MC_System_sb_MSS\MC_System_sb_MSS_syn.vhd","FALSE","FALSE"
ENDLIST
LIST "MC_System_top::work","component\work\MC_System_top\MC_System_top.vhd","TRUE","FALSE"
SUBBLOCK "Bldc_Axis::work","component\work\Bldc_Axis\Bldc_Axis.vhd","TRUE","FALSE"
SUBBLOCK "MC_System::work","component\work\MC_System\MC_System.vhd","TRUE","FALSE"
ENDLIST
LIST "MSS_010::work","component\work\MC_System_sb_MSS\MC_System_sb_MSS_syn.vhd","FALSE","FALSE"
ENDLIST
LIST "OLMNG::work","component\Microsemi\SolutionCore\OLMNG\4.1.1\Encrypted\olmng.vhd","FALSE","FALSE"
ENDLIST
LIST "PWM3PH::work","component\Microsemi\SolutionCore\PWM3PH\4.1.2\Encrypted\PWM3ph.vhd","FALSE","FALSE"
ENDLIST
LIST "PWM_SCALING::work","component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Encrypted\pwm_scaling.vhd","FALSE","FALSE"
ENDLIST
LIST "RATE_LIMITER::work","component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Encrypted\rate_limiter.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RESOLVER_INTERFACE::work","component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Encrypted\resolver_interface.vhd","FALSE","FALSE"
ENDLIST
LIST "SEQ_CONTROLLER::work","component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Encrypted\seq_controller.vhd","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_CMSIS::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_GPIO_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_HPDMA_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_NVM_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_System_Services_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_USB_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SPEED_ID_IQ_PI::work","component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Encrypted\speed_id_iq_pi.vhd","FALSE","FALSE"
ENDLIST
LIST "spi_engine::work","hdl\adc_interface_795x.vhd","FALSE","FALSE"
ENDLIST
LIST "Stepper_Axis::work","component\work\Stepper_Axis\Stepper_Axis.vhd","TRUE","FALSE"
SUBBLOCK "FOC_TRANSFORMS::work","component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Encrypted\FOC_Transforms.vhd","FALSE","FALSE"
SUBBLOCK "PWM3PH::work","component\Microsemi\SolutionCore\PWM3PH\4.1.2\Encrypted\PWM3ph.vhd","FALSE","FALSE"
SUBBLOCK "PWM_SCALING::work","component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Encrypted\pwm_scaling.vhd","FALSE","FALSE"
SUBBLOCK "SEQ_CONTROLLER::work","component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Encrypted\seq_controller.vhd","FALSE","FALSE"
SUBBLOCK "SPEED_ID_IQ_PI::work","component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Encrypted\speed_id_iq_pi.vhd","FALSE","FALSE"
SUBBLOCK "STEPPER_THETA::work","","FALSE","FALSE"
SUBBLOCK "adc_interface::work","","FALSE","FALSE"
SUBBLOCK "apb3_if_st::work","","FALSE","FALSE"
SUBBLOCK "ADC_SCALING::ADC_SCALING_LIB","component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Encrypted\adc_scaling.vhd","FALSE","FALSE"
ENDLIST
LIST "STEPPER_THETA::work","","FALSE","FALSE"
ENDLIST
LIST "SVM::work","component\Microsemi\SolutionCore\SVM\4.1.0\Encrypted\svm.vhd","FALSE","FALSE"
ENDLIST
LIST "XTLOSC::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "XTLOSC_FAB::work","component\Actel\SgCore\OSC\1.0.105\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "adc_scaling_tb::work","component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Test\adc_scaling_tb.vhd","FALSE","TRUE"
SUBBLOCK "ADC_SCALING::ADC_SCALING_LIB","component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Encrypted\adc_scaling.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_rot_ri::work","","FALSE","FALSE"
ENDLIST
LIST "coreparameters::work","component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\coreparameters.vhd","FALSE","TRUE"
ENDLIST
LIST "coreparameters::work","component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\coreparameters.vhd","FALSE","TRUE"
ENDLIST
LIST "foc_transforms_tb::work","component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Test\foc_transforms_tb.vhd","FALSE","TRUE"
SUBBLOCK "FOC_TRANSFORMS::work","component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Encrypted\FOC_Transforms.vhd","FALSE","FALSE"
ENDLIST
LIST "olmng_tb::work","component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\olmng_tb.vhd","FALSE","TRUE"
SUBBLOCK "OLMNG::work","component\Microsemi\SolutionCore\OLMNG\4.1.1\Encrypted\olmng.vhd","FALSE","FALSE"
ENDLIST
LIST "pwm3ph_tb::work","component\Microsemi\SolutionCore\PWM3PH\4.1.2\Stimulus\pwm3ph_tb.vhd","FALSE","TRUE"
SUBBLOCK "PWM3PH::work","component\Microsemi\SolutionCore\PWM3PH\4.1.2\Encrypted\PWM3ph.vhd","FALSE","FALSE"
ENDLIST
LIST "pwm_scaling_tb::work","component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Test\pwm_scaling_tb.vhd","FALSE","TRUE"
SUBBLOCK "PWM_SCALING::work","component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Encrypted\pwm_scaling.vhd","FALSE","FALSE"
ENDLIST
LIST "rate_limiter_tb::work","component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\rate_limiter_tb.vhd","FALSE","TRUE"
SUBBLOCK "RATE_LIMITER::work","component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Encrypted\rate_limiter.vhd","FALSE","FALSE"
ENDLIST
LIST "resolver_interface_tb::work","component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Test\resolver_interface_tb.vhd","FALSE","TRUE"
SUBBLOCK "RESOLVER_INTERFACE::work","component\Microsemi\SolutionCore\RESOLVER_INTERFACE\4.2.0\Encrypted\resolver_interface.vhd","FALSE","FALSE"
SUBBLOCK "cordic_rot_ri::work","","FALSE","FALSE"
ENDLIST
LIST "seq_controller_tb::work","component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Test\seq_controller_tb.vhd","FALSE","TRUE"
SUBBLOCK "SEQ_CONTROLLER::work","component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Encrypted\seq_controller.vhd","FALSE","FALSE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Test\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\FOC_TRANSFORMS\4.1.1\Test\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\OLMNG\4.1.1\Test\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\PWM3PH\4.1.2\Stimulus\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\PWM_SCALING\4.1.0\Test\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\RATE_LIMITER\4.1.0\Test\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\SEQ_CONTROLLER\4.1.1\Test\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Stimulus\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sim_pkg::work","component\Microsemi\SolutionCore\SVM\4.1.0\Test\sim_pkg.vhd","FALSE","TRUE"
ENDLIST
LIST "sinc3_filter_tb::work","component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Test\sinc3_filter_tb.vhd","FALSE","TRUE"
SUBBLOCK "sinc3_filter::SINC3_FILTER_LIB","component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Encrypted\sinc3_filter.vhd","FALSE","FALSE"
ENDLIST
LIST "speed_id_iq_pi_tb::work","component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Stimulus\speed_id_iq_pi_tb.vhd","FALSE","TRUE"
SUBBLOCK "SPEED_ID_IQ_PI::work","component\Microsemi\SolutionCore\SPEED_ID_IQ_PI\4.1.0\Encrypted\speed_id_iq_pi.vhd","FALSE","FALSE"
ENDLIST
LIST "svm_tb::work","component\Microsemi\SolutionCore\SVM\4.1.0\Test\svm_tb.vhd","FALSE","TRUE"
SUBBLOCK "SVM::work","component\Microsemi\SolutionCore\SVM\4.1.0\Encrypted\svm.vhd","FALSE","FALSE"
ENDLIST
LIST "components::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\components.vhd","FALSE","FALSE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB::components","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd","FALSE","FALSE"
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB::components","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd","FALSE","FALSE"
SUBBLOCK "COREAPB3_MUXPTOB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd","FALSE","FALSE"
SUBBLOCK "coreapb3_iaddr_reg::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_iaddr_reg.vhd","FALSE","FALSE"
ENDLIST
LIST "coreapb3_iaddr_reg::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_iaddr_reg.vhd","FALSE","FALSE"
ENDLIST
LIST "COREAPB3_MUXPTOB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd","FALSE","FALSE"
ENDLIST
LIST "bfM_Ahbl::COREAPB3_LIB","","FALSE","FALSE"
ENDLIST
LIST "bfM_ahblAPB::COREAPB3_LIB","","FALSE","FALSE"
ENDLIST
LIST "BFM_ahbSLAve::COREAPB3_LIB","","FALSE","FALSE"
ENDLIST
LIST "Bfm_aHBSlavEEXt::COREAPB3_LIB","","FALSE","FALSE"
ENDLIST
LIST "bfm_APb::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
SUBBLOCK "bfm_Main::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
SUBBLOCK "BFMA1i1lI::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
ENDLIST
LIST "Bfm_aPB2apb::COREAPB3_LIB","","FALSE","FALSE"
ENDLIST
LIST "BFM_apbSLAve::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslave.vhd","FALSE","TRUE"
SUBBLOCK "BFm_apBSLaveEXT::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
ENDLIST
LIST "BFm_apBSLaveEXT::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_Main::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_misc::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\misc.vhd","FALSE","TRUE"
ENDLIST
LIST "bfM_packAGE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_package.vhd","FALSE","TRUE"
SUBBLOCK "BFMA1i1lI::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
SUBBLOCK "BFM_ahbSLAve::COREAPB3_LIB","","FALSE","FALSE"
SUBBLOCK "BFM_apbSLAve::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslave.vhd","FALSE","TRUE"
SUBBLOCK "BFm_apBSLaveEXT::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
SUBBLOCK "Bfm_aHBSlavEEXt::COREAPB3_LIB","","FALSE","FALSE"
SUBBLOCK "Bfm_aPB2apb::COREAPB3_LIB","","FALSE","FALSE"
SUBBLOCK "bfM_Ahbl::COREAPB3_LIB","","FALSE","FALSE"
SUBBLOCK "bfM_ahblAPB::COREAPB3_LIB","","FALSE","FALSE"
SUBBLOCK "bfm_APb::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
SUBBLOCK "bfm_Main::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_textio::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_textio_test::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
ENDLIST
LIST "BFMA1i1lI::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
ENDLIST
LIST "coreparameters::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.vhd","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\test\user\testbench.vhd","FALSE","TRUE"
SUBBLOCK "bfm_APb::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
SUBBLOCK "BFM_apbSLAve::COREAPB3_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\amba_bfm\bfm_apbslave.vhd","FALSE","TRUE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB::components","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd","FALSE","FALSE"
ENDLIST
LIST "ADC_SCALING::ADC_SCALING_LIB","component\Microsemi\SolutionCore\ADC_SCALING\4.2.0\Encrypted\adc_scaling.vhd","FALSE","FALSE"
ENDLIST
LIST "sinc3_filter::SINC3_FILTER_LIB","component\Microsemi\SolutionCore\SINC3_FILTER\4.2.0\Encrypted\sinc3_filter.vhd","FALSE","FALSE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
ENDLIST
LIST IOTabList
VALUE "constraint\io\MC_System_top.io.pdc"
ENDLIST
LIST FPTabList
ENDLIST
LIST TimingTabList
VALUE "constraint\MS_MC_System_top_compile.sdc"
ENDLIST
LIST FDCTabList
ENDLIST
