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    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    Reading constraint file: E:\Webrelease\RS\SK1ABLRS10_5_1\constraint\MS_MC_System_top_compile.sdc
    Linked File: MC_System_top_1_scck.rpt
    Printing clock  summary report in "E:\Webrelease\RS\SK1ABLRS10_5_1\synthesis\MC_System_top_1_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 121MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 121MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 121MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 121MB)

    @W:BN132 : foc_transforms.vhd(585) | Removing sequential instance Bldc_Axis_0.FOC_TRANSFORMS_0.CLARKE_INST.mul_b_to_mas_o_1[9],  because it is equivalent to instance Bldc_Axis_0.FOC_TRANSFORMS_0.CLARKE_INST.mul_b_to_mas_o_1[6]
    @W:BN132 : foc_transforms.vhd(585) | Removing sequential instance Bldc_Axis_0.FOC_TRANSFORMS_0.CLARKE_INST.mul_b_to_mas_o_1[6],  because it is equivalent to instance Bldc_Axis_0.FOC_TRANSFORMS_0.CLARKE_INST.mul_b_to_mas_o_1[0]
    @W:BN132 : foc_transforms.vhd(1140) | Removing sequential instance Bldc_Axis_0.FOC_TRANSFORMS_0.ICLARKE_INST.s_va[17:0],  because it is equivalent to instance Bldc_Axis_0.FOC_TRANSFORMS_0.ICLARKE_INST.add_c_to_mas_o_1[27:10]
    @W:BN132 : foc_transforms.vhd(1140) | Removing sequential instance Bldc_Axis_0.FOC_TRANSFORMS_0.ICLARKE_INST.mul_b_to_mas_o_1[9],  because it is equivalent to instance Bldc_Axis_0.FOC_TRANSFORMS_0.ICLARKE_INST.mul_b_to_mas_o_1[5]
    @W:BN132 : foc_transforms.vhd(1140) | Removing sequential instance Bldc_Axis_0.FOC_TRANSFORMS_0.ICLARKE_INST.mul_b_to_mas_o_1[5],  because it is equivalent to instance Bldc_Axis_0.FOC_TRANSFORMS_0.ICLARKE_INST.mul_b_to_mas_o_1[1]
    @W:BN132 : coreresetp.vhd(1059) | Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int
    @N:BN362 : apb3_if.vhd(556) | Removing sequential instance Ls_by_Ts_pu_o[17:0] of view:PrimLib.dffre(prim) in hierarchy view:work.apb3_if_32_12_12_6_18(apb3_if) because there are no references to its outputs
    @N:BN362 : apb3_if.vhd(556) | Removing sequential instance Rs_pu_o[17:0] of view:PrimLib.dffre(prim) in hierarchy view:work.apb3_if_32_12_12_6_18(apb3_if) because there are no references to its outputs
    @N:BN362 : apb3_if.vhd(556) | Removing sequential instance angle_kp_o[17:0] of view:PrimLib.dffre(prim) in hierarchy view:work.apb3_if_32_12_12_6_18(apb3_if) because there are no references to its outputs
    @N:BN362 : apb3_if.vhd(556) | Removing sequential instance angle_ki_o[17:0] of view:PrimLib.dffre(prim) in hierarchy view:work.apb3_if_32_12_12_6_18(apb3_if) because there are no references to its outputs
    @N:BN362 : apb3_if.vhd(556) | Removing sequential instance filter_factor_bemf_o[3:0] of view:PrimLib.dffre(prim) in hierarchy view:work.apb3_if_32_12_12_6_18(apb3_if) because there are no references to its outputs
    @N:BN362 : apb3_if.vhd(556) | Removing sequential instance filter_factor_omega_o[3:0] of view:PrimLib.dffre(prim) in hierarchy view:work.apb3_if_32_12_12_6_18(apb3_if) because there are no references to its outputs
    @N:BN362 : pwm3ph.vhd(183) | Removing sequential instance PWM_AL_o of view:PrimLib.dffre(prim) in hierarchy view:work.PWM3PH_18(pwm3ph) because there are no references to its outputs
    @N:BN362 : pwm3ph.vhd(183) | Removing sequential instance PWM_BL_o of view:PrimLib.dffre(prim) in hierarchy view:work.PWM3PH_18(pwm3ph) because there are no references to its outputs
    @N:BN362 : pwm3ph.vhd(183) | Removing sequential instance PWM_CL_o of view:PrimLib.dffre(prim) in hierarchy view:work.PWM3PH_18(pwm3ph) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance sdif0_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance sdif1_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance sdif2_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance sdif3_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_work_mc_system_top_rtl_0layer0(rtl) because there are no references to its outputs
    syn_allowed_resources : blockrams=21,dsps=22  set on top level netlist MC_System_top

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 147MB peak: 149MB)

    @S |Clock Summary
    *****************

    Start                                                           Requested     Requested     Clock        Clock
    Clock                                                           Frequency     Period        Type         Group
    ----------------------------------------------------------------------------------------------------------------------------
    MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT     50.0 MHz      20.000        declared     default_clkgroup
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_2
    MC_System_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_1
    System                                                          100.0 MHz     10.000        system       system_clkgroup
    ============================================================================================================================

    @W:MT530 : adc_interface.vhd(569) | Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 2266 sequential elements including Bldc_Axis_0.adc_interface_0.s_channel_cnt[2:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : coreresetp.vhd(894) | Found inferred clock MC_System_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including MC_System_0.MC_System_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : sinc3_filter.v(138) | Found inferred clock MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock which controls 438 sequential elements including Bldc_Axis_0.sinc3_filter_1.s_diff2_dec[23:0]. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\Webrelease\RS\SK1ABLRS10_5_1\synthesis\MC_System_top_1.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 149MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Aug 25 10:43:17 2016

    ###########################################################]

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