--=================================================================================================
-- File Name                           : sinc3_filter.vhd

-- Description                         : This module implements the function of a sinc3 filter

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2016 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

--=================================================================================================
-- sinc3_filter entity declaration
--=================================================================================================
ENTITY sinc3_filter IS

GENERIC(
   
    -- Specifies width of all input and output ports
    g_STD_IO_WIDTH                     : INTEGER := 18;
	
	-- Decimation factor
	g_DECIMATION_FACTOR				   : INTEGER  RANGE 2 TO 20 := 6;
    
    --Polarity
    g_BIPOLAR                          : INTEGER RANGE 0 TO 1 := 1;
    
    --Negate Output
    g_NEGATE_OUTPUT                    : INTEGER RANGE 0 TO 1 := 1
);

PORT (
--Port list
    -- system reset
    reset_i                            : IN  STD_LOGIC;

    -- ADC clock
    clk_adc_i                          : IN  STD_LOGIC;

    -- ADC data bit stream
    data_adc_i                     	   : IN  STD_LOGIC;

    --Hold input
    hold_i                     	       : IN  STD_LOGIC;

    -- Filtered data output
    data_o                             : OUT STD_LOGIC_VECTOR(g_STD_IO_WIDTH-1 DOWNTO 0);

    -- Decimated clock
    clk_dec_o                          : OUT STD_LOGIC

);
END sinc3_filter;

--=================================================================================================
-- sinc3_filter architecture body
--=================================================================================================
ARCHITECTURE sinc3_filter OF sinc3_filter IS
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