@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLRS10\LiberoProject\SK1ABLRS10_5_1\synthesis\syntmp\gentmp1860a02424":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a02424":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
@W: CD796 :"syng0a02424":92:11:92:18|Bit 9 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a02424":92:11:92:18|Bit 10 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a02424":92:11:92:18|Bit 11 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a02424":92:11:92:18|Bit 12 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a02424":92:11:92:18|Bit 13 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a02424":92:11:92:18|Bit 14 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a02424":92:11:92:18|Bit 15 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a02424":92:11:92:18|Bit 16 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a02424":92:11:92:18|Bit 17 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@N: CD630 :"syng0a02424":6:7:6:16|Synthesizing work.eq_element.eqn.
@W: CD280 :"syng0a02424":15:11:15:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0a02424":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
Post processing for work.muxcy_l.syn_black_box
Post processing for work.eq_element.eqn
Post processing for work.cmp_eq.cell_level
Post processing for work.top.gen
