sourcing E:\Microsemi\Libero_v11.7\Synplify\lib\message_override.tcl

Starting:    E:\Microsemi\Libero_v11.7\Synplify\bin64\mbin\synplify.exe
Install:     E:\Microsemi\Libero_v11.7\Synplify
Hostname:    W764-MURALIA
Date:        Thu Aug 25 16:37:00 2016
Version:     J-2015.03M-SP1-2

Arguments:   -product synplify_pro MC_System_top_syn.prj
ProductType: synplify_pro

License checkout: synplifypro_actel
License: synplifypro_actel from server denzil 
Licensed Vendor: actel
License Option: actel_oem


auto_infer_blackbox is not supported in current product.
log file: "E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\MC_System_top_1.srr"
Running: synthesis in foreground

Running MC_System_top_syn|synthesis

Running: compile (Compile) on MC_System_top_syn|synthesis

Running: compile_flow (Compile Process) on MC_System_top_syn|synthesis

Running: compiler (Compile Input) on MC_System_top_syn|synthesis

compiler Completed
Return Code: 0
Run Time:0h:00m:01s

Running: multi_srs_gen (Multi-srs Generator) on MC_System_top_syn|synthesis
Copied E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\synwork\MC_System_top_1_comp.srs to E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\synwork\MC_System_top_1_s.srs
Up-To-Date: multi_srs_gen. No run necessary
Complete: Compile Process on MC_System_top_syn|synthesis

Running: premap (Pre-mapping) on MC_System_top_syn|synthesis
Copied E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\MC_System_top_1.sap to E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\synwork\MC_System_top_1_s.sap
Copied E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\MC_System_top_1.fse to E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\synwork\MC_System_top_1_s.fse

premap Completed with warnings
Return Code: 1
Run Time:0h:00m:02s
Complete: Compile on MC_System_top_syn|synthesis

Running: map (Map) on MC_System_top_syn|synthesis

Running: fpga_mapper (Map & Optimize) on MC_System_top_syn|synthesis
Copied E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\synwork\MC_System_top_1_m.srm to E:\LX77\VHDL\SK1ABLRS10_5_1\synthesis\MC_System_top_1.srm

fpga_mapper Completed with warnings
Return Code: 1
Run Time:0h:00m:21s
Complete: Map on MC_System_top_syn|synthesis
Complete: Logic Synthesis on MC_System_top_syn|synthesis
exit status=0
License checkin: synplifypro_actel
