--=================================================================================================
-- File Name                           : PWM3ph.vhd

-- Description                         : This module implements a 3-phase PWM generator

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2016 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
--=================================================================================================
-- PWM3PH entity declaration
--=================================================================================================
ENTITY PWM3PH IS
PORT (
-- Port List
    -- System reset
    reset_i                            : IN STD_LOGIC;

    -- System clock
    sys_clk_i                          : IN STD_LOGIC;

    -- Control input specifies enabling of PWM outputs
    en_pwm_i                           : IN STD_LOGIC;
    
    -- Dual trigger enable
    en_dual_trig_i                     : IN STD_LOGIC;

    -- Valpha input from PWM Scaling
    va_i              	   		   	   : IN  STD_LOGIC_VECTOR (17 downto 0);

    -- Vbeta input from PWM Scaling
    vb_i                	   		   : IN  STD_LOGIC_VECTOR (17 downto 0);

	-- Vbeta input from PWM Scaling
    vc_i                	   		   : IN  STD_LOGIC_VECTOR (17 downto 0);

	-- PWM period
    pwm_period_i               	   	   : IN  STD_LOGIC_VECTOR (17 downto 0);

    -- Dead time between to switch and bottom switch in terms of system clock
    dead_time_i           	   		   : IN  STD_LOGIC_VECTOR (17 downto 0);

	-- Dead time between to switch and bottom switch in terms of system clock
    delay_time_i           	   		   : IN  STD_LOGIC_VECTOR (17 downto 0);

	-- output specifies execution of scaling operation
    midmatch_o                         : OUT STD_LOGIC;

	-- PWM signal for U phase top switch
    PWM_AH_o                           : OUT STD_LOGIC;

    -- PWM signal for V phase top switch
    PWM_BH_o                           : OUT STD_LOGIC;

    -- PWM signal for W phase top switch
    PWM_CH_o                           : OUT STD_LOGIC;

	-- PWM signal for U phase bottom switch
    PWM_AL_o                           : OUT STD_LOGIC;

	-- PWM signal for V phase bottom switch
    PWM_BL_o                           : OUT STD_LOGIC;

	-- PWM signal for W phase bottom switch
    PWM_CL_o                           : OUT STD_LOGIC

);
END PWM3PH;
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