--=================================================================================================
-- File Name                           : resolver_interface.vhd

-- Description                         : This module computes theta from resolver signal inputs

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2015 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

--=================================================================================================
-- RESOLVER_INTERFACE entity declaration
--=================================================================================================
ENTITY RESOLVER_INTERFACE IS

GENERIC(
	
	-- Specifies the number of multi-cycle path delays introduced
    g_NO_MCYCLE_PATH                   : INTEGER RANGE 0 TO 4 := 2
	
);

PORT (
--Port list
    -- system reset
    reset_i                            : IN  STD_LOGIC;

    -- System clock
    sys_clk_i                          : IN  STD_LOGIC;
	
	-- Clears all the buffers
	clear_buffer_i                     : IN STD_LOGIC;
	
	-- Angle calibration input
    calib_angle_i                      : IN  STD_LOGIC;

    -- Cos measurement input
    cos_i                     	   	   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	
	-- Sine measurement input
    sin_i                     	   	   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	
	-- Pole pair ratio
    pp_ratio_i                 	   	   : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
	
	-- PLL PI Kp value
    pll_pi_kp_i                        : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);

    -- PLL PI Ki value
    pll_pi_ki_i                        : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	
	-- DC filter factor to extract DC component
    dc_filter_factor_i                 : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
	
	-- AC filter factor to remove high frequency component
    ac_filter_factor_i                 : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
	
	-- Theta factor for speed computation
    theta_factor_i                 	   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	
	-- Coil frequency
    hf_sig_period_i                    : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);

    -- High frequency signal for resolver driver
    hf_signal_o                        : OUT STD_LOGIC;
	
	-- Angle output
    theta_o                            : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	
	-- Speed output
    speed_o                            : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
);
END RESOLVER_INTERFACE;

--=================================================================================================
-- resolver_interface architecture body
--=================================================================================================
ARCHITECTURE resolver_interface OF RESOLVER_INTERFACE IS
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