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<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP2 (Version 11.8.2.4)</text>
<text>Date: Wed Nov 29 15:56:53 2017
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2S010</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
<row>
 <cell>Restrict SPI Pins</cell>
 <cell>No</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>MC_System_top</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>Verilog</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLRS10\LiberoProject\SK1ABLRS10_5_1\synthesis\MC_System_top_1.vm</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLRS10\LiberoProject\SK1ABLRS10_5_1\constraint\MS_MC_System_top_compile.sdc</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLRS10\LiberoProject\SK1ABLRS10_5_1\constraint\io\MC_System_top.io.pdc</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Enable Single Event Transient mitigation</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Enable Design Separation Methodology</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>4LUT</cell>
 <cell>5321</cell>
 <cell>12084</cell>
 <cell>44.03</cell>
</row>
<row>
 <cell>DFF</cell>
 <cell>3721</cell>
 <cell>12084</cell>
 <cell>30.79</cell>
</row>
<row>
 <cell>I/O Register</cell>
 <cell>0</cell>
 <cell>693</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>User I/O</cell>
 <cell>28</cell>
 <cell>231</cell>
 <cell>12.12</cell>
</row>
<row>
 <cell>-- Single-ended I/O</cell>
 <cell>28</cell>
 <cell>231</cell>
 <cell>12.12</cell>
</row>
<row>
 <cell>-- Differential I/O Pairs</cell>
 <cell>0</cell>
 <cell>115</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>22</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>0</cell>
 <cell>21</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>7</cell>
 <cell>22</cell>
 <cell>31.82</cell>
</row>
<row>
 <cell>Chip Globals</cell>
 <cell>3</cell>
 <cell>8</cell>
 <cell>37.50</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>1</cell>
 <cell>2</cell>
 <cell>50.00</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Detailed Logic Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>4LUT</cell>
 <cell>DFF</cell>
</header>
<row>
 <cell>Fabric Logic</cell>
 <cell>5069</cell>
 <cell>3469</cell>
</row>
<row>
 <cell>RAM64x18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM1K18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>MACC Interface Logic</cell>
 <cell>252</cell>
 <cell>252</cell>
</row>
<row>
 <cell>Total Used</cell>
 <cell>5321</cell>
 <cell>3721</cell>
</row>
</table>
<section><name>MSS Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Cortex-M3*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eNVM (256KB)*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eSRAM*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>TIMER*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>CAN</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>SPI</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>I2C</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>UART</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>USB</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MAC</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MDDR</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>HPDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>PDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
</table>
<text>* These resources are always marked as used when you are using the MSS</text>
<text></text>
<section><name>Detailed Carry Chains Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>2</cell>
 <cell>73</cell>
</row>
<row>
 <cell>6</cell>
 <cell>2</cell>
</row>
<row>
 <cell>10</cell>
 <cell>3</cell>
</row>
<row>
 <cell>14</cell>
 <cell>1</cell>
</row>
<row>
 <cell>15</cell>
 <cell>2</cell>
</row>
<row>
 <cell>18</cell>
 <cell>19</cell>
</row>
<row>
 <cell>19</cell>
 <cell>39</cell>
</row>
<row>
 <cell>20</cell>
 <cell>5</cell>
</row>
<row>
 <cell>24</cell>
 <cell>12</cell>
</row>
<row>
 <cell>31</cell>
 <cell>2</cell>
</row>
<row>
 <cell>34</cell>
 <cell>8</cell>
</row>
<row>
 <cell>35</cell>
 <cell>2</cell>
</row>
<row>
 <cell>36</cell>
 <cell>2</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>170</cell>
</row>
</table>
<section><name>Detailed MACC Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>1</cell>
 <cell>7</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>7</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>6</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>14</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>8</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vddi</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 6</cell>
 <cell> 14</cell>
 <cell> 8</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 28</cell>
 <cell>100.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>3482</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MC_System_0_FIC_0_LOCK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MC_System_0/MC_System_sb_0/CCC_0/CCC_INST_RNI2QPF/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>3048</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MC_System_0_FIC_0_CLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>437</cell>
 <cell>INT_NET</cell>
 <cell>Net   : GPIO_43_c</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>287</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/SEQ_CONTROLLER_0_motor_stopped_o</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_22/ADC_START_PROC.un103_s_state_i_a3_0_a2_i</cell>
</row>
<row>
 <cell>138</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/MSC_i_26/MSC_net_420</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_26/s_clk_dec_re</cell>
</row>
<row>
 <cell>138</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/MSC_i_33/MSC_net_420</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_33/s_clk_dec_re</cell>
</row>
<row>
 <cell>130</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/MSC_i_29/MSC_net_537</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_29/MSC_i_32/en_o</cell>
</row>
<row>
 <cell>115</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/apb3_if_0_dc_filter_factor_o[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/apb3_if_0/dc_filter_factor_o[3]</cell>
</row>
<row>
 <cell>114</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/apb3_if_0_dc_filter_factor_o[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/apb3_if_0/dc_filter_factor_o[2]</cell>
</row>
<row>
 <cell>108</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/apb3_if_0_ac_filter_factor_o[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/apb3_if_0/ac_filter_factor_o[3]</cell>
</row>
<row>
 <cell>107</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/apb3_if_0_ac_filter_factor_o[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/apb3_if_0/ac_filter_factor_o[2]</cell>
</row>
<row>
 <cell>105</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MC_System_0_AMBA_SLAVE_0_PADDR[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST</cell>
</row>
<row>
 <cell>104</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/MSC_i_29/PI_SCHEDULER_INST.s_pi_sel[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_29/MSC_i_32/s_pi_sel_Z[0]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>287</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/SEQ_CONTROLLER_0_motor_stopped_o</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_22/ADC_START_PROC.un103_s_state_i_a3_0_a2_i</cell>
</row>
<row>
 <cell>138</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/MSC_i_26/MSC_net_420</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_26/s_clk_dec_re</cell>
</row>
<row>
 <cell>138</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/MSC_i_33/MSC_net_420</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_33/s_clk_dec_re</cell>
</row>
<row>
 <cell>130</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/MSC_i_29/MSC_net_537</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_29/MSC_i_32/en_o</cell>
</row>
<row>
 <cell>115</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/apb3_if_0_dc_filter_factor_o[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/apb3_if_0/dc_filter_factor_o[3]</cell>
</row>
<row>
 <cell>114</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/apb3_if_0_dc_filter_factor_o[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/apb3_if_0/dc_filter_factor_o[2]</cell>
</row>
<row>
 <cell>108</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/apb3_if_0_ac_filter_factor_o[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/apb3_if_0/ac_filter_factor_o[3]</cell>
</row>
<row>
 <cell>107</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/apb3_if_0_ac_filter_factor_o[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/apb3_if_0/ac_filter_factor_o[2]</cell>
</row>
<row>
 <cell>105</cell>
 <cell>INT_NET</cell>
 <cell>Net   : MC_System_0_AMBA_SLAVE_0_PADDR[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST</cell>
</row>
<row>
 <cell>104</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Bldc_Axis_0/MSC_i_29/PI_SCHEDULER_INST.s_pi_sel[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Bldc_Axis_0/MSC_i_29/MSC_i_32/s_pi_sel_Z[0]</cell>
</row>
</table>
</doc>
