<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.8.2.4</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP2 (Version 11.8.2.4)</text>
<text>Date: Wed Nov 29 16:03:20 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>MC_System_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S010</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>5.267</cell>
 <cell>189.861</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>-2.093</cell>
 <cell>3.564</cell>
 <cell>7.601</cell>
 <cell>8.311</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>2.293</cell>
 <cell>436.110</cell>
 <cell>40.000</cell>
 <cell>25.000</cell>
 <cell>-0.631</cell>
 <cell>2.272</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>8.429</cell>
 <cell>5.976</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Bldc_Axis_0/MSC_i_23/MSC_i_24/theta_scl_buff_o[14]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_23/s_addc_input[27]:D</cell>
 <cell>0.438</cell>
 <cell>0.424</cell>
 <cell>5.455</cell>
 <cell>5.031</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_5/pll_pi_acc_in_o[36]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_3/s_acc_in[36]:D</cell>
 <cell>0.457</cell>
 <cell>0.429</cell>
 <cell>5.466</cell>
 <cell>5.037</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Bldc_Axis_0/apb3_if_0/olmng_theta_factor_o[11]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_23/s_mult1_input[11]:D</cell>
 <cell>0.444</cell>
 <cell>0.429</cell>
 <cell>5.451</cell>
 <cell>5.022</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_5/pll_pi_acc_in_o[26]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_3/s_acc_in[26]:D</cell>
 <cell>0.457</cell>
 <cell>0.429</cell>
 <cell>5.461</cell>
 <cell>5.032</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_5/pll_pi_acc_in_o[14]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_3/s_acc_in[14]:D</cell>
 <cell>0.457</cell>
 <cell>0.429</cell>
 <cell>5.467</cell>
 <cell>5.038</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Bldc_Axis_0/MSC_i_23/MSC_i_24/theta_scl_buff_o[14]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Bldc_Axis_0/MSC_i_23/s_addc_input[27]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.455</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.031</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.424</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.654</cell>
 <cell>3.654</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>3.845</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.160</cell>
 <cell>4.005</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.272</cell>
 <cell>4.277</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>4.520</cell>
 <cell>86</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_23/MSC_i_24/theta_scl_buff_o[14]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.497</cell>
 <cell>5.017</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_23/MSC_i_24/theta_scl_buff_o[14]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.089</cell>
 <cell>5.106</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_23/s_addc_input[27]:D</cell>
 <cell>net</cell>
 <cell>Bldc_Axis_0/MSC_i_23/MSC_net_226</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.349</cell>
 <cell>5.455</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.455</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.654</cell>
 <cell>3.654</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>3.845</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.160</cell>
 <cell>4.005</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.272</cell>
 <cell>4.277</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>4.520</cell>
 <cell>86</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_23/s_addc_input[27]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.511</cell>
 <cell>5.031</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_23/s_addc_input[27]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.031</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.031</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>A0_ADC_SDI_I</cell>
 <cell>Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>1.600</cell>
 <cell>1.390</cell>
 <cell>6.554</cell>
 <cell>5.164</cell>
 <cell>-0.026</cell>
 <cell>3.564</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: A0_ADC_SDI_I</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.554</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.164</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.390</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.654</cell>
 <cell>3.654</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>A0_ADC_SDI_I</cell>
 <cell>Input Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.300</cell>
 <cell>4.954</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>A0_ADC_SDI_I</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.954</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_ADC_SDI_I_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.235</cell>
 <cell>6.189</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>net</cell>
 <cell>A0_ADC_SDI_I_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>6.554</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.554</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.767</cell>
 <cell>3.767</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>3.964</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>4.130</cell>
 <cell>17</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB20:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>4.420</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB20:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.670</cell>
 <cell>83</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB20_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.520</cell>
 <cell>5.190</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF</cell>
 <cell>+</cell>
 <cell>-0.026</cell>
 <cell>5.164</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.164</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Bldc_Axis_0/MSC_i_36/PWM_CH_o_Z:CLK</cell>
 <cell>A0_PWM_WH_O</cell>
 <cell>2.570</cell>
 <cell>4.247</cell>
 <cell>7.601</cell>
 <cell>3.354</cell>
 <cell>7.601</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Bldc_Axis_0/MSC_i_36/PWM_BH_o_Z:CLK</cell>
 <cell>A0_PWM_VH_O</cell>
 <cell>2.614</cell>
 <cell>4.290</cell>
 <cell>7.644</cell>
 <cell>3.354</cell>
 <cell>7.644</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Bldc_Axis_0/MSC_i_36/PWM_AH_o_Z:CLK</cell>
 <cell>A0_PWM_UH_O</cell>
 <cell>2.667</cell>
 <cell>4.346</cell>
 <cell>7.700</cell>
 <cell>3.354</cell>
 <cell>7.700</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdo:CLK</cell>
 <cell>A0_ADC_SDO_O</cell>
 <cell>3.019</cell>
 <cell>4.700</cell>
 <cell>8.054</cell>
 <cell>3.354</cell>
 <cell>8.054</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Bldc_Axis_0/adc_interface_795x_0/spi_engine_inst/s_cs_n:CLK</cell>
 <cell>A0_ADC_CS_O</cell>
 <cell>4.074</cell>
 <cell>5.728</cell>
 <cell>9.082</cell>
 <cell>3.354</cell>
 <cell>9.082</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Bldc_Axis_0/MSC_i_36/PWM_CH_o_Z:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: A0_PWM_WH_O</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.601</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.354</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.247</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.654</cell>
 <cell>3.654</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>3.845</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.160</cell>
 <cell>4.005</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.275</cell>
 <cell>4.280</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>4.523</cell>
 <cell>142</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_36/PWM_CH_o_Z:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.508</cell>
 <cell>5.031</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_36/PWM_CH_o_Z:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOEFF</cell>
 <cell>+</cell>
 <cell>0.184</cell>
 <cell>5.215</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_PWM_WH_O_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>A0_PWM_WH_O_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>5.317</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_PWM_WH_O_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.284</cell>
 <cell>7.601</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_PWM_WH_O</cell>
 <cell>net</cell>
 <cell>A0_PWM_WH_O</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.601</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.601</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.654</cell>
 <cell>3.654</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>A0_PWM_WH_O</cell>
 <cell>Output Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell>0.300</cell>
 <cell>3.354</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.354</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_diff3[14]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/s_filter_incr[24]:D</cell>
 <cell>0.877</cell>
 <cell>1.041</cell>
 <cell>6.088</cell>
 <cell>5.047</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_diff3[6]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_0/s_sin_ac[0]:D</cell>
 <cell>0.870</cell>
 <cell>1.078</cell>
 <cell>6.081</cell>
 <cell>5.003</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_diff3[10]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/s_filter_incr[20]:D</cell>
 <cell>0.921</cell>
 <cell>1.085</cell>
 <cell>6.133</cell>
 <cell>5.048</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_diff3[8]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/s_filter_incr[18]:D</cell>
 <cell>0.963</cell>
 <cell>1.128</cell>
 <cell>6.175</cell>
 <cell>5.047</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_diff3[11]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_1/s_filter_incr[21]:D</cell>
 <cell>1.004</cell>
 <cell>1.133</cell>
 <cell>6.184</cell>
 <cell>5.051</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Bldc_Axis_0/MSC_i_33/s_diff3[14]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Bldc_Axis_0/MSC_i_0/MSC_i_2/s_filter_incr[24]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.088</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.047</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.041</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.847</cell>
 <cell>3.847</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.038</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.161</cell>
 <cell>4.199</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.274</cell>
 <cell>4.473</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB4:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>4.716</cell>
 <cell>30</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_33/s_diff3[14]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB4_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.495</cell>
 <cell>5.211</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_33/s_diff3[14]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.084</cell>
 <cell>5.295</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/FILTER_FSM_PROC.s_filter_incr_1_cry_24:A</cell>
 <cell>net</cell>
 <cell>Bldc_Axis_0/SINC3_FILTER_0_data_o[8]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.530</cell>
 <cell>5.825</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/FILTER_FSM_PROC.s_filter_incr_1_cry_24:S</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>6.015</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/s_filter_incr[24]:D</cell>
 <cell>net</cell>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/MSC_net_191</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.073</cell>
 <cell>6.088</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.088</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.654</cell>
 <cell>3.654</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>3.845</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.161</cell>
 <cell>4.006</cell>
 <cell>17</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.279</cell>
 <cell>4.285</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>4.528</cell>
 <cell>48</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/s_filter_incr[24]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB16_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.519</cell>
 <cell>5.047</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_0/MSC_i_2/s_filter_incr[24]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.047</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.047</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_diff2[10]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_diff2_dec[10]:D</cell>
 <cell>0.481</cell>
 <cell>0.454</cell>
 <cell>5.696</cell>
 <cell>5.242</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_diff1[20]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_diff1_dec[20]:D</cell>
 <cell>0.477</cell>
 <cell>0.474</cell>
 <cell>5.688</cell>
 <cell>5.214</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_clk_dec:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_clk_dec_dly:D</cell>
 <cell>0.505</cell>
 <cell>0.481</cell>
 <cell>5.698</cell>
 <cell>5.217</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_clk_dec:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_clk_dec_dly:D</cell>
 <cell>0.505</cell>
 <cell>0.490</cell>
 <cell>5.703</cell>
 <cell>5.213</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_dec_count[5]:CLK</cell>
 <cell>Bldc_Axis_0/MSC_i_33/s_clk_dec:D</cell>
 <cell>0.505</cell>
 <cell>0.499</cell>
 <cell>5.707</cell>
 <cell>5.208</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Bldc_Axis_0/MSC_i_26/s_diff2[10]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Bldc_Axis_0/MSC_i_26/s_diff2_dec[10]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.696</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.242</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.454</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.847</cell>
 <cell>3.847</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.038</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.161</cell>
 <cell>4.199</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB8:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.277</cell>
 <cell>4.476</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB8:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>4.719</cell>
 <cell>72</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_26/s_diff2[10]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB8_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.496</cell>
 <cell>5.215</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_26/s_diff2[10]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.084</cell>
 <cell>5.299</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_26/s_diff2_dec[10]:D</cell>
 <cell>net</cell>
 <cell>Bldc_Axis_0/MSC_i_26/MSC_net_210</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.397</cell>
 <cell>5.696</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.696</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.847</cell>
 <cell>3.847</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.038</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.161</cell>
 <cell>4.199</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB8:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.277</cell>
 <cell>4.476</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB8:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>4.719</cell>
 <cell>72</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_26/s_diff2_dec[10]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB8_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.523</cell>
 <cell>5.242</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_26/s_diff2_dec[10]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.242</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.242</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>TD</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_acc1[0]:EN</cell>
 <cell>3.100</cell>
 <cell>2.875</cell>
 <cell>8.247</cell>
 <cell>5.372</cell>
 <cell>0.000</cell>
 <cell>2.272</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>TD</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_acc1[13]:EN</cell>
 <cell>3.400</cell>
 <cell>3.160</cell>
 <cell>8.547</cell>
 <cell>5.387</cell>
 <cell>0.000</cell>
 <cell>1.987</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>TD</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_acc1[19]:EN</cell>
 <cell>3.400</cell>
 <cell>3.160</cell>
 <cell>8.547</cell>
 <cell>5.387</cell>
 <cell>0.000</cell>
 <cell>1.987</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>TD</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_acc1[17]:EN</cell>
 <cell>3.400</cell>
 <cell>3.160</cell>
 <cell>8.547</cell>
 <cell>5.387</cell>
 <cell>0.000</cell>
 <cell>1.987</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>TD</cell>
 <cell>Bldc_Axis_0/MSC_i_26/s_acc1[23]:EN</cell>
 <cell>3.400</cell>
 <cell>3.160</cell>
 <cell>8.547</cell>
 <cell>5.387</cell>
 <cell>0.000</cell>
 <cell>1.987</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: TD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Bldc_Axis_0/MSC_i_26/s_acc1[0]:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.247</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.372</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.875</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.847</cell>
 <cell>3.847</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>TD</cell>
 <cell>Input Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.300</cell>
 <cell>5.147</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>TD_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>TD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.147</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>TD_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.238</cell>
 <cell>6.385</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>TD_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>TD_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.042</cell>
 <cell>6.427</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>TD_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.091</cell>
 <cell>6.518</cell>
 <cell>24</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_26/s_acc1[0]:EN</cell>
 <cell>net</cell>
 <cell>TD_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.729</cell>
 <cell>8.247</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.247</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.966</cell>
 <cell>3.966</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>4.163</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>4.329</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB7:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.286</cell>
 <cell>4.615</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB7:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>4.866</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_26/s_acc1[0]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB7_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.506</cell>
 <cell>5.372</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Bldc_Axis_0/MSC_i_26/s_acc1[0]:EN</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.372</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.372</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:RCOSC_25_50MHZ</cell>
 <cell>GPIO_43</cell>
 <cell>6.463</cell>
 <cell>4.882</cell>
 <cell>8.429</cell>
 <cell>3.547</cell>
 <cell></cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:RCOSC_25_50MHZ</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: GPIO_43</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.429</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.547</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.882</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:RCOSC_25_50MHZ</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.966</cell>
 <cell>1.966</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CCC_IP</cell>
 <cell>+</cell>
 <cell>1.881</cell>
 <cell>3.847</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.038</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.160</cell>
 <cell>4.198</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.272</cell>
 <cell>4.470</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>4.713</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_43_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL2_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.675</cell>
 <cell>5.388</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_43_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.180</cell>
 <cell>5.568</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_43_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>GPIO_43_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.577</cell>
 <cell>6.145</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_43_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.284</cell>
 <cell>8.429</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_43</cell>
 <cell>net</cell>
 <cell>GPIO_43</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>8.429</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.429</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.847</cell>
 <cell>3.847</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>GPIO_43</cell>
 <cell>Output Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell>0.300</cell>
 <cell>3.547</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.547</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
