

@S |##### START OF TIMING REPORT #####[
# Timing Report written on Mon Nov 21 17:16:08 2016
#


Top view:               MC_System_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    E:\SVN\MotorControl\Development\MCSK\SK1ABLRS10\SK1ABLRS10_5_1\constraint\MS_MC_System_top_compile.sdc
                       
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: -0.673

                                                   Requested     Estimated      Requested     Estimated               Clock        Clock              
Starting Clock                                     Frequency     Frequency      Period        Period        Slack     Type         Group              
------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     111.1 MHz      10.000        9.003         0.997     inferred     Inferred_clkgroup_0
MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     100.0 MHz     195.4 MHz      10.000        5.117         2.442     inferred     Inferred_clkgroup_1
System                                             100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup    
======================================================================================================================================================



Clock Relationships
*******************

Clocks                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                        Ending                                          |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                          System                                          |  0.000       0.680   |  No paths    -      |  No paths    -      |  No paths    -    
System                                          MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  0.000       1.496   |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  0.000       -0.673  |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  0.000       0.568   |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  |  0.000       0.378   |  0.000       0.378  |  No paths    -      |  5.000       5.419
=======================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                            Starting                                                                              Arrival           
Instance                                    Reference                                          Type     Pin     Net               Time        Slack 
                                            Clock                                                                                                   
----------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[0]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[1]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[1]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[2]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[2]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[3]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[3]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[4]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[4]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[5]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[5]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[6]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[6]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[7]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[7]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[8]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[8]     0.053       -0.673
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[9]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       s_mult0_in[9]     0.053       -0.673
====================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                                       Starting                                                                            Required           
Instance                                                                                                               Reference                                          Type     Pin      Net            Time         Slack 
                                                                                                                       Clock                                                                                                  
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[0]     mul_a_i[0]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[1]     mul_a_i[1]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[2]     mul_a_i[2]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[3]     mul_a_i[3]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[4]     mul_a_i[4]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[5]     mul_a_i[5]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[6]     mul_a_i[6]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[7]     mul_a_i[7]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[8]     mul_a_i[8]     1.406        -0.673
Bldc_Axis_0.RESOLVER_INTERFACE_0.PLL_THETA_INST.PLL_THETA_MAS_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[28:0]     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MACC     A[9]     mul_a_i[9]     1.406        -0.673
==============================================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[0] / Q
    Ending point:                            Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[0]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK[0]

Instance / Net                                                                                               Pin      Pin               Arrival     No. of    
Name                                                                                                Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[0]                                                             SLE      Q        Out     0.053     0.053       -         
s_mult0_in[0]                                                                                       Net      -        -       0.680     -           1         
Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[0]     In      -         0.733       -         
==============================================================================================================================================================


Path information for path number 2: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[1] / Q
    Ending point:                            Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[1]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK[0]

Instance / Net                                                                                               Pin      Pin               Arrival     No. of    
Name                                                                                                Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[1]                                                             SLE      Q        Out     0.053     0.053       -         
s_mult0_in[1]                                                                                       Net      -        -       0.680     -           1         
Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[1]     In      -         0.733       -         
==============================================================================================================================================================


Path information for path number 3: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[2] / Q
    Ending point:                            Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[2]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK[0]

Instance / Net                                                                                               Pin      Pin               Arrival     No. of    
Name                                                                                                Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[2]                                                             SLE      Q        Out     0.053     0.053       -         
s_mult0_in[2]                                                                                       Net      -        -       0.680     -           1         
Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[2]     In      -         0.733       -         
==============================================================================================================================================================


Path information for path number 4: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[3] / Q
    Ending point:                            Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[3]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK[0]

Instance / Net                                                                                               Pin      Pin               Arrival     No. of    
Name                                                                                                Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[3]                                                             SLE      Q        Out     0.053     0.053       -         
s_mult0_in[3]                                                                                       Net      -        -       0.680     -           1         
Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[3]     In      -         0.733       -         
==============================================================================================================================================================


Path information for path number 5: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[4] / Q
    Ending point:                            Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[4]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK[0]

Instance / Net                                                                                               Pin      Pin               Arrival     No. of    
Name                                                                                                Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.ADC_SCALING_0.s_mult0_in[4]                                                             SLE      Q        Out     0.053     0.053       -         
s_mult0_in[4]                                                                                       Net      -        -       0.680     -           1         
Bldc_Axis_0.ADC_SCALING_0.MAS_ADC_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[4]     In      -         0.733       -         
==============================================================================================================================================================




====================================
Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                              Starting                                                                               Arrival          
Instance                                      Reference                                          Type     Pin     Net                Time        Slack
                                              Clock                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.SINC3_FILTER_2.s_clk_dec          MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_clk_dec          0.053       0.378
Bldc_Axis_0.SINC3_FILTER_0.s_clk_dec          MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_clk_dec          0.053       0.378
Bldc_Axis_0.SINC3_FILTER_2.s_dec_count[5]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_dec_count[5]     0.053       0.378
Bldc_Axis_0.SINC3_FILTER_0.s_dec_count[5]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_dec_count[5]     0.053       0.378
Bldc_Axis_0.SINC3_FILTER_0.s_diff1[1]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_diff1[1]         0.053       0.378
Bldc_Axis_0.SINC3_FILTER_2.s_diff1[1]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_diff1[1]         0.053       0.378
Bldc_Axis_0.SINC3_FILTER_2.s_diff1[2]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_diff1[2]         0.053       0.378
Bldc_Axis_0.SINC3_FILTER_0.s_diff1[2]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_diff1[2]         0.053       0.378
Bldc_Axis_0.SINC3_FILTER_2.s_diff1[3]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_diff1[3]         0.053       0.378
Bldc_Axis_0.SINC3_FILTER_0.s_diff1[3]         MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_diff1[3]         0.053       0.378
======================================================================================================================================================


Ending Points with Worst Slack
******************************

                                              Starting                                                                               Required          
Instance                                      Reference                                          Type     Pin     Net                Time         Slack
                                              Clock                                                                                                    
-------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.SINC3_FILTER_0.s_clk_dec          MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_dec_count[5]     0.155        0.378
Bldc_Axis_0.SINC3_FILTER_2.s_clk_dec          MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_dec_count[5]     0.155        0.378
Bldc_Axis_0.SINC3_FILTER_2.s_clk_dec_dly      MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_clk_dec          0.155        0.378
Bldc_Axis_0.SINC3_FILTER_0.s_clk_dec_dly      MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_clk_dec          0.155        0.378
Bldc_Axis_0.SINC3_FILTER_0.s_diff1_dec[1]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_diff1[1]         0.155        0.378
Bldc_Axis_0.SINC3_FILTER_2.s_diff1_dec[1]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_diff1[1]         0.155        0.378
Bldc_Axis_0.SINC3_FILTER_0.s_diff1_dec[2]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_diff1[2]         0.155        0.378
Bldc_Axis_0.SINC3_FILTER_2.s_diff1_dec[2]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_diff1[2]         0.155        0.378
Bldc_Axis_0.SINC3_FILTER_2.s_diff1_dec[3]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_diff1[3]         0.155        0.378
Bldc_Axis_0.SINC3_FILTER_0.s_diff1_dec[3]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       s_diff1[3]         0.155        0.378
=======================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.533
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.155
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (non-critical) :                 0.378

    Number of logic level(s):                0
    Starting point:                          Bldc_Axis_0.SINC3_FILTER_2.s_clk_dec / Q
    Ending point:                            Bldc_Axis_0.SINC3_FILTER_2.s_clk_dec_dly / D
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock [falling] on pin CLK
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock [falling] on pin CLK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                         Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
Bldc_Axis_0.SINC3_FILTER_2.s_clk_dec         SLE      Q        Out     0.053     0.053       -         
s_clk_dec                                    Net      -        -       0.480     -           2         
Bldc_Axis_0.SINC3_FILTER_2.s_clk_dec_dly     SLE      D        In      -         0.533       -         
=======================================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                                                           Arrival          
Instance                                                 Reference     Type               Pin        Net                                                    Time        Slack
                                                         Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       0.680
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                System        CCC                LOCK       LOCK                                                   0.000       1.496
=============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                    Starting                                                                                         Required          
Instance                                                                            Reference     Type     Pin                Net                                                    Time         Slack
                                                                                    Clock                                                                                                              
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                                           System        CCC      RCOSC_25_50MHZ     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000        0.680
Bldc_Axis_0.RESOLVER_INTERFACE_0.s_trig_dly                                         System        SLE      EN                 reset_i                                                0.205        1.496
Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[0]     System        SLE      D                  N_650                                                  0.155        2.292
Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[1]     System        SLE      D                  N_651                                                  0.155        2.292
Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[2]     System        SLE      D                  N_652                                                  0.155        2.292
Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[3]     System        SLE      D                  N_653                                                  0.155        2.292
Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[4]     System        SLE      D                  N_654                                                  0.155        2.292
Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[5]     System        SLE      D                  N_655                                                  0.155        2.292
Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[6]     System        SLE      D                  N_656                                                  0.155        2.292
Bldc_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[7]     System        SLE      D                  N_657                                                  0.155        2.292
=======================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.680
    + Clock delay at starting point:         0.000 (ideal)
-0.000
    - Requested Period:                      0.000
    - Hold time:                             0.000
    - Clock delay at ending point:           0.000 (ideal)
0.000
    = Slack (non-critical) :                 0.680

    Number of logic level(s):                0
    Starting point:                          MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT
    Ending point:                            MC_System_0.MC_System_sb_0.CCC_0.CCC_INST / RCOSC_25_50MHZ
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                              Pin                Pin               Arrival     No. of    
Name                                                     Type               Name               Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     RCOSC_25_50MHZ     CLKOUT             Out     0.000     0.000       -         
FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC       Net                -                  -       0.680     -           1         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                CCC                RCOSC_25_50MHZ     In      -         0.680       -         
=======================================================================================================================================



##### END OF TIMING REPORT #####]

