# Wed Nov 29 15:53:56 2017

Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09M-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 146MB)

@W: BN114 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\component\work\mc_system_sb\mc_system_sb.vhd":681:0:681:11|Removing instance SYSRESET_POR (in view: work.MC_System_sb(rtl)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances.

Available hyper_sources - for debug and ip models
	None Found

@W: FA239 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|Found ROM .delname. (in view: work.MC_System_sb(rtl)) with 16 words by 2 bits.

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB)

@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\apb3_if.vhd":672:8:672:9|Removing sequential instance apb3_if_0.pwm_gain_val_o[0] (in view: work.Bldc_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
Encoding state machine state[0:5] (in view: work.adc_interface_795x(adc_interface))
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[15] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[14] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[13] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[12] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[11] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[10] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[9] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[8] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[7] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[6] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[5] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[4] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[3] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[2] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Removing instance Bldc_Axis_0.adc_interface_795x_0.s_channel_sel[1] because it is equivalent to instance Bldc_Axis_0.adc_interface_795x_0.s_channel_sel[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[0] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[1] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[2] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[3] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[4] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[5] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine s_state[0:3] (in view: adc_scaling_lib.ADC_SCALING(adc_scaling))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
Encoding state machine s_state[0:2] (in view: work.cordic_scale(cordic_scale))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:2] (in view: work.OLMNG(olmng))
original code -> new code
   00 -> 00
   10 -> 01
   11 -> 10
Encoding state machine s_state[0:4] (in view: work.PWM_SCALING(pwm_scaling))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_ramp_present_state[0:2] (in view: work.RATE_LIMITER(rate_limiter))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:4] (in view: work.pi_controller_ri(pi_controller_ri))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:8] (in view: work.SEQ_CONTROLLER(seq_controller))
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine s_state[0:4] (in view: work.pi_controller_spi(pi_controller_spi))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:2] (in view: work.SVM(svm))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 160MB peak: 171MB)


Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 176MB peak: 177MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 170MB peak: 177MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 169MB peak: 177MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 171MB peak: 177MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 173MB peak: 177MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 171MB peak: 177MB)


Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 172MB peak: 177MB)


Finished technology mapping (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 220MB peak: 256MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:12s		    -1.31ns		5658 /      3469
   2		0h:00m:12s		    -1.31ns		5050 /      3469

   3		0h:00m:13s		    -1.31ns		5050 /      3469


   4		0h:00m:14s		    -1.31ns		5050 /      3469
@N: FP130 |Promoting Net MC_System_0_FIC_0_LOCK on CLKINT  I_71 

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 229MB peak: 256MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 229MB peak: 256MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
2 gated/generated clock tree(s) driving 3484 clock pin(s) of sequential element(s)
0 instances converted, 3484 sequential instances remain driven by gated/generated clocks

=================================================================================================== Gated/Generated Clocks ===================================================================================================
Clock Tree ID     Driving Element                               Drive Element Type     Fanout     Sample Instance                                                  Explanation                                                
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       MC_System_0.MC_System_sb_0.CCC_0.CCC_INST     CCC                    3048       MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     No gated clock conversion method for cell cell:work.MSS_010
@K:CKID0002       MC_System_0.MC_System_sb_0.CCC_0.CCC_INST     CCC                    436        Bldc_Axis_0.SINC3_FILTER_0.s_diff2[0]                            No gated clock conversion method for cell cell:ACG4.SLE    
==============================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 178MB peak: 256MB)

Writing Analyst data base F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLRS10\LiberoProject\SK1ABLRS10_5_1\synthesis\synwork\MC_System_top_1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 219MB peak: 256MB)

Writing Verilog Simulation files
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:19s; Memory used current: 217MB peak: 256MB)


Start final timing analysis (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 216MB peak: 256MB)

@W: MT246 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablrs10\liberoproject\sk1ablrs10_5_1\component\work\mc_system_sb\ccc_0\mc_system_sb_ccc_0_fccc.vhd":115:4:115:11|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.CCC_0.GL2_net"
@W: MT420 |Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.CCC_0.GL0_net"


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Nov 29 15:54:17 2017
#


Top view:               MC_System_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: 0.513

                                                   Requested     Estimated      Requested     Estimated               Clock        Clock              
Starting Clock                                     Frequency     Frequency      Period        Period        Slack     Type         Group              
------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     105.4 MHz      10.000        9.487         0.513     inferred     Inferred_clkgroup_0
MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     100.0 MHz     380.5 MHz      10.000        2.628         7.372     inferred     Inferred_clkgroup_1
System                                             100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup    
======================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                          |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                        Ending                                          |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                          System                                          |  10.000      9.029  |  No paths    -      |  No paths    -      |  No paths    -    
System                                          MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      2.682  |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      0.513  |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock  |  10.000      7.372  |  No paths    -      |  No paths    -      |  No paths    -    
======================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                                                                                                 Arrival          
Instance                                                         Reference                                          Type        Pin                Net                                    Time        Slack
                                                                 Clock                                                                                                                                     
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[8]      MC_System_0_AMBA_SLAVE_0_PADDR[8]      3.354       0.513
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[5]      MC_System_0_AMBA_SLAVE_0_PADDR[5]      3.110       0.715
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[10]     MC_System_0_AMBA_SLAVE_0_PADDR[10]     3.357       0.826
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[9]      MC_System_0_AMBA_SLAVE_0_PADDR[9]      3.175       0.920
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[6]      MC_System_0_AMBA_SLAVE_0_PADDR[6]      3.185       1.138
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[0]      MC_System_0_AMBA_SLAVE_0_PADDR[0]      3.112       1.176
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[1]      MC_System_0_AMBA_SLAVE_0_PADDR[1]      3.058       1.196
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[7]      MC_System_0_AMBA_SLAVE_0_PADDR[7]      3.055       1.340
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[11]     MC_System_0_AMBA_SLAVE_0_PADDR[11]     3.057       1.392
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[4]      MC_System_0_AMBA_SLAVE_0_PADDR[4]      3.026       1.440
===========================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                                                                                                  Required          
Instance                                                         Reference                                          Type        Pin                 Net                                                    Time         Slack
                                                                 Clock                                                                                                                                                       
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        0.513
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[9]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]      9.594        0.568
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        1.123
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.604        1.224
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[29]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.625        1.245
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[30]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.629        1.249
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[11]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]     9.650        1.250
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        1.258
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[5]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]      9.672        1.272
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[22]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.652        1.272
=============================================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.461
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.539

    - Propagation time:                      9.026
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     0.513

    Number of logic level(s):                6
    Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[8]
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[4]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                Pin                Pin               Arrival     No. of    
Name                                                              Type        Name               Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_ADDR[8]      Out     3.354     3.354       -         
MC_System_0_AMBA_SLAVE_0_PADDR[8]                                 Net         -                  -       0.999     -           39        
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_4_0[17]                     CFG2        A                  In      -         4.353       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_4_0[17]                     CFG2        Y                  Out     0.087     4.440       -         
prdata_o_1_0_a2_4_0[17]                                           Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_4[17]                       CFG4        D                  In      -         4.923       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_4[17]                       CFG4        Y                  Out     0.250     5.173       -         
N_1924                                                            Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_1[17]                       CFG4        B                  In      -         5.656       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_a2_1[17]                       CFG4        Y                  Out     0.143     5.799       -         
N_1931                                                            Net         -                  -       0.820     -           18        
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_RNO[4]                         CFG4        B                  In      -         6.619       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_RNO[4]                         CFG4        Y                  Out     0.143     6.762       -         
N_1903                                                            Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0[4]                             CFG4        D                  In      -         7.245       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0[4]                             CFG4        Y                  Out     0.250     7.496       -         
MC_System_0_AMBA_SLAVE_0_PRDATA[4]                                Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[4]     CFG2        A                  In      -         7.979       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[4]     CFG2        Y                  Out     0.076     8.055       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]                 Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_RDATA[4]     In      -         9.026       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 9.487 is 4.764(50.2%) logic and 4.723(49.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                                                          Arrival          
Instance                                 Reference                                          Type     Pin     Net           Time        Slack
                                         Clock                                                                                              
--------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[0]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[0]     0.094       7.372
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[0]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[0]     0.094       7.372
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[1]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[1]     0.094       7.431
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[1]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[1]     0.094       7.431
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[2]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[2]     0.094       7.446
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[2]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[2]     0.094       7.446
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[3]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[3]     0.094       7.460
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[3]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[3]     0.094       7.460
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[4]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[4]     0.094       7.474
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[4]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      Q       s_acc3[4]     0.094       7.474
============================================================================================================================================


Ending Points with Worst Slack
******************************

                                          Starting                                                                                    Required          
Instance                                  Reference                                          Type     Pin     Net                     Time         Slack
                                          Clock                                                                                                         
--------------------------------------------------------------------------------------------------------------------------------------------------------
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[23]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_s_23_S       9.778        7.372
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[23]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_s_23_S       9.778        7.372
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[22]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_cry_22_S     9.778        7.386
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[22]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_cry_22_S     9.778        7.386
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[21]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_cry_21_S     9.778        7.401
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[21]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_cry_21_S     9.778        7.401
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[20]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_cry_20_S     9.778        7.415
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[20]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_cry_20_S     9.778        7.415
Bldc_Axis_0.SINC3_FILTER_0.s_acc3[19]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_cry_19_S     9.778        7.429
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[19]     MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock     SLE      D       un2_s_acc3_cry_19_S     9.778        7.429
========================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.778

    - Propagation time:                      2.406
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 7.372

    Number of logic level(s):                24
    Starting point:                          Bldc_Axis_0.SINC3_FILTER_2.s_acc3[0] / Q
    Ending point:                            Bldc_Axis_0.SINC3_FILTER_2.s_acc3[23] / D
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL2_net_inferred_clock [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[0]             SLE      Q        Out     0.094     0.094       -         
s_acc3[0]                                        Net      -        -       0.790     -           4         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_0      ARI1     B        In      -         0.884       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_0      ARI1     FCO      Out     0.174     1.059       -         
un2_s_acc3_cry_0                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_1      ARI1     FCI      In      -         1.059       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_1      ARI1     FCO      Out     0.014     1.073       -         
un2_s_acc3_cry_1                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_2      ARI1     FCI      In      -         1.073       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_2      ARI1     FCO      Out     0.014     1.087       -         
un2_s_acc3_cry_2                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_3      ARI1     FCI      In      -         1.087       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_3      ARI1     FCO      Out     0.014     1.101       -         
un2_s_acc3_cry_3                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_4      ARI1     FCI      In      -         1.101       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_4      ARI1     FCO      Out     0.014     1.115       -         
un2_s_acc3_cry_4                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_5      ARI1     FCI      In      -         1.115       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_5      ARI1     FCO      Out     0.014     1.130       -         
un2_s_acc3_cry_5                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_6      ARI1     FCI      In      -         1.130       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_6      ARI1     FCO      Out     0.014     1.144       -         
un2_s_acc3_cry_6                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_7      ARI1     FCI      In      -         1.144       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_7      ARI1     FCO      Out     0.014     1.158       -         
un2_s_acc3_cry_7                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_8      ARI1     FCI      In      -         1.158       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_8      ARI1     FCO      Out     0.014     1.172       -         
un2_s_acc3_cry_8                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_9      ARI1     FCI      In      -         1.172       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_9      ARI1     FCO      Out     0.014     1.186       -         
un2_s_acc3_cry_9                                 Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_10     ARI1     FCI      In      -         1.186       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_10     ARI1     FCO      Out     0.014     1.201       -         
un2_s_acc3_cry_10                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_11     ARI1     FCI      In      -         1.201       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_11     ARI1     FCO      Out     0.014     1.215       -         
un2_s_acc3_cry_11                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_12     ARI1     FCI      In      -         1.215       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_12     ARI1     FCO      Out     0.014     1.229       -         
un2_s_acc3_cry_12                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_13     ARI1     FCI      In      -         1.229       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_13     ARI1     FCO      Out     0.014     1.243       -         
un2_s_acc3_cry_13                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_14     ARI1     FCI      In      -         1.243       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_14     ARI1     FCO      Out     0.014     1.257       -         
un2_s_acc3_cry_14                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_15     ARI1     FCI      In      -         1.257       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_15     ARI1     FCO      Out     0.014     1.272       -         
un2_s_acc3_cry_15                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_16     ARI1     FCI      In      -         1.272       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_16     ARI1     FCO      Out     0.014     1.286       -         
un2_s_acc3_cry_16                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_17     ARI1     FCI      In      -         1.286       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_17     ARI1     FCO      Out     0.014     1.300       -         
un2_s_acc3_cry_17                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_18     ARI1     FCI      In      -         1.300       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_18     ARI1     FCO      Out     0.014     1.314       -         
un2_s_acc3_cry_18                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_19     ARI1     FCI      In      -         1.314       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_19     ARI1     FCO      Out     0.014     1.328       -         
un2_s_acc3_cry_19                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_20     ARI1     FCI      In      -         1.328       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_20     ARI1     FCO      Out     0.014     1.343       -         
un2_s_acc3_cry_20                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_21     ARI1     FCI      In      -         1.343       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_21     ARI1     FCO      Out     0.014     1.357       -         
un2_s_acc3_cry_21                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_22     ARI1     FCI      In      -         1.357       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_cry_22     ARI1     FCO      Out     0.014     1.371       -         
un2_s_acc3_cry_22                                Net      -        -       0.000     -           1         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_s_23       ARI1     FCI      In      -         1.371       -         
Bldc_Axis_0.SINC3_FILTER_2.un2_s_acc3_s_23       ARI1     S        Out     0.063     1.434       -         
un2_s_acc3_s_23_S                                Net      -        -       0.971     -           1         
Bldc_Axis_0.SINC3_FILTER_2.s_acc3[23]            SLE      D        In      -         2.406       -         
===========================================================================================================
Total path delay (propagation time + setup) of 2.628 is 0.866(33.0%) logic and 1.761(67.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                                                           Arrival          
Instance                                                 Reference     Type               Pin        Net                                                    Time        Slack
                                                         Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                System        CCC                LOCK       LOCK                                                   0.000       2.682
MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
=============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                                                             Required          
Instance                                                         Reference     Type        Pin                 Net                                                    Time         Slack
                                                                 Clock                                                                                                                  
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        2.682
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        2.817
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        2.845
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        2.883
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[9]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]      9.594        2.900
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[2]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]      9.706        2.905
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.604        3.341
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[29]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.625        3.362
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[30]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.629        3.366
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[22]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.652        3.389
========================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.517
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.483

    - Propagation time:                      6.801
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 2.682

    Number of logic level(s):                7
    Starting point:                          MC_System_0.MC_System_sb_0.CCC_0.CCC_INST / LOCK
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
    The start point is clocked by            System [rising]
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                Pin                Pin               Arrival     No. of    
Name                                                              Type        Name               Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                         CCC         LOCK               Out     0.000     0.000       -         
LOCK                                                              Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                 CLKINT      A                  In      -         0.971       -         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                 CLKINT      Y                  Out     0.326     1.298       -         
MC_System_0_FIC_0_LOCK                                            Net         -                  -       0.994     -           3502      
Bldc_Axis_0.OLMNG_0.theta_o[3]                                    CFG4        D                  In      -         2.291       -         
Bldc_Axis_0.OLMNG_0.theta_o[3]                                    CFG4        Y                  Out     0.250     2.541       -         
theta_o[3]                                                        Net         -                  -       0.590     -           3         
Bldc_Axis_0.apb3_if_0.prdata_o_1_17_i_m2_am[3]                    CFG3        A                  In      -         3.131       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_17_i_m2_am[3]                    CFG3        Y                  Out     0.076     3.207       -         
prdata_o_1_17_i_m2_am[3]                                          Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_17_i_m2_ns[3]                    CFG4        C                  In      -         3.690       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_17_i_m2_ns[3]                    CFG4        Y                  Out     0.182     3.872       -         
N_853                                                             Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_20_i_m2[3]                       CFG3        C                  In      -         4.356       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_20_i_m2[3]                       CFG3        Y                  Out     0.182     4.538       -         
N_819                                                             Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1[3]                           CFG4        C                  In      -         5.021       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_1[3]                           CFG4        Y                  Out     0.182     5.203       -         
prdata_o_1_0_1[3]                                                 Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]     CFG4        B                  In      -         5.686       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]     CFG4        Y                  Out     0.143     5.829       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]                 Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_RDATA[3]     In      -         6.801       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 7.318 is 1.859(25.4%) logic and 5.459(74.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:20s; Memory used current: 217MB peak: 256MB)


Finished timing report (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:20s; Memory used current: 217MB peak: 256MB)

---------------------------------------
Resource Usage Report for MC_System_top 

Mapping to part: m2s010fbga484-1
Cell usage:
CCC             1 use
CLKINT          3 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
CFG1           51 uses
CFG2           669 uses
CFG3           1138 uses
CFG4           1033 uses

Carry cells:
ARI1            2005 uses - used for arithmetic functions
ARI1            146 uses - used for Wide-Mux implementation
Total ARI1      2151 uses


Sequential Cells: 
SLE            3469 uses

DSP Blocks:    7 of 22 (31%)
 MACC:         1 Mult
 MACC:         6 MultAdds

I/O ports: 29
I/O primitives: 28
BIBUF          8 uses
INBUF          6 uses
OUTBUF         13 uses
TRIBUFF        1 use


Global Clock Buffers: 3 of 8 (37%)


Total LUTs:    5042

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
MACC     Interface Logic : SLEs = 252; LUTs = 252;

Total number of SLEs after P&R:  3469 + 0 + 0 + 252 = 3721;
Total number of LUTs after P&R:  5042 + 0 + 0 + 252 = 5294;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:20s; Memory used current: 42MB peak: 256MB)

Process took 0h:00m:21s realtime, 0h:00m:20s cputime
# Wed Nov 29 15:54:18 2017

###########################################################]
