#Build: Synplify Pro J-2015.03M-3, Build 048R, May 14 2015
#install: E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3
#OS: Windows 7 6.1
#Hostname: W764-MURALIA

#Implementation: synthesis

Synopsys HDL Compiler, version comp201503p1, Build 094R, built May 14 2015
@N|Running in 64-bit mode
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

Synopsys VHDL Compiler, version comp201503p1, Build 094R, built May 14 2015
@N|Running in 64-bit mode
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@N: CD720 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
@N:"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Top entity is set to MC_System_top.
VHDL syntax check successful!
@N: CD231 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Synthesizing work.mc_system_top.rtl 
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\Stepper_Axis\Stepper_Axis.vhd":17:7:17:18|Synthesizing work.stepper_axis.rtl 
Post processing for work.accumulator_st.accumulator_st
Post processing for work.stepper_theta.stepper_theta
Post processing for work.mas_spi.mas_spi
Post processing for work.pi_controller_spi.pi_controller_spi
Post processing for work.pi_scheduler.pi_scheduler
Post processing for work.speed_id_iq_pi.speed_id_iq_pi
Post processing for work.seq_controller.seq_controller
Post processing for work.mas_pwm_scl.mas_pwm_scl
Post processing for work.pwm_scaling.pwm_scaling
Post processing for work.pwm3ph.pwm3ph
Post processing for work.mas_scheduler.mas_scheduler
Post processing for work.mas_foc.mas_foc
Post processing for work.inverse_clarke.inverse_clarke
Post processing for work.cordic_scale.cordic_scale
Post processing for work.cordic_rot_foc.cordic_rot_foc
Post processing for work.cordic_scheduler.cordic_scheduler
Post processing for work.clarke.clarke
Post processing for work.foc_transforms.foc_transforms
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\apb3_if_st.vhd":30:7:30:16|Synthesizing work.apb3_if_st.apb3_if_st 
Post processing for work.apb3_if_st.apb3_if_st
Post processing for work.mas_adc_scl.mas_adc_scl
Post processing for work.adc_scaling.adc_scaling
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":31:7:31:19|Synthesizing work.adc_interface.adc_interface 
@N: CD231 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":117:22:117:23|Using onehot encoding for type adc_op_state (idle="10000")
@W: CD604 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":252:12:252:25|OTHERS clause is not synthesized 
Post processing for work.adc_interface.adc_interface
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":343:8:343:9|Pruning register s_slave_select_cnt_5(3 downto 0)  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":320:8:320:9|Pruning register s_slave_select_dly_2  
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":440:8:440:9|Sharing sequential element s_r_sck_sync.
@W: CL111 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":289:8:289:9|All reachable assignments to s_r_sck_max_count(1) assign '0'; register removed by optimization
@W: CL111 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":289:8:289:9|All reachable assignments to s_r_sck_max_count(2) assign '0'; register removed by optimization
@W: CL111 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":289:8:289:9|All reachable assignments to s_r_sck_max_count(3) assign '0'; register removed by optimization
@W: CL111 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":289:8:289:9|All reachable assignments to s_r_sck_max_count(5) assign '0'; register removed by optimization
@W: CL111 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":289:8:289:9|All reachable assignments to s_r_sck_max_count(6) assign '0'; register removed by optimization
Post processing for work.stepper_axis.rtl
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System\MC_System.vhd":17:7:17:15|Synthesizing work.mc_system.rtl 
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb\MC_System_sb.vhd":20:7:20:18|Synthesizing work.mc_system_sb.rtl 
@N: CD630 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.vhd":786:10:786:17|Synthesizing smartfusion2.sysreset.syn_black_box 
Post processing for smartfusion2.sysreset.syn_black_box
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb_MSS\MC_System_sb_MSS.vhd":17:7:17:22|Synthesizing work.mc_system_sb_mss.rtl 
@N: CD630 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.vhd":434:10:434:14|Synthesizing smartfusion2.bibuf.syn_black_box 
Post processing for smartfusion2.bibuf.syn_black_box
@N: CD630 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.vhd":403:10:403:14|Synthesizing smartfusion2.inbuf.syn_black_box 
Post processing for smartfusion2.inbuf.syn_black_box
@N: CD630 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.vhd":423:10:423:16|Synthesizing smartfusion2.tribuff.syn_black_box 
Post processing for smartfusion2.tribuff.syn_black_box
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb_MSS\MC_System_sb_MSS_syn.vhd":10:7:10:13|Synthesizing work.mss_010.def_arch 
Post processing for work.mss_010.def_arch
Post processing for work.mc_system_sb_mss.rtl
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":8:7:8:31|Synthesizing work.mc_system_sb_fabosc_0_osc.def_arch 
@N: CD630 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.vhd":562:10:562:15|Synthesizing smartfusion2.clkint.syn_black_box 
Post processing for smartfusion2.clkint.syn_black_box
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\SgCore\OSC\1.0.103\osc_comps.vhd":19:7:19:20|Synthesizing work.rcosc_25_50mhz.def_arch 
Post processing for work.rcosc_25_50mhz.def_arch
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\SgCore\OSC\1.0.103\osc_comps.vhd":79:7:79:24|Synthesizing work.rcosc_25_50mhz_fab.def_arch 
Post processing for work.rcosc_25_50mhz_fab.def_arch
Post processing for work.mc_system_sb_fabosc_0_osc.def_arch
@W: CL240 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":16:10:16:19|XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":15:10:15:19|XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":14:10:14:23|RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":13:10:13:23|RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. 
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":27:7:27:16|Synthesizing work.coreresetp.rtl 
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":477:8:477:25|Signal soft_ext_reset_out in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":478:8:478:21|Signal soft_reset_f2m in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":479:8:479:20|Signal soft_m3_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":480:8:480:37|Signal soft_mddr_ddr_axi_s_core_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":481:8:481:27|Signal soft_fddr_core_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":482:8:482:27|Signal soft_sdif0_phy_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":483:8:483:28|Signal soft_sdif0_core_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":484:8:484:27|Signal soft_sdif1_phy_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":485:8:485:28|Signal soft_sdif1_core_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":486:8:486:27|Signal soft_sdif2_phy_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":487:8:487:28|Signal soft_sdif2_core_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":488:8:488:27|Signal soft_sdif3_phy_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":489:8:489:28|Signal soft_sdif3_core_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":490:8:490:30|Signal soft_sdif0_0_core_reset in the sensitivity list is not used in the process
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":491:8:491:30|Signal soft_sdif0_1_core_reset in the sensitivity list is not used in the process
Post processing for work.coreresetp.rtl
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1519:8:1519:9|Pruning register count_ddr_2(13 downto 0)  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1495:8:1495:9|Pruning register count_sdif3_2(12 downto 0)  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1471:8:1471:9|Pruning register count_sdif2_2(12 downto 0)  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1447:8:1447:9|Pruning register count_sdif1_2(12 downto 0)  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1423:8:1423:9|Pruning register count_sdif0_2(12 downto 0)  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_ddr_enable_rcosc_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_ddr_enable_q1_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif3_enable_rcosc_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif2_enable_rcosc_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif1_enable_rcosc_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif0_enable_rcosc_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif3_enable_q1_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif2_enable_q1_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif1_enable_q1_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif0_enable_q1_2  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Pruning register count_sdif3_enable_3  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Pruning register count_sdif2_enable_3  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Pruning register count_sdif1_enable_3  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Pruning register count_sdif0_enable_3  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Pruning register count_ddr_enable_3  
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q1.
@W: CL190 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Pruning register release_ext_reset  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Pruning register EXT_RESET_OUT_int  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Pruning register sm2_state(2 downto 0)  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":792:8:792:9|Pruning register sm2_areset_n_q1  
@W: CL169 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":792:8:792:9|Pruning register sm2_areset_n_clk_base  
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":34:7:34:14|Synthesizing coreapb3_lib.coreapb3.coreapb3_arch 
@W: CD604 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":665:16:665:29|OTHERS clause is not synthesized 
@W: CD434 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":1453:41:1453:46|Signal infill in the sensitivity list is not used in the process
@W: CD638 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":616:7:616:15|Signal ia_prdata is undriven 
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd":33:7:33:23|Synthesizing coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch 
Post processing for coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch
Post processing for coreapb3_lib.coreapb3.coreapb3_arch
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb\CCC_0\MC_System_sb_CCC_0_FCCC.vhd":8:7:8:29|Synthesizing work.mc_system_sb_ccc_0_fccc.def_arch 
@N: CD630 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.vhd":794:10:794:12|Synthesizing smartfusion2.ccc.syn_black_box 
Post processing for smartfusion2.ccc.syn_black_box
@N: CD630 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.vhd":576:10:576:12|Synthesizing smartfusion2.gnd.syn_black_box 
Post processing for smartfusion2.gnd.syn_black_box
@N: CD630 :"E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.vhd":582:10:582:12|Synthesizing smartfusion2.vcc.syn_black_box 
Post processing for smartfusion2.vcc.syn_black_box
Post processing for work.mc_system_sb_ccc_0_fccc.def_arch
Post processing for work.mc_system_sb.rtl
Post processing for work.mc_system.rtl
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\Bldc_Axis\Bldc_Axis.vhd":17:7:17:15|Synthesizing work.bldc_axis.rtl 
Post processing for work.svm.svm
Post processing for work.accumulator_rl.accumulator_rl
Post processing for work.rate_limiter.rate_limiter
Post processing for work.accumulator_olmng.accumulator_olmng
Post processing for work.mas_olmng.mas_olmng
Post processing for work.olmng.olmng
Post processing for work.accumulator_pe.accumulator_pe
Post processing for work.filter.filter
Post processing for work.mas_pll.mas_pll
Post processing for work.pll_theta.pll_theta
Post processing for work.mas_pe_pi.mas_pe_pi
Post processing for work.pi_controller_pe.pi_controller_pe
Post processing for work.cordic_rot_pe.cordic_rot_pe
Post processing for work.mas_fe.mas_fe
Post processing for work.flux_estimator.flux_estimator
Post processing for work.bldc_estimator.bldc_estimator
@N: CD630 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\apb3_if.vhd":31:7:31:13|Synthesizing work.apb3_if.apb3_if 
Post processing for work.apb3_if.apb3_if
Post processing for work.bldc_axis.rtl
Post processing for work.mc_system_top.rtl
@W: CL246 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\apb3_if.vhd":60:4:60:10|Input port bits 31 to 12 of paddr_i(31 downto 0) are unused 
@W: CL246 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\apb3_if.vhd":61:4:61:11|Input port bits 31 to 18 of pwdata_i(31 downto 0) are unused 
Extracted state machine for register s_state
State machine has 7 reachable states with original encodings of:
   00000001
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Extracted state machine for register s_state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
Extracted state machine for register s_state
State machine has 3 reachable states with original encodings of:
   00
   10
   11
Extracted state machine for register s_ramp_present_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Extracted state machine for register s_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":75:0:75:4|Input IADDR is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":76:0:76:6|Input PRESETN is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":77:0:77:3|Input PCLK is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":109:0:109:7|Input PRDATAS2 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":110:0:110:7|Input PRDATAS3 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":111:0:111:7|Input PRDATAS4 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":112:0:112:7|Input PRDATAS5 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":113:0:113:7|Input PRDATAS6 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":114:0:114:7|Input PRDATAS7 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":115:0:115:7|Input PRDATAS8 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":116:0:116:7|Input PRDATAS9 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":117:0:117:8|Input PRDATAS10 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":118:0:118:8|Input PRDATAS11 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":119:0:119:8|Input PRDATAS12 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":120:0:120:8|Input PRDATAS13 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":121:0:121:8|Input PRDATAS14 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":122:0:122:8|Input PRDATAS15 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":126:0:126:7|Input PREADYS2 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":127:0:127:7|Input PREADYS3 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":128:0:128:7|Input PREADYS4 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":129:0:129:7|Input PREADYS5 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":130:0:130:7|Input PREADYS6 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":131:0:131:7|Input PREADYS7 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":132:0:132:7|Input PREADYS8 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":133:0:133:7|Input PREADYS9 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":134:0:134:8|Input PREADYS10 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":135:0:135:8|Input PREADYS11 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":136:0:136:8|Input PREADYS12 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":137:0:137:8|Input PREADYS13 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":138:0:138:8|Input PREADYS14 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":139:0:139:8|Input PREADYS15 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":143:0:143:8|Input PSLVERRS2 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":144:0:144:8|Input PSLVERRS3 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":145:0:145:8|Input PSLVERRS4 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":146:0:146:8|Input PSLVERRS5 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":147:0:147:8|Input PSLVERRS6 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":148:0:148:8|Input PSLVERRS7 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":149:0:149:8|Input PSLVERRS8 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":150:0:150:8|Input PSLVERRS9 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":151:0:151:9|Input PSLVERRS10 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":152:0:152:9|Input PSLVERRS11 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":153:0:153:9|Input PSLVERRS12 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":154:0:154:9|Input PSLVERRS13 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":155:0:155:9|Input PSLVERRS14 is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":156:0:156:9|Input PSLVERRS15 is unused
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q2.
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL201 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":96:4:96:12|Input CLK_LTSSM is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":123:4:123:12|Input FPLL_LOCK is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":126:4:126:18|Input SDIF0_SPLL_LOCK is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":135:4:135:18|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":139:4:139:18|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":143:4:143:18|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":157:4:157:13|Input SDIF0_PSEL is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":158:4:158:15|Input SDIF0_PWRITE is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":159:4:159:15|Input SDIF0_PRDATA is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":160:4:160:13|Input SDIF1_PSEL is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":161:4:161:15|Input SDIF1_PWRITE is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":162:4:162:15|Input SDIF1_PRDATA is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":163:4:163:13|Input SDIF2_PSEL is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":164:4:164:15|Input SDIF2_PWRITE is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":165:4:165:15|Input SDIF2_PRDATA is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":166:4:166:13|Input SDIF3_PSEL is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":167:4:167:15|Input SDIF3_PWRITE is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":168:4:168:15|Input SDIF3_PRDATA is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":174:4:174:21|Input SOFT_EXT_RESET_OUT is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":175:4:175:17|Input SOFT_RESET_F2M is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":176:4:176:16|Input SOFT_M3_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":177:4:177:33|Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":178:4:178:23|Input SOFT_FDDR_CORE_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":179:4:179:23|Input SOFT_SDIF0_PHY_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":180:4:180:24|Input SOFT_SDIF0_CORE_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":181:4:181:23|Input SOFT_SDIF1_PHY_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":182:4:182:24|Input SOFT_SDIF1_CORE_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":183:4:183:23|Input SOFT_SDIF2_PHY_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":184:4:184:24|Input SOFT_SDIF2_CORE_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":185:4:185:23|Input SOFT_SDIF3_PHY_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":186:4:186:24|Input SOFT_SDIF3_CORE_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":190:4:190:26|Input SOFT_SDIF0_0_CORE_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":191:4:191:26|Input SOFT_SDIF0_1_CORE_RESET is unused
@W: CL159 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":10:10:10:12|Input XTL is unused
@W: CL190 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":492:8:492:9|Optimizing register bit s_r_sck_count(5) to a constant 0
@W: CL190 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":492:8:492:9|Optimizing register bit s_r_sck_count(6) to a constant 0
@W: CL279 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":492:8:492:9|Pruning register bits 6 to 5 of s_r_sck_count(6 downto 0)  
@W: CL260 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":289:8:289:9|Pruning register bit 4 of s_r_sck_max_count(4 downto 3)  
@N: CL201 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\adc_interface.vhd":554:8:554:9|Trying to extract state machine for register present_state
Extracted state machine for register present_state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
Extracted state machine for register s_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W: CL246 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\apb3_if_st.vhd":47:4:47:10|Input port bits 31 to 12 of paddr_i(31 downto 0) are unused 
@W: CL246 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\hdl\apb3_if_st.vhd":48:4:48:11|Input port bits 31 to 24 of pwdata_i(31 downto 0) are unused 
Extracted state machine for register s_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Extracted state machine for register s_state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
Extracted state machine for register s_state
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
Extracted state machine for register s_state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000

At c_vhdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 119MB peak: 128MB)

Process took 0h:00m:05s realtime, 0h:00m:05s cputime
# Tue Oct 27 16:21:03 2015

###########################################################]
Synopsys Netlist Linker, version comp201503p1, Build 094R, built May 14 2015
@N|Running in 64-bit mode
@N: NF107 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Selected library: work cell: MC_System_top view rtl as top level
@N: NF107 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Selected library: work cell: MC_System_top view rtl as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 81MB peak: 82MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Oct 27 16:21:06 2015

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Tue Oct 27 16:21:06 2015

###########################################################]
Synopsys Netlist Linker, version comp201503p1, Build 094R, built May 14 2015
@N|Running in 64-bit mode
@N: NF107 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Selected library: work cell: MC_System_top view rtl as top level
@N: NF107 :"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Selected library: work cell: MC_System_top view rtl as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 88MB peak: 89MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Oct 27 16:21:10 2015

###########################################################]
Pre-mapping Report

Synopsys Generic Technology Pre-mapping, Version map201503actrcp1, Build 002R, Built Jul  1 2015 06:58:23
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03M-3

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\constraint\MS_MC_System_top_compile.sdc
@L: E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\synthesis\MC_System_top_1_scck.rpt 
Printing clock  summary report in "E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\synthesis\MC_System_top_1_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 129MB)


Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB)


Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB)

@W: BN132 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance adc_control_reg_val_o[5:0] of view:PrimLib.dffre(prim) in hierarchy view:work.apb3_if_st(apb3_if_st) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance sdif0_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance sdif1_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance sdif2_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance sdif3_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance sm0_state[0:6] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":922:8:922:9|Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":803:8:803:9|Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":814:8:814:9|Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":825:8:825:9|Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":836:8:836:9|Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":908:8:908:9|Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":922:8:922:9|Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":803:8:803:9|Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":814:8:814:9|Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":825:8:825:9|Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":836:8:836:9|Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":908:8:908:9|Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1495:8:1495:9|Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1471:8:1471:9|Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1447:8:1447:9|Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1423:8:1423:9|Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1519:8:1519:9|Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":770:8:770:9|Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":894:8:894:9|Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":883:8:883:9|Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":872:8:872:9|Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":861:8:861:9|Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":770:8:770:9|Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":850:8:850:9|Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":894:8:894:9|Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":883:8:883:9|Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":872:8:872:9|Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":861:8:861:9|Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":850:8:850:9|Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":608:8:608:9|Removing sequential instance MSS_HPMS_READY_int of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":593:8:593:9|Removing sequential instance mss_ready_select of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":593:8:593:9|Removing sequential instance mss_ready_state of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":577:8:577:9|Removing sequential instance FIC_2_APB_M_PRESET_N_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":565:8:565:9|Removing sequential instance RESET_N_M2F_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":577:8:577:9|Removing sequential instance FIC_2_APB_M_PRESET_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":565:8:565:9|Removing sequential instance RESET_N_M2F_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":553:8:553:9|Removing sequential instance POWER_ON_RESET_N_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":553:8:553:9|Removing sequential instance POWER_ON_RESET_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
syn_allowed_resources : blockrams=21,dsps=22  set on top level netlist MC_System_top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 159MB peak: 161MB)



@S |Clock Summary
*****************

Start                                                           Requested     Requested     Clock        Clock              
Clock                                                           Frequency     Period        Type         Group              
----------------------------------------------------------------------------------------------------------------------------
MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT     50.0 MHz      20.000        declared     default_clkgroup   
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_1
MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_0
System                                                          100.0 MHz     10.000        system       system_clkgroup    
============================================================================================================================

@W: MT530 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":569:8:569:9|Found inferred clock MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock which controls 1804 sequential elements including Stepper_Axis_0.adc_interface_0.s_channel_cnt[2:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":569:8:569:9|Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 3518 sequential elements including Bldc_Axis_0.adc_interface_0.s_channel_cnt[2:0]. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\synthesis\MC_System_top_1.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 89MB peak: 161MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Oct 27 16:21:13 2015

###########################################################]
Map & Optimize Report

Synopsys Generic Technology Mapper, Version map201503actrcp1, Build 002R, Built Jul  1 2015 06:58:23
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03M-3

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 151MB)

@N: BN114 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\work\mc_system_sb\mc_system_sb.vhd":674:0:674:11|Removing instance SYSRESET_POR of black_box view:ACG4.SYSRESET(PRIM) because there are no references to its outputs 
@W: MO171 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 

Available hyper_sources - for debug and ip models
	None Found

@N: FA239 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
@N: FA239 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
@N: MO106 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|Found ROM, 'CoreAPB3_0.iPSELS_raw_5[1:0]', 16 words by 2 bits 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 156MB)

@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if.vhd":556:8:556:9|Removing sequential instance apb3_if_0.pwm_gain_val_o[0] of view:PrimLib.dffr(prim) in hierarchy view:work.Bldc_Axis(rtl) because there are no references to its outputs 
Encoding state machine present_state[0:4] (view:work.adc_interface_0(adc_interface))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N:"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":492:8:492:9|Found counter in view:work.adc_interface_0(adc_interface) inst s_r_sck_count[4:0]
@N:"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":440:8:440:9|Found counter in view:work.adc_interface_0(adc_interface) inst s_r_clock_count[7:0]
Encoding state machine s_state[0:3] (view:work.adc_scaling_0(adc_scaling))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
Encoding state machine s_state[0:6] (view:work.Flux_Estimator(flux_estimator))
original code -> new code
   00000001 -> 0000001
   00000100 -> 0000010
   00001000 -> 0000100
   00010000 -> 0001000
   00100000 -> 0010000
   01000000 -> 0100000
   10000000 -> 1000000
Encoding state machine s_state[0:4] (view:work.pi_controller_pe(pi_controller_pe))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:2] (view:work.cordic_scale_0(cordic_scale))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:2] (view:work.olmng(olmng))
original code -> new code
   00 -> 00
   10 -> 01
   11 -> 10
Encoding state machine s_state[0:4] (view:work.pwm_scaling_0(pwm_scaling))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_ramp_present_state[0:2] (view:work.rate_limiter(rate_limiter))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:8] (view:work.seq_controller_0(seq_controller))
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine s_state[0:4] (view:work.pi_controller_spi_0(pi_controller_spi))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:2] (view:work.svm(svm))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine present_state[0:4] (view:work.adc_interface_1(adc_interface))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N:"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":492:8:492:9|Found counter in view:work.adc_interface_1(adc_interface) inst s_r_sck_count[4:0]
@N:"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":440:8:440:9|Found counter in view:work.adc_interface_1(adc_interface) inst s_r_clock_count[7:0]
@W: MO129 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":475:8:475:9|Sequential instance Stepper_Axis_0.adc_interface_0.s_r_adc_chnls_4_samp[1] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":475:8:475:9|Sequential instance Stepper_Axis_0.adc_interface_0.s_r_adc_chnls_4_samp[2] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":475:8:475:9|Sequential instance Stepper_Axis_0.adc_interface_0.s_r_sck_sel[0] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":475:8:475:9|Sequential instance Stepper_Axis_0.adc_interface_0.s_r_sck_sel[2] reduced to a combinational gate by constant propagation
@W: BN132 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":475:8:475:9|Removing instance Stepper_Axis_0.adc_interface_0.s_r_sck_sel[1],  because it is equivalent to instance Stepper_Axis_0.adc_interface_0.s_r_sck_max_count[3]
@W: BN132 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":475:8:475:9|Removing instance Stepper_Axis_0.adc_interface_0.s_r_adc_chnls_4_samp[0],  because it is equivalent to instance Stepper_Axis_0.adc_interface_0.s_r_sck_max_count[3]
Encoding state machine s_state[0:3] (view:work.adc_scaling_1(adc_scaling))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
Encoding state machine s_state[0:2] (view:work.cordic_scale_1(cordic_scale))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:4] (view:work.pwm_scaling_1(pwm_scaling))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:8] (view:work.seq_controller_1(seq_controller))
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine s_state[0:4] (view:work.pi_controller_spi_1(pi_controller_spi))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[0] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[1] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[2] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[3] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[4] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[5] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[6] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[7] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[8] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[9] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[10] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[11] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[12] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[13] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[14] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch2_o[15] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[0] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[1] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[2] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[3] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[4] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[5] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[6] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[7] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[8] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[9] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[10] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[11] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[12] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[13] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[14] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance apb3_if_st_0.adc_channel_ch3_o[15] in hierarchy view:work.Stepper_Axis(rtl) because there are no references to its outputs 

Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 193MB peak: 193MB)

@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance Stepper_Axis_0.apb3_if_st_0.seq_cntl_config_o[0] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\apb3_if_st.vhd":360:1:360:2|Removing sequential instance Stepper_Axis_0.apb3_if_st_0.seq_cntl_config_o[3] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":569:8:569:9|Removing sequential instance Stepper_Axis_0.adc_interface_0.s_channel_cnt[2] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 187MB peak: 194MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 184MB peak: 212MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 189MB peak: 212MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 190MB peak: 212MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 187MB peak: 212MB)

@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":440:8:440:9|Removing sequential instance Stepper_Axis_0.adc_interface_0.s_r_clock_count[7] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":440:8:440:9|Removing sequential instance Stepper_Axis_0.adc_interface_0.s_r_clock_count[6] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":440:8:440:9|Removing sequential instance Stepper_Axis_0.adc_interface_0.s_r_clock_count[5] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":440:8:440:9|Removing sequential instance Stepper_Axis_0.adc_interface_0.s_r_clock_count[4] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs 
@N: BN362 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\hdl\adc_interface.vhd":440:8:440:9|Removing sequential instance Stepper_Axis_0.adc_interface_0.s_r_clock_count[3] in hierarchy view:work.MC_System_top(rtl) because there are no references to its outputs 

Finished preparing to map (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 190MB peak: 212MB)


Finished technology mapping (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 267MB peak: 273MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:18s		    -2.93ns		7181 /      4617
   2		0h:00m:18s		    -2.93ns		6929 /      4617
   3		0h:00m:19s		    -2.27ns		6929 /      4617
   4		0h:00m:19s		    -2.27ns		6929 /      4617


Timing driven replication report
Added 5 Registers via timing driven replication
Added 3 LUTs via timing driven replication

   5		0h:00m:26s		    -1.24ns		6970 /      4622


   6		0h:00m:27s		    -1.24ns		6971 /      4622
@N: FP130 |Promoting Net MC_System_0_FIC_0_LOCK on CLKINT  I_110 

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 230MB peak: 279MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 231MB peak: 279MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
2 non-gated/non-generated clock tree(s) driving 4647 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=============================================================== Non-Gated/Non-Generated Clocks ===============================================================
Clock Tree ID     Driving Element                               Drive Element Type     Fanout     Sample Instance                                             
--------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       MC_System_0.MC_System_sb_0.CCC_0.GL0_INST     CLKINT                 3144       MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST
@K:CKID0002       MC_System_0.MC_System_sb_0.CCC_0.GL1_INST     CLKINT                 1503       Stepper_Axis_0.apb3_if_st_0.start_motor_o                   
==============================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:30s; Memory used current: 171MB peak: 279MB)

Writing Analyst data base E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\synthesis\synwork\MC_System_top_1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:33s; Memory used current: 218MB peak: 279MB)

Writing Verilog Simulation files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:36s; CPU Time elapsed 0h:00m:35s; Memory used current: 215MB peak: 279MB)


Start final timing analysis (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:36s; Memory used current: 215MB peak: 279MB)

@W: MT246 :"e:\solutions_repo\motor control\development\mcsk\sk2ablslst10\sk2ablslst10_5_1\component\work\mc_system_sb\ccc_0\mc_system_sb_ccc_0_fccc.vhd":110:4:110:11|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.CCC_0.GL0_net"

@W: MT420 |Found inferred clock MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_0.MC_System_sb_0.CCC_0.GL1_net"



@S |##### START OF TIMING REPORT #####[
# Timing Report written on Tue Oct 27 16:21:50 2015
#


Top view:               MC_System_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10\SK2ABLSLST10_5_1\constraint\MS_MC_System_top_compile.sdc
                       
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: -0.888

                                                   Requested     Estimated      Requested     Estimated                Clock        Clock              
Starting Clock                                     Frequency     Frequency      Period        Period        Slack      Type         Group              
-------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     91.8 MHz       10.000        10.888        -0.888     inferred     Inferred_clkgroup_1
MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     100.0 MHz     138.6 MHz      10.000        7.214         2.786      inferred     Inferred_clkgroup_0
System                                             100.0 MHz     1029.4 MHz     10.000        0.971         9.029      system       system_clkgroup    
=======================================================================================================================================================
@W: MT548 :"e:/solutions_repo/motor control/development/mcsk/sk2ablslst10/sk2ablslst10_5_1/constraint/ms_mc_system_top_compile.sdc":3:0:3:0|Source for clock MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT not found in netlist. Run the constraint checker to verify if constraints are applied correctly.
@W: MT548 :"e:/solutions_repo/motor control/development/mcsk/sk2ablslst10/sk2ablslst10_5_1/constraint/ms_mc_system_top_compile.sdc":6:0:6:0|Source for clock MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.
@W: MT548 :"e:/solutions_repo/motor control/development/mcsk/sk2ablslst10/sk2ablslst10_5_1/constraint/ms_mc_system_top_compile.sdc":11:0:11:0|Source for clock MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.





Clock Relationships
*******************

Clocks                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                        Ending                                          |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                          System                                          |  10.000      9.029   |  No paths    -      |  No paths    -      |  No paths    -    
System                                          MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      1.017   |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock  |  10.000      2.786   |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      -0.888  |  No paths    -      |  No paths    -      |  No paths    -    
=======================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                                                                                                 Arrival           
Instance                                                         Reference                                          Type        Pin                Net                                    Time        Slack 
                                                                 Clock                                                                                                                                      
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[10]     MC_System_0_AMBA_SLAVE_1_PADDR[10]     3.357       -0.888
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[8]      MC_System_0_AMBA_SLAVE_1_PADDR[8]      3.354       -0.848
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[0]      MC_System_0_AMBA_SLAVE_1_PADDR[0]      3.112       -0.828
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[1]      MC_System_0_AMBA_SLAVE_1_PADDR[1]      3.058       -0.814
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[5]      MC_System_0_AMBA_SLAVE_1_PADDR[5]      3.110       -0.806
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[6]      MC_System_0_AMBA_SLAVE_1_PADDR[6]      3.185       -0.672
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[3]      MC_System_0_AMBA_SLAVE_1_PADDR[3]      3.040       -0.565
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[4]      MC_System_0_AMBA_SLAVE_1_PADDR[4]      3.026       -0.458
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[9]      MC_System_0_AMBA_SLAVE_1_PADDR[9]      3.175       -0.450
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[2]      MC_System_0_AMBA_SLAVE_1_PADDR[2]      3.040       -0.422
============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                                                                                                  Required           
Instance                                                         Reference                                          Type        Pin                 Net                                                    Time         Slack 
                                                                 Clock                                                                                                                                                        
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        -0.888
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        -0.848
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        -0.818
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[5]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]      9.672        -0.651
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        -0.628
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[2]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]      9.706        -0.606
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[13]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]     9.640        -0.406
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[16]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]     9.647        -0.399
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[10]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[10]     9.723        -0.374
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[11]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]     9.650        -0.358
==============================================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.461
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.539

    - Propagation time:                      10.427
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.888

    Number of logic level(s):                6
    Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[4]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                  Pin                Pin               Arrival     No. of    
Name                                                                Type        Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -         
MC_System_0_AMBA_SLAVE_1_PADDR[10]                                  Net         -                  -       0.999     -           39        
Bldc_Axis_0.apb3_if_0.g0_4                                          CFG4        D                  In      -         4.356       -         
Bldc_Axis_0.apb3_if_0.g0_4                                          CFG4        Y                  Out     0.411     4.766       -         
g0_4                                                                Net         -                  -       0.622     -           4         
Bldc_Axis_0.apb3_if_0.g0_0                                          CFG4        C                  In      -         5.388       -         
Bldc_Axis_0.apb3_if_0.g0_0                                          CFG4        Y                  Out     0.182     5.570       -         
N_2883                                                              Net         -                  -       0.802     -           16        
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_1[4]                        CFG4        D                  In      -         6.373       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_1[4]                        CFG4        Y                  Out     0.408     6.781       -         
prdata_o_1_12_0_0_1[4]                                              Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_sx[4]                       CFG4        D                  In      -         7.264       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_sx[4]                       CFG4        Y                  Out     0.408     7.673       -         
prdata_o_1_12_0_0_sx[4]                                             Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0[4]                          CFG4        D                  In      -         8.156       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0[4]                          CFG4        Y                  Out     0.408     8.564       -         
MC_System_0_AMBA_SLAVE_0_PRDATA[4]                                  Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[4]     CFG4        D                  In      -         9.048       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[4]     CFG4        Y                  Out     0.408     9.456       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]                   Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_RDATA[4]     In      -         10.427      -         
===========================================================================================================================================
Total path delay (propagation time + setup) of 10.888 is 6.045(55.5%) logic and 4.844(44.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.383
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.617

    - Propagation time:                      10.465
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.848

    Number of logic level(s):                6
    Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[8]
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[0]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                      Type        Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST              MSS_010     F_HM0_ADDR[8]      Out     3.354     3.354       -         
MC_System_0_AMBA_SLAVE_1_PADDR[8]                                         Net         -                  -       1.006     -           109       
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_15_0[17]                          CFG4        C                  In      -         4.360       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_15_0[17]                          CFG4        Y                  Out     0.200     4.560       -         
prdata_o_1_0_0_a2_15_1[17]                                                Net         -                  -       0.670     -           6         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_15_0_RNITI653[17]                 CFG4        D                  In      -         5.230       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_0_0_a2_15_0_RNITI653[17]                 CFG4        Y                  Out     0.408     5.638       -         
N_2885                                                                    Net         -                  -       0.772     -           13        
Bldc_Axis_0.apb3_if_0.prdata_o_1_24_0_0[0]                                CFG4        D                  In      -         6.410       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_24_0_0[0]                                CFG4        Y                  Out     0.408     6.819       -         
prdata_o_1_24_0_0[0]                                                      Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_RNO_3[0]     CFG4        D                  In      -         7.302       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_RNO_3[0]     CFG4        Y                  Out     0.408     7.710       -         
G_16_0_1                                                                  Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_RNO[0]       CFG4        D                  In      -         8.194       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_RNO[0]       CFG4        Y                  Out     0.408     8.602       -         
MC_System_0_AMBA_SLAVE_0_PRDATA[0]                                        Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[0]           CFG4        D                  In      -         9.085       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[0]           CFG4        Y                  Out     0.408     9.494       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]                         Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST              MSS_010     F_HM0_RDATA[0]     In      -         10.465      -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 10.848 is 5.979(55.1%) logic and 4.869(44.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.461
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.539

    - Propagation time:                      10.367
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.828

    Number of logic level(s):                6
    Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[0]
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[4]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                  Pin                Pin               Arrival     No. of    
Name                                                                Type        Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_ADDR[0]      Out     3.112     3.112       -         
MC_System_0_AMBA_SLAVE_1_PADDR[0]                                   Net         -                  -       0.988     -           10        
Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o188_1         CFG2        A                  In      -         4.100       -         
Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o188_1         CFG2        Y                  Out     0.087     4.188       -         
g0_0_1                                                              Net         -                  -       0.914     -           32        
Bldc_Axis_0.apb3_if_0.g0_0                                          CFG4        D                  In      -         5.102       -         
Bldc_Axis_0.apb3_if_0.g0_0                                          CFG4        Y                  Out     0.408     5.510       -         
N_2883                                                              Net         -                  -       0.802     -           16        
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_1[4]                        CFG4        D                  In      -         6.313       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_1[4]                        CFG4        Y                  Out     0.408     6.721       -         
prdata_o_1_12_0_0_1[4]                                              Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_sx[4]                       CFG4        D                  In      -         7.204       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_sx[4]                       CFG4        Y                  Out     0.408     7.613       -         
prdata_o_1_12_0_0_sx[4]                                             Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0[4]                          CFG4        D                  In      -         8.096       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0[4]                          CFG4        Y                  Out     0.408     8.504       -         
MC_System_0_AMBA_SLAVE_0_PRDATA[4]                                  Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[4]     CFG4        D                  In      -         8.988       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[4]     CFG4        Y                  Out     0.408     9.396       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]                   Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_RDATA[4]     In      -         10.367      -         
===========================================================================================================================================
Total path delay (propagation time + setup) of 10.828 is 5.702(52.7%) logic and 5.126(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.000
    - Setup time:                            0.517
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.483

    - Propagation time:                      10.301
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.818

    Number of logic level(s):                6
    Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                  Pin                Pin               Arrival     No. of    
Name                                                                Type        Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -         
MC_System_0_AMBA_SLAVE_1_PADDR[10]                                  Net         -                  -       0.999     -           39        
Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o192_2_0       CFG2        A                  In      -         4.356       -         
Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o192_2_0       CFG2        Y                  Out     0.087     4.443       -         
prdata_o192_2_0                                                     Net         -                  -       0.590     -           3         
Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o194           CFG4        D                  In      -         5.033       -         
Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o194           CFG4        Y                  Out     0.408     5.441       -         
prdata_o194                                                         Net         -                  -       0.827     -           19        
Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_3[3]                      CFG4        D                  In      -         6.268       -         
Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_3[3]                      CFG4        Y                  Out     0.408     6.677       -         
prdata_o_1_iv_3[3]                                                  Net         -                  -       0.483     -           1         
Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11_1[3]                   CFG4        D                  In      -         7.160       -         
Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11_1[3]                   CFG4        Y                  Out     0.384     7.544       -         
prdata_o_1_iv_11_1[3]                                               Net         -                  -       0.483     -           1         
Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11[3]                     CFG4        D                  In      -         8.027       -         
Stepper_Axis_0.apb3_if_st_0.prdata_o_1_iv_11[3]                     CFG4        Y                  Out     0.411     8.438       -         
prdata_o_1_iv_11[3]                                                 Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[3]     CFG4        D                  In      -         8.921       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[3]     CFG4        Y                  Out     0.408     9.330       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]                   Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_RDATA[3]     In      -         10.301      -         
===========================================================================================================================================
Total path delay (propagation time + setup) of 10.818 is 5.982(55.3%) logic and 4.837(44.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.000
    - Setup time:                            0.461
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.539

    - Propagation time:                      10.353
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.814

    Number of logic level(s):                6
    Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[1]
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[4]
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                  Pin                Pin               Arrival     No. of    
Name                                                                Type        Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_ADDR[1]      Out     3.058     3.058       -         
MC_System_0_AMBA_SLAVE_1_PADDR[1]                                   Net         -                  -       0.991     -           14        
Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o188_1         CFG2        B                  In      -         4.049       -         
Stepper_Axis_0.apb3_if_st_0.READ_DECODE_PROC\.prdata_o188_1         CFG2        Y                  Out     0.125     4.173       -         
g0_0_1                                                              Net         -                  -       0.914     -           32        
Bldc_Axis_0.apb3_if_0.g0_0                                          CFG4        D                  In      -         5.088       -         
Bldc_Axis_0.apb3_if_0.g0_0                                          CFG4        Y                  Out     0.408     5.496       -         
N_2883                                                              Net         -                  -       0.802     -           16        
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_1[4]                        CFG4        D                  In      -         6.298       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_1[4]                        CFG4        Y                  Out     0.408     6.707       -         
prdata_o_1_12_0_0_1[4]                                              Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_sx[4]                       CFG4        D                  In      -         7.190       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0_sx[4]                       CFG4        Y                  Out     0.408     7.598       -         
prdata_o_1_12_0_0_sx[4]                                             Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0[4]                          CFG4        D                  In      -         8.082       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_12_0_0[4]                          CFG4        Y                  Out     0.408     8.490       -         
MC_System_0_AMBA_SLAVE_0_PRDATA[4]                                  Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[4]     CFG4        D                  In      -         8.973       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[4]     CFG4        Y                  Out     0.408     9.382       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]                   Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST        MSS_010     F_HM0_RDATA[4]     In      -         10.353      -         
===========================================================================================================================================
Total path delay (propagation time + setup) of 10.814 is 5.686(52.6%) logic and 5.128(47.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                       Starting                                                                             Arrival          
Instance                                                                               Reference                                          Type     Pin     Net              Time        Slack
                                                                                       Clock                                                                                                 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[0]       MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_index[0]       0.094       2.786
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[1]       MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_index[1]       0.094       2.921
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[2]       MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_index[2]       0.094       3.360
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[3]       MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_index[3]       0.094       3.443
Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.s_pi_sel[1]                          MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_pi_sel[1]      0.094       3.583
Stepper_Axis_0.SPEED_ID_IQ_PI_0.PI_SCHEDULER_INST.s_pi_sel[0]                          MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_pi_sel[0]      0.076       3.671
Stepper_Axis_0.SEQ_CONTROLLER_0.s_state[6]                                             MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_state[6]       0.094       3.921
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot[17]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       m17_0_03_0       0.094       3.925
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot[14]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_xi_rot[14]     0.094       3.931
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot[16]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      Q       s_xi_rot[16]     0.094       3.959
=============================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                       Starting                                                                                                    Required          
Instance                                                                               Reference                                          Type     Pin     Net                                     Time         Slack
                                                                                       Clock                                                                                                                         
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[17]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_yi_rot_7[17]     9.778        2.786
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[16]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_yi_rot_7[16]     9.778        2.800
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[15]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_yi_rot_7[15]     9.778        2.814
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[14]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_yi_rot_7[14]     9.778        2.828
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[13]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_yi_rot_7[13]     9.778        2.842
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[12]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_yi_rot_7[12]     9.778        2.857
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot[17]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_xi_rot_7[17]     9.778        2.866
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[11]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_yi_rot_7[11]     9.778        2.871
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot[16]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_xi_rot_7[16]     9.778        2.881
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[10]     MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock     SLE      D       FSM_CORDIC_ROT_PROC\.s_yi_rot_7[10]     9.778        2.885
=====================================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.778

    - Propagation time:                      6.992
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.786

    Number of logic level(s):                23
    Starting point:                          Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[0] / Q
    Ending point:                            Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[17] / D
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL1_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                              Pin      Pin               Arrival     No. of    
Name                                                                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index[0]                                   SLE      Q        Out     0.094     0.094       -         
s_index[0]                                                                                                         Net      -        -       1.159     -           68        
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index_RNI5MMP[1]                           CFG2     A        In      -         1.253       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_index_RNI5MMP[1]                           CFG2     Y        Out     0.090     1.343       -         
N_84_i                                                                                                             Net      -        -       0.990     -           51        
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot_RNIEVM81[10]                        CFG4     D        In      -         2.333       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot_RNIEVM81[10]                        CFG4     Y        Out     0.411     2.743       -         
m8_0_1                                                                                                             Net      -        -       0.483     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot_RNIPANN1[11]                        CFG4     D        In      -         3.227       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_xi_rot_RNIPANN1[11]                        CFG4     Y        Out     0.411     3.637       -         
m8_0_03_0                                                                                                          Net      -        -       0.590     -           3         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.un1_s_yout_RNO_0[17]                         CFG4     C        In      -         4.227       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.un1_s_yout_RNO_0[17]                         CFG4     Y        Out     0.182     4.409       -         
m0_2_0                                                                                                             Net      -        -       0.483     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.un1_s_yout[17]                               CFG4     B        In      -         4.893       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.un1_s_yout[17]                               CFG4     Y        Out     0.143     5.036       -         
un1_s_yout_0[17]                                                                                                   Net      -        -       0.483     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_0_0      ARI1     C        In      -         5.519       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_0_0      ARI1     FCO      Out     0.211     5.730       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_0                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_1_0      ARI1     FCI      In      -         5.730       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_1_0      ARI1     FCO      Out     0.014     5.745       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_1                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_2_0      ARI1     FCI      In      -         5.745       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_2_0      ARI1     FCO      Out     0.014     5.759       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_2                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_3_0      ARI1     FCI      In      -         5.759       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_3_0      ARI1     FCO      Out     0.014     5.773       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_3                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_4_0      ARI1     FCI      In      -         5.773       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_4_0      ARI1     FCO      Out     0.014     5.787       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_4                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_5_0      ARI1     FCI      In      -         5.787       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_5_0      ARI1     FCO      Out     0.014     5.801       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_5                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_6_0      ARI1     FCI      In      -         5.801       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_6_0      ARI1     FCO      Out     0.014     5.816       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_6                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_7_0      ARI1     FCI      In      -         5.816       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_7_0      ARI1     FCO      Out     0.014     5.830       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_7                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_8_0      ARI1     FCI      In      -         5.830       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_8_0      ARI1     FCO      Out     0.014     5.844       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_8                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_9_0      ARI1     FCI      In      -         5.844       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_9_0      ARI1     FCO      Out     0.014     5.858       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_9                                                                              Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_10_0     ARI1     FCI      In      -         5.858       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_10_0     ARI1     FCO      Out     0.014     5.872       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_10                                                                             Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_11_0     ARI1     FCI      In      -         5.872       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_11_0     ARI1     FCO      Out     0.014     5.887       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_11                                                                             Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_12_0     ARI1     FCI      In      -         5.887       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_12_0     ARI1     FCO      Out     0.014     5.901       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_12                                                                             Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_13_0     ARI1     FCI      In      -         5.901       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_13_0     ARI1     FCO      Out     0.014     5.915       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_13                                                                             Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_14_0     ARI1     FCI      In      -         5.915       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_14_0     ARI1     FCO      Out     0.014     5.929       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_14                                                                             Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_15_0     ARI1     FCI      In      -         5.929       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_15_0     ARI1     FCO      Out     0.014     5.943       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_15                                                                             Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_16_0     ARI1     FCI      In      -         5.943       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_16_0     ARI1     FCO      Out     0.014     5.958       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7_cry_16                                                                             Net      -        -       0.000     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_s_17         ARI1     FCI      In      -         5.958       -         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.FSM_CORDIC_ROT_PROC\.s_yi_rot_7_s_17         ARI1     S        Out     0.063     6.021       -         
FSM_CORDIC_ROT_PROC\.s_yi_rot_7[17]                                                                                Net      -        -       0.971     -           1         
Stepper_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_yi_rot[17]                                 SLE      D        In      -         6.992       -         
=============================================================================================================================================================================
Total path delay (propagation time + setup) of 7.214 is 2.055(28.5%) logic and 5.160(71.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                                                           Arrival          
Instance                                                 Reference     Type               Pin        Net                                                    Time        Slack
                                                         Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                System        CCC                LOCK       LOCK                                                   0.000       1.017
MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
=============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                                                             Required          
Instance                                                         Reference     Type        Pin                 Net                                                    Time         Slack
                                                                 Clock                                                                                                                  
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        1.017
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        1.166
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]     9.604        1.276
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[17]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.675        1.296
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[29]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]     9.625        1.297
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[20]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[20]     9.677        1.298
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[30]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]     9.629        1.301
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[19]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[19]     9.688        1.309
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[24]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]     9.678        1.350
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[28]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]     9.688        1.360
========================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.383
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.617

    - Propagation time:                      8.600
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 1.017

    Number of logic level(s):                8
    Starting point:                          MC_System_0.MC_System_sb_0.CCC_0.CCC_INST / LOCK
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[0]
    The start point is clocked by            System [rising]
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                        Pin                Pin               Arrival     No. of    
Name                                                                      Type        Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                                 CCC         LOCK               Out     0.000     0.000       -         
LOCK                                                                      Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                         CLKINT      A                  In      -         0.971       -         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                         CLKINT      Y                  Out     0.548     1.520       -         
MC_System_0_FIC_0_LOCK                                                    Net         -                  -       0.993     -           4665      
Bldc_Axis_0.OLMNG_0.theta_o[0]                                            CFG4        D                  In      -         2.513       -         
Bldc_Axis_0.OLMNG_0.theta_o[0]                                            CFG4        Y                  Out     0.408     2.921       -         
theta_o[0]                                                                Net         -                  -       0.590     -           3         
Bldc_Axis_0.apb3_if_0.prdata_o_1_24_0_RNO_0[0]                            CFG4        B                  In      -         3.511       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_24_0_RNO_0[0]                            CFG4        Y                  Out     0.133     3.644       -         
prdata_o_1_15_i_m2_i_m2_1_1[0]                                            Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_24_0_0_RNO[0]                            CFG4        C                  In      -         4.128       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_24_0_0_RNO[0]                            CFG4        Y                  Out     0.200     4.327       -         
N_1312                                                                    Net         -                  -       0.483     -           1         
Bldc_Axis_0.apb3_if_0.prdata_o_1_24_0_0[0]                                CFG4        B                  In      -         4.811       -         
Bldc_Axis_0.apb3_if_0.prdata_o_1_24_0_0[0]                                CFG4        Y                  Out     0.143     4.954       -         
prdata_o_1_24_0_0[0]                                                      Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_RNO_3[0]     CFG4        D                  In      -         5.437       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_RNO_3[0]     CFG4        Y                  Out     0.408     5.845       -         
G_16_0_1                                                                  Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_RNO[0]       CFG4        D                  In      -         6.328       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_RNO[0]       CFG4        Y                  Out     0.408     6.737       -         
MC_System_0_AMBA_SLAVE_0_PRDATA[0]                                        Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[0]           CFG4        D                  In      -         7.220       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[0]           CFG4        Y                  Out     0.408     7.628       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]                         Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST              MSS_010     F_HM0_RDATA[0]     In      -         8.600       -         
=================================================================================================================================================
Total path delay (propagation time + setup) of 8.983 is 3.041(33.9%) logic and 5.942(66.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]


Finished final timing analysis (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:36s; Memory used current: 215MB peak: 279MB)


Finished timing report (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:36s; Memory used current: 215MB peak: 279MB)

---------------------------------------
Resource Usage Report for MC_System_top 

Mapping to part: m2s010fbga484-1
Cell usage:
CCC             1 use
CLKINT          3 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
CFG1           49 uses
CFG2           780 uses
CFG3           1716 uses
CFG4           1836 uses

Carry primitives used for arithmetic functions:
ARI1           2557 uses


Sequential Cells: 
SLE            4622 uses

DSP Blocks:   12
 MACC:         9 MultAdds
 MACC:         3 Mults

I/O ports: 36
I/O primitives: 35
BIBUF          8 uses
INBUF          5 uses
OUTBUF         21 uses
TRIBUFF        1 use


Global Clock Buffers: 3


Total LUTs:    6938

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
MACC     Interface Logic : SLEs = 432; LUTs = 432;

Total number of SLEs after P&R:  4622 + 0 + 0 + 432 = 5054;
Total number of LUTs after P&R:  6938 + 0 + 0 + 432 = 7370;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:36s; Memory used current: 66MB peak: 279MB)

Process took 0h:00m:37s realtime, 0h:00m:36s cputime
# Tue Oct 27 16:21:51 2015

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